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3c6e85 |
From f489fc7e6dc6a1092ab9a85fce340174c6a9c1fb Mon Sep 17 00:00:00 2001
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From: Himanshu Madhani <hmadhani@redhat.com>
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Date: Thu, 1 Aug 2019 15:54:57 -0400
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Subject: [PATCH 037/124] [scsi] scsi: qla2xxx: Update flash read/write routine
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Message-id: <20190801155618.12650-38-hmadhani@redhat.com>
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Patchwork-id: 267814
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O-Subject: [RHEL 7.8 e-stor PATCH 037/118] scsi: qla2xxx: Update flash read/write routine
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Bugzilla: 1729270
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RH-Acked-by: Jarod Wilson <jarod@redhat.com>
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RH-Acked-by: Tony Camuso <tcamuso@redhat.com>
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From: Joe Carnuccio <joe.carnuccio@cavium.com>
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Bugzilla 1729270
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This patch makes following changes to flash access routines:
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- update return type for read_optrom
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- use void instead of uint32_t * for buffer parameter in read
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and write optrom routines
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- fix flash/nvram addressing
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Signed-off-by: Joe Carnuccio <joe.carnuccio@cavium.com>
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3c6e85 |
Signed-off-by: Himanshu Madhani <hmadhani@marvell.com>
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Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
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(cherry picked from commit 3695310e37b4e571d40593cbe59188b0006a2274)
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Signed-off-by: Himanshu Madhani <hmadhani@redhat.com>
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Signed-off-by: Jan Stancek <jstancek@redhat.com>
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---
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drivers/scsi/qla2xxx/qla_attr.c | 65 +++---
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drivers/scsi/qla2xxx/qla_def.h | 8 +-
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drivers/scsi/qla2xxx/qla_gbl.h | 47 ++---
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drivers/scsi/qla2xxx/qla_init.c | 24 +--
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drivers/scsi/qla2xxx/qla_nx.c | 13 +-
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drivers/scsi/qla2xxx/qla_nx2.c | 8 +-
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drivers/scsi/qla2xxx/qla_sup.c | 443 +++++++++++++++++++---------------------
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7 files changed, 296 insertions(+), 312 deletions(-)
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diff --git a/drivers/scsi/qla2xxx/qla_attr.c b/drivers/scsi/qla2xxx/qla_attr.c
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index 4b3cd62a5c5b..02443efda34c 100644
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--- a/drivers/scsi/qla2xxx/qla_attr.c
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+++ b/drivers/scsi/qla2xxx/qla_attr.c
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@@ -223,9 +223,9 @@ qla2x00_sysfs_write_nvram(struct file *filp, struct kobject *kobj,
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}
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/* Write NVRAM. */
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- ha->isp_ops->write_nvram(vha, (uint8_t *)buf, ha->nvram_base, count);
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- ha->isp_ops->read_nvram(vha, (uint8_t *)ha->nvram, ha->nvram_base,
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- count);
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+ ha->isp_ops->write_nvram(vha, buf, ha->nvram_base, count);
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+ ha->isp_ops->read_nvram(vha, ha->nvram, ha->nvram_base,
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+ count);
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mutex_unlock(&ha->optrom_mutex);
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ql_dbg(ql_dbg_user, vha, 0x7060,
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@@ -511,22 +511,24 @@ qla2x00_sysfs_read_vpd(struct file *filp, struct kobject *kobj,
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if (!capable(CAP_SYS_ADMIN))
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return -EINVAL;
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- if (IS_NOCACHE_VPD_TYPE(ha)) {
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- faddr = ha->flt_region_vpd << 2;
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+ if (IS_NOCACHE_VPD_TYPE(ha))
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+ goto skip;
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- if ((IS_QLA27XX(ha) || IS_QLA28XX(ha)) &&
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- qla27xx_find_valid_image(vha) == QLA27XX_SECONDARY_IMAGE)
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- faddr = ha->flt_region_vpd_sec << 2;
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+ faddr = ha->flt_region_vpd << 2;
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- mutex_lock(&ha->optrom_mutex);
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- if (qla2x00_chip_is_down(vha)) {
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- mutex_unlock(&ha->optrom_mutex);
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- return -EAGAIN;
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- }
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- ha->isp_ops->read_optrom(vha, ha->vpd, faddr,
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- ha->vpd_size);
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+ if ((IS_QLA27XX(ha) || IS_QLA28XX(ha)) &&
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+ qla27xx_find_valid_image(vha) == QLA27XX_SECONDARY_IMAGE)
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+ faddr = ha->flt_region_vpd_sec << 2;
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+
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+ mutex_lock(&ha->optrom_mutex);
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+ if (qla2x00_chip_is_down(vha)) {
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mutex_unlock(&ha->optrom_mutex);
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+ return -EAGAIN;
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}
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+
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+ ha->isp_ops->read_optrom(vha, ha->vpd, faddr, ha->vpd_size);
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+ mutex_unlock(&ha->optrom_mutex);
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+skip:
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return memory_read_from_buffer(buf, count, &off, ha->vpd, ha->vpd_size);
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}
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@@ -563,8 +565,8 @@ qla2x00_sysfs_write_vpd(struct file *filp, struct kobject *kobj,
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}
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/* Write NVRAM. */
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- ha->isp_ops->write_nvram(vha, (uint8_t *)buf, ha->vpd_base, count);
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- ha->isp_ops->read_nvram(vha, (uint8_t *)ha->vpd, ha->vpd_base, count);
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+ ha->isp_ops->write_nvram(vha, buf, ha->vpd_base, count);
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+ ha->isp_ops->read_nvram(vha, ha->vpd, ha->vpd_base, count);
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/* Update flash version information for 4Gb & above. */
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if (!IS_FWI2_CAPABLE(ha)) {
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@@ -935,7 +937,7 @@ static struct bin_attribute sysfs_dcbx_tlv_attr = {
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static struct sysfs_entry {
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char *name;
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struct bin_attribute *attr;
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- int is4GBp_only;
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+ int type;
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} bin_file_entries[] = {
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{ "fw_dump", &sysfs_fw_dump_attr, },
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{ "nvram", &sysfs_nvram_attr, },
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@@ -958,11 +960,11 @@ qla2x00_alloc_sysfs_attr(scsi_qla_host_t *vha)
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int ret;
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for (iter = bin_file_entries; iter->name; iter++) {
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- if (iter->is4GBp_only && !IS_FWI2_CAPABLE(vha->hw))
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+ if (iter->type && !IS_FWI2_CAPABLE(vha->hw))
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continue;
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- if (iter->is4GBp_only == 2 && !IS_QLA25XX(vha->hw))
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+ if (iter->type == 2 && !IS_QLA25XX(vha->hw))
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continue;
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- if (iter->is4GBp_only == 3 && !(IS_CNA_CAPABLE(vha->hw)))
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+ if (iter->type == 3 && !(IS_CNA_CAPABLE(vha->hw)))
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continue;
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ret = sysfs_create_bin_file(&host->shost_gendev.kobj,
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@@ -986,14 +988,14 @@ qla2x00_free_sysfs_attr(scsi_qla_host_t *vha, bool stop_beacon)
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struct qla_hw_data *ha = vha->hw;
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for (iter = bin_file_entries; iter->name; iter++) {
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- if (iter->is4GBp_only && !IS_FWI2_CAPABLE(ha))
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+ if (iter->type && !IS_FWI2_CAPABLE(ha))
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continue;
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- if (iter->is4GBp_only == 2 && !IS_QLA25XX(ha))
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+ if (iter->type == 2 && !IS_QLA25XX(ha))
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continue;
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- if (iter->is4GBp_only == 3 && !(IS_CNA_CAPABLE(vha->hw)))
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+ if (iter->type == 3 && !(IS_CNA_CAPABLE(ha)))
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continue;
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- if (iter->is4GBp_only == 0x27 &&
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- (!IS_QLA27XX(vha->hw) || !IS_QLA28XX(ha)))
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+ if (iter->type == 0x27 &&
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+ (!IS_QLA27XX(ha) || !IS_QLA28XX(ha)))
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continue;
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sysfs_remove_bin_file(&host->shost_gendev.kobj,
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@@ -1361,19 +1363,20 @@ qla24xx_84xx_fw_version_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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int rval = QLA_SUCCESS;
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- uint16_t status[2] = {0, 0};
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+ uint16_t status[2] = { 0 };
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scsi_qla_host_t *vha = shost_priv(class_to_shost(dev));
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struct qla_hw_data *ha = vha->hw;
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if (!IS_QLA84XX(ha))
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return scnprintf(buf, PAGE_SIZE, "\n");
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- if (ha->cs84xx->op_fw_version == 0)
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+ if (!ha->cs84xx->op_fw_version) {
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rval = qla84xx_verify_chip(vha, status);
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- if ((rval == QLA_SUCCESS) && (status[0] == 0))
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- return scnprintf(buf, PAGE_SIZE, "%u\n",
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- (uint32_t)ha->cs84xx->op_fw_version);
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+ if (!rval && !status[0])
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+ return scnprintf(buf, PAGE_SIZE, "%u\n",
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+ (uint32_t)ha->cs84xx->op_fw_version);
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+ }
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return scnprintf(buf, PAGE_SIZE, "\n");
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}
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diff --git a/drivers/scsi/qla2xxx/qla_def.h b/drivers/scsi/qla2xxx/qla_def.h
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index ed5283e50b32..19bf9fb9b19c 100644
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--- a/drivers/scsi/qla2xxx/qla_def.h
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+++ b/drivers/scsi/qla2xxx/qla_def.h
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@@ -3171,9 +3171,9 @@ struct isp_operations {
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void *(*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t,
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uint32_t);
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- uint8_t *(*read_nvram) (struct scsi_qla_host *, uint8_t *,
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+ uint8_t *(*read_nvram)(struct scsi_qla_host *, void *,
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uint32_t, uint32_t);
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- int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t,
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+ int (*write_nvram)(struct scsi_qla_host *, void *, uint32_t,
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uint32_t);
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void (*fw_dump) (struct scsi_qla_host *, int);
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@@ -3182,9 +3182,9 @@ struct isp_operations {
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int (*beacon_off) (struct scsi_qla_host *);
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void (*beacon_blink) (struct scsi_qla_host *);
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- uint8_t * (*read_optrom) (struct scsi_qla_host *, uint8_t *,
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+ void *(*read_optrom)(struct scsi_qla_host *, void *,
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uint32_t, uint32_t);
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- int (*write_optrom) (struct scsi_qla_host *, uint8_t *, uint32_t,
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+ int (*write_optrom)(struct scsi_qla_host *, void *, uint32_t,
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3c6e85 |
uint32_t);
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3c6e85 |
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int (*get_flash_version) (struct scsi_qla_host *, void *);
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diff --git a/drivers/scsi/qla2xxx/qla_gbl.h b/drivers/scsi/qla2xxx/qla_gbl.h
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index fcb85c15c703..b0422ce94f20 100644
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--- a/drivers/scsi/qla2xxx/qla_gbl.h
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+++ b/drivers/scsi/qla2xxx/qla_gbl.h
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@@ -542,19 +542,20 @@ fc_port_t *qla2x00_find_fcport_by_nportid(scsi_qla_host_t *, port_id_t *, u8);
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3c6e85 |
*/
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3c6e85 |
extern void qla2x00_release_nvram_protection(scsi_qla_host_t *);
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3c6e85 |
extern uint32_t *qla24xx_read_flash_data(scsi_qla_host_t *, uint32_t *,
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- uint32_t, uint32_t);
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3c6e85 |
-extern uint8_t *qla2x00_read_nvram_data(scsi_qla_host_t *, uint8_t *, uint32_t,
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3c6e85 |
- uint32_t);
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3c6e85 |
-extern uint8_t *qla24xx_read_nvram_data(scsi_qla_host_t *, uint8_t *, uint32_t,
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3c6e85 |
- uint32_t);
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3c6e85 |
-extern int qla2x00_write_nvram_data(scsi_qla_host_t *, uint8_t *, uint32_t,
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3c6e85 |
- uint32_t);
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3c6e85 |
-extern int qla24xx_write_nvram_data(scsi_qla_host_t *, uint8_t *, uint32_t,
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3c6e85 |
- uint32_t);
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3c6e85 |
-extern uint8_t *qla25xx_read_nvram_data(scsi_qla_host_t *, uint8_t *, uint32_t,
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3c6e85 |
- uint32_t);
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3c6e85 |
-extern int qla25xx_write_nvram_data(scsi_qla_host_t *, uint8_t *, uint32_t,
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3c6e85 |
- uint32_t);
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3c6e85 |
+ uint32_t, uint32_t);
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3c6e85 |
+extern uint8_t *qla2x00_read_nvram_data(scsi_qla_host_t *, void *, uint32_t,
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3c6e85 |
+ uint32_t);
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3c6e85 |
+extern uint8_t *qla24xx_read_nvram_data(scsi_qla_host_t *, void *, uint32_t,
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3c6e85 |
+ uint32_t);
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3c6e85 |
+extern int qla2x00_write_nvram_data(scsi_qla_host_t *, void *, uint32_t,
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3c6e85 |
+ uint32_t);
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3c6e85 |
+extern int qla24xx_write_nvram_data(scsi_qla_host_t *, void *, uint32_t,
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3c6e85 |
+ uint32_t);
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3c6e85 |
+extern uint8_t *qla25xx_read_nvram_data(scsi_qla_host_t *, void *, uint32_t,
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3c6e85 |
+ uint32_t);
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3c6e85 |
+extern int qla25xx_write_nvram_data(scsi_qla_host_t *, void *, uint32_t,
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3c6e85 |
+ uint32_t);
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3c6e85 |
+
|
|
|
3c6e85 |
extern int qla2x00_is_a_vp_did(scsi_qla_host_t *, uint32_t);
|
|
|
3c6e85 |
bool qla2x00_check_reg32_for_disconnect(scsi_qla_host_t *, uint32_t);
|
|
|
3c6e85 |
bool qla2x00_check_reg16_for_disconnect(scsi_qla_host_t *, uint16_t);
|
|
|
3c6e85 |
@@ -574,18 +575,18 @@ extern int qla83xx_restart_nic_firmware(scsi_qla_host_t *);
|
|
|
3c6e85 |
extern int qla83xx_access_control(scsi_qla_host_t *, uint16_t, uint32_t,
|
|
|
3c6e85 |
uint32_t, uint16_t *);
|
|
|
3c6e85 |
|
|
|
3c6e85 |
-extern uint8_t *qla2x00_read_optrom_data(struct scsi_qla_host *, uint8_t *,
|
|
|
3c6e85 |
+extern void *qla2x00_read_optrom_data(struct scsi_qla_host *, void *,
|
|
|
3c6e85 |
uint32_t, uint32_t);
|
|
|
3c6e85 |
-extern int qla2x00_write_optrom_data(struct scsi_qla_host *, uint8_t *,
|
|
|
3c6e85 |
+extern int qla2x00_write_optrom_data(struct scsi_qla_host *, void *,
|
|
|
3c6e85 |
uint32_t, uint32_t);
|
|
|
3c6e85 |
-extern uint8_t *qla24xx_read_optrom_data(struct scsi_qla_host *, uint8_t *,
|
|
|
3c6e85 |
+extern void *qla24xx_read_optrom_data(struct scsi_qla_host *, void *,
|
|
|
3c6e85 |
uint32_t, uint32_t);
|
|
|
3c6e85 |
-extern int qla24xx_write_optrom_data(struct scsi_qla_host *, uint8_t *,
|
|
|
3c6e85 |
+extern int qla24xx_write_optrom_data(struct scsi_qla_host *, void *,
|
|
|
3c6e85 |
uint32_t, uint32_t);
|
|
|
3c6e85 |
-extern uint8_t *qla25xx_read_optrom_data(struct scsi_qla_host *, uint8_t *,
|
|
|
3c6e85 |
+extern void *qla25xx_read_optrom_data(struct scsi_qla_host *, void *,
|
|
|
3c6e85 |
uint32_t, uint32_t);
|
|
|
3c6e85 |
-extern uint8_t *qla8044_read_optrom_data(struct scsi_qla_host *,
|
|
|
3c6e85 |
- uint8_t *, uint32_t, uint32_t);
|
|
|
3c6e85 |
+extern void *qla8044_read_optrom_data(struct scsi_qla_host *,
|
|
|
3c6e85 |
+ void *, uint32_t, uint32_t);
|
|
|
3c6e85 |
extern void qla8044_watchdog(struct scsi_qla_host *vha);
|
|
|
3c6e85 |
|
|
|
3c6e85 |
extern int qla2x00_get_flash_version(scsi_qla_host_t *, void *);
|
|
|
3c6e85 |
@@ -765,9 +766,9 @@ extern int qla82xx_start_firmware(scsi_qla_host_t *);
|
|
|
3c6e85 |
|
|
|
3c6e85 |
/* Firmware and flash related functions */
|
|
|
3c6e85 |
extern int qla82xx_load_risc(scsi_qla_host_t *, uint32_t *);
|
|
|
3c6e85 |
-extern uint8_t *qla82xx_read_optrom_data(struct scsi_qla_host *, uint8_t *,
|
|
|
3c6e85 |
+extern void *qla82xx_read_optrom_data(struct scsi_qla_host *, void *,
|
|
|
3c6e85 |
uint32_t, uint32_t);
|
|
|
3c6e85 |
-extern int qla82xx_write_optrom_data(struct scsi_qla_host *, uint8_t *,
|
|
|
3c6e85 |
+extern int qla82xx_write_optrom_data(struct scsi_qla_host *, void *,
|
|
|
3c6e85 |
uint32_t, uint32_t);
|
|
|
3c6e85 |
|
|
|
3c6e85 |
/* Mailbox related functions */
|
|
|
3c6e85 |
@@ -863,7 +864,7 @@ extern void qla8044_clear_drv_active(struct qla_hw_data *);
|
|
|
3c6e85 |
void qla8044_get_minidump(struct scsi_qla_host *vha);
|
|
|
3c6e85 |
int qla8044_collect_md_data(struct scsi_qla_host *vha);
|
|
|
3c6e85 |
extern int qla8044_md_get_template(scsi_qla_host_t *);
|
|
|
3c6e85 |
-extern int qla8044_write_optrom_data(struct scsi_qla_host *, uint8_t *,
|
|
|
3c6e85 |
+extern int qla8044_write_optrom_data(struct scsi_qla_host *, void *,
|
|
|
3c6e85 |
uint32_t, uint32_t);
|
|
|
3c6e85 |
extern irqreturn_t qla8044_intr_handler(int, void *);
|
|
|
3c6e85 |
extern void qla82xx_mbx_completion(scsi_qla_host_t *, uint16_t);
|
|
|
3c6e85 |
diff --git a/drivers/scsi/qla2xxx/qla_init.c b/drivers/scsi/qla2xxx/qla_init.c
|
|
|
3c6e85 |
index 9fa3c3322809..27482aa84adf 100644
|
|
|
3c6e85 |
--- a/drivers/scsi/qla2xxx/qla_init.c
|
|
|
3c6e85 |
+++ b/drivers/scsi/qla2xxx/qla_init.c
|
|
|
3c6e85 |
@@ -4433,9 +4433,8 @@ qla2x00_nvram_config(scsi_qla_host_t *vha)
|
|
|
3c6e85 |
nv->nvram_version < 1) {
|
|
|
3c6e85 |
/* Reset NVRAM data. */
|
|
|
3c6e85 |
ql_log(ql_log_warn, vha, 0x0064,
|
|
|
3c6e85 |
- "Inconsistent NVRAM "
|
|
|
3c6e85 |
- "detected: checksum=0x%x id=%c version=0x%x.\n",
|
|
|
3c6e85 |
- chksum, nv->id[0], nv->nvram_version);
|
|
|
3c6e85 |
+ "Inconsistent NVRAM detected: checksum=%#x id=%.4s version=%#x.\n",
|
|
|
3c6e85 |
+ chksum, nv->id, nv->nvram_version);
|
|
|
3c6e85 |
ql_log(ql_log_warn, vha, 0x0065,
|
|
|
3c6e85 |
"Falling back to "
|
|
|
3c6e85 |
"functioning (yet invalid -- WWPN) defaults.\n");
|
|
|
3c6e85 |
@@ -7021,13 +7020,12 @@ qla24xx_nvram_config(scsi_qla_host_t *vha)
|
|
|
3c6e85 |
|
|
|
3c6e85 |
/* Get VPD data into cache */
|
|
|
3c6e85 |
ha->vpd = ha->nvram + VPD_OFFSET;
|
|
|
3c6e85 |
- ha->isp_ops->read_nvram(vha, (uint8_t *)ha->vpd,
|
|
|
3c6e85 |
+ ha->isp_ops->read_nvram(vha, ha->vpd,
|
|
|
3c6e85 |
ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4);
|
|
|
3c6e85 |
|
|
|
3c6e85 |
/* Get NVRAM data into cache and calculate checksum. */
|
|
|
3c6e85 |
dptr = (uint32_t *)nv;
|
|
|
3c6e85 |
- ha->isp_ops->read_nvram(vha, (uint8_t *)dptr, ha->nvram_base,
|
|
|
3c6e85 |
- ha->nvram_size);
|
|
|
3c6e85 |
+ ha->isp_ops->read_nvram(vha, dptr, ha->nvram_base, ha->nvram_size);
|
|
|
3c6e85 |
for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++, dptr++)
|
|
|
3c6e85 |
chksum += le32_to_cpu(*dptr);
|
|
|
3c6e85 |
|
|
|
3c6e85 |
@@ -7041,9 +7039,9 @@ qla24xx_nvram_config(scsi_qla_host_t *vha)
|
|
|
3c6e85 |
le16_to_cpu(nv->nvram_version) < ICB_VERSION) {
|
|
|
3c6e85 |
/* Reset NVRAM data. */
|
|
|
3c6e85 |
ql_log(ql_log_warn, vha, 0x006b,
|
|
|
3c6e85 |
- "Inconsistent NVRAM detected: checksum=0x%x id=%c "
|
|
|
3c6e85 |
- "version=0x%x.\n", chksum, nv->id[0], nv->nvram_version);
|
|
|
3c6e85 |
- ql_dump_buffer(ql_dbg_init, vha, 0x006b, nv, 32);
|
|
|
3c6e85 |
+ "Inconsistent NVRAM checksum=%#x id=%.4s version=%#x.\n",
|
|
|
3c6e85 |
+ chksum, nv->id, nv->nvram_version);
|
|
|
3c6e85 |
+ ql_dump_buffer(ql_dbg_init, vha, 0x006b, nv, sizeof(*nv));
|
|
|
3c6e85 |
ql_log(ql_log_warn, vha, 0x006c,
|
|
|
3c6e85 |
"Falling back to functioning (yet invalid -- WWPN) "
|
|
|
3c6e85 |
"defaults.\n");
|
|
|
3c6e85 |
@@ -7432,6 +7430,7 @@ qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr,
|
|
|
3c6e85 |
fwdt->template = NULL;
|
|
|
3c6e85 |
fwdt->length = 0;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
+ dcode = (void *)req->ring;
|
|
|
3c6e85 |
qla24xx_read_flash_data(vha, dcode, faddr, 7);
|
|
|
3c6e85 |
risc_size = be32_to_cpu(dcode[2]);
|
|
|
3c6e85 |
ql_dbg(ql_dbg_init, vha, 0x0161,
|
|
|
3c6e85 |
@@ -8034,10 +8033,9 @@ qla81xx_nvram_config(scsi_qla_host_t *vha)
|
|
|
3c6e85 |
le16_to_cpu(nv->nvram_version) < ICB_VERSION) {
|
|
|
3c6e85 |
/* Reset NVRAM data. */
|
|
|
3c6e85 |
ql_log(ql_log_info, vha, 0x0073,
|
|
|
3c6e85 |
- "Inconsistent NVRAM detected: checksum=0x%x id=%c "
|
|
|
3c6e85 |
- "version=0x%x.\n", chksum, nv->id[0],
|
|
|
3c6e85 |
- le16_to_cpu(nv->nvram_version));
|
|
|
3c6e85 |
- ql_dump_buffer(ql_dbg_init, vha, 0x0073, nv, 32);
|
|
|
3c6e85 |
+ "Inconsistent NVRAM checksum=%#x id=%.4s version=%#x.\n",
|
|
|
3c6e85 |
+ chksum, nv->id, le16_to_cpu(nv->nvram_version));
|
|
|
3c6e85 |
+ ql_dump_buffer(ql_dbg_init, vha, 0x0073, nv, sizeof(*nv));
|
|
|
3c6e85 |
ql_log(ql_log_info, vha, 0x0074,
|
|
|
3c6e85 |
"Falling back to functioning (yet invalid -- WWPN) "
|
|
|
3c6e85 |
"defaults.\n");
|
|
|
3c6e85 |
diff --git a/drivers/scsi/qla2xxx/qla_nx.c b/drivers/scsi/qla2xxx/qla_nx.c
|
|
|
3c6e85 |
index 868bfb56d972..ff624c06824e 100644
|
|
|
3c6e85 |
--- a/drivers/scsi/qla2xxx/qla_nx.c
|
|
|
3c6e85 |
+++ b/drivers/scsi/qla2xxx/qla_nx.c
|
|
|
3c6e85 |
@@ -2653,8 +2653,8 @@ done:
|
|
|
3c6e85 |
/*
|
|
|
3c6e85 |
* Address and length are byte address
|
|
|
3c6e85 |
*/
|
|
|
3c6e85 |
-uint8_t *
|
|
|
3c6e85 |
-qla82xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
|
|
|
3c6e85 |
+void *
|
|
|
3c6e85 |
+qla82xx_read_optrom_data(struct scsi_qla_host *vha, void *buf,
|
|
|
3c6e85 |
uint32_t offset, uint32_t length)
|
|
|
3c6e85 |
{
|
|
|
3c6e85 |
scsi_block_requests(vha->host);
|
|
|
3c6e85 |
@@ -2762,15 +2762,14 @@ write_done:
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
|
|
|
3c6e85 |
int
|
|
|
3c6e85 |
-qla82xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
|
|
|
3c6e85 |
+qla82xx_write_optrom_data(struct scsi_qla_host *vha, void *buf,
|
|
|
3c6e85 |
uint32_t offset, uint32_t length)
|
|
|
3c6e85 |
{
|
|
|
3c6e85 |
int rval;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
/* Suspend HBA. */
|
|
|
3c6e85 |
scsi_block_requests(vha->host);
|
|
|
3c6e85 |
- rval = qla82xx_write_flash_data(vha, (uint32_t *)buf, offset,
|
|
|
3c6e85 |
- length >> 2);
|
|
|
3c6e85 |
+ rval = qla82xx_write_flash_data(vha, buf, offset, length >> 2);
|
|
|
3c6e85 |
scsi_unblock_requests(vha->host);
|
|
|
3c6e85 |
|
|
|
3c6e85 |
/* Convert return ISP82xx to generic */
|
|
|
3c6e85 |
@@ -3694,8 +3693,8 @@ qla82xx_chip_reset_cleanup(scsi_qla_host_t *vha)
|
|
|
3c6e85 |
spin_unlock_irqrestore(&ha->hardware_lock, flags);
|
|
|
3c6e85 |
|
|
|
3c6e85 |
/* Wait for pending cmds (physical and virtual) to complete */
|
|
|
3c6e85 |
- if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0,
|
|
|
3c6e85 |
- WAIT_HOST)) {
|
|
|
3c6e85 |
+ if (!qla2x00_eh_wait_for_pending_commands(vha, 0, 0,
|
|
|
3c6e85 |
+ WAIT_HOST) == QLA_SUCCESS) {
|
|
|
3c6e85 |
ql_dbg(ql_dbg_init, vha, 0x00b3,
|
|
|
3c6e85 |
"Done wait for "
|
|
|
3c6e85 |
"pending commands.\n");
|
|
|
3c6e85 |
diff --git a/drivers/scsi/qla2xxx/qla_nx2.c b/drivers/scsi/qla2xxx/qla_nx2.c
|
|
|
3c6e85 |
index 56f72b44a965..412d589fe550 100644
|
|
|
3c6e85 |
--- a/drivers/scsi/qla2xxx/qla_nx2.c
|
|
|
3c6e85 |
+++ b/drivers/scsi/qla2xxx/qla_nx2.c
|
|
|
3c6e85 |
@@ -542,12 +542,12 @@ exit_lock_error:
|
|
|
3c6e85 |
/*
|
|
|
3c6e85 |
* Address and length are byte address
|
|
|
3c6e85 |
*/
|
|
|
3c6e85 |
-uint8_t *
|
|
|
3c6e85 |
-qla8044_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
|
|
|
3c6e85 |
+void *
|
|
|
3c6e85 |
+qla8044_read_optrom_data(struct scsi_qla_host *vha, void *buf,
|
|
|
3c6e85 |
uint32_t offset, uint32_t length)
|
|
|
3c6e85 |
{
|
|
|
3c6e85 |
scsi_block_requests(vha->host);
|
|
|
3c6e85 |
- if (qla8044_read_flash_data(vha, (uint8_t *)buf, offset, length / 4)
|
|
|
3c6e85 |
+ if (qla8044_read_flash_data(vha, buf, offset, length / 4)
|
|
|
3c6e85 |
!= QLA_SUCCESS) {
|
|
|
3c6e85 |
ql_log(ql_log_warn, vha, 0xb08d,
|
|
|
3c6e85 |
"%s: Failed to read from flash\n",
|
|
|
3c6e85 |
@@ -3780,7 +3780,7 @@ qla8044_write_flash_dword_mode(scsi_qla_host_t *vha, uint32_t *dwptr,
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
|
|
|
3c6e85 |
int
|
|
|
3c6e85 |
-qla8044_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
|
|
|
3c6e85 |
+qla8044_write_optrom_data(struct scsi_qla_host *vha, void *buf,
|
|
|
3c6e85 |
uint32_t offset, uint32_t length)
|
|
|
3c6e85 |
{
|
|
|
3c6e85 |
int rval = QLA_FUNCTION_FAILED, i, burst_iter_count;
|
|
|
3c6e85 |
diff --git a/drivers/scsi/qla2xxx/qla_sup.c b/drivers/scsi/qla2xxx/qla_sup.c
|
|
|
3c6e85 |
index 5c0c62f1f010..8a275cf2d4fc 100644
|
|
|
3c6e85 |
--- a/drivers/scsi/qla2xxx/qla_sup.c
|
|
|
3c6e85 |
+++ b/drivers/scsi/qla2xxx/qla_sup.c
|
|
|
3c6e85 |
@@ -429,66 +429,64 @@ qla2x00_set_nvram_protection(struct qla_hw_data *ha, int stat)
|
|
|
3c6e85 |
static inline uint32_t
|
|
|
3c6e85 |
flash_conf_addr(struct qla_hw_data *ha, uint32_t faddr)
|
|
|
3c6e85 |
{
|
|
|
3c6e85 |
- return ha->flash_conf_off | faddr;
|
|
|
3c6e85 |
+ return ha->flash_conf_off + faddr;
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
|
|
|
3c6e85 |
static inline uint32_t
|
|
|
3c6e85 |
flash_data_addr(struct qla_hw_data *ha, uint32_t faddr)
|
|
|
3c6e85 |
{
|
|
|
3c6e85 |
- return ha->flash_data_off | faddr;
|
|
|
3c6e85 |
+ return ha->flash_data_off + faddr;
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
|
|
|
3c6e85 |
static inline uint32_t
|
|
|
3c6e85 |
nvram_conf_addr(struct qla_hw_data *ha, uint32_t naddr)
|
|
|
3c6e85 |
{
|
|
|
3c6e85 |
- return ha->nvram_conf_off | naddr;
|
|
|
3c6e85 |
+ return ha->nvram_conf_off + naddr;
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
|
|
|
3c6e85 |
static inline uint32_t
|
|
|
3c6e85 |
nvram_data_addr(struct qla_hw_data *ha, uint32_t naddr)
|
|
|
3c6e85 |
{
|
|
|
3c6e85 |
- return ha->nvram_data_off | naddr;
|
|
|
3c6e85 |
+ return ha->nvram_data_off + naddr;
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
|
|
|
3c6e85 |
-static uint32_t
|
|
|
3c6e85 |
-qla24xx_read_flash_dword(struct qla_hw_data *ha, uint32_t addr)
|
|
|
3c6e85 |
+static int
|
|
|
3c6e85 |
+qla24xx_read_flash_dword(struct qla_hw_data *ha, uint32_t addr, uint32_t *data)
|
|
|
3c6e85 |
{
|
|
|
3c6e85 |
- int rval;
|
|
|
3c6e85 |
- uint32_t cnt, data;
|
|
|
3c6e85 |
struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
|
|
|
3c6e85 |
+ ulong cnt = 30000;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
WRT_REG_DWORD(®->flash_addr, addr & ~FARX_DATA_FLAG);
|
|
|
3c6e85 |
- /* Wait for READ cycle to complete. */
|
|
|
3c6e85 |
- rval = QLA_SUCCESS;
|
|
|
3c6e85 |
- for (cnt = 3000;
|
|
|
3c6e85 |
- (RD_REG_DWORD(®->flash_addr) & FARX_DATA_FLAG) == 0 &&
|
|
|
3c6e85 |
- rval == QLA_SUCCESS; cnt--) {
|
|
|
3c6e85 |
- if (cnt)
|
|
|
3c6e85 |
- udelay(10);
|
|
|
3c6e85 |
- else
|
|
|
3c6e85 |
- rval = QLA_FUNCTION_TIMEOUT;
|
|
|
3c6e85 |
+
|
|
|
3c6e85 |
+ while (cnt--) {
|
|
|
3c6e85 |
+ if (RD_REG_DWORD(®->flash_addr) & FARX_DATA_FLAG) {
|
|
|
3c6e85 |
+ *data = RD_REG_DWORD(®->flash_data);
|
|
|
3c6e85 |
+ return QLA_SUCCESS;
|
|
|
3c6e85 |
+ }
|
|
|
3c6e85 |
+ udelay(10);
|
|
|
3c6e85 |
cond_resched();
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
|
|
|
3c6e85 |
- /* TODO: What happens if we time out? */
|
|
|
3c6e85 |
- data = 0xDEADDEAD;
|
|
|
3c6e85 |
- if (rval == QLA_SUCCESS)
|
|
|
3c6e85 |
- data = RD_REG_DWORD(®->flash_data);
|
|
|
3c6e85 |
-
|
|
|
3c6e85 |
- return data;
|
|
|
3c6e85 |
+ ql_log(ql_log_warn, pci_get_drvdata(ha->pdev), 0x7090,
|
|
|
3c6e85 |
+ "Flash read dword at %x timeout.\n", addr);
|
|
|
3c6e85 |
+ *data = 0xDEADDEAD;
|
|
|
3c6e85 |
+ return QLA_FUNCTION_TIMEOUT;
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
|
|
|
3c6e85 |
uint32_t *
|
|
|
3c6e85 |
qla24xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
|
|
|
3c6e85 |
uint32_t dwords)
|
|
|
3c6e85 |
{
|
|
|
3c6e85 |
- uint32_t i;
|
|
|
3c6e85 |
+ ulong i;
|
|
|
3c6e85 |
struct qla_hw_data *ha = vha->hw;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
/* Dword reads to flash. */
|
|
|
3c6e85 |
- for (i = 0; i < dwords; i++, faddr++)
|
|
|
3c6e85 |
- dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
|
|
|
3c6e85 |
- flash_data_addr(ha, faddr)));
|
|
|
3c6e85 |
+ faddr = flash_data_addr(ha, faddr);
|
|
|
3c6e85 |
+ for (i = 0; i < dwords; i++, faddr++, dwptr++) {
|
|
|
3c6e85 |
+ if (qla24xx_read_flash_dword(ha, faddr, dwptr))
|
|
|
3c6e85 |
+ break;
|
|
|
3c6e85 |
+ cpu_to_le32s(dwptr);
|
|
|
3c6e85 |
+ }
|
|
|
3c6e85 |
|
|
|
3c6e85 |
return dwptr;
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
@@ -496,35 +494,37 @@ qla24xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
|
|
|
3c6e85 |
static int
|
|
|
3c6e85 |
qla24xx_write_flash_dword(struct qla_hw_data *ha, uint32_t addr, uint32_t data)
|
|
|
3c6e85 |
{
|
|
|
3c6e85 |
- int rval;
|
|
|
3c6e85 |
- uint32_t cnt;
|
|
|
3c6e85 |
struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
|
|
|
3c6e85 |
+ ulong cnt = 500000;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
WRT_REG_DWORD(®->flash_data, data);
|
|
|
3c6e85 |
- RD_REG_DWORD(®->flash_data); /* PCI Posting. */
|
|
|
3c6e85 |
WRT_REG_DWORD(®->flash_addr, addr | FARX_DATA_FLAG);
|
|
|
3c6e85 |
- /* Wait for Write cycle to complete. */
|
|
|
3c6e85 |
- rval = QLA_SUCCESS;
|
|
|
3c6e85 |
- for (cnt = 500000; (RD_REG_DWORD(®->flash_addr) & FARX_DATA_FLAG) &&
|
|
|
3c6e85 |
- rval == QLA_SUCCESS; cnt--) {
|
|
|
3c6e85 |
- if (cnt)
|
|
|
3c6e85 |
- udelay(10);
|
|
|
3c6e85 |
- else
|
|
|
3c6e85 |
- rval = QLA_FUNCTION_TIMEOUT;
|
|
|
3c6e85 |
+
|
|
|
3c6e85 |
+ while (cnt--) {
|
|
|
3c6e85 |
+ if (!(RD_REG_DWORD(®->flash_addr) & FARX_DATA_FLAG))
|
|
|
3c6e85 |
+ return QLA_SUCCESS;
|
|
|
3c6e85 |
+ udelay(10);
|
|
|
3c6e85 |
cond_resched();
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
- return rval;
|
|
|
3c6e85 |
+
|
|
|
3c6e85 |
+ ql_log(ql_log_warn, pci_get_drvdata(ha->pdev), 0x7090,
|
|
|
3c6e85 |
+ "Flash write dword at %x timeout.\n", addr);
|
|
|
3c6e85 |
+ return QLA_FUNCTION_TIMEOUT;
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
|
|
|
3c6e85 |
static void
|
|
|
3c6e85 |
qla24xx_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
|
|
|
3c6e85 |
uint8_t *flash_id)
|
|
|
3c6e85 |
{
|
|
|
3c6e85 |
- uint32_t ids;
|
|
|
3c6e85 |
+ uint32_t faddr, ids = 0;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
- ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x03ab));
|
|
|
3c6e85 |
- *man_id = LSB(ids);
|
|
|
3c6e85 |
- *flash_id = MSB(ids);
|
|
|
3c6e85 |
+ *man_id = *flash_id = 0;
|
|
|
3c6e85 |
+
|
|
|
3c6e85 |
+ faddr = flash_conf_addr(ha, 0x03ab);
|
|
|
3c6e85 |
+ if (!qla24xx_read_flash_dword(ha, faddr, &ids)) {
|
|
|
3c6e85 |
+ *man_id = LSB(ids);
|
|
|
3c6e85 |
+ *flash_id = MSB(ids);
|
|
|
3c6e85 |
+ }
|
|
|
3c6e85 |
|
|
|
3c6e85 |
/* Check if man_id and flash_id are valid. */
|
|
|
3c6e85 |
if (ids != 0xDEADDEAD && (*man_id == 0 || *flash_id == 0)) {
|
|
|
3c6e85 |
@@ -534,9 +534,11 @@ qla24xx_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
|
|
|
3c6e85 |
* Example: ATMEL 0x00 01 45 1F
|
|
|
3c6e85 |
* Extract MFG and Dev ID from last two bytes.
|
|
|
3c6e85 |
*/
|
|
|
3c6e85 |
- ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x009f));
|
|
|
3c6e85 |
- *man_id = LSB(ids);
|
|
|
3c6e85 |
- *flash_id = MSB(ids);
|
|
|
3c6e85 |
+ faddr = flash_conf_addr(ha, 0x009f);
|
|
|
3c6e85 |
+ if (!qla24xx_read_flash_dword(ha, faddr, &ids)) {
|
|
|
3c6e85 |
+ *man_id = LSB(ids);
|
|
|
3c6e85 |
+ *flash_id = MSB(ids);
|
|
|
3c6e85 |
+ }
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
|
|
|
3c6e85 |
@@ -545,12 +547,12 @@ qla2xxx_find_flt_start(scsi_qla_host_t *vha, uint32_t *start)
|
|
|
3c6e85 |
{
|
|
|
3c6e85 |
const char *loc, *locations[] = { "DEF", "PCI" };
|
|
|
3c6e85 |
uint32_t pcihdr, pcids;
|
|
|
3c6e85 |
- uint32_t *dcode;
|
|
|
3c6e85 |
- uint8_t *buf, *bcode, last_image;
|
|
|
3c6e85 |
uint16_t cnt, chksum, *wptr;
|
|
|
3c6e85 |
- struct qla_flt_location *fltl;
|
|
|
3c6e85 |
struct qla_hw_data *ha = vha->hw;
|
|
|
3c6e85 |
struct req_que *req = ha->req_q_map[0];
|
|
|
3c6e85 |
+ struct qla_flt_location *fltl = (void *)req->ring;
|
|
|
3c6e85 |
+ uint32_t *dcode = (void *)req->ring;
|
|
|
3c6e85 |
+ uint8_t *buf = (void *)req->ring, *bcode, last_image;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
/*
|
|
|
3c6e85 |
* FLT-location structure resides after the last PCI region.
|
|
|
3c6e85 |
@@ -575,11 +577,9 @@ qla2xxx_find_flt_start(scsi_qla_host_t *vha, uint32_t *start)
|
|
|
3c6e85 |
*start = FA_FLASH_LAYOUT_ADDR_28;
|
|
|
3c6e85 |
goto end;
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
+
|
|
|
3c6e85 |
/* Begin with first PCI expansion ROM header. */
|
|
|
3c6e85 |
- buf = (uint8_t *)req->ring;
|
|
|
3c6e85 |
- dcode = (uint32_t *)req->ring;
|
|
|
3c6e85 |
pcihdr = 0;
|
|
|
3c6e85 |
- last_image = 1;
|
|
|
3c6e85 |
do {
|
|
|
3c6e85 |
/* Verify PCI expansion ROM header. */
|
|
|
3c6e85 |
qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
|
|
|
3c6e85 |
@@ -604,15 +604,12 @@ qla2xxx_find_flt_start(scsi_qla_host_t *vha, uint32_t *start)
|
|
|
3c6e85 |
} while (!last_image);
|
|
|
3c6e85 |
|
|
|
3c6e85 |
/* Now verify FLT-location structure. */
|
|
|
3c6e85 |
- fltl = (struct qla_flt_location *)req->ring;
|
|
|
3c6e85 |
- qla24xx_read_flash_data(vha, dcode, pcihdr >> 2,
|
|
|
3c6e85 |
- sizeof(struct qla_flt_location) >> 2);
|
|
|
3c6e85 |
- if (fltl->sig[0] != 'Q' || fltl->sig[1] != 'F' ||
|
|
|
3c6e85 |
- fltl->sig[2] != 'L' || fltl->sig[3] != 'T')
|
|
|
3c6e85 |
+ qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, sizeof(*fltl) >> 2);
|
|
|
3c6e85 |
+ if (memcmp(fltl->sig, "QFLT", 4))
|
|
|
3c6e85 |
goto end;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
- wptr = (uint16_t *)req->ring;
|
|
|
3c6e85 |
- cnt = sizeof(struct qla_flt_location) >> 1;
|
|
|
3c6e85 |
+ wptr = (void *)req->ring;
|
|
|
3c6e85 |
+ cnt = sizeof(*fltl) / sizeof(*wptr);
|
|
|
3c6e85 |
for (chksum = 0; cnt--; wptr++)
|
|
|
3c6e85 |
chksum += le16_to_cpu(*wptr);
|
|
|
3c6e85 |
if (chksum) {
|
|
|
3c6e85 |
@@ -915,22 +912,19 @@ qla2xxx_get_fdt_info(scsi_qla_host_t *vha)
|
|
|
3c6e85 |
#define FLASH_BLK_SIZE_32K 0x8000
|
|
|
3c6e85 |
#define FLASH_BLK_SIZE_64K 0x10000
|
|
|
3c6e85 |
const char *loc, *locations[] = { "MID", "FDT" };
|
|
|
3c6e85 |
+ struct qla_hw_data *ha = vha->hw;
|
|
|
3c6e85 |
+ struct req_que *req = ha->req_q_map[0];
|
|
|
3c6e85 |
uint16_t cnt, chksum;
|
|
|
3c6e85 |
- uint16_t *wptr;
|
|
|
3c6e85 |
- struct qla_fdt_layout *fdt;
|
|
|
3c6e85 |
+ uint16_t *wptr = (void *)req->ring;
|
|
|
3c6e85 |
+ struct qla_fdt_layout *fdt = (void *)req->ring;
|
|
|
3c6e85 |
uint8_t man_id, flash_id;
|
|
|
3c6e85 |
uint16_t mid = 0, fid = 0;
|
|
|
3c6e85 |
- struct qla_hw_data *ha = vha->hw;
|
|
|
3c6e85 |
- struct req_que *req = ha->req_q_map[0];
|
|
|
3c6e85 |
|
|
|
3c6e85 |
- wptr = (uint16_t *)req->ring;
|
|
|
3c6e85 |
- fdt = (struct qla_fdt_layout *)req->ring;
|
|
|
3c6e85 |
- ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
|
|
|
3c6e85 |
- ha->flt_region_fdt << 2, OPTROM_BURST_SIZE);
|
|
|
3c6e85 |
- if (*wptr == cpu_to_le16(0xffff))
|
|
|
3c6e85 |
+ qla24xx_read_flash_data(vha, (void *)fdt, ha->flt_region_fdt,
|
|
|
3c6e85 |
+ OPTROM_BURST_DWORDS);
|
|
|
3c6e85 |
+ if (le16_to_cpu(*wptr) == 0xffff)
|
|
|
3c6e85 |
goto no_flash_data;
|
|
|
3c6e85 |
- if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' ||
|
|
|
3c6e85 |
- fdt->sig[3] != 'D')
|
|
|
3c6e85 |
+ if (memcmp(fdt->sig, "QLID", 4))
|
|
|
3c6e85 |
goto no_flash_data;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
for (cnt = 0, chksum = 0; cnt < sizeof(*fdt) >> 1; cnt++, wptr++)
|
|
|
3c6e85 |
@@ -1022,8 +1016,7 @@ qla2xxx_get_idc_param(scsi_qla_host_t *vha)
|
|
|
3c6e85 |
return;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
wptr = (uint32_t *)req->ring;
|
|
|
3c6e85 |
- ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
|
|
|
3c6e85 |
- QLA82XX_IDC_PARAM_ADDR , 8);
|
|
|
3c6e85 |
+ ha->isp_ops->read_optrom(vha, req->ring, QLA82XX_IDC_PARAM_ADDR, 8);
|
|
|
3c6e85 |
|
|
|
3c6e85 |
if (*wptr == cpu_to_le32(0xffffffff)) {
|
|
|
3c6e85 |
ha->fcoe_dev_init_timeout = QLA82XX_ROM_DEV_INIT_TIMEOUT;
|
|
|
3c6e85 |
@@ -1085,8 +1078,8 @@ qla2xxx_flash_npiv_conf(scsi_qla_host_t *vha)
|
|
|
3c6e85 |
if (IS_QLA8044(ha))
|
|
|
3c6e85 |
return;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
- ha->isp_ops->read_optrom(vha, (uint8_t *)&hdr,
|
|
|
3c6e85 |
- ha->flt_region_npiv_conf << 2, sizeof(struct qla_npiv_header));
|
|
|
3c6e85 |
+ ha->isp_ops->read_optrom(vha, &hdr, ha->flt_region_npiv_conf << 2,
|
|
|
3c6e85 |
+ sizeof(struct qla_npiv_header));
|
|
|
3c6e85 |
if (hdr.version == cpu_to_le16(0xffff))
|
|
|
3c6e85 |
return;
|
|
|
3c6e85 |
if (hdr.version != cpu_to_le16(1)) {
|
|
|
3c6e85 |
@@ -1105,8 +1098,8 @@ qla2xxx_flash_npiv_conf(scsi_qla_host_t *vha)
|
|
|
3c6e85 |
return;
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
|
|
|
3c6e85 |
- ha->isp_ops->read_optrom(vha, (uint8_t *)data,
|
|
|
3c6e85 |
- ha->flt_region_npiv_conf << 2, NPIV_CONFIG_SIZE);
|
|
|
3c6e85 |
+ ha->isp_ops->read_optrom(vha, data, ha->flt_region_npiv_conf << 2,
|
|
|
3c6e85 |
+ NPIV_CONFIG_SIZE);
|
|
|
3c6e85 |
|
|
|
3c6e85 |
cnt = (sizeof(hdr) + le16_to_cpu(hdr.entries) * sizeof(*entry)) >> 1;
|
|
|
3c6e85 |
for (wptr = data, chksum = 0; cnt--; wptr++)
|
|
|
3c6e85 |
@@ -1143,10 +1136,8 @@ qla2xxx_flash_npiv_conf(scsi_qla_host_t *vha)
|
|
|
3c6e85 |
vid.node_name = wwn_to_u64(entry->node_name);
|
|
|
3c6e85 |
|
|
|
3c6e85 |
ql_dbg(ql_dbg_user, vha, 0x7093,
|
|
|
3c6e85 |
- "NPIV[%02x]: wwpn=%llx "
|
|
|
3c6e85 |
- "wwnn=%llx vf_id=0x%x Q_qos=0x%x F_qos=0x%x.\n", cnt,
|
|
|
3c6e85 |
- (unsigned long long)vid.port_name,
|
|
|
3c6e85 |
- (unsigned long long)vid.node_name,
|
|
|
3c6e85 |
+ "NPIV[%02x]: wwpn=%llx wwnn=%llx vf_id=%#x Q_qos=%#x F_qos=%#x.\n",
|
|
|
3c6e85 |
+ cnt, vid.port_name, vid.node_name,
|
|
|
3c6e85 |
le16_to_cpu(entry->vf_id),
|
|
|
3c6e85 |
entry->q_qos, entry->f_qos);
|
|
|
3c6e85 |
|
|
|
3c6e85 |
@@ -1154,10 +1145,8 @@ qla2xxx_flash_npiv_conf(scsi_qla_host_t *vha)
|
|
|
3c6e85 |
vport = fc_vport_create(vha->host, 0, &vid);
|
|
|
3c6e85 |
if (!vport)
|
|
|
3c6e85 |
ql_log(ql_log_warn, vha, 0x7094,
|
|
|
3c6e85 |
- "NPIV-Config Failed to create vport [%02x]: "
|
|
|
3c6e85 |
- "wwpn=%llx wwnn=%llx.\n", cnt,
|
|
|
3c6e85 |
- (unsigned long long)vid.port_name,
|
|
|
3c6e85 |
- (unsigned long long)vid.node_name);
|
|
|
3c6e85 |
+ "NPIV-Config Failed to create vport [%02x]: wwpn=%llx wwnn=%llx.\n",
|
|
|
3c6e85 |
+ cnt, vid.port_name, vid.node_name);
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
done:
|
|
|
3c6e85 |
@@ -1192,9 +1181,10 @@ done:
|
|
|
3c6e85 |
static int
|
|
|
3c6e85 |
qla24xx_protect_flash(scsi_qla_host_t *vha)
|
|
|
3c6e85 |
{
|
|
|
3c6e85 |
- uint32_t cnt;
|
|
|
3c6e85 |
struct qla_hw_data *ha = vha->hw;
|
|
|
3c6e85 |
struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
|
|
|
3c6e85 |
+ ulong cnt = 300;
|
|
|
3c6e85 |
+ uint32_t faddr, dword;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
if (ha->flags.fac_supported)
|
|
|
3c6e85 |
return qla81xx_fac_do_write_enable(vha, 0);
|
|
|
3c6e85 |
@@ -1203,11 +1193,14 @@ qla24xx_protect_flash(scsi_qla_host_t *vha)
|
|
|
3c6e85 |
goto skip_wrt_protect;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
/* Enable flash write-protection and wait for completion. */
|
|
|
3c6e85 |
- qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101),
|
|
|
3c6e85 |
- ha->fdt_wrt_disable);
|
|
|
3c6e85 |
- for (cnt = 300; cnt &&
|
|
|
3c6e85 |
- qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x005)) & BIT_0;
|
|
|
3c6e85 |
- cnt--) {
|
|
|
3c6e85 |
+ faddr = flash_conf_addr(ha, 0x101);
|
|
|
3c6e85 |
+ qla24xx_write_flash_dword(ha, faddr, ha->fdt_wrt_disable);
|
|
|
3c6e85 |
+ faddr = flash_conf_addr(ha, 0x5);
|
|
|
3c6e85 |
+ while (cnt--) {
|
|
|
3c6e85 |
+ if (!qla24xx_read_flash_dword(ha, faddr, &dword)) {
|
|
|
3c6e85 |
+ if (!(dword & BIT_0))
|
|
|
3c6e85 |
+ break;
|
|
|
3c6e85 |
+ }
|
|
|
3c6e85 |
udelay(10);
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
|
|
|
3c6e85 |
@@ -1215,7 +1208,6 @@ skip_wrt_protect:
|
|
|
3c6e85 |
/* Disable flash write. */
|
|
|
3c6e85 |
WRT_REG_DWORD(®->ctrl_status,
|
|
|
3c6e85 |
RD_REG_DWORD(®->ctrl_status) & ~CSRX_FLASH_ENABLE);
|
|
|
3c6e85 |
- RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */
|
|
|
3c6e85 |
|
|
|
3c6e85 |
return QLA_SUCCESS;
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
@@ -1243,107 +1235,103 @@ qla24xx_write_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
|
|
|
3c6e85 |
uint32_t dwords)
|
|
|
3c6e85 |
{
|
|
|
3c6e85 |
int ret;
|
|
|
3c6e85 |
- uint32_t liter;
|
|
|
3c6e85 |
- uint32_t sec_mask, rest_addr;
|
|
|
3c6e85 |
- uint32_t fdata;
|
|
|
3c6e85 |
+ ulong liter;
|
|
|
3c6e85 |
+ ulong dburst = OPTROM_BURST_DWORDS; /* burst size in dwords */
|
|
|
3c6e85 |
+ uint32_t sec_mask, rest_addr, fdata;
|
|
|
3c6e85 |
dma_addr_t optrom_dma;
|
|
|
3c6e85 |
void *optrom = NULL;
|
|
|
3c6e85 |
struct qla_hw_data *ha = vha->hw;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
- /* Prepare burst-capable write on supported ISPs. */
|
|
|
3c6e85 |
- if ((IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) ||
|
|
|
3c6e85 |
- IS_QLA27XX(ha) || IS_QLA28XX(ha)) &&
|
|
|
3c6e85 |
- !(faddr & 0xfff) && dwords > OPTROM_BURST_DWORDS) {
|
|
|
3c6e85 |
- optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
|
|
|
3c6e85 |
- &optrom_dma, GFP_KERNEL);
|
|
|
3c6e85 |
- if (!optrom) {
|
|
|
3c6e85 |
- ql_log(ql_log_warn, vha, 0x7095,
|
|
|
3c6e85 |
- "Unable to allocate "
|
|
|
3c6e85 |
- "memory for optrom burst write (%x KB).\n",
|
|
|
3c6e85 |
- OPTROM_BURST_SIZE / 1024);
|
|
|
3c6e85 |
- }
|
|
|
3c6e85 |
- }
|
|
|
3c6e85 |
+ if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
|
|
|
3c6e85 |
+ !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
|
|
|
3c6e85 |
+ goto next;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
- rest_addr = (ha->fdt_block_size >> 2) - 1;
|
|
|
3c6e85 |
- sec_mask = ~rest_addr;
|
|
|
3c6e85 |
+ /* Allocate dma buffer for burst write */
|
|
|
3c6e85 |
+ optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
|
|
|
3c6e85 |
+ &optrom_dma, GFP_KERNEL);
|
|
|
3c6e85 |
+ if (!optrom) {
|
|
|
3c6e85 |
+ ql_log(ql_log_warn, vha, 0x7095,
|
|
|
3c6e85 |
+ "Failed allocate burst (%x bytes)\n", OPTROM_BURST_SIZE);
|
|
|
3c6e85 |
+ }
|
|
|
3c6e85 |
|
|
|
3c6e85 |
+next:
|
|
|
3c6e85 |
+ ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095,
|
|
|
3c6e85 |
+ "Unprotect flash...\n");
|
|
|
3c6e85 |
ret = qla24xx_unprotect_flash(vha);
|
|
|
3c6e85 |
- if (ret != QLA_SUCCESS) {
|
|
|
3c6e85 |
+ if (ret) {
|
|
|
3c6e85 |
ql_log(ql_log_warn, vha, 0x7096,
|
|
|
3c6e85 |
- "Unable to unprotect flash for update.\n");
|
|
|
3c6e85 |
+ "Failed to unprotect flash.\n");
|
|
|
3c6e85 |
goto done;
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
|
|
|
3c6e85 |
+ rest_addr = (ha->fdt_block_size >> 2) - 1;
|
|
|
3c6e85 |
+ sec_mask = ~rest_addr;
|
|
|
3c6e85 |
for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) {
|
|
|
3c6e85 |
fdata = (faddr & sec_mask) << 2;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
/* Are we at the beginning of a sector? */
|
|
|
3c6e85 |
- if ((faddr & rest_addr) == 0) {
|
|
|
3c6e85 |
- /* Do sector unprotect. */
|
|
|
3c6e85 |
- if (ha->fdt_unprotect_sec_cmd)
|
|
|
3c6e85 |
- qla24xx_write_flash_dword(ha,
|
|
|
3c6e85 |
- ha->fdt_unprotect_sec_cmd,
|
|
|
3c6e85 |
- (fdata & 0xff00) | ((fdata << 16) &
|
|
|
3c6e85 |
- 0xff0000) | ((fdata >> 16) & 0xff));
|
|
|
3c6e85 |
+ if (!(faddr & rest_addr)) {
|
|
|
3c6e85 |
+ ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095,
|
|
|
3c6e85 |
+ "Erase sector %#x...\n", faddr);
|
|
|
3c6e85 |
+
|
|
|
3c6e85 |
ret = qla24xx_erase_sector(vha, fdata);
|
|
|
3c6e85 |
- if (ret != QLA_SUCCESS) {
|
|
|
3c6e85 |
+ if (ret) {
|
|
|
3c6e85 |
ql_dbg(ql_dbg_user, vha, 0x7007,
|
|
|
3c6e85 |
- "Unable to erase erase sector: address=%x.\n",
|
|
|
3c6e85 |
- faddr);
|
|
|
3c6e85 |
+ "Failed to erase sector %x.\n", faddr);
|
|
|
3c6e85 |
break;
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
|
|
|
3c6e85 |
- /* Go with burst-write. */
|
|
|
3c6e85 |
- if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) {
|
|
|
3c6e85 |
- /* Copy data to DMA'ble buffer. */
|
|
|
3c6e85 |
- memcpy(optrom, dwptr, OPTROM_BURST_SIZE);
|
|
|
3c6e85 |
+ if (optrom) {
|
|
|
3c6e85 |
+ /* If smaller than a burst remaining */
|
|
|
3c6e85 |
+ if (dwords - liter < dburst)
|
|
|
3c6e85 |
+ dburst = dwords - liter;
|
|
|
3c6e85 |
+
|
|
|
3c6e85 |
+ /* Copy to dma buffer */
|
|
|
3c6e85 |
+ memcpy(optrom, dwptr, dburst << 2);
|
|
|
3c6e85 |
|
|
|
3c6e85 |
+ /* Burst write */
|
|
|
3c6e85 |
+ ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095,
|
|
|
3c6e85 |
+ "Write burst (%#lx dwords)...\n", dburst);
|
|
|
3c6e85 |
ret = qla2x00_load_ram(vha, optrom_dma,
|
|
|
3c6e85 |
- flash_data_addr(ha, faddr),
|
|
|
3c6e85 |
- OPTROM_BURST_DWORDS);
|
|
|
3c6e85 |
- if (ret != QLA_SUCCESS) {
|
|
|
3c6e85 |
- ql_log(ql_log_warn, vha, 0x7097,
|
|
|
3c6e85 |
- "Unable to burst-write optrom segment "
|
|
|
3c6e85 |
- "(%x/%x/%llx).\n", ret,
|
|
|
3c6e85 |
- flash_data_addr(ha, faddr),
|
|
|
3c6e85 |
- (unsigned long long)optrom_dma);
|
|
|
3c6e85 |
- ql_log(ql_log_warn, vha, 0x7098,
|
|
|
3c6e85 |
- "Reverting to slow-write.\n");
|
|
|
3c6e85 |
-
|
|
|
3c6e85 |
- dma_free_coherent(&ha->pdev->dev,
|
|
|
3c6e85 |
- OPTROM_BURST_SIZE, optrom, optrom_dma);
|
|
|
3c6e85 |
- optrom = NULL;
|
|
|
3c6e85 |
- } else {
|
|
|
3c6e85 |
- liter += OPTROM_BURST_DWORDS - 1;
|
|
|
3c6e85 |
- faddr += OPTROM_BURST_DWORDS - 1;
|
|
|
3c6e85 |
- dwptr += OPTROM_BURST_DWORDS - 1;
|
|
|
3c6e85 |
+ flash_data_addr(ha, faddr), dburst);
|
|
|
3c6e85 |
+ if (!ret) {
|
|
|
3c6e85 |
+ liter += dburst - 1;
|
|
|
3c6e85 |
+ faddr += dburst - 1;
|
|
|
3c6e85 |
+ dwptr += dburst - 1;
|
|
|
3c6e85 |
continue;
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
+
|
|
|
3c6e85 |
+ ql_log(ql_log_warn, vha, 0x7097,
|
|
|
3c6e85 |
+ "Failed burst-write at %x (%p/%#llx)....\n",
|
|
|
3c6e85 |
+ flash_data_addr(ha, faddr), optrom,
|
|
|
3c6e85 |
+ (u64)optrom_dma);
|
|
|
3c6e85 |
+
|
|
|
3c6e85 |
+ dma_free_coherent(&ha->pdev->dev,
|
|
|
3c6e85 |
+ OPTROM_BURST_SIZE, optrom, optrom_dma);
|
|
|
3c6e85 |
+ optrom = NULL;
|
|
|
3c6e85 |
+ if (IS_QLA27XX(ha) || IS_QLA28XX(ha))
|
|
|
3c6e85 |
+ break;
|
|
|
3c6e85 |
+ ql_log(ql_log_warn, vha, 0x7098,
|
|
|
3c6e85 |
+ "Reverting to slow write...\n");
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
|
|
|
3c6e85 |
+ /* Slow write */
|
|
|
3c6e85 |
ret = qla24xx_write_flash_dword(ha,
|
|
|
3c6e85 |
flash_data_addr(ha, faddr), cpu_to_le32(*dwptr));
|
|
|
3c6e85 |
- if (ret != QLA_SUCCESS) {
|
|
|
3c6e85 |
+ if (ret) {
|
|
|
3c6e85 |
ql_dbg(ql_dbg_user, vha, 0x7006,
|
|
|
3c6e85 |
- "Unable to program flash address=%x data=%x.\n",
|
|
|
3c6e85 |
- faddr, *dwptr);
|
|
|
3c6e85 |
+ "Failed slopw write %x (%x)\n", faddr, *dwptr);
|
|
|
3c6e85 |
break;
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
-
|
|
|
3c6e85 |
- /* Do sector protect. */
|
|
|
3c6e85 |
- if (ha->fdt_unprotect_sec_cmd &&
|
|
|
3c6e85 |
- ((faddr & rest_addr) == rest_addr))
|
|
|
3c6e85 |
- qla24xx_write_flash_dword(ha,
|
|
|
3c6e85 |
- ha->fdt_protect_sec_cmd,
|
|
|
3c6e85 |
- (fdata & 0xff00) | ((fdata << 16) &
|
|
|
3c6e85 |
- 0xff0000) | ((fdata >> 16) & 0xff));
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
|
|
|
3c6e85 |
+ ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095,
|
|
|
3c6e85 |
+ "Protect flash...\n");
|
|
|
3c6e85 |
ret = qla24xx_protect_flash(vha);
|
|
|
3c6e85 |
- if (ret != QLA_SUCCESS)
|
|
|
3c6e85 |
+ if (ret)
|
|
|
3c6e85 |
ql_log(ql_log_warn, vha, 0x7099,
|
|
|
3c6e85 |
- "Unable to protect flash after update.\n");
|
|
|
3c6e85 |
+ "Failed to protect flash\n");
|
|
|
3c6e85 |
done:
|
|
|
3c6e85 |
if (optrom)
|
|
|
3c6e85 |
dma_free_coherent(&ha->pdev->dev,
|
|
|
3c6e85 |
@@ -1353,7 +1341,7 @@ done:
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
|
|
|
3c6e85 |
uint8_t *
|
|
|
3c6e85 |
-qla2x00_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
|
|
|
3c6e85 |
+qla2x00_read_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr,
|
|
|
3c6e85 |
uint32_t bytes)
|
|
|
3c6e85 |
{
|
|
|
3c6e85 |
uint32_t i;
|
|
|
3c6e85 |
@@ -1372,27 +1360,30 @@ qla2x00_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
|
|
|
3c6e85 |
uint8_t *
|
|
|
3c6e85 |
-qla24xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
|
|
|
3c6e85 |
+qla24xx_read_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr,
|
|
|
3c6e85 |
uint32_t bytes)
|
|
|
3c6e85 |
{
|
|
|
3c6e85 |
- uint32_t i;
|
|
|
3c6e85 |
- uint32_t *dwptr;
|
|
|
3c6e85 |
struct qla_hw_data *ha = vha->hw;
|
|
|
3c6e85 |
+ uint32_t *dwptr = buf;
|
|
|
3c6e85 |
+ uint32_t i;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
if (IS_P3P_TYPE(ha))
|
|
|
3c6e85 |
return buf;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
/* Dword reads to flash. */
|
|
|
3c6e85 |
- dwptr = (uint32_t *)buf;
|
|
|
3c6e85 |
- for (i = 0; i < bytes >> 2; i++, naddr++)
|
|
|
3c6e85 |
- dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
|
|
|
3c6e85 |
- nvram_data_addr(ha, naddr)));
|
|
|
3c6e85 |
+ naddr = nvram_data_addr(ha, naddr);
|
|
|
3c6e85 |
+ bytes >>= 2;
|
|
|
3c6e85 |
+ for (i = 0; i < bytes; i++, naddr++, dwptr++) {
|
|
|
3c6e85 |
+ if (qla24xx_read_flash_dword(ha, naddr, dwptr))
|
|
|
3c6e85 |
+ break;
|
|
|
3c6e85 |
+ cpu_to_le32s(dwptr);
|
|
|
3c6e85 |
+ }
|
|
|
3c6e85 |
|
|
|
3c6e85 |
return buf;
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
|
|
|
3c6e85 |
int
|
|
|
3c6e85 |
-qla2x00_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
|
|
|
3c6e85 |
+qla2x00_write_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr,
|
|
|
3c6e85 |
uint32_t bytes)
|
|
|
3c6e85 |
{
|
|
|
3c6e85 |
int ret, stat;
|
|
|
3c6e85 |
@@ -1426,14 +1417,14 @@ qla2x00_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
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3c6e85 |
}
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3c6e85 |
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3c6e85 |
int
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3c6e85 |
-qla24xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
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3c6e85 |
+qla24xx_write_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr,
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3c6e85 |
uint32_t bytes)
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3c6e85 |
{
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3c6e85 |
- int ret;
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3c6e85 |
- uint32_t i;
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3c6e85 |
- uint32_t *dwptr;
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3c6e85 |
struct qla_hw_data *ha = vha->hw;
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3c6e85 |
struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
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3c6e85 |
+ uint32_t *dwptr = buf;
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3c6e85 |
+ uint32_t i;
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3c6e85 |
+ int ret;
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3c6e85 |
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3c6e85 |
ret = QLA_SUCCESS;
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3c6e85 |
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3c6e85 |
@@ -1450,11 +1441,10 @@ qla24xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
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3c6e85 |
qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0);
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3c6e85 |
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3c6e85 |
/* Dword writes to flash. */
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3c6e85 |
- dwptr = (uint32_t *)buf;
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3c6e85 |
- for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) {
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3c6e85 |
- ret = qla24xx_write_flash_dword(ha,
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3c6e85 |
- nvram_data_addr(ha, naddr), cpu_to_le32(*dwptr));
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3c6e85 |
- if (ret != QLA_SUCCESS) {
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3c6e85 |
+ naddr = nvram_data_addr(ha, naddr);
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3c6e85 |
+ bytes >>= 2;
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3c6e85 |
+ for (i = 0; i < bytes; i++, naddr++, dwptr++) {
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3c6e85 |
+ if (qla24xx_write_flash_dword(ha, naddr, cpu_to_le32(*dwptr))) {
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3c6e85 |
ql_dbg(ql_dbg_user, vha, 0x709a,
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3c6e85 |
"Unable to program nvram address=%x data=%x.\n",
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3c6e85 |
naddr, *dwptr);
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3c6e85 |
@@ -1474,31 +1464,34 @@ qla24xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
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3c6e85 |
}
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3c6e85 |
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3c6e85 |
uint8_t *
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3c6e85 |
-qla25xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
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3c6e85 |
+qla25xx_read_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr,
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3c6e85 |
uint32_t bytes)
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3c6e85 |
{
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3c6e85 |
- uint32_t i;
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3c6e85 |
- uint32_t *dwptr;
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3c6e85 |
struct qla_hw_data *ha = vha->hw;
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3c6e85 |
+ uint32_t *dwptr = buf;
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3c6e85 |
+ uint32_t i;
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3c6e85 |
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3c6e85 |
/* Dword reads to flash. */
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3c6e85 |
- dwptr = (uint32_t *)buf;
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3c6e85 |
- for (i = 0; i < bytes >> 2; i++, naddr++)
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3c6e85 |
- dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
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3c6e85 |
- flash_data_addr(ha, ha->flt_region_vpd_nvram | naddr)));
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3c6e85 |
+ naddr = flash_data_addr(ha, ha->flt_region_vpd_nvram | naddr);
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3c6e85 |
+ bytes >>= 2;
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3c6e85 |
+ for (i = 0; i < bytes; i++, naddr++, dwptr++) {
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3c6e85 |
+ if (qla24xx_read_flash_dword(ha, naddr, dwptr))
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3c6e85 |
+ break;
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3c6e85 |
+
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3c6e85 |
+ cpu_to_le32s(dwptr);
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3c6e85 |
+ }
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3c6e85 |
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3c6e85 |
return buf;
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3c6e85 |
}
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3c6e85 |
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3c6e85 |
+#define RMW_BUFFER_SIZE (64 * 1024)
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3c6e85 |
int
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3c6e85 |
-qla25xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
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3c6e85 |
+qla25xx_write_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr,
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3c6e85 |
uint32_t bytes)
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3c6e85 |
{
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3c6e85 |
struct qla_hw_data *ha = vha->hw;
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3c6e85 |
-#define RMW_BUFFER_SIZE (64 * 1024)
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3c6e85 |
- uint8_t *dbuf;
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3c6e85 |
+ uint8_t *dbuf = vmalloc(RMW_BUFFER_SIZE);
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3c6e85 |
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3c6e85 |
- dbuf = vmalloc(RMW_BUFFER_SIZE);
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3c6e85 |
if (!dbuf)
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3c6e85 |
return QLA_MEMORY_ALLOC_FAILED;
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3c6e85 |
ha->isp_ops->read_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
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3c6e85 |
@@ -2319,8 +2312,8 @@ qla2x00_resume_hba(struct scsi_qla_host *vha)
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3c6e85 |
scsi_unblock_requests(vha->host);
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3c6e85 |
}
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3c6e85 |
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3c6e85 |
-uint8_t *
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3c6e85 |
-qla2x00_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
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3c6e85 |
+void *
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3c6e85 |
+qla2x00_read_optrom_data(struct scsi_qla_host *vha, void *buf,
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3c6e85 |
uint32_t offset, uint32_t length)
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3c6e85 |
{
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3c6e85 |
uint32_t addr, midpoint;
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3c6e85 |
@@ -2354,12 +2347,12 @@ qla2x00_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
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3c6e85 |
}
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3c6e85 |
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3c6e85 |
int
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3c6e85 |
-qla2x00_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
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3c6e85 |
+qla2x00_write_optrom_data(struct scsi_qla_host *vha, void *buf,
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3c6e85 |
uint32_t offset, uint32_t length)
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3c6e85 |
{
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3c6e85 |
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3c6e85 |
int rval;
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3c6e85 |
- uint8_t man_id, flash_id, sec_number, data;
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3c6e85 |
+ uint8_t man_id, flash_id, sec_number, *data;
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3c6e85 |
uint16_t wd;
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3c6e85 |
uint32_t addr, liter, sec_mask, rest_addr;
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3c6e85 |
struct qla_hw_data *ha = vha->hw;
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3c6e85 |
@@ -2488,7 +2481,7 @@ update_flash:
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3c6e85 |
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3c6e85 |
for (addr = offset, liter = 0; liter < length; liter++,
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3c6e85 |
addr++) {
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3c6e85 |
- data = buf[liter];
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3c6e85 |
+ data = buf + liter;
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3c6e85 |
/* Are we at the beginning of a sector? */
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3c6e85 |
if ((addr & rest_addr) == 0) {
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3c6e85 |
if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
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3c6e85 |
@@ -2556,7 +2549,7 @@ update_flash:
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3c6e85 |
}
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3c6e85 |
}
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3c6e85 |
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3c6e85 |
- if (qla2x00_program_flash_address(ha, addr, data,
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3c6e85 |
+ if (qla2x00_program_flash_address(ha, addr, *data,
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3c6e85 |
man_id, flash_id)) {
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3c6e85 |
rval = QLA_FUNCTION_FAILED;
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3c6e85 |
break;
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3c6e85 |
@@ -2572,8 +2565,8 @@ update_flash:
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3c6e85 |
return rval;
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3c6e85 |
}
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3c6e85 |
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3c6e85 |
-uint8_t *
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3c6e85 |
-qla24xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
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3c6e85 |
+void *
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3c6e85 |
+qla24xx_read_optrom_data(struct scsi_qla_host *vha, void *buf,
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3c6e85 |
uint32_t offset, uint32_t length)
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3c6e85 |
{
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3c6e85 |
struct qla_hw_data *ha = vha->hw;
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3c6e85 |
@@ -2583,7 +2576,7 @@ qla24xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
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3c6e85 |
set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
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3c6e85 |
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3c6e85 |
/* Go with read. */
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3c6e85 |
- qla24xx_read_flash_data(vha, (uint32_t *)buf, offset >> 2, length >> 2);
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3c6e85 |
+ qla24xx_read_flash_data(vha, (void *)buf, offset >> 2, length >> 2);
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3c6e85 |
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3c6e85 |
/* Resume HBA. */
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3c6e85 |
clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
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3c6e85 |
@@ -2593,7 +2586,7 @@ qla24xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
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3c6e85 |
}
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3c6e85 |
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3c6e85 |
int
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3c6e85 |
-qla24xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
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3c6e85 |
+qla24xx_write_optrom_data(struct scsi_qla_host *vha, void *buf,
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3c6e85 |
uint32_t offset, uint32_t length)
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3c6e85 |
{
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3c6e85 |
int rval;
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3c6e85 |
@@ -2604,7 +2597,7 @@ qla24xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
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3c6e85 |
set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
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3c6e85 |
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3c6e85 |
/* Go with write. */
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3c6e85 |
- rval = qla24xx_write_flash_data(vha, (uint32_t *)buf, offset >> 2,
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3c6e85 |
+ rval = qla24xx_write_flash_data(vha, buf, offset >> 2,
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3c6e85 |
length >> 2);
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3c6e85 |
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3c6e85 |
clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
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3c6e85 |
@@ -2613,8 +2606,8 @@ qla24xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
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3c6e85 |
return rval;
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3c6e85 |
}
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3c6e85 |
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3c6e85 |
-uint8_t *
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3c6e85 |
-qla25xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
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3c6e85 |
+void *
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3c6e85 |
+qla25xx_read_optrom_data(struct scsi_qla_host *vha, void *buf,
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3c6e85 |
uint32_t offset, uint32_t length)
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3c6e85 |
{
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3c6e85 |
int rval;
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3c6e85 |
@@ -2881,7 +2874,7 @@ qla2x00_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
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3c6e85 |
"Dumping fw "
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3c6e85 |
"ver from flash:.\n");
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3c6e85 |
ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010b,
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3c6e85 |
- dbyte, 8);
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3c6e85 |
+ dbyte, 32);
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3c6e85 |
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3c6e85 |
if ((dcode[0] == 0xffff && dcode[1] == 0xffff &&
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3c6e85 |
dcode[2] == 0xffff && dcode[3] == 0xffff) ||
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3c6e85 |
@@ -2912,8 +2905,8 @@ qla82xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
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3c6e85 |
{
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3c6e85 |
int ret = QLA_SUCCESS;
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3c6e85 |
uint32_t pcihdr, pcids;
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3c6e85 |
- uint32_t *dcode;
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3c6e85 |
- uint8_t *bcode;
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3c6e85 |
+ uint32_t *dcode = mbuf;
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3c6e85 |
+ uint8_t *bcode = mbuf;
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3c6e85 |
uint8_t code_type, last_image;
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3c6e85 |
struct qla_hw_data *ha = vha->hw;
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3c6e85 |
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3c6e85 |
@@ -2925,17 +2918,14 @@ qla82xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
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3c6e85 |
memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
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3c6e85 |
memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
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3c6e85 |
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3c6e85 |
- dcode = mbuf;
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3c6e85 |
-
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3c6e85 |
/* Begin with first PCI expansion ROM header. */
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3c6e85 |
pcihdr = ha->flt_region_boot << 2;
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3c6e85 |
last_image = 1;
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3c6e85 |
do {
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3c6e85 |
/* Verify PCI expansion ROM header. */
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3c6e85 |
- ha->isp_ops->read_optrom(vha, (uint8_t *)dcode, pcihdr,
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3c6e85 |
- 0x20 * 4);
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3c6e85 |
+ ha->isp_ops->read_optrom(vha, dcode, pcihdr, 0x20 * 4);
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3c6e85 |
bcode = mbuf + (pcihdr % 4);
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3c6e85 |
- if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) {
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3c6e85 |
+ if (memcmp(bcode, "\x55\xaa", 2)) {
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3c6e85 |
/* No signature */
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3c6e85 |
ql_log(ql_log_fatal, vha, 0x0154,
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3c6e85 |
"No matching ROM signature.\n");
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3c6e85 |
@@ -2946,13 +2936,11 @@ qla82xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
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3c6e85 |
/* Locate PCI data structure. */
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3c6e85 |
pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
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3c6e85 |
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3c6e85 |
- ha->isp_ops->read_optrom(vha, (uint8_t *)dcode, pcids,
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3c6e85 |
- 0x20 * 4);
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3c6e85 |
+ ha->isp_ops->read_optrom(vha, dcode, pcids, 0x20 * 4);
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3c6e85 |
bcode = mbuf + (pcihdr % 4);
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3c6e85 |
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3c6e85 |
/* Validate signature of PCI data structure. */
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3c6e85 |
- if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
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3c6e85 |
- bcode[0x2] != 'I' || bcode[0x3] != 'R') {
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3c6e85 |
+ if (memcmp(bcode, "PCIR", 4)) {
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3c6e85 |
/* Incorrect header. */
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3c6e85 |
ql_log(ql_log_fatal, vha, 0x0155,
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3c6e85 |
"PCI data struct not found pcir_adr=%x.\n", pcids);
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3c6e85 |
@@ -3003,8 +2991,7 @@ qla82xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
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3c6e85 |
/* Read firmware image information. */
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3c6e85 |
memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
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3c6e85 |
dcode = mbuf;
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3c6e85 |
- ha->isp_ops->read_optrom(vha, (uint8_t *)dcode, ha->flt_region_fw << 2,
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3c6e85 |
- 0x20);
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3c6e85 |
+ ha->isp_ops->read_optrom(vha, dcode, ha->flt_region_fw << 2, 0x20);
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3c6e85 |
bcode = mbuf + (pcihdr % 4);
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3c6e85 |
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3c6e85 |
/* Validate signature of PCI data structure. */
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3c6e85 |
@@ -3026,16 +3013,14 @@ int
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3c6e85 |
qla24xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
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3c6e85 |
{
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3c6e85 |
int ret = QLA_SUCCESS;
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3c6e85 |
- uint32_t pcihdr, pcids;
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3c6e85 |
- uint32_t *dcode;
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3c6e85 |
- uint8_t *bcode;
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3c6e85 |
+ uint32_t pcihdr = 0, pcids = 0;
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3c6e85 |
+ uint32_t *dcode = mbuf;
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3c6e85 |
+ uint8_t *bcode = mbuf;
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3c6e85 |
uint8_t code_type, last_image;
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3c6e85 |
int i;
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3c6e85 |
struct qla_hw_data *ha = vha->hw;
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3c6e85 |
uint32_t faddr = 0;
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3c6e85 |
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3c6e85 |
- pcihdr = pcids = 0;
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3c6e85 |
-
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3c6e85 |
if (IS_P3P_TYPE(ha))
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3c6e85 |
return ret;
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3c6e85 |
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3c6e85 |
@@ -3047,18 +3032,16 @@ qla24xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
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3c6e85 |
memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
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3c6e85 |
memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
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3c6e85 |
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3c6e85 |
- dcode = mbuf;
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3c6e85 |
pcihdr = ha->flt_region_boot << 2;
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3c6e85 |
if ((IS_QLA27XX(ha) || IS_QLA28XX(ha)) &&
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3c6e85 |
qla27xx_find_valid_image(vha) == QLA27XX_SECONDARY_IMAGE)
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3c6e85 |
pcihdr = ha->flt_region_boot_sec << 2;
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3c6e85 |
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3c6e85 |
- last_image = 1;
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3c6e85 |
do {
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3c6e85 |
/* Verify PCI expansion ROM header. */
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3c6e85 |
qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
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3c6e85 |
bcode = mbuf + (pcihdr % 4);
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3c6e85 |
- if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) {
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3c6e85 |
+ if (memcmp(bcode, "\x55\xaa", 2)) {
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3c6e85 |
/* No signature */
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3c6e85 |
ql_log(ql_log_fatal, vha, 0x0059,
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3c6e85 |
"No matching ROM signature.\n");
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3c6e85 |
@@ -3073,11 +3056,11 @@ qla24xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
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3c6e85 |
bcode = mbuf + (pcihdr % 4);
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3c6e85 |
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3c6e85 |
/* Validate signature of PCI data structure. */
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3c6e85 |
- if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
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3c6e85 |
- bcode[0x2] != 'I' || bcode[0x3] != 'R') {
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3c6e85 |
+ if (memcmp(bcode, "PCIR", 4)) {
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3c6e85 |
/* Incorrect header. */
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3c6e85 |
ql_log(ql_log_fatal, vha, 0x005a,
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3c6e85 |
"PCI data struct not found pcir_adr=%x.\n", pcids);
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3c6e85 |
+ ql_dump_buffer(ql_dbg_init, vha, 0x0059, dcode, 32);
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3c6e85 |
ret = QLA_FUNCTION_FAILED;
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3c6e85 |
break;
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3c6e85 |
}
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3c6e85 |
@@ -3124,7 +3107,6 @@ qla24xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
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3c6e85 |
|
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3c6e85 |
/* Read firmware image information. */
|
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3c6e85 |
memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
|
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3c6e85 |
- dcode = mbuf;
|
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3c6e85 |
faddr = ha->flt_region_fw;
|
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3c6e85 |
if ((IS_QLA27XX(ha) || IS_QLA28XX(ha)) &&
|
|
|
3c6e85 |
qla27xx_find_valid_image(vha) == QLA27XX_SECONDARY_IMAGE)
|
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|
3c6e85 |
@@ -3135,11 +3117,12 @@ qla24xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
|
|
|
3c6e85 |
ql_log(ql_log_warn, vha, 0x005f,
|
|
|
3c6e85 |
"Unrecognized fw revision at %x.\n",
|
|
|
3c6e85 |
ha->flt_region_fw * 4);
|
|
|
3c6e85 |
+ ql_dump_buffer(ql_dbg_init, vha, 0x005f, dcode, 32);
|
|
|
3c6e85 |
} else {
|
|
|
3c6e85 |
for (i = 0; i < 4; i++)
|
|
|
3c6e85 |
ha->fw_revision[i] = be32_to_cpu(dcode[4+i]);
|
|
|
3c6e85 |
ql_dbg(ql_dbg_init, vha, 0x0060,
|
|
|
3c6e85 |
- "Firmware revision (flash) %d.%d.%d (%x).\n",
|
|
|
3c6e85 |
+ "Firmware revision (flash) %u.%u.%u (%x).\n",
|
|
|
3c6e85 |
ha->fw_revision[0], ha->fw_revision[1],
|
|
|
3c6e85 |
ha->fw_revision[2], ha->fw_revision[3]);
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
@@ -3151,12 +3134,12 @@ qla24xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
|
|
|
3c6e85 |
memset(ha->gold_fw_version, 0, sizeof(ha->gold_fw_version));
|
|
|
3c6e85 |
- dcode = mbuf;
|
|
|
3c6e85 |
- qla24xx_read_flash_data(vha, dcode, ha->flt_region_gold_fw, 8);
|
|
|
3c6e85 |
+ faddr = ha->flt_region_gold_fw;
|
|
|
3c6e85 |
+ qla24xx_read_flash_data(vha, (void *)dcode, ha->flt_region_gold_fw, 8);
|
|
|
3c6e85 |
if (qla24xx_risc_firmware_invalid(dcode)) {
|
|
|
3c6e85 |
ql_log(ql_log_warn, vha, 0x0056,
|
|
|
3c6e85 |
- "Unrecognized golden fw at 0x%x.\n",
|
|
|
3c6e85 |
- ha->flt_region_gold_fw * 4);
|
|
|
3c6e85 |
+ "Unrecognized golden fw at %#x.\n", faddr);
|
|
|
3c6e85 |
+ ql_dump_buffer(ql_dbg_init, vha, 0x0056, dcode, 32);
|
|
|
3c6e85 |
return ret;
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
|
|
|
3c6e85 |
@@ -3233,7 +3216,7 @@ qla24xx_read_fcp_prio_cfg(scsi_qla_host_t *vha)
|
|
|
3c6e85 |
fcp_prio_addr = ha->flt_region_fcp_prio;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
/* first read the fcp priority data header from flash */
|
|
|
3c6e85 |
- ha->isp_ops->read_optrom(vha, (uint8_t *)ha->fcp_prio_cfg,
|
|
|
3c6e85 |
+ ha->isp_ops->read_optrom(vha, ha->fcp_prio_cfg,
|
|
|
3c6e85 |
fcp_prio_addr << 2, FCP_PRIO_CFG_HDR_SIZE);
|
|
|
3c6e85 |
|
|
|
3c6e85 |
if (!qla24xx_fcp_prio_cfg_valid(vha, ha->fcp_prio_cfg, 0))
|
|
|
3c6e85 |
@@ -3244,7 +3227,7 @@ qla24xx_read_fcp_prio_cfg(scsi_qla_host_t *vha)
|
|
|
3c6e85 |
len = ha->fcp_prio_cfg->num_entries * FCP_PRIO_CFG_ENTRY_SIZE;
|
|
|
3c6e85 |
max_len = FCP_PRIO_CFG_SIZE - FCP_PRIO_CFG_HDR_SIZE;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
- ha->isp_ops->read_optrom(vha, (uint8_t *)&ha->fcp_prio_cfg->entry[0],
|
|
|
3c6e85 |
+ ha->isp_ops->read_optrom(vha, &ha->fcp_prio_cfg->entry[0],
|
|
|
3c6e85 |
fcp_prio_addr << 2, (len < max_len ? len : max_len));
|
|
|
3c6e85 |
|
|
|
3c6e85 |
/* revalidate the entire FCP priority config data, including entries */
|
|
|
3c6e85 |
--
|
|
|
3c6e85 |
2.13.6
|
|
|
3c6e85 |
|