|
 |
3c6e85 |
From e34881c9163c6a10a0ec45af51df9e862fd5a7b0 Mon Sep 17 00:00:00 2001
|
|
|
3c6e85 |
From: Himanshu Madhani <hmadhani@redhat.com>
|
|
|
3c6e85 |
Date: Thu, 1 Aug 2019 15:54:55 -0400
|
|
|
3c6e85 |
Subject: [PATCH 035/124] [scsi] scsi: qla2xxx: Cleanups for NVRAM/Flash
|
|
|
3c6e85 |
read/write path
|
|
|
3c6e85 |
|
|
|
3c6e85 |
Message-id: <20190801155618.12650-36-hmadhani@redhat.com>
|
|
|
3c6e85 |
Patchwork-id: 267808
|
|
|
3c6e85 |
O-Subject: [RHEL 7.8 e-stor PATCH 035/118] scsi: qla2xxx: Cleanups for NVRAM/Flash read/write path
|
|
|
3c6e85 |
Bugzilla: 1729270
|
|
|
3c6e85 |
RH-Acked-by: Jarod Wilson <jarod@redhat.com>
|
|
|
3c6e85 |
RH-Acked-by: Tony Camuso <tcamuso@redhat.com>
|
|
|
3c6e85 |
|
|
|
3c6e85 |
From: Joe Carnuccio <joe.carnuccio@cavium.com>
|
|
|
3c6e85 |
|
|
|
3c6e85 |
Bugzilla 1729270
|
|
|
3c6e85 |
|
|
|
3c6e85 |
This patch does following:
|
|
|
3c6e85 |
|
|
|
3c6e85 |
- Clean up NVRAM code.
|
|
|
3c6e85 |
- Optimizes reading of primary/secondary flash image validation.
|
|
|
3c6e85 |
- Remove 0xff mask and make correct width in FLT structure.
|
|
|
3c6e85 |
- Use endian macros to assign static fields in fwdump header.
|
|
|
3c6e85 |
- Correct fdwt checksum calculation.
|
|
|
3c6e85 |
- Simplify ql_dump_buffer() interface usage.
|
|
|
3c6e85 |
- Add endianizers to 27xx firmware image validator.
|
|
|
3c6e85 |
- fixes compiler warnings for big endian architecture.
|
|
|
3c6e85 |
|
|
|
3c6e85 |
Signed-off-by: Joe Carnuccio <joe.carnuccio@cavium.com>
|
|
|
3c6e85 |
Signed-off-by: Himanshu Madhani <hmadhani@marvell.com>
|
|
|
3c6e85 |
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
|
|
|
3c6e85 |
(cherry picked from commit f8f97b0c5b7f7c801d80ac78165edf25fff1f5e0)
|
|
|
3c6e85 |
Signed-off-by: Himanshu Madhani <hmadhani@redhat.com>
|
|
|
3c6e85 |
Signed-off-by: Jan Stancek <jstancek@redhat.com>
|
|
|
3c6e85 |
---
|
|
|
3c6e85 |
drivers/scsi/qla2xxx/qla_bsg.c | 6 +-
|
|
|
3c6e85 |
drivers/scsi/qla2xxx/qla_dbg.c | 19 ++---
|
|
|
3c6e85 |
drivers/scsi/qla2xxx/qla_dbg.h | 10 +--
|
|
|
3c6e85 |
drivers/scsi/qla2xxx/qla_def.h | 2 +-
|
|
|
3c6e85 |
drivers/scsi/qla2xxx/qla_fw.h | 4 +-
|
|
|
3c6e85 |
drivers/scsi/qla2xxx/qla_gbl.h | 10 +--
|
|
|
3c6e85 |
drivers/scsi/qla2xxx/qla_gs.c | 4 +-
|
|
|
3c6e85 |
drivers/scsi/qla2xxx/qla_init.c | 143 ++++++++++++++-----------------
|
|
|
3c6e85 |
drivers/scsi/qla2xxx/qla_isr.c | 12 +--
|
|
|
3c6e85 |
drivers/scsi/qla2xxx/qla_mbx.c | 16 +++-
|
|
|
3c6e85 |
drivers/scsi/qla2xxx/qla_mr.c | 39 ++++-----
|
|
|
3c6e85 |
drivers/scsi/qla2xxx/qla_os.c | 2 +-
|
|
|
3c6e85 |
drivers/scsi/qla2xxx/qla_sup.c | 41 ++++-----
|
|
|
3c6e85 |
drivers/scsi/qla2xxx/qla_tmpl.c | 184 ++++++++++++++++++++++++----------------
|
|
|
3c6e85 |
drivers/scsi/qla2xxx/qla_tmpl.h | 74 ++++++++--------
|
|
|
3c6e85 |
15 files changed, 292 insertions(+), 274 deletions(-)
|
|
|
3c6e85 |
|
|
|
3c6e85 |
diff --git a/drivers/scsi/qla2xxx/qla_bsg.c b/drivers/scsi/qla2xxx/qla_bsg.c
|
|
|
3c6e85 |
index fec996cdd4a0..f7cfb36e635e 100644
|
|
|
3c6e85 |
--- a/drivers/scsi/qla2xxx/qla_bsg.c
|
|
|
3c6e85 |
+++ b/drivers/scsi/qla2xxx/qla_bsg.c
|
|
|
3c6e85 |
@@ -1919,7 +1919,7 @@ qlafx00_mgmt_cmd(struct fc_bsg_job *bsg_job)
|
|
|
3c6e85 |
|
|
|
3c6e85 |
/* Dump the vendor information */
|
|
|
3c6e85 |
ql_dump_buffer(ql_dbg_user + ql_dbg_verbose , vha, 0x70cf,
|
|
|
3c6e85 |
- (uint8_t *)piocb_rqst, sizeof(struct qla_mt_iocb_rqst_fx00));
|
|
|
3c6e85 |
+ piocb_rqst, sizeof(*piocb_rqst));
|
|
|
3c6e85 |
|
|
|
3c6e85 |
if (!vha->flags.online) {
|
|
|
3c6e85 |
ql_log(ql_log_warn, vha, 0x70d0,
|
|
|
3c6e85 |
@@ -2269,8 +2269,8 @@ qla2x00_get_priv_stats(struct fc_bsg_job *bsg_job)
|
|
|
3c6e85 |
rval = qla24xx_get_isp_stats(base_vha, stats, stats_dma, options);
|
|
|
3c6e85 |
|
|
|
3c6e85 |
if (rval == QLA_SUCCESS) {
|
|
|
3c6e85 |
- ql_dump_buffer(ql_dbg_user + ql_dbg_verbose, vha, 0x70e3,
|
|
|
3c6e85 |
- (uint8_t *)stats, sizeof(*stats));
|
|
|
3c6e85 |
+ ql_dump_buffer(ql_dbg_user + ql_dbg_verbose, vha, 0x70e5,
|
|
|
3c6e85 |
+ stats, sizeof(*stats));
|
|
|
3c6e85 |
sg_copy_from_buffer(bsg_job->reply_payload.sg_list,
|
|
|
3c6e85 |
bsg_job->reply_payload.sg_cnt, stats, sizeof(*stats));
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
diff --git a/drivers/scsi/qla2xxx/qla_dbg.c b/drivers/scsi/qla2xxx/qla_dbg.c
|
|
|
3c6e85 |
index dd443940a019..ae202fa427c5 100644
|
|
|
3c6e85 |
--- a/drivers/scsi/qla2xxx/qla_dbg.c
|
|
|
3c6e85 |
+++ b/drivers/scsi/qla2xxx/qla_dbg.c
|
|
|
3c6e85 |
@@ -2521,7 +2521,7 @@ qla83xx_fw_dump_failed:
|
|
|
3c6e85 |
/****************************************************************************/
|
|
|
3c6e85 |
|
|
|
3c6e85 |
static inline int
|
|
|
3c6e85 |
-ql_mask_match(uint32_t level)
|
|
|
3c6e85 |
+ql_mask_match(uint level)
|
|
|
3c6e85 |
{
|
|
|
3c6e85 |
return (level & ql2xextended_error_logging) == level;
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
@@ -2540,7 +2540,7 @@ ql_mask_match(uint32_t level)
|
|
|
3c6e85 |
* msg: The message to be displayed.
|
|
|
3c6e85 |
*/
|
|
|
3c6e85 |
void
|
|
|
3c6e85 |
-ql_dbg(uint32_t level, scsi_qla_host_t *vha, int32_t id, const char *fmt, ...)
|
|
|
3c6e85 |
+ql_dbg(uint level, scsi_qla_host_t *vha, uint id, const char *fmt, ...)
|
|
|
3c6e85 |
{
|
|
|
3c6e85 |
va_list va;
|
|
|
3c6e85 |
struct va_format vaf;
|
|
|
3c6e85 |
@@ -2583,8 +2583,7 @@ ql_dbg(uint32_t level, scsi_qla_host_t *vha, int32_t id, const char *fmt, ...)
|
|
|
3c6e85 |
* msg: The message to be displayed.
|
|
|
3c6e85 |
*/
|
|
|
3c6e85 |
void
|
|
|
3c6e85 |
-ql_dbg_pci(uint32_t level, struct pci_dev *pdev, int32_t id,
|
|
|
3c6e85 |
- const char *fmt, ...)
|
|
|
3c6e85 |
+ql_dbg_pci(uint level, struct pci_dev *pdev, uint id, const char *fmt, ...)
|
|
|
3c6e85 |
{
|
|
|
3c6e85 |
va_list va;
|
|
|
3c6e85 |
struct va_format vaf;
|
|
|
3c6e85 |
@@ -2620,7 +2619,7 @@ ql_dbg_pci(uint32_t level, struct pci_dev *pdev, int32_t id,
|
|
|
3c6e85 |
* msg: The message to be displayed.
|
|
|
3c6e85 |
*/
|
|
|
3c6e85 |
void
|
|
|
3c6e85 |
-ql_log(uint32_t level, scsi_qla_host_t *vha, int32_t id, const char *fmt, ...)
|
|
|
3c6e85 |
+ql_log(uint level, scsi_qla_host_t *vha, uint id, const char *fmt, ...)
|
|
|
3c6e85 |
{
|
|
|
3c6e85 |
va_list va;
|
|
|
3c6e85 |
struct va_format vaf;
|
|
|
3c6e85 |
@@ -2678,8 +2677,7 @@ ql_log(uint32_t level, scsi_qla_host_t *vha, int32_t id, const char *fmt, ...)
|
|
|
3c6e85 |
* msg: The message to be displayed.
|
|
|
3c6e85 |
*/
|
|
|
3c6e85 |
void
|
|
|
3c6e85 |
-ql_log_pci(uint32_t level, struct pci_dev *pdev, int32_t id,
|
|
|
3c6e85 |
- const char *fmt, ...)
|
|
|
3c6e85 |
+ql_log_pci(uint level, struct pci_dev *pdev, uint id, const char *fmt, ...)
|
|
|
3c6e85 |
{
|
|
|
3c6e85 |
va_list va;
|
|
|
3c6e85 |
struct va_format vaf;
|
|
|
3c6e85 |
@@ -2719,7 +2717,7 @@ ql_log_pci(uint32_t level, struct pci_dev *pdev, int32_t id,
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
|
|
|
3c6e85 |
void
|
|
|
3c6e85 |
-ql_dump_regs(uint32_t level, scsi_qla_host_t *vha, int32_t id)
|
|
|
3c6e85 |
+ql_dump_regs(uint level, scsi_qla_host_t *vha, uint id)
|
|
|
3c6e85 |
{
|
|
|
3c6e85 |
int i;
|
|
|
3c6e85 |
struct qla_hw_data *ha = vha->hw;
|
|
|
3c6e85 |
@@ -2741,13 +2739,12 @@ ql_dump_regs(uint32_t level, scsi_qla_host_t *vha, int32_t id)
|
|
|
3c6e85 |
ql_dbg(level, vha, id, "Mailbox registers:\n");
|
|
|
3c6e85 |
for (i = 0; i < 6; i++, mbx_reg++)
|
|
|
3c6e85 |
ql_dbg(level, vha, id,
|
|
|
3c6e85 |
- "mbox[%d] 0x%04x\n", i, RD_REG_WORD(mbx_reg));
|
|
|
3c6e85 |
+ "mbox[%d] %#04x\n", i, RD_REG_WORD(mbx_reg));
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
|
|
|
3c6e85 |
|
|
|
3c6e85 |
void
|
|
|
3c6e85 |
-ql_dump_buffer(uint32_t level, scsi_qla_host_t *vha, int32_t id,
|
|
|
3c6e85 |
- uint8_t *buf, uint size)
|
|
|
3c6e85 |
+ql_dump_buffer(uint level, scsi_qla_host_t *vha, uint id, void *buf, uint size)
|
|
|
3c6e85 |
{
|
|
|
3c6e85 |
uint cnt;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
diff --git a/drivers/scsi/qla2xxx/qla_dbg.h b/drivers/scsi/qla2xxx/qla_dbg.h
|
|
|
3c6e85 |
index 8877aa97d829..bb01b680ce9f 100644
|
|
|
3c6e85 |
--- a/drivers/scsi/qla2xxx/qla_dbg.h
|
|
|
3c6e85 |
+++ b/drivers/scsi/qla2xxx/qla_dbg.h
|
|
|
3c6e85 |
@@ -318,20 +318,20 @@ struct qla2xxx_fw_dump {
|
|
|
3c6e85 |
* as compared to other log levels.
|
|
|
3c6e85 |
*/
|
|
|
3c6e85 |
|
|
|
3c6e85 |
-extern int ql_errlev;
|
|
|
3c6e85 |
+extern uint ql_errlev;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
void __attribute__((format (printf, 4, 5)))
|
|
|
3c6e85 |
-ql_dbg(uint32_t, scsi_qla_host_t *vha, int32_t, const char *fmt, ...);
|
|
|
3c6e85 |
+ql_dbg(uint, scsi_qla_host_t *vha, uint, const char *fmt, ...);
|
|
|
3c6e85 |
void __attribute__((format (printf, 4, 5)))
|
|
|
3c6e85 |
-ql_dbg_pci(uint32_t, struct pci_dev *pdev, int32_t, const char *fmt, ...);
|
|
|
3c6e85 |
+ql_dbg_pci(uint, struct pci_dev *pdev, uint, const char *fmt, ...);
|
|
|
3c6e85 |
void __attribute__((format (printf, 4, 5)))
|
|
|
3c6e85 |
ql_dbg_qp(uint32_t, struct qla_qpair *, int32_t, const char *fmt, ...);
|
|
|
3c6e85 |
|
|
|
3c6e85 |
|
|
|
3c6e85 |
void __attribute__((format (printf, 4, 5)))
|
|
|
3c6e85 |
-ql_log(uint32_t, scsi_qla_host_t *vha, int32_t, const char *fmt, ...);
|
|
|
3c6e85 |
+ql_log(uint, scsi_qla_host_t *vha, uint, const char *fmt, ...);
|
|
|
3c6e85 |
void __attribute__((format (printf, 4, 5)))
|
|
|
3c6e85 |
-ql_log_pci(uint32_t, struct pci_dev *pdev, int32_t, const char *fmt, ...);
|
|
|
3c6e85 |
+ql_log_pci(uint, struct pci_dev *pdev, uint, const char *fmt, ...);
|
|
|
3c6e85 |
|
|
|
3c6e85 |
void __attribute__((format (printf, 4, 5)))
|
|
|
3c6e85 |
ql_log_qp(uint32_t, struct qla_qpair *, int32_t, const char *fmt, ...);
|
|
|
3c6e85 |
diff --git a/drivers/scsi/qla2xxx/qla_def.h b/drivers/scsi/qla2xxx/qla_def.h
|
|
|
3c6e85 |
index 1730931cd6b2..15b146db7f71 100644
|
|
|
3c6e85 |
--- a/drivers/scsi/qla2xxx/qla_def.h
|
|
|
3c6e85 |
+++ b/drivers/scsi/qla2xxx/qla_def.h
|
|
|
3c6e85 |
@@ -4472,7 +4472,7 @@ typedef struct scsi_qla_host {
|
|
|
3c6e85 |
|
|
|
3c6e85 |
struct qla27xx_image_status {
|
|
|
3c6e85 |
uint8_t image_status_mask;
|
|
|
3c6e85 |
- uint16_t generation_number;
|
|
|
3c6e85 |
+ uint16_t generation;
|
|
|
3c6e85 |
uint8_t reserved[3];
|
|
|
3c6e85 |
uint8_t ver_minor;
|
|
|
3c6e85 |
uint8_t ver_major;
|
|
|
3c6e85 |
diff --git a/drivers/scsi/qla2xxx/qla_fw.h b/drivers/scsi/qla2xxx/qla_fw.h
|
|
|
3c6e85 |
index 62b37775a7b8..b9b1aaaff906 100644
|
|
|
3c6e85 |
--- a/drivers/scsi/qla2xxx/qla_fw.h
|
|
|
3c6e85 |
+++ b/drivers/scsi/qla2xxx/qla_fw.h
|
|
|
3c6e85 |
@@ -1516,7 +1516,9 @@ struct qla_flt_header {
|
|
|
3c6e85 |
#define FLT_REG_VPD_SEC_27XX_3 0xDA
|
|
|
3c6e85 |
|
|
|
3c6e85 |
struct qla_flt_region {
|
|
|
3c6e85 |
- uint32_t code;
|
|
|
3c6e85 |
+ uint16_t code;
|
|
|
3c6e85 |
+ uint8_t attribute;
|
|
|
3c6e85 |
+ uint8_t reserved;
|
|
|
3c6e85 |
uint32_t size;
|
|
|
3c6e85 |
uint32_t start;
|
|
|
3c6e85 |
uint32_t end;
|
|
|
3c6e85 |
diff --git a/drivers/scsi/qla2xxx/qla_gbl.h b/drivers/scsi/qla2xxx/qla_gbl.h
|
|
|
3c6e85 |
index aede9e5a31f7..3e4424ecd6ec 100644
|
|
|
3c6e85 |
--- a/drivers/scsi/qla2xxx/qla_gbl.h
|
|
|
3c6e85 |
+++ b/drivers/scsi/qla2xxx/qla_gbl.h
|
|
|
3c6e85 |
@@ -118,6 +118,7 @@ int qla_post_iidma_work(struct scsi_qla_host *vha, fc_port_t *fcport);
|
|
|
3c6e85 |
void qla_do_iidma_work(struct scsi_qla_host *vha, fc_port_t *fcport);
|
|
|
3c6e85 |
int qla2x00_reserve_mgmt_server_loop_id(scsi_qla_host_t *);
|
|
|
3c6e85 |
void qla_rscn_replay(fc_port_t *fcport);
|
|
|
3c6e85 |
+extern bool qla24xx_risc_firmware_invalid(uint32_t *);
|
|
|
3c6e85 |
|
|
|
3c6e85 |
/*
|
|
|
3c6e85 |
* Global Data in qla_os.c source file.
|
|
|
3c6e85 |
@@ -613,14 +614,9 @@ extern ulong qla27xx_fwdt_calculate_dump_size(struct scsi_qla_host *);
|
|
|
3c6e85 |
extern int qla27xx_fwdt_template_valid(void *);
|
|
|
3c6e85 |
extern ulong qla27xx_fwdt_template_size(void *);
|
|
|
3c6e85 |
|
|
|
3c6e85 |
-extern void qla2x00_dump_regs(scsi_qla_host_t *);
|
|
|
3c6e85 |
-extern void qla2x00_dump_buffer(uint8_t *, uint32_t);
|
|
|
3c6e85 |
-extern void qla2x00_dump_buffer_zipped(uint8_t *, uint32_t);
|
|
|
3c6e85 |
-extern void ql_dump_regs(uint32_t, scsi_qla_host_t *, int32_t);
|
|
|
3c6e85 |
-extern void ql_dump_buffer(uint32_t, scsi_qla_host_t *, int32_t,
|
|
|
3c6e85 |
- uint8_t *, uint32_t);
|
|
|
3c6e85 |
extern void qla2xxx_dump_post_process(scsi_qla_host_t *, int);
|
|
|
3c6e85 |
-
|
|
|
3c6e85 |
+extern void ql_dump_regs(uint, scsi_qla_host_t *, uint);
|
|
|
3c6e85 |
+extern void ql_dump_buffer(uint, scsi_qla_host_t *, uint, void *, uint);
|
|
|
3c6e85 |
/*
|
|
|
3c6e85 |
* Global Function Prototypes in qla_gs.c source file.
|
|
|
3c6e85 |
*/
|
|
|
3c6e85 |
diff --git a/drivers/scsi/qla2xxx/qla_gs.c b/drivers/scsi/qla2xxx/qla_gs.c
|
|
|
3c6e85 |
index adf853ead5b4..4864850d0844 100644
|
|
|
3c6e85 |
--- a/drivers/scsi/qla2xxx/qla_gs.c
|
|
|
3c6e85 |
+++ b/drivers/scsi/qla2xxx/qla_gs.c
|
|
|
3c6e85 |
@@ -152,8 +152,8 @@ qla2x00_chk_ms_status(scsi_qla_host_t *vha, ms_iocb_entry_t *ms_pkt,
|
|
|
3c6e85 |
vha->d_id.b.area, vha->d_id.b.al_pa,
|
|
|
3c6e85 |
comp_status, ct_rsp->header.response);
|
|
|
3c6e85 |
ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha,
|
|
|
3c6e85 |
- 0x2078, (uint8_t *)&ct_rsp->header,
|
|
|
3c6e85 |
- sizeof(struct ct_rsp_hdr));
|
|
|
3c6e85 |
+ 0x2078, ct_rsp,
|
|
|
3c6e85 |
+ offsetof(typeof(*ct_rsp), rsp));
|
|
|
3c6e85 |
rval = QLA_INVALID_COMMAND;
|
|
|
3c6e85 |
} else
|
|
|
3c6e85 |
rval = QLA_SUCCESS;
|
|
|
3c6e85 |
diff --git a/drivers/scsi/qla2xxx/qla_init.c b/drivers/scsi/qla2xxx/qla_init.c
|
|
|
3c6e85 |
index a2bf199b35d9..05c8a6befa4b 100644
|
|
|
3c6e85 |
--- a/drivers/scsi/qla2xxx/qla_init.c
|
|
|
3c6e85 |
+++ b/drivers/scsi/qla2xxx/qla_init.c
|
|
|
3c6e85 |
@@ -3648,8 +3648,7 @@ qla2x00_update_fw_options(scsi_qla_host_t *vha)
|
|
|
3c6e85 |
ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115,
|
|
|
3c6e85 |
"Serial link options.\n");
|
|
|
3c6e85 |
ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109,
|
|
|
3c6e85 |
- (uint8_t *)&ha->fw_seriallink_options,
|
|
|
3c6e85 |
- sizeof(ha->fw_seriallink_options));
|
|
|
3c6e85 |
+ ha->fw_seriallink_options, sizeof(ha->fw_seriallink_options));
|
|
|
3c6e85 |
|
|
|
3c6e85 |
ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
|
|
|
3c6e85 |
if (ha->fw_seriallink_options[3] & BIT_2) {
|
|
|
3c6e85 |
@@ -4376,7 +4375,7 @@ qla2x00_nvram_config(scsi_qla_host_t *vha)
|
|
|
3c6e85 |
rval = QLA_SUCCESS;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
/* Determine NVRAM starting address. */
|
|
|
3c6e85 |
- ha->nvram_size = sizeof(nvram_t);
|
|
|
3c6e85 |
+ ha->nvram_size = sizeof(*nv);
|
|
|
3c6e85 |
ha->nvram_base = 0;
|
|
|
3c6e85 |
if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha))
|
|
|
3c6e85 |
if ((RD_REG_WORD(®->ctrl_status) >> 14) == 1)
|
|
|
3c6e85 |
@@ -4390,7 +4389,7 @@ qla2x00_nvram_config(scsi_qla_host_t *vha)
|
|
|
3c6e85 |
ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f,
|
|
|
3c6e85 |
"Contents of NVRAM.\n");
|
|
|
3c6e85 |
ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110,
|
|
|
3c6e85 |
- (uint8_t *)nv, ha->nvram_size);
|
|
|
3c6e85 |
+ nv, ha->nvram_size);
|
|
|
3c6e85 |
|
|
|
3c6e85 |
/* Bad NVRAM data, set defaults parameters. */
|
|
|
3c6e85 |
if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' ||
|
|
|
3c6e85 |
@@ -4962,8 +4961,7 @@ qla2x00_configure_local_loop(scsi_qla_host_t *vha)
|
|
|
3c6e85 |
ql_dbg(ql_dbg_disc, vha, 0x2011,
|
|
|
3c6e85 |
"Entries in ID list (%d).\n", entries);
|
|
|
3c6e85 |
ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075,
|
|
|
3c6e85 |
- (uint8_t *)ha->gid_list,
|
|
|
3c6e85 |
- entries * sizeof(struct gid_list_info));
|
|
|
3c6e85 |
+ ha->gid_list, entries * sizeof(*ha->gid_list));
|
|
|
3c6e85 |
|
|
|
3c6e85 |
if (entries == 0) {
|
|
|
3c6e85 |
spin_lock_irqsave(&vha->work_lock, flags);
|
|
|
3c6e85 |
@@ -6981,7 +6979,7 @@ qla24xx_nvram_config(scsi_qla_host_t *vha)
|
|
|
3c6e85 |
ha->vpd_base = FA_NVRAM_VPD1_ADDR;
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
|
|
|
3c6e85 |
- ha->nvram_size = sizeof(struct nvram_24xx);
|
|
|
3c6e85 |
+ ha->nvram_size = sizeof(*nv);
|
|
|
3c6e85 |
ha->vpd_size = FA_NVRAM_VPD_SIZE;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
/* Get VPD data into cache */
|
|
|
3c6e85 |
@@ -6999,7 +6997,7 @@ qla24xx_nvram_config(scsi_qla_host_t *vha)
|
|
|
3c6e85 |
ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a,
|
|
|
3c6e85 |
"Contents of NVRAM\n");
|
|
|
3c6e85 |
ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d,
|
|
|
3c6e85 |
- (uint8_t *)nv, ha->nvram_size);
|
|
|
3c6e85 |
+ nv, ha->nvram_size);
|
|
|
3c6e85 |
|
|
|
3c6e85 |
/* Bad NVRAM data, set defaults parameters. */
|
|
|
3c6e85 |
if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
|
|
|
3c6e85 |
@@ -7009,6 +7007,7 @@ qla24xx_nvram_config(scsi_qla_host_t *vha)
|
|
|
3c6e85 |
ql_log(ql_log_warn, vha, 0x006b,
|
|
|
3c6e85 |
"Inconsistent NVRAM detected: checksum=0x%x id=%c "
|
|
|
3c6e85 |
"version=0x%x.\n", chksum, nv->id[0], nv->nvram_version);
|
|
|
3c6e85 |
+ ql_dump_buffer(ql_dbg_init, vha, 0x006b, nv, 32);
|
|
|
3c6e85 |
ql_log(ql_log_warn, vha, 0x006c,
|
|
|
3c6e85 |
"Falling back to functioning (yet invalid -- WWPN) "
|
|
|
3c6e85 |
"defaults.\n");
|
|
|
3c6e85 |
@@ -7220,18 +7219,16 @@ qla24xx_nvram_config(scsi_qla_host_t *vha)
|
|
|
3c6e85 |
uint8_t qla27xx_find_valid_image(struct scsi_qla_host *vha)
|
|
|
3c6e85 |
{
|
|
|
3c6e85 |
struct qla27xx_image_status pri_image_status, sec_image_status;
|
|
|
3c6e85 |
- uint8_t valid_pri_image, valid_sec_image;
|
|
|
3c6e85 |
+ bool valid_pri_image = true, valid_sec_image = true;
|
|
|
3c6e85 |
uint32_t *wptr;
|
|
|
3c6e85 |
- uint32_t cnt, chksum, size;
|
|
|
3c6e85 |
+ uint chksum, cnt, size = sizeof(pri_image_status) / sizeof(*wptr);
|
|
|
3c6e85 |
struct qla_hw_data *ha = vha->hw;
|
|
|
3c6e85 |
uint32_t signature;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
- valid_pri_image = valid_sec_image = 1;
|
|
|
3c6e85 |
ha->active_image = 0;
|
|
|
3c6e85 |
- size = sizeof(struct qla27xx_image_status) / sizeof(uint32_t);
|
|
|
3c6e85 |
|
|
|
3c6e85 |
if (!ha->flt_region_img_status_pri) {
|
|
|
3c6e85 |
- valid_pri_image = 0;
|
|
|
3c6e85 |
+ valid_pri_image = false;
|
|
|
3c6e85 |
goto check_sec_image;
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
|
|
|
3c6e85 |
@@ -7242,9 +7239,9 @@ uint8_t qla27xx_find_valid_image(struct scsi_qla_host *vha)
|
|
|
3c6e85 |
if (signature != QLA27XX_IMG_STATUS_SIGN &&
|
|
|
3c6e85 |
signature != QLA28XX_IMG_STATUS_SIGN) {
|
|
|
3c6e85 |
ql_dbg(ql_dbg_init, vha, 0x018b,
|
|
|
3c6e85 |
- "Primary image signature (0x%x) not valid\n",
|
|
|
3c6e85 |
- pri_image_status.signature);
|
|
|
3c6e85 |
- valid_pri_image = 0;
|
|
|
3c6e85 |
+ "Primary image signature (%#x) not valid\n",
|
|
|
3c6e85 |
+ le32_to_cpu(pri_image_status.signature));
|
|
|
3c6e85 |
+ valid_pri_image = false;
|
|
|
3c6e85 |
goto check_sec_image;
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
|
|
|
3c6e85 |
@@ -7256,14 +7253,13 @@ uint8_t qla27xx_find_valid_image(struct scsi_qla_host *vha)
|
|
|
3c6e85 |
|
|
|
3c6e85 |
if (chksum) {
|
|
|
3c6e85 |
ql_dbg(ql_dbg_init, vha, 0x018c,
|
|
|
3c6e85 |
- "Checksum validation failed for primary image (0x%x)\n",
|
|
|
3c6e85 |
- chksum);
|
|
|
3c6e85 |
- valid_pri_image = 0;
|
|
|
3c6e85 |
+ "Primary image checksum failed (%#x)\n", chksum);
|
|
|
3c6e85 |
+ valid_pri_image = false;
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
|
|
|
3c6e85 |
check_sec_image:
|
|
|
3c6e85 |
if (!ha->flt_region_img_status_sec) {
|
|
|
3c6e85 |
- valid_sec_image = 0;
|
|
|
3c6e85 |
+ valid_sec_image = false;
|
|
|
3c6e85 |
goto check_valid_image;
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
|
|
|
3c6e85 |
@@ -7274,9 +7270,9 @@ check_sec_image:
|
|
|
3c6e85 |
if (signature != QLA27XX_IMG_STATUS_SIGN &&
|
|
|
3c6e85 |
signature != QLA28XX_IMG_STATUS_SIGN) {
|
|
|
3c6e85 |
ql_dbg(ql_dbg_init, vha, 0x018d,
|
|
|
3c6e85 |
- "Secondary image signature(0x%x) not valid\n",
|
|
|
3c6e85 |
- sec_image_status.signature);
|
|
|
3c6e85 |
- valid_sec_image = 0;
|
|
|
3c6e85 |
+ "Secondary image signature (%#x) not valid\n",
|
|
|
3c6e85 |
+ le32_to_cpu(sec_image_status.signature));
|
|
|
3c6e85 |
+ valid_sec_image = false;
|
|
|
3c6e85 |
goto check_valid_image;
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
|
|
|
3c6e85 |
@@ -7286,19 +7282,20 @@ check_sec_image:
|
|
|
3c6e85 |
chksum += le32_to_cpu(*wptr);
|
|
|
3c6e85 |
if (chksum) {
|
|
|
3c6e85 |
ql_dbg(ql_dbg_init, vha, 0x018e,
|
|
|
3c6e85 |
- "Checksum validation failed for secondary image (0x%x)\n",
|
|
|
3c6e85 |
- chksum);
|
|
|
3c6e85 |
- valid_sec_image = 0;
|
|
|
3c6e85 |
+ "Secondary image checksum failed (%#x)\n", chksum);
|
|
|
3c6e85 |
+ valid_sec_image = false;
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
|
|
|
3c6e85 |
check_valid_image:
|
|
|
3c6e85 |
- if (valid_pri_image && (pri_image_status.image_status_mask & 0x1))
|
|
|
3c6e85 |
+ if (valid_pri_image && (pri_image_status.image_status_mask & 1))
|
|
|
3c6e85 |
ha->active_image = QLA27XX_PRIMARY_IMAGE;
|
|
|
3c6e85 |
- if (valid_sec_image && (sec_image_status.image_status_mask & 0x1)) {
|
|
|
3c6e85 |
+
|
|
|
3c6e85 |
+ if (valid_sec_image && (sec_image_status.image_status_mask & 1)) {
|
|
|
3c6e85 |
if (!ha->active_image ||
|
|
|
3c6e85 |
- pri_image_status.generation_number <
|
|
|
3c6e85 |
- sec_image_status.generation_number)
|
|
|
3c6e85 |
+ le16_to_cpu(pri_image_status.generation) <
|
|
|
3c6e85 |
+ le16_to_cpu(sec_image_status.generation)) {
|
|
|
3c6e85 |
ha->active_image = QLA27XX_SECONDARY_IMAGE;
|
|
|
3c6e85 |
+ }
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
|
|
|
3c6e85 |
ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x018f, "%s image\n",
|
|
|
3c6e85 |
@@ -7310,6 +7307,13 @@ check_valid_image:
|
|
|
3c6e85 |
return ha->active_image;
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
|
|
|
3c6e85 |
+bool qla24xx_risc_firmware_invalid(uint32_t *dword)
|
|
|
3c6e85 |
+{
|
|
|
3c6e85 |
+ return
|
|
|
3c6e85 |
+ !(dword[4] | dword[5] | dword[6] | dword[7]) ||
|
|
|
3c6e85 |
+ !(~dword[4] | ~dword[5] | ~dword[6] | ~dword[7]);
|
|
|
3c6e85 |
+}
|
|
|
3c6e85 |
+
|
|
|
3c6e85 |
static int
|
|
|
3c6e85 |
qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr,
|
|
|
3c6e85 |
uint32_t faddr)
|
|
|
3c6e85 |
@@ -7326,24 +7330,9 @@ qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr,
|
|
|
3c6e85 |
ql_dbg(ql_dbg_init, vha, 0x008b,
|
|
|
3c6e85 |
"FW: Loading firmware from flash (%x).\n", faddr);
|
|
|
3c6e85 |
|
|
|
3c6e85 |
- rval = QLA_SUCCESS;
|
|
|
3c6e85 |
-
|
|
|
3c6e85 |
- segments = FA_RISC_CODE_SEGMENTS;
|
|
|
3c6e85 |
- dcode = (uint32_t *)req->ring;
|
|
|
3c6e85 |
- *srisc_addr = 0;
|
|
|
3c6e85 |
-
|
|
|
3c6e85 |
- if ((IS_QLA27XX(ha) || IS_QLA28XX(ha)) &&
|
|
|
3c6e85 |
- qla27xx_find_valid_image(vha) == QLA27XX_SECONDARY_IMAGE)
|
|
|
3c6e85 |
- faddr = ha->flt_region_fw_sec;
|
|
|
3c6e85 |
-
|
|
|
3c6e85 |
- /* Validate firmware image by checking version. */
|
|
|
3c6e85 |
- qla24xx_read_flash_data(vha, dcode, faddr + 4, 4);
|
|
|
3c6e85 |
- for (i = 0; i < 4; i++)
|
|
|
3c6e85 |
- dcode[i] = be32_to_cpu(dcode[i]);
|
|
|
3c6e85 |
- if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
|
|
|
3c6e85 |
- dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
|
|
|
3c6e85 |
- (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
|
|
|
3c6e85 |
- dcode[3] == 0)) {
|
|
|
3c6e85 |
+ dcode = (void *)req->ring;
|
|
|
3c6e85 |
+ qla24xx_read_flash_data(vha, dcode, faddr, 8);
|
|
|
3c6e85 |
+ if (qla24xx_risc_firmware_invalid(dcode)) {
|
|
|
3c6e85 |
ql_log(ql_log_fatal, vha, 0x008c,
|
|
|
3c6e85 |
"Unable to verify the integrity of flash firmware "
|
|
|
3c6e85 |
"image.\n");
|
|
|
3c6e85 |
@@ -7568,7 +7557,7 @@ qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr)
|
|
|
3c6e85 |
uint32_t risc_size;
|
|
|
3c6e85 |
uint32_t i;
|
|
|
3c6e85 |
struct fw_blob *blob;
|
|
|
3c6e85 |
- const uint32_t *fwcode;
|
|
|
3c6e85 |
+ uint32_t *fwcode;
|
|
|
3c6e85 |
uint32_t fwclen;
|
|
|
3c6e85 |
struct qla_hw_data *ha = vha->hw;
|
|
|
3c6e85 |
struct req_que *req = ha->req_q_map[0];
|
|
|
3c6e85 |
@@ -7585,19 +7574,9 @@ qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr)
|
|
|
3c6e85 |
return QLA_FUNCTION_FAILED;
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
|
|
|
3c6e85 |
- ql_dbg(ql_dbg_init, vha, 0x0092,
|
|
|
3c6e85 |
- "FW: Loading via request-firmware.\n");
|
|
|
3c6e85 |
-
|
|
|
3c6e85 |
- rval = QLA_SUCCESS;
|
|
|
3c6e85 |
-
|
|
|
3c6e85 |
- segments = FA_RISC_CODE_SEGMENTS;
|
|
|
3c6e85 |
- dcode = (uint32_t *)req->ring;
|
|
|
3c6e85 |
- *srisc_addr = 0;
|
|
|
3c6e85 |
- fwcode = (uint32_t *)blob->fw->data;
|
|
|
3c6e85 |
- fwclen = 0;
|
|
|
3c6e85 |
-
|
|
|
3c6e85 |
- /* Validate firmware image by checking version. */
|
|
|
3c6e85 |
- if (blob->fw->size < 8 * sizeof(uint32_t)) {
|
|
|
3c6e85 |
+ fwcode = (void *)blob->fw->data;
|
|
|
3c6e85 |
+ dcode = fwcode;
|
|
|
3c6e85 |
+ if (qla24xx_risc_firmware_invalid(dcode)) {
|
|
|
3c6e85 |
ql_log(ql_log_fatal, vha, 0x0093,
|
|
|
3c6e85 |
"Unable to verify integrity of firmware image (%Zd).\n",
|
|
|
3c6e85 |
blob->fw->size);
|
|
|
3c6e85 |
@@ -7754,28 +7733,43 @@ qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
|
|
|
3c6e85 |
if (ql2xfwloadbin == 2)
|
|
|
3c6e85 |
goto try_blob_fw;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
- /*
|
|
|
3c6e85 |
- * FW Load priority:
|
|
|
3c6e85 |
+ /* FW Load priority:
|
|
|
3c6e85 |
* 1) Firmware residing in flash.
|
|
|
3c6e85 |
* 2) Firmware via request-firmware interface (.bin file).
|
|
|
3c6e85 |
- * 3) Golden-Firmware residing in flash -- limited operation.
|
|
|
3c6e85 |
+ * 3) Golden-Firmware residing in flash -- (limited operation).
|
|
|
3c6e85 |
*/
|
|
|
3c6e85 |
+
|
|
|
3c6e85 |
+ if (!IS_QLA27XX(ha) || !IS_QLA28XX(ha))
|
|
|
3c6e85 |
+ goto try_primary_fw;
|
|
|
3c6e85 |
+
|
|
|
3c6e85 |
+ if (qla27xx_find_valid_image(vha) != QLA27XX_SECONDARY_IMAGE)
|
|
|
3c6e85 |
+ goto try_primary_fw;
|
|
|
3c6e85 |
+
|
|
|
3c6e85 |
+ ql_dbg(ql_dbg_init, vha, 0x008b,
|
|
|
3c6e85 |
+ "Loading secondary firmware image.\n");
|
|
|
3c6e85 |
+ rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw_sec);
|
|
|
3c6e85 |
+ if (!rval)
|
|
|
3c6e85 |
+ return rval;
|
|
|
3c6e85 |
+
|
|
|
3c6e85 |
+try_primary_fw:
|
|
|
3c6e85 |
+ ql_dbg(ql_dbg_init, vha, 0x008b,
|
|
|
3c6e85 |
+ "Loading primary firmware image.\n");
|
|
|
3c6e85 |
rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw);
|
|
|
3c6e85 |
- if (rval == QLA_SUCCESS)
|
|
|
3c6e85 |
+ if (!rval)
|
|
|
3c6e85 |
return rval;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
try_blob_fw:
|
|
|
3c6e85 |
rval = qla24xx_load_risc_blob(vha, srisc_addr);
|
|
|
3c6e85 |
- if (rval == QLA_SUCCESS || !ha->flt_region_gold_fw)
|
|
|
3c6e85 |
+ if (!rval || !ha->flt_region_gold_fw)
|
|
|
3c6e85 |
return rval;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
ql_log(ql_log_info, vha, 0x0099,
|
|
|
3c6e85 |
"Attempting to fallback to golden firmware.\n");
|
|
|
3c6e85 |
rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw);
|
|
|
3c6e85 |
- if (rval != QLA_SUCCESS)
|
|
|
3c6e85 |
+ if (rval)
|
|
|
3c6e85 |
return rval;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
- ql_log(ql_log_info, vha, 0x009a, "Update operational firmware.\n");
|
|
|
3c6e85 |
+ ql_log(ql_log_info, vha, 0x009a, "Need firmware flash update.\n");
|
|
|
3c6e85 |
ha->flags.running_gold_fw = 1;
|
|
|
3c6e85 |
return rval;
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
@@ -7950,7 +7944,7 @@ qla81xx_nvram_config(scsi_qla_host_t *vha)
|
|
|
3c6e85 |
nv = ha->nvram;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
/* Determine NVRAM starting address. */
|
|
|
3c6e85 |
- ha->nvram_size = sizeof(struct nvram_81xx);
|
|
|
3c6e85 |
+ ha->nvram_size = sizeof(*nv);
|
|
|
3c6e85 |
ha->vpd_size = FA_NVRAM_VPD_SIZE;
|
|
|
3c6e85 |
if (IS_P3P_TYPE(ha) || IS_QLA8031(ha))
|
|
|
3c6e85 |
ha->vpd_size = FA_VPD_SIZE_82XX;
|
|
|
3c6e85 |
@@ -7970,7 +7964,7 @@ qla81xx_nvram_config(scsi_qla_host_t *vha)
|
|
|
3c6e85 |
ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111,
|
|
|
3c6e85 |
"Contents of NVRAM:\n");
|
|
|
3c6e85 |
ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112,
|
|
|
3c6e85 |
- (uint8_t *)nv, ha->nvram_size);
|
|
|
3c6e85 |
+ nv, ha->nvram_size);
|
|
|
3c6e85 |
|
|
|
3c6e85 |
/* Bad NVRAM data, set defaults parameters. */
|
|
|
3c6e85 |
if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
|
|
|
3c6e85 |
@@ -7981,6 +7975,7 @@ qla81xx_nvram_config(scsi_qla_host_t *vha)
|
|
|
3c6e85 |
"Inconsistent NVRAM detected: checksum=0x%x id=%c "
|
|
|
3c6e85 |
"version=0x%x.\n", chksum, nv->id[0],
|
|
|
3c6e85 |
le16_to_cpu(nv->nvram_version));
|
|
|
3c6e85 |
+ ql_dump_buffer(ql_dbg_init, vha, 0x0073, nv, 32);
|
|
|
3c6e85 |
ql_log(ql_log_info, vha, 0x0074,
|
|
|
3c6e85 |
"Falling back to functioning (yet invalid -- WWPN) "
|
|
|
3c6e85 |
"defaults.\n");
|
|
|
3c6e85 |
@@ -8203,12 +8198,6 @@ qla81xx_nvram_config(scsi_qla_host_t *vha)
|
|
|
3c6e85 |
/* N2N: driver will initiate Login instead of FW */
|
|
|
3c6e85 |
icb->firmware_options_3 |= BIT_8;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
- if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
|
|
|
3c6e85 |
- icb->firmware_options_3 |= BIT_8;
|
|
|
3c6e85 |
- ql_dbg(ql_log_info, vha, 0x0075,
|
|
|
3c6e85 |
- "Enabling direct connection.\n");
|
|
|
3c6e85 |
- }
|
|
|
3c6e85 |
-
|
|
|
3c6e85 |
if (rval) {
|
|
|
3c6e85 |
ql_log(ql_log_warn, vha, 0x0076,
|
|
|
3c6e85 |
"NVRAM configuration failed.\n");
|
|
|
3c6e85 |
diff --git a/drivers/scsi/qla2xxx/qla_isr.c b/drivers/scsi/qla2xxx/qla_isr.c
|
|
|
3c6e85 |
index 18631ea250c0..779753d0238a 100644
|
|
|
3c6e85 |
--- a/drivers/scsi/qla2xxx/qla_isr.c
|
|
|
3c6e85 |
+++ b/drivers/scsi/qla2xxx/qla_isr.c
|
|
|
3c6e85 |
@@ -1374,7 +1374,7 @@ qla2x00_mbx_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
|
|
|
3c6e85 |
le16_to_cpu(mbx->status_flags));
|
|
|
3c6e85 |
|
|
|
3c6e85 |
ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5029,
|
|
|
3c6e85 |
- (uint8_t *)mbx, sizeof(*mbx));
|
|
|
3c6e85 |
+ mbx, sizeof(*mbx));
|
|
|
3c6e85 |
|
|
|
3c6e85 |
goto logio_done;
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
@@ -1516,7 +1516,7 @@ qla2x00_ct_entry(scsi_qla_host_t *vha, struct req_que *req,
|
|
|
3c6e85 |
bsg_job->reply->reply_payload_rcv_len = 0;
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5035,
|
|
|
3c6e85 |
- (uint8_t *)pkt, sizeof(*pkt));
|
|
|
3c6e85 |
+ pkt, sizeof(*pkt));
|
|
|
3c6e85 |
} else {
|
|
|
3c6e85 |
res = DID_OK << 16;
|
|
|
3c6e85 |
bsg_job->reply->reply_payload_rcv_len =
|
|
|
3c6e85 |
@@ -1658,7 +1658,7 @@ qla24xx_els_ct_entry(scsi_qla_host_t *vha, struct req_que *req,
|
|
|
3c6e85 |
memcpy( fw_sts_ptr, fw_status, sizeof(fw_status));
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
ql_dump_buffer(ql_dbg_user + ql_dbg_buffer, vha, 0x5056,
|
|
|
3c6e85 |
- (uint8_t *)pkt, sizeof(*pkt));
|
|
|
3c6e85 |
+ pkt, sizeof(*pkt));
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
else {
|
|
|
3c6e85 |
res = DID_OK << 16;
|
|
|
3c6e85 |
@@ -1702,7 +1702,7 @@ qla24xx_logio_entry(scsi_qla_host_t *vha, struct req_que *req,
|
|
|
3c6e85 |
fcport->d_id.b.area, fcport->d_id.b.al_pa,
|
|
|
3c6e85 |
logio->entry_status);
|
|
|
3c6e85 |
ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x504d,
|
|
|
3c6e85 |
- (uint8_t *)logio, sizeof(*logio));
|
|
|
3c6e85 |
+ logio, sizeof(*logio));
|
|
|
3c6e85 |
|
|
|
3c6e85 |
goto logio_done;
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
@@ -1848,8 +1848,8 @@ qla24xx_tm_iocb_entry(scsi_qla_host_t *vha, struct req_que *req, void *tsk)
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
|
|
|
3c6e85 |
if (iocb->u.tmf.data != QLA_SUCCESS)
|
|
|
3c6e85 |
- ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5055,
|
|
|
3c6e85 |
- (uint8_t *)sts, sizeof(*sts));
|
|
|
3c6e85 |
+ ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, sp->vha, 0x5055,
|
|
|
3c6e85 |
+ sts, sizeof(*sts));
|
|
|
3c6e85 |
|
|
|
3c6e85 |
sp->done(sp, 0);
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
diff --git a/drivers/scsi/qla2xxx/qla_mbx.c b/drivers/scsi/qla2xxx/qla_mbx.c
|
|
|
3c6e85 |
index 509fc2d78614..4fa8b2b08768 100644
|
|
|
3c6e85 |
--- a/drivers/scsi/qla2xxx/qla_mbx.c
|
|
|
3c6e85 |
+++ b/drivers/scsi/qla2xxx/qla_mbx.c
|
|
|
3c6e85 |
@@ -1831,8 +1831,18 @@ qla2x00_init_firmware(scsi_qla_host_t *vha, uint16_t size)
|
|
|
3c6e85 |
if (rval != QLA_SUCCESS) {
|
|
|
3c6e85 |
/*EMPTY*/
|
|
|
3c6e85 |
ql_dbg(ql_dbg_mbx, vha, 0x104d,
|
|
|
3c6e85 |
- "Failed=%x mb[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x,.\n",
|
|
|
3c6e85 |
+ "Failed=%x mb[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x.\n",
|
|
|
3c6e85 |
rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3]);
|
|
|
3c6e85 |
+ if (ha->init_cb) {
|
|
|
3c6e85 |
+ ql_dbg(ql_dbg_mbx, vha, 0x104d, "init_cb:\n");
|
|
|
3c6e85 |
+ ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha,
|
|
|
3c6e85 |
+ 0x0104d, ha->init_cb, sizeof(*ha->init_cb));
|
|
|
3c6e85 |
+ }
|
|
|
3c6e85 |
+ if (ha->ex_init_cb && ha->ex_init_cb->ex_version) {
|
|
|
3c6e85 |
+ ql_dbg(ql_dbg_mbx, vha, 0x104d, "ex_init_cb:\n");
|
|
|
3c6e85 |
+ ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha,
|
|
|
3c6e85 |
+ 0x0104d, ha->ex_init_cb, sizeof(*ha->ex_init_cb));
|
|
|
3c6e85 |
+ }
|
|
|
3c6e85 |
} else {
|
|
|
3c6e85 |
if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
|
|
|
3c6e85 |
if (mcp->mb[2] == 6 || mcp->mb[3] == 2)
|
|
|
3c6e85 |
@@ -4245,7 +4255,7 @@ qla84xx_verify_chip(struct scsi_qla_host *vha, uint16_t *status)
|
|
|
3c6e85 |
ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111c,
|
|
|
3c6e85 |
"Dump of Verify Request.\n");
|
|
|
3c6e85 |
ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111e,
|
|
|
3c6e85 |
- (uint8_t *)mn, sizeof(*mn));
|
|
|
3c6e85 |
+ mn, sizeof(*mn));
|
|
|
3c6e85 |
|
|
|
3c6e85 |
rval = qla2x00_issue_iocb_timeout(vha, mn, mn_dma, 0, 120);
|
|
|
3c6e85 |
if (rval != QLA_SUCCESS) {
|
|
|
3c6e85 |
@@ -4257,7 +4267,7 @@ qla84xx_verify_chip(struct scsi_qla_host *vha, uint16_t *status)
|
|
|
3c6e85 |
ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1110,
|
|
|
3c6e85 |
"Dump of Verify Response.\n");
|
|
|
3c6e85 |
ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1118,
|
|
|
3c6e85 |
- (uint8_t *)mn, sizeof(*mn));
|
|
|
3c6e85 |
+ mn, sizeof(*mn));
|
|
|
3c6e85 |
|
|
|
3c6e85 |
status[0] = le16_to_cpu(mn->p.rsp.comp_status);
|
|
|
3c6e85 |
status[1] = status[0] == CS_VCS_CHIP_FAILURE ?
|
|
|
3c6e85 |
diff --git a/drivers/scsi/qla2xxx/qla_mr.c b/drivers/scsi/qla2xxx/qla_mr.c
|
|
|
3c6e85 |
index 045b00ecc24c..527d255999cd 100644
|
|
|
3c6e85 |
--- a/drivers/scsi/qla2xxx/qla_mr.c
|
|
|
3c6e85 |
+++ b/drivers/scsi/qla2xxx/qla_mr.c
|
|
|
3c6e85 |
@@ -1136,8 +1136,8 @@ qlafx00_find_all_targets(scsi_qla_host_t *vha,
|
|
|
3c6e85 |
|
|
|
3c6e85 |
ql_dbg(ql_dbg_disc + ql_dbg_init, vha, 0x2088,
|
|
|
3c6e85 |
"Listing Target bit map...\n");
|
|
|
3c6e85 |
- ql_dump_buffer(ql_dbg_disc + ql_dbg_init, vha,
|
|
|
3c6e85 |
- 0x2089, (uint8_t *)ha->gid_list, 32);
|
|
|
3c6e85 |
+ ql_dump_buffer(ql_dbg_disc + ql_dbg_init, vha, 0x2089,
|
|
|
3c6e85 |
+ ha->gid_list, 32);
|
|
|
3c6e85 |
|
|
|
3c6e85 |
/* Allocate temporary rmtport for any new rmtports discovered. */
|
|
|
3c6e85 |
new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
|
|
|
3c6e85 |
@@ -1913,8 +1913,7 @@ qlafx00_fx_disc(scsi_qla_host_t *vha, fc_port_t *fcport, uint16_t fx_type)
|
|
|
3c6e85 |
phost_info->domainname,
|
|
|
3c6e85 |
phost_info->hostdriver);
|
|
|
3c6e85 |
ql_dump_buffer(ql_dbg_init + ql_dbg_disc, vha, 0x014d,
|
|
|
3c6e85 |
- (uint8_t *)phost_info,
|
|
|
3c6e85 |
- sizeof(struct host_system_info));
|
|
|
3c6e85 |
+ phost_info, sizeof(*phost_info));
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
|
|
|
3c6e85 |
@@ -1968,7 +1967,7 @@ qlafx00_fx_disc(scsi_qla_host_t *vha, fc_port_t *fcport, uint16_t fx_type)
|
|
|
3c6e85 |
vha->d_id.b.al_pa = pinfo->port_id[2];
|
|
|
3c6e85 |
qlafx00_update_host_attr(vha, pinfo);
|
|
|
3c6e85 |
ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0141,
|
|
|
3c6e85 |
- (uint8_t *)pinfo, 16);
|
|
|
3c6e85 |
+ pinfo, 16);
|
|
|
3c6e85 |
} else if (fx_type == FXDISC_GET_TGT_NODE_INFO) {
|
|
|
3c6e85 |
struct qlafx00_tgt_node_info *pinfo =
|
|
|
3c6e85 |
(struct qlafx00_tgt_node_info *) fdisc->u.fxiocb.rsp_addr;
|
|
|
3c6e85 |
@@ -1976,12 +1975,12 @@ qlafx00_fx_disc(scsi_qla_host_t *vha, fc_port_t *fcport, uint16_t fx_type)
|
|
|
3c6e85 |
memcpy(fcport->port_name, pinfo->tgt_node_wwpn, WWN_SIZE);
|
|
|
3c6e85 |
fcport->port_type = FCT_TARGET;
|
|
|
3c6e85 |
ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0144,
|
|
|
3c6e85 |
- (uint8_t *)pinfo, 16);
|
|
|
3c6e85 |
+ pinfo, 16);
|
|
|
3c6e85 |
} else if (fx_type == FXDISC_GET_TGT_NODE_LIST) {
|
|
|
3c6e85 |
struct qlafx00_tgt_node_info *pinfo =
|
|
|
3c6e85 |
(struct qlafx00_tgt_node_info *) fdisc->u.fxiocb.rsp_addr;
|
|
|
3c6e85 |
ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0146,
|
|
|
3c6e85 |
- (uint8_t *)pinfo, 16);
|
|
|
3c6e85 |
+ pinfo, 16);
|
|
|
3c6e85 |
memcpy(vha->hw->gid_list, pinfo, QLAFX00_TGT_NODE_LIST_SIZE);
|
|
|
3c6e85 |
} else if (fx_type == FXDISC_ABORT_IOCTL)
|
|
|
3c6e85 |
fdisc->u.fxiocb.result =
|
|
|
3c6e85 |
@@ -2248,18 +2247,16 @@ qlafx00_ioctl_iosb_entry(scsi_qla_host_t *vha, struct req_que *req,
|
|
|
3c6e85 |
fw_sts_ptr = ((uint8_t *)bsg_job->req->sense) +
|
|
|
3c6e85 |
sizeof(struct fc_bsg_reply);
|
|
|
3c6e85 |
|
|
|
3c6e85 |
- memcpy(fw_sts_ptr, (uint8_t *)&fstatus,
|
|
|
3c6e85 |
- sizeof(struct qla_mt_iocb_rsp_fx00));
|
|
|
3c6e85 |
+ memcpy(fw_sts_ptr, &fstatus, sizeof(fstatus));
|
|
|
3c6e85 |
bsg_job->reply_len = sizeof(struct fc_bsg_reply) +
|
|
|
3c6e85 |
sizeof(struct qla_mt_iocb_rsp_fx00) + sizeof(uint8_t);
|
|
|
3c6e85 |
|
|
|
3c6e85 |
ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
|
|
|
3c6e85 |
- sp->fcport->vha, 0x5080,
|
|
|
3c6e85 |
- (uint8_t *)pkt, sizeof(struct ioctl_iocb_entry_fx00));
|
|
|
3c6e85 |
+ sp->vha, 0x5080, pkt, sizeof(*pkt));
|
|
|
3c6e85 |
|
|
|
3c6e85 |
ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
|
|
|
3c6e85 |
- sp->fcport->vha, 0x5074,
|
|
|
3c6e85 |
- (uint8_t *)fw_sts_ptr, sizeof(struct qla_mt_iocb_rsp_fx00));
|
|
|
3c6e85 |
+ sp->vha, 0x5074,
|
|
|
3c6e85 |
+ fw_sts_ptr, sizeof(fstatus));
|
|
|
3c6e85 |
|
|
|
3c6e85 |
res = bsg_job->reply->result = DID_OK << 16;
|
|
|
3c6e85 |
bsg_job->reply->reply_payload_rcv_len =
|
|
|
3c6e85 |
@@ -2599,7 +2596,7 @@ qlafx00_status_cont_entry(struct rsp_que *rsp, sts_cont_entry_t *pkt)
|
|
|
3c6e85 |
|
|
|
3c6e85 |
/* Move sense data. */
|
|
|
3c6e85 |
ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x304e,
|
|
|
3c6e85 |
- (uint8_t *)pkt, sizeof(sts_cont_entry_t));
|
|
|
3c6e85 |
+ pkt, sizeof(*pkt));
|
|
|
3c6e85 |
memcpy(sense_ptr, pkt->data, sense_sz);
|
|
|
3c6e85 |
ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x304a,
|
|
|
3c6e85 |
sense_ptr, sense_sz);
|
|
|
3c6e85 |
@@ -3059,13 +3056,13 @@ qlafx00_build_scsi_iocbs(srb_t *sp, struct cmd_type_7_fx00 *cmd_pkt,
|
|
|
3c6e85 |
if (avail_dsds == 0 && cont == 1) {
|
|
|
3c6e85 |
cont = 0;
|
|
|
3c6e85 |
memcpy_toio((void __iomem *)cont_pkt, &lcont_pkt,
|
|
|
3c6e85 |
- REQUEST_ENTRY_SIZE);
|
|
|
3c6e85 |
+ sizeof(lcont_pkt));
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
if (avail_dsds != 0 && cont == 1) {
|
|
|
3c6e85 |
memcpy_toio((void __iomem *)cont_pkt, &lcont_pkt,
|
|
|
3c6e85 |
- REQUEST_ENTRY_SIZE);
|
|
|
3c6e85 |
+ sizeof(lcont_pkt));
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
|
|
|
3c6e85 |
@@ -3186,9 +3183,9 @@ qlafx00_start_scsi(srb_t *sp)
|
|
|
3c6e85 |
lcmd_pkt.entry_status = (uint8_t) rsp->id;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x302e,
|
|
|
3c6e85 |
- (uint8_t *)cmd->cmnd, cmd->cmd_len);
|
|
|
3c6e85 |
+ cmd->cmnd, cmd->cmd_len);
|
|
|
3c6e85 |
ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x3032,
|
|
|
3c6e85 |
- (uint8_t *)&lcmd_pkt, REQUEST_ENTRY_SIZE);
|
|
|
3c6e85 |
+ &lcmd_pkt, sizeof(lcmd_pkt));
|
|
|
3c6e85 |
|
|
|
3c6e85 |
memcpy_toio((void __iomem *)cmd_pkt, &lcmd_pkt, REQUEST_ENTRY_SIZE);
|
|
|
3c6e85 |
wmb();
|
|
|
3c6e85 |
@@ -3467,10 +3464,8 @@ qlafx00_fxdisc_iocb(srb_t *sp, struct fxdisc_entry_fx00 *pfxiocb)
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
|
|
|
3c6e85 |
ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
|
|
|
3c6e85 |
- sp->vha, 0x3047,
|
|
|
3c6e85 |
- (uint8_t *)&fx_iocb, sizeof(struct fxdisc_entry_fx00));
|
|
|
3c6e85 |
+ sp->vha, 0x3047, &fx_iocb, sizeof(fx_iocb));
|
|
|
3c6e85 |
|
|
|
3c6e85 |
- memcpy_toio((void __iomem *)pfxiocb, &fx_iocb,
|
|
|
3c6e85 |
- sizeof(struct fxdisc_entry_fx00));
|
|
|
3c6e85 |
+ memcpy_toio((void __iomem *)pfxiocb, &fx_iocb, sizeof(fx_iocb));
|
|
|
3c6e85 |
wmb();
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
diff --git a/drivers/scsi/qla2xxx/qla_os.c b/drivers/scsi/qla2xxx/qla_os.c
|
|
|
3c6e85 |
index 95d3ff062320..8c567a82752b 100644
|
|
|
3c6e85 |
--- a/drivers/scsi/qla2xxx/qla_os.c
|
|
|
3c6e85 |
+++ b/drivers/scsi/qla2xxx/qla_os.c
|
|
|
3c6e85 |
@@ -41,7 +41,7 @@ static struct kmem_cache *ctx_cachep;
|
|
|
3c6e85 |
/*
|
|
|
3c6e85 |
* error level for logging
|
|
|
3c6e85 |
*/
|
|
|
3c6e85 |
-int ql_errlev = ql_log_all;
|
|
|
3c6e85 |
+uint ql_errlev = ql_log_all;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
static int ql2xenableclass2;
|
|
|
3c6e85 |
module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
|
|
|
3c6e85 |
diff --git a/drivers/scsi/qla2xxx/qla_sup.c b/drivers/scsi/qla2xxx/qla_sup.c
|
|
|
3c6e85 |
index 9ce542dccdb8..a062cecb3980 100644
|
|
|
3c6e85 |
--- a/drivers/scsi/qla2xxx/qla_sup.c
|
|
|
3c6e85 |
+++ b/drivers/scsi/qla2xxx/qla_sup.c
|
|
|
3c6e85 |
@@ -619,7 +619,7 @@ qla2xxx_find_flt_start(scsi_qla_host_t *vha, uint32_t *start)
|
|
|
3c6e85 |
ql_log(ql_log_fatal, vha, 0x0045,
|
|
|
3c6e85 |
"Inconsistent FLTL detected: checksum=0x%x.\n", chksum);
|
|
|
3c6e85 |
ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010e,
|
|
|
3c6e85 |
- buf, sizeof(struct qla_flt_location));
|
|
|
3c6e85 |
+ fltl, sizeof(*fltl));
|
|
|
3c6e85 |
return QLA_FUNCTION_FAILED;
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
|
|
|
3c6e85 |
@@ -721,12 +721,12 @@ qla2xxx_get_flt_info(scsi_qla_host_t *vha, uint32_t flt_addr)
|
|
|
3c6e85 |
/* Store addresses as DWORD offsets. */
|
|
|
3c6e85 |
start = le32_to_cpu(region->start) >> 2;
|
|
|
3c6e85 |
ql_dbg(ql_dbg_init, vha, 0x0049,
|
|
|
3c6e85 |
- "FLT[%02x]: start=0x%x "
|
|
|
3c6e85 |
- "end=0x%x size=0x%x.\n", le32_to_cpu(region->code) & 0xff,
|
|
|
3c6e85 |
+ "FLT[%#x]: start=%#x end=%#x size=%#x.\n",
|
|
|
3c6e85 |
+ le16_to_cpu(region->code),
|
|
|
3c6e85 |
start, le32_to_cpu(region->end) >> 2,
|
|
|
3c6e85 |
le32_to_cpu(region->size));
|
|
|
3c6e85 |
|
|
|
3c6e85 |
- switch (le32_to_cpu(region->code) & 0xff) {
|
|
|
3c6e85 |
+ switch (le16_to_cpu(region->code)) {
|
|
|
3c6e85 |
case FLT_REG_FCOE_FW:
|
|
|
3c6e85 |
if (!IS_QLA8031(ha))
|
|
|
3c6e85 |
break;
|
|
|
3c6e85 |
@@ -941,7 +941,7 @@ qla2xxx_get_fdt_info(scsi_qla_host_t *vha)
|
|
|
3c6e85 |
" checksum=0x%x id=%c version0x%x.\n", chksum,
|
|
|
3c6e85 |
fdt->sig[0], le16_to_cpu(fdt->version));
|
|
|
3c6e85 |
ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0113,
|
|
|
3c6e85 |
- (uint8_t *)fdt, sizeof(*fdt));
|
|
|
3c6e85 |
+ fdt, sizeof(*fdt));
|
|
|
3c6e85 |
goto no_flash_data;
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
|
|
|
3c6e85 |
@@ -2879,7 +2879,7 @@ qla2x00_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
|
|
|
3c6e85 |
"Dumping fw "
|
|
|
3c6e85 |
"ver from flash:.\n");
|
|
|
3c6e85 |
ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010b,
|
|
|
3c6e85 |
- (uint8_t *)dbyte, 8);
|
|
|
3c6e85 |
+ dbyte, 8);
|
|
|
3c6e85 |
|
|
|
3c6e85 |
if ((dcode[0] == 0xffff && dcode[1] == 0xffff &&
|
|
|
3c6e85 |
dcode[2] == 0xffff && dcode[3] == 0xffff) ||
|
|
|
3c6e85 |
@@ -3128,24 +3128,16 @@ qla24xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
|
|
|
3c6e85 |
qla27xx_find_valid_image(vha) == QLA27XX_SECONDARY_IMAGE)
|
|
|
3c6e85 |
faddr = ha->flt_region_fw_sec;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
- qla24xx_read_flash_data(vha, dcode, faddr + 4, 4);
|
|
|
3c6e85 |
- for (i = 0; i < 4; i++)
|
|
|
3c6e85 |
- dcode[i] = be32_to_cpu(dcode[i]);
|
|
|
3c6e85 |
-
|
|
|
3c6e85 |
- if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
|
|
|
3c6e85 |
- dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
|
|
|
3c6e85 |
- (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
|
|
|
3c6e85 |
- dcode[3] == 0)) {
|
|
|
3c6e85 |
+ qla24xx_read_flash_data(vha, dcode, faddr, 8);
|
|
|
3c6e85 |
+ if (qla24xx_risc_firmware_invalid(dcode)) {
|
|
|
3c6e85 |
ql_log(ql_log_warn, vha, 0x005f,
|
|
|
3c6e85 |
"Unrecognized fw revision at %x.\n",
|
|
|
3c6e85 |
ha->flt_region_fw * 4);
|
|
|
3c6e85 |
} else {
|
|
|
3c6e85 |
- ha->fw_revision[0] = dcode[0];
|
|
|
3c6e85 |
- ha->fw_revision[1] = dcode[1];
|
|
|
3c6e85 |
- ha->fw_revision[2] = dcode[2];
|
|
|
3c6e85 |
- ha->fw_revision[3] = dcode[3];
|
|
|
3c6e85 |
+ for (i = 0; i < 4; i++)
|
|
|
3c6e85 |
+ ha->fw_revision[i] = be32_to_cpu(dcode[4+i]);
|
|
|
3c6e85 |
ql_dbg(ql_dbg_init, vha, 0x0060,
|
|
|
3c6e85 |
- "Firmware revision %d.%d.%d (%x).\n",
|
|
|
3c6e85 |
+ "Firmware revision (flash) %d.%d.%d (%x).\n",
|
|
|
3c6e85 |
ha->fw_revision[0], ha->fw_revision[1],
|
|
|
3c6e85 |
ha->fw_revision[2], ha->fw_revision[3]);
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
@@ -3158,19 +3150,16 @@ qla24xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
|
|
|
3c6e85 |
|
|
|
3c6e85 |
memset(ha->gold_fw_version, 0, sizeof(ha->gold_fw_version));
|
|
|
3c6e85 |
dcode = mbuf;
|
|
|
3c6e85 |
- ha->isp_ops->read_optrom(vha, (uint8_t *)dcode,
|
|
|
3c6e85 |
- ha->flt_region_gold_fw << 2, 32);
|
|
|
3c6e85 |
-
|
|
|
3c6e85 |
- if (dcode[4] == 0xFFFFFFFF && dcode[5] == 0xFFFFFFFF &&
|
|
|
3c6e85 |
- dcode[6] == 0xFFFFFFFF && dcode[7] == 0xFFFFFFFF) {
|
|
|
3c6e85 |
+ qla24xx_read_flash_data(vha, dcode, ha->flt_region_gold_fw, 8);
|
|
|
3c6e85 |
+ if (qla24xx_risc_firmware_invalid(dcode)) {
|
|
|
3c6e85 |
ql_log(ql_log_warn, vha, 0x0056,
|
|
|
3c6e85 |
"Unrecognized golden fw at 0x%x.\n",
|
|
|
3c6e85 |
ha->flt_region_gold_fw * 4);
|
|
|
3c6e85 |
return ret;
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
|
|
|
3c6e85 |
- for (i = 4; i < 8; i++)
|
|
|
3c6e85 |
- ha->gold_fw_version[i-4] = be32_to_cpu(dcode[i]);
|
|
|
3c6e85 |
+ for (i = 0; i < 4; i++)
|
|
|
3c6e85 |
+ ha->gold_fw_version[i] = be32_to_cpu(dcode[4+i]);
|
|
|
3c6e85 |
|
|
|
3c6e85 |
return ret;
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
diff --git a/drivers/scsi/qla2xxx/qla_tmpl.c b/drivers/scsi/qla2xxx/qla_tmpl.c
|
|
|
3c6e85 |
index 8e1a825aed39..aab4aed88138 100644
|
|
|
3c6e85 |
--- a/drivers/scsi/qla2xxx/qla_tmpl.c
|
|
|
3c6e85 |
+++ b/drivers/scsi/qla2xxx/qla_tmpl.c
|
|
|
3c6e85 |
@@ -134,7 +134,7 @@ qla27xx_skip_entry(struct qla27xx_fwdt_entry *ent, void *buf)
|
|
|
3c6e85 |
static inline struct qla27xx_fwdt_entry *
|
|
|
3c6e85 |
qla27xx_next_entry(struct qla27xx_fwdt_entry *ent)
|
|
|
3c6e85 |
{
|
|
|
3c6e85 |
- return (void *)ent + ent->hdr.size;
|
|
|
3c6e85 |
+ return (void *)ent + le32_to_cpu(ent->hdr.size);
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
|
|
|
3c6e85 |
static struct qla27xx_fwdt_entry *
|
|
|
3c6e85 |
@@ -165,11 +165,14 @@ qla27xx_fwdt_entry_t256(struct scsi_qla_host *vha,
|
|
|
3c6e85 |
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
|
|
|
3c6e85 |
{
|
|
|
3c6e85 |
struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
|
|
|
3c6e85 |
+ ulong addr = le32_to_cpu(ent->t256.base_addr);
|
|
|
3c6e85 |
+ uint offset = ent->t256.pci_offset;
|
|
|
3c6e85 |
+ ulong count = le16_to_cpu(ent->t256.reg_count);
|
|
|
3c6e85 |
+ uint width = ent->t256.reg_width;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
ql_dbg(ql_dbg_misc, vha, 0xd200,
|
|
|
3c6e85 |
"%s: rdio t1 [%lx]\n", __func__, *len);
|
|
|
3c6e85 |
- qla27xx_read_window(reg, ent->t256.base_addr, ent->t256.pci_offset,
|
|
|
3c6e85 |
- ent->t256.reg_count, ent->t256.reg_width, buf, len);
|
|
|
3c6e85 |
+ qla27xx_read_window(reg, addr, offset, count, width, buf, len);
|
|
|
3c6e85 |
|
|
|
3c6e85 |
return qla27xx_next_entry(ent);
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
@@ -179,11 +182,14 @@ qla27xx_fwdt_entry_t257(struct scsi_qla_host *vha,
|
|
|
3c6e85 |
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
|
|
|
3c6e85 |
{
|
|
|
3c6e85 |
struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
|
|
|
3c6e85 |
+ ulong addr = le32_to_cpu(ent->t257.base_addr);
|
|
|
3c6e85 |
+ uint offset = ent->t257.pci_offset;
|
|
|
3c6e85 |
+ ulong data = le32_to_cpu(ent->t257.write_data);
|
|
|
3c6e85 |
|
|
|
3c6e85 |
ql_dbg(ql_dbg_misc, vha, 0xd201,
|
|
|
3c6e85 |
"%s: wrio t1 [%lx]\n", __func__, *len);
|
|
|
3c6e85 |
- qla27xx_write_reg(reg, IOBASE_ADDR, ent->t257.base_addr, buf);
|
|
|
3c6e85 |
- qla27xx_write_reg(reg, ent->t257.pci_offset, ent->t257.write_data, buf);
|
|
|
3c6e85 |
+ qla27xx_write_reg(reg, IOBASE(reg), addr, buf);
|
|
|
3c6e85 |
+ qla27xx_write_reg(reg, offset, data, buf);
|
|
|
3c6e85 |
|
|
|
3c6e85 |
return qla27xx_next_entry(ent);
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
@@ -193,12 +199,17 @@ qla27xx_fwdt_entry_t258(struct scsi_qla_host *vha,
|
|
|
3c6e85 |
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
|
|
|
3c6e85 |
{
|
|
|
3c6e85 |
struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
|
|
|
3c6e85 |
+ uint banksel = ent->t258.banksel_offset;
|
|
|
3c6e85 |
+ ulong bank = le32_to_cpu(ent->t258.bank);
|
|
|
3c6e85 |
+ ulong addr = le32_to_cpu(ent->t258.base_addr);
|
|
|
3c6e85 |
+ uint offset = ent->t258.pci_offset;
|
|
|
3c6e85 |
+ uint count = le16_to_cpu(ent->t258.reg_count);
|
|
|
3c6e85 |
+ uint width = ent->t258.reg_width;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
ql_dbg(ql_dbg_misc, vha, 0xd202,
|
|
|
3c6e85 |
"%s: rdio t2 [%lx]\n", __func__, *len);
|
|
|
3c6e85 |
- qla27xx_write_reg(reg, ent->t258.banksel_offset, ent->t258.bank, buf);
|
|
|
3c6e85 |
- qla27xx_read_window(reg, ent->t258.base_addr, ent->t258.pci_offset,
|
|
|
3c6e85 |
- ent->t258.reg_count, ent->t258.reg_width, buf, len);
|
|
|
3c6e85 |
+ qla27xx_write_reg(reg, banksel, bank, buf);
|
|
|
3c6e85 |
+ qla27xx_read_window(reg, addr, offset, count, width, buf, len);
|
|
|
3c6e85 |
|
|
|
3c6e85 |
return qla27xx_next_entry(ent);
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
@@ -208,12 +219,17 @@ qla27xx_fwdt_entry_t259(struct scsi_qla_host *vha,
|
|
|
3c6e85 |
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
|
|
|
3c6e85 |
{
|
|
|
3c6e85 |
struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
|
|
|
3c6e85 |
+ ulong addr = le32_to_cpu(ent->t259.base_addr);
|
|
|
3c6e85 |
+ uint banksel = ent->t259.banksel_offset;
|
|
|
3c6e85 |
+ ulong bank = le32_to_cpu(ent->t259.bank);
|
|
|
3c6e85 |
+ uint offset = ent->t259.pci_offset;
|
|
|
3c6e85 |
+ ulong data = le32_to_cpu(ent->t259.write_data);
|
|
|
3c6e85 |
|
|
|
3c6e85 |
ql_dbg(ql_dbg_misc, vha, 0xd203,
|
|
|
3c6e85 |
"%s: wrio t2 [%lx]\n", __func__, *len);
|
|
|
3c6e85 |
- qla27xx_write_reg(reg, IOBASE_ADDR, ent->t259.base_addr, buf);
|
|
|
3c6e85 |
- qla27xx_write_reg(reg, ent->t259.banksel_offset, ent->t259.bank, buf);
|
|
|
3c6e85 |
- qla27xx_write_reg(reg, ent->t259.pci_offset, ent->t259.write_data, buf);
|
|
|
3c6e85 |
+ qla27xx_write_reg(reg, IOBASE(reg), addr, buf);
|
|
|
3c6e85 |
+ qla27xx_write_reg(reg, banksel, bank, buf);
|
|
|
3c6e85 |
+ qla27xx_write_reg(reg, offset, data, buf);
|
|
|
3c6e85 |
|
|
|
3c6e85 |
return qla27xx_next_entry(ent);
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
@@ -223,11 +239,12 @@ qla27xx_fwdt_entry_t260(struct scsi_qla_host *vha,
|
|
|
3c6e85 |
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
|
|
|
3c6e85 |
{
|
|
|
3c6e85 |
struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
|
|
|
3c6e85 |
+ uint offset = ent->t260.pci_offset;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
ql_dbg(ql_dbg_misc, vha, 0xd204,
|
|
|
3c6e85 |
"%s: rdpci [%lx]\n", __func__, *len);
|
|
|
3c6e85 |
- qla27xx_insert32(ent->t260.pci_offset, buf, len);
|
|
|
3c6e85 |
- qla27xx_read_reg(reg, ent->t260.pci_offset, buf, len);
|
|
|
3c6e85 |
+ qla27xx_insert32(offset, buf, len);
|
|
|
3c6e85 |
+ qla27xx_read_reg(reg, offset, buf, len);
|
|
|
3c6e85 |
|
|
|
3c6e85 |
return qla27xx_next_entry(ent);
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
@@ -237,10 +254,12 @@ qla27xx_fwdt_entry_t261(struct scsi_qla_host *vha,
|
|
|
3c6e85 |
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
|
|
|
3c6e85 |
{
|
|
|
3c6e85 |
struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
|
|
|
3c6e85 |
+ uint offset = ent->t261.pci_offset;
|
|
|
3c6e85 |
+ ulong data = le32_to_cpu(ent->t261.write_data);
|
|
|
3c6e85 |
|
|
|
3c6e85 |
ql_dbg(ql_dbg_misc, vha, 0xd205,
|
|
|
3c6e85 |
"%s: wrpci [%lx]\n", __func__, *len);
|
|
|
3c6e85 |
- qla27xx_write_reg(reg, ent->t261.pci_offset, ent->t261.write_data, buf);
|
|
|
3c6e85 |
+ qla27xx_write_reg(reg, offset, data, buf);
|
|
|
3c6e85 |
|
|
|
3c6e85 |
return qla27xx_next_entry(ent);
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
@@ -249,51 +268,50 @@ static struct qla27xx_fwdt_entry *
|
|
|
3c6e85 |
qla27xx_fwdt_entry_t262(struct scsi_qla_host *vha,
|
|
|
3c6e85 |
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
|
|
|
3c6e85 |
{
|
|
|
3c6e85 |
+ uint area = ent->t262.ram_area;
|
|
|
3c6e85 |
+ ulong start = le32_to_cpu(ent->t262.start_addr);
|
|
|
3c6e85 |
+ ulong end = le32_to_cpu(ent->t262.end_addr);
|
|
|
3c6e85 |
ulong dwords;
|
|
|
3c6e85 |
- ulong start;
|
|
|
3c6e85 |
- ulong end;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
ql_dbg(ql_dbg_misc, vha, 0xd206,
|
|
|
3c6e85 |
"%s: rdram(%x) [%lx]\n", __func__, ent->t262.ram_area, *len);
|
|
|
3c6e85 |
- start = ent->t262.start_addr;
|
|
|
3c6e85 |
- end = ent->t262.end_addr;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
- if (ent->t262.ram_area == T262_RAM_AREA_CRITICAL_RAM) {
|
|
|
3c6e85 |
+ if (area == T262_RAM_AREA_CRITICAL_RAM) {
|
|
|
3c6e85 |
;
|
|
|
3c6e85 |
- } else if (ent->t262.ram_area == T262_RAM_AREA_EXTERNAL_RAM) {
|
|
|
3c6e85 |
+ } else if (area == T262_RAM_AREA_EXTERNAL_RAM) {
|
|
|
3c6e85 |
end = vha->hw->fw_memory_size;
|
|
|
3c6e85 |
if (buf)
|
|
|
3c6e85 |
- ent->t262.end_addr = end;
|
|
|
3c6e85 |
- } else if (ent->t262.ram_area == T262_RAM_AREA_SHARED_RAM) {
|
|
|
3c6e85 |
+ ent->t262.end_addr = cpu_to_le32(end);
|
|
|
3c6e85 |
+ } else if (area == T262_RAM_AREA_SHARED_RAM) {
|
|
|
3c6e85 |
start = vha->hw->fw_shared_ram_start;
|
|
|
3c6e85 |
end = vha->hw->fw_shared_ram_end;
|
|
|
3c6e85 |
if (buf) {
|
|
|
3c6e85 |
- ent->t262.start_addr = start;
|
|
|
3c6e85 |
- ent->t262.end_addr = end;
|
|
|
3c6e85 |
+ ent->t262.start_addr = cpu_to_le32(start);
|
|
|
3c6e85 |
+ ent->t262.end_addr = cpu_to_le32(end);
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
- } else if (ent->t262.ram_area == T262_RAM_AREA_DDR_RAM) {
|
|
|
3c6e85 |
+ } else if (area == T262_RAM_AREA_DDR_RAM) {
|
|
|
3c6e85 |
start = vha->hw->fw_ddr_ram_start;
|
|
|
3c6e85 |
end = vha->hw->fw_ddr_ram_end;
|
|
|
3c6e85 |
if (buf) {
|
|
|
3c6e85 |
- ent->t262.start_addr = start;
|
|
|
3c6e85 |
- ent->t262.end_addr = end;
|
|
|
3c6e85 |
+ ent->t262.start_addr = cpu_to_le32(start);
|
|
|
3c6e85 |
+ ent->t262.end_addr = cpu_to_le32(end);
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
- } else if (ent->t262.ram_area == T262_RAM_AREA_MISC) {
|
|
|
3c6e85 |
+ } else if (area == T262_RAM_AREA_MISC) {
|
|
|
3c6e85 |
if (buf) {
|
|
|
3c6e85 |
- ent->t262.start_addr = start;
|
|
|
3c6e85 |
- ent->t262.end_addr = end;
|
|
|
3c6e85 |
+ ent->t262.start_addr = cpu_to_le32(start);
|
|
|
3c6e85 |
+ ent->t262.end_addr = cpu_to_le32(end);
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
} else {
|
|
|
3c6e85 |
ql_dbg(ql_dbg_misc, vha, 0xd022,
|
|
|
3c6e85 |
- "%s: unknown area %x\n", __func__, ent->t262.ram_area);
|
|
|
3c6e85 |
+ "%s: unknown area %x\n", __func__, area);
|
|
|
3c6e85 |
qla27xx_skip_entry(ent, buf);
|
|
|
3c6e85 |
goto done;
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
|
|
|
3c6e85 |
if (end <= start || start == 0 || end == 0) {
|
|
|
3c6e85 |
ql_dbg(ql_dbg_misc, vha, 0xd023,
|
|
|
3c6e85 |
- "%s: unusable range (start=%x end=%x)\n", __func__,
|
|
|
3c6e85 |
- ent->t262.end_addr, ent->t262.start_addr);
|
|
|
3c6e85 |
+ "%s: unusable range (start=%lx end=%lx)\n",
|
|
|
3c6e85 |
+ __func__, start, end);
|
|
|
3c6e85 |
qla27xx_skip_entry(ent, buf);
|
|
|
3c6e85 |
goto done;
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
@@ -312,13 +330,14 @@ static struct qla27xx_fwdt_entry *
|
|
|
3c6e85 |
qla27xx_fwdt_entry_t263(struct scsi_qla_host *vha,
|
|
|
3c6e85 |
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
|
|
|
3c6e85 |
{
|
|
|
3c6e85 |
+ uint type = ent->t263.queue_type;
|
|
|
3c6e85 |
uint count = 0;
|
|
|
3c6e85 |
uint i;
|
|
|
3c6e85 |
uint length;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
- ql_dbg(ql_dbg_misc, vha, 0xd207,
|
|
|
3c6e85 |
- "%s: getq(%x) [%lx]\n", __func__, ent->t263.queue_type, *len);
|
|
|
3c6e85 |
- if (ent->t263.queue_type == T263_QUEUE_TYPE_REQ) {
|
|
|
3c6e85 |
+ ql_dbg(ql_dbg_misc + ql_dbg_verbose, vha, 0xd207,
|
|
|
3c6e85 |
+ "%s: getq(%x) [%lx]\n", __func__, type, *len);
|
|
|
3c6e85 |
+ if (type == T263_QUEUE_TYPE_REQ) {
|
|
|
3c6e85 |
for (i = 0; i < vha->hw->max_req_queues; i++) {
|
|
|
3c6e85 |
struct req_que *req = vha->hw->req_q_map[i];
|
|
|
3c6e85 |
|
|
|
3c6e85 |
@@ -332,7 +351,7 @@ qla27xx_fwdt_entry_t263(struct scsi_qla_host *vha,
|
|
|
3c6e85 |
count++;
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
- } else if (ent->t263.queue_type == T263_QUEUE_TYPE_RSP) {
|
|
|
3c6e85 |
+ } else if (type == T263_QUEUE_TYPE_RSP) {
|
|
|
3c6e85 |
for (i = 0; i < vha->hw->max_rsp_queues; i++) {
|
|
|
3c6e85 |
struct rsp_que *rsp = vha->hw->rsp_q_map[i];
|
|
|
3c6e85 |
|
|
|
3c6e85 |
@@ -360,7 +379,7 @@ qla27xx_fwdt_entry_t263(struct scsi_qla_host *vha,
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
} else {
|
|
|
3c6e85 |
ql_dbg(ql_dbg_misc, vha, 0xd026,
|
|
|
3c6e85 |
- "%s: unknown queue %x\n", __func__, ent->t263.queue_type);
|
|
|
3c6e85 |
+ "%s: unknown queue %x\n", __func__, type);
|
|
|
3c6e85 |
qla27xx_skip_entry(ent, buf);
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
|
|
|
3c6e85 |
@@ -433,10 +452,12 @@ qla27xx_fwdt_entry_t267(struct scsi_qla_host *vha,
|
|
|
3c6e85 |
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
|
|
|
3c6e85 |
{
|
|
|
3c6e85 |
struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
|
|
|
3c6e85 |
+ uint offset = ent->t267.pci_offset;
|
|
|
3c6e85 |
+ ulong data = le32_to_cpu(ent->t267.data);
|
|
|
3c6e85 |
|
|
|
3c6e85 |
ql_dbg(ql_dbg_misc, vha, 0xd20b,
|
|
|
3c6e85 |
"%s: dis intr [%lx]\n", __func__, *len);
|
|
|
3c6e85 |
- qla27xx_write_reg(reg, ent->t267.pci_offset, ent->t267.data, buf);
|
|
|
3c6e85 |
+ qla27xx_write_reg(reg, offset, data, buf);
|
|
|
3c6e85 |
|
|
|
3c6e85 |
return qla27xx_next_entry(ent);
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
@@ -533,8 +554,8 @@ qla27xx_fwdt_entry_t270(struct scsi_qla_host *vha,
|
|
|
3c6e85 |
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
|
|
|
3c6e85 |
{
|
|
|
3c6e85 |
struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
|
|
|
3c6e85 |
- ulong dwords = ent->t270.count;
|
|
|
3c6e85 |
- ulong addr = ent->t270.addr;
|
|
|
3c6e85 |
+ ulong addr = le32_to_cpu(ent->t270.addr);
|
|
|
3c6e85 |
+ ulong dwords = le32_to_cpu(ent->t270.count);
|
|
|
3c6e85 |
|
|
|
3c6e85 |
ql_dbg(ql_dbg_misc, vha, 0xd20e,
|
|
|
3c6e85 |
"%s: rdremreg [%lx]\n", __func__, *len);
|
|
|
3c6e85 |
@@ -554,8 +575,8 @@ qla27xx_fwdt_entry_t271(struct scsi_qla_host *vha,
|
|
|
3c6e85 |
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
|
|
|
3c6e85 |
{
|
|
|
3c6e85 |
struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
|
|
|
3c6e85 |
- ulong addr = ent->t271.addr;
|
|
|
3c6e85 |
- ulong data = ent->t271.data;
|
|
|
3c6e85 |
+ ulong addr = le32_to_cpu(ent->t271.addr);
|
|
|
3c6e85 |
+ ulong data = le32_to_cpu(ent->t271.data);
|
|
|
3c6e85 |
|
|
|
3c6e85 |
ql_dbg(ql_dbg_misc, vha, 0xd20f,
|
|
|
3c6e85 |
"%s: wrremreg [%lx]\n", __func__, *len);
|
|
|
3c6e85 |
@@ -570,8 +591,8 @@ static struct qla27xx_fwdt_entry *
|
|
|
3c6e85 |
qla27xx_fwdt_entry_t272(struct scsi_qla_host *vha,
|
|
|
3c6e85 |
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
|
|
|
3c6e85 |
{
|
|
|
3c6e85 |
- ulong dwords = ent->t272.count;
|
|
|
3c6e85 |
- ulong start = ent->t272.addr;
|
|
|
3c6e85 |
+ ulong dwords = le32_to_cpu(ent->t272.count);
|
|
|
3c6e85 |
+ ulong start = le32_to_cpu(ent->t272.addr);
|
|
|
3c6e85 |
|
|
|
3c6e85 |
ql_dbg(ql_dbg_misc, vha, 0xd210,
|
|
|
3c6e85 |
"%s: rdremram [%lx]\n", __func__, *len);
|
|
|
3c6e85 |
@@ -590,8 +611,8 @@ static struct qla27xx_fwdt_entry *
|
|
|
3c6e85 |
qla27xx_fwdt_entry_t273(struct scsi_qla_host *vha,
|
|
|
3c6e85 |
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
|
|
|
3c6e85 |
{
|
|
|
3c6e85 |
- ulong dwords = ent->t273.count;
|
|
|
3c6e85 |
- ulong addr = ent->t273.addr;
|
|
|
3c6e85 |
+ ulong dwords = le32_to_cpu(ent->t273.count);
|
|
|
3c6e85 |
+ ulong addr = le32_to_cpu(ent->t273.addr);
|
|
|
3c6e85 |
uint32_t value;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
ql_dbg(ql_dbg_misc, vha, 0xd211,
|
|
|
3c6e85 |
@@ -613,12 +634,13 @@ static struct qla27xx_fwdt_entry *
|
|
|
3c6e85 |
qla27xx_fwdt_entry_t274(struct scsi_qla_host *vha,
|
|
|
3c6e85 |
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
|
|
|
3c6e85 |
{
|
|
|
3c6e85 |
+ ulong type = ent->t274.queue_type;
|
|
|
3c6e85 |
uint count = 0;
|
|
|
3c6e85 |
uint i;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
- ql_dbg(ql_dbg_misc, vha, 0xd212,
|
|
|
3c6e85 |
- "%s: getqsh(%x) [%lx]\n", __func__, ent->t274.queue_type, *len);
|
|
|
3c6e85 |
- if (ent->t274.queue_type == T274_QUEUE_TYPE_REQ_SHAD) {
|
|
|
3c6e85 |
+ ql_dbg(ql_dbg_misc + ql_dbg_verbose, vha, 0xd212,
|
|
|
3c6e85 |
+ "%s: getqsh(%lx) [%lx]\n", __func__, type, *len);
|
|
|
3c6e85 |
+ if (type == T274_QUEUE_TYPE_REQ_SHAD) {
|
|
|
3c6e85 |
for (i = 0; i < vha->hw->max_req_queues; i++) {
|
|
|
3c6e85 |
struct req_que *req = vha->hw->req_q_map[i];
|
|
|
3c6e85 |
|
|
|
3c6e85 |
@@ -630,7 +652,7 @@ qla27xx_fwdt_entry_t274(struct scsi_qla_host *vha,
|
|
|
3c6e85 |
count++;
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
- } else if (ent->t274.queue_type == T274_QUEUE_TYPE_RSP_SHAD) {
|
|
|
3c6e85 |
+ } else if (type == T274_QUEUE_TYPE_RSP_SHAD) {
|
|
|
3c6e85 |
for (i = 0; i < vha->hw->max_rsp_queues; i++) {
|
|
|
3c6e85 |
struct rsp_que *rsp = vha->hw->rsp_q_map[i];
|
|
|
3c6e85 |
|
|
|
3c6e85 |
@@ -656,7 +678,7 @@ qla27xx_fwdt_entry_t274(struct scsi_qla_host *vha,
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
} else {
|
|
|
3c6e85 |
ql_dbg(ql_dbg_misc, vha, 0xd02f,
|
|
|
3c6e85 |
- "%s: unknown queue %x\n", __func__, ent->t274.queue_type);
|
|
|
3c6e85 |
+ "%s: unknown queue %lx\n", __func__, type);
|
|
|
3c6e85 |
qla27xx_skip_entry(ent, buf);
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
|
|
|
3c6e85 |
@@ -675,23 +697,26 @@ qla27xx_fwdt_entry_t275(struct scsi_qla_host *vha,
|
|
|
3c6e85 |
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
|
|
|
3c6e85 |
{
|
|
|
3c6e85 |
ulong offset = offsetof(typeof(*ent), t275.buffer);
|
|
|
3c6e85 |
+ ulong length = le32_to_cpu(ent->t275.length);
|
|
|
3c6e85 |
+ ulong size = le32_to_cpu(ent->hdr.size);
|
|
|
3c6e85 |
+ void *buffer = ent->t275.buffer;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
- ql_dbg(ql_dbg_misc, vha, 0xd213,
|
|
|
3c6e85 |
- "%s: buffer(%x) [%lx]\n", __func__, ent->t275.length, *len);
|
|
|
3c6e85 |
- if (!ent->t275.length) {
|
|
|
3c6e85 |
+ ql_dbg(ql_dbg_misc + ql_dbg_verbose, vha, 0xd213,
|
|
|
3c6e85 |
+ "%s: buffer(%lx) [%lx]\n", __func__, length, *len);
|
|
|
3c6e85 |
+ if (!length) {
|
|
|
3c6e85 |
ql_dbg(ql_dbg_misc, vha, 0xd020,
|
|
|
3c6e85 |
"%s: buffer zero length\n", __func__);
|
|
|
3c6e85 |
qla27xx_skip_entry(ent, buf);
|
|
|
3c6e85 |
goto done;
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
- if (offset + ent->t275.length > ent->hdr.size) {
|
|
|
3c6e85 |
+ if (offset + length > size) {
|
|
|
3c6e85 |
ql_dbg(ql_dbg_misc, vha, 0xd030,
|
|
|
3c6e85 |
"%s: buffer overflow\n", __func__);
|
|
|
3c6e85 |
qla27xx_skip_entry(ent, buf);
|
|
|
3c6e85 |
goto done;
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
|
|
|
3c6e85 |
- qla27xx_insertbuf(ent->t275.buffer, ent->t275.length, buf, len);
|
|
|
3c6e85 |
+ qla27xx_insertbuf(buffer, length, buf, len);
|
|
|
3c6e85 |
done:
|
|
|
3c6e85 |
return qla27xx_next_entry(ent);
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
@@ -700,13 +725,15 @@ static struct qla27xx_fwdt_entry *
|
|
|
3c6e85 |
qla27xx_fwdt_entry_t276(struct scsi_qla_host *vha,
|
|
|
3c6e85 |
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
|
|
|
3c6e85 |
{
|
|
|
3c6e85 |
+ ulong cond1 = le32_to_cpu(ent->t276.cond1);
|
|
|
3c6e85 |
+ ulong cond2 = le32_to_cpu(ent->t276.cond2);
|
|
|
3c6e85 |
uint type = vha->hw->pdev->device >> 4 & 0xf;
|
|
|
3c6e85 |
uint func = vha->hw->port_no & 0x3;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
ql_dbg(ql_dbg_misc + ql_dbg_verbose, vha, 0xd214,
|
|
|
3c6e85 |
"%s: cond [%lx]\n", __func__, *len);
|
|
|
3c6e85 |
|
|
|
3c6e85 |
- if (type != ent->t276.cond1 || func != ent->t276.cond2) {
|
|
|
3c6e85 |
+ if (type != cond1 || func != cond2) {
|
|
|
3c6e85 |
ent = qla27xx_next_entry(ent);
|
|
|
3c6e85 |
qla27xx_skip_entry(ent, buf);
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
@@ -719,12 +746,15 @@ qla27xx_fwdt_entry_t277(struct scsi_qla_host *vha,
|
|
|
3c6e85 |
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
|
|
|
3c6e85 |
{
|
|
|
3c6e85 |
struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
|
|
|
3c6e85 |
+ ulong cmd_addr = le32_to_cpu(ent->t277.cmd_addr);
|
|
|
3c6e85 |
+ ulong wr_cmd_data = le32_to_cpu(ent->t277.wr_cmd_data);
|
|
|
3c6e85 |
+ ulong data_addr = le32_to_cpu(ent->t277.data_addr);
|
|
|
3c6e85 |
|
|
|
3c6e85 |
ql_dbg(ql_dbg_misc + ql_dbg_verbose, vha, 0xd215,
|
|
|
3c6e85 |
"%s: rdpep [%lx]\n", __func__, *len);
|
|
|
3c6e85 |
- qla27xx_insert32(ent->t277.wr_cmd_data, buf, len);
|
|
|
3c6e85 |
- qla27xx_write_reg(reg, ent->t277.cmd_addr, ent->t277.wr_cmd_data, buf);
|
|
|
3c6e85 |
- qla27xx_read_reg(reg, ent->t277.data_addr, buf, len);
|
|
|
3c6e85 |
+ qla27xx_insert32(wr_cmd_data, buf, len);
|
|
|
3c6e85 |
+ qla27xx_write_reg(reg, cmd_addr, wr_cmd_data, buf);
|
|
|
3c6e85 |
+ qla27xx_read_reg(reg, data_addr, buf, len);
|
|
|
3c6e85 |
|
|
|
3c6e85 |
return qla27xx_next_entry(ent);
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
@@ -734,11 +764,15 @@ qla27xx_fwdt_entry_t278(struct scsi_qla_host *vha,
|
|
|
3c6e85 |
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
|
|
|
3c6e85 |
{
|
|
|
3c6e85 |
struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
|
|
|
3c6e85 |
+ ulong cmd_addr = le32_to_cpu(ent->t278.cmd_addr);
|
|
|
3c6e85 |
+ ulong wr_cmd_data = le32_to_cpu(ent->t278.wr_cmd_data);
|
|
|
3c6e85 |
+ ulong data_addr = le32_to_cpu(ent->t278.data_addr);
|
|
|
3c6e85 |
+ ulong wr_data = le32_to_cpu(ent->t278.wr_data);
|
|
|
3c6e85 |
|
|
|
3c6e85 |
ql_dbg(ql_dbg_misc + ql_dbg_verbose, vha, 0xd216,
|
|
|
3c6e85 |
"%s: wrpep [%lx]\n", __func__, *len);
|
|
|
3c6e85 |
- qla27xx_write_reg(reg, ent->t278.data_addr, ent->t278.wr_data, buf);
|
|
|
3c6e85 |
- qla27xx_write_reg(reg, ent->t278.cmd_addr, ent->t278.wr_cmd_data, buf);
|
|
|
3c6e85 |
+ qla27xx_write_reg(reg, data_addr, wr_data, buf);
|
|
|
3c6e85 |
+ qla27xx_write_reg(reg, cmd_addr, wr_cmd_data, buf);
|
|
|
3c6e85 |
|
|
|
3c6e85 |
return qla27xx_next_entry(ent);
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
@@ -747,8 +781,10 @@ static struct qla27xx_fwdt_entry *
|
|
|
3c6e85 |
qla27xx_fwdt_entry_other(struct scsi_qla_host *vha,
|
|
|
3c6e85 |
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
|
|
|
3c6e85 |
{
|
|
|
3c6e85 |
+ ulong type = le32_to_cpu(ent->hdr.type);
|
|
|
3c6e85 |
+
|
|
|
3c6e85 |
ql_dbg(ql_dbg_misc, vha, 0xd2ff,
|
|
|
3c6e85 |
- "%s: type %x [%lx]\n", __func__, ent->hdr.type, *len);
|
|
|
3c6e85 |
+ "%s: other %lx [%lx]\n", __func__, type, *len);
|
|
|
3c6e85 |
qla27xx_skip_entry(ent, buf);
|
|
|
3c6e85 |
|
|
|
3c6e85 |
return qla27xx_next_entry(ent);
|
|
|
3c6e85 |
@@ -803,13 +839,16 @@ static void
|
|
|
3c6e85 |
qla27xx_walk_template(struct scsi_qla_host *vha,
|
|
|
3c6e85 |
struct qla27xx_fwdt_template *tmp, void *buf, ulong *len)
|
|
|
3c6e85 |
{
|
|
|
3c6e85 |
- struct qla27xx_fwdt_entry *ent = (void *)tmp + tmp->entry_offset;
|
|
|
3c6e85 |
- ulong count = tmp->entry_count;
|
|
|
3c6e85 |
+ struct qla27xx_fwdt_entry *ent = (void *)tmp +
|
|
|
3c6e85 |
+ le32_to_cpu(tmp->entry_offset);
|
|
|
3c6e85 |
+ ulong count = le32_to_cpu(tmp->entry_count);
|
|
|
3c6e85 |
+ ulong type = 0;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
ql_dbg(ql_dbg_misc, vha, 0xd01a,
|
|
|
3c6e85 |
"%s: entry count %lx\n", __func__, count);
|
|
|
3c6e85 |
while (count--) {
|
|
|
3c6e85 |
- ent = qla27xx_find_entry(ent->hdr.type)(vha, ent, buf, len);
|
|
|
3c6e85 |
+ type = le32_to_cpu(ent->hdr.type);
|
|
|
3c6e85 |
+ ent = qla27xx_find_entry(type)(vha, ent, buf, len);
|
|
|
3c6e85 |
if (!ent)
|
|
|
3c6e85 |
break;
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
@@ -879,13 +918,13 @@ ql27xx_edit_template(struct scsi_qla_host *vha,
|
|
|
3c6e85 |
static inline uint32_t
|
|
|
3c6e85 |
qla27xx_template_checksum(void *p, ulong size)
|
|
|
3c6e85 |
{
|
|
|
3c6e85 |
- uint32_t *buf = p;
|
|
|
3c6e85 |
+ __le32 *buf = p;
|
|
|
3c6e85 |
uint64_t sum = 0;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
size /= sizeof(*buf);
|
|
|
3c6e85 |
|
|
|
3c6e85 |
- while (size--)
|
|
|
3c6e85 |
- sum += *buf++;
|
|
|
3c6e85 |
+ for ( ; size--; buf++)
|
|
|
3c6e85 |
+ sum += le32_to_cpu(*buf);
|
|
|
3c6e85 |
|
|
|
3c6e85 |
sum = (sum & 0xffffffff) + (sum >> 32);
|
|
|
3c6e85 |
|
|
|
3c6e85 |
@@ -901,7 +940,7 @@ qla27xx_verify_template_checksum(struct qla27xx_fwdt_template *tmp)
|
|
|
3c6e85 |
static inline int
|
|
|
3c6e85 |
qla27xx_verify_template_header(struct qla27xx_fwdt_template *tmp)
|
|
|
3c6e85 |
{
|
|
|
3c6e85 |
- return tmp->template_type == TEMPLATE_TYPE_FWDUMP;
|
|
|
3c6e85 |
+ return le32_to_cpu(tmp->template_type) == TEMPLATE_TYPE_FWDUMP;
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
|
|
|
3c6e85 |
static void
|
|
|
3c6e85 |
@@ -949,7 +988,8 @@ qla27xx_fwdt_template_valid(void *p)
|
|
|
3c6e85 |
|
|
|
3c6e85 |
if (!qla27xx_verify_template_header(tmp)) {
|
|
|
3c6e85 |
ql_log(ql_log_warn, NULL, 0xd01c,
|
|
|
3c6e85 |
- "%s: template type %x\n", __func__, tmp->template_type);
|
|
|
3c6e85 |
+ "%s: template type %x\n", __func__,
|
|
|
3c6e85 |
+ le32_to_cpu(tmp->template_type));
|
|
|
3c6e85 |
return false;
|
|
|
3c6e85 |
}
|
|
|
3c6e85 |
|
|
|
3c6e85 |
diff --git a/drivers/scsi/qla2xxx/qla_tmpl.h b/drivers/scsi/qla2xxx/qla_tmpl.h
|
|
|
3c6e85 |
index f7990f2a057a..036194234430 100644
|
|
|
3c6e85 |
--- a/drivers/scsi/qla2xxx/qla_tmpl.h
|
|
|
3c6e85 |
+++ b/drivers/scsi/qla2xxx/qla_tmpl.h
|
|
|
3c6e85 |
@@ -11,12 +11,12 @@
|
|
|
3c6e85 |
#define IOBASE_ADDR offsetof(struct device_reg_24xx, iobase_addr)
|
|
|
3c6e85 |
|
|
|
3c6e85 |
struct __packed qla27xx_fwdt_template {
|
|
|
3c6e85 |
- uint32_t template_type;
|
|
|
3c6e85 |
- uint32_t entry_offset;
|
|
|
3c6e85 |
+ __le32 template_type;
|
|
|
3c6e85 |
+ __le32 entry_offset;
|
|
|
3c6e85 |
uint32_t template_size;
|
|
|
3c6e85 |
uint32_t reserved_1;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
- uint32_t entry_count;
|
|
|
3c6e85 |
+ __le32 entry_count;
|
|
|
3c6e85 |
uint32_t template_version;
|
|
|
3c6e85 |
uint32_t capture_timestamp;
|
|
|
3c6e85 |
uint32_t template_checksum;
|
|
|
3c6e85 |
@@ -65,8 +65,8 @@ struct __packed qla27xx_fwdt_template {
|
|
|
3c6e85 |
|
|
|
3c6e85 |
struct __packed qla27xx_fwdt_entry {
|
|
|
3c6e85 |
struct __packed {
|
|
|
3c6e85 |
- uint32_t type;
|
|
|
3c6e85 |
- uint32_t size;
|
|
|
3c6e85 |
+ __le32 type;
|
|
|
3c6e85 |
+ __le32 size;
|
|
|
3c6e85 |
uint32_t reserved_1;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
uint8_t capture_flags;
|
|
|
3c6e85 |
@@ -81,36 +81,36 @@ struct __packed qla27xx_fwdt_entry {
|
|
|
3c6e85 |
} t255;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
struct __packed {
|
|
|
3c6e85 |
- uint32_t base_addr;
|
|
|
3c6e85 |
+ __le32 base_addr;
|
|
|
3c6e85 |
uint8_t reg_width;
|
|
|
3c6e85 |
- uint16_t reg_count;
|
|
|
3c6e85 |
+ __le16 reg_count;
|
|
|
3c6e85 |
uint8_t pci_offset;
|
|
|
3c6e85 |
} t256;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
struct __packed {
|
|
|
3c6e85 |
- uint32_t base_addr;
|
|
|
3c6e85 |
- uint32_t write_data;
|
|
|
3c6e85 |
+ __le32 base_addr;
|
|
|
3c6e85 |
+ __le32 write_data;
|
|
|
3c6e85 |
uint8_t pci_offset;
|
|
|
3c6e85 |
uint8_t reserved[3];
|
|
|
3c6e85 |
} t257;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
struct __packed {
|
|
|
3c6e85 |
- uint32_t base_addr;
|
|
|
3c6e85 |
+ __le32 base_addr;
|
|
|
3c6e85 |
uint8_t reg_width;
|
|
|
3c6e85 |
- uint16_t reg_count;
|
|
|
3c6e85 |
+ __le16 reg_count;
|
|
|
3c6e85 |
uint8_t pci_offset;
|
|
|
3c6e85 |
uint8_t banksel_offset;
|
|
|
3c6e85 |
uint8_t reserved[3];
|
|
|
3c6e85 |
- uint32_t bank;
|
|
|
3c6e85 |
+ __le32 bank;
|
|
|
3c6e85 |
} t258;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
struct __packed {
|
|
|
3c6e85 |
- uint32_t base_addr;
|
|
|
3c6e85 |
- uint32_t write_data;
|
|
|
3c6e85 |
+ __le32 base_addr;
|
|
|
3c6e85 |
+ __le32 write_data;
|
|
|
3c6e85 |
uint8_t reserved[2];
|
|
|
3c6e85 |
uint8_t pci_offset;
|
|
|
3c6e85 |
uint8_t banksel_offset;
|
|
|
3c6e85 |
- uint32_t bank;
|
|
|
3c6e85 |
+ __le32 bank;
|
|
|
3c6e85 |
} t259;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
struct __packed {
|
|
|
3c6e85 |
@@ -121,14 +121,14 @@ struct __packed qla27xx_fwdt_entry {
|
|
|
3c6e85 |
struct __packed {
|
|
|
3c6e85 |
uint8_t pci_offset;
|
|
|
3c6e85 |
uint8_t reserved[3];
|
|
|
3c6e85 |
- uint32_t write_data;
|
|
|
3c6e85 |
+ __le32 write_data;
|
|
|
3c6e85 |
} t261;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
struct __packed {
|
|
|
3c6e85 |
uint8_t ram_area;
|
|
|
3c6e85 |
uint8_t reserved[3];
|
|
|
3c6e85 |
- uint32_t start_addr;
|
|
|
3c6e85 |
- uint32_t end_addr;
|
|
|
3c6e85 |
+ __le32 start_addr;
|
|
|
3c6e85 |
+ __le32 end_addr;
|
|
|
3c6e85 |
} t262;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
struct __packed {
|
|
|
3c6e85 |
@@ -158,7 +158,7 @@ struct __packed qla27xx_fwdt_entry {
|
|
|
3c6e85 |
struct __packed {
|
|
|
3c6e85 |
uint8_t pci_offset;
|
|
|
3c6e85 |
uint8_t reserved[3];
|
|
|
3c6e85 |
- uint32_t data;
|
|
|
3c6e85 |
+ __le32 data;
|
|
|
3c6e85 |
} t267;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
struct __packed {
|
|
|
3c6e85 |
@@ -173,23 +173,23 @@ struct __packed qla27xx_fwdt_entry {
|
|
|
3c6e85 |
} t269;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
struct __packed {
|
|
|
3c6e85 |
- uint32_t addr;
|
|
|
3c6e85 |
- uint32_t count;
|
|
|
3c6e85 |
+ __le32 addr;
|
|
|
3c6e85 |
+ __le32 count;
|
|
|
3c6e85 |
} t270;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
struct __packed {
|
|
|
3c6e85 |
- uint32_t addr;
|
|
|
3c6e85 |
- uint32_t data;
|
|
|
3c6e85 |
+ __le32 addr;
|
|
|
3c6e85 |
+ __le32 data;
|
|
|
3c6e85 |
} t271;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
struct __packed {
|
|
|
3c6e85 |
- uint32_t addr;
|
|
|
3c6e85 |
- uint32_t count;
|
|
|
3c6e85 |
+ __le32 addr;
|
|
|
3c6e85 |
+ __le32 count;
|
|
|
3c6e85 |
} t272;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
struct __packed {
|
|
|
3c6e85 |
- uint32_t addr;
|
|
|
3c6e85 |
- uint32_t count;
|
|
|
3c6e85 |
+ __le32 addr;
|
|
|
3c6e85 |
+ __le32 count;
|
|
|
3c6e85 |
} t273;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
struct __packed {
|
|
|
3c6e85 |
@@ -199,26 +199,26 @@ struct __packed qla27xx_fwdt_entry {
|
|
|
3c6e85 |
} t274;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
struct __packed {
|
|
|
3c6e85 |
- uint32_t length;
|
|
|
3c6e85 |
+ __le32 length;
|
|
|
3c6e85 |
uint8_t buffer[];
|
|
|
3c6e85 |
} t275;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
struct __packed {
|
|
|
3c6e85 |
- uint32_t cond1;
|
|
|
3c6e85 |
- uint32_t cond2;
|
|
|
3c6e85 |
+ __le32 cond1;
|
|
|
3c6e85 |
+ __le32 cond2;
|
|
|
3c6e85 |
} t276;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
struct __packed {
|
|
|
3c6e85 |
- uint32_t cmd_addr;
|
|
|
3c6e85 |
- uint32_t wr_cmd_data;
|
|
|
3c6e85 |
- uint32_t data_addr;
|
|
|
3c6e85 |
+ __le32 cmd_addr;
|
|
|
3c6e85 |
+ __le32 wr_cmd_data;
|
|
|
3c6e85 |
+ __le32 data_addr;
|
|
|
3c6e85 |
} t277;
|
|
|
3c6e85 |
|
|
|
3c6e85 |
struct __packed {
|
|
|
3c6e85 |
- uint32_t cmd_addr;
|
|
|
3c6e85 |
- uint32_t wr_cmd_data;
|
|
|
3c6e85 |
- uint32_t data_addr;
|
|
|
3c6e85 |
- uint32_t wr_data;
|
|
|
3c6e85 |
+ __le32 cmd_addr;
|
|
|
3c6e85 |
+ __le32 wr_cmd_data;
|
|
|
3c6e85 |
+ __le32 data_addr;
|
|
|
3c6e85 |
+ __le32 wr_data;
|
|
|
3c6e85 |
} t278;
|
|
|
3c6e85 |
};
|
|
|
3c6e85 |
};
|
|
|
3c6e85 |
--
|
|
|
3c6e85 |
2.13.6
|
|
|
3c6e85 |
|