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Date: Thu, 18 Jun 2020 19:42:39 -0400
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From: Jonathan Toppins <jtoppins@redhat.com>
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To: rhkernel-list@redhat.com
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Cc: darcari@redhat.com, nhorman@redhat.com, linville@redhat.com
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Subject: [PATCH RHEL-8.3 04/16] ionic: updates to ionic FW api description
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Lots of comment cleanup for better documentation, a few new
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fields added, and a few minor mistakes fixed up.
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Signed-off-by: Shannon Nelson <snelson@pensando.io>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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(cherry picked from commit c4e7a75a096c02035a102686e2569e7b0341a122)
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Bugzilla: 1848149
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Build Info: https://brewweb.engineering.redhat.com/brew/taskinfo?taskID=29498383
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Tested: QE tested devel kernel as well as the partner
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Signed-off-by: Jonathan Toppins <jtoppins@redhat.com>
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---
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drivers/net/ethernet/pensando/ionic/ionic_if.h | 979 +++++++++++++++----------
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1 file changed, 576 insertions(+), 403 deletions(-)
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diff --git a/drivers/net/ethernet/pensando/ionic/ionic_if.h b/drivers/net/ethernet/pensando/ionic/ionic_if.h
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index 7b9ec07db363..20f262913639 100644
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--- a/drivers/net/ethernet/pensando/ionic/ionic_if.h
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+++ b/drivers/net/ethernet/pensando/ionic/ionic_if.h
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@@ -1,5 +1,5 @@
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/* SPDX-License-Identifier: (GPL-2.0 OR Linux-OpenIB) OR BSD-2-Clause */
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-/* Copyright (c) 2017-2019 Pensando Systems, Inc. All rights reserved. */
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+/* Copyright (c) 2017-2020 Pensando Systems, Inc. All rights reserved. */
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#ifndef _IONIC_IF_H_
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#define _IONIC_IF_H_
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@@ -9,7 +9,7 @@
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#define IONIC_IFNAMSIZ 16
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/**
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- * Commands
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+ * enum ionic_cmd_opcode - Device commands
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*/
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enum ionic_cmd_opcode {
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IONIC_CMD_NOP = 0,
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@@ -58,6 +58,7 @@ enum ionic_cmd_opcode {
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IONIC_CMD_QOS_CLASS_IDENTIFY = 240,
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IONIC_CMD_QOS_CLASS_INIT = 241,
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IONIC_CMD_QOS_CLASS_RESET = 242,
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+ IONIC_CMD_QOS_CLASS_UPDATE = 243,
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/* Firmware commands */
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IONIC_CMD_FW_DOWNLOAD = 254,
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@@ -65,7 +66,7 @@ enum ionic_cmd_opcode {
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};
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/**
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- * Command Return codes
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+ * enum ionic_status_code - Device command return codes
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*/
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enum ionic_status_code {
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IONIC_RC_SUCCESS = 0, /* Success */
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@@ -98,6 +99,7 @@ enum ionic_notifyq_opcode {
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IONIC_EVENT_RESET = 2,
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IONIC_EVENT_HEARTBEAT = 3,
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IONIC_EVENT_LOG = 4,
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+ IONIC_EVENT_XCVR = 5,
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};
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/**
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@@ -115,12 +117,11 @@ struct ionic_admin_cmd {
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/**
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* struct ionic_admin_comp - General admin command completion format
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- * @status: The status of the command (enum status_code)
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- * @comp_index: The index in the descriptor ring for which this
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- * is the completion.
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- * @cmd_data: Command-specific bytes.
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- * @color: Color bit. (Always 0 for commands issued to the
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- * Device Cmd Registers.)
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+ * @status: Status of the command (enum ionic_status_code)
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+ * @comp_index: Index in the descriptor ring for which this is the completion
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+ * @cmd_data: Command-specific bytes
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+ * @color: Color bit (Always 0 for commands issued to the
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+ * Device Cmd Registers)
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*/
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struct ionic_admin_comp {
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u8 status;
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@@ -147,7 +148,7 @@ struct ionic_nop_cmd {
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/**
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* struct ionic_nop_comp - NOP command completion
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- * @status: The status of the command (enum status_code)
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+ * @status: Status of the command (enum ionic_status_code)
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*/
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struct ionic_nop_comp {
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u8 status;
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@@ -157,7 +158,7 @@ struct ionic_nop_comp {
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/**
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* struct ionic_dev_init_cmd - Device init command
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* @opcode: opcode
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- * @type: device type
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+ * @type: Device type
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*/
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struct ionic_dev_init_cmd {
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u8 opcode;
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@@ -167,7 +168,7 @@ struct ionic_dev_init_cmd {
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/**
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* struct init_comp - Device init command completion
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- * @status: The status of the command (enum status_code)
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+ * @status: Status of the command (enum ionic_status_code)
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*/
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struct ionic_dev_init_comp {
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u8 status;
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@@ -185,7 +186,7 @@ struct ionic_dev_reset_cmd {
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/**
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* struct reset_comp - Reset command completion
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- * @status: The status of the command (enum status_code)
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+ * @status: Status of the command (enum ionic_status_code)
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*/
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struct ionic_dev_reset_comp {
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u8 status;
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@@ -206,8 +207,8 @@ struct ionic_dev_identify_cmd {
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};
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/**
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- * struct dev_identify_comp - Driver/device identify command completion
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- * @status: The status of the command (enum status_code)
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+ * struct ionic_dev_identify_comp - Driver/device identify command completion
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+ * @status: Status of the command (enum ionic_status_code)
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* @ver: Version of identify returned by device
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*/
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struct ionic_dev_identify_comp {
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@@ -226,8 +227,8 @@ enum ionic_os_type {
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};
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/**
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- * union drv_identity - driver identity information
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- * @os_type: OS type (see enum os_type)
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+ * union ionic_drv_identity - driver identity information
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+ * @os_type: OS type (see enum ionic_os_type)
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* @os_dist: OS distribution, numeric format
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* @os_dist_str: OS distribution, string format
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* @kernel_ver: Kernel version, numeric format
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@@ -243,26 +244,26 @@ union ionic_drv_identity {
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char kernel_ver_str[32];
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char driver_ver_str[32];
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};
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- __le32 words[512];
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+ __le32 words[478];
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};
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/**
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- * union dev_identity - device identity information
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+ * union ionic_dev_identity - device identity information
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* @version: Version of device identify
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* @type: Identify type (0 for now)
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* @nports: Number of ports provisioned
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* @nlifs: Number of LIFs provisioned
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* @nintrs: Number of interrupts provisioned
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* @ndbpgs_per_lif: Number of doorbell pages per LIF
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- * @intr_coal_mult: Interrupt coalescing multiplication factor.
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+ * @intr_coal_mult: Interrupt coalescing multiplication factor
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* Scale user-supplied interrupt coalescing
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* value in usecs to device units using:
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* device units = usecs * mult / div
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- * @intr_coal_div: Interrupt coalescing division factor.
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+ * @intr_coal_div: Interrupt coalescing division factor
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* Scale user-supplied interrupt coalescing
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* value in usecs to device units using:
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* device units = usecs * mult / div
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- *
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+ * @eq_count: Number of shared event queues
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*/
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union ionic_dev_identity {
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struct {
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@@ -276,8 +277,9 @@ union ionic_dev_identity {
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__le32 ndbpgs_per_lif;
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__le32 intr_coal_mult;
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__le32 intr_coal_div;
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+ __le32 eq_count;
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};
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- __le32 words[512];
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+ __le32 words[478];
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};
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enum ionic_lif_type {
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@@ -287,10 +289,10 @@ enum ionic_lif_type {
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};
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/**
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- * struct ionic_lif_identify_cmd - lif identify command
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+ * struct ionic_lif_identify_cmd - LIF identify command
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* @opcode: opcode
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- * @type: lif type (enum lif_type)
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- * @ver: version of identify returned by device
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+ * @type: LIF type (enum ionic_lif_type)
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+ * @ver: Version of identify returned by device
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*/
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struct ionic_lif_identify_cmd {
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u8 opcode;
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@@ -300,9 +302,9 @@ struct ionic_lif_identify_cmd {
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};
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/**
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- * struct ionic_lif_identify_comp - lif identify command completion
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- * @status: status of the command (enum status_code)
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- * @ver: version of identify returned by device
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+ * struct ionic_lif_identify_comp - LIF identify command completion
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+ * @status: Status of the command (enum ionic_status_code)
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+ * @ver: Version of identify returned by device
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*/
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struct ionic_lif_identify_comp {
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u8 status;
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@@ -310,13 +312,24 @@ struct ionic_lif_identify_comp {
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u8 rsvd2[14];
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};
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+/**
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+ * enum ionic_lif_capability - LIF capabilities
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+ * @IONIC_LIF_CAP_ETH: LIF supports Ethernet
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+ * @IONIC_LIF_CAP_RDMA: LIF support RDMA
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+ */
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enum ionic_lif_capability {
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IONIC_LIF_CAP_ETH = BIT(0),
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IONIC_LIF_CAP_RDMA = BIT(1),
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};
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/**
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- * Logical Queue Types
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+ * enum ionic_logical_qtype - Logical Queue Types
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+ * @IONIC_QTYPE_ADMINQ: Administrative Queue
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+ * @IONIC_QTYPE_NOTIFYQ: Notify Queue
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+ * @IONIC_QTYPE_RXQ: Receive Queue
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+ * @IONIC_QTYPE_TXQ: Transmit Queue
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+ * @IONIC_QTYPE_EQ: Event Queue
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+ * @IONIC_QTYPE_MAX: Max queue type supported
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*/
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enum ionic_logical_qtype {
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IONIC_QTYPE_ADMINQ = 0,
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@@ -328,10 +341,10 @@ enum ionic_logical_qtype {
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};
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/**
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- * struct ionic_lif_logical_qtype - Descriptor of logical to hardware queue type.
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- * @qtype: Hardware Queue Type.
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- * @qid_count: Number of Queue IDs of the logical type.
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- * @qid_base: Minimum Queue ID of the logical type.
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+ * struct ionic_lif_logical_qtype - Descriptor of logical to HW queue type
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+ * @qtype: Hardware Queue Type
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+ * @qid_count: Number of Queue IDs of the logical type
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+ * @qid_base: Minimum Queue ID of the logical type
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*/
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struct ionic_lif_logical_qtype {
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u8 qtype;
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@@ -340,6 +353,12 @@ struct ionic_lif_logical_qtype {
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__le32 qid_base;
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};
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+/**
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+ * enum ionic_lif_state - LIF state
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+ * @IONIC_LIF_DISABLE: LIF disabled
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+ * @IONIC_LIF_ENABLE: LIF enabled
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+ * @IONIC_LIF_HANG_RESET: LIF hung, being reset
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+ */
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enum ionic_lif_state {
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IONIC_LIF_DISABLE = 0,
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IONIC_LIF_ENABLE = 1,
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@@ -347,13 +366,13 @@ enum ionic_lif_state {
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};
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1632d2 |
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1632d2 |
/**
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- * LIF configuration
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- * @state: lif state (enum lif_state)
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- * @name: lif name
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- * @mtu: mtu
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- * @mac: station mac address
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- * @features: features (enum ionic_eth_hw_features)
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- * @queue_count: queue counts per queue-type
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+ * union ionic_lif_config - LIF configuration
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+ * @state: LIF state (enum ionic_lif_state)
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+ * @name: LIF name
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+ * @mtu: MTU
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+ * @mac: Station MAC address
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+ * @features: Features (enum ionic_eth_hw_features)
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+ * @queue_count: Queue counts per queue-type
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*/
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1632d2 |
union ionic_lif_config {
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struct {
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1632d2 |
@@ -370,37 +389,36 @@ union ionic_lif_config {
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1632d2 |
};
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1632d2 |
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1632d2 |
/**
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1632d2 |
- * struct ionic_lif_identity - lif identity information (type-specific)
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1632d2 |
+ * struct ionic_lif_identity - LIF identity information (type-specific)
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1632d2 |
*
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- * @capabilities LIF capabilities
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1632d2 |
+ * @capabilities: LIF capabilities
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1632d2 |
*
|
|
|
1632d2 |
- * Ethernet:
|
|
|
1632d2 |
- * @version: Ethernet identify structure version.
|
|
|
1632d2 |
- * @features: Ethernet features supported on this lif type.
|
|
|
1632d2 |
- * @max_ucast_filters: Number of perfect unicast addresses supported.
|
|
|
1632d2 |
- * @max_mcast_filters: Number of perfect multicast addresses supported.
|
|
|
1632d2 |
- * @min_frame_size: Minimum size of frames to be sent
|
|
|
1632d2 |
- * @max_frame_size: Maximim size of frames to be sent
|
|
|
1632d2 |
- * @config: LIF config struct with features, mtu, mac, q counts
|
|
|
1632d2 |
+ * @eth: Ethernet identify structure
|
|
|
1632d2 |
+ * @version: Ethernet identify structure version
|
|
|
1632d2 |
+ * @max_ucast_filters: Number of perfect unicast addresses supported
|
|
|
1632d2 |
+ * @max_mcast_filters: Number of perfect multicast addresses supported
|
|
|
1632d2 |
+ * @min_frame_size: Minimum size of frames to be sent
|
|
|
1632d2 |
+ * @max_frame_size: Maximim size of frames to be sent
|
|
|
1632d2 |
+ * @config: LIF config struct with features, mtu, mac, q counts
|
|
|
1632d2 |
*
|
|
|
1632d2 |
- * RDMA:
|
|
|
1632d2 |
- * @version: RDMA version of opcodes and queue descriptors.
|
|
|
1632d2 |
- * @qp_opcodes: Number of rdma queue pair opcodes supported.
|
|
|
1632d2 |
- * @admin_opcodes: Number of rdma admin opcodes supported.
|
|
|
1632d2 |
- * @npts_per_lif: Page table size per lif
|
|
|
1632d2 |
- * @nmrs_per_lif: Number of memory regions per lif
|
|
|
1632d2 |
- * @nahs_per_lif: Number of address handles per lif
|
|
|
1632d2 |
- * @max_stride: Max work request stride.
|
|
|
1632d2 |
- * @cl_stride: Cache line stride.
|
|
|
1632d2 |
- * @pte_stride: Page table entry stride.
|
|
|
1632d2 |
- * @rrq_stride: Remote RQ work request stride.
|
|
|
1632d2 |
- * @rsq_stride: Remote SQ work request stride.
|
|
|
1632d2 |
+ * @rdma: RDMA identify structure
|
|
|
1632d2 |
+ * @version: RDMA version of opcodes and queue descriptors
|
|
|
1632d2 |
+ * @qp_opcodes: Number of RDMA queue pair opcodes supported
|
|
|
1632d2 |
+ * @admin_opcodes: Number of RDMA admin opcodes supported
|
|
|
1632d2 |
+ * @npts_per_lif: Page table size per LIF
|
|
|
1632d2 |
+ * @nmrs_per_lif: Number of memory regions per LIF
|
|
|
1632d2 |
+ * @nahs_per_lif: Number of address handles per LIF
|
|
|
1632d2 |
+ * @max_stride: Max work request stride
|
|
|
1632d2 |
+ * @cl_stride: Cache line stride
|
|
|
1632d2 |
+ * @pte_stride: Page table entry stride
|
|
|
1632d2 |
+ * @rrq_stride: Remote RQ work request stride
|
|
|
1632d2 |
+ * @rsq_stride: Remote SQ work request stride
|
|
|
1632d2 |
* @dcqcn_profiles: Number of DCQCN profiles
|
|
|
1632d2 |
- * @aq_qtype: RDMA Admin Qtype.
|
|
|
1632d2 |
- * @sq_qtype: RDMA Send Qtype.
|
|
|
1632d2 |
- * @rq_qtype: RDMA Receive Qtype.
|
|
|
1632d2 |
- * @cq_qtype: RDMA Completion Qtype.
|
|
|
1632d2 |
- * @eq_qtype: RDMA Event Qtype.
|
|
|
1632d2 |
+ * @aq_qtype: RDMA Admin Qtype
|
|
|
1632d2 |
+ * @sq_qtype: RDMA Send Qtype
|
|
|
1632d2 |
+ * @rq_qtype: RDMA Receive Qtype
|
|
|
1632d2 |
+ * @cq_qtype: RDMA Completion Qtype
|
|
|
1632d2 |
+ * @eq_qtype: RDMA Event Qtype
|
|
|
1632d2 |
*/
|
|
|
1632d2 |
union ionic_lif_identity {
|
|
|
1632d2 |
struct {
|
|
|
1632d2 |
@@ -440,15 +458,15 @@ union ionic_lif_identity {
|
|
|
1632d2 |
struct ionic_lif_logical_qtype eq_qtype;
|
|
|
1632d2 |
} __packed rdma;
|
|
|
1632d2 |
} __packed;
|
|
|
1632d2 |
- __le32 words[512];
|
|
|
1632d2 |
+ __le32 words[478];
|
|
|
1632d2 |
};
|
|
|
1632d2 |
|
|
|
1632d2 |
/**
|
|
|
1632d2 |
* struct ionic_lif_init_cmd - LIF init command
|
|
|
1632d2 |
- * @opcode: opcode
|
|
|
1632d2 |
- * @type: LIF type (enum lif_type)
|
|
|
1632d2 |
+ * @opcode: Opcode
|
|
|
1632d2 |
+ * @type: LIF type (enum ionic_lif_type)
|
|
|
1632d2 |
* @index: LIF index
|
|
|
1632d2 |
- * @info_pa: destination address for lif info (struct ionic_lif_info)
|
|
|
1632d2 |
+ * @info_pa: Destination address for LIF info (struct ionic_lif_info)
|
|
|
1632d2 |
*/
|
|
|
1632d2 |
struct ionic_lif_init_cmd {
|
|
|
1632d2 |
u8 opcode;
|
|
|
1632d2 |
@@ -461,7 +479,8 @@ struct ionic_lif_init_cmd {
|
|
|
1632d2 |
|
|
|
1632d2 |
/**
|
|
|
1632d2 |
* struct ionic_lif_init_comp - LIF init command completion
|
|
|
1632d2 |
- * @status: The status of the command (enum status_code)
|
|
|
1632d2 |
+ * @status: Status of the command (enum ionic_status_code)
|
|
|
1632d2 |
+ * @hw_index: Hardware index of the initialized LIF
|
|
|
1632d2 |
*/
|
|
|
1632d2 |
struct ionic_lif_init_comp {
|
|
|
1632d2 |
u8 status;
|
|
|
1632d2 |
@@ -534,10 +553,10 @@ union ionic_q_identity {
|
|
|
1632d2 |
* struct ionic_q_init_cmd - Queue init command
|
|
|
1632d2 |
* @opcode: opcode
|
|
|
1632d2 |
* @type: Logical queue type
|
|
|
1632d2 |
- * @ver: Queue version (defines opcode/descriptor scope)
|
|
|
1632d2 |
+ * @ver: Queue type version
|
|
|
1632d2 |
* @lif_index: LIF index
|
|
|
1632d2 |
- * @index: (lif, qtype) relative admin queue index
|
|
|
1632d2 |
- * @intr_index: Interrupt control register index
|
|
|
1632d2 |
+ * @index: (LIF, qtype) relative admin queue index
|
|
|
1632d2 |
+ * @intr_index: Interrupt control register index, or Event queue index
|
|
|
1632d2 |
* @pid: Process ID
|
|
|
1632d2 |
* @flags:
|
|
|
1632d2 |
* IRQ: Interrupt requested on completion
|
|
|
1632d2 |
@@ -555,12 +574,11 @@ union ionic_q_identity {
|
|
|
1632d2 |
* descriptors. Values of ring_size <2 and >16 are
|
|
|
1632d2 |
* reserved.
|
|
|
1632d2 |
* EQ: Enable the Event Queue
|
|
|
1632d2 |
- * @cos: Class of service for this queue.
|
|
|
1632d2 |
+ * @cos: Class of service for this queue
|
|
|
1632d2 |
* @ring_size: Queue ring size, encoded as a log2(size)
|
|
|
1632d2 |
* @ring_base: Queue ring base address
|
|
|
1632d2 |
* @cq_ring_base: Completion queue ring base address
|
|
|
1632d2 |
* @sg_ring_base: Scatter/Gather ring base address
|
|
|
1632d2 |
- * @eq_index: Event queue index
|
|
|
1632d2 |
*/
|
|
|
1632d2 |
struct ionic_q_init_cmd {
|
|
|
1632d2 |
u8 opcode;
|
|
|
1632d2 |
@@ -577,29 +595,27 @@ struct ionic_q_init_cmd {
|
|
|
1632d2 |
#define IONIC_QINIT_F_ENA 0x02 /* Enable the queue */
|
|
|
1632d2 |
#define IONIC_QINIT_F_SG 0x04 /* Enable scatter/gather on the queue */
|
|
|
1632d2 |
#define IONIC_QINIT_F_EQ 0x08 /* Enable event queue */
|
|
|
1632d2 |
-#define IONIC_QINIT_F_DEBUG 0x80 /* Enable queue debugging */
|
|
|
1632d2 |
+#define IONIC_QINIT_F_CMB 0x10 /* Enable cmb-based queue */
|
|
|
1632d2 |
+#define IONIC_QINIT_F_DEBUG 0x80 /* Enable queue debugging */
|
|
|
1632d2 |
u8 cos;
|
|
|
1632d2 |
u8 ring_size;
|
|
|
1632d2 |
__le64 ring_base;
|
|
|
1632d2 |
__le64 cq_ring_base;
|
|
|
1632d2 |
__le64 sg_ring_base;
|
|
|
1632d2 |
- __le32 eq_index;
|
|
|
1632d2 |
- u8 rsvd2[16];
|
|
|
1632d2 |
+ u8 rsvd2[20];
|
|
|
1632d2 |
} __packed;
|
|
|
1632d2 |
|
|
|
1632d2 |
/**
|
|
|
1632d2 |
* struct ionic_q_init_comp - Queue init command completion
|
|
|
1632d2 |
- * @status: The status of the command (enum status_code)
|
|
|
1632d2 |
- * @ver: Queue version (defines opcode/descriptor scope)
|
|
|
1632d2 |
- * @comp_index: The index in the descriptor ring for which this
|
|
|
1632d2 |
- * is the completion.
|
|
|
1632d2 |
+ * @status: Status of the command (enum ionic_status_code)
|
|
|
1632d2 |
+ * @comp_index: Index in the descriptor ring for which this is the completion
|
|
|
1632d2 |
* @hw_index: Hardware Queue ID
|
|
|
1632d2 |
* @hw_type: Hardware Queue type
|
|
|
1632d2 |
* @color: Color
|
|
|
1632d2 |
*/
|
|
|
1632d2 |
struct ionic_q_init_comp {
|
|
|
1632d2 |
u8 status;
|
|
|
1632d2 |
- u8 ver;
|
|
|
1632d2 |
+ u8 rsvd;
|
|
|
1632d2 |
__le16 comp_index;
|
|
|
1632d2 |
__le32 hw_index;
|
|
|
1632d2 |
u8 hw_type;
|
|
|
1632d2 |
@@ -620,10 +636,9 @@ enum ionic_txq_desc_opcode {
|
|
|
1632d2 |
|
|
|
1632d2 |
/**
|
|
|
1632d2 |
* struct ionic_txq_desc - Ethernet Tx queue descriptor format
|
|
|
1632d2 |
- * @opcode: Tx operation, see TXQ_DESC_OPCODE_*:
|
|
|
1632d2 |
+ * @cmd: Tx operation, see IONIC_TXQ_DESC_OPCODE_*:
|
|
|
1632d2 |
*
|
|
|
1632d2 |
* IONIC_TXQ_DESC_OPCODE_CSUM_NONE:
|
|
|
1632d2 |
- *
|
|
|
1632d2 |
* Non-offload send. No segmentation,
|
|
|
1632d2 |
* fragmentation or checksum calc/insertion is
|
|
|
1632d2 |
* performed by device; packet is prepared
|
|
|
1632d2 |
@@ -631,7 +646,6 @@ enum ionic_txq_desc_opcode {
|
|
|
1632d2 |
* no further manipulation from device.
|
|
|
1632d2 |
*
|
|
|
1632d2 |
* IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL:
|
|
|
1632d2 |
- *
|
|
|
1632d2 |
* Offload 16-bit L4 checksum
|
|
|
1632d2 |
* calculation/insertion. The device will
|
|
|
1632d2 |
* calculate the L4 checksum value and
|
|
|
1632d2 |
@@ -640,14 +654,16 @@ enum ionic_txq_desc_opcode {
|
|
|
1632d2 |
* is calculated starting at @csum_start bytes
|
|
|
1632d2 |
* into the packet to the end of the packet.
|
|
|
1632d2 |
* The checksum insertion position is given
|
|
|
1632d2 |
- * in @csum_offset. This feature is only
|
|
|
1632d2 |
- * applicable to protocols such as TCP, UDP
|
|
|
1632d2 |
- * and ICMP where a standard (i.e. the
|
|
|
1632d2 |
- * 'IP-style' checksum) one's complement
|
|
|
1632d2 |
- * 16-bit checksum is used, using an IP
|
|
|
1632d2 |
- * pseudo-header to seed the calculation.
|
|
|
1632d2 |
- * Software will preload the L4 checksum
|
|
|
1632d2 |
- * field with the IP pseudo-header checksum.
|
|
|
1632d2 |
+ * in @csum_offset, which is the offset from
|
|
|
1632d2 |
+ * @csum_start to the checksum field in the L4
|
|
|
1632d2 |
+ * header. This feature is only applicable to
|
|
|
1632d2 |
+ * protocols such as TCP, UDP and ICMP where a
|
|
|
1632d2 |
+ * standard (i.e. the 'IP-style' checksum)
|
|
|
1632d2 |
+ * one's complement 16-bit checksum is used,
|
|
|
1632d2 |
+ * using an IP pseudo-header to seed the
|
|
|
1632d2 |
+ * calculation. Software will preload the L4
|
|
|
1632d2 |
+ * checksum field with the IP pseudo-header
|
|
|
1632d2 |
+ * checksum.
|
|
|
1632d2 |
*
|
|
|
1632d2 |
* For tunnel encapsulation, @csum_start and
|
|
|
1632d2 |
* @csum_offset refer to the inner L4
|
|
|
1632d2 |
@@ -663,7 +679,6 @@ enum ionic_txq_desc_opcode {
|
|
|
1632d2 |
* offloads.txt for more info).
|
|
|
1632d2 |
*
|
|
|
1632d2 |
* IONIC_TXQ_DESC_OPCODE_CSUM_HW:
|
|
|
1632d2 |
- *
|
|
|
1632d2 |
* Offload 16-bit checksum computation to hardware.
|
|
|
1632d2 |
* If @csum_l3 is set then the packet's L3 checksum is
|
|
|
1632d2 |
* updated. Similarly, if @csum_l4 is set the the L4
|
|
|
1632d2 |
@@ -671,7 +686,6 @@ enum ionic_txq_desc_opcode {
|
|
|
1632d2 |
* checksums are also updated.
|
|
|
1632d2 |
*
|
|
|
1632d2 |
* IONIC_TXQ_DESC_OPCODE_TSO:
|
|
|
1632d2 |
- *
|
|
|
1632d2 |
* Device preforms TCP segmentation offload
|
|
|
1632d2 |
* (TSO). @hdr_len is the number of bytes
|
|
|
1632d2 |
* to the end of TCP header (the offset to
|
|
|
1632d2 |
@@ -698,40 +712,41 @@ enum ionic_txq_desc_opcode {
|
|
|
1632d2 |
* clear CWR in remaining segments.
|
|
|
1632d2 |
* @flags:
|
|
|
1632d2 |
* vlan:
|
|
|
1632d2 |
- * Insert an L2 VLAN header using @vlan_tci.
|
|
|
1632d2 |
+ * Insert an L2 VLAN header using @vlan_tci
|
|
|
1632d2 |
* encap:
|
|
|
1632d2 |
- * Calculate encap header checksum.
|
|
|
1632d2 |
+ * Calculate encap header checksum
|
|
|
1632d2 |
* csum_l3:
|
|
|
1632d2 |
- * Compute L3 header checksum.
|
|
|
1632d2 |
+ * Compute L3 header checksum
|
|
|
1632d2 |
* csum_l4:
|
|
|
1632d2 |
- * Compute L4 header checksum.
|
|
|
1632d2 |
+ * Compute L4 header checksum
|
|
|
1632d2 |
* tso_sot:
|
|
|
1632d2 |
* TSO start
|
|
|
1632d2 |
* tso_eot:
|
|
|
1632d2 |
* TSO end
|
|
|
1632d2 |
* @num_sg_elems: Number of scatter-gather elements in SG
|
|
|
1632d2 |
* descriptor
|
|
|
1632d2 |
- * @addr: First data buffer's DMA address.
|
|
|
1632d2 |
- * (Subsequent data buffers are on txq_sg_desc).
|
|
|
1632d2 |
+ * @addr: First data buffer's DMA address
|
|
|
1632d2 |
+ * (Subsequent data buffers are on txq_sg_desc)
|
|
|
1632d2 |
* @len: First data buffer's length, in bytes
|
|
|
1632d2 |
* @vlan_tci: VLAN tag to insert in the packet (if requested
|
|
|
1632d2 |
* by @V-bit). Includes .1p and .1q tags
|
|
|
1632d2 |
* @hdr_len: Length of packet headers, including
|
|
|
1632d2 |
- * encapsulating outer header, if applicable.
|
|
|
1632d2 |
- * Valid for opcodes TXQ_DESC_OPCODE_CALC_CSUM and
|
|
|
1632d2 |
- * TXQ_DESC_OPCODE_TSO. Should be set to zero for
|
|
|
1632d2 |
+ * encapsulating outer header, if applicable
|
|
|
1632d2 |
+ * Valid for opcodes IONIC_TXQ_DESC_OPCODE_CALC_CSUM and
|
|
|
1632d2 |
+ * IONIC_TXQ_DESC_OPCODE_TSO. Should be set to zero for
|
|
|
1632d2 |
* all other modes. For
|
|
|
1632d2 |
- * TXQ_DESC_OPCODE_CALC_CSUM, @hdr_len is length
|
|
|
1632d2 |
+ * IONIC_TXQ_DESC_OPCODE_CALC_CSUM, @hdr_len is length
|
|
|
1632d2 |
* of headers up to inner-most L4 header. For
|
|
|
1632d2 |
- * TXQ_DESC_OPCODE_TSO, @hdr_len is up to
|
|
|
1632d2 |
+ * IONIC_TXQ_DESC_OPCODE_TSO, @hdr_len is up to
|
|
|
1632d2 |
* inner-most L4 payload, so inclusive of
|
|
|
1632d2 |
* inner-most L4 header.
|
|
|
1632d2 |
- * @mss: Desired MSS value for TSO. Only applicable for
|
|
|
1632d2 |
- * TXQ_DESC_OPCODE_TSO.
|
|
|
1632d2 |
- * @csum_start: Offset into inner-most L3 header of checksum
|
|
|
1632d2 |
- * @csum_offset: Offset into inner-most L4 header of checksum
|
|
|
1632d2 |
+ * @mss: Desired MSS value for TSO; only applicable for
|
|
|
1632d2 |
+ * IONIC_TXQ_DESC_OPCODE_TSO
|
|
|
1632d2 |
+ * @csum_start: Offset from packet to first byte checked in L4 checksum
|
|
|
1632d2 |
+ * @csum_offset: Offset from csum_start to L4 checksum field
|
|
|
1632d2 |
*/
|
|
|
1632d2 |
-
|
|
|
1632d2 |
+struct ionic_txq_desc {
|
|
|
1632d2 |
+ __le64 cmd;
|
|
|
1632d2 |
#define IONIC_TXQ_DESC_OPCODE_MASK 0xf
|
|
|
1632d2 |
#define IONIC_TXQ_DESC_OPCODE_SHIFT 4
|
|
|
1632d2 |
#define IONIC_TXQ_DESC_FLAGS_MASK 0xf
|
|
|
1632d2 |
@@ -753,8 +768,6 @@ enum ionic_txq_desc_opcode {
|
|
|
1632d2 |
#define IONIC_TXQ_DESC_FLAG_TSO_SOT 0x4
|
|
|
1632d2 |
#define IONIC_TXQ_DESC_FLAG_TSO_EOT 0x8
|
|
|
1632d2 |
|
|
|
1632d2 |
-struct ionic_txq_desc {
|
|
|
1632d2 |
- __le64 cmd;
|
|
|
1632d2 |
__le16 len;
|
|
|
1632d2 |
union {
|
|
|
1632d2 |
__le16 vlan_tci;
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1632d2 |
@@ -823,10 +836,9 @@ struct ionic_txq_sg_desc_v1 {
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1632d2 |
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1632d2 |
/**
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1632d2 |
* struct ionic_txq_comp - Ethernet transmit queue completion descriptor
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1632d2 |
- * @status: The status of the command (enum status_code)
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1632d2 |
- * @comp_index: The index in the descriptor ring for which this
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1632d2 |
- * is the completion.
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1632d2 |
- * @color: Color bit.
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1632d2 |
+ * @status: Status of the command (enum ionic_status_code)
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1632d2 |
+ * @comp_index: Index in the descriptor ring for which this is the completion
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1632d2 |
+ * @color: Color bit
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1632d2 |
*/
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1632d2 |
struct ionic_txq_comp {
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1632d2 |
u8 status;
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1632d2 |
@@ -843,16 +855,15 @@ enum ionic_rxq_desc_opcode {
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1632d2 |
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1632d2 |
/**
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1632d2 |
* struct ionic_rxq_desc - Ethernet Rx queue descriptor format
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1632d2 |
- * @opcode: Rx operation, see RXQ_DESC_OPCODE_*:
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1632d2 |
- *
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1632d2 |
- * RXQ_DESC_OPCODE_SIMPLE:
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1632d2 |
+ * @opcode: Rx operation, see IONIC_RXQ_DESC_OPCODE_*:
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1632d2 |
*
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1632d2 |
+ * IONIC_RXQ_DESC_OPCODE_SIMPLE:
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1632d2 |
* Receive full packet into data buffer
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1632d2 |
* starting at @addr. Results of
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1632d2 |
* receive, including actual bytes received,
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1632d2 |
* are recorded in Rx completion descriptor.
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1632d2 |
*
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1632d2 |
- * @len: Data buffer's length, in bytes.
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1632d2 |
+ * @len: Data buffer's length, in bytes
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1632d2 |
* @addr: Data buffer's DMA address
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1632d2 |
*/
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1632d2 |
struct ionic_rxq_desc {
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1632d2 |
@@ -863,7 +874,7 @@ struct ionic_rxq_desc {
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1632d2 |
};
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1632d2 |
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1632d2 |
/**
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1632d2 |
- * struct ionic_rxq_sg_desc - Receive scatter-gather (SG) descriptor element
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1632d2 |
+ * struct ionic_rxq_sg_elem - Receive scatter-gather (SG) descriptor element
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1632d2 |
* @addr: DMA address of SG element data buffer
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1632d2 |
* @len: Length of SG element data buffer, in bytes
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1632d2 |
*/
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1632d2 |
@@ -885,12 +896,11 @@ struct ionic_rxq_sg_desc {
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1632d2 |
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1632d2 |
/**
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1632d2 |
* struct ionic_rxq_comp - Ethernet receive queue completion descriptor
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1632d2 |
- * @status: The status of the command (enum status_code)
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1632d2 |
+ * @status: Status of the command (enum ionic_status_code)
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1632d2 |
* @num_sg_elems: Number of SG elements used by this descriptor
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1632d2 |
- * @comp_index: The index in the descriptor ring for which this
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1632d2 |
- * is the completion.
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1632d2 |
+ * @comp_index: Index in the descriptor ring for which this is the completion
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1632d2 |
* @rss_hash: 32-bit RSS hash
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1632d2 |
- * @csum: 16-bit sum of the packet's L2 payload.
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1632d2 |
+ * @csum: 16-bit sum of the packet's L2 payload
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1632d2 |
* If the packet's L2 payload is odd length, an extra
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1632d2 |
* zero-value byte is included in the @csum calculation but
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1632d2 |
* not included in @len.
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1632d2 |
@@ -898,33 +908,51 @@ struct ionic_rxq_sg_desc {
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1632d2 |
* set. Includes .1p and .1q tags.
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1632d2 |
* @len: Received packet length, in bytes. Excludes FCS.
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1632d2 |
* @csum_calc L2 payload checksum is computed or not
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1632d2 |
- * @csum_tcp_ok: The TCP checksum calculated by the device
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1632d2 |
- * matched the checksum in the receive packet's
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1632d2 |
- * TCP header
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1632d2 |
- * @csum_tcp_bad: The TCP checksum calculated by the device did
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1632d2 |
- * not match the checksum in the receive packet's
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1632d2 |
- * TCP header.
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1632d2 |
- * @csum_udp_ok: The UDP checksum calculated by the device
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1632d2 |
- * matched the checksum in the receive packet's
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1632d2 |
- * UDP header
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1632d2 |
- * @csum_udp_bad: The UDP checksum calculated by the device did
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1632d2 |
- * not match the checksum in the receive packet's
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1632d2 |
- * UDP header.
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1632d2 |
- * @csum_ip_ok: The IPv4 checksum calculated by the device
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1632d2 |
- * matched the checksum in the receive packet's
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1632d2 |
- * first IPv4 header. If the receive packet
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1632d2 |
- * contains both a tunnel IPv4 header and a
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1632d2 |
- * transport IPv4 header, the device validates the
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1632d2 |
- * checksum for the both IPv4 headers.
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1632d2 |
- * @csum_ip_bad: The IPv4 checksum calculated by the device did
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1632d2 |
- * not match the checksum in the receive packet's
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1632d2 |
- * first IPv4 header. If the receive packet
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1632d2 |
- * contains both a tunnel IPv4 header and a
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1632d2 |
- * transport IPv4 header, the device validates the
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1632d2 |
- * checksum for both IP headers.
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1632d2 |
- * @VLAN: VLAN header was stripped and placed in @vlan_tci.
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1632d2 |
- * @pkt_type: Packet type
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1632d2 |
- * @color: Color bit.
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1632d2 |
+ * @csum_flags: See IONIC_RXQ_COMP_CSUM_F_*:
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1632d2 |
+ *
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1632d2 |
+ * IONIC_RXQ_COMP_CSUM_F_TCP_OK:
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1632d2 |
+ * The TCP checksum calculated by the device
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1632d2 |
+ * matched the checksum in the receive packet's
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1632d2 |
+ * TCP header.
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1632d2 |
+ *
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1632d2 |
+ * IONIC_RXQ_COMP_CSUM_F_TCP_BAD:
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1632d2 |
+ * The TCP checksum calculated by the device did
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1632d2 |
+ * not match the checksum in the receive packet's
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1632d2 |
+ * TCP header.
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1632d2 |
+ *
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1632d2 |
+ * IONIC_RXQ_COMP_CSUM_F_UDP_OK:
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1632d2 |
+ * The UDP checksum calculated by the device
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1632d2 |
+ * matched the checksum in the receive packet's
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1632d2 |
+ * UDP header
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1632d2 |
+ *
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1632d2 |
+ * IONIC_RXQ_COMP_CSUM_F_UDP_BAD:
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1632d2 |
+ * The UDP checksum calculated by the device did
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1632d2 |
+ * not match the checksum in the receive packet's
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1632d2 |
+ * UDP header.
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1632d2 |
+ *
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1632d2 |
+ * IONIC_RXQ_COMP_CSUM_F_IP_OK:
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1632d2 |
+ * The IPv4 checksum calculated by the device
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1632d2 |
+ * matched the checksum in the receive packet's
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1632d2 |
+ * first IPv4 header. If the receive packet
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1632d2 |
+ * contains both a tunnel IPv4 header and a
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1632d2 |
+ * transport IPv4 header, the device validates the
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1632d2 |
+ * checksum for the both IPv4 headers.
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1632d2 |
+ *
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1632d2 |
+ * IONIC_RXQ_COMP_CSUM_F_IP_BAD:
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1632d2 |
+ * The IPv4 checksum calculated by the device did
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1632d2 |
+ * not match the checksum in the receive packet's
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1632d2 |
+ * first IPv4 header. If the receive packet
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1632d2 |
+ * contains both a tunnel IPv4 header and a
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1632d2 |
+ * transport IPv4 header, the device validates the
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1632d2 |
+ * checksum for both IP headers.
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1632d2 |
+ *
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1632d2 |
+ * IONIC_RXQ_COMP_CSUM_F_VLAN:
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1632d2 |
+ * The VLAN header was stripped and placed in @vlan_tci.
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1632d2 |
+ *
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1632d2 |
+ * IONIC_RXQ_COMP_CSUM_F_CALC:
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1632d2 |
+ * The checksum was calculated by the device.
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1632d2 |
+ *
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1632d2 |
+ * @pkt_type_color: Packet type and color bit; see IONIC_RXQ_COMP_PKT_TYPE_MASK
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|
1632d2 |
*/
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1632d2 |
struct ionic_rxq_comp {
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1632d2 |
u8 status;
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|
1632d2 |
@@ -971,8 +999,8 @@ enum ionic_eth_hw_features {
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1632d2 |
IONIC_ETH_HW_TSO_ECN = BIT(10),
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1632d2 |
IONIC_ETH_HW_TSO_GRE = BIT(11),
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1632d2 |
IONIC_ETH_HW_TSO_GRE_CSUM = BIT(12),
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1632d2 |
- IONIC_ETH_HW_TSO_IPXIP4 = BIT(13),
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1632d2 |
- IONIC_ETH_HW_TSO_IPXIP6 = BIT(14),
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|
1632d2 |
+ IONIC_ETH_HW_TSO_IPXIP4 = BIT(13),
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|
1632d2 |
+ IONIC_ETH_HW_TSO_IPXIP6 = BIT(14),
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|
1632d2 |
IONIC_ETH_HW_TSO_UDP = BIT(15),
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1632d2 |
IONIC_ETH_HW_TSO_UDP_CSUM = BIT(16),
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1632d2 |
};
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1632d2 |
@@ -1003,7 +1031,10 @@ enum q_control_oper {
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1632d2 |
};
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1632d2 |
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1632d2 |
/**
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1632d2 |
- * Physical connection type
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1632d2 |
+ * enum ionic_phy_type - Physical connection type
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1632d2 |
+ * @IONIC_PHY_TYPE_NONE: No PHY installed
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1632d2 |
+ * @IONIC_PHY_TYPE_COPPER: Copper PHY
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|
1632d2 |
+ * @IONIC_PHY_TYPE_FIBER: Fiber PHY
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|
1632d2 |
*/
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1632d2 |
enum ionic_phy_type {
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1632d2 |
IONIC_PHY_TYPE_NONE = 0,
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1632d2 |
@@ -1012,18 +1043,23 @@ enum ionic_phy_type {
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1632d2 |
};
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1632d2 |
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1632d2 |
/**
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|
1632d2 |
- * Transceiver status
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|
1632d2 |
+ * enum ionic_xcvr_state - Transceiver status
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1632d2 |
+ * @IONIC_XCVR_STATE_REMOVED: Transceiver removed
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1632d2 |
+ * @IONIC_XCVR_STATE_INSERTED: Transceiver inserted
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1632d2 |
+ * @IONIC_XCVR_STATE_PENDING: Transceiver pending
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1632d2 |
+ * @IONIC_XCVR_STATE_SPROM_READ: Transceiver data read
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|
1632d2 |
+ * @IONIC_XCVR_STATE_SPROM_READ_ERR: Transceiver data read error
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|
1632d2 |
*/
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1632d2 |
enum ionic_xcvr_state {
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1632d2 |
IONIC_XCVR_STATE_REMOVED = 0,
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1632d2 |
IONIC_XCVR_STATE_INSERTED = 1,
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1632d2 |
IONIC_XCVR_STATE_PENDING = 2,
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1632d2 |
IONIC_XCVR_STATE_SPROM_READ = 3,
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1632d2 |
- IONIC_XCVR_STATE_SPROM_READ_ERR = 4,
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|
1632d2 |
+ IONIC_XCVR_STATE_SPROM_READ_ERR = 4,
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1632d2 |
};
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1632d2 |
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1632d2 |
/**
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|
1632d2 |
- * Supported link modes
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1632d2 |
+ * enum ionic_xcvr_pid - Supported link modes
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1632d2 |
*/
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1632d2 |
enum ionic_xcvr_pid {
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|
1632d2 |
IONIC_XCVR_PID_UNKNOWN = 0,
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|
1632d2 |
@@ -1057,64 +1093,83 @@ enum ionic_xcvr_pid {
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|
1632d2 |
IONIC_XCVR_PID_SFP_10GBASE_CU = 68,
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1632d2 |
IONIC_XCVR_PID_QSFP_100G_CWDM4 = 69,
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1632d2 |
IONIC_XCVR_PID_QSFP_100G_PSM4 = 70,
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|
1632d2 |
+ IONIC_XCVR_PID_SFP_25GBASE_ACC = 71,
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1632d2 |
};
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1632d2 |
|
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|
1632d2 |
/**
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|
1632d2 |
- * Port types
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|
1632d2 |
+ * enum ionic_port_type - Port types
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|
1632d2 |
+ * @IONIC_PORT_TYPE_NONE: Port type not configured
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|
1632d2 |
+ * @IONIC_PORT_TYPE_ETH: Port carries ethernet traffic (inband)
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|
1632d2 |
+ * @IONIC_PORT_TYPE_MGMT: Port carries mgmt traffic (out-of-band)
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|
1632d2 |
*/
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1632d2 |
enum ionic_port_type {
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|
1632d2 |
- IONIC_PORT_TYPE_NONE = 0, /* port type not configured */
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|
1632d2 |
- IONIC_PORT_TYPE_ETH = 1, /* port carries ethernet traffic (inband) */
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|
1632d2 |
- IONIC_PORT_TYPE_MGMT = 2, /* port carries mgmt traffic (out-of-band) */
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|
1632d2 |
+ IONIC_PORT_TYPE_NONE = 0,
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1632d2 |
+ IONIC_PORT_TYPE_ETH = 1,
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|
1632d2 |
+ IONIC_PORT_TYPE_MGMT = 2,
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|
1632d2 |
};
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1632d2 |
|
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|
1632d2 |
/**
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|
1632d2 |
- * Port config state
|
|
|
1632d2 |
+ * enum ionic_port_admin_state - Port config state
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|
1632d2 |
+ * @IONIC_PORT_ADMIN_STATE_NONE: Port admin state not configured
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|
1632d2 |
+ * @IONIC_PORT_ADMIN_STATE_DOWN: Port admin disabled
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|
1632d2 |
+ * @IONIC_PORT_ADMIN_STATE_UP: Port admin enabled
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|
1632d2 |
*/
|
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|
1632d2 |
enum ionic_port_admin_state {
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|
1632d2 |
- IONIC_PORT_ADMIN_STATE_NONE = 0, /* port admin state not configured */
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|
1632d2 |
- IONIC_PORT_ADMIN_STATE_DOWN = 1, /* port is admin disabled */
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|
1632d2 |
- IONIC_PORT_ADMIN_STATE_UP = 2, /* port is admin enabled */
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|
1632d2 |
+ IONIC_PORT_ADMIN_STATE_NONE = 0,
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|
1632d2 |
+ IONIC_PORT_ADMIN_STATE_DOWN = 1,
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|
1632d2 |
+ IONIC_PORT_ADMIN_STATE_UP = 2,
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|
1632d2 |
};
|
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|
1632d2 |
|
|
|
1632d2 |
/**
|
|
|
1632d2 |
- * Port operational status
|
|
|
1632d2 |
+ * enum ionic_port_oper_status - Port operational status
|
|
|
1632d2 |
+ * @IONIC_PORT_OPER_STATUS_NONE: Port disabled
|
|
|
1632d2 |
+ * @IONIC_PORT_OPER_STATUS_UP: Port link status up
|
|
|
1632d2 |
+ * @IONIC_PORT_OPER_STATUS_DOWN: Port link status down
|
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|
1632d2 |
*/
|
|
|
1632d2 |
enum ionic_port_oper_status {
|
|
|
1632d2 |
- IONIC_PORT_OPER_STATUS_NONE = 0, /* port is disabled */
|
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|
1632d2 |
- IONIC_PORT_OPER_STATUS_UP = 1, /* port is linked up */
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|
|
1632d2 |
- IONIC_PORT_OPER_STATUS_DOWN = 2, /* port link status is down */
|
|
|
1632d2 |
+ IONIC_PORT_OPER_STATUS_NONE = 0,
|
|
|
1632d2 |
+ IONIC_PORT_OPER_STATUS_UP = 1,
|
|
|
1632d2 |
+ IONIC_PORT_OPER_STATUS_DOWN = 2,
|
|
|
1632d2 |
};
|
|
|
1632d2 |
|
|
|
1632d2 |
/**
|
|
|
1632d2 |
- * Ethernet Forward error correction (fec) modes
|
|
|
1632d2 |
+ * enum ionic_port_fec_type - Ethernet Forward error correction (FEC) modes
|
|
|
1632d2 |
+ * @IONIC_PORT_FEC_TYPE_NONE: FEC Disabled
|
|
|
1632d2 |
+ * @IONIC_PORT_FEC_TYPE_FC: FireCode FEC
|
|
|
1632d2 |
+ * @IONIC_PORT_FEC_TYPE_RS: ReedSolomon FEC
|
|
|
1632d2 |
*/
|
|
|
1632d2 |
enum ionic_port_fec_type {
|
|
|
1632d2 |
- IONIC_PORT_FEC_TYPE_NONE = 0, /* Disabled */
|
|
|
1632d2 |
- IONIC_PORT_FEC_TYPE_FC = 1, /* FireCode */
|
|
|
1632d2 |
- IONIC_PORT_FEC_TYPE_RS = 2, /* ReedSolomon */
|
|
|
1632d2 |
+ IONIC_PORT_FEC_TYPE_NONE = 0,
|
|
|
1632d2 |
+ IONIC_PORT_FEC_TYPE_FC = 1,
|
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|
1632d2 |
+ IONIC_PORT_FEC_TYPE_RS = 2,
|
|
|
1632d2 |
};
|
|
|
1632d2 |
|
|
|
1632d2 |
/**
|
|
|
1632d2 |
- * Ethernet pause (flow control) modes
|
|
|
1632d2 |
+ * enum ionic_port_pause_type - Ethernet pause (flow control) modes
|
|
|
1632d2 |
+ * @IONIC_PORT_PAUSE_TYPE_NONE: Disable Pause
|
|
|
1632d2 |
+ * @IONIC_PORT_PAUSE_TYPE_LINK: Link level pause
|
|
|
1632d2 |
+ * @IONIC_PORT_PAUSE_TYPE_PFC: Priority-Flow Control
|
|
|
1632d2 |
*/
|
|
|
1632d2 |
enum ionic_port_pause_type {
|
|
|
1632d2 |
- IONIC_PORT_PAUSE_TYPE_NONE = 0, /* Disable Pause */
|
|
|
1632d2 |
- IONIC_PORT_PAUSE_TYPE_LINK = 1, /* Link level pause */
|
|
|
1632d2 |
- IONIC_PORT_PAUSE_TYPE_PFC = 2, /* Priority-Flow control */
|
|
|
1632d2 |
+ IONIC_PORT_PAUSE_TYPE_NONE = 0,
|
|
|
1632d2 |
+ IONIC_PORT_PAUSE_TYPE_LINK = 1,
|
|
|
1632d2 |
+ IONIC_PORT_PAUSE_TYPE_PFC = 2,
|
|
|
1632d2 |
};
|
|
|
1632d2 |
|
|
|
1632d2 |
/**
|
|
|
1632d2 |
- * Loopback modes
|
|
|
1632d2 |
+ * enum ionic_port_loopback_mode - Loopback modes
|
|
|
1632d2 |
+ * @IONIC_PORT_LOOPBACK_MODE_NONE: Disable loopback
|
|
|
1632d2 |
+ * @IONIC_PORT_LOOPBACK_MODE_MAC: MAC loopback
|
|
|
1632d2 |
+ * @IONIC_PORT_LOOPBACK_MODE_PHY: PHY/SerDes loopback
|
|
|
1632d2 |
*/
|
|
|
1632d2 |
enum ionic_port_loopback_mode {
|
|
|
1632d2 |
- IONIC_PORT_LOOPBACK_MODE_NONE = 0, /* Disable loopback */
|
|
|
1632d2 |
- IONIC_PORT_LOOPBACK_MODE_MAC = 1, /* MAC loopback */
|
|
|
1632d2 |
- IONIC_PORT_LOOPBACK_MODE_PHY = 2, /* PHY/Serdes loopback */
|
|
|
1632d2 |
+ IONIC_PORT_LOOPBACK_MODE_NONE = 0,
|
|
|
1632d2 |
+ IONIC_PORT_LOOPBACK_MODE_MAC = 1,
|
|
|
1632d2 |
+ IONIC_PORT_LOOPBACK_MODE_PHY = 2,
|
|
|
1632d2 |
};
|
|
|
1632d2 |
|
|
|
1632d2 |
/**
|
|
|
1632d2 |
- * Transceiver Status information
|
|
|
1632d2 |
+ * struct ionic_xcvr_status - Transceiver Status information
|
|
|
1632d2 |
* @state: Transceiver status (enum ionic_xcvr_state)
|
|
|
1632d2 |
* @phy: Physical connection type (enum ionic_phy_type)
|
|
|
1632d2 |
* @pid: Transceiver link mode (enum pid)
|
|
|
1632d2 |
@@ -1128,7 +1183,7 @@ struct ionic_xcvr_status {
|
|
|
1632d2 |
};
|
|
|
1632d2 |
|
|
|
1632d2 |
/**
|
|
|
1632d2 |
- * Port configuration
|
|
|
1632d2 |
+ * union ionic_port_config - Port configuration
|
|
|
1632d2 |
* @speed: port speed (in Mbps)
|
|
|
1632d2 |
* @mtu: mtu
|
|
|
1632d2 |
* @state: port admin state (enum port_admin_state)
|
|
|
1632d2 |
@@ -1161,17 +1216,21 @@ union ionic_port_config {
|
|
|
1632d2 |
};
|
|
|
1632d2 |
|
|
|
1632d2 |
/**
|
|
|
1632d2 |
- * Port Status information
|
|
|
1632d2 |
+ * struct ionic_port_status - Port Status information
|
|
|
1632d2 |
* @status: link status (enum ionic_port_oper_status)
|
|
|
1632d2 |
* @id: port id
|
|
|
1632d2 |
* @speed: link speed (in Mbps)
|
|
|
1632d2 |
+ * @link_down_count: number of times link went from from up to down
|
|
|
1632d2 |
+ * @fec_type: fec type (enum ionic_port_fec_type)
|
|
|
1632d2 |
* @xcvr: tranceiver status
|
|
|
1632d2 |
*/
|
|
|
1632d2 |
struct ionic_port_status {
|
|
|
1632d2 |
__le32 id;
|
|
|
1632d2 |
__le32 speed;
|
|
|
1632d2 |
u8 status;
|
|
|
1632d2 |
- u8 rsvd[51];
|
|
|
1632d2 |
+ __le16 link_down_count;
|
|
|
1632d2 |
+ u8 fec_type;
|
|
|
1632d2 |
+ u8 rsvd[48];
|
|
|
1632d2 |
struct ionic_xcvr_status xcvr;
|
|
|
1632d2 |
} __packed;
|
|
|
1632d2 |
|
|
|
1632d2 |
@@ -1190,7 +1249,7 @@ struct ionic_port_identify_cmd {
|
|
|
1632d2 |
|
|
|
1632d2 |
/**
|
|
|
1632d2 |
* struct ionic_port_identify_comp - Port identify command completion
|
|
|
1632d2 |
- * @status: The status of the command (enum status_code)
|
|
|
1632d2 |
+ * @status: Status of the command (enum ionic_status_code)
|
|
|
1632d2 |
* @ver: Version of identify returned by device
|
|
|
1632d2 |
*/
|
|
|
1632d2 |
struct ionic_port_identify_comp {
|
|
|
1632d2 |
@@ -1215,7 +1274,7 @@ struct ionic_port_init_cmd {
|
|
|
1632d2 |
|
|
|
1632d2 |
/**
|
|
|
1632d2 |
* struct ionic_port_init_comp - Port initialization command completion
|
|
|
1632d2 |
- * @status: The status of the command (enum status_code)
|
|
|
1632d2 |
+ * @status: Status of the command (enum ionic_status_code)
|
|
|
1632d2 |
*/
|
|
|
1632d2 |
struct ionic_port_init_comp {
|
|
|
1632d2 |
u8 status;
|
|
|
1632d2 |
@@ -1235,7 +1294,7 @@ struct ionic_port_reset_cmd {
|
|
|
1632d2 |
|
|
|
1632d2 |
/**
|
|
|
1632d2 |
* struct ionic_port_reset_comp - Port reset command completion
|
|
|
1632d2 |
- * @status: The status of the command (enum status_code)
|
|
|
1632d2 |
+ * @status: Status of the command (enum ionic_status_code)
|
|
|
1632d2 |
*/
|
|
|
1632d2 |
struct ionic_port_reset_comp {
|
|
|
1632d2 |
u8 status;
|
|
|
1632d2 |
@@ -1243,15 +1302,23 @@ struct ionic_port_reset_comp {
|
|
|
1632d2 |
};
|
|
|
1632d2 |
|
|
|
1632d2 |
/**
|
|
|
1632d2 |
- * enum stats_ctl_cmd - List of commands for stats control
|
|
|
1632d2 |
+ * enum ionic_stats_ctl_cmd - List of commands for stats control
|
|
|
1632d2 |
+ * @IONIC_STATS_CTL_RESET: Reset statistics
|
|
|
1632d2 |
*/
|
|
|
1632d2 |
enum ionic_stats_ctl_cmd {
|
|
|
1632d2 |
IONIC_STATS_CTL_RESET = 0,
|
|
|
1632d2 |
};
|
|
|
1632d2 |
|
|
|
1632d2 |
-
|
|
|
1632d2 |
/**
|
|
|
1632d2 |
* enum ionic_port_attr - List of device attributes
|
|
|
1632d2 |
+ * @IONIC_PORT_ATTR_STATE: Port state attribute
|
|
|
1632d2 |
+ * @IONIC_PORT_ATTR_SPEED: Port speed attribute
|
|
|
1632d2 |
+ * @IONIC_PORT_ATTR_MTU: Port MTU attribute
|
|
|
1632d2 |
+ * @IONIC_PORT_ATTR_AUTONEG: Port autonegotation attribute
|
|
|
1632d2 |
+ * @IONIC_PORT_ATTR_FEC: Port FEC attribute
|
|
|
1632d2 |
+ * @IONIC_PORT_ATTR_PAUSE: Port pause attribute
|
|
|
1632d2 |
+ * @IONIC_PORT_ATTR_LOOPBACK: Port loopback attribute
|
|
|
1632d2 |
+ * @IONIC_PORT_ATTR_STATS_CTRL: Port statistics control attribute
|
|
|
1632d2 |
*/
|
|
|
1632d2 |
enum ionic_port_attr {
|
|
|
1632d2 |
IONIC_PORT_ATTR_STATE = 0,
|
|
|
1632d2 |
@@ -1266,9 +1333,17 @@ enum ionic_port_attr {
|
|
|
1632d2 |
|
|
|
1632d2 |
/**
|
|
|
1632d2 |
* struct ionic_port_setattr_cmd - Set port attributes on the NIC
|
|
|
1632d2 |
- * @opcode: Opcode
|
|
|
1632d2 |
- * @index: port index
|
|
|
1632d2 |
- * @attr: Attribute type (enum ionic_port_attr)
|
|
|
1632d2 |
+ * @opcode: Opcode
|
|
|
1632d2 |
+ * @index: Port index
|
|
|
1632d2 |
+ * @attr: Attribute type (enum ionic_port_attr)
|
|
|
1632d2 |
+ * @state: Port state
|
|
|
1632d2 |
+ * @speed: Port speed
|
|
|
1632d2 |
+ * @mtu: Port MTU
|
|
|
1632d2 |
+ * @an_enable: Port autonegotiation setting
|
|
|
1632d2 |
+ * @fec_type: Port FEC type setting
|
|
|
1632d2 |
+ * @pause_type: Port pause type setting
|
|
|
1632d2 |
+ * @loopback_mode: Port loopback mode
|
|
|
1632d2 |
+ * @stats_ctl: Port stats setting
|
|
|
1632d2 |
*/
|
|
|
1632d2 |
struct ionic_port_setattr_cmd {
|
|
|
1632d2 |
u8 opcode;
|
|
|
1632d2 |
@@ -1283,14 +1358,14 @@ struct ionic_port_setattr_cmd {
|
|
|
1632d2 |
u8 fec_type;
|
|
|
1632d2 |
u8 pause_type;
|
|
|
1632d2 |
u8 loopback_mode;
|
|
|
1632d2 |
- u8 stats_ctl;
|
|
|
1632d2 |
+ u8 stats_ctl;
|
|
|
1632d2 |
u8 rsvd2[60];
|
|
|
1632d2 |
};
|
|
|
1632d2 |
};
|
|
|
1632d2 |
|
|
|
1632d2 |
/**
|
|
|
1632d2 |
* struct ionic_port_setattr_comp - Port set attr command completion
|
|
|
1632d2 |
- * @status: The status of the command (enum status_code)
|
|
|
1632d2 |
+ * @status: Status of the command (enum ionic_status_code)
|
|
|
1632d2 |
* @color: Color bit
|
|
|
1632d2 |
*/
|
|
|
1632d2 |
struct ionic_port_setattr_comp {
|
|
|
1632d2 |
@@ -1314,8 +1389,15 @@ struct ionic_port_getattr_cmd {
|
|
|
1632d2 |
|
|
|
1632d2 |
/**
|
|
|
1632d2 |
* struct ionic_port_getattr_comp - Port get attr command completion
|
|
|
1632d2 |
- * @status: The status of the command (enum status_code)
|
|
|
1632d2 |
- * @color: Color bit
|
|
|
1632d2 |
+ * @status: Status of the command (enum ionic_status_code)
|
|
|
1632d2 |
+ * @state: Port state
|
|
|
1632d2 |
+ * @speed: Port speed
|
|
|
1632d2 |
+ * @mtu: Port MTU
|
|
|
1632d2 |
+ * @an_enable: Port autonegotiation setting
|
|
|
1632d2 |
+ * @fec_type: Port FEC type setting
|
|
|
1632d2 |
+ * @pause_type: Port pause type setting
|
|
|
1632d2 |
+ * @loopback_mode: Port loopback mode
|
|
|
1632d2 |
+ * @color: Color bit
|
|
|
1632d2 |
*/
|
|
|
1632d2 |
struct ionic_port_getattr_comp {
|
|
|
1632d2 |
u8 status;
|
|
|
1632d2 |
@@ -1334,12 +1416,12 @@ struct ionic_port_getattr_comp {
|
|
|
1632d2 |
};
|
|
|
1632d2 |
|
|
|
1632d2 |
/**
|
|
|
1632d2 |
- * struct ionic_lif_status - Lif status register
|
|
|
1632d2 |
+ * struct ionic_lif_status - LIF status register
|
|
|
1632d2 |
* @eid: most recent NotifyQ event id
|
|
|
1632d2 |
- * @port_num: port the lif is connected to
|
|
|
1632d2 |
+ * @port_num: port the LIF is connected to
|
|
|
1632d2 |
* @link_status: port status (enum ionic_port_oper_status)
|
|
|
1632d2 |
* @link_speed: speed of link in Mbps
|
|
|
1632d2 |
- * @link_down_count: number of times link status changes
|
|
|
1632d2 |
+ * @link_down_count: number of times link went from up to down
|
|
|
1632d2 |
*/
|
|
|
1632d2 |
struct ionic_lif_status {
|
|
|
1632d2 |
__le64 eid;
|
|
|
1632d2 |
@@ -1373,6 +1455,9 @@ enum ionic_dev_state {
|
|
|
1632d2 |
|
|
|
1632d2 |
/**
|
|
|
1632d2 |
* enum ionic_dev_attr - List of device attributes
|
|
|
1632d2 |
+ * @IONIC_DEV_ATTR_STATE: Device state attribute
|
|
|
1632d2 |
+ * @IONIC_DEV_ATTR_NAME: Device name attribute
|
|
|
1632d2 |
+ * @IONIC_DEV_ATTR_FEATURES: Device feature attributes
|
|
|
1632d2 |
*/
|
|
|
1632d2 |
enum ionic_dev_attr {
|
|
|
1632d2 |
IONIC_DEV_ATTR_STATE = 0,
|
|
|
1632d2 |
@@ -1402,7 +1487,7 @@ struct ionic_dev_setattr_cmd {
|
|
|
1632d2 |
|
|
|
1632d2 |
/**
|
|
|
1632d2 |
* struct ionic_dev_setattr_comp - Device set attr command completion
|
|
|
1632d2 |
- * @status: The status of the command (enum status_code)
|
|
|
1632d2 |
+ * @status: Status of the command (enum ionic_status_code)
|
|
|
1632d2 |
* @features: Device features
|
|
|
1632d2 |
* @color: Color bit
|
|
|
1632d2 |
*/
|
|
|
1632d2 |
@@ -1429,7 +1514,7 @@ struct ionic_dev_getattr_cmd {
|
|
|
1632d2 |
|
|
|
1632d2 |
/**
|
|
|
1632d2 |
* struct ionic_dev_setattr_comp - Device set attr command completion
|
|
|
1632d2 |
- * @status: The status of the command (enum status_code)
|
|
|
1632d2 |
+ * @status: Status of the command (enum ionic_status_code)
|
|
|
1632d2 |
* @features: Device features
|
|
|
1632d2 |
* @color: Color bit
|
|
|
1632d2 |
*/
|
|
|
1632d2 |
@@ -1459,6 +1544,13 @@ enum ionic_rss_hash_types {
|
|
|
1632d2 |
|
|
|
1632d2 |
/**
|
|
|
1632d2 |
* enum ionic_lif_attr - List of LIF attributes
|
|
|
1632d2 |
+ * @IONIC_LIF_ATTR_STATE: LIF state attribute
|
|
|
1632d2 |
+ * @IONIC_LIF_ATTR_NAME: LIF name attribute
|
|
|
1632d2 |
+ * @IONIC_LIF_ATTR_MTU: LIF MTU attribute
|
|
|
1632d2 |
+ * @IONIC_LIF_ATTR_MAC: LIF MAC attribute
|
|
|
1632d2 |
+ * @IONIC_LIF_ATTR_FEATURES: LIF features attribute
|
|
|
1632d2 |
+ * @IONIC_LIF_ATTR_RSS: LIF RSS attribute
|
|
|
1632d2 |
+ * @IONIC_LIF_ATTR_STATS_CTRL: LIF statistics control attribute
|
|
|
1632d2 |
*/
|
|
|
1632d2 |
enum ionic_lif_attr {
|
|
|
1632d2 |
IONIC_LIF_ATTR_STATE = 0,
|
|
|
1632d2 |
@@ -1473,18 +1565,18 @@ enum ionic_lif_attr {
|
|
|
1632d2 |
/**
|
|
|
1632d2 |
* struct ionic_lif_setattr_cmd - Set LIF attributes on the NIC
|
|
|
1632d2 |
* @opcode: Opcode
|
|
|
1632d2 |
- * @type: Attribute type (enum ionic_lif_attr)
|
|
|
1632d2 |
+ * @attr: Attribute type (enum ionic_lif_attr)
|
|
|
1632d2 |
* @index: LIF index
|
|
|
1632d2 |
- * @state: lif state (enum lif_state)
|
|
|
1632d2 |
+ * @state: LIF state (enum ionic_lif_state)
|
|
|
1632d2 |
* @name: The netdev name string, 0 terminated
|
|
|
1632d2 |
* @mtu: Mtu
|
|
|
1632d2 |
* @mac: Station mac
|
|
|
1632d2 |
* @features: Features (enum ionic_eth_hw_features)
|
|
|
1632d2 |
* @rss: RSS properties
|
|
|
1632d2 |
- * @types: The hash types to enable (see rss_hash_types).
|
|
|
1632d2 |
- * @key: The hash secret key.
|
|
|
1632d2 |
- * @addr: Address for the indirection table shared memory.
|
|
|
1632d2 |
- * @stats_ctl: stats control commands (enum stats_ctl_cmd)
|
|
|
1632d2 |
+ * @types: The hash types to enable (see rss_hash_types)
|
|
|
1632d2 |
+ * @key: The hash secret key
|
|
|
1632d2 |
+ * @addr: Address for the indirection table shared memory
|
|
|
1632d2 |
+ * @stats_ctl: stats control commands (enum ionic_stats_ctl_cmd)
|
|
|
1632d2 |
*/
|
|
|
1632d2 |
struct ionic_lif_setattr_cmd {
|
|
|
1632d2 |
u8 opcode;
|
|
|
1632d2 |
@@ -1502,16 +1594,15 @@ struct ionic_lif_setattr_cmd {
|
|
|
1632d2 |
u8 rsvd[6];
|
|
|
1632d2 |
__le64 addr;
|
|
|
1632d2 |
} rss;
|
|
|
1632d2 |
- u8 stats_ctl;
|
|
|
1632d2 |
+ u8 stats_ctl;
|
|
|
1632d2 |
u8 rsvd[60];
|
|
|
1632d2 |
} __packed;
|
|
|
1632d2 |
};
|
|
|
1632d2 |
|
|
|
1632d2 |
/**
|
|
|
1632d2 |
* struct ionic_lif_setattr_comp - LIF set attr command completion
|
|
|
1632d2 |
- * @status: The status of the command (enum status_code)
|
|
|
1632d2 |
- * @comp_index: The index in the descriptor ring for which this
|
|
|
1632d2 |
- * is the completion.
|
|
|
1632d2 |
+ * @status: Status of the command (enum ionic_status_code)
|
|
|
1632d2 |
+ * @comp_index: Index in the descriptor ring for which this is the completion
|
|
|
1632d2 |
* @features: features (enum ionic_eth_hw_features)
|
|
|
1632d2 |
* @color: Color bit
|
|
|
1632d2 |
*/
|
|
|
1632d2 |
@@ -1541,10 +1632,9 @@ struct ionic_lif_getattr_cmd {
|
|
|
1632d2 |
|
|
|
1632d2 |
/**
|
|
|
1632d2 |
* struct ionic_lif_getattr_comp - LIF get attr command completion
|
|
|
1632d2 |
- * @status: The status of the command (enum status_code)
|
|
|
1632d2 |
- * @comp_index: The index in the descriptor ring for which this
|
|
|
1632d2 |
- * is the completion.
|
|
|
1632d2 |
- * @state: lif state (enum lif_state)
|
|
|
1632d2 |
+ * @status: Status of the command (enum ionic_status_code)
|
|
|
1632d2 |
+ * @comp_index: Index in the descriptor ring for which this is the completion
|
|
|
1632d2 |
+ * @state: LIF state (enum ionic_lif_state)
|
|
|
1632d2 |
* @name: The netdev name string, 0 terminated
|
|
|
1632d2 |
* @mtu: Mtu
|
|
|
1632d2 |
* @mac: Station mac
|
|
|
1632d2 |
@@ -1566,11 +1656,12 @@ struct ionic_lif_getattr_comp {
|
|
|
1632d2 |
};
|
|
|
1632d2 |
|
|
|
1632d2 |
enum ionic_rx_mode {
|
|
|
1632d2 |
- IONIC_RX_MODE_F_UNICAST = BIT(0),
|
|
|
1632d2 |
- IONIC_RX_MODE_F_MULTICAST = BIT(1),
|
|
|
1632d2 |
- IONIC_RX_MODE_F_BROADCAST = BIT(2),
|
|
|
1632d2 |
- IONIC_RX_MODE_F_PROMISC = BIT(3),
|
|
|
1632d2 |
- IONIC_RX_MODE_F_ALLMULTI = BIT(4),
|
|
|
1632d2 |
+ IONIC_RX_MODE_F_UNICAST = BIT(0),
|
|
|
1632d2 |
+ IONIC_RX_MODE_F_MULTICAST = BIT(1),
|
|
|
1632d2 |
+ IONIC_RX_MODE_F_BROADCAST = BIT(2),
|
|
|
1632d2 |
+ IONIC_RX_MODE_F_PROMISC = BIT(3),
|
|
|
1632d2 |
+ IONIC_RX_MODE_F_ALLMULTI = BIT(4),
|
|
|
1632d2 |
+ IONIC_RX_MODE_F_RDMA_SNIFFER = BIT(5),
|
|
|
1632d2 |
};
|
|
|
1632d2 |
|
|
|
1632d2 |
/**
|
|
|
1632d2 |
@@ -1578,11 +1669,12 @@ enum ionic_rx_mode {
|
|
|
1632d2 |
* @opcode: opcode
|
|
|
1632d2 |
* @lif_index: LIF index
|
|
|
1632d2 |
* @rx_mode: Rx mode flags:
|
|
|
1632d2 |
- * IONIC_RX_MODE_F_UNICAST: Accept known unicast packets.
|
|
|
1632d2 |
- * IONIC_RX_MODE_F_MULTICAST: Accept known multicast packets.
|
|
|
1632d2 |
- * IONIC_RX_MODE_F_BROADCAST: Accept broadcast packets.
|
|
|
1632d2 |
- * IONIC_RX_MODE_F_PROMISC: Accept any packets.
|
|
|
1632d2 |
- * IONIC_RX_MODE_F_ALLMULTI: Accept any multicast packets.
|
|
|
1632d2 |
+ * IONIC_RX_MODE_F_UNICAST: Accept known unicast packets
|
|
|
1632d2 |
+ * IONIC_RX_MODE_F_MULTICAST: Accept known multicast packets
|
|
|
1632d2 |
+ * IONIC_RX_MODE_F_BROADCAST: Accept broadcast packets
|
|
|
1632d2 |
+ * IONIC_RX_MODE_F_PROMISC: Accept any packets
|
|
|
1632d2 |
+ * IONIC_RX_MODE_F_ALLMULTI: Accept any multicast packets
|
|
|
1632d2 |
+ * IONIC_RX_MODE_F_RDMA_SNIFFER: Sniff RDMA packets
|
|
|
1632d2 |
*/
|
|
|
1632d2 |
struct ionic_rx_mode_set_cmd {
|
|
|
1632d2 |
u8 opcode;
|
|
|
1632d2 |
@@ -1606,9 +1698,14 @@ enum ionic_rx_filter_match_type {
|
|
|
1632d2 |
* @qtype: Queue type
|
|
|
1632d2 |
* @lif_index: LIF index
|
|
|
1632d2 |
* @qid: Queue ID
|
|
|
1632d2 |
- * @match: Rx filter match type. (See IONIC_RX_FILTER_MATCH_xxx)
|
|
|
1632d2 |
- * @vlan: VLAN ID
|
|
|
1632d2 |
- * @addr: MAC address (network-byte order)
|
|
|
1632d2 |
+ * @match: Rx filter match type (see IONIC_RX_FILTER_MATCH_xxx)
|
|
|
1632d2 |
+ * @vlan: VLAN filter
|
|
|
1632d2 |
+ * @vlan: VLAN ID
|
|
|
1632d2 |
+ * @mac: MAC filter
|
|
|
1632d2 |
+ * @addr: MAC address (network-byte order)
|
|
|
1632d2 |
+ * @mac_vlan: MACVLAN filter
|
|
|
1632d2 |
+ * @vlan: VLAN ID
|
|
|
1632d2 |
+ * @addr: MAC address (network-byte order)
|
|
|
1632d2 |
*/
|
|
|
1632d2 |
struct ionic_rx_filter_add_cmd {
|
|
|
1632d2 |
u8 opcode;
|
|
|
1632d2 |
@@ -1633,11 +1730,10 @@ struct ionic_rx_filter_add_cmd {
|
|
|
1632d2 |
|
|
|
1632d2 |
/**
|
|
|
1632d2 |
* struct ionic_rx_filter_add_comp - Add LIF Rx filter command completion
|
|
|
1632d2 |
- * @status: The status of the command (enum status_code)
|
|
|
1632d2 |
- * @comp_index: The index in the descriptor ring for which this
|
|
|
1632d2 |
- * is the completion.
|
|
|
1632d2 |
+ * @status: Status of the command (enum ionic_status_code)
|
|
|
1632d2 |
+ * @comp_index: Index in the descriptor ring for which this is the completion
|
|
|
1632d2 |
* @filter_id: Filter ID
|
|
|
1632d2 |
- * @color: Color bit.
|
|
|
1632d2 |
+ * @color: Color bit
|
|
|
1632d2 |
*/
|
|
|
1632d2 |
struct ionic_rx_filter_add_comp {
|
|
|
1632d2 |
u8 status;
|
|
|
1632d2 |
@@ -1664,63 +1760,6 @@ struct ionic_rx_filter_del_cmd {
|
|
|
1632d2 |
|
|
|
1632d2 |
typedef struct ionic_admin_comp ionic_rx_filter_del_comp;
|
|
|
1632d2 |
|
|
|
1632d2 |
-/**
|
|
|
1632d2 |
- * struct ionic_qos_identify_cmd - QoS identify command
|
|
|
1632d2 |
- * @opcode: opcode
|
|
|
1632d2 |
- * @ver: Highest version of identify supported by driver
|
|
|
1632d2 |
- *
|
|
|
1632d2 |
- */
|
|
|
1632d2 |
-struct ionic_qos_identify_cmd {
|
|
|
1632d2 |
- u8 opcode;
|
|
|
1632d2 |
- u8 ver;
|
|
|
1632d2 |
- u8 rsvd[62];
|
|
|
1632d2 |
-};
|
|
|
1632d2 |
-
|
|
|
1632d2 |
-/**
|
|
|
1632d2 |
- * struct ionic_qos_identify_comp - QoS identify command completion
|
|
|
1632d2 |
- * @status: The status of the command (enum status_code)
|
|
|
1632d2 |
- * @ver: Version of identify returned by device
|
|
|
1632d2 |
- */
|
|
|
1632d2 |
-struct ionic_qos_identify_comp {
|
|
|
1632d2 |
- u8 status;
|
|
|
1632d2 |
- u8 ver;
|
|
|
1632d2 |
- u8 rsvd[14];
|
|
|
1632d2 |
-};
|
|
|
1632d2 |
-
|
|
|
1632d2 |
-#define IONIC_QOS_CLASS_MAX 7
|
|
|
1632d2 |
-#define IONIC_QOS_CLASS_NAME_SZ 32
|
|
|
1632d2 |
-#define IONIC_QOS_DSCP_MAX_VALUES 64
|
|
|
1632d2 |
-
|
|
|
1632d2 |
-/**
|
|
|
1632d2 |
- * enum ionic_qos_class
|
|
|
1632d2 |
- */
|
|
|
1632d2 |
-enum ionic_qos_class {
|
|
|
1632d2 |
- IONIC_QOS_CLASS_DEFAULT = 0,
|
|
|
1632d2 |
- IONIC_QOS_CLASS_USER_DEFINED_1 = 1,
|
|
|
1632d2 |
- IONIC_QOS_CLASS_USER_DEFINED_2 = 2,
|
|
|
1632d2 |
- IONIC_QOS_CLASS_USER_DEFINED_3 = 3,
|
|
|
1632d2 |
- IONIC_QOS_CLASS_USER_DEFINED_4 = 4,
|
|
|
1632d2 |
- IONIC_QOS_CLASS_USER_DEFINED_5 = 5,
|
|
|
1632d2 |
- IONIC_QOS_CLASS_USER_DEFINED_6 = 6,
|
|
|
1632d2 |
-};
|
|
|
1632d2 |
-
|
|
|
1632d2 |
-/**
|
|
|
1632d2 |
- * enum ionic_qos_class_type - Traffic classification criteria
|
|
|
1632d2 |
- */
|
|
|
1632d2 |
-enum ionic_qos_class_type {
|
|
|
1632d2 |
- IONIC_QOS_CLASS_TYPE_NONE = 0,
|
|
|
1632d2 |
- IONIC_QOS_CLASS_TYPE_PCP = 1, /* Dot1Q pcp */
|
|
|
1632d2 |
- IONIC_QOS_CLASS_TYPE_DSCP = 2, /* IP dscp */
|
|
|
1632d2 |
-};
|
|
|
1632d2 |
-
|
|
|
1632d2 |
-/**
|
|
|
1632d2 |
- * enum ionic_qos_sched_type - Qos class scheduling type
|
|
|
1632d2 |
- */
|
|
|
1632d2 |
-enum ionic_qos_sched_type {
|
|
|
1632d2 |
- IONIC_QOS_SCHED_TYPE_STRICT = 0, /* Strict priority */
|
|
|
1632d2 |
- IONIC_QOS_SCHED_TYPE_DWRR = 1, /* Deficit weighted round-robin */
|
|
|
1632d2 |
-};
|
|
|
1632d2 |
-
|
|
|
1632d2 |
enum ionic_vf_attr {
|
|
|
1632d2 |
IONIC_VF_ATTR_SPOOFCHK = 1,
|
|
|
1632d2 |
IONIC_VF_ATTR_TRUST = 2,
|
|
|
1632d2 |
@@ -1732,26 +1771,29 @@ enum ionic_vf_attr {
|
|
|
1632d2 |
};
|
|
|
1632d2 |
|
|
|
1632d2 |
/**
|
|
|
1632d2 |
- * VF link status
|
|
|
1632d2 |
+ * enum ionic_vf_link_status - Virtual Function link status
|
|
|
1632d2 |
+ * @IONIC_VF_LINK_STATUS_AUTO: Use link state of the uplink
|
|
|
1632d2 |
+ * @IONIC_VF_LINK_STATUS_UP: Link always up
|
|
|
1632d2 |
+ * @IONIC_VF_LINK_STATUS_DOWN: Link always down
|
|
|
1632d2 |
*/
|
|
|
1632d2 |
enum ionic_vf_link_status {
|
|
|
1632d2 |
- IONIC_VF_LINK_STATUS_AUTO = 0, /* link state of the uplink */
|
|
|
1632d2 |
- IONIC_VF_LINK_STATUS_UP = 1, /* link is always up */
|
|
|
1632d2 |
- IONIC_VF_LINK_STATUS_DOWN = 2, /* link is always down */
|
|
|
1632d2 |
+ IONIC_VF_LINK_STATUS_AUTO = 0,
|
|
|
1632d2 |
+ IONIC_VF_LINK_STATUS_UP = 1,
|
|
|
1632d2 |
+ IONIC_VF_LINK_STATUS_DOWN = 2,
|
|
|
1632d2 |
};
|
|
|
1632d2 |
|
|
|
1632d2 |
/**
|
|
|
1632d2 |
* struct ionic_vf_setattr_cmd - Set VF attributes on the NIC
|
|
|
1632d2 |
* @opcode: Opcode
|
|
|
1632d2 |
- * @index: VF index
|
|
|
1632d2 |
* @attr: Attribute type (enum ionic_vf_attr)
|
|
|
1632d2 |
- * macaddr mac address
|
|
|
1632d2 |
- * vlanid vlan ID
|
|
|
1632d2 |
- * maxrate max Tx rate in Mbps
|
|
|
1632d2 |
- * spoofchk enable address spoof checking
|
|
|
1632d2 |
- * trust enable VF trust
|
|
|
1632d2 |
- * linkstate set link up or down
|
|
|
1632d2 |
- * stats_pa set DMA address for VF stats
|
|
|
1632d2 |
+ * @vf_index: VF index
|
|
|
1632d2 |
+ * @macaddr: mac address
|
|
|
1632d2 |
+ * @vlanid: vlan ID
|
|
|
1632d2 |
+ * @maxrate: max Tx rate in Mbps
|
|
|
1632d2 |
+ * @spoofchk: enable address spoof checking
|
|
|
1632d2 |
+ * @trust: enable VF trust
|
|
|
1632d2 |
+ * @linkstate: set link up or down
|
|
|
1632d2 |
+ * @stats_pa: set DMA address for VF stats
|
|
|
1632d2 |
*/
|
|
|
1632d2 |
struct ionic_vf_setattr_cmd {
|
|
|
1632d2 |
u8 opcode;
|
|
|
1632d2 |
@@ -1781,8 +1823,8 @@ struct ionic_vf_setattr_comp {
|
|
|
1632d2 |
/**
|
|
|
1632d2 |
* struct ionic_vf_getattr_cmd - Get VF attributes from the NIC
|
|
|
1632d2 |
* @opcode: Opcode
|
|
|
1632d2 |
- * @index: VF index
|
|
|
1632d2 |
* @attr: Attribute type (enum ionic_vf_attr)
|
|
|
1632d2 |
+ * @vf_index: VF index
|
|
|
1632d2 |
*/
|
|
|
1632d2 |
struct ionic_vf_getattr_cmd {
|
|
|
1632d2 |
u8 opcode;
|
|
|
1632d2 |
@@ -1809,19 +1851,85 @@ struct ionic_vf_getattr_comp {
|
|
|
1632d2 |
};
|
|
|
1632d2 |
|
|
|
1632d2 |
/**
|
|
|
1632d2 |
- * union ionic_qos_config - Qos configuration structure
|
|
|
1632d2 |
+ * struct ionic_qos_identify_cmd - QoS identify command
|
|
|
1632d2 |
+ * @opcode: opcode
|
|
|
1632d2 |
+ * @ver: Highest version of identify supported by driver
|
|
|
1632d2 |
+ *
|
|
|
1632d2 |
+ */
|
|
|
1632d2 |
+struct ionic_qos_identify_cmd {
|
|
|
1632d2 |
+ u8 opcode;
|
|
|
1632d2 |
+ u8 ver;
|
|
|
1632d2 |
+ u8 rsvd[62];
|
|
|
1632d2 |
+};
|
|
|
1632d2 |
+
|
|
|
1632d2 |
+/**
|
|
|
1632d2 |
+ * struct ionic_qos_identify_comp - QoS identify command completion
|
|
|
1632d2 |
+ * @status: Status of the command (enum ionic_status_code)
|
|
|
1632d2 |
+ * @ver: Version of identify returned by device
|
|
|
1632d2 |
+ */
|
|
|
1632d2 |
+struct ionic_qos_identify_comp {
|
|
|
1632d2 |
+ u8 status;
|
|
|
1632d2 |
+ u8 ver;
|
|
|
1632d2 |
+ u8 rsvd[14];
|
|
|
1632d2 |
+};
|
|
|
1632d2 |
+
|
|
|
1632d2 |
+#define IONIC_QOS_TC_MAX 8
|
|
|
1632d2 |
+/* Capri max supported, should be renamed. */
|
|
|
1632d2 |
+#define IONIC_QOS_CLASS_MAX 7
|
|
|
1632d2 |
+#define IONIC_QOS_PCP_MAX 8
|
|
|
1632d2 |
+#define IONIC_QOS_CLASS_NAME_SZ 32
|
|
|
1632d2 |
+#define IONIC_QOS_DSCP_MAX 64
|
|
|
1632d2 |
+#define IONIC_QOS_ALL_PCP 0xFF
|
|
|
1632d2 |
+
|
|
|
1632d2 |
+/**
|
|
|
1632d2 |
+ * enum ionic_qos_class
|
|
|
1632d2 |
+ */
|
|
|
1632d2 |
+enum ionic_qos_class {
|
|
|
1632d2 |
+ IONIC_QOS_CLASS_DEFAULT = 0,
|
|
|
1632d2 |
+ IONIC_QOS_CLASS_USER_DEFINED_1 = 1,
|
|
|
1632d2 |
+ IONIC_QOS_CLASS_USER_DEFINED_2 = 2,
|
|
|
1632d2 |
+ IONIC_QOS_CLASS_USER_DEFINED_3 = 3,
|
|
|
1632d2 |
+ IONIC_QOS_CLASS_USER_DEFINED_4 = 4,
|
|
|
1632d2 |
+ IONIC_QOS_CLASS_USER_DEFINED_5 = 5,
|
|
|
1632d2 |
+ IONIC_QOS_CLASS_USER_DEFINED_6 = 6,
|
|
|
1632d2 |
+};
|
|
|
1632d2 |
+
|
|
|
1632d2 |
+/**
|
|
|
1632d2 |
+ * enum ionic_qos_class_type - Traffic classification criteria
|
|
|
1632d2 |
+ * @IONIC_QOS_CLASS_TYPE_NONE: No QoS
|
|
|
1632d2 |
+ * @IONIC_QOS_CLASS_TYPE_PCP: Dot1Q PCP
|
|
|
1632d2 |
+ * @IONIC_QOS_CLASS_TYPE_DSCP: IP DSCP
|
|
|
1632d2 |
+ */
|
|
|
1632d2 |
+enum ionic_qos_class_type {
|
|
|
1632d2 |
+ IONIC_QOS_CLASS_TYPE_NONE = 0,
|
|
|
1632d2 |
+ IONIC_QOS_CLASS_TYPE_PCP = 1,
|
|
|
1632d2 |
+ IONIC_QOS_CLASS_TYPE_DSCP = 2,
|
|
|
1632d2 |
+};
|
|
|
1632d2 |
+
|
|
|
1632d2 |
+/**
|
|
|
1632d2 |
+ * enum ionic_qos_sched_type - QoS class scheduling type
|
|
|
1632d2 |
+ * @IONIC_QOS_SCHED_TYPE_STRICT: Strict priority
|
|
|
1632d2 |
+ * @IONIC_QOS_SCHED_TYPE_DWRR: Deficit weighted round-robin
|
|
|
1632d2 |
+ */
|
|
|
1632d2 |
+enum ionic_qos_sched_type {
|
|
|
1632d2 |
+ IONIC_QOS_SCHED_TYPE_STRICT = 0,
|
|
|
1632d2 |
+ IONIC_QOS_SCHED_TYPE_DWRR = 1,
|
|
|
1632d2 |
+};
|
|
|
1632d2 |
+
|
|
|
1632d2 |
+/**
|
|
|
1632d2 |
+ * union ionic_qos_config - QoS configuration structure
|
|
|
1632d2 |
* @flags: Configuration flags
|
|
|
1632d2 |
* IONIC_QOS_CONFIG_F_ENABLE enable
|
|
|
1632d2 |
- * IONIC_QOS_CONFIG_F_DROP drop/nodrop
|
|
|
1632d2 |
+ * IONIC_QOS_CONFIG_F_NO_DROP drop/nodrop
|
|
|
1632d2 |
* IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP enable dot1q pcp rewrite
|
|
|
1632d2 |
* IONIC_QOS_CONFIG_F_RW_IP_DSCP enable ip dscp rewrite
|
|
|
1632d2 |
- * @sched_type: Qos class scheduling type (enum ionic_qos_sched_type)
|
|
|
1632d2 |
- * @class_type: Qos class type (enum ionic_qos_class_type)
|
|
|
1632d2 |
- * @pause_type: Qos pause type (enum ionic_qos_pause_type)
|
|
|
1632d2 |
- * @name: Qos class name
|
|
|
1632d2 |
+ * @sched_type: QoS class scheduling type (enum ionic_qos_sched_type)
|
|
|
1632d2 |
+ * @class_type: QoS class type (enum ionic_qos_class_type)
|
|
|
1632d2 |
+ * @pause_type: QoS pause type (enum ionic_qos_pause_type)
|
|
|
1632d2 |
+ * @name: QoS class name
|
|
|
1632d2 |
* @mtu: MTU of the class
|
|
|
1632d2 |
- * @pfc_dot1q_pcp: Pcp value for pause frames (valid iff F_NODROP)
|
|
|
1632d2 |
- * @dwrr_weight: Qos class scheduling weight
|
|
|
1632d2 |
+ * @pfc_cos: Priority-Flow Control class of service
|
|
|
1632d2 |
+ * @dwrr_weight: QoS class scheduling weight
|
|
|
1632d2 |
* @strict_rlmt: Rate limit for strict priority scheduling
|
|
|
1632d2 |
* @rw_dot1q_pcp: Rewrite dot1q pcp to this value (valid iff F_RW_DOT1Q_PCP)
|
|
|
1632d2 |
* @rw_ip_dscp: Rewrite ip dscp to this value (valid iff F_RW_IP_DSCP)
|
|
|
1632d2 |
@@ -1832,7 +1940,8 @@ struct ionic_vf_getattr_comp {
|
|
|
1632d2 |
union ionic_qos_config {
|
|
|
1632d2 |
struct {
|
|
|
1632d2 |
#define IONIC_QOS_CONFIG_F_ENABLE BIT(0)
|
|
|
1632d2 |
-#define IONIC_QOS_CONFIG_F_DROP BIT(1)
|
|
|
1632d2 |
+#define IONIC_QOS_CONFIG_F_NO_DROP BIT(1)
|
|
|
1632d2 |
+/* Used to rewrite PCP or DSCP value. */
|
|
|
1632d2 |
#define IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP BIT(2)
|
|
|
1632d2 |
#define IONIC_QOS_CONFIG_F_RW_IP_DSCP BIT(3)
|
|
|
1632d2 |
u8 flags;
|
|
|
1632d2 |
@@ -1849,6 +1958,7 @@ union ionic_qos_config {
|
|
|
1632d2 |
__le64 strict_rlmt;
|
|
|
1632d2 |
};
|
|
|
1632d2 |
/* marking */
|
|
|
1632d2 |
+ /* Used to rewrite PCP or DSCP value. */
|
|
|
1632d2 |
union {
|
|
|
1632d2 |
u8 rw_dot1q_pcp;
|
|
|
1632d2 |
u8 rw_ip_dscp;
|
|
|
1632d2 |
@@ -1858,7 +1968,7 @@ union ionic_qos_config {
|
|
|
1632d2 |
u8 dot1q_pcp;
|
|
|
1632d2 |
struct {
|
|
|
1632d2 |
u8 ndscp;
|
|
|
1632d2 |
- u8 ip_dscp[IONIC_QOS_DSCP_MAX_VALUES];
|
|
|
1632d2 |
+ u8 ip_dscp[IONIC_QOS_DSCP_MAX];
|
|
|
1632d2 |
};
|
|
|
1632d2 |
};
|
|
|
1632d2 |
};
|
|
|
1632d2 |
@@ -1877,15 +1987,15 @@ union ionic_qos_identity {
|
|
|
1632d2 |
u8 version;
|
|
|
1632d2 |
u8 type;
|
|
|
1632d2 |
u8 rsvd[62];
|
|
|
1632d2 |
- union ionic_qos_config config[IONIC_QOS_CLASS_MAX];
|
|
|
1632d2 |
+ union ionic_qos_config config[IONIC_QOS_CLASS_MAX];
|
|
|
1632d2 |
};
|
|
|
1632d2 |
- __le32 words[512];
|
|
|
1632d2 |
+ __le32 words[478];
|
|
|
1632d2 |
};
|
|
|
1632d2 |
|
|
|
1632d2 |
/**
|
|
|
1632d2 |
- * struct qos_init_cmd - QoS config init command
|
|
|
1632d2 |
+ * struct ionic_qos_init_cmd - QoS config init command
|
|
|
1632d2 |
* @opcode: Opcode
|
|
|
1632d2 |
- * @group: Qos class id
|
|
|
1632d2 |
+ * @group: QoS class id
|
|
|
1632d2 |
* @info_pa: destination address for qos info
|
|
|
1632d2 |
*/
|
|
|
1632d2 |
struct ionic_qos_init_cmd {
|
|
|
1632d2 |
@@ -1899,8 +2009,9 @@ struct ionic_qos_init_cmd {
|
|
|
1632d2 |
typedef struct ionic_admin_comp ionic_qos_init_comp;
|
|
|
1632d2 |
|
|
|
1632d2 |
/**
|
|
|
1632d2 |
- * struct ionic_qos_reset_cmd - Qos config reset command
|
|
|
1632d2 |
+ * struct ionic_qos_reset_cmd - QoS config reset command
|
|
|
1632d2 |
* @opcode: Opcode
|
|
|
1632d2 |
+ * @group: QoS class id
|
|
|
1632d2 |
*/
|
|
|
1632d2 |
struct ionic_qos_reset_cmd {
|
|
|
1632d2 |
u8 opcode;
|
|
|
1632d2 |
@@ -1927,10 +2038,16 @@ struct ionic_fw_download_cmd {
|
|
|
1632d2 |
|
|
|
1632d2 |
typedef struct ionic_admin_comp ionic_fw_download_comp;
|
|
|
1632d2 |
|
|
|
1632d2 |
+/**
|
|
|
1632d2 |
+ * enum ionic_fw_control_oper - FW control operations
|
|
|
1632d2 |
+ * @IONIC_FW_RESET: Reset firmware
|
|
|
1632d2 |
+ * @IONIC_FW_INSTALL: Install firmware
|
|
|
1632d2 |
+ * @IONIC_FW_ACTIVATE: Activate firmware
|
|
|
1632d2 |
+ */
|
|
|
1632d2 |
enum ionic_fw_control_oper {
|
|
|
1632d2 |
- IONIC_FW_RESET = 0, /* Reset firmware */
|
|
|
1632d2 |
- IONIC_FW_INSTALL = 1, /* Install firmware */
|
|
|
1632d2 |
- IONIC_FW_ACTIVATE = 2, /* Activate firmware */
|
|
|
1632d2 |
+ IONIC_FW_RESET = 0,
|
|
|
1632d2 |
+ IONIC_FW_INSTALL = 1,
|
|
|
1632d2 |
+ IONIC_FW_ACTIVATE = 2,
|
|
|
1632d2 |
};
|
|
|
1632d2 |
|
|
|
1632d2 |
/**
|
|
|
1632d2 |
@@ -1949,8 +2066,10 @@ struct ionic_fw_control_cmd {
|
|
|
1632d2 |
|
|
|
1632d2 |
/**
|
|
|
1632d2 |
* struct ionic_fw_control_comp - Firmware control copletion
|
|
|
1632d2 |
- * @opcode: opcode
|
|
|
1632d2 |
- * @slot: slot where the firmware was installed
|
|
|
1632d2 |
+ * @status: Status of the command (enum ionic_status_code)
|
|
|
1632d2 |
+ * @comp_index: Index in the descriptor ring for which this is the completion
|
|
|
1632d2 |
+ * @slot: Slot where the firmware was installed
|
|
|
1632d2 |
+ * @color: Color bit
|
|
|
1632d2 |
*/
|
|
|
1632d2 |
struct ionic_fw_control_comp {
|
|
|
1632d2 |
u8 status;
|
|
|
1632d2 |
@@ -1968,11 +2087,11 @@ struct ionic_fw_control_comp {
|
|
|
1632d2 |
/**
|
|
|
1632d2 |
* struct ionic_rdma_reset_cmd - Reset RDMA LIF cmd
|
|
|
1632d2 |
* @opcode: opcode
|
|
|
1632d2 |
- * @lif_index: lif index
|
|
|
1632d2 |
+ * @lif_index: LIF index
|
|
|
1632d2 |
*
|
|
|
1632d2 |
- * There is no rdma specific dev command completion struct. Completion uses
|
|
|
1632d2 |
+ * There is no RDMA specific dev command completion struct. Completion uses
|
|
|
1632d2 |
* the common struct ionic_admin_comp. Only the status is indicated.
|
|
|
1632d2 |
- * Nonzero status means the LIF does not support rdma.
|
|
|
1632d2 |
+ * Nonzero status means the LIF does not support RDMA.
|
|
|
1632d2 |
**/
|
|
|
1632d2 |
struct ionic_rdma_reset_cmd {
|
|
|
1632d2 |
u8 opcode;
|
|
|
1632d2 |
@@ -1984,30 +2103,29 @@ struct ionic_rdma_reset_cmd {
|
|
|
1632d2 |
/**
|
|
|
1632d2 |
* struct ionic_rdma_queue_cmd - Create RDMA Queue command
|
|
|
1632d2 |
* @opcode: opcode, 52, 53
|
|
|
1632d2 |
- * @lif_index lif index
|
|
|
1632d2 |
- * @qid_ver: (qid | (rdma version << 24))
|
|
|
1632d2 |
+ * @lif_index: LIF index
|
|
|
1632d2 |
+ * @qid_ver: (qid | (RDMA version << 24))
|
|
|
1632d2 |
* @cid: intr, eq_id, or cq_id
|
|
|
1632d2 |
* @dbid: doorbell page id
|
|
|
1632d2 |
* @depth_log2: log base two of queue depth
|
|
|
1632d2 |
* @stride_log2: log base two of queue stride
|
|
|
1632d2 |
* @dma_addr: address of the queue memory
|
|
|
1632d2 |
- * @xxx_table_index: temporary, but should not need pgtbl for contig. queues.
|
|
|
1632d2 |
*
|
|
|
1632d2 |
- * The same command struct is used to create an rdma event queue, completion
|
|
|
1632d2 |
- * queue, or rdma admin queue. The cid is an interrupt number for an event
|
|
|
1632d2 |
+ * The same command struct is used to create an RDMA event queue, completion
|
|
|
1632d2 |
+ * queue, or RDMA admin queue. The cid is an interrupt number for an event
|
|
|
1632d2 |
* queue, an event queue id for a completion queue, or a completion queue id
|
|
|
1632d2 |
- * for an rdma admin queue.
|
|
|
1632d2 |
+ * for an RDMA admin queue.
|
|
|
1632d2 |
*
|
|
|
1632d2 |
* The queue created via a dev command must be contiguous in dma space.
|
|
|
1632d2 |
*
|
|
|
1632d2 |
* The dev commands are intended only to be used during driver initialization,
|
|
|
1632d2 |
- * to create queues supporting the rdma admin queue. Other queues, and other
|
|
|
1632d2 |
- * types of rdma resources like memory regions, will be created and registered
|
|
|
1632d2 |
- * via the rdma admin queue, and will support a more complete interface
|
|
|
1632d2 |
+ * to create queues supporting the RDMA admin queue. Other queues, and other
|
|
|
1632d2 |
+ * types of RDMA resources like memory regions, will be created and registered
|
|
|
1632d2 |
+ * via the RDMA admin queue, and will support a more complete interface
|
|
|
1632d2 |
* providing scatter gather lists for larger, scattered queue buffers and
|
|
|
1632d2 |
* memory registration.
|
|
|
1632d2 |
*
|
|
|
1632d2 |
- * There is no rdma specific dev command completion struct. Completion uses
|
|
|
1632d2 |
+ * There is no RDMA specific dev command completion struct. Completion uses
|
|
|
1632d2 |
* the common struct ionic_admin_comp. Only the status is indicated.
|
|
|
1632d2 |
**/
|
|
|
1632d2 |
struct ionic_rdma_queue_cmd {
|
|
|
1632d2 |
@@ -2020,8 +2138,7 @@ struct ionic_rdma_queue_cmd {
|
|
|
1632d2 |
u8 depth_log2;
|
|
|
1632d2 |
u8 stride_log2;
|
|
|
1632d2 |
__le64 dma_addr;
|
|
|
1632d2 |
- u8 rsvd2[36];
|
|
|
1632d2 |
- __le32 xxx_table_index;
|
|
|
1632d2 |
+ u8 rsvd2[40];
|
|
|
1632d2 |
};
|
|
|
1632d2 |
|
|
|
1632d2 |
/******************************************************************
|
|
|
1632d2 |
@@ -2029,7 +2146,7 @@ struct ionic_rdma_queue_cmd {
|
|
|
1632d2 |
******************************************************************/
|
|
|
1632d2 |
|
|
|
1632d2 |
/**
|
|
|
1632d2 |
- * struct ionic_notifyq_event
|
|
|
1632d2 |
+ * struct ionic_notifyq_event - Generic event reporting structure
|
|
|
1632d2 |
* @eid: event number
|
|
|
1632d2 |
* @ecode: event code
|
|
|
1632d2 |
* @data: unspecified data about the event
|
|
|
1632d2 |
@@ -2044,9 +2161,9 @@ struct ionic_notifyq_event {
|
|
|
1632d2 |
};
|
|
|
1632d2 |
|
|
|
1632d2 |
/**
|
|
|
1632d2 |
- * struct ionic_link_change_event
|
|
|
1632d2 |
+ * struct ionic_link_change_event - Link change event notification
|
|
|
1632d2 |
* @eid: event number
|
|
|
1632d2 |
- * @ecode: event code = EVENT_OPCODE_LINK_CHANGE
|
|
|
1632d2 |
+ * @ecode: event code = IONIC_EVENT_LINK_CHANGE
|
|
|
1632d2 |
* @link_status: link up or down, with error bits (enum port_status)
|
|
|
1632d2 |
* @link_speed: speed of the network link
|
|
|
1632d2 |
*
|
|
|
1632d2 |
@@ -2061,9 +2178,9 @@ struct ionic_link_change_event {
|
|
|
1632d2 |
};
|
|
|
1632d2 |
|
|
|
1632d2 |
/**
|
|
|
1632d2 |
- * struct ionic_reset_event
|
|
|
1632d2 |
+ * struct ionic_reset_event - Reset event notification
|
|
|
1632d2 |
* @eid: event number
|
|
|
1632d2 |
- * @ecode: event code = EVENT_OPCODE_RESET
|
|
|
1632d2 |
+ * @ecode: event code = IONIC_EVENT_RESET
|
|
|
1632d2 |
* @reset_code: reset type
|
|
|
1632d2 |
* @state: 0=pending, 1=complete, 2=error
|
|
|
1632d2 |
*
|
|
|
1632d2 |
@@ -2079,11 +2196,9 @@ struct ionic_reset_event {
|
|
|
1632d2 |
};
|
|
|
1632d2 |
|
|
|
1632d2 |
/**
|
|
|
1632d2 |
- * struct ionic_heartbeat_event
|
|
|
1632d2 |
+ * struct ionic_heartbeat_event - Sent periodically by NIC to indicate health
|
|
|
1632d2 |
* @eid: event number
|
|
|
1632d2 |
- * @ecode: event code = EVENT_OPCODE_HEARTBEAT
|
|
|
1632d2 |
- *
|
|
|
1632d2 |
- * Sent periodically by the NIC to indicate continued health
|
|
|
1632d2 |
+ * @ecode: event code = IONIC_EVENT_HEARTBEAT
|
|
|
1632d2 |
*/
|
|
|
1632d2 |
struct ionic_heartbeat_event {
|
|
|
1632d2 |
__le64 eid;
|
|
|
1632d2 |
@@ -2092,12 +2207,10 @@ struct ionic_heartbeat_event {
|
|
|
1632d2 |
};
|
|
|
1632d2 |
|
|
|
1632d2 |
/**
|
|
|
1632d2 |
- * struct ionic_log_event
|
|
|
1632d2 |
+ * struct ionic_log_event - Sent to notify the driver of an internal error
|
|
|
1632d2 |
* @eid: event number
|
|
|
1632d2 |
- * @ecode: event code = EVENT_OPCODE_LOG
|
|
|
1632d2 |
+ * @ecode: event code = IONIC_EVENT_LOG
|
|
|
1632d2 |
* @data: log data
|
|
|
1632d2 |
- *
|
|
|
1632d2 |
- * Sent to notify the driver of an internal error.
|
|
|
1632d2 |
*/
|
|
|
1632d2 |
struct ionic_log_event {
|
|
|
1632d2 |
__le64 eid;
|
|
|
1632d2 |
@@ -2106,7 +2219,18 @@ struct ionic_log_event {
|
|
|
1632d2 |
};
|
|
|
1632d2 |
|
|
|
1632d2 |
/**
|
|
|
1632d2 |
- * struct ionic_port_stats
|
|
|
1632d2 |
+ * struct ionic_xcvr_event - Transceiver change event
|
|
|
1632d2 |
+ * @eid: event number
|
|
|
1632d2 |
+ * @ecode: event code = IONIC_EVENT_XCVR
|
|
|
1632d2 |
+ */
|
|
|
1632d2 |
+struct ionic_xcvr_event {
|
|
|
1632d2 |
+ __le64 eid;
|
|
|
1632d2 |
+ __le16 ecode;
|
|
|
1632d2 |
+ u8 rsvd[54];
|
|
|
1632d2 |
+};
|
|
|
1632d2 |
+
|
|
|
1632d2 |
+/**
|
|
|
1632d2 |
+ * struct ionic_port_stats - Port statistics structure
|
|
|
1632d2 |
*/
|
|
|
1632d2 |
struct ionic_port_stats {
|
|
|
1632d2 |
__le64 frames_rx_ok;
|
|
|
1632d2 |
@@ -2211,28 +2335,61 @@ struct ionic_mgmt_port_stats {
|
|
|
1632d2 |
__le64 frames_rx_multicast;
|
|
|
1632d2 |
__le64 frames_rx_broadcast;
|
|
|
1632d2 |
__le64 frames_rx_pause;
|
|
|
1632d2 |
- __le64 frames_rx_bad_length0;
|
|
|
1632d2 |
- __le64 frames_rx_undersized1;
|
|
|
1632d2 |
- __le64 frames_rx_oversized2;
|
|
|
1632d2 |
- __le64 frames_rx_fragments3;
|
|
|
1632d2 |
- __le64 frames_rx_jabber4;
|
|
|
1632d2 |
- __le64 frames_rx_64b5;
|
|
|
1632d2 |
- __le64 frames_rx_65b_127b6;
|
|
|
1632d2 |
- __le64 frames_rx_128b_255b7;
|
|
|
1632d2 |
- __le64 frames_rx_256b_511b8;
|
|
|
1632d2 |
- __le64 frames_rx_512b_1023b9;
|
|
|
1632d2 |
- __le64 frames_rx_1024b_1518b0;
|
|
|
1632d2 |
- __le64 frames_rx_gt_1518b1;
|
|
|
1632d2 |
- __le64 frames_rx_fifo_full2;
|
|
|
1632d2 |
- __le64 frames_tx_ok3;
|
|
|
1632d2 |
- __le64 frames_tx_all4;
|
|
|
1632d2 |
- __le64 frames_tx_bad5;
|
|
|
1632d2 |
- __le64 octets_tx_ok6;
|
|
|
1632d2 |
- __le64 octets_tx_total7;
|
|
|
1632d2 |
- __le64 frames_tx_unicast8;
|
|
|
1632d2 |
- __le64 frames_tx_multicast9;
|
|
|
1632d2 |
- __le64 frames_tx_broadcast0;
|
|
|
1632d2 |
- __le64 frames_tx_pause1;
|
|
|
1632d2 |
+ __le64 frames_rx_bad_length;
|
|
|
1632d2 |
+ __le64 frames_rx_undersized;
|
|
|
1632d2 |
+ __le64 frames_rx_oversized;
|
|
|
1632d2 |
+ __le64 frames_rx_fragments;
|
|
|
1632d2 |
+ __le64 frames_rx_jabber;
|
|
|
1632d2 |
+ __le64 frames_rx_64b;
|
|
|
1632d2 |
+ __le64 frames_rx_65b_127b;
|
|
|
1632d2 |
+ __le64 frames_rx_128b_255b;
|
|
|
1632d2 |
+ __le64 frames_rx_256b_511b;
|
|
|
1632d2 |
+ __le64 frames_rx_512b_1023b;
|
|
|
1632d2 |
+ __le64 frames_rx_1024b_1518b;
|
|
|
1632d2 |
+ __le64 frames_rx_gt_1518b;
|
|
|
1632d2 |
+ __le64 frames_rx_fifo_full;
|
|
|
1632d2 |
+ __le64 frames_tx_ok;
|
|
|
1632d2 |
+ __le64 frames_tx_all;
|
|
|
1632d2 |
+ __le64 frames_tx_bad;
|
|
|
1632d2 |
+ __le64 octets_tx_ok;
|
|
|
1632d2 |
+ __le64 octets_tx_total;
|
|
|
1632d2 |
+ __le64 frames_tx_unicast;
|
|
|
1632d2 |
+ __le64 frames_tx_multicast;
|
|
|
1632d2 |
+ __le64 frames_tx_broadcast;
|
|
|
1632d2 |
+ __le64 frames_tx_pause;
|
|
|
1632d2 |
+};
|
|
|
1632d2 |
+
|
|
|
1632d2 |
+enum ionic_pb_buffer_drop_stats {
|
|
|
1632d2 |
+ IONIC_BUFFER_INTRINSIC_DROP = 0,
|
|
|
1632d2 |
+ IONIC_BUFFER_DISCARDED,
|
|
|
1632d2 |
+ IONIC_BUFFER_ADMITTED,
|
|
|
1632d2 |
+ IONIC_BUFFER_OUT_OF_CELLS_DROP,
|
|
|
1632d2 |
+ IONIC_BUFFER_OUT_OF_CELLS_DROP_2,
|
|
|
1632d2 |
+ IONIC_BUFFER_OUT_OF_CREDIT_DROP,
|
|
|
1632d2 |
+ IONIC_BUFFER_TRUNCATION_DROP,
|
|
|
1632d2 |
+ IONIC_BUFFER_PORT_DISABLED_DROP,
|
|
|
1632d2 |
+ IONIC_BUFFER_COPY_TO_CPU_TAIL_DROP,
|
|
|
1632d2 |
+ IONIC_BUFFER_SPAN_TAIL_DROP,
|
|
|
1632d2 |
+ IONIC_BUFFER_MIN_SIZE_VIOLATION_DROP,
|
|
|
1632d2 |
+ IONIC_BUFFER_ENQUEUE_ERROR_DROP,
|
|
|
1632d2 |
+ IONIC_BUFFER_INVALID_PORT_DROP,
|
|
|
1632d2 |
+ IONIC_BUFFER_INVALID_OUTPUT_QUEUE_DROP,
|
|
|
1632d2 |
+ IONIC_BUFFER_DROP_MAX,
|
|
|
1632d2 |
+};
|
|
|
1632d2 |
+
|
|
|
1632d2 |
+/**
|
|
|
1632d2 |
+ * struct port_pb_stats - packet buffers system stats
|
|
|
1632d2 |
+ * uses ionic_pb_buffer_drop_stats for drop_counts[]
|
|
|
1632d2 |
+ */
|
|
|
1632d2 |
+struct ionic_port_pb_stats {
|
|
|
1632d2 |
+ __le64 sop_count_in;
|
|
|
1632d2 |
+ __le64 eop_count_in;
|
|
|
1632d2 |
+ __le64 sop_count_out;
|
|
|
1632d2 |
+ __le64 eop_count_out;
|
|
|
1632d2 |
+ __le64 drop_counts[IONIC_BUFFER_DROP_MAX];
|
|
|
1632d2 |
+ __le64 input_queue_buffer_occupancy[IONIC_QOS_TC_MAX];
|
|
|
1632d2 |
+ __le64 input_queue_port_monitor[IONIC_QOS_TC_MAX];
|
|
|
1632d2 |
+ __le64 output_queue_port_monitor[IONIC_QOS_TC_MAX];
|
|
|
1632d2 |
};
|
|
|
1632d2 |
|
|
|
1632d2 |
/**
|
|
|
1632d2 |
@@ -2264,22 +2421,31 @@ union ionic_port_identity {
|
|
|
1632d2 |
u8 rsvd2[44];
|
|
|
1632d2 |
union ionic_port_config config;
|
|
|
1632d2 |
};
|
|
|
1632d2 |
- __le32 words[512];
|
|
|
1632d2 |
+ __le32 words[478];
|
|
|
1632d2 |
};
|
|
|
1632d2 |
|
|
|
1632d2 |
/**
|
|
|
1632d2 |
* struct ionic_port_info - port info structure
|
|
|
1632d2 |
- * @port_status: port status
|
|
|
1632d2 |
- * @port_stats: port stats
|
|
|
1632d2 |
+ * @config: Port configuration data
|
|
|
1632d2 |
+ * @status: Port status data
|
|
|
1632d2 |
+ * @stats: Port statistics data
|
|
|
1632d2 |
+ * @mgmt_stats: Port management statistics data
|
|
|
1632d2 |
+ * @port_pb_drop_stats: uplink pb drop stats
|
|
|
1632d2 |
*/
|
|
|
1632d2 |
struct ionic_port_info {
|
|
|
1632d2 |
union ionic_port_config config;
|
|
|
1632d2 |
struct ionic_port_status status;
|
|
|
1632d2 |
- struct ionic_port_stats stats;
|
|
|
1632d2 |
+ union {
|
|
|
1632d2 |
+ struct ionic_port_stats stats;
|
|
|
1632d2 |
+ struct ionic_mgmt_port_stats mgmt_stats;
|
|
|
1632d2 |
+ };
|
|
|
1632d2 |
+ /* room for pb_stats to start at 2k offset */
|
|
|
1632d2 |
+ u8 rsvd[760];
|
|
|
1632d2 |
+ struct ionic_port_pb_stats pb_stats;
|
|
|
1632d2 |
};
|
|
|
1632d2 |
|
|
|
1632d2 |
/**
|
|
|
1632d2 |
- * struct ionic_lif_stats
|
|
|
1632d2 |
+ * struct ionic_lif_stats - LIF statistics structure
|
|
|
1632d2 |
*/
|
|
|
1632d2 |
struct ionic_lif_stats {
|
|
|
1632d2 |
/* RX */
|
|
|
1632d2 |
@@ -2332,7 +2498,7 @@ struct ionic_lif_stats {
|
|
|
1632d2 |
__le64 tx_queue_error;
|
|
|
1632d2 |
__le64 tx_desc_fetch_error;
|
|
|
1632d2 |
__le64 tx_desc_data_error;
|
|
|
1632d2 |
- __le64 rsvd9;
|
|
|
1632d2 |
+ __le64 tx_queue_empty;
|
|
|
1632d2 |
__le64 rsvd10;
|
|
|
1632d2 |
__le64 rsvd11;
|
|
|
1632d2 |
__le64 rsvd12;
|
|
|
1632d2 |
@@ -2433,7 +2599,10 @@ struct ionic_lif_stats {
|
|
|
1632d2 |
};
|
|
|
1632d2 |
|
|
|
1632d2 |
/**
|
|
|
1632d2 |
- * struct ionic_lif_info - lif info structure
|
|
|
1632d2 |
+ * struct ionic_lif_info - LIF info structure
|
|
|
1632d2 |
+ * @config: LIF configuration structure
|
|
|
1632d2 |
+ * @status: LIF status structure
|
|
|
1632d2 |
+ * @stats: LIF statistics structure
|
|
|
1632d2 |
*/
|
|
|
1632d2 |
struct ionic_lif_info {
|
|
|
1632d2 |
union ionic_lif_config config;
|
|
|
1632d2 |
@@ -2471,6 +2640,7 @@ union ionic_dev_cmd {
|
|
|
1632d2 |
|
|
|
1632d2 |
struct ionic_q_identify_cmd q_identify;
|
|
|
1632d2 |
struct ionic_q_init_cmd q_init;
|
|
|
1632d2 |
+ struct ionic_q_control_cmd q_control;
|
|
|
1632d2 |
};
|
|
|
1632d2 |
|
|
|
1632d2 |
union ionic_dev_cmd_comp {
|
|
|
1632d2 |
@@ -2507,15 +2677,15 @@ union ionic_dev_cmd_comp {
|
|
|
1632d2 |
};
|
|
|
1632d2 |
|
|
|
1632d2 |
/**
|
|
|
1632d2 |
- * union dev_info - Device info register format (read-only)
|
|
|
1632d2 |
- * @signature: Signature value of 0x44455649 ('DEVI').
|
|
|
1632d2 |
- * @version: Current version of info.
|
|
|
1632d2 |
- * @asic_type: Asic type.
|
|
|
1632d2 |
- * @asic_rev: Asic revision.
|
|
|
1632d2 |
- * @fw_status: Firmware status.
|
|
|
1632d2 |
- * @fw_heartbeat: Firmware heartbeat counter.
|
|
|
1632d2 |
- * @serial_num: Serial number.
|
|
|
1632d2 |
- * @fw_version: Firmware version.
|
|
|
1632d2 |
+ * union ionic_dev_info_regs - Device info register format (read-only)
|
|
|
1632d2 |
+ * @signature: Signature value of 0x44455649 ('DEVI')
|
|
|
1632d2 |
+ * @version: Current version of info
|
|
|
1632d2 |
+ * @asic_type: Asic type
|
|
|
1632d2 |
+ * @asic_rev: Asic revision
|
|
|
1632d2 |
+ * @fw_status: Firmware status
|
|
|
1632d2 |
+ * @fw_heartbeat: Firmware heartbeat counter
|
|
|
1632d2 |
+ * @serial_num: Serial number
|
|
|
1632d2 |
+ * @fw_version: Firmware version
|
|
|
1632d2 |
*/
|
|
|
1632d2 |
union ionic_dev_info_regs {
|
|
|
1632d2 |
#define IONIC_DEVINFO_FWVERS_BUFLEN 32
|
|
|
1632d2 |
@@ -2536,10 +2706,10 @@ union ionic_dev_info_regs {
|
|
|
1632d2 |
|
|
|
1632d2 |
/**
|
|
|
1632d2 |
* union ionic_dev_cmd_regs - Device command register format (read-write)
|
|
|
1632d2 |
- * @doorbell: Device Cmd Doorbell, write-only.
|
|
|
1632d2 |
+ * @doorbell: Device Cmd Doorbell, write-only
|
|
|
1632d2 |
* Write a 1 to signal device to process cmd,
|
|
|
1632d2 |
* poll done for completion.
|
|
|
1632d2 |
- * @done: Done indicator, bit 0 == 1 when command is complete.
|
|
|
1632d2 |
+ * @done: Done indicator, bit 0 == 1 when command is complete
|
|
|
1632d2 |
* @cmd: Opcode-specific command bytes
|
|
|
1632d2 |
* @comp: Opcode-specific response bytes
|
|
|
1632d2 |
* @data: Opcode-specific side-data
|
|
|
1632d2 |
@@ -2557,7 +2727,7 @@ union ionic_dev_cmd_regs {
|
|
|
1632d2 |
};
|
|
|
1632d2 |
|
|
|
1632d2 |
/**
|
|
|
1632d2 |
- * union ionic_dev_regs - Device register format in for bar 0 page 0
|
|
|
1632d2 |
+ * union ionic_dev_regs - Device register format for bar 0 page 0
|
|
|
1632d2 |
* @info: Device info registers
|
|
|
1632d2 |
* @devcmd: Device command registers
|
|
|
1632d2 |
*/
|
|
|
1632d2 |
@@ -2572,6 +2742,7 @@ union ionic_dev_regs {
|
|
|
1632d2 |
union ionic_adminq_cmd {
|
|
|
1632d2 |
struct ionic_admin_cmd cmd;
|
|
|
1632d2 |
struct ionic_nop_cmd nop;
|
|
|
1632d2 |
+ struct ionic_q_identify_cmd q_identify;
|
|
|
1632d2 |
struct ionic_q_init_cmd q_init;
|
|
|
1632d2 |
struct ionic_q_control_cmd q_control;
|
|
|
1632d2 |
struct ionic_lif_setattr_cmd lif_setattr;
|
|
|
1632d2 |
@@ -2588,6 +2759,7 @@ union ionic_adminq_cmd {
|
|
|
1632d2 |
union ionic_adminq_comp {
|
|
|
1632d2 |
struct ionic_admin_comp comp;
|
|
|
1632d2 |
struct ionic_nop_comp nop;
|
|
|
1632d2 |
+ struct ionic_q_identify_comp q_identify;
|
|
|
1632d2 |
struct ionic_q_init_comp q_init;
|
|
|
1632d2 |
struct ionic_lif_setattr_comp lif_setattr;
|
|
|
1632d2 |
struct ionic_lif_getattr_comp lif_getattr;
|
|
|
1632d2 |
@@ -2613,14 +2785,14 @@ union ionic_adminq_comp {
|
|
|
1632d2 |
/**
|
|
|
1632d2 |
* struct ionic_doorbell - Doorbell register layout
|
|
|
1632d2 |
* @p_index: Producer index
|
|
|
1632d2 |
- * @ring: Selects the specific ring of the queue to update.
|
|
|
1632d2 |
+ * @ring: Selects the specific ring of the queue to update
|
|
|
1632d2 |
* Type-specific meaning:
|
|
|
1632d2 |
- * ring=0: Default producer/consumer queue.
|
|
|
1632d2 |
+ * ring=0: Default producer/consumer queue
|
|
|
1632d2 |
* ring=1: (CQ, EQ) Re-Arm queue. RDMA CQs
|
|
|
1632d2 |
* send events to EQs when armed. EQs send
|
|
|
1632d2 |
* interrupts when armed.
|
|
|
1632d2 |
- * @qid: The queue id selects the queue destination for the
|
|
|
1632d2 |
- * producer index and flags.
|
|
|
1632d2 |
+ * @qid_lo: Queue destination for the producer index and flags (low bits)
|
|
|
1632d2 |
+ * @qid_hi: Queue destination for the producer index and flags (high bits)
|
|
|
1632d2 |
*/
|
|
|
1632d2 |
struct ionic_doorbell {
|
|
|
1632d2 |
__le16 p_index;
|
|
|
1632d2 |
@@ -2653,6 +2825,7 @@ struct ionic_identity {
|
|
|
1632d2 |
union ionic_lif_identity lif;
|
|
|
1632d2 |
union ionic_port_identity port;
|
|
|
1632d2 |
union ionic_qos_identity qos;
|
|
|
1632d2 |
+ union ionic_q_identity txq;
|
|
|
1632d2 |
};
|
|
|
1632d2 |
|
|
|
1632d2 |
#endif /* _IONIC_IF_H_ */
|
|
|
1632d2 |
--
|
|
|
1632d2 |
2.16.4
|
|
|
1632d2 |
|
|
|
1632d2 |
|