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From 0441942faf5c6e7372792b10cf57345cfad2cefa Mon Sep 17 00:00:00 2001
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From: Jonathan Toppins <jtoppins@redhat.com>
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Date: Wed, 2 Oct 2019 18:23:38 -0400
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Subject: [PATCH 83/96] [netdrv] bnxt_en: Update firmware interface spec. to
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1.10.0.100
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Message-id: <e0fd84c142e378fb6fcc8bae77e40a1090a2597c.1570027456.git.jtoppins@redhat.com>
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Patchwork-id: 276500
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O-Subject: [RHEL-8.2 PATCH 76/78] bnxt_en: Update firmware interface spec. to 1.10.0.100.
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Bugzilla: 1724766
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RH-Acked-by: John Linville <linville@redhat.com>
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RH-Acked-by: Jarod Wilson <jarod@redhat.com>
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Some error recovery updates to the spec., among other minor changes.
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Signed-off-by: Michael Chan <michael.chan@broadcom.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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(cherry picked from commit 72e0c9f91238f1f5f22954be6aea535d1d5fbf31)
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Bugzilla: 1724766
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Build Info: https://brewweb.engineering.redhat.com/brew/taskinfo?taskID=23809532
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Tested: build, boot, basic ping
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Signed-off-by: Jonathan Toppins <jtoppins@redhat.com>
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Signed-off-by: Bruno Meneguele <bmeneg@redhat.com>
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---
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drivers/net/ethernet/broadcom/bnxt/bnxt_hsi.h | 146 ++++++++++++++++++--------
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1 file changed, 103 insertions(+), 43 deletions(-)
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Index: src/drivers/net/ethernet/broadcom/bnxt/bnxt_hsi.h
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===================================================================
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--- src.orig/drivers/net/ethernet/broadcom/bnxt/bnxt_hsi.h 2020-02-06 16:23:15.728512987 +0100
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+++ src/drivers/net/ethernet/broadcom/bnxt/bnxt_hsi.h 2020-02-06 16:23:21.544459601 +0100
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@@ -44,11 +44,12 @@
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#define TLV_TYPE_ENGINE_CKV_IV 0x8003UL
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#define TLV_TYPE_ENGINE_CKV_AUTH_TAG 0x8004UL
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#define TLV_TYPE_ENGINE_CKV_CIPHERTEXT 0x8005UL
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-#define TLV_TYPE_ENGINE_CKV_ALGORITHMS 0x8006UL
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+#define TLV_TYPE_ENGINE_CKV_HOST_ALGORITHMS 0x8006UL
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#define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY 0x8007UL
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#define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE 0x8008UL
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-#define TLV_TYPE_ENGINE_CKV_SRT_ECC_PUBLIC_KEY 0x8009UL
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-#define TLV_TYPE_LAST TLV_TYPE_ENGINE_CKV_SRT_ECC_PUBLIC_KEY
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+#define TLV_TYPE_ENGINE_CKV_FW_ECC_PUBLIC_KEY 0x8009UL
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+#define TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS 0x800aUL
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+#define TLV_TYPE_LAST TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS
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/* tlv (size:64b/8B) */
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@@ -201,10 +202,16 @@
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#define HWRM_PORT_QSTATS_EXT 0xb4UL
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#define HWRM_PORT_PHY_MDIO_WRITE 0xb5UL
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#define HWRM_PORT_PHY_MDIO_READ 0xb6UL
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+ #define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE 0xb7UL
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+ #define HWRM_PORT_PHY_MDIO_BUS_RELEASE 0xb8UL
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#define HWRM_FW_RESET 0xc0UL
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#define HWRM_FW_QSTATUS 0xc1UL
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#define HWRM_FW_HEALTH_CHECK 0xc2UL
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#define HWRM_FW_SYNC 0xc3UL
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+ #define HWRM_FW_STATE_BUFFER_QCAPS 0xc4UL
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+ #define HWRM_FW_STATE_QUIESCE 0xc5UL
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+ #define HWRM_FW_STATE_BACKUP 0xc6UL
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+ #define HWRM_FW_STATE_RESTORE 0xc7UL
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#define HWRM_FW_SET_TIME 0xc8UL
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#define HWRM_FW_GET_TIME 0xc9UL
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#define HWRM_FW_SET_STRUCTURED_DATA 0xcaUL
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@@ -216,7 +223,10 @@
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#define HWRM_FWD_ASYNC_EVENT_CMPL 0xd3UL
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#define HWRM_OEM_CMD 0xd4UL
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#define HWRM_PORT_PRBS_TEST 0xd5UL
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+ #define HWRM_PORT_SFP_SIDEBAND_CFG 0xd6UL
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+ #define HWRM_PORT_SFP_SIDEBAND_QCFG 0xd7UL
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#define HWRM_TEMP_MONITOR_QUERY 0xe0UL
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+ #define HWRM_REG_POWER_QUERY 0xe1UL
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#define HWRM_WOL_FILTER_ALLOC 0xf0UL
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#define HWRM_WOL_FILTER_FREE 0xf1UL
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#define HWRM_WOL_FILTER_QCFG 0xf2UL
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@@ -411,8 +421,8 @@
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#define HWRM_VERSION_MAJOR 1
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#define HWRM_VERSION_MINOR 10
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#define HWRM_VERSION_UPDATE 0
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-#define HWRM_VERSION_RSVD 89
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-#define HWRM_VERSION_STR "1.10.0.89"
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+#define HWRM_VERSION_RSVD 100
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+#define HWRM_VERSION_STR "1.10.0.100"
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/* hwrm_ver_get_input (size:192b/24B) */
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struct hwrm_ver_get_input {
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@@ -805,6 +815,37 @@
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#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE 0x10UL
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};
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+/* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */
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+struct hwrm_async_event_cmpl_default_vnic_change {
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+ __le16 type;
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+ #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK 0x3fUL
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+ #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT 0
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+ #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
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+ #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT
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+ #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK 0xffc0UL
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+ #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT 6
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+ __le16 event_id;
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+ #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION 0x35UL
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+ #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION
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+ __le32 event_data2;
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+ u8 opaque_v;
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+ #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V 0x1UL
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+ #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK 0xfeUL
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+ #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1
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+ u8 timestamp_lo;
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+ __le16 timestamp_hi;
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+ __le32 event_data1;
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+ #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK 0x3UL
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+ #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT 0
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+ #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC 0x1UL
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+ #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE 0x2UL
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+ #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE
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+ #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK 0x3fcUL
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+ #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT 2
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+ #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK 0x3fffc00UL
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+ #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT 10
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+};
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+
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/* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */
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struct hwrm_async_event_cmpl_hw_flow_aged {
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__le16 type;
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@@ -1047,31 +1088,33 @@
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__le16 fid;
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__le16 port_id;
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__le32 flags;
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- #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL
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- #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL
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- #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED 0x4UL
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- #define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED 0x8UL
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- #define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED 0x10UL
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- #define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED 0x20UL
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- #define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED 0x40UL
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- #define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED 0x80UL
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- #define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED 0x100UL
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- #define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED 0x200UL
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- #define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED 0x400UL
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- #define FUNC_QCAPS_RESP_FLAGS_STD_TX_RING_MODE_SUPPORTED 0x800UL
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- #define FUNC_QCAPS_RESP_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED 0x1000UL
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- #define FUNC_QCAPS_RESP_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED 0x2000UL
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- #define FUNC_QCAPS_RESP_FLAGS_GRE_TUN_FLAGS_SUPPORTED 0x4000UL
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- #define FUNC_QCAPS_RESP_FLAGS_MPLS_TUN_FLAGS_SUPPORTED 0x8000UL
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- #define FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED 0x10000UL
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- #define FUNC_QCAPS_RESP_FLAGS_ADOPTED_PF_SUPPORTED 0x20000UL
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- #define FUNC_QCAPS_RESP_FLAGS_ADMIN_PF_SUPPORTED 0x40000UL
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- #define FUNC_QCAPS_RESP_FLAGS_LINK_ADMIN_STATUS_SUPPORTED 0x80000UL
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- #define FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE 0x100000UL
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- #define FUNC_QCAPS_RESP_FLAGS_DYNAMIC_TX_RING_ALLOC 0x200000UL
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- #define FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE 0x400000UL
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- #define FUNC_QCAPS_RESP_FLAGS_ERROR_RECOVERY_CAPABLE 0x800000UL
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- #define FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED 0x1000000UL
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+ #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL
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+ #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL
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+ #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED 0x4UL
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+ #define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED 0x8UL
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+ #define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED 0x10UL
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+ #define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED 0x20UL
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+ #define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED 0x40UL
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+ #define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED 0x80UL
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+ #define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED 0x100UL
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+ #define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED 0x200UL
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+ #define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED 0x400UL
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+ #define FUNC_QCAPS_RESP_FLAGS_STD_TX_RING_MODE_SUPPORTED 0x800UL
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+ #define FUNC_QCAPS_RESP_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED 0x1000UL
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+ #define FUNC_QCAPS_RESP_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED 0x2000UL
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+ #define FUNC_QCAPS_RESP_FLAGS_GRE_TUN_FLAGS_SUPPORTED 0x4000UL
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+ #define FUNC_QCAPS_RESP_FLAGS_MPLS_TUN_FLAGS_SUPPORTED 0x8000UL
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+ #define FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED 0x10000UL
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+ #define FUNC_QCAPS_RESP_FLAGS_ADOPTED_PF_SUPPORTED 0x20000UL
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+ #define FUNC_QCAPS_RESP_FLAGS_ADMIN_PF_SUPPORTED 0x40000UL
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+ #define FUNC_QCAPS_RESP_FLAGS_LINK_ADMIN_STATUS_SUPPORTED 0x80000UL
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+ #define FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE 0x100000UL
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+ #define FUNC_QCAPS_RESP_FLAGS_DYNAMIC_TX_RING_ALLOC 0x200000UL
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+ #define FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE 0x400000UL
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+ #define FUNC_QCAPS_RESP_FLAGS_ERROR_RECOVERY_CAPABLE 0x800000UL
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+ #define FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED 0x1000000UL
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+ #define FUNC_QCAPS_RESP_FLAGS_ERR_RECOVER_RELOAD 0x2000000UL
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f95c89 |
+ #define FUNC_QCAPS_RESP_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED 0x4000000UL
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f95c89 |
u8 mac_address[6];
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f95c89 |
__le16 max_rsscos_ctx;
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__le16 max_cmpl_rings;
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@@ -1208,7 +1251,8 @@
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__le16 alloc_stat_ctx;
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__le16 alloc_msix;
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__le16 registered_vfs;
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f95c89 |
- u8 unused_1[3];
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f95c89 |
+ __le16 l2_doorbell_bar_size_kb;
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f95c89 |
+ u8 unused_1;
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f95c89 |
u8 always_1;
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f95c89 |
__le32 reset_addr_poll;
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f95c89 |
u8 unused_2[3];
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f95c89 |
@@ -1363,7 +1407,11 @@
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f95c89 |
__le16 target_id;
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f95c89 |
__le64 resp_addr;
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f95c89 |
__le16 fid;
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f95c89 |
- u8 unused_0[6];
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f95c89 |
+ u8 flags;
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f95c89 |
+ #define FUNC_QSTATS_REQ_FLAGS_UNUSED 0x0UL
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f95c89 |
+ #define FUNC_QSTATS_REQ_FLAGS_ROCE_ONLY 0x1UL
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f95c89 |
+ #define FUNC_QSTATS_REQ_FLAGS_LAST FUNC_QSTATS_REQ_FLAGS_ROCE_ONLY
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f95c89 |
+ u8 unused_0[5];
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f95c89 |
};
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f95c89 |
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f95c89 |
/* hwrm_func_qstats_output (size:1408b/176B) */
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f95c89 |
@@ -4714,7 +4762,7 @@
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f95c89 |
u8 valid;
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f95c89 |
};
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f95c89 |
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f95c89 |
-/* hwrm_vnic_cfg_input (size:320b/40B) */
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f95c89 |
+/* hwrm_vnic_cfg_input (size:384b/48B) */
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f95c89 |
struct hwrm_vnic_cfg_input {
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f95c89 |
__le16 req_type;
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f95c89 |
__le16 cmpl_ring;
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f95c89 |
@@ -4737,6 +4785,7 @@
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f95c89 |
#define VNIC_CFG_REQ_ENABLES_MRU 0x10UL
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f95c89 |
#define VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID 0x20UL
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f95c89 |
#define VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID 0x40UL
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f95c89 |
+ #define VNIC_CFG_REQ_ENABLES_QUEUE_ID 0x80UL
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f95c89 |
__le16 vnic_id;
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f95c89 |
__le16 dflt_ring_grp;
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f95c89 |
__le16 rss_rule;
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f95c89 |
@@ -4745,6 +4794,8 @@
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f95c89 |
__le16 mru;
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f95c89 |
__le16 default_rx_ring_id;
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f95c89 |
__le16 default_cmpl_ring_id;
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f95c89 |
+ __le16 queue_id;
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f95c89 |
+ u8 unused0[6];
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f95c89 |
};
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f95c89 |
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f95c89 |
/* hwrm_vnic_cfg_output (size:128b/16B) */
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f95c89 |
@@ -4785,6 +4836,7 @@
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f95c89 |
#define VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP 0x20UL
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f95c89 |
#define VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP 0x40UL
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f95c89 |
#define VNIC_QCAPS_RESP_FLAGS_OUTERMOST_RSS_CAP 0x80UL
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f95c89 |
+ #define VNIC_QCAPS_RESP_FLAGS_COS_ASSIGNMENT_CAP 0x100UL
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f95c89 |
__le16 max_aggs_supported;
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f95c89 |
u8 unused_1[5];
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f95c89 |
u8 valid;
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f95c89 |
@@ -6794,15 +6846,16 @@
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f95c89 |
__le16 target_id;
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f95c89 |
__le64 resp_addr;
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f95c89 |
u8 embedded_proc_type;
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f95c89 |
- #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL
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f95c89 |
- #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL
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f95c89 |
- #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL
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f95c89 |
- #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL
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f95c89 |
- #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL
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f95c89 |
- #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL
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f95c89 |
- #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL
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f95c89 |
- #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT 0x7UL
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f95c89 |
- #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_LAST FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT
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f95c89 |
+ #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL
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f95c89 |
+ #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL
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f95c89 |
+ #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL
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f95c89 |
+ #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL
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f95c89 |
+ #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL
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f95c89 |
+ #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL
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f95c89 |
+ #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL
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f95c89 |
+ #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT 0x7UL
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f95c89 |
+ #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION 0x8UL
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f95c89 |
+ #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_LAST FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION
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f95c89 |
u8 selfrst_status;
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f95c89 |
#define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE 0x0UL
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f95c89 |
#define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP 0x1UL
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f95c89 |
@@ -7125,7 +7178,14 @@
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f95c89 |
__le16 seq_id;
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f95c89 |
__le16 resp_len;
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f95c89 |
u8 temp;
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f95c89 |
- u8 unused_0[6];
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f95c89 |
+ u8 phy_temp;
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f95c89 |
+ u8 om_temp;
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f95c89 |
+ u8 flags;
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f95c89 |
+ #define TEMP_MONITOR_QUERY_RESP_FLAGS_TEMP_NOT_AVAILABLE 0x1UL
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f95c89 |
+ #define TEMP_MONITOR_QUERY_RESP_FLAGS_PHY_TEMP_NOT_AVAILABLE 0x2UL
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f95c89 |
+ #define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_NOT_PRESENT 0x4UL
|
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|
f95c89 |
+ #define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_TEMP_NOT_AVAILABLE 0x8UL
|
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|
f95c89 |
+ u8 unused_0[3];
|
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|
f95c89 |
u8 valid;
|
|
|
f95c89 |
};
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|
f95c89 |
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