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From dc28bfc3213960b549bcc70f0d5379a6222d2c60 Mon Sep 17 00:00:00 2001
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From: Bhupesh Sharma <bhsharma@redhat.com>
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Date: Wed, 13 Sep 2017 05:04:00 +0900
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Subject: [PATCH] [PATCH v2] book3s/ppc64: Lower the max real address to 53
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bits for kernels >= v4.11
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* Required for kernel 4.11
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Kernel commit 2f18d533757da3899f4bedab0b2c051b080079dc lowered the
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max real address on ppc64 to 53 bits.
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Make similar changes in makedumpfile (on basis of the underlying kernel
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version), without which the makedumpfile will fail to create a dumpfile
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and instead throw a SEGV fault as shown below on kernels >= v4.11:
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# makedumpfile --split -d 31 -x vmlinux vmcore dumpfile_{1,2,3} 2>&1
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The kernel version is not supported.
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The makedumpfile operation may be incomplete.
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[ 1196.252094] makedumpfile[2367]: unhandled signal 11 at
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00000100f7011ca8 nip 000000001001eecc lr 000000001001f3c0 code 30001
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Segmentation fault
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Signed-off-by: Bhupesh Sharma <bhsharma@redhat.com>
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---
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arch/ppc64.c | 8 +++++++-
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makedumpfile.h | 5 +++++
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2 files changed, 12 insertions(+), 1 deletion(-)
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diff --git a/makedumpfile-1.6.2/arch/ppc64.c b/makedumpfile-1.6.2/arch/ppc64.c
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index bacac778f73c..2f5a0daa16b2 100644
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--- a/makedumpfile-1.6.2/arch/ppc64.c
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+++ b/makedumpfile-1.6.2/arch/ppc64.c
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@@ -307,11 +307,17 @@ ppc64_vmalloc_init(void)
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}
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info->pte_rpn_mask = PTE_RPN_MASK_DEFAULT;
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- if (info->kernel_version >= KERNEL_VERSION(4, 6, 0)) {
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+ if ((info->kernel_version >= KERNEL_VERSION(4, 6, 0)) &&
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+ (info->kernel_version < KERNEL_VERSION(4, 11, 0))) {
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info->pte_rpn_mask = PTE_RPN_MASK_L4_4_6;
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info->pte_rpn_shift = PTE_RPN_SHIFT_L4_4_6;
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}
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+ if (info->kernel_version >= KERNEL_VERSION(4, 11, 0)) {
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+ info->pte_rpn_mask = PTE_RPN_MASK_L4_4_11;
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+ info->pte_rpn_shift = PTE_RPN_SHIFT_L4_4_11;
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+ }
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+
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/*
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* Compute ptrs per each level
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*/
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diff --git a/makedumpfile-1.6.2/makedumpfile.h b/makedumpfile-1.6.2/makedumpfile.h
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index 7d81bbcf2234..f4ba02d11f09 100644
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--- a/makedumpfile-1.6.2/makedumpfile.h
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+++ b/makedumpfile-1.6.2/makedumpfile.h
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@@ -692,6 +692,11 @@ unsigned long get_kvbase_arm64(void);
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#define PUD_MASKED_BITS_4_7 0xc0000000000000ffUL
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#define PMD_MASKED_BITS_4_7 0xc0000000000000ffUL
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+#define PTE_RPN_SIZE_L4_4_11 53
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+#define PTE_RPN_MASK_L4_4_11 \
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+ (((1UL << PTE_RPN_SIZE_L4_4_11) - 1) & ~((1UL << info->page_shift) - 1))
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+#define PTE_RPN_SHIFT_L4_4_11 info->page_shift
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+
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/*
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* Supported MMU types
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*/
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--
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2.7.4
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