From 33d983b5bb2929ae242606925e708092b1dfdd8f Mon Sep 17 00:00:00 2001

From: Ard Biesheuvel <ard.biesheuvel@linaro.org>

Date: Sat, 2 Sep 2017 11:01:22 +0100

Subject: drivers/irqchip: gicv3: add workaround for Synquacer pre-ITS

In their infinite wisdom, the Socionext engineers have decided

that ITS device IDs should not be hardwired, but it should be

left up to the software to assign them, by allowing it to

redirect MSI doorbell writes via a separate hardware block

that issues the doorbell write with a device ID that is

derived from the memory address. This completely breaks any

kind of isolation, or virtualization in general, for that

matter, but add support for it nonetheless.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

---

 arch/arm64/Kconfig               |  8 +++++++

 drivers/irqchip/irq-gic-v3-its.c | 48 +++++++++++++++++++++++++++++++++++-----

 2 files changed, 51 insertions(+), 5 deletions(-)

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig

index 0df64a6..c4361df 100644

--- a/arch/arm64/Kconfig

+++ b/arch/arm64/Kconfig

@@ -539,6 +539,14 @@ config QCOM_QDF2400_ERRATUM_0065

 	  If unsure, say Y.

+config SOCIONEXT_SYNQUACER_PREITS

+	bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"

+	default y

+	help

+	  Socionext Synquacer SoCs implement a separate h/w block to generate

+	  MSI doorbell writes with non-zero values for the device ID.

+

+	  If unsure, say Y.

 endmenu

diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c

index e8d8934..0d372f1 100644

--- a/drivers/irqchip/irq-gic-v3-its.c

+++ b/drivers/irqchip/irq-gic-v3-its.c

@@ -46,6 +46,7 @@

 #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING		(1ULL << 0)

 #define ITS_FLAGS_WORKAROUND_CAVIUM_22375	(1ULL << 1)

 #define ITS_FLAGS_WORKAROUND_CAVIUM_23144	(1ULL << 2)

+#define ITS_FLAGS_WORKAROUND_SOCIONEXT_PREITS	(1ULL << 3)

 #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING	(1 << 0)

@@ -99,6 +100,10 @@ struct its_node {

 	struct its_collection	*collections;

 	struct list_head	its_device_list;

 	u64			flags;

+#ifdef CONFIG_SOCIONEXT_SYNQUACER_PREITS

+	u64			pre_its_base;

+	u64			pre_its_size;

+#endif

 	u32			ite_size;

 	u32			device_ids;

 	int			numa_node;

@@ -1102,13 +1107,29 @@ static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg)

 	u64 addr;

 	its = its_dev->its;

-	addr = its->phys_base + GITS_TRANSLATER;

+

+#ifdef CONFIG_SOCIONEXT_SYNQUACER_PREITS

+	if (its->flags & ITS_FLAGS_WORKAROUND_SOCIONEXT_PREITS)

+

+		/*

+		 * The Socionext Synquacer SoC has a so-called 'pre-ITS',

+		 * which maps 32-bit writes into a separate window of size

+		 * '4 << device_id_bits' onto writes to GITS_TRANSLATER with

+		 * device ID taken from bits [device_id_bits + 1:2] of the

+		 * window offset.

+		 */

+		addr = its->pre_its_base + (its_dev->device_id << 2);

+	else

+#endif

+		addr = its->phys_base + GITS_TRANSLATER;

 	msg->address_lo		= lower_32_bits(addr);

 	msg->address_hi		= upper_32_bits(addr);

 	msg->data		= its_get_event_id(d);

-	iommu_dma_map_msi_msg(d->irq, msg);

+	if (!IS_ENABLED(CONFIG_SOCIONEXT_SYNQUACER_PREITS) ||

+	    !(its->flags & ITS_FLAGS_WORKAROUND_SOCIONEXT_PREITS))

+		iommu_dma_map_msi_msg(d->irq, msg);

 }

 static int its_irq_set_irqchip_state(struct irq_data *d,

@@ -1666,6 +1687,11 @@ static int its_alloc_tables(struct its_node *its)

 		ids     = 0x14;                 /* 20 bits, 8MB */

 	}

+#ifdef CONFIG_SOCIONEXT_SYNQUACER_PREITS

+	if (its->flags & ITS_FLAGS_WORKAROUND_SOCIONEXT_PREITS)

+		ids = ilog2(its->pre_its_size) - 2;

+#endif

+

 	its->device_ids = ids;

 	for (i = 0; i < GITS_BASER_NR_REGS; i++) {

@@ -2788,11 +2814,21 @@ static const struct gic_quirk its_quirks[] = {

 	}

 };

-static void its_enable_quirks(struct its_node *its)

+static void its_enable_quirks(struct its_node *its,

+			      struct fwnode_handle *handle)

 {

 	u32 iidr = readl_relaxed(its->base + GITS_IIDR);

 	gic_enable_quirks(iidr, its_quirks, its);

+

+#ifdef CONFIG_SOCIONEXT_SYNQUACER_PREITS

+	if (!fwnode_property_read_u64_array(handle,

+					"socionext,synquacer-pre-its",

+					&its->pre_its_base, 2)) {

+		its->flags |= ITS_FLAGS_WORKAROUND_SOCIONEXT_PREITS;

+		pr_info("ITS: enabling workaround for Socionext Synquacer pre-ITS\n");

+	}

+#endif

 }

 static int its_init_domain(struct fwnode_handle *handle, struct its_node *its)

@@ -2812,7 +2848,9 @@ static int its_init_domain(struct fwnode_handle *handle, struct its_node *its)

 	inner_domain->parent = its_parent;

 	irq_domain_update_bus_token(inner_domain, DOMAIN_BUS_NEXUS);

-	inner_domain->flags |= IRQ_DOMAIN_FLAG_MSI_REMAP;

+

+	if (!(its->flags & ITS_FLAGS_WORKAROUND_SOCIONEXT_PREITS))

+		inner_domain->flags |= IRQ_DOMAIN_FLAG_MSI_REMAP;

 	info->ops = &its_msi_domain_ops;

 	info->data = its;

 	inner_domain->host_data = info;

@@ -2966,7 +3004,7 @@ static int __init its_probe_one(struct resource *res,

 	}

 	its->cmd_write = its->cmd_base;

-	its_enable_quirks(its);

+	its_enable_quirks(its, handle);

 	err = its_alloc_tables(its);

 	if (err)

-- 

cgit v1.1

From 26e7bb47b0fb03a01be1e391a08c7375b45335a2 Mon Sep 17 00:00:00 2001

From: Ard Biesheuvel <ard.biesheuvel@linaro.org>

Date: Mon, 21 Aug 2017 20:29:05 +0100

Subject: pci: designware: add driver for DWC controller in ECAM shift mode

Some implementations of the Synopsys Designware PCIe controller implement

a so-called ECAM shift mode, which allows a static memory window to be

configured that covers the configuration space of the entire bus range.

If the firmware performs all the low level configuration that is required

to expose this controller in a fully ECAM compatible manner, we can

simply describe it as "pci-host-ecam-generic" and be done with it.

However, it appears that in some cases (one of which is the Armada 80x0),

the IP is synthesized with an ATU window size that does not allow the

first bus to be mapped in a way that prevents the device on the

downstream port from appearing more than once.

So implement a driver that relies on the firmware to perform all low

level initialization, and drives the controller in ECAM mode, but

overrides the config space accessors to take the above quirk into

account.

Note that, unlike most drivers for this IP, this driver does not expose

a fake bridge device at B/D/F 00:00.0. There is no point in doing so,

given that this is not a true bridge, and does not require any windows

to be configured in order for the downstream device to operate correctly.

Omitting it also prevents the PCI resource allocation routines from

handing out BAR space to it unnecessarily.

Cc: Bjorn Helgaas <bhelgaas@google.com>

Cc: Jingoo Han <jingoohan1@gmail.com>

Cc: Joao Pinto <Joao.Pinto@synopsys.com>

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

---

 drivers/pci/dwc/Kconfig                | 11 +++++

 drivers/pci/dwc/Makefile               |  1 +

 drivers/pci/dwc/pcie-designware-ecam.c | 77 ++++++++++++++++++++++++++++++++++

 3 files changed, 89 insertions(+)

 create mode 100644 drivers/pci/dwc/pcie-designware-ecam.c

diff --git a/drivers/pci/dwc/Kconfig b/drivers/pci/dwc/Kconfig

index 22ec82f..19856b1 100644

--- a/drivers/pci/dwc/Kconfig

+++ b/drivers/pci/dwc/Kconfig

@@ -169,4 +169,15 @@ config PCIE_KIRIN

 	  Say Y here if you want PCIe controller support

 	  on HiSilicon Kirin series SoCs.

+config PCIE_DW_HOST_ECAM

+	bool "Synopsys DesignWare PCIe controller in ECAM mode"

+	depends on OF && PCI

+	select PCI_HOST_COMMON

+	select IRQ_DOMAIN

+	help

+	  Add support for Synopsys DesignWare PCIe controllers configured

+	  by the firmware into ECAM shift mode. In some cases, these are

+	  fully ECAM compliant, in which case the pci-host-generic driver

+	  may be used instead.

+

 endmenu

diff --git a/drivers/pci/dwc/Makefile b/drivers/pci/dwc/Makefile

index c61be97..7d5a23e 100644

--- a/drivers/pci/dwc/Makefile

+++ b/drivers/pci/dwc/Makefile

@@ -1,5 +1,6 @@

 # SPDX-License-Identifier: GPL-2.0

 obj-$(CONFIG_PCIE_DW) += pcie-designware.o

 obj-$(CONFIG_PCIE_DW_HOST) += pcie-designware-host.o

+obj-$(CONFIG_PCIE_DW_HOST_ECAM) += pcie-designware-ecam.o

 obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o

 obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o

 ifneq ($(filter y,$(CONFIG_PCI_DRA7XX_HOST) $(CONFIG_PCI_DRA7XX_EP)),)

diff --git a/drivers/pci/dwc/pcie-designware-ecam.c b/drivers/pci/dwc/pcie-designware-ecam.c

new file mode 100644

index 0000000..ede627d

--- /dev/null

+++ b/drivers/pci/dwc/pcie-designware-ecam.c

@@ -0,0 +1,77 @@

+/*

+ * Driver for mostly ECAM compatible Synopsys dw PCIe controllers

+ * configured by the firmware into RC mode

+ *

+ * This program is free software; you can redistribute it and/or modify

+ * it under the terms of the GNU General Public License version 2 as

+ * published by the Free Software Foundation.

+ *

+ * Copyright (C) 2014 ARM Limited

+ * Copyright (C) 2017 Linaro Limited

+ *

+ * Authors: Will Deacon <will.deacon@arm.com>

+ *          Ard Biesheuvel <ard.biesheuvel@linaro.org>

+ */

+

+#include <linux/kernel.h>

+#include <linux/init.h>

+#include <linux/of_address.h>

+#include <linux/of_pci.h>

+#include <linux/pci-ecam.h>

+#include <linux/platform_device.h>

+

+static int pci_dw_ecam_config_read(struct pci_bus *bus, u32 devfn, int where,

+				   int size, u32 *val)

+{

+	struct pci_config_window *cfg = bus->sysdata;

+

+	/*

+	 * The Synopsys dw PCIe controller in RC mode will not filter type 0

+	 * config TLPs sent to devices 1 and up on its downstream port,

+	 * resulting in devices appearing multiple times on bus 0 unless we

+	 * filter them here.

+	 */

+	if (bus->number == cfg->busr.start && PCI_SLOT(devfn) > 0) {

+		*val = 0xffffffff;

+		return PCIBIOS_DEVICE_NOT_FOUND;

+	}

+	return pci_generic_config_read(bus, devfn, where, size, val);

+}

+

+static int pci_dw_ecam_config_write(struct pci_bus *bus, u32 devfn, int where,

+				    int size, u32 val)

+{

+	struct pci_config_window *cfg = bus->sysdata;

+

+	if (bus->number == cfg->busr.start && PCI_SLOT(devfn) > 0)

+		return PCIBIOS_DEVICE_NOT_FOUND;

+

+	return pci_generic_config_write(bus, devfn, where, size, val);

+}

+

+static struct pci_ecam_ops pci_dw_ecam_bus_ops = {

+	.pci_ops.map_bus		= pci_ecam_map_bus,

+	.pci_ops.read			= pci_dw_ecam_config_read,

+	.pci_ops.write			= pci_dw_ecam_config_write,

+	.bus_shift			= 20,

+};

+

+static const struct of_device_id pci_dw_ecam_of_match[] = {

+	{ .compatible = "marvell,armada8k-pcie-ecam" },

+	{ .compatible = "socionext,synquacer-pcie-ecam" },

+	{ .compatible = "snps,dw-pcie-ecam" },

+	{ },

+};

+

+static int pci_dw_ecam_probe(struct platform_device *pdev)

+{

+	return pci_host_common_probe(pdev, &pci_dw_ecam_bus_ops);

+}

+

+static struct platform_driver pci_dw_ecam_driver = {

+	.driver.name			= "pcie-designware-ecam",

+	.driver.of_match_table		= pci_dw_ecam_of_match,

+	.driver.suppress_bind_attrs	= true,

+	.probe				= pci_dw_ecam_probe,

+};

+builtin_platform_driver(pci_dw_ecam_driver);

-- 

cgit v1.1

From e3dff048a10f16aa0fd32438442ce39558bbdbef Mon Sep 17 00:00:00 2001

From: Jassi Brar <jaswinder.singh@linaro.org>

Date: Tue, 29 Aug 2017 22:45:59 +0530

Subject: net: socionext: Add Synquacer NetSec driver

This driver adds support for Socionext "netsec" IP Gigabit

Ethernet + PHY IP used in the Synquacer SC2A11 SoC.

Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

---

 drivers/net/ethernet/Kconfig                       |   1 +

 drivers/net/ethernet/Makefile                      |   1 +

 drivers/net/ethernet/socionext/Kconfig             |  29 +

 drivers/net/ethernet/socionext/Makefile            |   1 +

 drivers/net/ethernet/socionext/netsec/Makefile     |   6 +

 drivers/net/ethernet/socionext/netsec/netsec.h     | 408 ++++++++++++++

 .../socionext/netsec/netsec_desc_ring_access.c     | 623 +++++++++++++++++++++

 .../net/ethernet/socionext/netsec/netsec_ethtool.c |  78 +++

 .../ethernet/socionext/netsec/netsec_gmac_access.c | 330 +++++++++++

 .../net/ethernet/socionext/netsec/netsec_netdev.c  | 540 ++++++++++++++++++

 .../ethernet/socionext/netsec/netsec_platform.c    | 435 ++++++++++++++

 11 files changed, 2452 insertions(+)

 create mode 100644 drivers/net/ethernet/socionext/Kconfig

 create mode 100644 drivers/net/ethernet/socionext/Makefile

 create mode 100644 drivers/net/ethernet/socionext/netsec/Makefile

 create mode 100644 drivers/net/ethernet/socionext/netsec/netsec.h

 create mode 100644 drivers/net/ethernet/socionext/netsec/netsec_desc_ring_access.c

 create mode 100644 drivers/net/ethernet/socionext/netsec/netsec_ethtool.c

 create mode 100644 drivers/net/ethernet/socionext/netsec/netsec_gmac_access.c

 create mode 100644 drivers/net/ethernet/socionext/netsec/netsec_netdev.c

 create mode 100644 drivers/net/ethernet/socionext/netsec/netsec_platform.c

diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig

index c604213..d50519e 100644

--- a/drivers/net/ethernet/Kconfig

+++ b/drivers/net/ethernet/Kconfig

@@ -170,6 +170,7 @@ source "drivers/net/ethernet/sis/Kconfig"

 source "drivers/net/ethernet/sfc/Kconfig"

 source "drivers/net/ethernet/sgi/Kconfig"

 source "drivers/net/ethernet/smsc/Kconfig"

+source "drivers/net/ethernet/socionext/Kconfig"

 source "drivers/net/ethernet/stmicro/Kconfig"

 source "drivers/net/ethernet/sun/Kconfig"

 source "drivers/net/ethernet/tehuti/Kconfig"

diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile

index a0a03d4..6ae1bb9 100644

--- a/drivers/net/ethernet/Makefile

+++ b/drivers/net/ethernet/Makefile

@@ -81,6 +81,7 @@ obj-$(CONFIG_SFC) += sfc/

 obj-$(CONFIG_SFC_FALCON) += sfc/falcon/

 obj-$(CONFIG_NET_VENDOR_SGI) += sgi/

 obj-$(CONFIG_NET_VENDOR_SMSC) += smsc/

+obj-$(CONFIG_NET_VENDOR_SNI) += socionext/

 obj-$(CONFIG_NET_VENDOR_STMICRO) += stmicro/

 obj-$(CONFIG_NET_VENDOR_SUN) += sun/

 obj-$(CONFIG_NET_VENDOR_TEHUTI) += tehuti/

diff --git a/drivers/net/ethernet/socionext/Kconfig b/drivers/net/ethernet/socionext/Kconfig

new file mode 100644

index 0000000..a6dc195

--- /dev/null

+++ b/drivers/net/ethernet/socionext/Kconfig

@@ -0,0 +1,29 @@

+#

+# Socionext Network device configuration

+#

+

+config NET_VENDOR_SNI

+	bool "Socionext devices"

+	default y

+	---help---

+	  If you have a network (Ethernet) card belonging to this class, say Y.

+

+	  Note that the answer to this question doesn't directly affect the

+	  the questions about Socionext cards. If you say Y, you will be asked

+	  for your specific card in the following questions.

+

+if NET_VENDOR_SNI

+

+config SNI_NETSEC

+	tristate "NETSEC Driver Support"

+	depends on OF

+	select PHYLIB

+	select MII

+help

+	  Enable to add support for the SocioNext NetSec Gigabit Ethernet

+	  controller + PHY, as found on the Synquacer SC2A11 SoC

+

+	  To compile this driver as a module, choose M here: the module will be

+	  called netsec.  If unsure, say N.

+

+endif # NET_VENDOR_SNI

diff --git a/drivers/net/ethernet/socionext/Makefile b/drivers/net/ethernet/socionext/Makefile

new file mode 100644

index 0000000..9555899

--- /dev/null

+++ b/drivers/net/ethernet/socionext/Makefile

@@ -0,0 +1 @@

+obj-$(CONFIG_SNI_NETSEC) += netsec/

diff --git a/drivers/net/ethernet/socionext/netsec/Makefile b/drivers/net/ethernet/socionext/netsec/Makefile

new file mode 100644

index 0000000..18884ed

--- /dev/null

+++ b/drivers/net/ethernet/socionext/netsec/Makefile

@@ -0,0 +1,6 @@

+obj-$(CONFIG_SNI_NETSEC) := netsec.o

+netsec-objs := netsec_desc_ring_access.o \

+		netsec_netdev.o \

+		netsec_ethtool.o \

+		netsec_platform.o \

+		netsec_gmac_access.o

diff --git a/drivers/net/ethernet/socionext/netsec/netsec.h b/drivers/net/ethernet/socionext/netsec/netsec.h

new file mode 100644

index 0000000..3b97661

--- /dev/null

+++ b/drivers/net/ethernet/socionext/netsec/netsec.h

@@ -0,0 +1,408 @@

+/**

+ * netsec.h

+ *

+ *  Copyright (C) 2013-2014 Fujitsu Semiconductor Limited.

+ *  Copyright (C) 2014-2017 Linaro Ltd. All rights reserved.

+ *     Andy Green <andy.green@linaro.org>

+ *     Jassi Brar <jaswinder.singh@linaro.org>

+ *     Ard Biesheuvel <ard.biesheuvel@linaro.org>

+ *

+ *  This program is free software; you can redistribute it and/or

+ *  modify it under the terms of the GNU General Public License

+ *  as published by the Free Software Foundation; either version 2

+ *  of the License, or (at your option) any later version.

+ */

+#ifndef NETSEC_INTERNAL_H

+#define NETSEC_INTERNAL_H

+

+#include <linux/netdevice.h>

+#include <linux/types.h>

+#include <linux/device.h>

+#include <linux/phy.h>

+#include <linux/ethtool.h>

+#include <linux/of_address.h>

+#include <linux/of_mdio.h>

+#include <linux/etherdevice.h>

+#include <net/sock.h>

+

+#define NETSEC_FLOW_CONTROL_START_THRESHOLD	36

+#define NETSEC_FLOW_CONTROL_STOP_THRESHOLD	48

+

+#define NETSEC_CLK_MHZ				1000000

+

+#define NETSEC_RX_PKT_BUF_LEN			1522

+#define NETSEC_RX_JUMBO_PKT_BUF_LEN		9022

+

+#define NETSEC_NETDEV_TX_PKT_SCAT_NUM_MAX	19

+

+#define DESC_NUM				128

+

+#define NETSEC_TX_SHIFT_OWN_FIELD		31

+#define NETSEC_TX_SHIFT_LD_FIELD		30

+#define NETSEC_TX_SHIFT_DRID_FIELD		24

+#define NETSEC_TX_SHIFT_PT_FIELD		21

+#define NETSEC_TX_SHIFT_TDRID_FIELD		16

+#define NETSEC_TX_SHIFT_CC_FIELD		15

+#define NETSEC_TX_SHIFT_FS_FIELD		9

+#define NETSEC_TX_LAST				8

+#define NETSEC_TX_SHIFT_CO			7

+#define NETSEC_TX_SHIFT_SO			6

+#define NETSEC_TX_SHIFT_TRS_FIELD		4

+

+#define NETSEC_RX_PKT_OWN_FIELD			31

+#define NETSEC_RX_PKT_LD_FIELD			30

+#define NETSEC_RX_PKT_SDRID_FIELD		24

+#define NETSEC_RX_PKT_FR_FIELD			23

+#define NETSEC_RX_PKT_ER_FIELD			21

+#define NETSEC_RX_PKT_ERR_FIELD			16

+#define NETSEC_RX_PKT_TDRID_FIELD		12

+#define NETSEC_RX_PKT_FS_FIELD			9

+#define NETSEC_RX_PKT_LS_FIELD			8

+#define NETSEC_RX_PKT_CO_FIELD			6

+

+#define NETSEC_RX_PKT_ERR_MASK			3

+

+#define NETSEC_MAX_TX_PKT_LEN			1518

+#define NETSEC_MAX_TX_JUMBO_PKT_LEN		9018

+

+enum netsec_rings {

+	NETSEC_RING_TX,

+	NETSEC_RING_RX

+};

+

+#define NETSEC_RING_GMAC			15

+#define NETSEC_RING_MAX				1

+

+#define NETSEC_TCP_SEG_LEN_MAX			1460

+#define NETSEC_TCP_JUMBO_SEG_LEN_MAX		8960

+

+#define NETSEC_RX_CKSUM_NOTAVAIL		0

+#define NETSEC_RX_CKSUM_OK			1

+#define NETSEC_RX_CKSUM_NG			2

+

+#define NETSEC_TOP_IRQ_REG_CODE_LOAD_END	BIT(20)

+#define NETSEC_IRQ_TRANSITION_COMPLETE		BIT(4)

+#define NETSEC_IRQ_RX				BIT(1)

+#define NETSEC_IRQ_TX				BIT(0)

+

+#define NETSEC_IRQ_EMPTY			BIT(17)

+#define NETSEC_IRQ_ERR				BIT(16)

+#define NETSEC_IRQ_PKT_CNT			BIT(15)

+#define NETSEC_IRQ_TIMEUP			BIT(14)

+#define NETSEC_IRQ_RCV				(NETSEC_IRQ_PKT_CNT | \

+						 NETSEC_IRQ_TIMEUP)

+

+#define NETSEC_IRQ_TX_DONE			BIT(15)

+#define NETSEC_IRQ_SND				(NETSEC_IRQ_TX_DONE | \

+						 NETSEC_IRQ_TIMEUP)

+

+#define NETSEC_MODE_TRANS_COMP_IRQ_N2T		BIT(20)

+#define NETSEC_MODE_TRANS_COMP_IRQ_T2N		BIT(19)

+

+#define NETSEC_DESC_MIN				2

+#define NETSEC_DESC_MAX				2047

+#define NETSEC_INT_PKTCNT_MAX			2047

+

+#define NETSEC_FLOW_START_TH_MAX		95

+#define NETSEC_FLOW_STOP_TH_MAX			95

+#define NETSEC_FLOW_PAUSE_TIME_MIN		5

+

+#define NETSEC_CLK_EN_REG_DOM_ALL		0x3f

+

+#define NETSEC_REG_TOP_STATUS			0x80

+#define NETSEC_REG_TOP_INTEN			0x81

+#define NETSEC_REG_INTEN_SET			0x8d

+#define NETSEC_REG_INTEN_CLR			0x8e

+#define NETSEC_REG_NRM_TX_STATUS		0x100

+#define NETSEC_REG_NRM_TX_INTEN			0x101

+#define NETSEC_REG_NRM_TX_INTEN_SET		0x10a

+#define NETSEC_REG_NRM_TX_INTEN_CLR		0x10b

+#define NETSEC_REG_NRM_RX_STATUS		0x110

+#define NETSEC_REG_NRM_RX_INTEN			0x111

+#define NETSEC_REG_NRM_RX_INTEN_SET		0x11a

+#define NETSEC_REG_NRM_RX_INTEN_CLR		0x11b

+#define NETSEC_REG_RESERVED_RX_DESC_START	0x122

+#define NETSEC_REG_RESERVED_TX_DESC_START	0x132

+#define NETSEC_REG_CLK_EN			0x40

+#define NETSEC_REG_SOFT_RST			0x41

+#define NETSEC_REG_PKT_CMD_BUF			0x34

+#define NETSEC_REG_PKT_CTRL			0x50

+#define NETSEC_REG_COM_INIT			0x48

+#define NETSEC_REG_DMA_TMR_CTRL			0x83

+#define NETSEC_REG_F_TAIKI_MC_VER		0x8b

+#define NETSEC_REG_F_TAIKI_VER			0x8c

+#define NETSEC_REG_DMA_HM_CTRL			0x85

+#define NETSEC_REG_DMA_MH_CTRL			0x88

+#define NETSEC_REG_ADDR_DIS_CORE		0x86

+#define NETSEC_REG_DMAC_HM_CMD_BUF		0x84

+#define NETSEC_REG_DMAC_MH_CMD_BUF		0x87

+#define NETSEC_REG_NRM_TX_PKTCNT		0x104

+#define NETSEC_REG_NRM_TX_DONE_TXINT_PKTCNT	0x106

+#define NETSEC_REG_NRM_RX_RXINT_PKTCNT		0x116

+#define NETSEC_REG_NRM_TX_TXINT_TMR		0x108

+#define NETSEC_REG_NRM_RX_RXINT_TMR		0x118

+#define NETSEC_REG_NRM_TX_DONE_PKTCNT		0x105

+#define NETSEC_REG_NRM_RX_PKTCNT		0x115

+#define NETSEC_REG_NRM_TX_TMR			0x107

+#define NETSEC_REG_NRM_RX_TMR			0x117

+#define NETSEC_REG_NRM_TX_DESC_START_UP		0x10d

+#define NETSEC_REG_NRM_TX_DESC_START_LW		0x102

+#define NETSEC_REG_NRM_RX_DESC_START_UP		0x11d

+#define NETSEC_REG_NRM_RX_DESC_START_LW		0x112

+#define NETSEC_REG_NRM_TX_CONFIG		0x10c

+#define NETSEC_REG_NRM_RX_CONFIG		0x11c

+#define MAC_REG_DATA				0x470

+#define MAC_REG_CMD				0x471

+#define MAC_REG_FLOW_TH				0x473

+#define MAC_REG_INTF_SEL			0x475

+#define MAC_REG_DESC_INIT			0x47f

+#define MAC_REG_DESC_SOFT_RST			0x481

+#define NETSEC_REG_MODE_TRANS_COMP_STATUS	0x140

+#define GMAC_REG_MCR				0x0000

+#define GMAC_REG_MFFR				0x0004

+#define GMAC_REG_GAR				0x0010

+#define GMAC_REG_GDR				0x0014

+#define GMAC_REG_FCR				0x0018

+#define GMAC_REG_BMR				0x1000

+#define GMAC_REG_RDLAR				0x100c

+#define GMAC_REG_TDLAR				0x1010

+#define GMAC_REG_OMR				0x1018

+

+#define NETSEC_PKT_CTRL_REG_MODE_NRM		BIT(28)

+#define NETSEC_PKT_CTRL_REG_EN_JUMBO		BIT(27)

+#define NETSEC_PKT_CTRL_REG_LOG_CHKSUM_ER	BIT(3)

+#define NETSEC_PKT_CTRL_REG_LOG_HD_INCOMPLETE	BIT(2)

+#define NETSEC_PKT_CTRL_REG_LOG_HD_ER		BIT(1)

+#define NETSEC_PKT_CTRL_REG_DRP_NO_MATCH	BIT(0)

+

+#define NETSEC_CLK_EN_REG_DOM_G			BIT(5)

+#define NETSEC_CLK_EN_REG_DOM_C			BIT(1)

+#define NETSEC_CLK_EN_REG_DOM_D			BIT(0)

+

+#define NETSEC_COM_INIT_REG_DB			BIT(2)

+#define NETSEC_COM_INIT_REG_CLS			BIT(1)

+#define NETSEC_COM_INIT_REG_ALL			(NETSEC_COM_INIT_REG_CLS | \

+						 NETSEC_COM_INIT_REG_DB)

+

+#define NETSEC_SOFT_RST_REG_RESET		0

+#define NETSEC_SOFT_RST_REG_RUN			BIT(31)

+

+#define NETSEC_DMA_CTRL_REG_STOP		1

+#define MH_CTRL__MODE_TRANS			BIT(20)

+

+#define NETSEC_GMAC_CMD_ST_READ			0

+#define NETSEC_GMAC_CMD_ST_WRITE		BIT(28)

+#define NETSEC_GMAC_CMD_ST_BUSY			BIT(31)

+

+#define NETSEC_GMAC_BMR_REG_COMMON		0x00412080

+#define NETSEC_GMAC_BMR_REG_RESET		0x00020181

+#define NETSEC_GMAC_BMR_REG_SWR			0x00000001

+

+#define NETSEC_GMAC_OMR_REG_ST			BIT(13)

+#define NETSEC_GMAC_OMR_REG_SR			BIT(1)

+

+#define NETSEC_GMAC_MCR_REG_IBN			BIT(30)

+#define NETSEC_GMAC_MCR_REG_CST			BIT(25)

+#define NETSEC_GMAC_MCR_REG_JE			BIT(20)

+#define NETSEC_MCR_PS				BIT(15)

+#define NETSEC_GMAC_MCR_REG_FES			BIT(14)

+#define NETSEC_GMAC_MCR_REG_FULL_DUPLEX_COMMON	0x0000280c

+#define NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON	0x0001a00c

+

+#define NETSEC_FCR_RFE				BIT(2)

+#define NETSEC_FCR_TFE				BIT(1)

+

+#define NETSEC_GMAC_GAR_REG_GW			BIT(1)

+#define NETSEC_GMAC_GAR_REG_GB			BIT(0)

+

+#define NETSEC_GMAC_GAR_REG_SHIFT_PA		11

+#define NETSEC_GMAC_GAR_REG_SHIFT_GR		6

+#define GMAC_REG_SHIFT_CR_GAR			2

+

+#define NETSEC_GMAC_GAR_REG_CR_25_35_MHZ	2

+#define NETSEC_GMAC_GAR_REG_CR_35_60_MHZ	3

+#define NETSEC_GMAC_GAR_REG_CR_60_100_MHZ	0

+#define NETSEC_GMAC_GAR_REG_CR_100_150_MHZ	1

+#define NETSEC_GMAC_GAR_REG_CR_150_250_MHZ	4

+#define NETSEC_GMAC_GAR_REG_CR_250_300_MHZ	5

+

+#define NETSEC_GMAC_RDLAR_REG_COMMON		0x18000

+#define NETSEC_GMAC_TDLAR_REG_COMMON		0x1c000

+

+#define NETSEC_REG_NETSEC_VER_F_TAIKI		0x50000

+

+#define NETSEC_REG_DESC_RING_CONFIG_CFG_UP	BIT(31)

+#define NETSEC_REG_DESC_RING_CONFIG_CH_RST	BIT(30)

+#define NETSEC_REG_DESC_TMR_MODE		4

+#define NETSEC_REG_DESC_ENDIAN			0

+

+#define NETSEC_MAC_DESC_SOFT_RST_SOFT_RST	1

+#define NETSEC_MAC_DESC_INIT_REG_INIT		1

+

+#define NETSEC_EEPROM_MAC_ADDRESS		0x00

+#define NETSEC_EEPROM_HM_ME_ADDRESS_H		0x08

+#define NETSEC_EEPROM_HM_ME_ADDRESS_L		0x0C

+#define NETSEC_EEPROM_HM_ME_SIZE		0x10

+#define NETSEC_EEPROM_MH_ME_ADDRESS_H		0x14

+#define NETSEC_EEPROM_MH_ME_ADDRESS_L		0x18

+#define NETSEC_EEPROM_MH_ME_SIZE		0x1C

+#define NETSEC_EEPROM_PKT_ME_ADDRESS		0x20

+#define NETSEC_EEPROM_PKT_ME_SIZE		0x24

+

+/* this is used to interpret a register layout */

+struct netsec_pkt_ctrlaram {

+	u8 log_chksum_er_flag:1;

+	u8 log_hd_imcomplete_flag:1;

+	u8 log_hd_er_flag:1;

+};

+

+struct netsec_param {

+	struct netsec_pkt_ctrlaram pkt_ctrlaram;

+	bool use_jumbo_pkt_flag;

+};

+

+struct netsec_mac_mode {

+	u16 flow_start_th;

+	u16 flow_stop_th;

+	u16 pause_time;

+	bool flow_ctrl_enable_flag;

+};

+

+struct netsec_desc_ring {

+	spinlock_t spinlock_desc; /* protect descriptor access */

+	phys_addr_t desc_phys;

+	struct netsec_frag_info *frag;

+	struct sk_buff **priv;

+	void *ring_vaddr;

+	enum netsec_rings id;

+	int len;

+	u16 tx_done_num;

+	u16 rx_num;

+	u16 head;

+	u16 tail;

+	bool running;

+	bool full;

+};

+

+struct netsec_frag_info {

+	dma_addr_t dma_addr;

+	void *addr;

+	u16 len;