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From 1b28a544627ddce094091946f06f99bc41d0098f Mon Sep 17 00:00:00 2001
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From: Corentin LABBE <clabbe.montjoie@gmail.com>
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Date: Tue, 24 Oct 2017 19:57:12 +0200
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Subject: [PATCH 01/11] net: stmmac: snps, dwmac-mdio MDIOs are automatically
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 registered
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stmmac bindings docs said that its mdio node must have
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compatible = "snps,dwmac-mdio";
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Since dwmac-sun8i does not have any good reasons to not doing it, all
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their MDIO node must have it.
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Since these compatible is automatically registered, dwmac-sun8i compatible
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does not need to be in need_mdio_ids.
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Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
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---
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 drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 4 ----
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 1 file changed, 4 deletions(-)
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diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
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index 6383695004a5..645ef949705f 100644
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--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
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+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
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@@ -318,10 +318,6 @@ static int stmmac_dt_phy(struct plat_stmmacenet_data *plat,
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 	bool mdio = true;
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 	static const struct of_device_id need_mdio_ids[] = {
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 		{ .compatible = "snps,dwc-qos-ethernet-4.10" },
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-		{ .compatible = "allwinner,sun8i-a83t-emac" },
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-		{ .compatible = "allwinner,sun8i-h3-emac" },
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-		{ .compatible = "allwinner,sun8i-v3s-emac" },
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-		{ .compatible = "allwinner,sun50i-a64-emac" },
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 		{},
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 	};
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-- 
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2.14.3
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From 9a5b1d9a7614b022512744896d889e76f687e90a Mon Sep 17 00:00:00 2001
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From: Corentin LABBE <clabbe.montjoie@gmail.com>
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Date: Tue, 24 Oct 2017 19:57:13 +0200
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Subject: [PATCH 02/11] net: stmmac: dwmac-sun8i: Handle integrated/external
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 MDIOs
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The Allwinner H3 SoC have two distinct MDIO bus, only one could be
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active at the same time.
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The selection of the active MDIO bus are done via some bits in the EMAC
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register of the system controller.
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This patch implement this MDIO switch via a custom MDIO-mux.
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Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
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Reviewed-by: Andrew Lunn <andrew@lunn.ch>
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---
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 drivers/net/ethernet/stmicro/stmmac/Kconfig       |   1 +
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 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 353 ++++++++++++++--------
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 2 files changed, 224 insertions(+), 130 deletions(-)
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diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig
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index 97035766c291..e28c0d2c58e9 100644
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--- a/drivers/net/ethernet/stmicro/stmmac/Kconfig
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+++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig
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@@ -159,6 +159,7 @@ config DWMAC_SUN8I
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 	tristate "Allwinner sun8i GMAC support"
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 	default ARCH_SUNXI
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 	depends on OF && (ARCH_SUNXI || COMPILE_TEST)
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+	select MDIO_BUS_MUX
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 	---help---
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 	  Support for Allwinner H3 A83T A64 EMAC ethernet controllers.
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diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
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index 39c2122a4f26..b3eb344bb158 100644
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--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
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+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
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@@ -17,6 +17,7 @@
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 #include <linux/clk.h>
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 #include <linux/io.h>
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 #include <linux/iopoll.h>
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+#include <linux/mdio-mux.h>
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 #include <linux/mfd/syscon.h>
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 #include <linux/module.h>
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 #include <linux/of_device.h>
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@@ -41,14 +42,14 @@
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  *				This value is used for disabling properly EMAC
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  *				and used as a good starting value in case of the
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  *				boot process(uboot) leave some stuff.
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- * @internal_phy:		Does the MAC embed an internal PHY
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+ * @soc_has_internal_phy:	Does the MAC embed an internal PHY
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  * @support_mii:		Does the MAC handle MII
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  * @support_rmii:		Does the MAC handle RMII
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  * @support_rgmii:		Does the MAC handle RGMII
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  */
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 struct emac_variant {
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 	u32 default_syscon_value;
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-	int internal_phy;
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+	bool soc_has_internal_phy;
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 	bool support_mii;
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 	bool support_rmii;
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 	bool support_rgmii;
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@@ -61,7 +62,8 @@ struct emac_variant {
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  * @rst_ephy:	reference to the optional EPHY reset for the internal PHY
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  * @variant:	reference to the current board variant
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  * @regmap:	regmap for using the syscon
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- * @use_internal_phy: Does the current PHY choice imply using the internal PHY
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+ * @internal_phy_powered: Does the internal PHY is enabled
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+ * @mux_handle:	Internal pointer used by mdio-mux lib
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  */
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 struct sunxi_priv_data {
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 	struct clk *tx_clk;
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@@ -70,12 +72,13 @@ struct sunxi_priv_data {
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 	struct reset_control *rst_ephy;
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 	const struct emac_variant *variant;
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 	struct regmap *regmap;
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-	bool use_internal_phy;
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+	bool internal_phy_powered;
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+	void *mux_handle;
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 };
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 static const struct emac_variant emac_variant_h3 = {
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 	.default_syscon_value = 0x58000,
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-	.internal_phy = PHY_INTERFACE_MODE_MII,
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+	.soc_has_internal_phy = true,
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 	.support_mii = true,
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 	.support_rmii = true,
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 	.support_rgmii = true
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@@ -83,20 +86,20 @@ static const struct emac_variant emac_variant_h3 = {
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 static const struct emac_variant emac_variant_v3s = {
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 	.default_syscon_value = 0x38000,
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-	.internal_phy = PHY_INTERFACE_MODE_MII,
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+	.soc_has_internal_phy = true,
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 	.support_mii = true
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 };
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 static const struct emac_variant emac_variant_a83t = {
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 	.default_syscon_value = 0,
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-	.internal_phy = 0,
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+	.soc_has_internal_phy = false,
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 	.support_mii = true,
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 	.support_rgmii = true
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 };
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 static const struct emac_variant emac_variant_a64 = {
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 	.default_syscon_value = 0,
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-	.internal_phy = 0,
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+	.soc_has_internal_phy = false,
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 	.support_mii = true,
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 	.support_rmii = true,
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 	.support_rgmii = true
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@@ -195,6 +198,9 @@ static const struct emac_variant emac_variant_a64 = {
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 #define H3_EPHY_LED_POL		BIT(17) /* 1: active low, 0: active high */
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 #define H3_EPHY_SHUTDOWN	BIT(16) /* 1: shutdown, 0: power up */
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 #define H3_EPHY_SELECT		BIT(15) /* 1: internal PHY, 0: external PHY */
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+#define H3_EPHY_MUX_MASK	(H3_EPHY_SHUTDOWN | H3_EPHY_SELECT)
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+#define DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID	1
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+#define DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID	2
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 /* H3/A64 specific bits */
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 #define SYSCON_RMII_EN		BIT(13) /* 1: enable RMII (overrides EPIT) */
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@@ -634,6 +640,159 @@ static int sun8i_dwmac_reset(struct stmmac_priv *priv)
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 	return 0;
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 }
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+/* Search in mdio-mux node for internal PHY node and get its clk/reset */
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+static int get_ephy_nodes(struct stmmac_priv *priv)
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+{
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+	struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
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+	struct device_node *mdio_mux, *iphynode;
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+	struct device_node *mdio_internal;
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+	int ret;
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+
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+	mdio_mux = of_get_child_by_name(priv->device->of_node, "mdio-mux");
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+	if (!mdio_mux) {
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+		dev_err(priv->device, "Cannot get mdio-mux node\n");
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+		return -ENODEV;
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+	}
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+
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+	mdio_internal = of_find_compatible_node(mdio_mux, NULL,
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+						"allwinner,sun8i-h3-mdio-internal");
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+	if (!mdio_internal) {
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+		dev_err(priv->device, "Cannot get internal_mdio node\n");
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+		return -ENODEV;
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+	}
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+
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+	/* Seek for internal PHY */
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+	for_each_child_of_node(mdio_internal, iphynode) {
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+		gmac->ephy_clk = of_clk_get(iphynode, 0);
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+		if (IS_ERR(gmac->ephy_clk))
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+			continue;
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+		gmac->rst_ephy = of_reset_control_get_exclusive(iphynode, NULL);
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+		if (IS_ERR(gmac->rst_ephy)) {
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+			ret = PTR_ERR(gmac->rst_ephy);
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+			if (ret == -EPROBE_DEFER)
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+				return ret;
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+			continue;
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+		}
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+		dev_info(priv->device, "Found internal PHY node\n");
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+		return 0;
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+	}
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+	return -ENODEV;
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+}
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+
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+static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv)
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+{
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+	struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
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+	int ret;
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+
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+	if (gmac->internal_phy_powered) {
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+		dev_warn(priv->device, "Internal PHY already powered\n");
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+		return 0;
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+	}
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+
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+	dev_info(priv->device, "Powering internal PHY\n");
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+	ret = clk_prepare_enable(gmac->ephy_clk);
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+	if (ret) {
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+		dev_err(priv->device, "Cannot enable internal PHY\n");
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+		return ret;
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+	}
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+
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+	/* Make sure the EPHY is properly reseted, as U-Boot may leave
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+	 * it at deasserted state, and thus it may fail to reset EMAC.
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+	 */
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+	reset_control_assert(gmac->rst_ephy);
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+
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+	ret = reset_control_deassert(gmac->rst_ephy);
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+	if (ret) {
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+		dev_err(priv->device, "Cannot deassert internal phy\n");
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+		clk_disable_unprepare(gmac->ephy_clk);
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+		return ret;
f2c60e
+	}
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+
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+	gmac->internal_phy_powered = true;
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+
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+	return 0;
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+}
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+
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+static int sun8i_dwmac_unpower_internal_phy(struct sunxi_priv_data *gmac)
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+{
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+	if (!gmac->internal_phy_powered)
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+		return 0;
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+
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+	clk_disable_unprepare(gmac->ephy_clk);
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+	reset_control_assert(gmac->rst_ephy);
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+	gmac->internal_phy_powered = false;
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+	return 0;
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+}
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+
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+/* MDIO multiplexing switch function
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+ * This function is called by the mdio-mux layer when it thinks the mdio bus
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+ * multiplexer needs to switch.
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+ * 'current_child' is the current value of the mux register
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+ * 'desired_child' is the value of the 'reg' property of the target child MDIO
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+ * node.
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+ * The first time this function is called, current_child == -1.
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+ * If current_child == desired_child, then the mux is already set to the
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+ * correct bus.
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+ */
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+static int mdio_mux_syscon_switch_fn(int current_child, int desired_child,
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+				     void *data)
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+{
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+	struct stmmac_priv *priv = data;
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+	struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
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+	u32 reg, val;
f2c60e
+	int ret = 0;
f2c60e
+	bool need_power_ephy = false;
f2c60e
+
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+	if (current_child ^ desired_child) {
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+		regmap_read(gmac->regmap, SYSCON_EMAC_REG, ®);
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+		switch (desired_child) {
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+		case DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID:
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+			dev_info(priv->device, "Switch mux to internal PHY");
f2c60e
+			val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SELECT;
f2c60e
+
f2c60e
+			need_power_ephy = true;
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+			break;
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+		case DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID:
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+			dev_info(priv->device, "Switch mux to external PHY");
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+			val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SHUTDOWN;
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+			need_power_ephy = false;
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+			break;
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+		default:
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+			dev_err(priv->device, "Invalid child ID %x\n",
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+				desired_child);
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+			return -EINVAL;
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+		}
f2c60e
+		regmap_write(gmac->regmap, SYSCON_EMAC_REG, val);
f2c60e
+		if (need_power_ephy) {
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+			ret = sun8i_dwmac_power_internal_phy(priv);
f2c60e
+			if (ret)
f2c60e
+				return ret;
f2c60e
+		} else {
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+			sun8i_dwmac_unpower_internal_phy(gmac);
f2c60e
+		}
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+		/* After changing syscon value, the MAC need reset or it will
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+		 * use the last value (and so the last PHY set).
f2c60e
+		 */
f2c60e
+		ret = sun8i_dwmac_reset(priv);
f2c60e
+	}
f2c60e
+	return ret;
f2c60e
+}
f2c60e
+
f2c60e
+static int sun8i_dwmac_register_mdio_mux(struct stmmac_priv *priv)
f2c60e
+{
f2c60e
+	int ret;
f2c60e
+	struct device_node *mdio_mux;
f2c60e
+	struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
f2c60e
+
f2c60e
+	mdio_mux = of_get_child_by_name(priv->device->of_node, "mdio-mux");
f2c60e
+	if (!mdio_mux)
f2c60e
+		return -ENODEV;
f2c60e
+
f2c60e
+	ret = mdio_mux_init(priv->device, mdio_mux, mdio_mux_syscon_switch_fn,
f2c60e
+			    &gmac->mux_handle, priv, priv->mii);
f2c60e
+	return ret;
f2c60e
+}
f2c60e
+
f2c60e
 static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv)
f2c60e
 {
f2c60e
 	struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
f2c60e
@@ -648,35 +807,25 @@ static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv)
f2c60e
 			 "Current syscon value is not the default %x (expect %x)\n",
f2c60e
 			 val, reg);
f2c60e
 
f2c60e
-	if (gmac->variant->internal_phy) {
f2c60e
-		if (!gmac->use_internal_phy) {
f2c60e
-			/* switch to external PHY interface */
f2c60e
-			reg &= ~H3_EPHY_SELECT;
f2c60e
-		} else {
f2c60e
-			reg |= H3_EPHY_SELECT;
f2c60e
-			reg &= ~H3_EPHY_SHUTDOWN;
f2c60e
-			dev_dbg(priv->device, "Select internal_phy %x\n", reg);
f2c60e
-
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-			if (of_property_read_bool(priv->plat->phy_node,
f2c60e
-						  "allwinner,leds-active-low"))
f2c60e
-				reg |= H3_EPHY_LED_POL;
f2c60e
-			else
f2c60e
-				reg &= ~H3_EPHY_LED_POL;
f2c60e
-
f2c60e
-			/* Force EPHY xtal frequency to 24MHz. */
f2c60e
-			reg |= H3_EPHY_CLK_SEL;
f2c60e
-
f2c60e
-			ret = of_mdio_parse_addr(priv->device,
f2c60e
-						 priv->plat->phy_node);
f2c60e
-			if (ret < 0) {
f2c60e
-				dev_err(priv->device, "Could not parse MDIO addr\n");
f2c60e
-				return ret;
f2c60e
-			}
f2c60e
-			/* of_mdio_parse_addr returns a valid (0 ~ 31) PHY
f2c60e
-			 * address. No need to mask it again.
f2c60e
-			 */
f2c60e
-			reg |= ret << H3_EPHY_ADDR_SHIFT;
f2c60e
+	if (gmac->variant->soc_has_internal_phy) {
f2c60e
+		if (of_property_read_bool(priv->plat->phy_node,
f2c60e
+					  "allwinner,leds-active-low"))
f2c60e
+			reg |= H3_EPHY_LED_POL;
f2c60e
+		else
f2c60e
+			reg &= ~H3_EPHY_LED_POL;
f2c60e
+
f2c60e
+		/* Force EPHY xtal frequency to 24MHz. */
f2c60e
+		reg |= H3_EPHY_CLK_SEL;
f2c60e
+
f2c60e
+		ret = of_mdio_parse_addr(priv->device, priv->plat->phy_node);
f2c60e
+		if (ret < 0) {
f2c60e
+			dev_err(priv->device, "Could not parse MDIO addr\n");
f2c60e
+			return ret;
f2c60e
 		}
f2c60e
+		/* of_mdio_parse_addr returns a valid (0 ~ 31) PHY
f2c60e
+		 * address. No need to mask it again.
f2c60e
+		 */
f2c60e
+		reg |= 1 << H3_EPHY_ADDR_SHIFT;
f2c60e
 	}
f2c60e
 
f2c60e
 	if (!of_property_read_u32(node, "allwinner,tx-delay-ps", &val)) {
f2c60e
@@ -746,81 +895,21 @@ static void sun8i_dwmac_unset_syscon(struct sunxi_priv_data *gmac)
f2c60e
 	regmap_write(gmac->regmap, SYSCON_EMAC_REG, reg);
f2c60e
 }
f2c60e
 
f2c60e
-static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv)
f2c60e
+static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv)
f2c60e
 {
f2c60e
-	struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
f2c60e
-	int ret;
f2c60e
-
f2c60e
-	if (!gmac->use_internal_phy)
f2c60e
-		return 0;
f2c60e
-
f2c60e
-	ret = clk_prepare_enable(gmac->ephy_clk);
f2c60e
-	if (ret) {
f2c60e
-		dev_err(priv->device, "Cannot enable ephy\n");
f2c60e
-		return ret;
f2c60e
-	}
f2c60e
-
f2c60e
-	/* Make sure the EPHY is properly reseted, as U-Boot may leave
f2c60e
-	 * it at deasserted state, and thus it may fail to reset EMAC.
f2c60e
-	 */
f2c60e
-	reset_control_assert(gmac->rst_ephy);
f2c60e
+	struct sunxi_priv_data *gmac = priv;
f2c60e
 
f2c60e
-	ret = reset_control_deassert(gmac->rst_ephy);
f2c60e
-	if (ret) {
f2c60e
-		dev_err(priv->device, "Cannot deassert ephy\n");
f2c60e
-		clk_disable_unprepare(gmac->ephy_clk);
f2c60e
-		return ret;
f2c60e
+	if (gmac->variant->soc_has_internal_phy) {
f2c60e
+		/* sun8i_dwmac_exit could be called with mdiomux uninit */
f2c60e
+		if (gmac->mux_handle)
f2c60e
+			mdio_mux_uninit(gmac->mux_handle);
f2c60e
+		if (gmac->internal_phy_powered)
f2c60e
+			sun8i_dwmac_unpower_internal_phy(gmac);
f2c60e
 	}
f2c60e
 
f2c60e
-	return 0;
f2c60e
-}
f2c60e
-
f2c60e
-static int sun8i_dwmac_unpower_internal_phy(struct sunxi_priv_data *gmac)
f2c60e
-{
f2c60e
-	if (!gmac->use_internal_phy)
f2c60e
-		return 0;
f2c60e
-
f2c60e
-	clk_disable_unprepare(gmac->ephy_clk);
f2c60e
-	reset_control_assert(gmac->rst_ephy);
f2c60e
-	return 0;
f2c60e
-}
f2c60e
-
f2c60e
-/* sun8i_power_phy() - Activate the PHY:
f2c60e
- * In case of error, no need to call sun8i_unpower_phy(),
f2c60e
- * it will be called anyway by sun8i_dwmac_exit()
f2c60e
- */
f2c60e
-static int sun8i_power_phy(struct stmmac_priv *priv)
f2c60e
-{
f2c60e
-	int ret;
f2c60e
-
f2c60e
-	ret = sun8i_dwmac_power_internal_phy(priv);
f2c60e
-	if (ret)
f2c60e
-		return ret;
f2c60e
-
f2c60e
-	ret = sun8i_dwmac_set_syscon(priv);
f2c60e
-	if (ret)
f2c60e
-		return ret;
f2c60e
-
f2c60e
-	/* After changing syscon value, the MAC need reset or it will use
f2c60e
-	 * the last value (and so the last PHY set.
f2c60e
-	 */
f2c60e
-	ret = sun8i_dwmac_reset(priv);
f2c60e
-	if (ret)
f2c60e
-		return ret;
f2c60e
-	return 0;
f2c60e
-}
f2c60e
-
f2c60e
-static void sun8i_unpower_phy(struct sunxi_priv_data *gmac)
f2c60e
-{
f2c60e
 	sun8i_dwmac_unset_syscon(gmac);
f2c60e
-	sun8i_dwmac_unpower_internal_phy(gmac);
f2c60e
-}
f2c60e
-
f2c60e
-static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv)
f2c60e
-{
f2c60e
-	struct sunxi_priv_data *gmac = priv;
f2c60e
 
f2c60e
-	sun8i_unpower_phy(gmac);
f2c60e
+	reset_control_put(gmac->rst_ephy);
f2c60e
 
f2c60e
 	clk_disable_unprepare(gmac->tx_clk);
f2c60e
 
f2c60e
@@ -849,7 +938,7 @@ static struct mac_device_info *sun8i_dwmac_setup(void *ppriv)
f2c60e
 	if (!mac)
f2c60e
 		return NULL;
f2c60e
 
f2c60e
-	ret = sun8i_power_phy(priv);
f2c60e
+	ret = sun8i_dwmac_set_syscon(priv);
f2c60e
 	if (ret)
f2c60e
 		return NULL;
f2c60e
 
f2c60e
@@ -889,6 +978,8 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
f2c60e
 	struct sunxi_priv_data *gmac;
f2c60e
 	struct device *dev = &pdev->dev;
f2c60e
 	int ret;
f2c60e
+	struct stmmac_priv *priv;
f2c60e
+	struct net_device *ndev;
f2c60e
 
f2c60e
 	ret = stmmac_get_platform_resources(pdev, &stmmac_res);
f2c60e
 	if (ret)
f2c60e
@@ -932,29 +1023,6 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
f2c60e
 	}
f2c60e
 
f2c60e
 	plat_dat->interface = of_get_phy_mode(dev->of_node);
f2c60e
-	if (plat_dat->interface == gmac->variant->internal_phy) {
f2c60e
-		dev_info(&pdev->dev, "Will use internal PHY\n");
f2c60e
-		gmac->use_internal_phy = true;
f2c60e
-		gmac->ephy_clk = of_clk_get(plat_dat->phy_node, 0);
f2c60e
-		if (IS_ERR(gmac->ephy_clk)) {
f2c60e
-			ret = PTR_ERR(gmac->ephy_clk);
f2c60e
-			dev_err(&pdev->dev, "Cannot get EPHY clock: %d\n", ret);
f2c60e
-			return -EINVAL;
f2c60e
-		}
f2c60e
-
f2c60e
-		gmac->rst_ephy = of_reset_control_get(plat_dat->phy_node, NULL);
f2c60e
-		if (IS_ERR(gmac->rst_ephy)) {
f2c60e
-			ret = PTR_ERR(gmac->rst_ephy);
f2c60e
-			if (ret == -EPROBE_DEFER)
f2c60e
-				return ret;
f2c60e
-			dev_err(&pdev->dev, "No EPHY reset control found %d\n",
f2c60e
-				ret);
f2c60e
-			return -EINVAL;
f2c60e
-		}
f2c60e
-	} else {
f2c60e
-		dev_info(&pdev->dev, "Will use external PHY\n");
f2c60e
-		gmac->use_internal_phy = false;
f2c60e
-	}
f2c60e
 
f2c60e
 	/* platform data specifying hardware features and callbacks.
f2c60e
 	 * hardware features were copied from Allwinner drivers.
f2c60e
@@ -973,9 +1041,34 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
f2c60e
 
f2c60e
 	ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
f2c60e
 	if (ret)
f2c60e
-		sun8i_dwmac_exit(pdev, plat_dat->bsp_priv);
f2c60e
+		goto dwmac_exit;
f2c60e
+
f2c60e
+	ndev = dev_get_drvdata(&pdev->dev);
f2c60e
+	priv = netdev_priv(ndev);
f2c60e
+	/* The mux must be registered after parent MDIO
f2c60e
+	 * so after stmmac_dvr_probe()
f2c60e
+	 */
f2c60e
+	if (gmac->variant->soc_has_internal_phy) {
f2c60e
+		ret = get_ephy_nodes(priv);
f2c60e
+		if (ret)
f2c60e
+			goto dwmac_exit;
f2c60e
+		ret = sun8i_dwmac_register_mdio_mux(priv);
f2c60e
+		if (ret) {
f2c60e
+			dev_err(&pdev->dev, "Failed to register mux\n");
f2c60e
+			goto dwmac_mux;
f2c60e
+		}
f2c60e
+	} else {
f2c60e
+		ret = sun8i_dwmac_reset(priv);
f2c60e
+		if (ret)
f2c60e
+			goto dwmac_exit;
f2c60e
+	}
f2c60e
 
f2c60e
 	return ret;
f2c60e
+dwmac_mux:
f2c60e
+	sun8i_dwmac_unset_syscon(gmac);
f2c60e
+dwmac_exit:
f2c60e
+	sun8i_dwmac_exit(pdev, plat_dat->bsp_priv);
f2c60e
+return ret;
f2c60e
 }
f2c60e
 
f2c60e
 static const struct of_device_id sun8i_dwmac_match[] = {
f2c60e
-- 
f2c60e
2.14.3
f2c60e
f2c60e
From f58f11ebb67468471ed8f232c576f348dd1a32b1 Mon Sep 17 00:00:00 2001
f2c60e
From: Corentin LABBE <clabbe.montjoie@gmail.com>
f2c60e
Date: Tue, 24 Oct 2017 19:57:14 +0200
f2c60e
Subject: [PATCH 03/11] net: stmmac: sun8i: Restore the compatibles
f2c60e
f2c60e
The original dwmac-sun8i DT bindings have some issue on how to handle
f2c60e
integrated PHY and was reverted in last RC of 4.13.
f2c60e
But now we have a solution so we need to get back that was reverted.
f2c60e
f2c60e
This patch restore compatibles about dwmac-sun8i
f2c60e
This reverts commit ad4540cc5aa3 ("net: stmmac: sun8i: Remove the compatibles")
f2c60e
f2c60e
Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
f2c60e
---
f2c60e
 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 8 ++++++++
f2c60e
 1 file changed, 8 insertions(+)
f2c60e
f2c60e
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
f2c60e
index b3eb344bb158..e5ff734d4f9b 100644
f2c60e
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
f2c60e
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
f2c60e
@@ -1072,6 +1072,14 @@ return ret;
f2c60e
 }
f2c60e
 
f2c60e
 static const struct of_device_id sun8i_dwmac_match[] = {
f2c60e
+	{ .compatible = "allwinner,sun8i-h3-emac",
f2c60e
+		.data = &emac_variant_h3 },
f2c60e
+	{ .compatible = "allwinner,sun8i-v3s-emac",
f2c60e
+		.data = &emac_variant_v3s },
f2c60e
+	{ .compatible = "allwinner,sun8i-a83t-emac",
f2c60e
+		.data = &emac_variant_a83t },
f2c60e
+	{ .compatible = "allwinner,sun50i-a64-emac",
f2c60e
+		.data = &emac_variant_a64 },
f2c60e
 	{ }
f2c60e
 };
f2c60e
 MODULE_DEVICE_TABLE(of, sun8i_dwmac_match);
f2c60e
-- 
f2c60e
2.14.3
f2c60e
f2c60e
From 54678636d98cd9625f342c831015e302642bf104 Mon Sep 17 00:00:00 2001
f2c60e
From: Corentin LABBE <clabbe.montjoie@gmail.com>
f2c60e
Date: Tue, 31 Oct 2017 09:19:08 +0100
f2c60e
Subject: [PATCH 04/11] dt-bindings: net: Restore sun8i dwmac binding
f2c60e
f2c60e
The original dwmac-sun8i DT bindings have some issue on how to handle
f2c60e
integrated PHY and was reverted in last RC of 4.13.
f2c60e
But now we have a solution so we need to get back that was reverted.
f2c60e
f2c60e
This patch restore dt-bindings documentation about dwmac-sun8i
f2c60e
This reverts commit 8aa33ec2f481 ("dt-bindings: net: Revert sun8i dwmac binding")
f2c60e
f2c60e
Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
f2c60e
Acked-by: Rob Herring <robh@kernel.org>
f2c60e
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
f2c60e
---
f2c60e
 .../devicetree/bindings/net/dwmac-sun8i.txt        | 84 ++++++++++++++++++++++
f2c60e
 1 file changed, 84 insertions(+)
f2c60e
 create mode 100644 Documentation/devicetree/bindings/net/dwmac-sun8i.txt
f2c60e
f2c60e
diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
f2c60e
new file mode 100644
f2c60e
index 000000000000..725f3b187886
f2c60e
--- /dev/null
f2c60e
+++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
f2c60e
@@ -0,0 +1,84 @@
f2c60e
+* Allwinner sun8i GMAC ethernet controller
f2c60e
+
f2c60e
+This device is a platform glue layer for stmmac.
f2c60e
+Please see stmmac.txt for the other unchanged properties.
f2c60e
+
f2c60e
+Required properties:
f2c60e
+- compatible: should be one of the following string:
f2c60e
+		"allwinner,sun8i-a83t-emac"
f2c60e
+		"allwinner,sun8i-h3-emac"
f2c60e
+		"allwinner,sun8i-v3s-emac"
f2c60e
+		"allwinner,sun50i-a64-emac"
f2c60e
+- reg: address and length of the register for the device.
f2c60e
+- interrupts: interrupt for the device
f2c60e
+- interrupt-names: should be "macirq"
f2c60e
+- clocks: A phandle to the reference clock for this device
f2c60e
+- clock-names: should be "stmmaceth"
f2c60e
+- resets: A phandle to the reset control for this device
f2c60e
+- reset-names: should be "stmmaceth"
f2c60e
+- phy-mode: See ethernet.txt
f2c60e
+- phy-handle: See ethernet.txt
f2c60e
+- #address-cells: shall be 1
f2c60e
+- #size-cells: shall be 0
f2c60e
+- syscon: A phandle to the syscon of the SoC with one of the following
f2c60e
+ compatible string:
f2c60e
+  - allwinner,sun8i-h3-system-controller
f2c60e
+  - allwinner,sun8i-v3s-system-controller
f2c60e
+  - allwinner,sun50i-a64-system-controller
f2c60e
+  - allwinner,sun8i-a83t-system-controller
f2c60e
+
f2c60e
+Optional properties:
f2c60e
+- allwinner,tx-delay-ps: TX clock delay chain value in ps. Range value is 0-700. Default is 0)
f2c60e
+- allwinner,rx-delay-ps: RX clock delay chain value in ps. Range value is 0-3100. Default is 0)
f2c60e
+Both delay properties need to be a multiple of 100. They control the delay for
f2c60e
+external PHY.
f2c60e
+
f2c60e
+Optional properties for the following compatibles:
f2c60e
+  - "allwinner,sun8i-h3-emac",
f2c60e
+  - "allwinner,sun8i-v3s-emac":
f2c60e
+- allwinner,leds-active-low: EPHY LEDs are active low
f2c60e
+
f2c60e
+Required child node of emac:
f2c60e
+- mdio bus node: should be named mdio
f2c60e
+
f2c60e
+Required properties of the mdio node:
f2c60e
+- #address-cells: shall be 1
f2c60e
+- #size-cells: shall be 0
f2c60e
+
f2c60e
+The device node referenced by "phy" or "phy-handle" should be a child node
f2c60e
+of the mdio node. See phy.txt for the generic PHY bindings.
f2c60e
+
f2c60e
+Required properties of the phy node with the following compatibles:
f2c60e
+  - "allwinner,sun8i-h3-emac",
f2c60e
+  - "allwinner,sun8i-v3s-emac":
f2c60e
+- clocks: a phandle to the reference clock for the EPHY
f2c60e
+- resets: a phandle to the reset control for the EPHY
f2c60e
+
f2c60e
+Example:
f2c60e
+
f2c60e
+emac: ethernet@1c0b000 {
f2c60e
+	compatible = "allwinner,sun8i-h3-emac";
f2c60e
+	syscon = <&syscon>;
f2c60e
+	reg = <0x01c0b000 0x104>;
f2c60e
+	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
f2c60e
+	interrupt-names = "macirq";
f2c60e
+	resets = <&ccu RST_BUS_EMAC>;
f2c60e
+	reset-names = "stmmaceth";
f2c60e
+	clocks = <&ccu CLK_BUS_EMAC>;
f2c60e
+	clock-names = "stmmaceth";
f2c60e
+	#address-cells = <1>;
f2c60e
+	#size-cells = <0>;
f2c60e
+
f2c60e
+	phy-handle = <&int_mii_phy>;
f2c60e
+	phy-mode = "mii";
f2c60e
+	allwinner,leds-active-low;
f2c60e
+	mdio: mdio {
f2c60e
+		#address-cells = <1>;
f2c60e
+		#size-cells = <0>;
f2c60e
+		int_mii_phy: ethernet-phy@1 {
f2c60e
+			reg = <1>;
f2c60e
+			clocks = <&ccu CLK_BUS_EPHY>;
f2c60e
+			resets = <&ccu RST_BUS_EPHY>;
f2c60e
+		};
f2c60e
+	};
f2c60e
+};
f2c60e
-- 
f2c60e
2.14.3
f2c60e
f2c60e
From 227bc8c6bfad58c32c7a6c3bbc13d99eb6d266c0 Mon Sep 17 00:00:00 2001
f2c60e
From: Corentin LABBE <clabbe.montjoie@gmail.com>
f2c60e
Date: Tue, 31 Oct 2017 09:19:09 +0100
f2c60e
Subject: [PATCH 05/11] dt-bindings: net: dwmac-sun8i: update documentation
f2c60e
 about integrated PHY
f2c60e
f2c60e
This patch add documentation about the MDIO switch used on sun8i-h3-emac
f2c60e
for integrated PHY.
f2c60e
f2c60e
Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
f2c60e
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
f2c60e
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
f2c60e
---
f2c60e
 .../devicetree/bindings/net/dwmac-sun8i.txt        | 147 +++++++++++++++++++--
f2c60e
 1 file changed, 135 insertions(+), 12 deletions(-)
f2c60e
f2c60e
diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
f2c60e
index 725f3b187886..3d6d5fa0c4d5 100644
f2c60e
--- a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
f2c60e
+++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
f2c60e
@@ -4,18 +4,18 @@ This device is a platform glue layer for stmmac.
f2c60e
 Please see stmmac.txt for the other unchanged properties.
f2c60e
 
f2c60e
 Required properties:
f2c60e
-- compatible: should be one of the following string:
f2c60e
+- compatible: must be one of the following string:
f2c60e
 		"allwinner,sun8i-a83t-emac"
f2c60e
 		"allwinner,sun8i-h3-emac"
f2c60e
 		"allwinner,sun8i-v3s-emac"
f2c60e
 		"allwinner,sun50i-a64-emac"
f2c60e
 - reg: address and length of the register for the device.
f2c60e
 - interrupts: interrupt for the device
f2c60e
-- interrupt-names: should be "macirq"
f2c60e
+- interrupt-names: must be "macirq"
f2c60e
 - clocks: A phandle to the reference clock for this device
f2c60e
-- clock-names: should be "stmmaceth"
f2c60e
+- clock-names: must be "stmmaceth"
f2c60e
 - resets: A phandle to the reset control for this device
f2c60e
-- reset-names: should be "stmmaceth"
f2c60e
+- reset-names: must be "stmmaceth"
f2c60e
 - phy-mode: See ethernet.txt
f2c60e
 - phy-handle: See ethernet.txt
f2c60e
 - #address-cells: shall be 1
f2c60e
@@ -39,23 +39,42 @@ Optional properties for the following compatibles:
f2c60e
 - allwinner,leds-active-low: EPHY LEDs are active low
f2c60e
 
f2c60e
 Required child node of emac:
f2c60e
-- mdio bus node: should be named mdio
f2c60e
+- mdio bus node: should be named mdio with compatible "snps,dwmac-mdio"
f2c60e
 
f2c60e
 Required properties of the mdio node:
f2c60e
 - #address-cells: shall be 1
f2c60e
 - #size-cells: shall be 0
f2c60e
 
f2c60e
-The device node referenced by "phy" or "phy-handle" should be a child node
f2c60e
+The device node referenced by "phy" or "phy-handle" must be a child node
f2c60e
 of the mdio node. See phy.txt for the generic PHY bindings.
f2c60e
 
f2c60e
-Required properties of the phy node with the following compatibles:
f2c60e
+The following compatibles require that the emac node have a mdio-mux child
f2c60e
+node called "mdio-mux":
f2c60e
+  - "allwinner,sun8i-h3-emac"
f2c60e
+  - "allwinner,sun8i-v3s-emac":
f2c60e
+Required properties for the mdio-mux node:
f2c60e
+  - compatible = "allwinner,sun8i-h3-mdio-mux"
f2c60e
+  - mdio-parent-bus: a phandle to EMAC mdio
f2c60e
+  - one child mdio for the integrated mdio with the compatible
f2c60e
+    "allwinner,sun8i-h3-mdio-internal"
f2c60e
+  - one child mdio for the external mdio if present (V3s have none)
f2c60e
+Required properties for the mdio-mux children node:
f2c60e
+  - reg: 1 for internal MDIO bus, 2 for external MDIO bus
f2c60e
+
f2c60e
+The following compatibles require a PHY node representing the integrated
f2c60e
+PHY, under the integrated MDIO bus node if an mdio-mux node is used:
f2c60e
   - "allwinner,sun8i-h3-emac",
f2c60e
   - "allwinner,sun8i-v3s-emac":
f2c60e
+
f2c60e
+Additional information regarding generic multiplexer properties can be found
f2c60e
+at Documentation/devicetree/bindings/net/mdio-mux.txt
f2c60e
+
f2c60e
+Required properties of the integrated phy node:
f2c60e
 - clocks: a phandle to the reference clock for the EPHY
f2c60e
 - resets: a phandle to the reset control for the EPHY
f2c60e
+- Must be a child of the integrated mdio
f2c60e
 
f2c60e
-Example:
f2c60e
-
f2c60e
+Example with integrated PHY:
f2c60e
 emac: ethernet@1c0b000 {
f2c60e
 	compatible = "allwinner,sun8i-h3-emac";
f2c60e
 	syscon = <&syscon>;
f2c60e
@@ -72,13 +91,117 @@ emac: ethernet@1c0b000 {
f2c60e
 	phy-handle = <&int_mii_phy>;
f2c60e
 	phy-mode = "mii";
f2c60e
 	allwinner,leds-active-low;
f2c60e
+
f2c60e
+	mdio: mdio {
f2c60e
+		#address-cells = <1>;
f2c60e
+		#size-cells = <0>;
f2c60e
+		compatible = "snps,dwmac-mdio";
f2c60e
+	};
f2c60e
+
f2c60e
+	mdio-mux {
f2c60e
+		compatible = "mdio-mux", "allwinner,sun8i-h3-mdio-mux";
f2c60e
+		#address-cells = <1>;
f2c60e
+		#size-cells = <0>;
f2c60e
+
f2c60e
+		mdio-parent-bus = <&mdio>;
f2c60e
+
f2c60e
+		int_mdio: mdio@1 {
f2c60e
+			compatible = "allwinner,sun8i-h3-mdio-internal";
f2c60e
+			reg = <1>;
f2c60e
+			#address-cells = <1>;
f2c60e
+			#size-cells = <0>;
f2c60e
+			int_mii_phy: ethernet-phy@1 {
f2c60e
+				reg = <1>;
f2c60e
+				clocks = <&ccu CLK_BUS_EPHY>;
f2c60e
+				resets = <&ccu RST_BUS_EPHY>;
f2c60e
+				phy-is-integrated;
f2c60e
+			};
f2c60e
+		};
f2c60e
+		ext_mdio: mdio@2 {
f2c60e
+			reg = <2>;
f2c60e
+			#address-cells = <1>;
f2c60e
+			#size-cells = <0>;
f2c60e
+		};
f2c60e
+	};
f2c60e
+};
f2c60e
+
f2c60e
+Example with external PHY:
f2c60e
+emac: ethernet@1c0b000 {
f2c60e
+	compatible = "allwinner,sun8i-h3-emac";
f2c60e
+	syscon = <&syscon>;
f2c60e
+	reg = <0x01c0b000 0x104>;
f2c60e
+	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
f2c60e
+	interrupt-names = "macirq";
f2c60e
+	resets = <&ccu RST_BUS_EMAC>;
f2c60e
+	reset-names = "stmmaceth";
f2c60e
+	clocks = <&ccu CLK_BUS_EMAC>;
f2c60e
+	clock-names = "stmmaceth";
f2c60e
+	#address-cells = <1>;
f2c60e
+	#size-cells = <0>;
f2c60e
+
f2c60e
+	phy-handle = <&ext_rgmii_phy>;
f2c60e
+	phy-mode = "rgmii";
f2c60e
+	allwinner,leds-active-low;
f2c60e
+
f2c60e
+	mdio: mdio {
f2c60e
+		#address-cells = <1>;
f2c60e
+		#size-cells = <0>;
f2c60e
+		compatible = "snps,dwmac-mdio";
f2c60e
+	};
f2c60e
+
f2c60e
+	mdio-mux {
f2c60e
+		compatible = "allwinner,sun8i-h3-mdio-mux";
f2c60e
+		#address-cells = <1>;
f2c60e
+		#size-cells = <0>;
f2c60e
+
f2c60e
+		mdio-parent-bus = <&mdio>;
f2c60e
+
f2c60e
+		int_mdio: mdio@1 {
f2c60e
+			compatible = "allwinner,sun8i-h3-mdio-internal";
f2c60e
+			reg = <1>;
f2c60e
+			#address-cells = <1>;
f2c60e
+			#size-cells = <0>;
f2c60e
+			int_mii_phy: ethernet-phy@1 {
f2c60e
+				reg = <1>;
f2c60e
+				clocks = <&ccu CLK_BUS_EPHY>;
f2c60e
+				resets = <&ccu RST_BUS_EPHY>;
f2c60e
+			};
f2c60e
+		};
f2c60e
+		ext_mdio: mdio@2 {
f2c60e
+			reg = <2>;
f2c60e
+			#address-cells = <1>;
f2c60e
+			#size-cells = <0>;
f2c60e
+			ext_rgmii_phy: ethernet-phy@1 {
f2c60e
+				reg = <1>;
f2c60e
+			};
f2c60e
+		}:
f2c60e
+	};
f2c60e
+};
f2c60e
+
f2c60e
+Example with SoC without integrated PHY
f2c60e
+
f2c60e
+emac: ethernet@1c0b000 {
f2c60e
+	compatible = "allwinner,sun8i-a83t-emac";
f2c60e
+	syscon = <&syscon>;
f2c60e
+	reg = <0x01c0b000 0x104>;
f2c60e
+	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
f2c60e
+	interrupt-names = "macirq";
f2c60e
+	resets = <&ccu RST_BUS_EMAC>;
f2c60e
+	reset-names = "stmmaceth";
f2c60e
+	clocks = <&ccu CLK_BUS_EMAC>;
f2c60e
+	clock-names = "stmmaceth";
f2c60e
+	#address-cells = <1>;
f2c60e
+	#size-cells = <0>;
f2c60e
+
f2c60e
+	phy-handle = <&ext_rgmii_phy>;
f2c60e
+	phy-mode = "rgmii";
f2c60e
+
f2c60e
 	mdio: mdio {
f2c60e
+		compatible = "snps,dwmac-mdio";
f2c60e
 		#address-cells = <1>;
f2c60e
 		#size-cells = <0>;
f2c60e
-		int_mii_phy: ethernet-phy@1 {
f2c60e
+		ext_rgmii_phy: ethernet-phy@1 {
f2c60e
 			reg = <1>;
f2c60e
-			clocks = <&ccu CLK_BUS_EPHY>;
f2c60e
-			resets = <&ccu RST_BUS_EPHY>;
f2c60e
 		};
f2c60e
 	};
f2c60e
 };
f2c60e
-- 
f2c60e
2.14.3
f2c60e
f2c60e
From 1de79efa35a1130c7a085f62b9d9b666d79b9a89 Mon Sep 17 00:00:00 2001
f2c60e
From: Peter Robinson <pbrobinson@gmail.com>
f2c60e
Date: Wed, 1 Nov 2017 14:04:20 +0000
f2c60e
Subject: [PATCH 06/11] arm: dts: sunxi: h3/h5: Restore EMAC changes
f2c60e
f2c60e
The original dwmac-sun8i DT bindings have some issue on how to handle
f2c60e
integrated PHY and was reverted in last RC of 4.13.
f2c60e
But now we have a solution so we need to get back that was reverted.
f2c60e
f2c60e
This patch restore sunxi-h3-h5.dtsi
f2c60e
This reverts partially commit fe45174b72ae ("arm: dts: sunxi: Revert EMAC changes")
f2c60e
f2c60e
Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
f2c60e
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
f2c60e
---
f2c60e
 arch/arm/boot/dts/sunxi-h3-h5.dtsi | 26 ++++++++++++++++++++++++++
f2c60e
 1 file changed, 26 insertions(+)
f2c60e
f2c60e
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
f2c60e
index 11240a8313c2..d38282b9e5d4 100644
f2c60e
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
f2c60e
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
f2c60e
@@ -391,6 +391,32 @@
f2c60e
 			clocks = <&osc24M>;
f2c60e
 		};
f2c60e
 
f2c60e
+		emac: ethernet@1c30000 {
f2c60e
+			compatible = "allwinner,sun8i-h3-emac";
f2c60e
+			syscon = <&syscon>;
f2c60e
+			reg = <0x01c30000 0x10000>;
f2c60e
+			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
f2c60e
+			interrupt-names = "macirq";
f2c60e
+			resets = <&ccu RST_BUS_EMAC>;
f2c60e
+			reset-names = "stmmaceth";
f2c60e
+			clocks = <&ccu CLK_BUS_EMAC>;
f2c60e
+			clock-names = "stmmaceth";
f2c60e
+			#address-cells = <1>;
f2c60e
+			#size-cells = <0>;
f2c60e
+			status = "disabled";
f2c60e
+
f2c60e
+			mdio: mdio {
f2c60e
+				#address-cells = <1>;
f2c60e
+				#size-cells = <0>;
f2c60e
+				int_mii_phy: ethernet-phy@1 {
f2c60e
+					compatible = "ethernet-phy-ieee802.3-c22";
f2c60e
+					reg = <1>;
f2c60e
+					clocks = <&ccu CLK_BUS_EPHY>;
f2c60e
+					resets = <&ccu RST_BUS_EPHY>;
f2c60e
+				};
f2c60e
+			};
f2c60e
+		};
f2c60e
+
f2c60e
 		spi0: spi@01c68000 {
f2c60e
 			compatible = "allwinner,sun8i-h3-spi";
f2c60e
 			reg = <0x01c68000 0x1000>;
f2c60e
-- 
f2c60e
2.14.3
f2c60e
f2c60e
From 65233cba93184e0efa8d94f907d65af947d197a1 Mon Sep 17 00:00:00 2001
f2c60e
From: Corentin LABBE <clabbe.montjoie@gmail.com>
f2c60e
Date: Tue, 31 Oct 2017 09:19:11 +0100
f2c60e
Subject: [PATCH 07/11] ARM: dts: sunxi: h3/h5: represent the mdio switch used
f2c60e
 by sun8i-h3-emac
f2c60e
f2c60e
Since dwmac-sun8i could use either an integrated PHY or an external PHY
f2c60e
(which could be at same MDIO address), we need to represent this selection
f2c60e
by a MDIO switch.
f2c60e
f2c60e
Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
f2c60e
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
f2c60e
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
f2c60e
---
f2c60e
 arch/arm/boot/dts/sunxi-h3-h5.dtsi | 31 +++++++++++++++++++++++++++----
f2c60e
 1 file changed, 27 insertions(+), 4 deletions(-)
f2c60e
f2c60e
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
f2c60e
index d38282b9e5d4..2721b39c1875 100644
f2c60e
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
f2c60e
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
f2c60e
@@ -408,11 +408,34 @@
f2c60e
 			mdio: mdio {
f2c60e
 				#address-cells = <1>;
f2c60e
 				#size-cells = <0>;
f2c60e
-				int_mii_phy: ethernet-phy@1 {
f2c60e
-					compatible = "ethernet-phy-ieee802.3-c22";
f2c60e
+				compatible = "snps,dwmac-mdio";
f2c60e
+			};
f2c60e
+
f2c60e
+			mdio-mux {
f2c60e
+				compatible = "allwinner,sun8i-h3-mdio-mux";
f2c60e
+				#address-cells = <1>;
f2c60e
+				#size-cells = <0>;
f2c60e
+
f2c60e
+				mdio-parent-bus = <&mdio>;
f2c60e
+				/* Only one MDIO is usable at the time */
f2c60e
+				internal_mdio: mdio@1 {
f2c60e
+					compatible = "allwinner,sun8i-h3-mdio-internal";
f2c60e
 					reg = <1>;
f2c60e
-					clocks = <&ccu CLK_BUS_EPHY>;
f2c60e
-					resets = <&ccu RST_BUS_EPHY>;
f2c60e
+					#address-cells = <1>;
f2c60e
+					#size-cells = <0>;
f2c60e
+
f2c60e
+					int_mii_phy: ethernet-phy@1 {
f2c60e
+						compatible = "ethernet-phy-ieee802.3-c22";
f2c60e
+						reg = <1>;
f2c60e
+						clocks = <&ccu CLK_BUS_EPHY>;
f2c60e
+						resets = <&ccu RST_BUS_EPHY>;
f2c60e
+					};
f2c60e
+				};
f2c60e
+
f2c60e
+				external_mdio: mdio@2 {
f2c60e
+					reg = <2>;
f2c60e
+					#address-cells = <1>;
f2c60e
+					#size-cells = <0>;
f2c60e
 				};
f2c60e
 			};
f2c60e
 		};
f2c60e
-- 
f2c60e
2.14.3
f2c60e
f2c60e
From b705315d36dbe1b31062f30c987b3a502b437c85 Mon Sep 17 00:00:00 2001
f2c60e
From: Peter Robinson <pbrobinson@gmail.com>
f2c60e
Date: Wed, 1 Nov 2017 14:08:45 +0000
f2c60e
Subject: [PATCH 08/11] ARM: dts: sunxi: Restore EMAC changes (boards)
f2c60e
f2c60e
The original dwmac-sun8i DT bindings have some issue on how to handle
f2c60e
integrated PHY and was reverted in last RC of 4.13.
f2c60e
But now we have a solution so we need to get back that was reverted.
f2c60e
f2c60e
This patch restore all boards DT about dwmac-sun8i
f2c60e
This reverts partially commit fe45174b72ae ("arm: dts: sunxi: Revert EMAC changes")
f2c60e
f2c60e
Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
f2c60e
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
f2c60e
---
f2c60e
 arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts |  9 +++++++++
f2c60e
 arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts   | 19 +++++++++++++++++++
f2c60e
 arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts     | 19 +++++++++++++++++++
f2c60e
 arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts         |  7 +++++++
f2c60e
 arch/arm/boot/dts/sun8i-h3-orangepi-2.dts         |  8 ++++++++
f2c60e
 arch/arm/boot/dts/sun8i-h3-orangepi-one.dts       |  8 ++++++++
f2c60e
 arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts   |  5 +++++
f2c60e
 arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts        |  8 ++++++++
f2c60e
 arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts      | 22 ++++++++++++++++++++++
f2c60e
 arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts    | 16 ++++++++++++++++
f2c60e
 10 files changed, 121 insertions(+)
f2c60e
f2c60e
diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
f2c60e
index b1502df7b509..6713d0f2b3f4 100644
f2c60e
--- a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
f2c60e
+++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
f2c60e
@@ -56,6 +56,8 @@
f2c60e
 
f2c60e
 	aliases {
f2c60e
 		serial0 = &uart;;
f2c60e
+		/* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
f2c60e
+		ethernet0 = &emac;
f2c60e
 		ethernet1 = &xr819;
f2c60e
 	};
f2c60e
 
f2c60e
@@ -102,6 +104,13 @@
f2c60e
 	status = "okay";
f2c60e
 };
f2c60e
 
f2c60e
+&emac {
f2c60e
+	phy-handle = <&int_mii_phy>;
f2c60e
+	phy-mode = "mii";
f2c60e
+	allwinner,leds-active-low;
f2c60e
+	status = "okay";
f2c60e
+};
f2c60e
+
f2c60e
 &mmc0 {
f2c60e
 	pinctrl-names = "default";
f2c60e
 	pinctrl-0 = <&mmc0_pins_a>;
f2c60e
diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
f2c60e
index a337af1de322..3f95d806355b 100644
f2c60e
--- a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
f2c60e
+++ b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
f2c60e
@@ -52,6 +52,7 @@
f2c60e
 	compatible = "sinovoip,bpi-m2-plus", "allwinner,sun8i-h3";
f2c60e
 
f2c60e
 	aliases {
f2c60e
+		ethernet0 = &emac;
f2c60e
 		serial0 = &uart;;
f2c60e
 		serial1 = &uart;;
f2c60e
 	};
f2c60e
@@ -114,6 +115,24 @@
f2c60e
 	status = "okay";
f2c60e
 };
f2c60e
 
f2c60e
+&emac {
f2c60e
+	pinctrl-names = "default";
f2c60e
+	pinctrl-0 = <&emac_rgmii_pins>;
f2c60e
+	phy-supply = <&reg_gmac_3v3>;
f2c60e
+	phy-handle = <&ext_rgmii_phy>;
f2c60e
+	phy-mode = "rgmii";
f2c60e
+
f2c60e
+	allwinner,leds-active-low;
f2c60e
+	status = "okay";
f2c60e
+};
f2c60e
+
f2c60e
+&external_mdio {
f2c60e
+	ext_rgmii_phy: ethernet-phy@1 {
f2c60e
+		compatible = "ethernet-phy-ieee802.3-c22";
f2c60e
+		reg = <0>;
f2c60e
+	};
f2c60e
+};
f2c60e
+
f2c60e
 &ir {
f2c60e
 	pinctrl-names = "default";
f2c60e
 	pinctrl-0 = <&ir_pins_a>;
f2c60e
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
f2c60e
index 8ddd1b2cc097..ef0371811296 100644
f2c60e
--- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
f2c60e
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
f2c60e
@@ -62,3 +62,22 @@
f2c60e
 &ohci2 {
f2c60e
 	status = "okay";
f2c60e
 };
f2c60e
+
f2c60e
+&emac {
f2c60e
+	pinctrl-names = "default";
f2c60e
+	pinctrl-0 = <&emac_rgmii_pins>;
f2c60e
+	phy-supply = <&reg_gmac_3v3>;
f2c60e
+	phy-handle = <&ext_rgmii_phy>;
f2c60e
+	phy-mode = "rgmii";
f2c60e
+
f2c60e
+	allwinner,leds-active-low;
f2c60e
+
f2c60e
+	status = "okay";
f2c60e
+};
f2c60e
+
f2c60e
+&external_mdio {
f2c60e
+	ext_rgmii_phy: ethernet-phy@1 {
f2c60e
+		compatible = "ethernet-phy-ieee802.3-c22";
f2c60e
+		reg = <7>;
f2c60e
+	};
f2c60e
+};
f2c60e
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
f2c60e
index 8d2cc6e9a03f..78f6c24952dd 100644
f2c60e
--- a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
f2c60e
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
f2c60e
@@ -46,3 +46,10 @@
f2c60e
 	model = "FriendlyARM NanoPi NEO";
f2c60e
 	compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3";
f2c60e
 };
f2c60e
+
f2c60e
+&emac {
f2c60e
+	phy-handle = <&int_mii_phy>;
f2c60e
+	phy-mode = "mii";
f2c60e
+	allwinner,leds-active-low;
f2c60e
+	status = "okay";
f2c60e
+};
f2c60e
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
f2c60e
index 8ff71b1bb45b..17cdeae19c6f 100644
f2c60e
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
f2c60e
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
f2c60e
@@ -54,6 +54,7 @@
f2c60e
 	aliases {
f2c60e
 		serial0 = &uart;;
f2c60e
 		/* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
f2c60e
+		ethernet0 = &emac;
f2c60e
 		ethernet1 = &rtl8189;
f2c60e
 	};
f2c60e
 
f2c60e
@@ -117,6 +118,13 @@
f2c60e
 	status = "okay";
f2c60e
 };
f2c60e
 
f2c60e
+&emac {
f2c60e
+	phy-handle = <&int_mii_phy>;
f2c60e
+	phy-mode = "mii";
f2c60e
+	allwinner,leds-active-low;
f2c60e
+	status = "okay";
f2c60e
+};
f2c60e
+
f2c60e
 &ir {
f2c60e
 	pinctrl-names = "default";
f2c60e
 	pinctrl-0 = <&ir_pins_a>;
f2c60e
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
f2c60e
index 5fea430e0eb1..6880268e8b87 100644
f2c60e
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
f2c60e
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
f2c60e
@@ -52,6 +52,7 @@
f2c60e
 	compatible = "xunlong,orangepi-one", "allwinner,sun8i-h3";
f2c60e
 
f2c60e
 	aliases {
f2c60e
+		ethernet0 = &emac;
f2c60e
 		serial0 = &uart;;
f2c60e
 	};
f2c60e
 
f2c60e
@@ -97,6 +98,13 @@
f2c60e
 	status = "okay";
f2c60e
 };
f2c60e
 
f2c60e
+&emac {
f2c60e
+	phy-handle = <&int_mii_phy>;
f2c60e
+	phy-mode = "mii";
f2c60e
+	allwinner,leds-active-low;
f2c60e
+	status = "okay";
f2c60e
+};
f2c60e
+
f2c60e
 &mmc0 {
f2c60e
 	pinctrl-names = "default";
f2c60e
 	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
f2c60e
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts
f2c60e
index 8b93f5c781a7..a10281b455f5 100644
f2c60e
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts
f2c60e
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts
f2c60e
@@ -53,6 +53,11 @@
f2c60e
 	};
f2c60e
 };
f2c60e
 
f2c60e
+&emac {
f2c60e
+	/* LEDs changed to active high on the plus */
f2c60e
+	/delete-property/ allwinner,leds-active-low;
f2c60e
+};
f2c60e
+
f2c60e
 &mmc1 {
f2c60e
 	pinctrl-names = "default";
f2c60e
 	pinctrl-0 = <&mmc1_pins_a>;
f2c60e
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
f2c60e
index 1a044b17d6c6..998b60f8d295 100644
f2c60e
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
f2c60e
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
f2c60e
@@ -52,6 +52,7 @@
f2c60e
 	compatible = "xunlong,orangepi-pc", "allwinner,sun8i-h3";
f2c60e
 
f2c60e
 	aliases {
f2c60e
+		ethernet0 = &emac;
f2c60e
 		serial0 = &uart;;
f2c60e
 	};
f2c60e
 
f2c60e
@@ -113,6 +114,13 @@
f2c60e
 	status = "okay";
f2c60e
 };
f2c60e
 
f2c60e
+&emac {
f2c60e
+	phy-handle = <&int_mii_phy>;
f2c60e
+	phy-mode = "mii";
f2c60e
+	allwinner,leds-active-low;
f2c60e
+	status = "okay";
f2c60e
+};
f2c60e
+
f2c60e
 &ir {
f2c60e
 	pinctrl-names = "default";
f2c60e
 	pinctrl-0 = <&ir_pins_a>;
f2c60e
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
f2c60e
index 828ae7a526d9..3002c025e187 100644
f2c60e
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
f2c60e
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
f2c60e
@@ -47,6 +47,10 @@
f2c60e
 	model = "Xunlong Orange Pi Plus / Plus 2";
f2c60e
 	compatible = "xunlong,orangepi-plus", "allwinner,sun8i-h3";
f2c60e
 
f2c60e
+	aliases {
f2c60e
+		ethernet0 = &emac;
f2c60e
+	};
f2c60e
+
f2c60e
 	reg_gmac_3v3: gmac-3v3 {
f2c60e
 		compatible = "regulator-fixed";
f2c60e
 		regulator-name = "gmac-3v3";
f2c60e
@@ -74,6 +78,24 @@
f2c60e
 	status = "okay";
f2c60e
 };
f2c60e
 
f2c60e
+&emac {
f2c60e
+	pinctrl-names = "default";
f2c60e
+	pinctrl-0 = <&emac_rgmii_pins>;
f2c60e
+	phy-supply = <&reg_gmac_3v3>;
f2c60e
+	phy-handle = <&ext_rgmii_phy>;
f2c60e
+	phy-mode = "rgmii";
f2c60e
+
f2c60e
+	allwinner,leds-active-low;
f2c60e
+	status = "okay";
f2c60e
+};
f2c60e
+
f2c60e
+&external_mdio {
f2c60e
+	ext_rgmii_phy: ethernet-phy@1 {
f2c60e
+		compatible = "ethernet-phy-ieee802.3-c22";
f2c60e
+		reg = <0>;
f2c60e
+	};
f2c60e
+};
f2c60e
+
f2c60e
 &mmc2 {
f2c60e
 	pinctrl-names = "default";
f2c60e
 	pinctrl-0 = <&mmc2_8bit_pins>;
f2c60e
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts
f2c60e
index 97920b12a944..6dbf7b2e0c13 100644
f2c60e
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts
f2c60e
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts
f2c60e
@@ -61,3 +61,19 @@
f2c60e
 		gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
f2c60e
 	};
f2c60e
 };
f2c60e
+
f2c60e
+&emac {
f2c60e
+	pinctrl-names = "default";
f2c60e
+	pinctrl-0 = <&emac_rgmii_pins>;
f2c60e
+	phy-supply = <&reg_gmac_3v3>;
f2c60e
+	phy-handle = <&ext_rgmii_phy>;
f2c60e
+	phy-mode = "rgmii";
f2c60e
+	status = "okay";
f2c60e
+};
f2c60e
+
f2c60e
+&external_mdio {
f2c60e
+	ext_rgmii_phy: ethernet-phy@1 {
f2c60e
+		compatible = "ethernet-phy-ieee802.3-c22";
f2c60e
+		reg = <1>;
f2c60e
+	};
f2c60e
+};
f2c60e
-- 
f2c60e
2.14.3
f2c60e
f2c60e
From 516b88bfa40cf54732d2ba5e689fdf592a742ec3 Mon Sep 17 00:00:00 2001
f2c60e
From: Corentin LABBE <clabbe.montjoie@gmail.com>
f2c60e
Date: Tue, 31 Oct 2017 09:19:13 +0100
f2c60e
Subject: [PATCH 09/11] arm64: dts: allwinner: A64: Restore EMAC changes
f2c60e
f2c60e
The original dwmac-sun8i DT bindings have some issue on how to handle
f2c60e
integrated PHY and was reverted in last RC of 4.13.
f2c60e
But now we have a solution so we need to get back that was reverted.
f2c60e
f2c60e
This patch restore arm64 DT about dwmac-sun8i for A64
f2c60e
This reverts commit 87e1f5e8bb4b ("arm64: dts: allwinner: Revert EMAC changes")
f2c60e
f2c60e
Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
f2c60e
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
f2c60e
---
f2c60e
 .../boot/dts/allwinner/sun50i-a64-bananapi-m64.dts   | 16 ++++++++++++++++
f2c60e
 .../boot/dts/allwinner/sun50i-a64-pine64-plus.dts    | 15 +++++++++++++++
f2c60e
 arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts  | 17 +++++++++++++++++
f2c60e
 .../dts/allwinner/sun50i-a64-sopine-baseboard.dts    | 16 ++++++++++++++++
f2c60e
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi        | 20 ++++++++++++++++++++
f2c60e
 5 files changed, 84 insertions(+)
f2c60e
f2c60e
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
f2c60e
index d347f52e27f6..45bdbfb96126 100644
f2c60e
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
f2c60e
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
f2c60e
@@ -51,6 +51,7 @@
f2c60e
 	compatible = "sinovoip,bananapi-m64", "allwinner,sun50i-a64";
f2c60e
 
f2c60e
 	aliases {
f2c60e
+		ethernet0 = &emac;
f2c60e
 		serial0 = &uart;;
f2c60e
 		serial1 = &uart;;
f2c60e
 	};
f2c60e
@@ -69,6 +70,14 @@
f2c60e
 	status = "okay";
f2c60e
 };
f2c60e
 
f2c60e
+&emac {
f2c60e
+	pinctrl-names = "default";
f2c60e
+	pinctrl-0 = <&rgmii_pins>;
f2c60e
+	phy-mode = "rgmii";
f2c60e
+	phy-handle = <&ext_rgmii_phy>;
f2c60e
+	status = "okay";
f2c60e
+};
f2c60e
+
f2c60e
 &i2c1 {
f2c60e
 	pinctrl-names = "default";
f2c60e
 	pinctrl-0 = <&i2c1_pins>;
f2c60e
@@ -79,6 +88,13 @@
f2c60e
 	bias-pull-up;
f2c60e
 };
f2c60e
 
f2c60e
+&mdio {
f2c60e
+	ext_rgmii_phy: ethernet-phy@1 {
f2c60e
+		compatible = "ethernet-phy-ieee802.3-c22";
f2c60e
+		reg = <1>;
f2c60e
+	};
f2c60e
+};
f2c60e
+
f2c60e
 &mmc0 {
f2c60e
 	pinctrl-names = "default";
f2c60e
 	pinctrl-0 = <&mmc0_pins>;
f2c60e
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
f2c60e
index f82ccf332c0f..24f1aac366d6 100644
f2c60e
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
f2c60e
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
f2c60e
@@ -48,3 +48,18 @@
f2c60e
 
f2c60e
 	/* TODO: Camera, touchscreen, etc. */
f2c60e
 };
f2c60e
+
f2c60e
+&emac {
f2c60e
+	pinctrl-names = "default";
f2c60e
+	pinctrl-0 = <&rgmii_pins>;
f2c60e
+	phy-mode = "rgmii";
f2c60e
+	phy-handle = <&ext_rgmii_phy>;
f2c60e
+	status = "okay";
f2c60e
+};
f2c60e
+
f2c60e
+&mdio {
f2c60e
+	ext_rgmii_phy: ethernet-phy@1 {
f2c60e
+		compatible = "ethernet-phy-ieee802.3-c22";
f2c60e
+		reg = <1>;
f2c60e
+	};
f2c60e
+};
f2c60e
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
f2c60e
index d06e34b5d192..806442d3e846 100644
f2c60e
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
f2c60e
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
f2c60e
@@ -51,6 +51,7 @@
f2c60e
 	compatible = "pine64,pine64", "allwinner,sun50i-a64";
f2c60e
 
f2c60e
 	aliases {
f2c60e
+		ethernet0 = &emac;
f2c60e
 		serial0 = &uart;;
f2c60e
 		serial1 = &uart;;
f2c60e
 		serial2 = &uart;;
f2c60e
@@ -71,6 +72,15 @@
f2c60e
 	status = "okay";
f2c60e
 };
f2c60e
 
f2c60e
+&emac {
f2c60e
+	pinctrl-names = "default";
f2c60e
+	pinctrl-0 = <&rmii_pins>;
f2c60e
+	phy-mode = "rmii";
f2c60e
+	phy-handle = <&ext_rmii_phy1>;
f2c60e
+	status = "okay";
f2c60e
+
f2c60e
+};
f2c60e
+
f2c60e
 &i2c1 {
f2c60e
 	pinctrl-names = "default";
f2c60e
 	pinctrl-0 = <&i2c1_pins>;
f2c60e
@@ -81,6 +91,13 @@
f2c60e
 	bias-pull-up;
f2c60e
 };
f2c60e
 
f2c60e
+&mdio {
f2c60e
+	ext_rmii_phy1: ethernet-phy@1 {
f2c60e
+		compatible = "ethernet-phy-ieee802.3-c22";
f2c60e
+		reg = <1>;
f2c60e
+	};
f2c60e
+};
f2c60e
+
f2c60e
 &mmc0 {
f2c60e
 	pinctrl-names = "default";
f2c60e
 	pinctrl-0 = <&mmc0_pins>;
f2c60e
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
f2c60e
index 17ccc12b58df..0eb2acedf8c3 100644
f2c60e
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
f2c60e
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
f2c60e
@@ -53,6 +53,7 @@
f2c60e
 		     "allwinner,sun50i-a64";
f2c60e
 
f2c60e
 	aliases {
f2c60e
+		ethernet0 = &emac;
f2c60e
 		serial0 = &uart;;
f2c60e
 	};
f2c60e
 
f2c60e
@@ -76,6 +77,21 @@
f2c60e
 	status = "okay";
f2c60e
 };
f2c60e
 
f2c60e
+&emac {
f2c60e
+	pinctrl-names = "default";
f2c60e
+	pinctrl-0 = <&rgmii_pins>;
f2c60e
+	phy-mode = "rgmii";
f2c60e
+	phy-handle = <&ext_rgmii_phy>;
f2c60e
+	status = "okay";
f2c60e
+};
f2c60e
+
f2c60e
+&mdio {
f2c60e
+	ext_rgmii_phy: ethernet-phy@1 {
f2c60e
+		compatible = "ethernet-phy-ieee802.3-c22";
f2c60e
+		reg = <1>;
f2c60e
+	};
f2c60e
+};
f2c60e
+
f2c60e
 &mmc2 {
f2c60e
 	pinctrl-names = "default";
f2c60e
 	pinctrl-0 = <&mmc2_pins>;
f2c60e
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
f2c60e
index 8c8db1b057df..50f17bab0c07 100644
f2c60e
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
f2c60e
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
f2c60e
@@ -449,6 +449,26 @@
f2c60e
 			#size-cells = <0>;
f2c60e
 		};
f2c60e
 
f2c60e
+		emac: ethernet@1c30000 {
f2c60e
+			compatible = "allwinner,sun50i-a64-emac";
f2c60e
+			syscon = <&syscon>;
f2c60e
+			reg = <0x01c30000 0x10000>;
f2c60e
+			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
f2c60e
+			interrupt-names = "macirq";
f2c60e
+			resets = <&ccu RST_BUS_EMAC>;
f2c60e
+			reset-names = "stmmaceth";
f2c60e
+			clocks = <&ccu CLK_BUS_EMAC>;
f2c60e
+			clock-names = "stmmaceth";
f2c60e
+			status = "disabled";
f2c60e
+			#address-cells = <1>;
f2c60e
+			#size-cells = <0>;
f2c60e
+
f2c60e
+			mdio: mdio {
f2c60e
+				#address-cells = <1>;
f2c60e
+				#size-cells = <0>;
f2c60e
+			};
f2c60e
+		};
f2c60e
+
f2c60e
 		gic: interrupt-controller@1c81000 {
f2c60e
 			compatible = "arm,gic-400";
f2c60e
 			reg = <0x01c81000 0x1000>,
f2c60e
-- 
f2c60e
2.14.3
f2c60e
f2c60e
From 070173449eb88e9cf9c91889c77f53616911f4d0 Mon Sep 17 00:00:00 2001
f2c60e
From: Corentin LABBE <clabbe.montjoie@gmail.com>
f2c60e
Date: Tue, 31 Oct 2017 09:19:14 +0100
f2c60e
Subject: [PATCH 10/11] arm64: dts: allwinner: H5: Restore EMAC changes
f2c60e
f2c60e
The original dwmac-sun8i DT bindings have some issue on how to handle
f2c60e
integrated PHY and was reverted in last RC of 4.13.
f2c60e
But now we have a solution so we need to get back that was reverted.
f2c60e
f2c60e
This patch restore arm64 DT about dwmac-sun8i for H5
f2c60e
This reverts a part of commit 87e1f5e8bb4b ("arm64: dts: allwinner: Revert EMAC changes")
f2c60e
f2c60e
Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
f2c60e
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
f2c60e
---
f2c60e
 arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts | 17 +++++++++++++++++
f2c60e
 .../arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts | 17 +++++++++++++++++
f2c60e
 .../boot/dts/allwinner/sun50i-h5-orangepi-prime.dts     | 17 +++++++++++++++++
f2c60e
 3 files changed, 51 insertions(+)
f2c60e
f2c60e
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts
f2c60e
index 1c2387bd5df6..6eb8092d8e57 100644
f2c60e
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts
f2c60e
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts
f2c60e
@@ -50,6 +50,7 @@
f2c60e
 	compatible = "friendlyarm,nanopi-neo2", "allwinner,sun50i-h5";
f2c60e
 
f2c60e
 	aliases {
f2c60e
+		ethernet0 = &emac;
f2c60e
 		serial0 = &uart;;
f2c60e
 	};
f2c60e
 
f2c60e
@@ -108,6 +109,22 @@
f2c60e
 	status = "okay";
f2c60e
 };
f2c60e
 
f2c60e
+&emac {
f2c60e
+	pinctrl-names = "default";
f2c60e
+	pinctrl-0 = <&emac_rgmii_pins>;
f2c60e
+	phy-supply = <&reg_gmac_3v3>;
f2c60e
+	phy-handle = <&ext_rgmii_phy>;
f2c60e
+	phy-mode = "rgmii";
f2c60e
+	status = "okay";
f2c60e
+};
f2c60e
+
f2c60e
+&external_mdio {
f2c60e
+	ext_rgmii_phy: ethernet-phy@7 {
f2c60e
+		compatible = "ethernet-phy-ieee802.3-c22";
f2c60e
+		reg = <7>;
f2c60e
+	};
f2c60e
+};
f2c60e
+
f2c60e
 &mmc0 {
f2c60e
 	pinctrl-names = "default";
f2c60e
 	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
f2c60e
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
f2c60e
index 4f77c8470f6c..a0ca925175aa 100644
f2c60e
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
f2c60e
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
f2c60e
@@ -59,6 +59,7 @@
f2c60e
 	};
f2c60e
 
f2c60e
 	aliases {
f2c60e
+		ethernet0 = &emac;
f2c60e
 		serial0 = &uart;;
f2c60e
 	};
f2c60e
 
f2c60e
@@ -136,6 +137,22 @@
f2c60e
 	status = "okay";
f2c60e
 };
f2c60e
 
f2c60e
+&emac {
f2c60e
+	pinctrl-names = "default";
f2c60e
+	pinctrl-0 = <&emac_rgmii_pins>;
f2c60e
+	phy-supply = <&reg_gmac_3v3>;
f2c60e
+	phy-handle = <&ext_rgmii_phy>;
f2c60e
+	phy-mode = "rgmii";
f2c60e
+	status = "okay";
f2c60e
+};
f2c60e
+
f2c60e
+&external_mdio {
f2c60e
+	ext_rgmii_phy: ethernet-phy@1 {
f2c60e
+		compatible = "ethernet-phy-ieee802.3-c22";
f2c60e
+		reg = <1>;
f2c60e
+	};
f2c60e
+};
f2c60e
+
f2c60e
 &ir {
f2c60e
 	pinctrl-names = "default";
f2c60e
 	pinctrl-0 = <&ir_pins_a>;
f2c60e
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
f2c60e
index 6be06873e5af..b47790650144 100644
f2c60e
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
f2c60e
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
f2c60e
@@ -54,6 +54,7 @@
f2c60e
 	compatible = "xunlong,orangepi-prime", "allwinner,sun50i-h5";
f2c60e
 
f2c60e
 	aliases {
f2c60e
+		ethernet0 = &emac;
f2c60e
 		serial0 = &uart;;
f2c60e
 	};
f2c60e
 
f2c60e
@@ -143,6 +144,22 @@
f2c60e
 	status = "okay";
f2c60e
 };
f2c60e
 
f2c60e
+&emac {
f2c60e
+	pinctrl-names = "default";
f2c60e
+	pinctrl-0 = <&emac_rgmii_pins>;
f2c60e
+	phy-supply = <&reg_gmac_3v3>;
f2c60e
+	phy-handle = <&ext_rgmii_phy>;
f2c60e
+	phy-mode = "rgmii";
f2c60e
+	status = "okay";
f2c60e
+};
f2c60e
+
f2c60e
+&external_mdio {
f2c60e
+	ext_rgmii_phy: ethernet-phy@1 {
f2c60e
+		compatible = "ethernet-phy-ieee802.3-c22";
f2c60e
+		reg = <1>;
f2c60e
+	};
f2c60e
+};
f2c60e
+
f2c60e
 &ir {
f2c60e
 	pinctrl-names = "default";
f2c60e
 	pinctrl-0 = <&ir_pins_a>;
f2c60e
-- 
f2c60e
2.14.3
f2c60e
f2c60e
From 63118a9f7808a0a67c23e7d276138c996e094eae Mon Sep 17 00:00:00 2001
f2c60e
From: Corentin LABBE <clabbe.montjoie@gmail.com>
f2c60e
Date: Tue, 31 Oct 2017 09:19:15 +0100
f2c60e
Subject: [PATCH 11/11] arm64: dts: allwinner: add snps, dwmac-mdio compatible
f2c60e
 to emac/mdio
f2c60e
f2c60e
stmmac bindings docs said that its mdio node must have
f2c60e
compatible = "snps,dwmac-mdio";
f2c60e
Since dwmac-sun8i does not have any good reasons to not doing it, all
f2c60e
their MDIO node must have it.
f2c60e
f2c60e
Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
f2c60e
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
f2c60e
---
f2c60e
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 1 +
f2c60e
 1 file changed, 1 insertion(+)
f2c60e
f2c60e
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
f2c60e
index 50f17bab0c07..8fd75c95937a 100644
f2c60e
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
f2c60e
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
f2c60e
@@ -464,6 +464,7 @@
f2c60e
 			#size-cells = <0>;
f2c60e
 
f2c60e
 			mdio: mdio {
f2c60e
+				compatible = "snps,dwmac-mdio";
f2c60e
 				#address-cells = <1>;
f2c60e
 				#size-cells = <0>;
f2c60e
 			};
f2c60e
-- 
f2c60e
2.14.3
f2c60e
f2c60e
From patchwork Fri Nov 10 09:26:54 2017
f2c60e
Content-Type: text/plain; charset="utf-8"
f2c60e
MIME-Version: 1.0
f2c60e
Content-Transfer-Encoding: 7bit
f2c60e
Subject: arm64: allwinner: a64: add Ethernet PHY regulator for several boards
f2c60e
From: Icenowy Zheng <icenowy@aosc.io>
f2c60e
X-Patchwork-Id: 10052659
f2c60e
Message-Id: <20171110092654.10746-1-icenowy@aosc.io>
f2c60e
To: Maxime Ripard <maxime.ripard@free-electrons.com>,
f2c60e
 Chen-Yu Tsai <wens@csie.org>
f2c60e
Cc: linux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org,
f2c60e
 linux-arm-kernel@lists.infradead.org, Icenowy Zheng <icenowy@aosc.io>
f2c60e
Date: Fri, 10 Nov 2017 17:26:54 +0800
f2c60e
f2c60e
On several A64 boards the Ethernet PHY is powered by the DC1SW regulator
f2c60e
on the AXP803 PMIC.
f2c60e
f2c60e
Add phy-handle property to these boards' emac node.
f2c60e
f2c60e
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
f2c60e
Acked-by: Corentin LABBE <clabbe.montjoie@gmail.com>
f2c60e
Tested-by: Corentin LABBE <clabbe.montjoie@gmail.com>
f2c60e
---
f2c60e
 arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts     | 1 +
f2c60e
 arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts           | 1 +
f2c60e
 arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts | 1 +
f2c60e
 3 files changed, 3 insertions(+)
f2c60e
f2c60e
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
f2c60e
index 45bdbfb96126..4a8d3f83a36e 100644
f2c60e
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
f2c60e
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
f2c60e
@@ -75,6 +75,7 @@
f2c60e
 	pinctrl-0 = <&rgmii_pins>;
f2c60e
 	phy-mode = "rgmii";
f2c60e
 	phy-handle = <&ext_rgmii_phy>;
f2c60e
+	phy-supply = <&reg_dc1sw>;
f2c60e
 	status = "okay";
f2c60e
 };
f2c60e
 
f2c60e
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
f2c60e
index 806442d3e846..604cdaedac38 100644
f2c60e
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
f2c60e
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
f2c60e
@@ -77,6 +77,7 @@
f2c60e
 	pinctrl-0 = <&rmii_pins>;
f2c60e
 	phy-mode = "rmii";
f2c60e
 	phy-handle = <&ext_rmii_phy1>;
f2c60e
+	phy-supply = <&reg_dc1sw>;
f2c60e
 	status = "okay";
f2c60e
 
f2c60e
 };
f2c60e
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
f2c60e
index 0eb2acedf8c3..a053a6ac5267 100644
f2c60e
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
f2c60e
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
f2c60e
@@ -82,6 +82,7 @@
f2c60e
 	pinctrl-0 = <&rgmii_pins>;
f2c60e
 	phy-mode = "rgmii";
f2c60e
 	phy-handle = <&ext_rgmii_phy>;
f2c60e
+	phy-supply = <&reg_dc1sw>;
f2c60e
 	status = "okay";
f2c60e
 };
f2c60e
 
f2c60e
From 79e7d6c8bfe67fce8c8fe4953e74ce7f420dd732 Mon Sep 17 00:00:00 2001
f2c60e
From: Peter Robinson <pbrobinson@gmail.com>
f2c60e
Date: Tue, 21 Nov 2017 15:43:19 +0000
f2c60e
Subject: [PATCH] ARM: dts: sunxi: sun8i-h3-nanopi-m1-plus: Add missing
f2c60e
 regulator
f2c60e
f2c60e
This patch add the missing regulator for sun8i-h3-nanopi-m1-plus.
f2c60e
f2c60e
Fixes: ("ARM: dts: sunxi: Restore EMAC changes (boards)")
f2c60e
Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
f2c60e
---
f2c60e
 arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts | 11 +++++++++++
f2c60e
 1 file changed, 11 insertions(+)
f2c60e
f2c60e
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
f2c60e
index ef0371811296..738ef1d9e844 100644
f2c60e
--- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
f2c60e
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
f2c60e
@@ -45,6 +45,17 @@
f2c60e
 / {
f2c60e
 	model = "FriendlyArm NanoPi M1 Plus";
f2c60e
 	compatible = "friendlyarm,nanopi-m1-plus", "allwinner,sun8i-h3";
f2c60e
+
f2c60e
+        reg_gmac_3v3: gmac-3v3 {
f2c60e
+                compatible = "regulator-fixed";
f2c60e
+                regulator-name = "gmac-3v3";
f2c60e
+                regulator-min-microvolt = <3300000>;
f2c60e
+                regulator-max-microvolt = <3300000>;
f2c60e
+                startup-delay-us = <100000>;
f2c60e
+                enable-active-high;
f2c60e
+                gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
f2c60e
+        };
f2c60e
+
f2c60e
 };
f2c60e
 
f2c60e
 &ehci1 {
f2c60e
-- 
f2c60e
2.14.3
f2c60e
f2c60e
From 4497478c60c04d2bf37082e27fc98f4f835db96b Mon Sep 17 00:00:00 2001
f2c60e
From: Niklas Cassel <niklas.cassel@axis.com>
f2c60e
Date: Tue, 14 Nov 2017 11:15:54 +0100
f2c60e
Subject: net: stmmac: fix LPI transitioning for dwmac4
f2c60e
f2c60e
The LPI transitioning logic in stmmac_main uses
f2c60e
priv->tx_path_in_lpi_mode to enter/exit LPI.
f2c60e
f2c60e
However, priv->tx_path_in_lpi_mode is assigned
f2c60e
using the return value from host_irq_status().
f2c60e
f2c60e
So for dwmac4, priv->tx_path_in_lpi_mode was always false,
f2c60e
so stmmac_tx_clean() would always try to put us in eee mode,
f2c60e
and stmmac_xmit() would never take us out of eee mode.
f2c60e
f2c60e
To fix this, make host_irq_status() read and return the LPI
f2c60e
irq status also for dwmac4.
f2c60e
f2c60e
This also increments the existing LPI counters, so that
f2c60e
ethtool --statistics shows LPI transitions also for dwmac4.
f2c60e
f2c60e
For dwmac1000, irqs are enabled/disabled using the register
f2c60e
named "Interrupt Mask Register", and thus setting a bit disables
f2c60e
that specific irq.
f2c60e
f2c60e
For dwmac4 the matching register is named "MAC_Interrupt_Enable",
f2c60e
and thus setting a bit enables that specific irq.
f2c60e
f2c60e
Looking at dwmac1000_core.c, the irqs that are always enabled are:
f2c60e
LPI and PMT.
f2c60e
f2c60e
Looking at dwmac4_core.c, the irqs that are always enabled are:
f2c60e
PMT.
f2c60e
f2c60e
To be able to read the LPI irq status, we need to enable the LPI
f2c60e
irq also for dwmac4.
f2c60e
f2c60e
Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
f2c60e
Signed-off-by: David S. Miller <davem@davemloft.net>
f2c60e
---
f2c60e
 drivers/net/ethernet/stmicro/stmmac/dwmac4.h      |  7 ++++++-
f2c60e
 drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c | 19 +++++++++++++++++++
f2c60e
 2 files changed, 25 insertions(+), 1 deletion(-)
f2c60e
f2c60e
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h
f2c60e
index aeda3ab..789dad8 100644
f2c60e
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h
f2c60e
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h
f2c60e
@@ -98,7 +98,7 @@
f2c60e
 #define	GMAC_PCS_IRQ_DEFAULT	(GMAC_INT_RGSMIIS | GMAC_INT_PCS_LINK |	\
f2c60e
 				 GMAC_INT_PCS_ANE)
f2c60e
 
f2c60e
-#define	GMAC_INT_DEFAULT_MASK	GMAC_INT_PMT_EN
f2c60e
+#define	GMAC_INT_DEFAULT_MASK	(GMAC_INT_PMT_EN | GMAC_INT_LPI_EN)
f2c60e
 
f2c60e
 enum dwmac4_irq_status {
f2c60e
 	time_stamp_irq = 0x00001000,
f2c60e
@@ -106,6 +106,7 @@ enum dwmac4_irq_status {
f2c60e
 	mmc_tx_irq = 0x00000400,
f2c60e
 	mmc_rx_irq = 0x00000200,
f2c60e
 	mmc_irq = 0x00000100,
f2c60e
+	lpi_irq = 0x00000020,
f2c60e
 	pmt_irq = 0x00000010,
f2c60e
 };
f2c60e
 
f2c60e
@@ -132,6 +133,10 @@ enum power_event {
f2c60e
 #define GMAC4_LPI_CTRL_STATUS_LPITXA	BIT(19)	/* Enable LPI TX Automate */
f2c60e
 #define GMAC4_LPI_CTRL_STATUS_PLS	BIT(17) /* PHY Link Status */
f2c60e
 #define GMAC4_LPI_CTRL_STATUS_LPIEN	BIT(16)	/* LPI Enable */
f2c60e
+#define GMAC4_LPI_CTRL_STATUS_RLPIEX	BIT(3) /* Receive LPI Exit */
f2c60e
+#define GMAC4_LPI_CTRL_STATUS_RLPIEN	BIT(2) /* Receive LPI Entry */
f2c60e
+#define GMAC4_LPI_CTRL_STATUS_TLPIEX	BIT(1) /* Transmit LPI Exit */
f2c60e
+#define GMAC4_LPI_CTRL_STATUS_TLPIEN	BIT(0) /* Transmit LPI Entry */
f2c60e
 
f2c60e
 /* MAC Debug bitmap */
f2c60e
 #define GMAC_DEBUG_TFCSTS_MASK		GENMASK(18, 17)
f2c60e
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
f2c60e
index 2f7d7ec..f3ed8f7 100644
f2c60e
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
f2c60e
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
f2c60e
@@ -580,6 +580,25 @@ static int dwmac4_irq_status(struct mac_device_info *hw,
f2c60e
 		x->irq_receive_pmt_irq_n++;
f2c60e
 	}
f2c60e
 
f2c60e
+	/* MAC tx/rx EEE LPI entry/exit interrupts */
f2c60e
+	if (intr_status & lpi_irq) {
f2c60e
+		/* Clear LPI interrupt by reading MAC_LPI_Control_Status */
f2c60e
+		u32 status = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
f2c60e
+
f2c60e
+		if (status & GMAC4_LPI_CTRL_STATUS_TLPIEN) {
f2c60e
+			ret |= CORE_IRQ_TX_PATH_IN_LPI_MODE;
f2c60e
+			x->irq_tx_path_in_lpi_mode_n++;
f2c60e
+		}
f2c60e
+		if (status & GMAC4_LPI_CTRL_STATUS_TLPIEX) {
f2c60e
+			ret |= CORE_IRQ_TX_PATH_EXIT_LPI_MODE;
f2c60e
+			x->irq_tx_path_exit_lpi_mode_n++;
f2c60e
+		}
f2c60e
+		if (status & GMAC4_LPI_CTRL_STATUS_RLPIEN)
f2c60e
+			x->irq_rx_path_in_lpi_mode_n++;
f2c60e
+		if (status & GMAC4_LPI_CTRL_STATUS_RLPIEX)
f2c60e
+			x->irq_rx_path_exit_lpi_mode_n++;
f2c60e
+	}
f2c60e
+
f2c60e
 	dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x);
f2c60e
 	if (intr_status & PCS_RGSMIIIS_IRQ)
f2c60e
 		dwmac4_phystatus(ioaddr, x);
f2c60e
-- 
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cgit v1.1
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From 1c08ac0c4bd8e9d66c4dde29bc496c3b430dd028 Mon Sep 17 00:00:00 2001
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From: Corentin Labbe <clabbe.montjoie@gmail.com>
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Date: Tue, 28 Nov 2017 17:48:22 +0100
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Subject: net: stmmac: dwmac-sun8i: fix allwinner,leds-active-low handling
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The driver expect "allwinner,leds-active-low" to be in PHY node, but
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the binding doc expect it to be in MAC node.
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Since all board DT use it also in MAC node, the driver need to search
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allwinner,leds-active-low in MAC node.
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Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 3 +--
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 1 file changed, 1 insertion(+), 2 deletions(-)
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diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
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index e5ff734..9eb7f65 100644
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--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
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+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
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@@ -808,8 +808,7 @@ static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv)
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 			 val, reg);
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 	if (gmac->variant->soc_has_internal_phy) {
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-		if (of_property_read_bool(priv->plat->phy_node,
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-					  "allwinner,leds-active-low"))
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+		if (of_property_read_bool(node, "allwinner,leds-active-low"))
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 			reg |= H3_EPHY_LED_POL;
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 		else
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 			reg &= ~H3_EPHY_LED_POL;
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-- 
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cgit v1.1
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