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Combination of the following two upstream patches to make
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Xeon Phi work correctly.
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commit ca535e7eb7cd1df884189a36949499d17c297456
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Author: Brice Goglin <Brice.Goglin@inria.fr>
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Date: Thu Apr 30 16:25:05 2015 +0200
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x86: CPUID 0x1b is actually supported when we have the x2apic feature
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Thanks to Grzegorz Andrejczuk and Lukasz Anaczkowski.
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commit 2119a8b499f73c2759380ccbad89bc4c0c297f11
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Author: Brice Goglin <Brice.Goglin@inria.fr>
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Date: Thu Apr 30 16:27:24 2015 +0200
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x86: Also get the real APIC ID from the x2APIC code
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This fixes support for the upcoming Knights Landing Xeon Phi.
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Thanks to Grzegorz Andrejczuk and Lukasz Anaczkowski.
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diff -Nrup hwloc-1.7.orig/src/topology-x86.c hwloc-1.7/src/topology-x86.c
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--- hwloc-1.7.orig/src/topology-x86.c 2013-03-26 16:00:17.000000000 -0400
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+++ hwloc-1.7/src/topology-x86.c 2015-07-14 16:59:47.457390618 -0400
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@@ -23,6 +23,7 @@
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#include <private/cpuid.h>
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#define has_topoext(features) ((features)[6] & (1 << 22))
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+#define has_x2apic(features) ((features)[4] & (1 << 21))
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struct cacheinfo {
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unsigned type;
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@@ -301,7 +302,7 @@ static void look_proc(struct procinfo *i
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}
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}
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- if (cpuid_type == intel && highest_cpuid >= 0x0b) {
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+ if (cpuid_type == intel && has_x2apic(features)) {
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unsigned level, apic_nextshift, apic_number, apic_type, apic_id = 0, apic_shift = 0, id;
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for (level = 0; ; level++) {
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ecx = level;
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@@ -341,8 +342,10 @@ static void look_proc(struct procinfo *i
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}
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apic_shift = apic_nextshift;
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}
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+ infos->apicid = apic_id;
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infos->socketid = apic_id >> apic_shift;
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hwloc_debug("x2APIC remainder: %d\n", infos->socketid);
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+ hwloc_debug("this is thread %u of core %u\n", infos->threadid, infos->coreid);
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} else
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infos->otherids = NULL;
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} else
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