|
 |
94084c |
commit b952c25dc7adf0684c53ad72d1d667da0348c929
|
|
|
94084c |
Author: H.J. Lu <hjl.tools@gmail.com>
|
|
|
94084c |
Date: Fri Jan 14 14:48:01 2022 -0800
|
|
|
94084c |
|
|
|
94084c |
x86: Black list more Intel CPUs for TSX [BZ #27398]
|
|
|
94084c |
|
|
|
94084c |
Disable TSX and enable RTM_ALWAYS_ABORT for Intel CPUs listed in:
|
|
|
94084c |
|
|
|
94084c |
https://www.intel.com/content/www/us/en/support/articles/000059422/processors.html
|
|
|
94084c |
|
|
|
94084c |
This fixes BZ #27398.
|
|
|
94084c |
|
|
|
94084c |
Reviewed-by: Noah Goldstein <goldstein.w.n@gmail.com>
|
|
|
94084c |
(cherry picked from commit 1e000d3d33211d5a954300e2a69b90f93f18a1a1)
|
|
|
94084c |
|
|
|
94084c |
diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
|
|
|
94084c |
index 645bba63147f6589..de4e3c3b7258120d 100644
|
|
|
94084c |
--- a/sysdeps/x86/cpu-features.c
|
|
|
94084c |
+++ b/sysdeps/x86/cpu-features.c
|
|
|
94084c |
@@ -507,11 +507,39 @@ init_cpu_features (struct cpu_features *cpu_features)
|
|
|
94084c |
break;
|
|
|
94084c |
}
|
|
|
94084c |
|
|
|
94084c |
- /* Disable TSX on some Haswell processors to avoid TSX on kernels that
|
|
|
94084c |
- weren't updated with the latest microcode package (which disables
|
|
|
94084c |
- broken feature by default). */
|
|
|
94084c |
+ /* Disable TSX on some processors to avoid TSX on kernels that
|
|
|
94084c |
+ weren't updated with the latest microcode package (which
|
|
|
94084c |
+ disables broken feature by default). */
|
|
|
94084c |
switch (model)
|
|
|
94084c |
{
|
|
|
94084c |
+ case 0x55:
|
|
|
94084c |
+ if (stepping <= 5)
|
|
|
94084c |
+ goto disable_tsx;
|
|
|
94084c |
+ break;
|
|
|
94084c |
+ case 0x8e:
|
|
|
94084c |
+ /* NB: Although the errata documents that for model == 0x8e,
|
|
|
94084c |
+ only 0xb stepping or lower are impacted, the intention of
|
|
|
94084c |
+ the errata was to disable TSX on all client processors on
|
|
|
94084c |
+ all steppings. Include 0xc stepping which is an Intel
|
|
|
94084c |
+ Core i7-8665U, a client mobile processor. */
|
|
|
94084c |
+ case 0x9e:
|
|
|
94084c |
+ if (stepping > 0xc)
|
|
|
94084c |
+ break;
|
|
|
94084c |
+ /* Fall through. */
|
|
|
94084c |
+ case 0x4e:
|
|
|
94084c |
+ case 0x5e:
|
|
|
94084c |
+ {
|
|
|
94084c |
+ /* Disable Intel TSX and enable RTM_ALWAYS_ABORT for
|
|
|
94084c |
+ processors listed in:
|
|
|
94084c |
+
|
|
|
94084c |
+https://www.intel.com/content/www/us/en/support/articles/000059422/processors.html
|
|
|
94084c |
+ */
|
|
|
94084c |
+disable_tsx:
|
|
|
94084c |
+ CPU_FEATURE_UNSET (cpu_features, HLE);
|
|
|
94084c |
+ CPU_FEATURE_UNSET (cpu_features, RTM);
|
|
|
94084c |
+ CPU_FEATURE_SET (cpu_features, RTM_ALWAYS_ABORT);
|
|
|
94084c |
+ }
|
|
|
94084c |
+ break;
|
|
|
94084c |
case 0x3f:
|
|
|
94084c |
/* Xeon E7 v3 with stepping >= 4 has working TSX. */
|
|
|
94084c |
if (stepping >= 4)
|