6ca6e8
commit 691f70b84a1284f35c8cf9fbf3ef3b1cec41c234
6ca6e8
Author: Vladislav Khmelevsky <och95@yandex.ru>
6ca6e8
Date:   Thu Nov 17 12:47:29 2022 +0400
6ca6e8
6ca6e8
    elf: Fix rtld-audit trampoline for aarch64
6ca6e8
    
6ca6e8
    This patch fixes two problems with audit:
6ca6e8
    
6ca6e8
      1. The DL_OFFSET_RV_VPCS offset was mixed up with DL_OFFSET_RG_VPCS,
6ca6e8
         resulting in x2 register value nulling in RG structure.
6ca6e8
    
6ca6e8
      2. We need to preserve the x8 register before function call, but
6ca6e8
         don't have to save it's new value and restore it before return.
6ca6e8
    
6ca6e8
    Anyway the final restore was using OFFSET_RV instead of OFFSET_RG value
6ca6e8
    which is wrong (althoug doesn't affect anything).
6ca6e8
    
6ca6e8
    Reviewed-by: Adhemerval Zanella  <adhemerval.zanella@linaro.org>
6ca6e8
    (cherry picked from commit eb4181e9f4a512de37dad4ba623c921671584dea)
6ca6e8
6ca6e8
diff --git a/sysdeps/aarch64/dl-trampoline.S b/sysdeps/aarch64/dl-trampoline.S
6ca6e8
index 457570e7df5148c0..b84c53d1a544c1b1 100644
6ca6e8
--- a/sysdeps/aarch64/dl-trampoline.S
6ca6e8
+++ b/sysdeps/aarch64/dl-trampoline.S
6ca6e8
@@ -298,12 +298,11 @@ _dl_runtime_profile:
6ca6e8
 	stp	x2, x3, [x29, #OFFSET_RV + DL_OFFSET_RV_X0 + 16*1]
6ca6e8
 	stp	x4, x5, [x29, #OFFSET_RV + DL_OFFSET_RV_X0 + 16*2]
6ca6e8
 	stp	x6, x7, [x29, #OFFSET_RV + DL_OFFSET_RV_X0 + 16*3]
6ca6e8
-	str	x8,     [x29, #OFFSET_RG + DL_OFFSET_RG_X0 + 16*4]
6ca6e8
 	stp	q0, q1, [x29, #OFFSET_RV + DL_OFFSET_RV_V0 + 32*0]
6ca6e8
 	stp	q2, q3, [x29, #OFFSET_RV + DL_OFFSET_RV_V0 + 32*1]
6ca6e8
 	stp	q4, q5, [x29, #OFFSET_RV + DL_OFFSET_RV_V0 + 32*2]
6ca6e8
 	stp	q6, q7, [x29, #OFFSET_RV + DL_OFFSET_RV_V0 + 32*3]
6ca6e8
-	str	xzr,    [X29, #OFFSET_RV + DL_OFFSET_RG_VPCS]
6ca6e8
+	str	xzr,    [X29, #OFFSET_RV + DL_OFFSET_RV_VPCS]
6ca6e8
 
6ca6e8
 	/* Setup call to pltexit  */
6ca6e8
 	ldp	x0, x1, [x29, #OFFSET_SAVED_CALL_X0]
6ca6e8
@@ -315,7 +314,6 @@ _dl_runtime_profile:
6ca6e8
 	ldp	x2, x3, [x29, #OFFSET_RV + DL_OFFSET_RV_X0 + 16*1]
6ca6e8
 	ldp	x4, x5, [x29, #OFFSET_RV + DL_OFFSET_RV_X0 + 16*2]
6ca6e8
 	ldp	x6, x7, [x29, #OFFSET_RV + DL_OFFSET_RV_X0 + 16*3]
6ca6e8
-	ldr	x8,     [x29, #OFFSET_RV + DL_OFFSET_RV_X0 + 16*4]
6ca6e8
 	ldp	q0, q1, [x29, #OFFSET_RV + DL_OFFSET_RV_V0 + 32*0]
6ca6e8
 	ldp	q2, q3, [x29, #OFFSET_RV + DL_OFFSET_RV_V0 + 32*1]
6ca6e8
 	ldp	q4, q5, [x29, #OFFSET_RV + DL_OFFSET_RV_V0 + 32*2]