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		08c3a6	`commit d201c59177b98946d7f80145e7b4d02991d04805`
		08c3a6	`Author: Noah Goldstein <goldstein.w.n@gmail.com>`
		08c3a6	`Date: Fri Jun 24 09:42:12 2022 -0700`
		08c3a6
		08c3a6	`x86: Align entry for memrchr to 64-bytes.`
		08c3a6
		08c3a6	`The function was tuned around 64-byte entry alignment and performs`
		08c3a6	`better for all sizes with it.`
		08c3a6
		08c3a6	`As well different code boths where explicitly written to touch the`
		08c3a6	`minimum number of cache line i.e sizes <= 32 touch only the entry`
		08c3a6	`cache line.`
		08c3a6
		08c3a6	`(cherry picked from commit 227afaa67213efcdce6a870ef5086200f1076438)`
		08c3a6
		08c3a6	`diff --git a/sysdeps/x86_64/multiarch/memrchr-avx2.S b/sysdeps/x86_64/multiarch/memrchr-avx2.S`
		08c3a6	`index 5f8e0be18cfe4fad..edd8180ba1ede9a5 100644`
		08c3a6	`--- a/sysdeps/x86_64/multiarch/memrchr-avx2.S`
		08c3a6	`+++ b/sysdeps/x86_64/multiarch/memrchr-avx2.S`
		08c3a6	`@@ -35,7 +35,7 @@`
		08c3a6	`# define VEC_SIZE 32`
		08c3a6	`# define PAGE_SIZE 4096`
		08c3a6	`.section SECTION(.text), "ax", @progbits`
		08c3a6	`-ENTRY(MEMRCHR)`
		08c3a6	`+ENTRY_P2ALIGN(MEMRCHR, 6)`
		08c3a6	`# ifdef __ILP32__`
		08c3a6	`/* Clear upper bits. */`
		08c3a6	`and %RDX_LP, %RDX_LP`