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This is a combination of two commits:
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From 42b373ad467ba426610a358d90034bcf68abb15f Mon Sep 17 00:00:00 2001
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From: Edjunior Machado <emachado@linux.vnet.ibm.com>
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Date: Thu, 23 May 2013 10:06:24 -0500
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Subject: [PATCH 31/42] PowerPC: Add functions for shared resources hints.
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 (cherry picked from commit
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 9323d39baea2fb0cca3735136abe263eff405133)
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From a6d45052042c1fc962523633c0489634864e1a02 Mon Sep 17 00:00:00 2001
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From: Adhemerval Zanella <azanella@linux.vnet.ibm.com>
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Date: Fri, 24 May 2013 13:29:30 -0500
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Subject: [PATCH 32/42] PowerPC: Program Priority Register support
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This patch add inline functions to change the Program Priority Register
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from ISA 2.05.
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(cherry picked from commit d116b7c414c8239b677e341ac517745db689ac2d)
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diff -pruN glibc-2.17-c758a686/manual/platform.texi glibc-2.17-c758a686/manual/platform.texi
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--- glibc-2.17-c758a686/manual/platform.texi	2012-12-25 08:32:13.000000000 +0530
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+++ glibc-2.17-c758a686/manual/platform.texi	2013-08-05 19:06:49.523550318 +0530
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@@ -34,3 +34,48 @@ This frequency is not related to the pro
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 It is also possible that this frequency is not constant.  More information is
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 available in @cite{Power ISA 2.06b - Book II - Section 5.2}.
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 @end deftypefun
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+
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+The following functions provide hints about the usage of resources that are
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+shared with other processors.  They can be used, for example, if a program
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+waiting on a lock intends to divert the shared resources to be used by other
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+processors.  More information is available in @cite{Power ISA 2.06b - Book II -
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+Section 3.2}.
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+
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+@deftypefun {void} __ppc_yield (void)
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+Provide a hint that performance will probably be improved if shared resources
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+dedicated to the executing processor are released for use by other processors.
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+@end deftypefun
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+
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+@deftypefun {void} __ppc_mdoio (void)
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+Provide a hint that performance will probably be improved if shared resources
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+dedicated to the executing processor are released until all outstanding storage
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+accesses to caching-inhibited storage have been completed.
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+@end deftypefun
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+
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+@deftypefun {void} __ppc_mdoom (void)
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+Provide a hint that performance will probably be improved if shared resources
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+dedicated to the executing processor are released until all outstanding storage
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+accesses to cacheable storage for which the data is not in the cache have been
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+completed.
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+@end deftypefun
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+
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+@deftypefun {void} __ppc_set_ppr_med (void)
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+Set the Program Priority Register to medium value (default).
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+
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+The @dfn{Program Priority Register} (PPR) is a 64-bit register that controls
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+the program's priority.  By adjusting the PPR value the programmer may
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+improve system throughput by causing the system resources to be used
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+more efficiently, especially in contention situations.
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+The three unprivileged states available are covered by the functions
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+@code{__ppc_set_ppr_med} (medium -- default), @code{__ppc_set_ppc_low} (low)
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+and @code{__ppc_set_ppc_med_low} (medium low).  More information
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+available in @cite{Power ISA 2.06b - Book II - Section 3.1}.
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+@end deftypefun
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+
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+@deftypefun {void} __ppc_set_ppr_low (void)
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+Set the Program Priority Register to low value.
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+@end deftypefun
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+
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+@deftypefun {void} __ppc_set_ppr_med_low (void)
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+Set the Program Priority Register to medium low value.
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+@end deftypefun
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diff -pruN glibc-2.17-c758a686/sysdeps/powerpc/sys/platform/ppc.h glibc-2.17-c758a686/sysdeps/powerpc/sys/platform/ppc.h
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--- glibc-2.17-c758a686/sysdeps/powerpc/sys/platform/ppc.h	2012-12-25 08:32:13.000000000 +0530
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+++ glibc-2.17-c758a686/sysdeps/powerpc/sys/platform/ppc.h	2013-08-05 19:06:49.523550318 +0530
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@@ -50,4 +50,66 @@ __ppc_get_timebase (void)
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 #endif
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 }
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+/* The following functions provide hints about the usage of shared processor
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+   resources, as defined in ISA 2.06 and newer. */
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+
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+/* Provides a hint that performance will probably be improved if shared
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+   resources dedicated to the executing processor are released for use by other
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+   processors.  */
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+static inline void
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+__ppc_yield (void)
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+{
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+  __asm__ volatile ("or 27,27,27");
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+}
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+
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+/* Provides a hint that performance will probably be improved if shared
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+   resources dedicated to the executing processor are released until
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+   all outstanding storage accesses to caching-inhibited storage have been
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+   completed.  */
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+static inline void
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+__ppc_mdoio (void)
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+{
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+  __asm__ volatile ("or 29,29,29");
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+}
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+
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+/* Provides a hint that performance will probably be improved if shared
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+   resources dedicated to the executing processor are released until all
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+   outstanding storage accesses to cacheable storage for which the data is not
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+   in the cache have been completed.  */
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+static inline void
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+__ppc_mdoom (void)
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+{
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+  __asm__ volatile ("or 30,30,30");
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+}
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+
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+
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+/* ISA 2.05 and beyond support the Program Priority Register (PPR) to adjust
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+   thread priorities based on lock acquisition, wait and release. The ISA
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+   defines the use of form 'or Rx,Rx,Rx' as the way to modify the PRI field.
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+   The unprivileged priorities are:
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+     Rx = 1 (low)
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+     Rx = 2 (medium)
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+     Rx = 6 (medium-low/normal)
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+   The 'or' instruction form is a nop in previous hardware, so it is safe to
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+   use unguarded. The default value is 'medium'.
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+ */
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+
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+static inline void
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+__ppc_set_ppr_med (void)
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+{
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+  __asm__ volatile ("or 2,2,2");
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+}
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+
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+static inline void
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+__ppc_set_ppr_med_low (void)
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+{
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+  __asm__ volatile ("or 6,6,6");
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+}
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+
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+static inline void
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+__ppc_set_ppr_low (void)
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+{
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+  __asm__ volatile ("or 1,1,1");
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+}
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+
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 #endif  /* sys/platform/ppc.h */