|
|
cb4ff2 |
From 82c7441f04e3c2a653ee29672731e040a1799c6b Mon Sep 17 00:00:00 2001
|
|
|
cb4ff2 |
From: Matheus Castanho <msc@linux.ibm.com>
|
|
|
cb4ff2 |
Date: Tue, 7 Jun 2022 10:27:26 -0300
|
|
|
cb4ff2 |
Subject: powerpc: Fix VSX register number on __strncpy_power9 [BZ #29197]
|
|
|
cb4ff2 |
|
|
|
cb4ff2 |
__strncpy_power9 initializes VR 18 with zeroes to be used throughout the
|
|
|
cb4ff2 |
code, including when zero-padding the destination string. However, the
|
|
|
cb4ff2 |
v18 reference was mistakenly being used for stxv and stxvl, which take a
|
|
|
cb4ff2 |
VSX vector as operand. The code ended up using the uninitialized VSR 18
|
|
|
cb4ff2 |
register by mistake.
|
|
|
cb4ff2 |
|
|
|
cb4ff2 |
Both occurrences have been changed to use the proper VSX number for VR 18
|
|
|
cb4ff2 |
(i.e. VSR 50).
|
|
|
cb4ff2 |
|
|
|
cb4ff2 |
Tested on powerpc, powerpc64 and powerpc64le.
|
|
|
cb4ff2 |
|
|
|
cb4ff2 |
Signed-off-by: Kewen Lin <linkw@gcc.gnu.org>
|
|
|
cb4ff2 |
(cherry picked from commit 0218463dd8265ed937622f88ac68c7d984fe0cfc)
|
|
|
cb4ff2 |
|
|
|
cb4ff2 |
diff --git a/sysdeps/powerpc/powerpc64/le/power9/strncpy.S b/sysdeps/powerpc/powerpc64/le/power9/strncpy.S
|
|
|
cb4ff2 |
index 291941c1e5..5421525ace 100644
|
|
|
cb4ff2 |
--- a/sysdeps/powerpc/powerpc64/le/power9/strncpy.S
|
|
|
cb4ff2 |
+++ b/sysdeps/powerpc/powerpc64/le/power9/strncpy.S
|
|
|
cb4ff2 |
@@ -352,7 +352,7 @@ L(zero_padding_loop):
|
|
|
cb4ff2 |
cmpldi cr6,r5,16 /* Check if length was reached. */
|
|
|
cb4ff2 |
ble cr6,L(zero_padding_end)
|
|
|
cb4ff2 |
|
|
|
cb4ff2 |
- stxv v18,0(r11)
|
|
|
cb4ff2 |
+ stxv 32+v18,0(r11)
|
|
|
cb4ff2 |
addi r11,r11,16
|
|
|
cb4ff2 |
addi r5,r5,-16
|
|
|
cb4ff2 |
|
|
|
cb4ff2 |
@@ -360,7 +360,7 @@ L(zero_padding_loop):
|
|
|
cb4ff2 |
|
|
|
cb4ff2 |
L(zero_padding_end):
|
|
|
cb4ff2 |
sldi r10,r5,56 /* stxvl wants size in top 8 bits */
|
|
|
cb4ff2 |
- stxvl v18,r11,r10 /* Partial store */
|
|
|
cb4ff2 |
+ stxvl 32+v18,r11,r10 /* Partial store */
|
|
|
cb4ff2 |
blr
|
|
|
cb4ff2 |
|
|
|
cb4ff2 |
.align 4
|