|
|
c5d972 |
From a5db6a5cae6a92d1675c013e5c8d972768721576 Mon Sep 17 00:00:00 2001
|
|
|
c5d972 |
From: Wilco Dijkstra <wdijkstr@arm.com>
|
|
|
c5d972 |
Date: Tue, 10 Aug 2021 13:46:20 +0100
|
|
|
c5d972 |
Subject: [PATCH] [5/5] AArch64: Improve A64FX memset medium loops
|
|
|
c5d972 |
|
|
|
c5d972 |
Simplify the code for memsets smaller than L1. Improve the unroll8 and
|
|
|
c5d972 |
L1_prefetch loops.
|
|
|
c5d972 |
|
|
|
c5d972 |
Reviewed-by: Naohiro Tamura <naohirot@fujitsu.com>
|
|
|
c5d972 |
---
|
|
|
c5d972 |
sysdeps/aarch64/multiarch/memset_a64fx.S | 45 ++++++++++--------------
|
|
|
c5d972 |
1 file changed, 19 insertions(+), 26 deletions(-)
|
|
|
c5d972 |
|
|
|
c5d972 |
diff --git a/sysdeps/aarch64/multiarch/memset_a64fx.S b/sysdeps/aarch64/multiarch/memset_a64fx.S
|
|
|
c5d972 |
index ef0315658a..7bf759b6a7 100644
|
|
|
c5d972 |
--- a/sysdeps/aarch64/multiarch/memset_a64fx.S
|
|
|
c5d972 |
+++ b/sysdeps/aarch64/multiarch/memset_a64fx.S
|
|
|
c5d972 |
@@ -30,7 +30,6 @@
|
|
|
c5d972 |
#define L2_SIZE (8*1024*1024) // L2 8MB
|
|
|
c5d972 |
#define CACHE_LINE_SIZE 256
|
|
|
c5d972 |
#define PF_DIST_L1 (CACHE_LINE_SIZE * 16) // Prefetch distance L1
|
|
|
c5d972 |
-#define rest x2
|
|
|
c5d972 |
#define vector_length x9
|
|
|
c5d972 |
|
|
|
c5d972 |
#if HAVE_AARCH64_SVE_ASM
|
|
|
c5d972 |
@@ -89,29 +88,19 @@ ENTRY (MEMSET)
|
|
|
c5d972 |
|
|
|
c5d972 |
.p2align 4
|
|
|
c5d972 |
L(vl_agnostic): // VL Agnostic
|
|
|
c5d972 |
- mov rest, count
|
|
|
c5d972 |
mov dst, dstin
|
|
|
c5d972 |
- add dstend, dstin, count
|
|
|
c5d972 |
- // if rest >= L2_SIZE && vector_length == 64 then L(L2)
|
|
|
c5d972 |
- mov tmp1, 64
|
|
|
c5d972 |
- cmp rest, L2_SIZE
|
|
|
c5d972 |
- ccmp vector_length, tmp1, 0, cs
|
|
|
c5d972 |
- b.eq L(L2)
|
|
|
c5d972 |
- // if rest >= L1_SIZE && vector_length == 64 then L(L1_prefetch)
|
|
|
c5d972 |
- cmp rest, L1_SIZE
|
|
|
c5d972 |
- ccmp vector_length, tmp1, 0, cs
|
|
|
c5d972 |
- b.eq L(L1_prefetch)
|
|
|
c5d972 |
-
|
|
|
c5d972 |
+ cmp count, L1_SIZE
|
|
|
c5d972 |
+ b.hi L(L1_prefetch)
|
|
|
c5d972 |
|
|
|
c5d972 |
+ // count >= 8 * vector_length
|
|
|
c5d972 |
L(unroll8):
|
|
|
c5d972 |
- lsl tmp1, vector_length, 3
|
|
|
c5d972 |
- .p2align 3
|
|
|
c5d972 |
-1: cmp rest, tmp1
|
|
|
c5d972 |
- b.cc L(last)
|
|
|
c5d972 |
- st1b_unroll
|
|
|
c5d972 |
+ sub count, count, tmp1
|
|
|
c5d972 |
+ .p2align 4
|
|
|
c5d972 |
+1: st1b_unroll 0, 7
|
|
|
c5d972 |
add dst, dst, tmp1
|
|
|
c5d972 |
- sub rest, rest, tmp1
|
|
|
c5d972 |
- b 1b
|
|
|
c5d972 |
+ subs count, count, tmp1
|
|
|
c5d972 |
+ b.hi 1b
|
|
|
c5d972 |
+ add count, count, tmp1
|
|
|
c5d972 |
|
|
|
c5d972 |
L(last):
|
|
|
c5d972 |
cmp count, vector_length, lsl 1
|
|
|
c5d972 |
@@ -129,18 +118,22 @@ L(last):
|
|
|
c5d972 |
st1b z0.b, p0, [dstend, -1, mul vl]
|
|
|
c5d972 |
ret
|
|
|
c5d972 |
|
|
|
c5d972 |
-L(L1_prefetch): // if rest >= L1_SIZE
|
|
|
c5d972 |
+ // count >= L1_SIZE
|
|
|
c5d972 |
.p2align 3
|
|
|
c5d972 |
+L(L1_prefetch):
|
|
|
c5d972 |
+ cmp count, L2_SIZE
|
|
|
c5d972 |
+ b.hs L(L2)
|
|
|
c5d972 |
+ cmp vector_length, 64
|
|
|
c5d972 |
+ b.ne L(unroll8)
|
|
|
c5d972 |
1: st1b_unroll 0, 3
|
|
|
c5d972 |
prfm pstl1keep, [dst, PF_DIST_L1]
|
|
|
c5d972 |
st1b_unroll 4, 7
|
|
|
c5d972 |
prfm pstl1keep, [dst, PF_DIST_L1 + CACHE_LINE_SIZE]
|
|
|
c5d972 |
add dst, dst, CACHE_LINE_SIZE * 2
|
|
|
c5d972 |
- sub rest, rest, CACHE_LINE_SIZE * 2
|
|
|
c5d972 |
- cmp rest, L1_SIZE
|
|
|
c5d972 |
- b.ge 1b
|
|
|
c5d972 |
- cbnz rest, L(unroll8)
|
|
|
c5d972 |
- ret
|
|
|
c5d972 |
+ sub count, count, CACHE_LINE_SIZE * 2
|
|
|
c5d972 |
+ cmp count, PF_DIST_L1
|
|
|
c5d972 |
+ b.hs 1b
|
|
|
c5d972 |
+ b L(unroll8)
|
|
|
c5d972 |
|
|
|
c5d972 |
// count >= L2_SIZE
|
|
|
c5d972 |
.p2align 3
|
|
|
c5d972 |
--
|
|
|
c5d972 |
2.31.1
|
|
|
c5d972 |
|