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commit 23fdf8178cce3c2ec320dd5eca8b544245bcaef0
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Author: Raoni Fassina Firmino <raoni@linux.ibm.com>
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Date: Fri Apr 30 18:12:08 2021 -0300
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powerpc64le: Optimize memset for POWER10
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This implementation is based on __memset_power8 and integrates a lot
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of suggestions from Anton Blanchard.
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The biggest difference is that it makes extensive use of stxvl to
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alignment and tail code to avoid branches and small stores. It has
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three main execution paths:
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a) "Short lengths" for lengths up to 64 bytes, avoiding as many
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branches as possible.
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b) "General case" for larger lengths, it has an alignment section
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using stxvl to avoid branches, a 128 bytes loop and then a tail
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code, again using stxvl with few branches.
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c) "Zeroing cache blocks" for lengths from 256 bytes upwards and set
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value being zero. It is mostly the __memset_power8 code but the
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alignment phase was simplified because, at this point, address is
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already 16-bytes aligned and also changed to use vector stores.
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The tail code was also simplified to reuse the general case tail.
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All unaligned stores use stxvl instructions that do not generate
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alignment interrupts on POWER10, making it safe to use on
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caching-inhibited memory.
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On average, this implementation provides something around 30%
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improvement when compared to __memset_power8.
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Reviewed-by: Matheus Castanho <msc@linux.ibm.com>
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Reviewed-by: Tulio Magno Quites Machado Filho <tuliom@linux.ibm.com>
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diff --git a/sysdeps/powerpc/powerpc64/le/power10/memset.S b/sysdeps/powerpc/powerpc64/le/power10/memset.S
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new file mode 100644
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index 0000000000000000..6b8e2cfdaf25fd30
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--- /dev/null
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+++ b/sysdeps/powerpc/powerpc64/le/power10/memset.S
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@@ -0,0 +1,256 @@
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+/* Optimized memset implementation for POWER10 LE.
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+ Copyright (C) 2021 Free Software Foundation, Inc.
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+ This file is part of the GNU C Library.
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+
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+ The GNU C Library is free software; you can redistribute it and/or
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+ modify it under the terms of the GNU Lesser General Public
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+ License as published by the Free Software Foundation; either
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+ version 2.1 of the License, or (at your option) any later version.
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+
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+ The GNU C Library is distributed in the hope that it will be useful,
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+ but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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+ Lesser General Public License for more details.
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+
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+ You should have received a copy of the GNU Lesser General Public
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+ License along with the GNU C Library; if not, see
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+ <https://www.gnu.org/licenses/>. */
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+
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+#include <sysdep.h>
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+
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+/* void * [r3] memset (void *s [r3], int c [r4], size_t n [r5]));
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+ Returns 's'. */
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+
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+#ifndef MEMSET
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+# define MEMSET memset
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+#endif
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+
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+ .machine power9
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+ENTRY_TOCLESS (MEMSET, 5)
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+ CALL_MCOUNT 3
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+
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+L(_memset):
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+ /* Assume memset of zero length is uncommon, and just let it go
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+ through the small path below. */
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+ cmpldi r5,64
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+
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+ /* Replicate byte to quad word. */
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+ mtvsrd v0+32,r4
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+ vspltb v0,v0,7
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+
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+ li r7,16
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+ sldi r8,r7,56
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+
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+ bgt L(large)
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+
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+ /* For short lengths we want to avoid as many branches as possible.
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+ We use store VSX vector with length instructions to do this.
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+ It takes advantage of the fact that if the length passed to stxvl
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+ is zero nothing is done, effectively a no-op. */
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+ sldi r5,r5,56
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+
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+ addi r10,r3,16
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+
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+ sub. r11,r5,r8
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+ isellt r11,0,r11 /* Saturate the subtraction to zero. */
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+
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+ stxvl v0+32,r3,r5
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+ stxvl v0+32,r10,r11
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+
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+ addi r9,r3,32
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+ addi r10,r3,48
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+
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+ sub. r11,r11,r8
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+ isellt r11,0,r11
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+
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+ sub. r5,r11,r8
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+ isellt r5,0,r5
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+
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+ stxvl v0+32,r9,r11
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+ stxvl v0+32,r10,r5
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+
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+ blr
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+
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+ .balign 16
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+L(large):
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+ mr r6,r3 /* Don't modify r3 since we need to return it. */
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+
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+ /* Get dest 16B aligned. */
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+ neg r0,r3
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+ clrldi. r7,r0,(64-4)
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+ beq L(aligned)
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+ rldic r9,r0,56,4 /* (~X & 0xf)<<56 "clrlsldi r9,r0,64-4,56". */
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+
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+ stxvl v0+32,r6,r9 /* Store up to 15B until aligned address. */
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+
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+ add r6,r6,r7
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+ sub r5,r5,r7
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+
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+ /* Go to tail if there is less than 64B left after alignment. */
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+ cmpldi r5,64
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+ blt L(tail_64)
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+
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+ .balign 16
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+L(aligned):
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+ /* Go to tail if there is less than 128B left after alignment. */
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+ srdi. r0,r5,7
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+ beq L(tail_128)
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+
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+ /* If c == 0 && n >= 256 use dcbz to zero out full cache blocks. */
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+ cmpldi cr5,r5,255
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+ cmpldi cr6,r4,0
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+ crand 27,26,21
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+ bt 27,L(dcbz)
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+
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+ mtctr r0
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+
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+ .balign 32
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+L(loop):
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+ stxv v0+32,0(r6)
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+ stxv v0+32,16(r6)
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+ stxv v0+32,32(r6)
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+ stxv v0+32,48(r6)
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+ stxv v0+32,64(r6)
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+ stxv v0+32,80(r6)
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+ stxv v0+32,96(r6)
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+ stxv v0+32,112(r6)
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+ addi r6,r6,128
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+ bdnz L(loop)
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+
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+ .balign 16
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+L(tail):
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+ /* 127B or less left, finish the tail or return. */
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+ andi. r5,r5,127
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+ beqlr
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+
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+ cmpldi r5,64
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+ blt L(tail_64)
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+
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+ .balign 16
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+L(tail_128):
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+ /* Stores a minimum of 64B and up to 128B and return. */
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+ stxv v0+32,0(r6)
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+ stxv v0+32,16(r6)
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+ stxv v0+32,32(r6)
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+ stxv v0+32,48(r6)
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+ addi r6,r6,64
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+ andi. r5,r5,63
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+ beqlr
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+
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+ .balign 16
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+L(tail_64):
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+ /* Stores up to 64B and return. */
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+ sldi r5,r5,56
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+
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+ addi r10,r6,16
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+
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+ sub. r11,r5,r8
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+ isellt r11,0,r11
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+
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+ stxvl v0+32,r6,r5
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+ stxvl v0+32,r10,r11
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+
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+ sub. r11,r11,r8
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+ blelr
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+
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+ addi r9,r6,32
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+ addi r10,r6,48
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+
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+ isellt r11,0,r11
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+
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+ sub. r5,r11,r8
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+ isellt r5,0,r5
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+
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+ stxvl v0+32,r9,r11
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+ stxvl v0+32,r10,r5
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+
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+ blr
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+
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+ .balign 16
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+L(dcbz):
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+ /* Special case when value is 0 and we have a long length to deal
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+ with. Use dcbz to zero out a full cacheline of 128 bytes at a time.
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+ Before using dcbz though, we need to get the destination 128-byte
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+ aligned. */
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+ neg r0,r6
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+ clrldi. r0,r0,(64-7)
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+ beq L(dcbz_aligned)
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+
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+ sub r5,r5,r0
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+ mtocrf 0x2,r0 /* copying bits 57..59 to cr6. The ones for sizes 64,
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+ 32 and 16 which need to be checked. */
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+
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+ /* Write 16-128 bytes until DST is aligned to 128 bytes. */
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+64: bf 25,32f
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+ stxv v0+32,0(r6)
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+ stxv v0+32,16(r6)
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+ stxv v0+32,32(r6)
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+ stxv v0+32,48(r6)
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+ addi r6,r6,64
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+
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+32: bf 26,16f
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+ stxv v0+32,0(r6)
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+ stxv v0+32,16(r6)
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+ addi r6,r6,32
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+
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+16: bf 27,L(dcbz_aligned)
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+ stxv v0+32,0(r6)
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+ addi r6,r6,16
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+
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8a984d |
+ .balign 16
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8a984d |
+L(dcbz_aligned):
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8a984d |
+ /* Setup dcbz unroll offsets and count numbers. */
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8a984d |
+ srdi. r0,r5,9
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+ li r9,128
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+ beq L(bcdz_tail)
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+ li r10,256
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+ li r11,384
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+ mtctr r0
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+
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8a984d |
+ .balign 16
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8a984d |
+L(dcbz_loop):
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8a984d |
+ /* Sets 512 bytes to zero in each iteration, the loop unrolling shows
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+ a throughput boost for large sizes (2048 bytes or higher). */
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8a984d |
+ dcbz 0,r6
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+ dcbz r9,r6
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+ dcbz r10,r6
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+ dcbz r11,r6
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8a984d |
+ addi r6,r6,512
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+ bdnz L(dcbz_loop)
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+
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8a984d |
+ andi. r5,r5,511
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8a984d |
+ beqlr
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+
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8a984d |
+ .balign 16
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8a984d |
+L(bcdz_tail):
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8a984d |
+ /* We have 1-511 bytes remaining. */
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8a984d |
+ srdi. r0,r5,7
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8a984d |
+ beq L(tail)
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+
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+ mtocrf 0x1,r0
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+
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+256: bf 30,128f
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+ dcbz 0,r6
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8a984d |
+ dcbz r9,r6
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8a984d |
+ addi r6,r6,256
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+
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+128: bf 31,L(tail)
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8a984d |
+ dcbz 0,r6
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8a984d |
+ addi r6,r6,128
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+
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8a984d |
+ b L(tail)
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+
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8a984d |
+END_GEN_TB (MEMSET,TB_TOCLESS)
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8a984d |
+libc_hidden_builtin_def (memset)
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8a984d |
+
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8a984d |
+/* Copied from bzero.S to prevent the linker from inserting a stub
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8a984d |
+ between bzero and memset. */
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8a984d |
+ENTRY_TOCLESS (__bzero)
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8a984d |
+ CALL_MCOUNT 2
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8a984d |
+ mr r5,r4
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|
|
8a984d |
+ li r4,0
|
|
|
8a984d |
+ b L(_memset)
|
|
|
8a984d |
+END (__bzero)
|
|
|
8a984d |
+#ifndef __bzero
|
|
|
8a984d |
+weak_alias (__bzero, bzero)
|
|
|
8a984d |
+#endif
|
|
|
8a984d |
diff --git a/sysdeps/powerpc/powerpc64/multiarch/Makefile b/sysdeps/powerpc/powerpc64/multiarch/Makefile
|
|
|
8a984d |
index 2e3c8f2e8a81cda4..1d517698429e1230 100644
|
|
|
8a984d |
--- a/sysdeps/powerpc/powerpc64/multiarch/Makefile
|
|
|
8a984d |
+++ b/sysdeps/powerpc/powerpc64/multiarch/Makefile
|
|
|
8a984d |
@@ -32,7 +32,7 @@ sysdep_routines += memcpy-power8-cached memcpy-power7 memcpy-a2 memcpy-power6 \
|
|
|
8a984d |
strncase-power8
|
|
|
8a984d |
|
|
|
8a984d |
ifneq (,$(filter %le,$(config-machine)))
|
|
|
8a984d |
-sysdep_routines += memcpy-power10 memmove-power10 \
|
|
|
8a984d |
+sysdep_routines += memcpy-power10 memmove-power10 memset-power10 \
|
|
|
8a984d |
strcmp-power9 strncmp-power9 strcpy-power9 stpcpy-power9 \
|
|
|
8a984d |
rawmemchr-power9 strlen-power9 strncpy-power9 stpncpy-power9 \
|
|
|
8a984d |
strlen-power10
|
|
|
8a984d |
diff --git a/sysdeps/powerpc/powerpc64/multiarch/bzero.c b/sysdeps/powerpc/powerpc64/multiarch/bzero.c
|
|
|
8a984d |
index f8cb05bea8a3505b..4ce98e324d12a31e 100644
|
|
|
8a984d |
--- a/sysdeps/powerpc/powerpc64/multiarch/bzero.c
|
|
|
8a984d |
+++ b/sysdeps/powerpc/powerpc64/multiarch/bzero.c
|
|
|
8a984d |
@@ -27,8 +27,16 @@ extern __typeof (bzero) __bzero_power4 attribute_hidden;
|
|
|
8a984d |
extern __typeof (bzero) __bzero_power6 attribute_hidden;
|
|
|
8a984d |
extern __typeof (bzero) __bzero_power7 attribute_hidden;
|
|
|
8a984d |
extern __typeof (bzero) __bzero_power8 attribute_hidden;
|
|
|
8a984d |
+# ifdef __LITTLE_ENDIAN__
|
|
|
8a984d |
+extern __typeof (bzero) __bzero_power10 attribute_hidden;
|
|
|
8a984d |
+# endif
|
|
|
8a984d |
|
|
|
8a984d |
libc_ifunc (__bzero,
|
|
|
8a984d |
+# ifdef __LITTLE_ENDIAN__
|
|
|
8a984d |
+ (hwcap2 & (PPC_FEATURE2_ARCH_3_1 | PPC_FEATURE2_HAS_ISEL)
|
|
|
8a984d |
+ && hwcap & PPC_FEATURE_HAS_VSX)
|
|
|
8a984d |
+ ? __bzero_power10 :
|
|
|
8a984d |
+# endif
|
|
|
8a984d |
(hwcap2 & PPC_FEATURE2_ARCH_2_07)
|
|
|
8a984d |
? __bzero_power8 :
|
|
|
8a984d |
(hwcap & PPC_FEATURE_HAS_VSX)
|
|
|
8a984d |
diff --git a/sysdeps/powerpc/powerpc64/multiarch/ifunc-impl-list.c b/sysdeps/powerpc/powerpc64/multiarch/ifunc-impl-list.c
|
|
|
8a984d |
index 9d5a14e480c02171..11532f77d4d03b2a 100644
|
|
|
8a984d |
--- a/sysdeps/powerpc/powerpc64/multiarch/ifunc-impl-list.c
|
|
|
8a984d |
+++ b/sysdeps/powerpc/powerpc64/multiarch/ifunc-impl-list.c
|
|
|
8a984d |
@@ -86,6 +86,13 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
|
|
|
8a984d |
|
|
|
8a984d |
/* Support sysdeps/powerpc/powerpc64/multiarch/memset.c. */
|
|
|
8a984d |
IFUNC_IMPL (i, name, memset,
|
|
|
8a984d |
+#ifdef __LITTLE_ENDIAN__
|
|
|
8a984d |
+ IFUNC_IMPL_ADD (array, i, memset,
|
|
|
8a984d |
+ hwcap2 & (PPC_FEATURE2_ARCH_3_1 |
|
|
|
8a984d |
+ PPC_FEATURE2_HAS_ISEL)
|
|
|
8a984d |
+ && hwcap & PPC_FEATURE_HAS_VSX,
|
|
|
8a984d |
+ __memset_power10)
|
|
|
8a984d |
+#endif
|
|
|
8a984d |
IFUNC_IMPL_ADD (array, i, memset, hwcap2 & PPC_FEATURE2_ARCH_2_07,
|
|
|
8a984d |
__memset_power8)
|
|
|
8a984d |
IFUNC_IMPL_ADD (array, i, memset, hwcap & PPC_FEATURE_HAS_VSX,
|
|
|
8a984d |
@@ -187,6 +194,13 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
|
|
|
8a984d |
|
|
|
8a984d |
/* Support sysdeps/powerpc/powerpc64/multiarch/bzero.c. */
|
|
|
8a984d |
IFUNC_IMPL (i, name, bzero,
|
|
|
8a984d |
+#ifdef __LITTLE_ENDIAN__
|
|
|
8a984d |
+ IFUNC_IMPL_ADD (array, i, bzero,
|
|
|
8a984d |
+ hwcap2 & (PPC_FEATURE2_ARCH_3_1 |
|
|
|
8a984d |
+ PPC_FEATURE2_HAS_ISEL)
|
|
|
8a984d |
+ && hwcap & PPC_FEATURE_HAS_VSX,
|
|
|
8a984d |
+ __bzero_power10)
|
|
|
8a984d |
+#endif
|
|
|
8a984d |
IFUNC_IMPL_ADD (array, i, bzero, hwcap2 & PPC_FEATURE2_ARCH_2_07,
|
|
|
8a984d |
__bzero_power8)
|
|
|
8a984d |
IFUNC_IMPL_ADD (array, i, bzero, hwcap & PPC_FEATURE_HAS_VSX,
|
|
|
8a984d |
diff --git a/sysdeps/powerpc/powerpc64/multiarch/memset-power10.S b/sysdeps/powerpc/powerpc64/multiarch/memset-power10.S
|
|
|
8a984d |
new file mode 100644
|
|
|
8a984d |
index 0000000000000000..548e99789735296c
|
|
|
8a984d |
--- /dev/null
|
|
|
8a984d |
+++ b/sysdeps/powerpc/powerpc64/multiarch/memset-power10.S
|
|
|
8a984d |
@@ -0,0 +1,27 @@
|
|
|
8a984d |
+/* Optimized memset implementation for POWER10 LE.
|
|
|
8a984d |
+ Copyright (C) 2021 Free Software Foundation, Inc.
|
|
|
8a984d |
+ This file is part of the GNU C Library.
|
|
|
8a984d |
+
|
|
|
8a984d |
+ The GNU C Library is free software; you can redistribute it and/or
|
|
|
8a984d |
+ modify it under the terms of the GNU Lesser General Public
|
|
|
8a984d |
+ License as published by the Free Software Foundation; either
|
|
|
8a984d |
+ version 2.1 of the License, or (at your option) any later version.
|
|
|
8a984d |
+
|
|
|
8a984d |
+ The GNU C Library is distributed in the hope that it will be useful,
|
|
|
8a984d |
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
|
8a984d |
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
|
|
8a984d |
+ Lesser General Public License for more details.
|
|
|
8a984d |
+
|
|
|
8a984d |
+ You should have received a copy of the GNU Lesser General Public
|
|
|
8a984d |
+ License along with the GNU C Library; if not, see
|
|
|
8a984d |
+ <https://www.gnu.org/licenses/>. */
|
|
|
8a984d |
+
|
|
|
8a984d |
+#define MEMSET __memset_power10
|
|
|
8a984d |
+
|
|
|
8a984d |
+#undef libc_hidden_builtin_def
|
|
|
8a984d |
+#define libc_hidden_builtin_def(name)
|
|
|
8a984d |
+
|
|
|
8a984d |
+#undef __bzero
|
|
|
8a984d |
+#define __bzero __bzero_power10
|
|
|
8a984d |
+
|
|
|
8a984d |
+#include <sysdeps/powerpc/powerpc64/le/power10/memset.S>
|
|
|
8a984d |
diff --git a/sysdeps/powerpc/powerpc64/multiarch/memset.c b/sysdeps/powerpc/powerpc64/multiarch/memset.c
|
|
|
8a984d |
index 1a7c46fecf78ab1f..4c97622c7d7eb8aa 100644
|
|
|
8a984d |
--- a/sysdeps/powerpc/powerpc64/multiarch/memset.c
|
|
|
8a984d |
+++ b/sysdeps/powerpc/powerpc64/multiarch/memset.c
|
|
|
8a984d |
@@ -33,10 +33,18 @@ extern __typeof (__redirect_memset) __memset_power4 attribute_hidden;
|
|
|
8a984d |
extern __typeof (__redirect_memset) __memset_power6 attribute_hidden;
|
|
|
8a984d |
extern __typeof (__redirect_memset) __memset_power7 attribute_hidden;
|
|
|
8a984d |
extern __typeof (__redirect_memset) __memset_power8 attribute_hidden;
|
|
|
8a984d |
+# ifdef __LITTLE_ENDIAN__
|
|
|
8a984d |
+extern __typeof (__redirect_memset) __memset_power10 attribute_hidden;
|
|
|
8a984d |
+# endif
|
|
|
8a984d |
|
|
|
8a984d |
/* Avoid DWARF definition DIE on ifunc symbol so that GDB can handle
|
|
|
8a984d |
ifunc symbol properly. */
|
|
|
8a984d |
libc_ifunc (__libc_memset,
|
|
|
8a984d |
+# ifdef __LITTLE_ENDIAN__
|
|
|
8a984d |
+ (hwcap2 & (PPC_FEATURE2_ARCH_3_1 | PPC_FEATURE2_HAS_ISEL)
|
|
|
8a984d |
+ && hwcap & PPC_FEATURE_HAS_VSX)
|
|
|
8a984d |
+ ? __memset_power10 :
|
|
|
8a984d |
+# endif
|
|
|
8a984d |
(hwcap2 & PPC_FEATURE2_ARCH_2_07)
|
|
|
8a984d |
? __memset_power8 :
|
|
|
8a984d |
(hwcap & PPC_FEATURE_HAS_VSX)
|