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commit 8813b2682e4094e43b0cf1634e99619f1b8b2c62
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Author: Sajan Karumanchi <sajan.karumanchi@amd.com>
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Date: Wed Oct 28 13:05:33 2020 +0530
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x86: Optimizing memcpy for AMD Zen architecture.
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Modifying the shareable cache '__x86_shared_cache_size', which is a
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factor in computing the non-temporal threshold parameter
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'__x86_shared_non_temporal_threshold' to optimize memcpy for AMD Zen
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architectures.
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In the existing implementation, the shareable cache is computed as 'L3
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per thread, L2 per core'. Recomputing this shareable cache as 'L3 per
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CCX(Core-Complex)' has brought in performance gains.
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As per the large bench variant results, this patch also addresses the
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regression problem on AMD Zen architectures.
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Backport of commit 59803e81f96b479c17f583b31eac44b57591a1bf upstream,
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with the fix from cb3a749a22a55645dc6a52659eea765300623f98 ("x86:
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Restore processing of cache size tunables in init_cacheinfo") applied.
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Reviewed-by: Premachandra Mallappa <premachandra.mallappa@amd.com>
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Co-Authored-by: Florian Weimer <fweimer@redhat.com>
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Backport is off the release/2.32/master branch upstream, to minimize
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conflicts. Adjusted for missing "basic" member in struct cpu_features.
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diff --git a/sysdeps/x86/cacheinfo.c b/sysdeps/x86/cacheinfo.c
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index 42b468d0c4885bad..57c36d030a76c8b2 100644
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--- a/sysdeps/x86/cacheinfo.c
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+++ b/sysdeps/x86/cacheinfo.c
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@@ -722,7 +722,7 @@ intel_bug_no_cache_info:
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threads = 1 << ((ecx >> 12) & 0x0f);
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}
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- if (threads == 0)
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+ if (threads == 0 || cpu_features->family >= 0x17)
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{
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/* If APIC ID width is not available, use logical
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processor count. */
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@@ -737,8 +737,22 @@ intel_bug_no_cache_info:
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if (threads > 0)
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shared /= threads;
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- /* Account for exclusive L2 and L3 caches. */
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- shared += core;
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+ /* Get shared cache per ccx for Zen architectures. */
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+ if (cpu_features->family >= 0x17)
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+ {
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+ unsigned int eax;
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+
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+ /* Get number of threads share the L3 cache in CCX. */
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+ __cpuid_count (0x8000001D, 0x3, eax, ebx, ecx, edx);
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+
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+ unsigned int threads_per_ccx = ((eax >> 14) & 0xfff) + 1;
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+ shared *= threads_per_ccx;
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+ }
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+ else
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+ {
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+ /* Account for exclusive L2 and L3 caches. */
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+ shared += core;
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+ }
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}
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#ifndef DISABLE_PREFETCHW
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