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commit e68b1151f7460d5fa88c3a567c13f66052da79a7
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Author: Paul A. Clarke <pc@us.ibm.com>
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Date: Thu Sep 19 11:39:44 2019 -0500
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[powerpc] __fesetround_inline optimizations
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On POWER9, use more efficient means to update the 2-bit rounding mode
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via the 'mffscrn' instruction (instead of two 'mtfsb0/1' instructions
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or one 'mtfsfi' instruction that modifies 4 bits).
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Suggested-by: Paul E. Murphy <murphyp@linux.ibm.com>
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Reviewed-By: Paul E Murphy <murphyp@linux.ibm.com>
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diff --git a/sysdeps/powerpc/fpu/fenv_libc.h b/sysdeps/powerpc/fpu/fenv_libc.h
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index 86ae7fda016abd8b..c3f541c08440b20e 100644
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--- a/sysdeps/powerpc/fpu/fenv_libc.h
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+++ b/sysdeps/powerpc/fpu/fenv_libc.h
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@@ -149,7 +149,12 @@ typedef union
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static inline int
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__fesetround_inline (int round)
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{
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- if ((unsigned int) round < 2)
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+#ifdef _ARCH_PWR9
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+ __fe_mffscrn (round);
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+#else
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+ if (__glibc_likely (GLRO(dl_hwcap2) & PPC_FEATURE2_ARCH_3_00))
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+ __fe_mffscrn (round);
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+ else if ((unsigned int) round < 2)
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{
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asm volatile ("mtfsb0 30");
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if ((unsigned int) round == 0)
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@@ -165,7 +170,7 @@ __fesetround_inline (int round)
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else
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asm volatile ("mtfsb1 31");
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}
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-
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+#endif
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return 0;
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}
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@@ -174,7 +179,14 @@ __fesetround_inline (int round)
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static inline void
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__fesetround_inline_nocheck (const int round)
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{
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- asm volatile ("mtfsfi 7,%0" : : "i" (round));
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+#ifdef _ARCH_PWR9
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+ __fe_mffscrn (round);
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+#else
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+ if (__glibc_likely (GLRO(dl_hwcap2) & PPC_FEATURE2_ARCH_3_00))
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+ __fe_mffscrn (round);
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+ else
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+ asm volatile ("mtfsfi 7,%0" : : "i" (round));
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+#endif
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}
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#define FPSCR_MASK(bit) (1 << (31 - (bit)))
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