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commit e3d85df50b083c9ba68a40f5d45b201cbec4e68b
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Author: Paul A. Clarke <pc@us.ibm.com>
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Date:   Thu Sep 19 09:13:14 2019 -0500
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    [powerpc] fenv_private.h clean up
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    fenv_private.h includes unused functions, magic macro constants, and
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    some replicated common code fragments.
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    Remove unused functions, replace magic constants with constants from
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    fenv_libc.h, and refactor replicated code.
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    Suggested-by: Paul E. Murphy <murphyp@linux.ibm.com>
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    Reviewed-By: Paul E Murphy <murphyp@linux.ibm.com>
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diff --git a/sysdeps/powerpc/fpu/fedisblxcpt.c b/sysdeps/powerpc/fpu/fedisblxcpt.c
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index 2a776c72fb5a2b70..bdf55ac62f1ffe4f 100644
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--- a/sysdeps/powerpc/fpu/fedisblxcpt.c
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+++ b/sysdeps/powerpc/fpu/fedisblxcpt.c
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@@ -43,8 +43,7 @@ fedisableexcept (int excepts)
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   if (fe.l != curr.l)
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     fesetenv_mode (fe.fenv);
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-  if (new == 0 && result != 0)
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-    (void)__fe_mask_env ();
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+  __TEST_AND_ENTER_NON_STOP (-1ULL, fe.l);
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   return result;
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 }
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diff --git a/sysdeps/powerpc/fpu/feenablxcpt.c b/sysdeps/powerpc/fpu/feenablxcpt.c
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index 6f5a828e80965bfa..78ebabed9232c0ad 100644
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--- a/sysdeps/powerpc/fpu/feenablxcpt.c
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+++ b/sysdeps/powerpc/fpu/feenablxcpt.c
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@@ -43,8 +43,7 @@ feenableexcept (int excepts)
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   if (fe.l != curr.l)
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     fesetenv_mode (fe.fenv);
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-  if (new != 0 && result == 0)
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-    (void) __fe_nomask_env_priv ();
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+  __TEST_AND_EXIT_NON_STOP (0ULL, fe.l);
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   return result;
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 }
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diff --git a/sysdeps/powerpc/fpu/feholdexcpt.c b/sysdeps/powerpc/fpu/feholdexcpt.c
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index 8ec3fbff82b22f51..9636ecaa0b600b0d 100644
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--- a/sysdeps/powerpc/fpu/feholdexcpt.c
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+++ b/sysdeps/powerpc/fpu/feholdexcpt.c
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@@ -18,7 +18,6 @@
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 #include <fenv_libc.h>
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 #include <fpu_control.h>
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-#define _FPU_MASK_ALL (_FPU_MASK_ZM | _FPU_MASK_OM | _FPU_MASK_UM | _FPU_MASK_XM | _FPU_MASK_IM)
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 int
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 __feholdexcept (fenv_t *envp)
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@@ -35,11 +34,7 @@ __feholdexcept (fenv_t *envp)
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   if (new.l == old.l)
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     return 0;
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-  /* If the old env had any enabled exceptions, then mask SIGFPE in the
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-     MSR FE0/FE1 bits.  This may allow the FPU to run faster because it
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-     always takes the default action and can not generate SIGFPE. */
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-  if ((old.l & _FPU_MASK_ALL) != 0)
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-    (void)__fe_mask_env ();
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+  __TEST_AND_ENTER_NON_STOP (old.l, 0ULL);
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   /* Put the new state in effect.  */
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   fesetenv_register (new.fenv);
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diff --git a/sysdeps/powerpc/fpu/fenv_libc.h b/sysdeps/powerpc/fpu/fenv_libc.h
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index b10b6a141ded4bfd..36b639c3939586f6 100644
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--- a/sysdeps/powerpc/fpu/fenv_libc.h
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+++ b/sysdeps/powerpc/fpu/fenv_libc.h
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@@ -27,6 +27,26 @@ extern const fenv_t *__fe_nomask_env_priv (void);
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 extern const fenv_t *__fe_mask_env (void) attribute_hidden;
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+/* If the old env had any enabled exceptions and the new env has no enabled
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+   exceptions, then mask SIGFPE in the MSR FE0/FE1 bits.  This may allow the
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+   FPU to run faster because it always takes the default action and can not
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+   generate SIGFPE.  */
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+#define __TEST_AND_ENTER_NON_STOP(old, new) \
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+  do { \
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+    if (((old) & FPSCR_ENABLES_MASK) != 0 && ((new) & FPSCR_ENABLES_MASK) == 0) \
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+      (void) __fe_mask_env (); \
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+  } while (0)
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+
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+/* If the old env has no enabled exceptions and the new env has any enabled
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+   exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits.  This will put the
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+   hardware into "precise mode" and may cause the FPU to run slower on some
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+   hardware.  */
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+#define __TEST_AND_EXIT_NON_STOP(old, new) \
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+  do { \
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+    if (((old) & FPSCR_ENABLES_MASK) == 0 && ((new) & FPSCR_ENABLES_MASK) != 0) \
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+      (void) __fe_nomask_env_priv (); \
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+  } while (0)
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+
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 /* The sticky bits in the FPSCR indicating exceptions have occurred.  */
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 #define FPSCR_STICKY_BITS ((FE_ALL_EXCEPT | FE_ALL_INVALID) & ~FE_INVALID)
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diff --git a/sysdeps/powerpc/fpu/fenv_private.h b/sysdeps/powerpc/fpu/fenv_private.h
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index 30df92c9a4700dee..c236d45db2f399a4 100644
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--- a/sysdeps/powerpc/fpu/fenv_private.h
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+++ b/sysdeps/powerpc/fpu/fenv_private.h
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@@ -23,73 +23,20 @@
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 #include <fenv_libc.h>
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 #include <fpu_control.h>
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-/* Mask for the exception enable bits.  */
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-#define _FPU_ALL_TRAPS (_FPU_MASK_ZM | _FPU_MASK_OM | _FPU_MASK_UM \
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-                      | _FPU_MASK_XM | _FPU_MASK_IM)
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-
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-/* Mask the rounding mode bits.  */
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-#define _FPU_MASK_RN 0xfffffffffffffffcLL
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-
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-/* Mask everything but the rounding modes and non-IEEE arithmetic flags.  */
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-#define _FPU_MASK_NOT_RN_NI 0xffffffff00000807LL
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-
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-/* Mask restore rounding mode and exception enabled.  */
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-#define _FPU_MASK_TRAPS_RN 0xffffffffffffff00LL
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-
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-/* Mask FP result flags, preserve fraction rounded/inexact bits.  */
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-#define _FPU_MASK_FRAC_INEX_RET_CC 0xfffffffffff80fffLL
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-
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 static __always_inline void
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-__libc_feholdbits_ppc (fenv_t *envp, unsigned long long mask,
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-	unsigned long long bits)
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+libc_feholdexcept_setround_ppc (fenv_t *envp, int r)
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 {
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   fenv_union_t old, new;
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   old.fenv = *envp = fegetenv_register ();
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-  new.l = (old.l & mask) | bits;
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-
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-  /* If the old env had any enabled exceptions, then mask SIGFPE in the
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-     MSR FE0/FE1 bits.  This may allow the FPU to run faster because it
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-     always takes the default action and can not generate SIGFPE.  */
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-  if ((old.l & _FPU_ALL_TRAPS) != 0)
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-    (void) __fe_mask_env ();
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+  __TEST_AND_ENTER_NON_STOP (old.l, 0ULL);
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+  /* Clear everything and set the rounding mode.  */
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+  new.l = r;
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   fesetenv_register (new.fenv);
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 }
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-static __always_inline void
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-libc_feholdexcept_ppc (fenv_t *envp)
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-{
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-  __libc_feholdbits_ppc (envp, _FPU_MASK_NOT_RN_NI, 0LL);
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-}
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-
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-static __always_inline void
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-libc_feholdexcept_setround_ppc (fenv_t *envp, int r)
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-{
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-  __libc_feholdbits_ppc (envp, _FPU_MASK_NOT_RN_NI & _FPU_MASK_RN, r);
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-}
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-
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-static __always_inline void
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-libc_fesetround_ppc (int r)
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-{
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-  __fesetround_inline (r);
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-}
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-
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-static __always_inline int
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-libc_fetestexcept_ppc (int e)
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-{
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-  fenv_union_t u;
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-  u.fenv = fegetenv_register ();
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-  return u.l & e;
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-}
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-
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-static __always_inline void
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-libc_feholdsetround_ppc (fenv_t *e, int r)
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-{
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-  __libc_feholdbits_ppc (e, _FPU_MASK_TRAPS_RN, r);
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-}
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-
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 static __always_inline unsigned long long
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 __libc_femergeenv_ppc (const fenv_t *envp, unsigned long long old_mask,
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 	unsigned long long new_mask)
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@@ -102,19 +49,8 @@ __libc_femergeenv_ppc (const fenv_t *envp, unsigned long long old_mask,
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   /* Merge bits while masking unwanted bits from new and old env.  */
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   new.l = (old.l & old_mask) | (new.l & new_mask);
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-  /* If the old env has no enabled exceptions and the new env has any enabled
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-     exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits.  This will put the
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-     hardware into "precise mode" and may cause the FPU to run slower on some
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-     hardware.  */
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-  if ((old.l & _FPU_ALL_TRAPS) == 0 && (new.l & _FPU_ALL_TRAPS) != 0)
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-    (void) __fe_nomask_env_priv ();
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-
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-  /* If the old env had any enabled exceptions and the new env has no enabled
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-     exceptions, then mask SIGFPE in the MSR FE0/FE1 bits.  This may allow the
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-     FPU to run faster because it always takes the default action and can not
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-     generate SIGFPE.  */
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-  if ((old.l & _FPU_ALL_TRAPS) != 0 && (new.l & _FPU_ALL_TRAPS) == 0)
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-    (void) __fe_mask_env ();
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+  __TEST_AND_EXIT_NON_STOP (old.l, new.l);
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+  __TEST_AND_ENTER_NON_STOP (old.l, new.l);
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   /* Atomically enable and raise (if appropriate) exceptions set in `new'.  */
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   fesetenv_register (new.fenv);
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@@ -139,8 +75,8 @@ libc_feresetround_ppc (fenv_t *envp)
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 static __always_inline int
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 libc_feupdateenv_test_ppc (fenv_t *envp, int ex)
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 {
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-  return __libc_femergeenv_ppc (envp, _FPU_MASK_TRAPS_RN,
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-				_FPU_MASK_FRAC_INEX_RET_CC) & ex;
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+  return __libc_femergeenv_ppc (envp, ~FPSCR_CONTROL_MASK,
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+				~FPSCR_STATUS_MASK) & ex;
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 }
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 static __always_inline void
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@@ -193,8 +129,7 @@ libc_feholdsetround_noex_ppc_ctx (struct rm_ctx *ctx, int r)
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   ctx->env = old.fenv;
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   if (__glibc_unlikely (new.l != old.l))
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     {
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-      if ((old.l & _FPU_ALL_TRAPS) != 0)
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-	(void) __fe_mask_env ();
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+      __TEST_AND_ENTER_NON_STOP (old.l, 0ULL);
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       fesetenv_register (new.fenv);
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       ctx->updated_status = true;
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     }
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diff --git a/sysdeps/powerpc/fpu/fesetenv.c b/sysdeps/powerpc/fpu/fesetenv.c
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index ac927c8f3ada40b4..4eab5045c48105e3 100644
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--- a/sysdeps/powerpc/fpu/fesetenv.c
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+++ b/sysdeps/powerpc/fpu/fesetenv.c
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@@ -28,19 +28,8 @@ __fesetenv (const fenv_t *envp)
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   new.fenv = *envp;
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   old.fenv = fegetenv_status ();
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-  /* If the old env has no enabled exceptions and the new env has any enabled
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-     exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits.  This will put the
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-     hardware into "precise mode" and may cause the FPU to run slower on some
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-     hardware.  */
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-  if ((old.l & FPSCR_ENABLES_MASK) == 0 && (new.l & FPSCR_ENABLES_MASK) != 0)
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-    (void) __fe_nomask_env_priv ();
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-
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-  /* If the old env had any enabled exceptions and the new env has no enabled
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-     exceptions, then mask SIGFPE in the MSR FE0/FE1 bits.  This may allow the
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-     FPU to run faster because it always takes the default action and can not
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-     generate SIGFPE. */
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-  if ((old.l & FPSCR_ENABLES_MASK) != 0 && (new.l & FPSCR_ENABLES_MASK) == 0)
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-    (void)__fe_mask_env ();
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+  __TEST_AND_EXIT_NON_STOP (old.l, new.l);
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+  __TEST_AND_ENTER_NON_STOP (old.l, new.l);
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   fesetenv_register (new.fenv);
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diff --git a/sysdeps/powerpc/fpu/fesetmode.c b/sysdeps/powerpc/fpu/fesetmode.c
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index 29e088d5ab1c0d93..58ba02c0a1e64c27 100644
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--- a/sysdeps/powerpc/fpu/fesetmode.c
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+++ b/sysdeps/powerpc/fpu/fesetmode.c
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@@ -33,11 +33,8 @@ fesetmode (const femode_t *modep)
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   if (old.l == new.l)
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     return 0;
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-  if ((old.l & FPSCR_ENABLES_MASK) == 0 && (new.l & FPSCR_ENABLES_MASK) != 0)
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-    (void) __fe_nomask_env_priv ();
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-
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-  if ((old.l & FPSCR_ENABLES_MASK) != 0 && (new.l & FPSCR_ENABLES_MASK) == 0)
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-    (void) __fe_mask_env ();
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+  __TEST_AND_EXIT_NON_STOP (old.l, new.l);
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+  __TEST_AND_ENTER_NON_STOP (old.l, new.l);
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   fesetenv_mode (new.fenv);
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   return 0;
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diff --git a/sysdeps/powerpc/fpu/feupdateenv.c b/sysdeps/powerpc/fpu/feupdateenv.c
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index 2dbd1c4e9ec65ed0..fdd15651e0101f9e 100644
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--- a/sysdeps/powerpc/fpu/feupdateenv.c
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+++ b/sysdeps/powerpc/fpu/feupdateenv.c
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@@ -20,8 +20,6 @@
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 #include <fenv_libc.h>
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 #include <fpu_control.h>
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-#define _FPU_MASK_ALL (_FPU_MASK_ZM | _FPU_MASK_OM | _FPU_MASK_UM | _FPU_MASK_XM | _FPU_MASK_IM)
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-
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 int
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 __feupdateenv (const fenv_t *envp)
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 {
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@@ -36,19 +34,8 @@ __feupdateenv (const fenv_t *envp)
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      unchanged.  */
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   new.l = (old.l & 0xffffffff1fffff00LL) | (new.l & 0x1ff80fff);
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-  /* If the old env has no enabled exceptions and the new env has any enabled
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-     exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits.  This will put
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-     the hardware into "precise mode" and may cause the FPU to run slower on
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-     some hardware.  */
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-  if ((old.l & _FPU_MASK_ALL) == 0 && (new.l & _FPU_MASK_ALL) != 0)
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-    (void) __fe_nomask_env_priv ();
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-
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-  /* If the old env had any enabled exceptions and the new env has no enabled
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-     exceptions, then mask SIGFPE in the MSR FE0/FE1 bits.  This may allow the
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-     FPU to run faster because it always takes the default action and can not
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-     generate SIGFPE. */
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-  if ((old.l & _FPU_MASK_ALL) != 0 && (new.l & _FPU_MASK_ALL) == 0)
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-    (void)__fe_mask_env ();
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+  __TEST_AND_EXIT_NON_STOP (old.l, new.l);
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+  __TEST_AND_ENTER_NON_STOP (old.l, new.l);
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   /* Atomically enable and raise (if appropriate) exceptions set in `new'. */
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   fesetenv_register (new.fenv);