Blame SOURCES/glibc-rh1498925-2.patch
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The memmove related fix is dropped in this patch because rhel-7.5
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does not have optimized memmove for POWER7.
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commit 63da5cd4a097d089033d980c42254c3356fa723f
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Author: Rajalakshmi Srinivasaraghavan <raji@linux.vnet.ibm.com>
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Date: Wed Oct 25 13:13:53 2017 -0200
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powerpc: Replace lxvd2x/stxvd2x with lvx/stvx in P7's memcpy/memmove
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POWER9 DD2.1 and earlier has an issue where some cache inhibited
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vector load traps to the kernel, causing a performance degradation. To
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handle this in memcpy and memmove, lvx/stvx is used for aligned
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addresses instead of lxvd2x/stxvd2x.
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Reference: https://patchwork.ozlabs.org/patch/814059/
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* sysdeps/powerpc/powerpc64/power7/memcpy.S: Replace
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lxvd2x/stxvd2x with lvx/stvx.
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* sysdeps/powerpc/powerpc64/power7/memmove.S: Likewise.
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Reviewed-by: Tulio Magno Quites Machado Filho <tuliom@linux.vnet.ibm.com>
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Reviewed-by: Adhemerval Zanella <adhemerval.zanella@linaro.org>
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diff --git a/sysdeps/powerpc/powerpc64/power7/memcpy.S b/sysdeps/powerpc/powerpc64/power7/memcpy.S
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index 1ccbc2e..a7cdf8b 100644
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--- a/sysdeps/powerpc/powerpc64/power7/memcpy.S
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+++ b/sysdeps/powerpc/powerpc64/power7/memcpy.S
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@@ -91,63 +91,63 @@ L(aligned_copy):
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srdi 12,cnt,7
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cmpdi 12,0
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beq L(aligned_tail)
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- lxvd2x 6,0,src
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- lxvd2x 7,src,6
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+ lvx 6,0,src
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+ lvx 7,src,6
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mtctr 12
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b L(aligned_128loop)
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.align 4
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L(aligned_128head):
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/* for the 2nd + iteration of this loop. */
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- lxvd2x 6,0,src
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- lxvd2x 7,src,6
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+ lvx 6,0,src
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+ lvx 7,src,6
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L(aligned_128loop):
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- lxvd2x 8,src,7
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- lxvd2x 9,src,8
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- stxvd2x 6,0,dst
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+ lvx 8,src,7
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+ lvx 9,src,8
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+ stvx 6,0,dst
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addi src,src,64
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- stxvd2x 7,dst,6
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- stxvd2x 8,dst,7
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- stxvd2x 9,dst,8
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- lxvd2x 6,0,src
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- lxvd2x 7,src,6
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+ stvx 7,dst,6
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+ stvx 8,dst,7
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+ stvx 9,dst,8
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+ lvx 6,0,src
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+ lvx 7,src,6
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addi dst,dst,64
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- lxvd2x 8,src,7
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- lxvd2x 9,src,8
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+ lvx 8,src,7
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+ lvx 9,src,8
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addi src,src,64
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- stxvd2x 6,0,dst
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- stxvd2x 7,dst,6
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- stxvd2x 8,dst,7
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- stxvd2x 9,dst,8
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+ stvx 6,0,dst
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+ stvx 7,dst,6
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+ stvx 8,dst,7
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+ stvx 9,dst,8
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addi dst,dst,64
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bdnz L(aligned_128head)
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L(aligned_tail):
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mtocrf 0x01,cnt
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bf 25,32f
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- lxvd2x 6,0,src
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- lxvd2x 7,src,6
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- lxvd2x 8,src,7
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- lxvd2x 9,src,8
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+ lvx 6,0,src
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+ lvx 7,src,6
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+ lvx 8,src,7
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+ lvx 9,src,8
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addi src,src,64
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- stxvd2x 6,0,dst
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- stxvd2x 7,dst,6
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- stxvd2x 8,dst,7
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- stxvd2x 9,dst,8
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+ stvx 6,0,dst
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+ stvx 7,dst,6
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+ stvx 8,dst,7
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+ stvx 9,dst,8
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addi dst,dst,64
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32:
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bf 26,16f
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- lxvd2x 6,0,src
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- lxvd2x 7,src,6
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+ lvx 6,0,src
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+ lvx 7,src,6
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addi src,src,32
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- stxvd2x 6,0,dst
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- stxvd2x 7,dst,6
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+ stvx 6,0,dst
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+ stvx 7,dst,6
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addi dst,dst,32
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16:
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bf 27,8f
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- lxvd2x 6,0,src
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+ lvx 6,0,src
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addi src,src,16
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- stxvd2x 6,0,dst
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+ stvx 6,0,dst
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addi dst,dst,16
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8:
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bf 28,4f
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