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commit 87868c2418fb74357757e3b739ce5b76b17a8929
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Author: Adhemerval Zanella <azanella@linux.vnet.ibm.com>
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Date: Wed Jun 25 11:54:31 2014 -0500
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PowerPC: Align power7 memcpy using VSX to quadword
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This patch changes power7 memcpy to use VSX instructions only when
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memory is aligned to quardword. It is to avoid unaligned kernel traps
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on non-cacheable memory (for instance, memory-mapped I/O).
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diff --git a/sysdeps/powerpc/powerpc32/power7/memcpy.S b/sysdeps/powerpc/powerpc32/power7/memcpy.S
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index 52c2a6b..e540fea 100644
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--- a/sysdeps/powerpc/powerpc32/power7/memcpy.S
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+++ b/sysdeps/powerpc/powerpc32/power7/memcpy.S
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@@ -38,8 +38,8 @@ EALIGN (memcpy, 5, 0)
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ble cr1, L(copy_LT_32) /* If move < 32 bytes use short move
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code. */
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- andi. 11,3,7 /* Check alignment of DST. */
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- clrlwi 10,4,29 /* Check alignment of SRC. */
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+ andi. 11,3,15 /* Check alignment of DST. */
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+ clrlwi 10,4,28 /* Check alignment of SRC. */
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cmplw cr6,10,11 /* SRC and DST alignments match? */
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mr 12,4
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mr 31,5
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diff --git a/sysdeps/powerpc/powerpc64/power7/memcpy.S b/sysdeps/powerpc/powerpc64/power7/memcpy.S
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index bbfd381..58d9b12 100644
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--- a/sysdeps/powerpc/powerpc64/power7/memcpy.S
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+++ b/sysdeps/powerpc/powerpc64/power7/memcpy.S
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@@ -36,16 +36,11 @@ EALIGN (memcpy, 5, 0)
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ble cr1, L(copy_LT_32) /* If move < 32 bytes use short move
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code. */
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-#ifdef __LITTLE_ENDIAN__
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-/* In little-endian mode, power7 takes an alignment trap on any lxvd2x
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- or stxvd2x crossing a 32-byte boundary, so ensure the aligned_copy
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- loop is only used for quadword aligned copies. */
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+/* Align copies using VSX instructions to quadword. It is to avoid alignment
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+ traps when memcpy is used on non-cacheable memory (for instance, memory
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+ mapped I/O). */
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andi. 10,3,15
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clrldi 11,4,60
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-#else
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- andi. 10,3,7 /* Check alignment of DST. */
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- clrldi 11,4,61 /* Check alignment of SRC. */
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-#endif
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cmpld cr6,10,11 /* SRC and DST alignments match? */
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mr dst,3
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@@ -53,13 +48,9 @@ EALIGN (memcpy, 5, 0)
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beq L(aligned_copy)
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mtocrf 0x01,0
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-#ifdef __LITTLE_ENDIAN__
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clrldi 0,0,60
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-#else
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- clrldi 0,0,61
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-#endif
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-/* Get the DST and SRC aligned to 8 bytes (16 for little-endian). */
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+/* Get the DST and SRC aligned to 16 bytes. */
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1:
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bf 31,2f
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lbz 6,0(src)
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@@ -79,14 +70,12 @@ EALIGN (memcpy, 5, 0)
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stw 6,0(dst)
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addi dst,dst,4
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8:
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-#ifdef __LITTLE_ENDIAN__
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bf 28,16f
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ld 6,0(src)
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addi src,src,8
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std 6,0(dst)
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addi dst,dst,8
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16:
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-#endif
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subf cnt,0,cnt
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/* Main aligned copy loop. Copies 128 bytes at a time. */
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@@ -298,9 +287,6 @@ L(copy_LE_8):
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.align 4
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L(copy_GE_32_unaligned):
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clrldi 0,0,60 /* Number of bytes until the 1st dst quadword. */
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-#ifndef __LITTLE_ENDIAN__
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- andi. 10,3,15 /* Check alignment of DST (against quadwords). */
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-#endif
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srdi 9,cnt,4 /* Number of full quadwords remaining. */
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beq L(copy_GE_32_unaligned_cont)
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