Full backports of the following patches:

commit b97eb2bdb1ed72982a7821c3078be591051cef59

Author: H.J. Lu <hjl.tools@gmail.com>

Date:   Mon Mar 16 14:58:43 2015 -0700

    Preserve bound registers in _dl_runtime_resolve

    We need to add a BND prefix before indirect branch at the end of

    _dl_runtime_resolve to preserve bound registers.

commit ddd85a65b6e3d6ec1e756c1f78559f99a2c943ca

Author: H.J. Lu <hjl.tools@gmail.com>

Date:   Tue Jul 7 05:23:24 2015 -0700

    Add and use sysdeps/i386/link-defines.sym

    Define macros for fields in La_i86_regs and La_i86_retval and use them

    in dl-trampoline.S, instead of hardcoded values.

commit 14c5cbabc2d11004ab223ae5eae761ddf83ef99e

Author: Igor Zamyatin <igor.zamyatin@intel.com>

Date:   Thu Jul 9 06:50:12 2015 -0700

    Preserve bound registers for pointer pass/return

    We need to save/restore bound registers and add a BND prefix before

    branches in _dl_runtime_profile so that bound registers for pointer

    pass and return are preserved when LD_AUDIT is used.

commit f3dcae82d54e5097e18e1d6ef4ff55c2ea4e621e

Author: H.J. Lu <hjl.tools@gmail.com>

Date:   Tue Aug 25 04:33:54 2015 -0700

    Save and restore vector registers in x86-64 ld.so

    This patch adds SSE, AVX and AVX512 versions of _dl_runtime_resolve

    and _dl_runtime_profile, which save and restore the first 8 vector

    registers used for parameter passing.  elf_machine_runtime_setup

    selects the proper _dl_runtime_resolve or _dl_runtime_profile based

    on _dl_x86_cpu_features.  It avoids race condition caused by

    FOREIGN_CALL macros, which are only used for x86-64.

    Performance impact of saving and restoring 8 vector registers are

    negligible on Nehalem, Sandy Bridge, Ivy Bridge and Haswell when

    ld.so is optimized with SSE2.

commit fb0f7a6755c1bfaec38f490fbfcaa39a66ee3604

Author: H.J. Lu <hjl.tools@gmail.com>

Date:   Tue Sep 6 08:50:55 2016 -0700

    X86-64: Add _dl_runtime_resolve_avx[512]_{opt|slow} [BZ #20508]

    There is transition penalty when SSE instructions are mixed with 256-bit

    AVX or 512-bit AVX512 load instructions.  Since _dl_runtime_resolve_avx

    and _dl_runtime_profile_avx512 save/restore 256-bit YMM/512-bit ZMM

    registers, there is transition penalty when SSE instructions are used

    with lazy binding on AVX and AVX512 processors.

    To avoid SSE transition penalty, if only the lower 128 bits of the first

    8 vector registers are non-zero, we can preserve %xmm0 - %xmm7 registers

    with the zero upper bits.

    For AVX and AVX512 processors which support XGETBV with ECX == 1, we can

    use XGETBV with ECX == 1 to check if the upper 128 bits of YMM registers

    or the upper 256 bits of ZMM registers are zero.  We can restore only the

    non-zero portion of vector registers with AVX/AVX512 load instructions

    which will zero-extend upper bits of vector registers.

    This patch adds _dl_runtime_resolve_sse_vex which saves and restores

    XMM registers with 128-bit AVX store/load instructions.  It is used to

    preserve YMM/ZMM registers when only the lower 128 bits are non-zero.

    _dl_runtime_resolve_avx_opt and _dl_runtime_resolve_avx512_opt are added

    and used on AVX/AVX512 processors supporting XGETBV with ECX == 1 so

    that we store and load only the non-zero portion of vector registers.

    This avoids SSE transition penalty caused by _dl_runtime_resolve_avx and

    _dl_runtime_profile_avx512 when only the lower 128 bits of vector

    registers are used.

    _dl_runtime_resolve_avx_slow is added and used for AVX processors which

    don't support XGETBV with ECX == 1.  Since there is no SSE transition

    penalty on AVX512 processors which don't support XGETBV with ECX == 1,

    _dl_runtime_resolve_avx512_slow isn't provided.

commit 3403a17fea8ccef7dc5f99553a13231acf838744

Author: H.J. Lu <hjl.tools@gmail.com>

Date:   Thu Feb 9 12:19:44 2017 -0800

    x86-64: Verify that _dl_runtime_resolve preserves vector registers

    On x86-64, _dl_runtime_resolve must preserve the first 8 vector

    registers.  Add 3 _dl_runtime_resolve tests to verify that SSE,

    AVX and AVX512 registers are preserved.

commit c15f8eb50cea7ad1a4ccece6e0982bf426d52c00

Author: H.J. Lu <hjl.tools@gmail.com>

Date:   Tue Mar 21 10:59:31 2017 -0700

    x86-64: Improve branch predication in _dl_runtime_resolve_avx512_opt [BZ #21258]

    On Skylake server, _dl_runtime_resolve_avx512_opt is used to preserve

    the first 8 vector registers.  The code layout is

      if only %xmm0 - %xmm7 registers are used

         preserve %xmm0 - %xmm7 registers

      if only %ymm0 - %ymm7 registers are used

         preserve %ymm0 - %ymm7 registers

      preserve %zmm0 - %zmm7 registers

    Branch predication always executes the fallthrough code path to preserve

    %zmm0 - %zmm7 registers speculatively, even though only %xmm0 - %xmm7

    registers are used.  This leads to lower CPU frequency on Skylake

    server.  This patch changes the fallthrough code path to preserve

    %xmm0 - %xmm7 registers instead:

      if whole %zmm0 - %zmm7 registers are used

        preserve %zmm0 - %zmm7 registers

      if only %ymm0 - %ymm7 registers are used

         preserve %ymm0 - %ymm7 registers

      preserve %xmm0 - %xmm7 registers

    Tested on Skylake server.

            [BZ #21258]

            * sysdeps/x86_64/dl-trampoline.S (_dl_runtime_resolve_opt):

            Define only if _dl_runtime_resolve is defined to

            _dl_runtime_resolve_sse_vex.

            * sysdeps/x86_64/dl-trampoline.h (_dl_runtime_resolve_opt):

            Fallthrough to _dl_runtime_resolve_sse_vex.

Index: glibc-2.17-c758a686/nptl/sysdeps/x86_64/tcb-offsets.sym

===================================================================

--- glibc-2.17-c758a686.orig/nptl/sysdeps/x86_64/tcb-offsets.sym

+++ glibc-2.17-c758a686/nptl/sysdeps/x86_64/tcb-offsets.sym

@@ -15,7 +15,6 @@ VGETCPU_CACHE_OFFSET	offsetof (tcbhead_t

 #ifndef __ASSUME_PRIVATE_FUTEX

 PRIVATE_FUTEX		offsetof (tcbhead_t, private_futex)

 #endif

-RTLD_SAVESPACE_SSE	offsetof (tcbhead_t, rtld_savespace_sse)

 -- Not strictly offsets, but these values are also used in the TCB.

 TCB_CANCELSTATE_BITMASK	 CANCELSTATE_BITMASK

Index: glibc-2.17-c758a686/nptl/sysdeps/x86_64/tls.h

===================================================================

--- glibc-2.17-c758a686.orig/nptl/sysdeps/x86_64/tls.h

+++ glibc-2.17-c758a686/nptl/sysdeps/x86_64/tls.h

@@ -67,12 +67,13 @@ typedef struct

 # else

   int __unused1;

 # endif

-  int rtld_must_xmm_save;

+  int __glibc_unused1;

   /* Reservation of some values for the TM ABI.  */

   void *__private_tm[5];

   long int __unused2;

-  /* Have space for the post-AVX register size.  */

-  __128bits rtld_savespace_sse[8][4] __attribute__ ((aligned (32)));

+  /* Must be kept even if it is no longer used by glibc since programs,

+     like AddressSanitizer, depend on the size of tcbhead_t.  */

+  __128bits __glibc_unused2[8][4] __attribute__ ((aligned (32)));

   void *__padding[8];

 } tcbhead_t;

@@ -380,41 +381,6 @@ typedef struct

 # define THREAD_GSCOPE_WAIT() \

   GL(dl_wait_lookup_done) ()

-

-# ifdef SHARED

-/* Defined in dl-trampoline.S.  */

-extern void _dl_x86_64_save_sse (void);

-extern void _dl_x86_64_restore_sse (void);

-

-# define RTLD_CHECK_FOREIGN_CALL \

-  (THREAD_GETMEM (THREAD_SELF, header.rtld_must_xmm_save) != 0)

-

-/* NB: Don't use the xchg operation because that would imply a lock

-   prefix which is expensive and unnecessary.  The cache line is also

-   not contested at all.  */

-#  define RTLD_ENABLE_FOREIGN_CALL \

-  int old_rtld_must_xmm_save = THREAD_GETMEM (THREAD_SELF,		      \

-					      header.rtld_must_xmm_save);     \

-  THREAD_SETMEM (THREAD_SELF, header.rtld_must_xmm_save, 1)

-

-#  define RTLD_PREPARE_FOREIGN_CALL \

-  do if (THREAD_GETMEM (THREAD_SELF, header.rtld_must_xmm_save))	      \

-    {									      \

-      _dl_x86_64_save_sse ();						      \

-      THREAD_SETMEM (THREAD_SELF, header.rtld_must_xmm_save, 0);	      \

-    }									      \

-  while (0)

-

-#  define RTLD_FINALIZE_FOREIGN_CALL \

-  do {									      \

-    if (THREAD_GETMEM (THREAD_SELF, header.rtld_must_xmm_save) == 0)	      \

-      _dl_x86_64_restore_sse ();					      \

-    THREAD_SETMEM (THREAD_SELF, header.rtld_must_xmm_save,		      \

-		   old_rtld_must_xmm_save);				      \

-  } while (0)

-# endif

-

-

 #endif /* __ASSEMBLER__ */

 #endif	/* tls.h */

Index: glibc-2.17-c758a686/sysdeps/i386/Makefile

===================================================================

--- glibc-2.17-c758a686.orig/sysdeps/i386/Makefile

+++ glibc-2.17-c758a686/sysdeps/i386/Makefile

@@ -33,6 +33,7 @@ sysdep-CFLAGS += -mpreferred-stack-bound

 else

 ifeq ($(subdir),csu)

 sysdep-CFLAGS += -mpreferred-stack-boundary=4

+gen-as-const-headers += link-defines.sym

 else

 # Likewise, any function which calls user callbacks

 uses-callbacks += -mpreferred-stack-boundary=4

Index: glibc-2.17-c758a686/sysdeps/i386/configure

===================================================================

--- glibc-2.17-c758a686.orig/sysdeps/i386/configure

+++ glibc-2.17-c758a686/sysdeps/i386/configure

@@ -179,5 +179,32 @@ fi

 { $as_echo "$as_me:${as_lineno-$LINENO}: result: $libc_cv_cc_novzeroupper" >&5

 $as_echo "$libc_cv_cc_novzeroupper" >&6; }

+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for Intel MPX support" >&5

+$as_echo_n "checking for Intel MPX support... " >&6; }

+if ${libc_cv_asm_mpx+:} false; then :

+  $as_echo_n "(cached) " >&6

+else

+  cat > conftest.s <<\EOF

+        bndmov %bnd0,(%esp)

+EOF

+if { ac_try='${CC-cc} -c $ASFLAGS conftest.s 1>&5'

+  { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5

+  (eval $ac_try) 2>&5

+  ac_status=$?

+  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5

+  test $ac_status = 0; }; }; then

+  libc_cv_asm_mpx=yes

+else

+  libc_cv_asm_mpx=no

+fi

+rm -f conftest*

+fi

+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $libc_cv_asm_mpx" >&5

+$as_echo "$libc_cv_asm_mpx" >&6; }

+if test $libc_cv_asm_mpx == yes; then

+  $as_echo "#define HAVE_MPX_SUPPORT 1" >>confdefs.h

+

+fi

+

 $as_echo "#define PI_STATIC_AND_HIDDEN 1" >>confdefs.h

Index: glibc-2.17-c758a686/sysdeps/i386/configure.in

===================================================================

--- glibc-2.17-c758a686.orig/sysdeps/i386/configure.in

+++ glibc-2.17-c758a686/sysdeps/i386/configure.in

@@ -53,6 +53,21 @@ LIBC_TRY_CC_OPTION([-mno-vzeroupper],

 		   [libc_cv_cc_novzeroupper=no])

 ])

+dnl Check whether asm supports Intel MPX

+AC_CACHE_CHECK(for Intel MPX support, libc_cv_asm_mpx, [dnl

+cat > conftest.s <<\EOF

+        bndmov %bnd0,(%esp)

+EOF

+if AC_TRY_COMMAND(${CC-cc} -c $ASFLAGS conftest.s 1>&AS_MESSAGE_LOG_FD); then

+  libc_cv_asm_mpx=yes

+else

+  libc_cv_asm_mpx=no

+fi

+rm -f conftest*])

+if test $libc_cv_asm_mpx == yes; then

+  AC_DEFINE(HAVE_MPX_SUPPORT)

+fi

+

 dnl It is always possible to access static and hidden symbols in an

 dnl position independent way.

 AC_DEFINE(PI_STATIC_AND_HIDDEN)

Index: glibc-2.17-c758a686/sysdeps/i386/dl-trampoline.S

===================================================================

--- glibc-2.17-c758a686.orig/sysdeps/i386/dl-trampoline.S

+++ glibc-2.17-c758a686/sysdeps/i386/dl-trampoline.S

@@ -17,6 +17,13 @@

    <http://www.gnu.org/licenses/>.  */

 #include <sysdep.h>

+#include <link-defines.h>

+

+#ifdef HAVE_MPX_SUPPORT

+# define PRESERVE_BND_REGS_PREFIX bnd

+#else

+# define PRESERVE_BND_REGS_PREFIX .byte 0xf2

+#endif

 	.text

 	.globl _dl_runtime_resolve

@@ -161,24 +168,47 @@ _dl_runtime_profile:

 	    +4      free

 	   %esp     free

 	*/

-	subl $20, %esp

-	cfi_adjust_cfa_offset (20)

-	movl %eax, (%esp)

-	movl %edx, 4(%esp)

-	fstpt 8(%esp)

-	fstpt 20(%esp)

+#if LONG_DOUBLE_SIZE != 12

+# error "long double size must be 12 bytes"

+#endif

+	# Allocate space for La_i86_retval and subtract 12 free bytes.

+	subl $(LRV_SIZE - 12), %esp

+	cfi_adjust_cfa_offset (LRV_SIZE - 12)

+	movl %eax, LRV_EAX_OFFSET(%esp)

+	movl %edx, LRV_EDX_OFFSET(%esp)

+	fstpt LRV_ST0_OFFSET(%esp)

+	fstpt LRV_ST1_OFFSET(%esp)

+#ifdef HAVE_MPX_SUPPORT

+	bndmov %bnd0, LRV_BND0_OFFSET(%esp)

+	bndmov %bnd1, LRV_BND1_OFFSET(%esp)

+#else

+	.byte 0x66,0x0f,0x1b,0x44,0x24,LRV_BND0_OFFSET

+	.byte 0x66,0x0f,0x1b,0x4c,0x24,LRV_BND1_OFFSET

+#endif

 	pushl %esp

 	cfi_adjust_cfa_offset (4)

-	leal 36(%esp), %ecx

-	movl 56(%esp), %eax

-	movl 60(%esp), %edx

+	# Address of La_i86_regs area.

+	leal (LRV_SIZE + 4)(%esp), %ecx

+	# PLT2

+	movl (LRV_SIZE + 4 + LR_SIZE)(%esp), %eax

+	# PLT1

+	movl (LRV_SIZE + 4 + LR_SIZE + 4)(%esp), %edx

 	call _dl_call_pltexit

-	movl (%esp), %eax

-	movl 4(%esp), %edx

-	fldt 20(%esp)

-	fldt 8(%esp)

-	addl $60, %esp

-	cfi_adjust_cfa_offset (-60)

+	movl LRV_EAX_OFFSET(%esp), %eax

+	movl LRV_EDX_OFFSET(%esp), %edx

+	fldt LRV_ST1_OFFSET(%esp)

+	fldt LRV_ST0_OFFSET(%esp)

+#ifdef HAVE_MPX_SUPPORT

+	bndmov LRV_BND0_OFFSET(%esp), %bnd0

+	bndmov LRV_BND1_OFFSET(%esp), %bnd1

+#else

+	.byte 0x66,0x0f,0x1a,0x44,0x24,LRV_BND0_OFFSET

+	.byte 0x66,0x0f,0x1a,0x4c,0x24,LRV_BND1_OFFSET

+#endif

+	# Restore stack before return.

+	addl $(LRV_SIZE + 4 + LR_SIZE + 4), %esp

+	cfi_adjust_cfa_offset (-(LRV_SIZE + 4 + LR_SIZE + 4))

+	PRESERVE_BND_REGS_PREFIX

 	ret

 	cfi_endproc

 	.size _dl_runtime_profile, .-_dl_runtime_profile

Index: glibc-2.17-c758a686/sysdeps/i386/link-defines.sym

===================================================================

--- /dev/null

+++ glibc-2.17-c758a686/sysdeps/i386/link-defines.sym

@@ -0,0 +1,20 @@

+#include "link.h"

+#include <stddef.h>

+

+--

+LONG_DOUBLE_SIZE	sizeof (long double)

+

+LR_SIZE			sizeof (struct La_i86_regs)

+LR_EDX_OFFSET		offsetof (struct La_i86_regs, lr_edx)

+LR_ECX_OFFSET		offsetof (struct La_i86_regs, lr_ecx)

+LR_EAX_OFFSET		offsetof (struct La_i86_regs, lr_eax)

+LR_EBP_OFFSET		offsetof (struct La_i86_regs, lr_ebp)

+LR_ESP_OFFSET		offsetof (struct La_i86_regs, lr_esp)

+

+LRV_SIZE		sizeof (struct La_i86_retval)

+LRV_EAX_OFFSET		offsetof (struct La_i86_retval, lrv_eax)

+LRV_EDX_OFFSET		offsetof (struct La_i86_retval, lrv_edx)

+LRV_ST0_OFFSET		offsetof (struct La_i86_retval, lrv_st0)

+LRV_ST1_OFFSET		offsetof (struct La_i86_retval, lrv_st1)

+LRV_BND0_OFFSET		offsetof (struct La_i86_retval, lrv_bnd0)

+LRV_BND1_OFFSET		offsetof (struct La_i86_retval, lrv_bnd1)

Index: glibc-2.17-c758a686/sysdeps/x86/bits/link.h

===================================================================

--- glibc-2.17-c758a686.orig/sysdeps/x86/bits/link.h

+++ glibc-2.17-c758a686/sysdeps/x86/bits/link.h

@@ -38,6 +38,8 @@ typedef struct La_i86_retval

   uint32_t lrv_edx;

   long double lrv_st0;

   long double lrv_st1;

+  uint64_t lrv_bnd0;

+  uint64_t lrv_bnd1;

 } La_i86_retval;

Index: glibc-2.17-c758a686/sysdeps/x86/cpu-features.c

===================================================================

--- glibc-2.17-c758a686.orig/sysdeps/x86/cpu-features.c

+++ glibc-2.17-c758a686/sysdeps/x86/cpu-features.c

@@ -130,6 +130,20 @@ init_cpu_features (struct cpu_features *

 	      break;

 	    }

 	}

+

+      /* To avoid SSE transition penalty, use _dl_runtime_resolve_slow.

+         If XGETBV suports ECX == 1, use _dl_runtime_resolve_opt.  */

+      cpu_features->feature[index_Use_dl_runtime_resolve_slow]

+	|= bit_Use_dl_runtime_resolve_slow;

+      if (cpu_features->max_cpuid >= 0xd)

+	{

+	  unsigned int eax;

+

+	  __cpuid_count (0xd, 1, eax, ebx, ecx, edx);

+	  if ((eax & (1 << 2)) != 0)

+	    cpu_features->feature[index_Use_dl_runtime_resolve_opt]

+	      |= bit_Use_dl_runtime_resolve_opt;

+	}

     }

   /* This spells out "AuthenticAMD".  */

   else if (ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65)

Index: glibc-2.17-c758a686/sysdeps/x86/cpu-features.h

===================================================================

--- glibc-2.17-c758a686.orig/sysdeps/x86/cpu-features.h

+++ glibc-2.17-c758a686/sysdeps/x86/cpu-features.h

@@ -34,6 +34,9 @@

 #define bit_AVX512DQ_Usable		(1 << 13)

 #define bit_Prefer_MAP_32BIT_EXEC	(1 << 16)

 #define bit_Prefer_No_VZEROUPPER	(1 << 17)

+#define bit_Use_dl_runtime_resolve_opt	(1 << 20)

+#define bit_Use_dl_runtime_resolve_slow	(1 << 21)

+

 /* CPUID Feature flags.  */

@@ -95,6 +98,9 @@

 # define index_AVX512DQ_Usable		FEATURE_INDEX_1*FEATURE_SIZE

 # define index_Prefer_MAP_32BIT_EXEC	FEATURE_INDEX_1*FEATURE_SIZE

 # define index_Prefer_No_VZEROUPPER	FEATURE_INDEX_1*FEATURE_SIZE

+# define index_Use_dl_runtime_resolve_opt FEATURE_INDEX_1*FEATURE_SIZE

+# define index_Use_dl_runtime_resolve_slow FEATURE_INDEX_1*FEATURE_SIZE

+

 # if defined (_LIBC) && !IS_IN (nonlib)

 #  ifdef __x86_64__

@@ -273,6 +279,8 @@ extern const struct cpu_features *__get_

 # define index_AVX512DQ_Usable		FEATURE_INDEX_1

 # define index_Prefer_MAP_32BIT_EXEC	FEATURE_INDEX_1

 # define index_Prefer_No_VZEROUPPER     FEATURE_INDEX_1

+# define index_Use_dl_runtime_resolve_opt FEATURE_INDEX_1

+# define index_Use_dl_runtime_resolve_slow FEATURE_INDEX_1

 #endif	/* !__ASSEMBLER__ */

Index: glibc-2.17-c758a686/sysdeps/x86_64/Makefile

===================================================================

--- glibc-2.17-c758a686.orig/sysdeps/x86_64/Makefile

+++ glibc-2.17-c758a686/sysdeps/x86_64/Makefile

@@ -21,6 +21,11 @@ endif

 ifeq ($(subdir),elf)

 sysdep-dl-routines += tlsdesc dl-tlsdesc

+tests += ifuncmain8

+modules-names += ifuncmod8

+

+$(objpfx)ifuncmain8: $(objpfx)ifuncmod8.so

+

 tests += tst-quad1 tst-quad2

 modules-names += tst-quadmod1 tst-quadmod2

@@ -34,18 +39,32 @@ tests-pie += $(quad-pie-test)

 $(objpfx)tst-quad1pie: $(objpfx)tst-quadmod1pie.o

 $(objpfx)tst-quad2pie: $(objpfx)tst-quadmod2pie.o

+tests += tst-sse tst-avx tst-avx512

+test-extras += tst-avx-aux tst-avx512-aux

+extra-test-objs += tst-avx-aux.o tst-avx512-aux.o

+

 tests += tst-audit10

-modules-names += tst-auditmod10a tst-auditmod10b

+modules-names += tst-auditmod10a tst-auditmod10b \

+		 tst-ssemod tst-avxmod tst-avx512mod

 $(objpfx)tst-audit10: $(objpfx)tst-auditmod10a.so

 $(objpfx)tst-audit10.out: $(objpfx)tst-auditmod10b.so

 tst-audit10-ENV = LD_AUDIT=$(objpfx)tst-auditmod10b.so

+$(objpfx)tst-sse: $(objpfx)tst-ssemod.so

+$(objpfx)tst-avx: $(objpfx)tst-avx-aux.o $(objpfx)tst-avxmod.so

+$(objpfx)tst-avx512: $(objpfx)tst-avx512-aux.o $(objpfx)tst-avx512mod.so

+

+CFLAGS-tst-avx-aux.c += $(AVX-CFLAGS)

+CFLAGS-tst-avxmod.c += $(AVX-CFLAGS)

+

 ifeq (yes,$(config-cflags-avx512))

 AVX512-CFLAGS = -mavx512f

 CFLAGS-tst-audit10.c += $(AVX512-CFLAGS)

 CFLAGS-tst-auditmod10a.c += $(AVX512-CFLAGS)

 CFLAGS-tst-auditmod10b.c += $(AVX512-CFLAGS)

+CFLAGS-tst-avx512-aux.c += $(AVX512-CFLAGS)

+CFLAGS-tst-avx512mod.c += $(AVX512-CFLAGS)

 endif

 endif

Index: glibc-2.17-c758a686/sysdeps/x86_64/dl-machine.h

===================================================================

--- glibc-2.17-c758a686.orig/sysdeps/x86_64/dl-machine.h

+++ glibc-2.17-c758a686/sysdeps/x86_64/dl-machine.h

@@ -66,8 +66,15 @@ static inline int __attribute__ ((unused

 elf_machine_runtime_setup (struct link_map *l, int lazy, int profile)

 {

   Elf64_Addr *got;

-  extern void _dl_runtime_resolve (ElfW(Word)) attribute_hidden;

-  extern void _dl_runtime_profile (ElfW(Word)) attribute_hidden;

+  extern void _dl_runtime_resolve_sse (ElfW(Word)) attribute_hidden;

+  extern void _dl_runtime_resolve_avx (ElfW(Word)) attribute_hidden;

+  extern void _dl_runtime_resolve_avx_slow (ElfW(Word)) attribute_hidden;

+  extern void _dl_runtime_resolve_avx_opt (ElfW(Word)) attribute_hidden;

+  extern void _dl_runtime_resolve_avx512 (ElfW(Word)) attribute_hidden;

+  extern void _dl_runtime_resolve_avx512_opt (ElfW(Word)) attribute_hidden;

+  extern void _dl_runtime_profile_sse (ElfW(Word)) attribute_hidden;

+  extern void _dl_runtime_profile_avx (ElfW(Word)) attribute_hidden;

+  extern void _dl_runtime_profile_avx512 (ElfW(Word)) attribute_hidden;

   if (l->l_info[DT_JMPREL] && lazy)

     {

@@ -95,7 +102,12 @@ elf_machine_runtime_setup (struct link_m

 	 end in this function.  */

       if (__builtin_expect (profile, 0))

 	{

-	  *(ElfW(Addr) *) (got + 2) = (ElfW(Addr)) &_dl_runtime_profile;

+	  if (HAS_ARCH_FEATURE (AVX512F_Usable))

+	    *(ElfW(Addr) *) (got + 2) = (ElfW(Addr)) &_dl_runtime_profile_avx512;

+	  else if (HAS_ARCH_FEATURE (AVX_Usable))

+	    *(ElfW(Addr) *) (got + 2) = (ElfW(Addr)) &_dl_runtime_profile_avx;

+	  else

+	    *(ElfW(Addr) *) (got + 2) = (ElfW(Addr)) &_dl_runtime_profile_sse;

 	  if (GLRO(dl_profile) != NULL

 	      && _dl_name_match_p (GLRO(dl_profile), l))

@@ -104,9 +116,34 @@ elf_machine_runtime_setup (struct link_m

 	    GL(dl_profile_map) = l;

 	}

       else

-	/* This function will get called to fix up the GOT entry indicated by

-	   the offset on the stack, and then jump to the resolved address.  */

-	*(ElfW(Addr) *) (got + 2) = (ElfW(Addr)) &_dl_runtime_resolve;

+	{

+	  /* This function will get called to fix up the GOT entry

+	     indicated by the offset on the stack, and then jump to

+	     the resolved address.  */

+	  if (HAS_ARCH_FEATURE (AVX512F_Usable))

+	    {

+	      if (HAS_ARCH_FEATURE (Use_dl_runtime_resolve_opt))

+		*(ElfW(Addr) *) (got + 2)

+		  = (ElfW(Addr)) &_dl_runtime_resolve_avx512_opt;

+	      else

+		*(ElfW(Addr) *) (got + 2)

+		  = (ElfW(Addr)) &_dl_runtime_resolve_avx512;

+	    }

+	  else if (HAS_ARCH_FEATURE (AVX_Usable))

+	    {

+	      if (HAS_ARCH_FEATURE (Use_dl_runtime_resolve_opt))

+		*(ElfW(Addr) *) (got + 2)

+		  = (ElfW(Addr)) &_dl_runtime_resolve_avx_opt;

+	      else if (HAS_ARCH_FEATURE (Use_dl_runtime_resolve_slow))

+		*(ElfW(Addr) *) (got + 2)

+		  = (ElfW(Addr)) &_dl_runtime_resolve_avx_slow;

+	      else

+		*(ElfW(Addr) *) (got + 2)

+		  = (ElfW(Addr)) &_dl_runtime_resolve_avx;

+	    }

+	  else

+	    *(ElfW(Addr) *) (got + 2) = (ElfW(Addr)) &_dl_runtime_resolve_sse;

+	}

     }

   if (l->l_info[ADDRIDX (DT_TLSDESC_GOT)] && lazy)

Index: glibc-2.17-c758a686/sysdeps/x86_64/dl-trampoline.S

===================================================================

--- glibc-2.17-c758a686.orig/sysdeps/x86_64/dl-trampoline.S

+++ glibc-2.17-c758a686/sysdeps/x86_64/dl-trampoline.S

@@ -18,28 +18,52 @@

 #include <config.h>

 #include <sysdep.h>

+#include <cpu-features.h>

 #include <link-defines.h>

-#if (RTLD_SAVESPACE_SSE % 32) != 0

-# error RTLD_SAVESPACE_SSE must be aligned to 32 bytes

+#ifndef DL_STACK_ALIGNMENT

+/* Due to GCC bug:

+

+   https://gcc.gnu.org/bugzilla/show_bug.cgi?id=58066

+

+   __tls_get_addr may be called with 8-byte stack alignment.  Although

+   this bug has been fixed in GCC 4.9.4, 5.3 and 6, we can't assume

+   that stack will be always aligned at 16 bytes.  We use unaligned

+   16-byte move to load and store SSE registers, which has no penalty

+   on modern processors if stack is 16-byte aligned.  */

+# define DL_STACK_ALIGNMENT 8

 #endif

+#ifndef DL_RUNIME_UNALIGNED_VEC_SIZE

+/* The maximum size of unaligned vector load and store.  */

+# define DL_RUNIME_UNALIGNED_VEC_SIZE 16

+#endif

+

+/* True if _dl_runtime_resolve should align stack to VEC_SIZE bytes.  */

+#define DL_RUNIME_RESOLVE_REALIGN_STACK \

+  (VEC_SIZE > DL_STACK_ALIGNMENT \

+   && VEC_SIZE > DL_RUNIME_UNALIGNED_VEC_SIZE)

+

+/* Align vector register save area to 16 bytes.  */

+#define REGISTER_SAVE_VEC_OFF	0

+

 /* Area on stack to save and restore registers used for parameter

    passing when calling _dl_fixup.  */

 #ifdef __ILP32__

-/* X32 saves RCX, RDX, RSI, RDI, R8 and R9 plus RAX.  */

-# define REGISTER_SAVE_AREA	(8 * 7)

-# define REGISTER_SAVE_RAX	0

+# define REGISTER_SAVE_RAX	(REGISTER_SAVE_VEC_OFF + VEC_SIZE * 8)

+# define PRESERVE_BND_REGS_PREFIX

 #else

-/* X86-64 saves RCX, RDX, RSI, RDI, R8 and R9 plus RAX as well as BND0,

-   BND1, BND2, BND3.  */

-# define REGISTER_SAVE_AREA	(8 * 7 + 16 * 4)

 /* Align bound register save area to 16 bytes.  */

-# define REGISTER_SAVE_BND0	0

+# define REGISTER_SAVE_BND0	(REGISTER_SAVE_VEC_OFF + VEC_SIZE * 8)

 # define REGISTER_SAVE_BND1	(REGISTER_SAVE_BND0 + 16)

 # define REGISTER_SAVE_BND2	(REGISTER_SAVE_BND1 + 16)

 # define REGISTER_SAVE_BND3	(REGISTER_SAVE_BND2 + 16)

 # define REGISTER_SAVE_RAX	(REGISTER_SAVE_BND3 + 16)

+# ifdef HAVE_MPX_SUPPORT

+#  define PRESERVE_BND_REGS_PREFIX bnd

+# else

+#  define PRESERVE_BND_REGS_PREFIX .byte 0xf2

+# endif

 #endif

 #define REGISTER_SAVE_RCX	(REGISTER_SAVE_RAX + 8)

 #define REGISTER_SAVE_RDX	(REGISTER_SAVE_RCX + 8)

@@ -48,376 +72,71 @@

 #define REGISTER_SAVE_R8	(REGISTER_SAVE_RDI + 8)

 #define REGISTER_SAVE_R9	(REGISTER_SAVE_R8 + 8)

-	.text

-	.globl _dl_runtime_resolve

-	.type _dl_runtime_resolve, @function

-	.align 16

-	cfi_startproc

-_dl_runtime_resolve:

-	cfi_adjust_cfa_offset(16) # Incorporate PLT

-	subq $REGISTER_SAVE_AREA,%rsp

-	cfi_adjust_cfa_offset(REGISTER_SAVE_AREA)

-	# Preserve registers otherwise clobbered.

-	movq %rax, REGISTER_SAVE_RAX(%rsp)

-	movq %rcx, REGISTER_SAVE_RCX(%rsp)

-	movq %rdx, REGISTER_SAVE_RDX(%rsp)

-	movq %rsi, REGISTER_SAVE_RSI(%rsp)

-	movq %rdi, REGISTER_SAVE_RDI(%rsp)

-	movq %r8, REGISTER_SAVE_R8(%rsp)

-	movq %r9, REGISTER_SAVE_R9(%rsp)

-#ifndef __ILP32__

-	# We also have to preserve bound registers.  These are nops if

-	# Intel MPX isn't available or disabled.

-# ifdef HAVE_MPX_SUPPORT

-	bndmov %bnd0, REGISTER_SAVE_BND0(%rsp)

-	bndmov %bnd1, REGISTER_SAVE_BND1(%rsp)

-	bndmov %bnd2, REGISTER_SAVE_BND2(%rsp)

-	bndmov %bnd3, REGISTER_SAVE_BND3(%rsp)

-# else

-	.byte 0x66,0x0f,0x1b,0x44,0x24,REGISTER_SAVE_BND0

-	.byte 0x66,0x0f,0x1b,0x4c,0x24,REGISTER_SAVE_BND1

-	.byte 0x66,0x0f,0x1b,0x54,0x24,REGISTER_SAVE_BND2

-	.byte 0x66,0x0f,0x1b,0x5c,0x24,REGISTER_SAVE_BND3

-# endif

-#endif

-	# Copy args pushed by PLT in register.

-	# %rdi: link_map, %rsi: reloc_index

-	movq (REGISTER_SAVE_AREA + 8)(%rsp), %rsi

-	movq REGISTER_SAVE_AREA(%rsp), %rdi

-	call _dl_fixup		# Call resolver.

-	movq %rax, %r11		# Save return value

-#ifndef __ILP32__

-	# Restore bound registers.  These are nops if Intel MPX isn't

-	# avaiable or disabled.

-# ifdef HAVE_MPX_SUPPORT

-	bndmov REGISTER_SAVE_BND3(%rsp), %bnd3

-	bndmov REGISTER_SAVE_BND2(%rsp), %bnd2

-	bndmov REGISTER_SAVE_BND1(%rsp), %bnd1

-	bndmov REGISTER_SAVE_BND0(%rsp), %bnd0

-# else

-	.byte 0x66,0x0f,0x1a,0x5c,0x24,REGISTER_SAVE_BND3

-	.byte 0x66,0x0f,0x1a,0x54,0x24,REGISTER_SAVE_BND2

-	.byte 0x66,0x0f,0x1a,0x4c,0x24,REGISTER_SAVE_BND1

-	.byte 0x66,0x0f,0x1a,0x44,0x24,REGISTER_SAVE_BND0

-# endif

+#define VEC_SIZE		64

+#define VMOVA			vmovdqa64

+#if DL_RUNIME_RESOLVE_REALIGN_STACK || VEC_SIZE <= DL_STACK_ALIGNMENT

+# define VMOV			vmovdqa64

+#else

+# define VMOV			vmovdqu64

 #endif

-	# Get register content back.

-	movq REGISTER_SAVE_R9(%rsp), %r9

-	movq REGISTER_SAVE_R8(%rsp), %r8

-	movq REGISTER_SAVE_RDI(%rsp), %rdi

-	movq REGISTER_SAVE_RSI(%rsp), %rsi

-	movq REGISTER_SAVE_RDX(%rsp), %rdx

-	movq REGISTER_SAVE_RCX(%rsp), %rcx

-	movq REGISTER_SAVE_RAX(%rsp), %rax