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From 0d3555b9b4d5cefe116c32bfa38ac70f1d6c25cb Mon Sep 17 00:00:00 2001
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From: Carlos Eduardo Seo <cseo@linux.vnet.ibm.com>
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Date: Wed, 11 Nov 2015 17:31:28 -0200
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Subject: [PATCH] powerpc: Optimization for strlen for POWER8.
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This implementation takes advantage of vectorization to improve performance of
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the loop over the current strlen implementation for POWER7.
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(cherry picked from commit 1b045ee53e0b8bed75745b931b33f27d21c9ed22)
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---
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ChangeLog | 13 +
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sysdeps/powerpc/powerpc64/multiarch/Makefile | 2 +-
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.../powerpc/powerpc64/multiarch/ifunc-impl-list.c | 2 +
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.../powerpc/powerpc64/multiarch/strlen-power8.S | 39 +++
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sysdeps/powerpc/powerpc64/multiarch/strlen.c | 9 +-
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sysdeps/powerpc/powerpc64/power8/strlen.S | 297 +++++++++++++++++++++
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6 files changed, 358 insertions(+), 4 deletions(-)
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create mode 100644 sysdeps/powerpc/powerpc64/multiarch/strlen-power8.S
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create mode 100644 sysdeps/powerpc/powerpc64/power8/strlen.S
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diff --git a/ChangeLog b/ChangeLog
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index f030b68..e7ea58a 100644
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diff --git a/sysdeps/powerpc/powerpc64/multiarch/Makefile b/sysdeps/powerpc/powerpc64/multiarch/Makefile
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index 7ed56bf..57abe8f 100644
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--- a/sysdeps/powerpc/powerpc64/multiarch/Makefile
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+++ b/sysdeps/powerpc/powerpc64/multiarch/Makefile
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@@ -20,7 +20,7 @@ sysdep_routines += memcpy-power7 memcpy-a2 memcpy-power6 memcpy-cell \
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strncpy-power8 strncpy-power7 strncpy-ppc64 \
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strncat-power7 \
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strstr-power7 strstr-ppc64 \
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- strspn-power8 strspn-ppc64 \
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+ strspn-power8 strspn-ppc64 strlen-power8 \
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rawmemchr-ppc64 strlen-power7 strlen-ppc64 strnlen-power7 \
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strnlen-ppc64 strcasecmp-power7 strcasecmp_l-power7 \
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strncase-power7 strncase_l-power7 \
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diff --git a/sysdeps/powerpc/powerpc64/multiarch/ifunc-impl-list.c b/sysdeps/powerpc/powerpc64/multiarch/ifunc-impl-list.c
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index f6c70ba..583885c 100644
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--- a/sysdeps/powerpc/powerpc64/multiarch/ifunc-impl-list.c
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+++ b/sysdeps/powerpc/powerpc64/multiarch/ifunc-impl-list.c
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@@ -101,6 +101,8 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
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/* Support sysdeps/powerpc/powerpc64/multiarch/strlen.c. */
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IFUNC_IMPL (i, name, strlen,
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+ IFUNC_IMPL_ADD (array, i, strlen, hwcap2 & PPC_FEATURE2_ARCH_2_07,
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+ __strlen_power8)
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IFUNC_IMPL_ADD (array, i, strlen, hwcap & PPC_FEATURE_HAS_VSX,
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__strlen_power7)
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IFUNC_IMPL_ADD (array, i, strlen, 1,
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diff --git a/sysdeps/powerpc/powerpc64/multiarch/strlen-power8.S b/sysdeps/powerpc/powerpc64/multiarch/strlen-power8.S
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new file mode 100644
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index 0000000..686dc3d
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--- /dev/null
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+++ b/sysdeps/powerpc/powerpc64/multiarch/strlen-power8.S
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@@ -0,0 +1,39 @@
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+/* Optimized strlen implementation for POWER8.
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+ Copyright (C) 2016 Free Software Foundation, Inc.
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+ This file is part of the GNU C Library.
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+
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+ The GNU C Library is free software; you can redistribute it and/or
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+ modify it under the terms of the GNU Lesser General Public
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+ License as published by the Free Software Foundation; either
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+ version 2.1 of the License, or (at your option) any later version.
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+
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+ The GNU C Library is distributed in the hope that it will be useful,
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+ but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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+ Lesser General Public License for more details.
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+
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+ You should have received a copy of the GNU Lesser General Public
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+ License along with the GNU C Library; if not, see
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+ <http://www.gnu.org/licenses/>. */
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+
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+#include <sysdep.h>
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+
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+#undef EALIGN
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+#define EALIGN(name, alignt, words) \
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+ .section ".text"; \
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+ ENTRY_2(__strlen_power8) \
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+ .align ALIGNARG(alignt); \
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+ EALIGN_W_##words; \
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+ BODY_LABEL(__strlen_power8): \
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+ cfi_startproc; \
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+ LOCALENTRY(__strlen_power8)
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+#undef END
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+#define END(name) \
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+ cfi_endproc; \
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+ TRACEBACK(__strlen_power8) \
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+ END_2(__strlen_power8)
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+
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+#undef libc_hidden_builtin_def
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+#define libc_hidden_builtin_def(name)
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+
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+#include <sysdeps/powerpc/powerpc64/power8/strlen.S>
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diff --git a/sysdeps/powerpc/powerpc64/multiarch/strlen.c b/sysdeps/powerpc/powerpc64/multiarch/strlen.c
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index 79a53d9..4b400a5 100644
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--- a/sysdeps/powerpc/powerpc64/multiarch/strlen.c
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+++ b/sysdeps/powerpc/powerpc64/multiarch/strlen.c
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@@ -29,11 +29,14 @@ extern __typeof (__redirect_strlen) __libc_strlen;
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extern __typeof (__redirect_strlen) __strlen_ppc attribute_hidden;
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extern __typeof (__redirect_strlen) __strlen_power7 attribute_hidden;
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+extern __typeof (__redirect_strlen) __strlen_power8 attribute_hidden;
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libc_ifunc (__libc_strlen,
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- (hwcap & PPC_FEATURE_HAS_VSX)
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- ? __strlen_power7
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- : __strlen_ppc);
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+ (hwcap2 & PPC_FEATURE2_ARCH_2_07)
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+ ? __strlen_power8 :
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+ (hwcap & PPC_FEATURE_HAS_VSX)
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+ ? __strlen_power7
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+ : __strlen_ppc);
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#undef strlen
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strong_alias (__libc_strlen, strlen)
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diff --git a/sysdeps/powerpc/powerpc64/power8/strlen.S b/sysdeps/powerpc/powerpc64/power8/strlen.S
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new file mode 100644
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index 0000000..0142747
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--- /dev/null
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+++ b/sysdeps/powerpc/powerpc64/power8/strlen.S
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@@ -0,0 +1,297 @@
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+/* Optimized strlen implementation for PowerPC64/POWER8 using a vectorized
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+ loop.
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+ Copyright (C) 2016 Free Software Foundation, Inc.
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+ This file is part of the GNU C Library.
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+
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+ The GNU C Library is free software; you can redistribute it and/or
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+ modify it under the terms of the GNU Lesser General Public
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+ License as published by the Free Software Foundation; either
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+ version 2.1 of the License, or (at your option) any later version.
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+
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+ The GNU C Library is distributed in the hope that it will be useful,
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+ but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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+ Lesser General Public License for more details.
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+
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+ You should have received a copy of the GNU Lesser General Public
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+ License along with the GNU C Library; if not, see
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+ <http://www.gnu.org/licenses/>. */
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+
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+#include <sysdep.h>
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+
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+/* TODO: change these to the actual instructions when the minimum required
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+ binutils allows it. */
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+#define MFVRD(r,v) .long (0x7c000067 | ((v)<<(32-11)) | ((r)<<(32-16)))
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+#define VBPERMQ(t,a,b) .long (0x1000054c \
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+ | ((t)<<(32-11)) \
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+ | ((a)<<(32-16)) \
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+ | ((b)<<(32-21)) )
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+
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+/* int [r3] strlen (char *s [r3]) */
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+
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+/* TODO: change this to .machine power8 when the minimum required binutils
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+ allows it. */
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+ .machine power7
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+EALIGN (strlen, 4, 0)
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+ CALL_MCOUNT 1
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+ dcbt 0,r3
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+ clrrdi r4,r3,3 /* Align the address to doubleword boundary. */
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+ rlwinm r6,r3,3,26,28 /* Calculate padding. */
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+ li r0,0 /* Doubleword with null chars to use
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+ with cmpb. */
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+ li r5,-1 /* MASK = 0xffffffffffffffff. */
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+ ld r12,0(r4) /* Load doubleword from memory. */
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+#ifdef __LITTLE_ENDIAN__
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+ sld r5,r5,r6
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+#else
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+ srd r5,r5,r6 /* MASK = MASK >> padding. */
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+#endif
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+ orc r9,r12,r5 /* Mask bits that are not part of the string. */
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+ cmpb r10,r9,r0 /* Check for null bytes in DWORD1. */
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+ cmpdi cr7,r10,0 /* If r10 == 0, no null's have been found. */
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+ bne cr7,L(done)
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+
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+ /* For shorter strings (< 64 bytes), we will not use vector registers,
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+ as the overhead isn't worth it. So, let's use GPRs instead. This
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+ will be done the same way as we do in the POWER7 implementation.
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+ Let's see if we are aligned to a quadword boundary. If so, we can
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+ jump to the first (non-vectorized) loop. Otherwise, we have to
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+ handle the next DWORD first. */
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+ mtcrf 0x01,r4
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+ mr r9,r4
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+ addi r9,r9,8
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+ bt 28,L(align64)
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+
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+ /* Handle the next 8 bytes so we are aligned to a quadword
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+ boundary. */
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+ ldu r5,8(r4)
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+ cmpb r10,r5,r0
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+ cmpdi cr7,r10,0
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+ addi r9,r9,8
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+ bne cr7,L(done)
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+
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+L(align64):
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+ /* Proceed to the old (POWER7) implementation, checking two doublewords
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+ per iteraction. For the first 56 bytes, we will just check for null
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+ characters. After that, we will also check if we are 64-byte aligned
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+ so we can jump to the vectorized implementation. We will unroll
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+ these loops to avoid excessive branching. */
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+ ld r6,8(r4)
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+ ldu r5,16(r4)
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+ cmpb r10,r6,r0
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+ cmpb r11,r5,r0
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+ or r5,r10,r11
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+ cmpdi cr7,r5,0
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+ addi r9,r9,16
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+ bne cr7,L(dword_zero)
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+
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+ ld r6,8(r4)
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+ ldu r5,16(r4)
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+ cmpb r10,r6,r0
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+ cmpb r11,r5,r0
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ce426f |
+ or r5,r10,r11
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+ cmpdi cr7,r5,0
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+ addi r9,r9,16
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+ bne cr7,L(dword_zero)
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+
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+ ld r6,8(r4)
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+ ldu r5,16(r4)
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+ cmpb r10,r6,r0
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+ cmpb r11,r5,r0
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ce426f |
+ or r5,r10,r11
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ce426f |
+ cmpdi cr7,r5,0
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ce426f |
+ addi r9,r9,16
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+ bne cr7,L(dword_zero)
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+
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ce426f |
+ /* Are we 64-byte aligned? If so, jump to the vectorized loop.
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ce426f |
+ Note: aligning to 64-byte will necessarily slow down performance for
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+ strings around 64 bytes in length due to the extra comparisons
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+ required to check alignment for the vectorized loop. This is a
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+ necessary tradeoff we are willing to take in order to speed up the
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ce426f |
+ calculation for larger strings. */
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ce426f |
+ andi. r10,r9,63
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ce426f |
+ beq cr0,L(preloop)
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ce426f |
+ ld r6,8(r4)
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ce426f |
+ ldu r5,16(r4)
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ce426f |
+ cmpb r10,r6,r0
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ce426f |
+ cmpb r11,r5,r0
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ce426f |
+ or r5,r10,r11
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ce426f |
+ cmpdi cr7,r5,0
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ce426f |
+ addi r9,r9,16
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ce426f |
+ bne cr7,L(dword_zero)
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ce426f |
+
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ce426f |
+ andi. r10,r9,63
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ce426f |
+ beq cr0,L(preloop)
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ce426f |
+ ld r6,8(r4)
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ce426f |
+ ldu r5,16(r4)
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ce426f |
+ cmpb r10,r6,r0
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ce426f |
+ cmpb r11,r5,r0
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ce426f |
+ or r5,r10,r11
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ce426f |
+ cmpdi cr7,r5,0
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ce426f |
+ addi r9,r9,16
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ce426f |
+ bne cr7,L(dword_zero)
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ce426f |
+
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ce426f |
+ andi. r10,r9,63
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ce426f |
+ beq cr0,L(preloop)
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ce426f |
+ ld r6,8(r4)
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ce426f |
+ ldu r5,16(r4)
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ce426f |
+ cmpb r10,r6,r0
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ce426f |
+ cmpb r11,r5,r0
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ce426f |
+ or r5,r10,r11
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ce426f |
+ cmpdi cr7,r5,0
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ce426f |
+ addi r9,r9,16
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ce426f |
+ bne cr7,L(dword_zero)
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ce426f |
+
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ce426f |
+ andi. r10,r9,63
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ce426f |
+ beq cr0,L(preloop)
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ce426f |
+ ld r6,8(r4)
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ce426f |
+ ldu r5,16(r4)
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ce426f |
+ cmpb r10,r6,r0
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ce426f |
+ cmpb r11,r5,r0
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ce426f |
+ or r5,r10,r11
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ce426f |
+ cmpdi cr7,r5,0
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ce426f |
+ addi r9,r9,16
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ce426f |
+
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ce426f |
+ /* At this point, we are necessarily 64-byte aligned. If no zeroes were
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ce426f |
+ found, jump to the vectorized loop. */
|
|
|
ce426f |
+ beq cr7,L(preloop)
|
|
|
ce426f |
+
|
|
|
ce426f |
+L(dword_zero):
|
|
|
ce426f |
+ /* OK, one (or both) of the doublewords contains a null byte. Check
|
|
|
ce426f |
+ the first doubleword and decrement the address in case the first
|
|
|
ce426f |
+ doubleword really contains a null byte. */
|
|
|
ce426f |
+
|
|
|
ce426f |
+ cmpdi cr6,r10,0
|
|
|
ce426f |
+ addi r4,r4,-8
|
|
|
ce426f |
+ bne cr6,L(done)
|
|
|
ce426f |
+
|
|
|
ce426f |
+ /* The null byte must be in the second doubleword. Adjust the address
|
|
|
ce426f |
+ again and move the result of cmpb to r10 so we can calculate the
|
|
|
ce426f |
+ length. */
|
|
|
ce426f |
+
|
|
|
ce426f |
+ mr r10,r11
|
|
|
ce426f |
+ addi r4,r4,8
|
|
|
ce426f |
+
|
|
|
ce426f |
+ /* If the null byte was found in the non-vectorized code, compute the
|
|
|
ce426f |
+ final length. r10 has the output of the cmpb instruction, that is,
|
|
|
ce426f |
+ it contains 0xff in the same position as the null byte in the
|
|
|
ce426f |
+ original doubleword from the string. Use that to calculate the
|
|
|
ce426f |
+ length. */
|
|
|
ce426f |
+L(done):
|
|
|
ce426f |
+#ifdef __LITTLE_ENDIAN__
|
|
|
ce426f |
+ addi r9, r10,-1 /* Form a mask from trailing zeros. */
|
|
|
ce426f |
+ andc r9, r9,r10
|
|
|
ce426f |
+ popcntd r0, r9 /* Count the bits in the mask. */
|
|
|
ce426f |
+#else
|
|
|
ce426f |
+ cntlzd r0,r10 /* Count leading zeros before the match. */
|
|
|
ce426f |
+#endif
|
|
|
ce426f |
+ subf r5,r3,r4
|
|
|
ce426f |
+ srdi r0,r0,3 /* Convert leading/trailing zeros to bytes. */
|
|
|
ce426f |
+ add r3,r5,r0 /* Compute final length. */
|
|
|
ce426f |
+ blr
|
|
|
ce426f |
+
|
|
|
ce426f |
+ /* Vectorized implementation starts here. */
|
|
|
ce426f |
+ .p2align 4
|
|
|
ce426f |
+L(preloop):
|
|
|
ce426f |
+ /* Set up for the loop. */
|
|
|
ce426f |
+ mr r4,r9
|
|
|
ce426f |
+ li r7, 16 /* Load required offsets. */
|
|
|
ce426f |
+ li r8, 32
|
|
|
ce426f |
+ li r9, 48
|
|
|
ce426f |
+ li r12, 8
|
|
|
ce426f |
+ vxor v0,v0,v0 /* VR with null chars to use with
|
|
|
ce426f |
+ vcmpequb. */
|
|
|
ce426f |
+
|
|
|
ce426f |
+ /* Main loop to look for the end of the string. We will read in
|
|
|
ce426f |
+ 64-byte chunks. Align it to 32 bytes and unroll it 3 times to
|
|
|
ce426f |
+ leverage the icache performance. */
|
|
|
ce426f |
+ .p2align 5
|
|
|
ce426f |
+L(loop):
|
|
|
ce426f |
+ lvx v1,r4,r0 /* Load 4 quadwords. */
|
|
|
ce426f |
+ lvx v2,r4,r7
|
|
|
ce426f |
+ lvx v3,r4,r8
|
|
|
ce426f |
+ lvx v4,r4,r9
|
|
|
ce426f |
+ vminub v5,v1,v2 /* Compare and merge into one VR for speed. */
|
|
|
ce426f |
+ vminub v6,v3,v4
|
|
|
ce426f |
+ vminub v7,v5,v6
|
|
|
ce426f |
+ vcmpequb. v7,v7,v0 /* Check for NULLs. */
|
|
|
ce426f |
+ addi r4,r4,64 /* Adjust address for the next iteration. */
|
|
|
ce426f |
+ bne cr6,L(vmx_zero)
|
|
|
ce426f |
+
|
|
|
ce426f |
+ lvx v1,r4,r0 /* Load 4 quadwords. */
|
|
|
ce426f |
+ lvx v2,r4,r7
|
|
|
ce426f |
+ lvx v3,r4,r8
|
|
|
ce426f |
+ lvx v4,r4,r9
|
|
|
ce426f |
+ vminub v5,v1,v2 /* Compare and merge into one VR for speed. */
|
|
|
ce426f |
+ vminub v6,v3,v4
|
|
|
ce426f |
+ vminub v7,v5,v6
|
|
|
ce426f |
+ vcmpequb. v7,v7,v0 /* Check for NULLs. */
|
|
|
ce426f |
+ addi r4,r4,64 /* Adjust address for the next iteration. */
|
|
|
ce426f |
+ bne cr6,L(vmx_zero)
|
|
|
ce426f |
+
|
|
|
ce426f |
+ lvx v1,r4,r0 /* Load 4 quadwords. */
|
|
|
ce426f |
+ lvx v2,r4,r7
|
|
|
ce426f |
+ lvx v3,r4,r8
|
|
|
ce426f |
+ lvx v4,r4,r9
|
|
|
ce426f |
+ vminub v5,v1,v2 /* Compare and merge into one VR for speed. */
|
|
|
ce426f |
+ vminub v6,v3,v4
|
|
|
ce426f |
+ vminub v7,v5,v6
|
|
|
ce426f |
+ vcmpequb. v7,v7,v0 /* Check for NULLs. */
|
|
|
ce426f |
+ addi r4,r4,64 /* Adjust address for the next iteration. */
|
|
|
ce426f |
+ beq cr6,L(loop)
|
|
|
ce426f |
+
|
|
|
ce426f |
+L(vmx_zero):
|
|
|
ce426f |
+ /* OK, we found a null byte. Let's look for it in the current 64-byte
|
|
|
ce426f |
+ block and mark it in its corresponding VR. */
|
|
|
ce426f |
+ vcmpequb v1,v1,v0
|
|
|
ce426f |
+ vcmpequb v2,v2,v0
|
|
|
ce426f |
+ vcmpequb v3,v3,v0
|
|
|
ce426f |
+ vcmpequb v4,v4,v0
|
|
|
ce426f |
+
|
|
|
ce426f |
+ /* We will now 'compress' the result into a single doubleword, so it
|
|
|
ce426f |
+ can be moved to a GPR for the final calculation. First, we
|
|
|
ce426f |
+ generate an appropriate mask for vbpermq, so we can permute bits into
|
|
|
ce426f |
+ the first halfword. */
|
|
|
ce426f |
+ vspltisb v10,3
|
|
|
ce426f |
+ lvsl v11,r0,r0
|
|
|
ce426f |
+ vslb v10,v11,v10
|
|
|
ce426f |
+
|
|
|
ce426f |
+ /* Permute the first bit of each byte into bits 48-63. */
|
|
|
ce426f |
+ VBPERMQ(v1,v1,v10)
|
|
|
ce426f |
+ VBPERMQ(v2,v2,v10)
|
|
|
ce426f |
+ VBPERMQ(v3,v3,v10)
|
|
|
ce426f |
+ VBPERMQ(v4,v4,v10)
|
|
|
ce426f |
+
|
|
|
ce426f |
+ /* Shift each component into its correct position for merging. */
|
|
|
ce426f |
+#ifdef __LITTLE_ENDIAN__
|
|
|
ce426f |
+ vsldoi v2,v2,v2,2
|
|
|
ce426f |
+ vsldoi v3,v3,v3,4
|
|
|
ce426f |
+ vsldoi v4,v4,v4,6
|
|
|
ce426f |
+#else
|
|
|
ce426f |
+ vsldoi v1,v1,v1,6
|
|
|
ce426f |
+ vsldoi v2,v2,v2,4
|
|
|
ce426f |
+ vsldoi v3,v3,v3,2
|
|
|
ce426f |
+#endif
|
|
|
ce426f |
+
|
|
|
ce426f |
+ /* Merge the results and move to a GPR. */
|
|
|
ce426f |
+ vor v1,v2,v1
|
|
|
ce426f |
+ vor v2,v3,v4
|
|
|
ce426f |
+ vor v4,v1,v2
|
|
|
ce426f |
+ MFVRD(r10,v4)
|
|
|
ce426f |
+
|
|
|
ce426f |
+ /* Adjust address to the begninning of the current 64-byte block. */
|
|
|
ce426f |
+ addi r4,r4,-64
|
|
|
ce426f |
+
|
|
|
ce426f |
+#ifdef __LITTLE_ENDIAN__
|
|
|
ce426f |
+ addi r9, r10,-1 /* Form a mask from trailing zeros. */
|
|
|
ce426f |
+ andc r9, r9,r10
|
|
|
ce426f |
+ popcntd r0, r9 /* Count the bits in the mask. */
|
|
|
ce426f |
+#else
|
|
|
ce426f |
+ cntlzd r0,r10 /* Count leading zeros before the match. */
|
|
|
ce426f |
+#endif
|
|
|
ce426f |
+ subf r5,r3,r4
|
|
|
ce426f |
+ add r3,r5,r0 /* Compute final length. */
|
|
|
ce426f |
+ blr
|
|
|
ce426f |
+
|
|
|
ce426f |
+END (strlen)
|
|
|
ce426f |
+libc_hidden_builtin_def (strlen)
|
|
|
ce426f |
--
|
|
|
ce426f |
2.1.0
|
|
|
ce426f |
|