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From 1cf3bb5ec15f28245a6840b5b0443685c828a467 Mon Sep 17 00:00:00 2001
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From: "Paul E. Murphy" <murphyp@linux.vnet.ibm.com>
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Date: Mon, 14 Mar 2016 17:40:46 -0400
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Subject: [PATCH] powerpc: Add optimized P8 strspn
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This utilizes vectors and bitmasks. For small needle, large
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haystack, the performance improvement is upto 8x. For short
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strings (0-4B), the cost of computing the bitmask dominates,
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and is a tad slower.
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(cherry picked from commit 25dba0ad054723196fb633ba5d8a463ef5cb775c)
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---
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ChangeLog | 15 ++
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sysdeps/powerpc/powerpc64/multiarch/Makefile | 3 +-
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.../powerpc/powerpc64/multiarch/ifunc-impl-list.c | 8 +
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.../powerpc/powerpc64/multiarch/strspn-power8.S | 40 +++++
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sysdeps/powerpc/powerpc64/multiarch/strspn-ppc64.c | 25 +++
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sysdeps/powerpc/powerpc64/multiarch/strspn.c | 35 ++++
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sysdeps/powerpc/powerpc64/power8/strspn.S | 179 +++++++++++++++++++++
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7 files changed, 304 insertions(+), 1 deletion(-)
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create mode 100644 sysdeps/powerpc/powerpc64/multiarch/strspn-power8.S
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create mode 100644 sysdeps/powerpc/powerpc64/multiarch/strspn-ppc64.c
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create mode 100644 sysdeps/powerpc/powerpc64/multiarch/strspn.c
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create mode 100644 sysdeps/powerpc/powerpc64/power8/strspn.S
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diff --git a/ChangeLog b/ChangeLog
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index 496ef12..f030b68 100644
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diff --git a/sysdeps/powerpc/powerpc64/multiarch/Makefile b/sysdeps/powerpc/powerpc64/multiarch/Makefile
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index 3b0e3a0..7ed56bf 100644
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--- a/sysdeps/powerpc/powerpc64/multiarch/Makefile
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+++ b/sysdeps/powerpc/powerpc64/multiarch/Makefile
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@@ -19,6 +19,7 @@ sysdep_routines += memcpy-power7 memcpy-a2 memcpy-power6 memcpy-cell \
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strncpy-power8 strncpy-power7 strncpy-ppc64 \
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strncat-power7 \
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strstr-power7 strstr-ppc64 \
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+ strspn-power8 strspn-ppc64 \
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rawmemchr-ppc64 strlen-power7 strlen-ppc64 strnlen-power7 \
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strnlen-ppc64 strcasecmp-power7 strcasecmp_l-power7 \
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strncase-power7 strncase_l-power7 \
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diff --git a/sysdeps/powerpc/powerpc64/multiarch/ifunc-impl-list.c b/sysdeps/powerpc/powerpc64/multiarch/ifunc-impl-list.c
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index 364385b..f6c70ba 100644
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--- a/sysdeps/powerpc/powerpc64/multiarch/ifunc-impl-list.c
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+++ b/sysdeps/powerpc/powerpc64/multiarch/ifunc-impl-list.c
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@@ -322,6 +322,14 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
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IFUNC_IMPL_ADD (array, i, strcat, 1,
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__strcat_ppc))
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+ /* Support sysdeps/powerpc/powerpc64/multiarch/strspn.c. */
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+ IFUNC_IMPL (i, name, strspn,
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+ IFUNC_IMPL_ADD (array, i, strspn,
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+ hwcap2 & PPC_FEATURE2_ARCH_2_07,
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+ __strspn_power8)
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+ IFUNC_IMPL_ADD (array, i, strspn, 1,
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+ __strspn_ppc))
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+
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/* Support sysdeps/powerpc/powerpc64/multiarch/strstr.c. */
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IFUNC_IMPL (i, name, strstr,
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IFUNC_IMPL_ADD (array, i, strstr,
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diff --git a/sysdeps/powerpc/powerpc64/multiarch/strspn-power8.S b/sysdeps/powerpc/powerpc64/multiarch/strspn-power8.S
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new file mode 100644
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index 0000000..86a4e09
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--- /dev/null
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+++ b/sysdeps/powerpc/powerpc64/multiarch/strspn-power8.S
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@@ -0,0 +1,40 @@
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+/* Optimized strspn implementation for POWER8.
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+ Copyright (C) 2016 Free Software Foundation, Inc.
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+ This file is part of the GNU C Library.
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+
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+ The GNU C Library is free software; you can redistribute it and/or
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+ modify it under the terms of the GNU Lesser General Public
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+ License as published by the Free Software Foundation; either
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+ version 2.1 of the License, or (at your option) any later version.
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+
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+ The GNU C Library is distributed in the hope that it will be useful,
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+ but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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+ Lesser General Public License for more details.
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+
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+ You should have received a copy of the GNU Lesser General Public
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+ License along with the GNU C Library; if not, see
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+ <http://www.gnu.org/licenses/>. */
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+
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+#include <sysdep.h>
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+
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+#undef EALIGN
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+#define EALIGN(name, alignt, words) \
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+ .section ".text"; \
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+ ENTRY_2(__strspn_power8) \
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+ .align ALIGNARG(alignt); \
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+ EALIGN_W_##words; \
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+ BODY_LABEL(__strspn_power8): \
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+ cfi_startproc; \
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+ LOCALENTRY(__strspn_power8)
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+
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+#undef END
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+#define END(name) \
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+ cfi_endproc; \
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+ TRACEBACK(__strspn_power8) \
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+ END_2(__strspn_power8)
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+
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+#undef libc_hidden_builtin_def
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+#define libc_hidden_builtin_def(name)
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+
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+#include <sysdeps/powerpc/powerpc64/power8/strspn.S>
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diff --git a/sysdeps/powerpc/powerpc64/multiarch/strspn-ppc64.c b/sysdeps/powerpc/powerpc64/multiarch/strspn-ppc64.c
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new file mode 100644
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index 0000000..4c63665
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--- /dev/null
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+++ b/sysdeps/powerpc/powerpc64/multiarch/strspn-ppc64.c
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@@ -0,0 +1,25 @@
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+/* Default strspn implementation for PowerPC64.
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+ Copyright (C) 2016 Free Software Foundation, Inc.
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+ This file is part of the GNU C Library.
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+
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+ The GNU C Library is free software; you can redistribute it and/or
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+ modify it under the terms of the GNU Lesser General Public
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+ License as published by the Free Software Foundation; either
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+ version 2.1 of the License, or (at your option) any later version.
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+
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+ The GNU C Library is distributed in the hope that it will be useful,
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+ but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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+ Lesser General Public License for more details.
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+
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+ You should have received a copy of the GNU Lesser General Public
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+ License along with the GNU C Library; if not, see
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+ <http://www.gnu.org/licenses/>. */
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+
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+#define STRSPN __strspn_ppc
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+#ifdef SHARED
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+#undef libc_hidden_def
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+#define libc_hidden_def(name)
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+#endif
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+
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+#include <string/strspn.c>
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diff --git a/sysdeps/powerpc/powerpc64/multiarch/strspn.c b/sysdeps/powerpc/powerpc64/multiarch/strspn.c
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new file mode 100644
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index 0000000..0e653f3
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--- /dev/null
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+++ b/sysdeps/powerpc/powerpc64/multiarch/strspn.c
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@@ -0,0 +1,35 @@
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+/* Multiple versions of strspn. PowerPC64 version.
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+ Copyright (C) 2016 Free Software Foundation, Inc.
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+ This file is part of the GNU C Library.
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+
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+ The GNU C Library is free software; you can redistribute it and/or
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+ modify it under the terms of the GNU Lesser General Public
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+ License as published by the Free Software Foundation; either
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+ version 2.1 of the License, or (at your option) any later version.
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+
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+ The GNU C Library is distributed in the hope that it will be useful,
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+ but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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+ Lesser General Public License for more details.
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+
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+ You should have received a copy of the GNU Lesser General Public
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+ License along with the GNU C Library; if not, see
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+ <http://www.gnu.org/licenses/>. */
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+
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+# include <string.h>
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+# include <shlib-compat.h>
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+# include "init-arch.h"
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+
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+#undef strspn
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+extern __typeof (strspn) __libc_strspn;
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+
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+extern __typeof (strspn) __strspn_ppc attribute_hidden;
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+extern __typeof (strspn) __strspn_power8 attribute_hidden;
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+
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+libc_ifunc (__libc_strspn,
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+ (hwcap2 & PPC_FEATURE2_ARCH_2_07)
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+ ? __strspn_power8
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+ : __strspn_ppc);
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+
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+weak_alias (__libc_strspn, strspn)
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+libc_hidden_builtin_def (strspn)
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diff --git a/sysdeps/powerpc/powerpc64/power8/strspn.S b/sysdeps/powerpc/powerpc64/power8/strspn.S
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new file mode 100644
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index 0000000..0dda437
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--- /dev/null
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+++ b/sysdeps/powerpc/powerpc64/power8/strspn.S
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@@ -0,0 +1,179 @@
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+/* Optimized strspn implementation for Power8.
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+
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+ Copyright (C) 2016 Free Software Foundation, Inc.
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+ This file is part of the GNU C Library.
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+
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+ The GNU C Library is free software; you can redistribute it and/or
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+ modify it under the terms of the GNU Lesser General Public
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+ License as published by the Free Software Foundation; either
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+ version 2.1 of the License, or (at your option) any later version.
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+
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+ The GNU C Library is distributed in the hope that it will be useful,
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+ but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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+ Lesser General Public License for more details.
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+
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+ You should have received a copy of the GNU Lesser General Public
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+ License along with the GNU C Library; if not, see
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+ <http://www.gnu.org/licenses/>. */
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+
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+/* size_t [r3] strspn (const char *string [r3],
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+ const char *needleAccept [r4]) */
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+
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+/* This takes a novel approach by computing a 256 bit mask whereby
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+ each set bit implies the byte is "accepted". P8 vector hardware
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+ has extremely efficient hardware for selecting bits from a mask.
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+
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+ One might ask "why not use bpermd for short strings"? It is
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+ so slow that its performance about matches the generic PPC64
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+ variant without any fancy masking, with the added expense of
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+ making the mask. That was the first variant of this. */
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+
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+
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+
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+#include "sysdep.h"
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+
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+/* Simple macro to use VSX instructions in overlapping VR's. */
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+#define XXVR(insn, vrt, vra, vrb) \
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+ insn 32+vrt, 32+vra, 32+vrb
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+
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+/* ISA 2.07B instructions are not all defined for older binutils.
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+ Macros are defined below for these newer instructions in order
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+ to maintain compatibility. */
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+
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+/* Note, TX/SX is always set as VMX regs are the high 32 VSX regs. */
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+#define MTVRD(v,r) .long (0x7c000167 | ((v)<<(32-11)) | ((r)<<(32-16)))
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+#define MFVRD(r,v) .long (0x7c000067 | ((v)<<(32-11)) | ((r)<<(32-16)))
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+
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+#define VBPERMQ(t,a,b) .long (0x1000054c \
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+ | ((t)<<(32-11)) \
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+ | ((a)<<(32-16)) \
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+ | ((b)<<(32-21)) )
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+
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+ /* This can be updated to power8 once the minimum version of
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+ binutils supports power8 and the above instructions. */
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+ .machine power7
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+EALIGN(strspn, 4, 0)
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+ CALL_MCOUNT 2
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+
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+ /* Generate useful constants for later on. */
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+ vspltisb v1, 7
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+ vspltisb v2, -1
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+ vslb v1, v1, v1 /* 0x80 to swap high bit for vbpermq. */
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+ vspltisb v10, 0
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+ vsldoi v4, v10, v2, 2 /* 0xFFFF into vr4. */
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+ XXVR(xxmrgld, v4, v4, v10) /* Mask for checking matches. */
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+
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+ /* Prepare to compute 256b mask. */
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+ addi r4, r4, -1
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+ li r5, 0
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+ li r6, 0
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+ li r7, 0
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+ li r8, 0
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+ li r11, 1
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+ sldi r11, r11, 63
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+
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+ /* Start interleaved Mask computation.
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+ This will eventually or 1's into ignored bits from vbpermq. */
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+ lvsr v11, 0, r3
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+ vspltb v11, v11, 0 /* Splat shift constant. */
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+
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+ /* Build a 256b mask in r5-r8. */
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+ .align 4
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+L(next_needle):
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+ lbzu r9, 1(r4)
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+
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+ cmpldi cr0, r9, 0
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+ cmpldi cr1, r9, 128
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+
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+ /* This is a little tricky. srd only uses the first 7 bits,
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+ and if bit 7 is set, value is always 0. So, we can
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+ effectively shift 128b in this case. */
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+ xori r12, r9, 0x40 /* Invert bit 6. */
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+ srd r10, r11, r9 /* Mask for bits 0-63. */
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+ srd r12, r11, r12 /* Mask for bits 64-127. */
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+
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8ae002 |
+ beq cr0, L(start_cmp)
|
|
|
8ae002 |
+
|
|
|
8ae002 |
+ /* Now, or the value into the correct GPR. */
|
|
|
8ae002 |
+ bge cr1,L(needle_gt128)
|
|
|
8ae002 |
+ or r5, r5, r10 /* 0 - 63. */
|
|
|
8ae002 |
+ or r6, r6, r12 /* 64 - 127. */
|
|
|
8ae002 |
+ b L(next_needle)
|
|
|
8ae002 |
+
|
|
|
8ae002 |
+ .align 4
|
|
|
8ae002 |
+L(needle_gt128):
|
|
|
8ae002 |
+ or r7, r7, r10 /* 128 - 191. */
|
|
|
8ae002 |
+ or r8, r8, r12 /* 192 - 255. */
|
|
|
8ae002 |
+ b L(next_needle)
|
|
|
8ae002 |
+
|
|
|
8ae002 |
+
|
|
|
8ae002 |
+ .align 4
|
|
|
8ae002 |
+L(start_cmp):
|
|
|
8ae002 |
+ /* Move and merge bitmap into 2 VRs. bpermd is slower on P8. */
|
|
|
8ae002 |
+ mr r0, r3 /* Save r3 for final length computation. */
|
|
|
8ae002 |
+ MTVRD (v5, r5)
|
|
|
8ae002 |
+ MTVRD (v6, r6)
|
|
|
8ae002 |
+ MTVRD (v7, r7)
|
|
|
8ae002 |
+ MTVRD (v8, r8)
|
|
|
8ae002 |
+
|
|
|
8ae002 |
+ /* Continue interleaved mask generation. */
|
|
|
8ae002 |
+#ifdef __LITTLE_ENDIAN__
|
|
|
8ae002 |
+ vsrw v11, v2, v11 /* Note, shift ignores higher order bits. */
|
|
|
8ae002 |
+ vsplth v11, v11, 0 /* Only care about the high 16 bits of v10. */
|
|
|
8ae002 |
+#else
|
|
|
8ae002 |
+ vslw v11, v2, v11 /* Note, shift ignores higher order bits. */
|
|
|
8ae002 |
+ vsplth v11, v11, 1 /* Only care about the low 16 bits of v10. */
|
|
|
8ae002 |
+#endif
|
|
|
8ae002 |
+ lvx v0, 0, r3 /* Note, unaligned load ignores lower bits. */
|
|
|
8ae002 |
+
|
|
|
8ae002 |
+ /* Do the merging of the bitmask. */
|
|
|
8ae002 |
+ XXVR(xxmrghd, v5, v5, v6)
|
|
|
8ae002 |
+ XXVR(xxmrghd, v6, v7, v8)
|
|
|
8ae002 |
+
|
|
|
8ae002 |
+ /* Finish mask generation. */
|
|
|
8ae002 |
+ vand v11, v11, v4 /* Throwaway bits not in the mask. */
|
|
|
8ae002 |
+
|
|
|
8ae002 |
+ /* Compare the first 1-16B, while masking unwanted bytes. */
|
|
|
8ae002 |
+ clrrdi r3, r3, 4 /* Note, counts from qw boundaries. */
|
|
|
8ae002 |
+ vxor v9, v0, v1 /* Swap high bit. */
|
|
|
8ae002 |
+ VBPERMQ (v8, v5, v0)
|
|
|
8ae002 |
+ VBPERMQ (v7, v6, v9)
|
|
|
8ae002 |
+ vor v7, v7, v8
|
|
|
8ae002 |
+ vor v7, v7, v11 /* Ignore non-participating bytes. */
|
|
|
8ae002 |
+ vcmpequh. v8, v7, v4
|
|
|
8ae002 |
+ bnl cr6, L(done)
|
|
|
8ae002 |
+
|
|
|
8ae002 |
+ addi r3, r3, 16
|
|
|
8ae002 |
+
|
|
|
8ae002 |
+ .align 4
|
|
|
8ae002 |
+L(vec):
|
|
|
8ae002 |
+ lvx v0, 0, r3
|
|
|
8ae002 |
+ addi r3, r3, 16
|
|
|
8ae002 |
+ vxor v9, v0, v1 /* Swap high bit. */
|
|
|
8ae002 |
+ VBPERMQ (v8, v5, v0)
|
|
|
8ae002 |
+ VBPERMQ (v7, v6, v9)
|
|
|
8ae002 |
+ vor v7, v7, v8
|
|
|
8ae002 |
+ vcmpequh. v8, v7, v4
|
|
|
8ae002 |
+ blt cr6, L(vec)
|
|
|
8ae002 |
+
|
|
|
8ae002 |
+ addi r3, r3, -16
|
|
|
8ae002 |
+L(done):
|
|
|
8ae002 |
+ subf r3, r0, r3
|
|
|
8ae002 |
+ MFVRD (r10, v7)
|
|
|
8ae002 |
+
|
|
|
8ae002 |
+#ifdef __LITTLE_ENDIAN__
|
|
|
8ae002 |
+ addi r0, r10, 1 /* Count the trailing 1's. */
|
|
|
8ae002 |
+ andc r10, r10, r0
|
|
|
8ae002 |
+ popcntd r10, r10
|
|
|
8ae002 |
+#else
|
|
|
8ae002 |
+ xori r10, r10, 0xffff /* Count leading 1's by inverting. */
|
|
|
8ae002 |
+ addi r3, r3, -48 /* Account for the extra leading zeros. */
|
|
|
8ae002 |
+ cntlzd r10, r10
|
|
|
8ae002 |
+#endif
|
|
|
8ae002 |
+
|
|
|
8ae002 |
+ add r3, r3, r10
|
|
|
8ae002 |
+ blr
|
|
|
8ae002 |
+
|
|
|
8ae002 |
+END(strspn)
|
|
|
8ae002 |
+libc_hidden_builtin_def (strspn)
|
|
|
8ae002 |
--
|
|
|
8ae002 |
2.1.0
|
|
|
8ae002 |
|