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commit ff8714269c9312d9164456279a56b6f6c47e2771
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Author: Torvald Riegel <triegel@redhat.com>
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Date: Sun Sep 14 20:04:54 2014 +0200
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Add atomic operations similar to those provided by C11.
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Index: glibc-2.17-c758a686/include/atomic.h
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===================================================================
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--- glibc-2.17-c758a686.orig/include/atomic.h
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+++ glibc-2.17-c758a686/include/atomic.h
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@@ -542,6 +542,218 @@
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({ __typeof (x) __x; __asm ("" : "=r" (__x) : "0" (x)); __x; })
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#endif
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+/* This is equal to 1 iff the architecture supports 64b atomic operations. */
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+#ifndef __HAVE_64B_ATOMICS
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+#error Unable to determine if 64-bit atomics are present.
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+#endif
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+
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+/* The following functions are a subset of the atomic operations provided by
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+ C11. Usually, a function named atomic_OP_MO(args) is equivalent to C11's
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+ atomic_OP_explicit(args, memory_order_MO); exceptions noted below. */
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+
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+/* Each arch can request to use compiler built-ins for C11 atomics. If it
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+ does, all atomics will be based on these. */
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+#if USE_ATOMIC_COMPILER_BUILTINS
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+
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+/* We require 32b atomic operations; some archs also support 64b atomic
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+ operations. */
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+void __atomic_link_error (void);
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+# if __HAVE_64B_ATOMICS == 1
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+# define __atomic_check_size(mem) \
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+ if ((sizeof (*mem) != 4) && (sizeof (*mem) != 8)) \
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+ __atomic_link_error ();
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+# else
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+# define __atomic_check_size(mem) \
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+ if (sizeof (*mem) != 4) \
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+ __atomic_link_error ();
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+# endif
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+
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+# define atomic_thread_fence_acquire() \
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+ __atomic_thread_fence (__ATOMIC_ACQUIRE)
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+# define atomic_thread_fence_release() \
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+ __atomic_thread_fence (__ATOMIC_RELEASE)
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+# define atomic_thread_fence_seq_cst() \
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+ __atomic_thread_fence (__ATOMIC_SEQ_CST)
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+
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+# define atomic_load_relaxed(mem) \
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+ ({ __atomic_check_size((mem)); __atomic_load_n ((mem), __ATOMIC_RELAXED); })
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+# define atomic_load_acquire(mem) \
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+ ({ __atomic_check_size((mem)); __atomic_load_n ((mem), __ATOMIC_ACQUIRE); })
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+
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+# define atomic_store_relaxed(mem, val) \
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+ do { \
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+ __atomic_check_size((mem)); \
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+ __atomic_store_n ((mem), (val), __ATOMIC_RELAXED); \
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+ } while (0)
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+# define atomic_store_release(mem, val) \
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+ do { \
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+ __atomic_check_size((mem)); \
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+ __atomic_store_n ((mem), (val), __ATOMIC_RELEASE); \
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+ } while (0)
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+
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+/* On failure, this CAS has memory_order_relaxed semantics. */
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+# define atomic_compare_exchange_weak_relaxed(mem, expected, desired) \
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+ ({ __atomic_check_size((mem)); \
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+ __atomic_compare_exchange_n ((mem), (expected), (desired), 1, \
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+ __ATOMIC_RELAXED, __ATOMIC_RELAXED); })
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+# define atomic_compare_exchange_weak_acquire(mem, expected, desired) \
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+ ({ __atomic_check_size((mem)); \
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+ __atomic_compare_exchange_n ((mem), (expected), (desired), 1, \
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+ __ATOMIC_ACQUIRE, __ATOMIC_RELAXED); })
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+# define atomic_compare_exchange_weak_release(mem, expected, desired) \
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+ ({ __atomic_check_size((mem)); \
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+ __atomic_compare_exchange_n ((mem), (expected), (desired), 1, \
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+ __ATOMIC_RELEASE, __ATOMIC_RELAXED); })
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+
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+# define atomic_exchange_acquire(mem, desired) \
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+ ({ __atomic_check_size((mem)); \
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+ __atomic_exchange_n ((mem), (desired), __ATOMIC_ACQUIRE); })
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+# define atomic_exchange_release(mem, desired) \
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+ ({ __atomic_check_size((mem)); \
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+ __atomic_exchange_n ((mem), (desired), __ATOMIC_RELEASE); })
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+
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+# define atomic_fetch_add_relaxed(mem, operand) \
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+ ({ __atomic_check_size((mem)); \
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+ __atomic_fetch_add ((mem), (operand), __ATOMIC_RELAXED); })
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+# define atomic_fetch_add_acquire(mem, operand) \
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+ ({ __atomic_check_size((mem)); \
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+ __atomic_fetch_add ((mem), (operand), __ATOMIC_ACQUIRE); })
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+# define atomic_fetch_add_release(mem, operand) \
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+ ({ __atomic_check_size((mem)); \
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+ __atomic_fetch_add ((mem), (operand), __ATOMIC_RELEASE); })
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+# define atomic_fetch_add_acq_rel(mem, operand) \
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+ ({ __atomic_check_size((mem)); \
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+ __atomic_fetch_add ((mem), (operand), __ATOMIC_ACQ_REL); })
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+
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+# define atomic_fetch_and_acquire(mem, operand) \
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+ ({ __atomic_check_size((mem)); \
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+ __atomic_fetch_and ((mem), (operand), __ATOMIC_ACQUIRE); })
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+
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+# define atomic_fetch_or_relaxed(mem, operand) \
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+ ({ __atomic_check_size((mem)); \
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+ __atomic_fetch_or ((mem), (operand), __ATOMIC_RELAXED); })
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+# define atomic_fetch_or_acquire(mem, operand) \
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+ ({ __atomic_check_size((mem)); \
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+ __atomic_fetch_or ((mem), (operand), __ATOMIC_ACQUIRE); })
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+
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+#else /* !USE_ATOMIC_COMPILER_BUILTINS */
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+
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+/* By default, we assume that read, write, and full barriers are equivalent
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+ to acquire, release, and seq_cst barriers. Archs for which this does not
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+ hold have to provide custom definitions of the fences. */
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+# ifndef atomic_thread_fence_acquire
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+# define atomic_thread_fence_acquire() atomic_read_barrier ()
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+# endif
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+# ifndef atomic_thread_fence_release
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+# define atomic_thread_fence_release() atomic_write_barrier ()
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+# endif
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+# ifndef atomic_thread_fence_seq_cst
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+# define atomic_thread_fence_seq_cst() atomic_full_barrier ()
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+# endif
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+
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+# ifndef atomic_load_relaxed
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+# define atomic_load_relaxed(mem) \
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+ ({ __typeof (*(mem)) __atg100_val; \
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+ __asm ("" : "=r" (__atg100_val) : "0" (*(mem))); \
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+ __atg100_val; })
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+# endif
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+# ifndef atomic_load_acquire
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+# define atomic_load_acquire(mem) \
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+ ({ __typeof (*(mem)) __atg101_val = atomic_load_relaxed (mem); \
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+ atomic_thread_fence_acquire (); \
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+ __atg101_val; })
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+# endif
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+
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+# ifndef atomic_store_relaxed
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+/* XXX Use inline asm here? */
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+# define atomic_store_relaxed(mem, val) do { *(mem) = (val); } while (0)
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+# endif
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+# ifndef atomic_store_release
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+# define atomic_store_release(mem, val) \
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+ do { \
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+ atomic_thread_fence_release (); \
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+ atomic_store_relaxed ((mem), (val)); \
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+ } while (0)
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+# endif
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+
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+/* On failure, this CAS has memory_order_relaxed semantics. */
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+/* XXX This potentially has one branch more than necessary, but archs
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+ currently do not define a CAS that returns both the previous value and
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+ the success flag. */
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+# ifndef atomic_compare_exchange_weak_acquire
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+# define atomic_compare_exchange_weak_acquire(mem, expected, desired) \
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+ ({ typeof (*(expected)) __atg102_expected = *(expected); \
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+ *(expected) = \
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+ atomic_compare_and_exchange_val_acq ((mem), (desired), *(expected)); \
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+ *(expected) == __atg102_expected; })
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+# endif
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+# ifndef atomic_compare_exchange_weak_relaxed
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+/* XXX Fall back to CAS with acquire MO because archs do not define a weaker
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+ CAS. */
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+# define atomic_compare_exchange_weak_relaxed(mem, expected, desired) \
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+ atomic_compare_exchange_weak_acquire ((mem), (expected), (desired))
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+# endif
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+# ifndef atomic_compare_exchange_weak_release
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+# define atomic_compare_exchange_weak_release(mem, expected, desired) \
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+ ({ typeof (*(expected)) __atg103_expected = *(expected); \
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+ *(expected) = \
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+ atomic_compare_and_exchange_val_rel ((mem), (desired), *(expected)); \
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+ *(expected) == __atg103_expected; })
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+# endif
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+
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+# ifndef atomic_exchange_acquire
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+# define atomic_exchange_acquire(mem, val) \
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+ atomic_exchange_acq ((mem), (val))
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+# endif
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+# ifndef atomic_exchange_release
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+# define atomic_exchange_release(mem, val) \
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+ atomic_exchange_rel ((mem), (val))
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+# endif
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+
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+# ifndef atomic_fetch_add_acquire
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+# define atomic_fetch_add_acquire(mem, operand) \
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+ atomic_exchange_and_add_acq ((mem), (operand))
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+# endif
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+# ifndef atomic_fetch_add_relaxed
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+/* XXX Fall back to acquire MO because the MO semantics of
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+ atomic_exchange_and_add are not documented; the generic version falls back
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+ to atomic_exchange_and_add_acq if atomic_exchange_and_add is not defined,
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+ and vice versa. */
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+# define atomic_fetch_add_relaxed(mem, operand) \
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+ atomic_fetch_add_acquire ((mem), (operand))
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+# endif
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+# ifndef atomic_fetch_add_release
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+# define atomic_fetch_add_release(mem, operand) \
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+ atomic_exchange_and_add_rel ((mem), (operand))
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+# endif
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+# ifndef atomic_fetch_add_acq_rel
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+# define atomic_fetch_add_acq_rel(mem, operand) \
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+ ({ atomic_thread_fence_release (); \
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+ atomic_exchange_and_add_acq ((mem), (operand)); })
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+# endif
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+
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+/* XXX The default for atomic_and_val has acquire semantics, but this is not
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+ documented. */
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+# ifndef atomic_fetch_and_acquire
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+# define atomic_fetch_and_acquire(mem, operand) \
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+ atomic_and_val ((mem), (operand))
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+# endif
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+
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+/* XXX The default for atomic_or_val has acquire semantics, but this is not
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+ documented. */
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+# ifndef atomic_fetch_or_acquire
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+# define atomic_fetch_or_acquire(mem, operand) \
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+ atomic_or_val ((mem), (operand))
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+# endif
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+/* XXX Fall back to acquire MO because archs do not define a weaker
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+ atomic_or_val. */
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+# ifndef atomic_fetch_or_relaxed
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+# define atomic_fetch_or_relaxed(mem, operand) \
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+ atomic_fetch_or_acquire ((mem), (operand))
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+# endif
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+
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+#endif /* !USE_ATOMIC_COMPILER_BUILTINS */
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+
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#ifndef atomic_delay
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# define atomic_delay() do { /* nothing */ } while (0)
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