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Backporting the C11 atomic support will allow future algorithms
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to be more easily backported to RHEL7. This is initially backported
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to support the new semaphore algorithm which is now in RHEL7
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(rhbz#1027348).
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commit 1ea339b69725cb2f30b5a84cb7ca96111c9a637b
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Author: Torvald Riegel <triegel@redhat.com>
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Date: Sat Oct 18 01:02:59 2014 +0200
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Add arch-specific configuration for C11 atomics support.
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This sets __HAVE_64B_ATOMICS if provided. It also sets
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USE_ATOMIC_COMPILER_BUILTINS to true if the existing atomic ops use the
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__atomic* builtins (aarch64, mips partially) or if this has been
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tested (x86_64); otherwise, this is set to false so that C11 atomics will
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be based on the existing atomic operations.
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Index: glibc-2.17-c758a686/ports/sysdeps/aarch64/bits/atomic.h
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===================================================================
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--- glibc-2.17-c758a686.orig/ports/sysdeps/aarch64/bits/atomic.h
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+++ glibc-2.17-c758a686/ports/sysdeps/aarch64/bits/atomic.h
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@@ -36,6 +36,8 @@ typedef uintptr_t uatomicptr_t;
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typedef intmax_t atomic_max_t;
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typedef uintmax_t uatomic_max_t;
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+#define __HAVE_64B_ATOMICS 1
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+#define USE_ATOMIC_COMPILER_BUILTINS 1
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/* Compare and exchange.
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For all "bool" routines, we return FALSE if exchange succesful. */
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Index: glibc-2.17-c758a686/ports/sysdeps/alpha/bits/atomic.h
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===================================================================
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--- glibc-2.17-c758a686.orig/ports/sysdeps/alpha/bits/atomic.h
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+++ glibc-2.17-c758a686/ports/sysdeps/alpha/bits/atomic.h
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@@ -42,6 +42,9 @@ typedef uintptr_t uatomicptr_t;
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typedef intmax_t atomic_max_t;
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typedef uintmax_t uatomic_max_t;
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+#define __HAVE_64B_ATOMICS 1
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+#define USE_ATOMIC_COMPILER_BUILTINS 0
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+
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#ifdef UP
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# define __MB /* nothing */
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Index: glibc-2.17-c758a686/ports/sysdeps/arm/bits/atomic.h
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===================================================================
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--- glibc-2.17-c758a686.orig/ports/sysdeps/arm/bits/atomic.h
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+++ glibc-2.17-c758a686/ports/sysdeps/arm/bits/atomic.h
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@@ -33,6 +33,9 @@ typedef uintptr_t uatomicptr_t;
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typedef intmax_t atomic_max_t;
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typedef uintmax_t uatomic_max_t;
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+#define __HAVE_64B_ATOMICS 0
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+#define USE_ATOMIC_COMPILER_BUILTINS 0
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+
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void __arm_link_error (void);
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/* Use the atomic builtins provided by GCC in case the backend provides
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Index: glibc-2.17-c758a686/sysdeps/i386/i486/bits/atomic.h
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===================================================================
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--- glibc-2.17-c758a686.orig/sysdeps/i386/i486/bits/atomic.h
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+++ glibc-2.17-c758a686/sysdeps/i386/i486/bits/atomic.h
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@@ -54,6 +54,9 @@ typedef uintmax_t uatomic_max_t;
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# endif
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#endif
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+#define __HAVE_64B_ATOMICS 0
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+#define USE_ATOMIC_COMPILER_BUILTINS 0
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+
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#define atomic_compare_and_exchange_val_acq(mem, newval, oldval) \
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__sync_val_compare_and_swap (mem, oldval, newval)
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Index: glibc-2.17-c758a686/ports/sysdeps/ia64/bits/atomic.h
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===================================================================
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--- glibc-2.17-c758a686.orig/ports/sysdeps/ia64/bits/atomic.h
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+++ glibc-2.17-c758a686/ports/sysdeps/ia64/bits/atomic.h
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@@ -43,6 +43,9 @@ typedef uintptr_t uatomicptr_t;
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typedef intmax_t atomic_max_t;
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typedef uintmax_t uatomic_max_t;
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+#define __HAVE_64B_ATOMICS 1
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+#define USE_ATOMIC_COMPILER_BUILTINS 0
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+
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#define __arch_compare_and_exchange_bool_8_acq(mem, newval, oldval) \
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(abort (), 0)
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Index: glibc-2.17-c758a686/ports/sysdeps/m68k/coldfire/bits/atomic.h
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===================================================================
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--- glibc-2.17-c758a686.orig/ports/sysdeps/m68k/coldfire/bits/atomic.h
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+++ glibc-2.17-c758a686/ports/sysdeps/m68k/coldfire/bits/atomic.h
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@@ -49,6 +49,10 @@ typedef uintptr_t uatomicptr_t;
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typedef intmax_t atomic_max_t;
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typedef uintmax_t uatomic_max_t;
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+/* If we have just non-atomic operations, we can as well make them wide. */
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+#define __HAVE_64B_ATOMICS 1
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+#define USE_ATOMIC_COMPILER_BUILTINS 0
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+
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/* The only basic operation needed is compare and exchange. */
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#define atomic_compare_and_exchange_val_acq(mem, newval, oldval) \
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({ __typeof (mem) __gmemp = (mem); \
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Index: glibc-2.17-c758a686/ports/sysdeps/m68k/m680x0/m68020/bits/atomic.h
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===================================================================
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--- glibc-2.17-c758a686.orig/ports/sysdeps/m68k/m680x0/m68020/bits/atomic.h
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+++ glibc-2.17-c758a686/ports/sysdeps/m68k/m680x0/m68020/bits/atomic.h
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@@ -44,6 +44,9 @@ typedef uintptr_t uatomicptr_t;
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typedef intmax_t atomic_max_t;
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typedef uintmax_t uatomic_max_t;
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+#define __HAVE_64B_ATOMICS 1
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+#define USE_ATOMIC_COMPILER_BUILTINS 0
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+
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#define __arch_compare_and_exchange_val_8_acq(mem, newval, oldval) \
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({ __typeof (*(mem)) __ret; \
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__asm __volatile ("cas%.b %0,%2,%1" \
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Index: glibc-2.17-c758a686/ports/sysdeps/mips/bits/atomic.h
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===================================================================
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--- glibc-2.17-c758a686.orig/ports/sysdeps/mips/bits/atomic.h
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+++ glibc-2.17-c758a686/ports/sysdeps/mips/bits/atomic.h
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@@ -43,6 +43,12 @@ typedef uintmax_t uatomic_max_t;
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#define MIPS_PUSH_MIPS2
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#endif
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+#if _MIPS_SIM == _ABIO32
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+#define __HAVE_64B_ATOMICS 0
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+#else
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+#define __HAVE_64B_ATOMICS 1
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+#endif
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+
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/* See the comments in <sys/asm.h> about the use of the sync instruction. */
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#ifndef MIPS_SYNC
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# define MIPS_SYNC sync
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@@ -82,6 +88,8 @@ typedef uintmax_t uatomic_max_t;
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/* The __atomic_* builtins are available in GCC 4.7 and later, but MIPS
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support for their efficient implementation was added only in GCC 4.8. */
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+#define USE_ATOMIC_COMPILER_BUILTINS 1
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+
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/* Compare and exchange.
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For all "bool" routines, we return FALSE if exchange succesful. */
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@@ -204,6 +212,8 @@ typedef uintmax_t uatomic_max_t;
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/* This implementation using inline assembly will be removed once glibc
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requires GCC 4.8 or later to build. */
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+#define USE_ATOMIC_COMPILER_BUILTINS 0
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+
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/* Compare and exchange. For all of the "xxx" routines, we expect a
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"__prev" and a "__cmp" variable to be provided by the enclosing scope,
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in which values are returned. */
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Index: glibc-2.17-c758a686/sysdeps/powerpc/powerpc32/bits/atomic.h
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===================================================================
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--- glibc-2.17-c758a686.orig/sysdeps/powerpc/powerpc32/bits/atomic.h
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+++ glibc-2.17-c758a686/sysdeps/powerpc/powerpc32/bits/atomic.h
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@@ -33,6 +33,9 @@
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# define MUTEX_HINT_REL
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#endif
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+#define __HAVE_64B_ATOMICS 0
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+#define USE_ATOMIC_COMPILER_BUILTINS 0
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+
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/*
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* The 32-bit exchange_bool is different on powerpc64 because the subf
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* does signed 64-bit arthmatic while the lwarx is 32-bit unsigned
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Index: glibc-2.17-c758a686/sysdeps/powerpc/powerpc64/bits/atomic.h
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===================================================================
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--- glibc-2.17-c758a686.orig/sysdeps/powerpc/powerpc64/bits/atomic.h
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+++ glibc-2.17-c758a686/sysdeps/powerpc/powerpc64/bits/atomic.h
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@@ -33,6 +33,9 @@
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# define MUTEX_HINT_REL
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#endif
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+#define __HAVE_64B_ATOMICS 1
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+#define USE_ATOMIC_COMPILER_BUILTINS 0
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+
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/* The 32-bit exchange_bool is different on powerpc64 because the subf
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does signed 64-bit arthmatic while the lwarx is 32-bit unsigned
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(a load word and zero (high 32) form) load.
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Index: glibc-2.17-c758a686/sysdeps/s390/bits/atomic.h
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===================================================================
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--- glibc-2.17-c758a686.orig/sysdeps/s390/bits/atomic.h
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+++ glibc-2.17-c758a686/sysdeps/s390/bits/atomic.h
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@@ -43,6 +43,8 @@ typedef uintptr_t uatomicptr_t;
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typedef intmax_t atomic_max_t;
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typedef uintmax_t uatomic_max_t;
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+#define USE_ATOMIC_COMPILER_BUILTINS 0
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+
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#define __arch_compare_and_exchange_val_8_acq(mem, newval, oldval) \
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(abort (), (__typeof (*mem)) 0)
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@@ -59,6 +61,7 @@ typedef uintmax_t uatomic_max_t;
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__archold; })
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#ifdef __s390x__
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+# define __HAVE_64B_ATOMICS 1
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# define __arch_compare_and_exchange_val_64_acq(mem, newval, oldval) \
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({ __typeof (mem) __archmem = (mem); \
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__typeof (*mem) __archold = (oldval); \
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00db10 |
@@ -67,6 +70,7 @@ typedef uintmax_t uatomic_max_t;
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: "d" ((long) (newval)), "m" (*__archmem) : "cc", "memory" ); \
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__archold; })
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#else
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+# define __HAVE_64B_ATOMICS 0
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/* For 31 bit we do not really need 64-bit compare-and-exchange. We can
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implement them by use of the csd instruction. The straightforward
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implementation causes warnings so we skip the definition for now. */
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00db10 |
Index: glibc-2.17-c758a686/sysdeps/sparc/sparc32/bits/atomic.h
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===================================================================
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00db10 |
--- glibc-2.17-c758a686.orig/sysdeps/sparc/sparc32/bits/atomic.h
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00db10 |
+++ glibc-2.17-c758a686/sysdeps/sparc/sparc32/bits/atomic.h
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@@ -47,6 +47,9 @@ typedef uintptr_t uatomicptr_t;
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typedef intmax_t atomic_max_t;
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typedef uintmax_t uatomic_max_t;
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+#define __HAVE_64B_ATOMICS 0
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+#define USE_ATOMIC_COMPILER_BUILTINS 0
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+
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|
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/* We have no compare and swap, just test and set.
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00db10 |
The following implementation contends on 64 global locks
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00db10 |
Index: glibc-2.17-c758a686/sysdeps/sparc/sparc32/sparcv9/bits/atomic.h
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===================================================================
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00db10 |
--- glibc-2.17-c758a686.orig/sysdeps/sparc/sparc32/sparcv9/bits/atomic.h
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00db10 |
+++ glibc-2.17-c758a686/sysdeps/sparc/sparc32/sparcv9/bits/atomic.h
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00db10 |
@@ -44,6 +44,9 @@ typedef uintptr_t uatomicptr_t;
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typedef intmax_t atomic_max_t;
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00db10 |
typedef uintmax_t uatomic_max_t;
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00db10 |
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+#define __HAVE_64B_ATOMICS 0
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+#define USE_ATOMIC_COMPILER_BUILTINS 0
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00db10 |
+
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00db10 |
|
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#define __arch_compare_and_exchange_val_8_acq(mem, newval, oldval) \
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(abort (), (__typeof (*mem)) 0)
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|
|
00db10 |
Index: glibc-2.17-c758a686/sysdeps/sparc/sparc64/bits/atomic.h
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===================================================================
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|
00db10 |
--- glibc-2.17-c758a686.orig/sysdeps/sparc/sparc64/bits/atomic.h
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00db10 |
+++ glibc-2.17-c758a686/sysdeps/sparc/sparc64/bits/atomic.h
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00db10 |
@@ -44,6 +44,9 @@ typedef uintptr_t uatomicptr_t;
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00db10 |
typedef intmax_t atomic_max_t;
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00db10 |
typedef uintmax_t uatomic_max_t;
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00db10 |
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+#define __HAVE_64B_ATOMICS 1
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00db10 |
+#define USE_ATOMIC_COMPILER_BUILTINS 0
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00db10 |
+
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00db10 |
|
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#define __arch_compare_and_exchange_val_8_acq(mem, newval, oldval) \
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00db10 |
(abort (), (__typeof (*mem)) 0)
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|
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00db10 |
Index: glibc-2.17-c758a686/ports/sysdeps/unix/sysv/linux/hppa/bits/atomic.h
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===================================================================
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00db10 |
--- glibc-2.17-c758a686.orig/ports/sysdeps/unix/sysv/linux/hppa/bits/atomic.h
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00db10 |
+++ glibc-2.17-c758a686/ports/sysdeps/unix/sysv/linux/hppa/bits/atomic.h
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00db10 |
@@ -44,6 +44,9 @@ typedef uintptr_t uatomicptr_t;
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00db10 |
typedef intmax_t atomic_max_t;
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00db10 |
typedef uintmax_t uatomic_max_t;
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00db10 |
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+#define __HAVE_64B_ATOMICS 0
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00db10 |
+#define USE_ATOMIC_COMPILER_BUILTINS 0
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+
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/* prev = *addr;
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00db10 |
if (prev == old)
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00db10 |
*addr = new;
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00db10 |
Index: glibc-2.17-c758a686/sysdeps/x86_64/bits/atomic.h
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===================================================================
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--- glibc-2.17-c758a686.orig/sysdeps/x86_64/bits/atomic.h
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+++ glibc-2.17-c758a686/sysdeps/x86_64/bits/atomic.h
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@@ -55,6 +55,12 @@ typedef uintmax_t uatomic_max_t;
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# endif
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#endif
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+#define __HAVE_64B_ATOMICS 1
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+#if __GNUC_PREREQ (4, 7)
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+#define USE_ATOMIC_COMPILER_BUILTINS 1
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+#else
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+#define USE_ATOMIC_COMPILER_BUILTINS 0
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+#endif
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#define atomic_compare_and_exchange_val_acq(mem, newval, oldval) \
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__sync_val_compare_and_swap (mem, oldval, newval)
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