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# commit be1e5d311342e08ae1f8013342df27b7ded2c156
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# Author: Anton Blanchard <anton@au1.ibm.com>
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# Date: Sat Aug 17 18:34:40 2013 +0930
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#
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# PowerPC LE setjmp/longjmp
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# http://sourceware.org/ml/libc-alpha/2013-08/msg00089.html
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#
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# Little-endian fixes for setjmp/longjmp. When writing these I noticed
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# the setjmp code corrupts the non volatile VMX registers when using an
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# unaligned buffer. Anton fixed this, and also simplified it quite a
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# bit.
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#
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# The current code uses boilerplate for the case where we want to store
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# 16 bytes to an unaligned address. For that we have to do a
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# read/modify/write of two aligned 16 byte quantities. In our case we
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# are storing a bunch of back to back data (consective VMX registers),
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# and only the start and end of the region need the read/modify/write.
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#
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# [BZ #15723]
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# * sysdeps/powerpc/jmpbuf-offsets.h: Comment fix.
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# * sysdeps/powerpc/powerpc32/fpu/__longjmp-common.S: Correct
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# _dl_hwcap access for little-endian.
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# * sysdeps/powerpc/powerpc32/fpu/setjmp-common.S: Likewise. Don't
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# destroy vmx regs when saving unaligned.
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# * sysdeps/powerpc/powerpc64/__longjmp-common.S: Correct CR load.
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# * sysdeps/powerpc/powerpc64/setjmp-common.S: Likewise CR save. Don't
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# destroy vmx regs when saving unaligned.
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#
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diff -urN glibc-2.17-c758a686/sysdeps/powerpc/jmpbuf-offsets.h glibc-2.17-c758a686/sysdeps/powerpc/jmpbuf-offsets.h
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--- glibc-2.17-c758a686/sysdeps/powerpc/jmpbuf-offsets.h 2014-05-27 22:55:23.000000000 -0500
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+++ glibc-2.17-c758a686/sysdeps/powerpc/jmpbuf-offsets.h 2014-05-27 22:55:27.000000000 -0500
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@@ -21,12 +21,10 @@
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#define JB_LR 2 /* The address we will return to */
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#if __WORDSIZE == 64
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# define JB_GPRS 3 /* GPRs 14 through 31 are saved, 18*2 words total. */
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-# define JB_CR 21 /* Condition code registers with the VRSAVE at */
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- /* offset 172 (low half of the double word. */
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+# define JB_CR 21 /* Shared dword with VRSAVE. CR word at offset 172. */
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# define JB_FPRS 22 /* FPRs 14 through 31 are saved, 18*2 words total. */
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# define JB_SIZE (64 * 8) /* As per PPC64-VMX ABI. */
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-# define JB_VRSAVE 21 /* VRSAVE shares a double word with the CR at offset */
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- /* 168 (high half of the double word). */
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+# define JB_VRSAVE 21 /* Shared dword with CR. VRSAVE word at offset 168. */
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# define JB_VRS 40 /* VRs 20 through 31 are saved, 12*4 words total. */
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#else
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# define JB_GPRS 3 /* GPRs 14 through 31 are saved, 18 in total. */
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diff -urN glibc-2.17-c758a686/sysdeps/powerpc/powerpc32/fpu/__longjmp-common.S glibc-2.17-c758a686/sysdeps/powerpc/powerpc32/fpu/__longjmp-common.S
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--- glibc-2.17-c758a686/sysdeps/powerpc/powerpc32/fpu/__longjmp-common.S 2014-05-27 22:55:23.000000000 -0500
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+++ glibc-2.17-c758a686/sysdeps/powerpc/powerpc32/fpu/__longjmp-common.S 2014-05-27 22:55:27.000000000 -0500
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@@ -46,16 +46,16 @@
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# endif
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mtlr r6
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cfi_same_value (lr)
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- lwz r5,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET+4(r5)
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+ lwz r5,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET+LOWORD(r5)
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# else
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lwz r5,_dl_hwcap@got(r5)
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mtlr r6
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cfi_same_value (lr)
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- lwz r5,4(r5)
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+ lwz r5,LOWORD(r5)
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# endif
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# else
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- lis r5,(_dl_hwcap+4)@ha
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- lwz r5,(_dl_hwcap+4)@l(r5)
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+ lis r5,(_dl_hwcap+LOWORD)@ha
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+ lwz r5,(_dl_hwcap+LOWORD)@l(r5)
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# endif
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andis. r5,r5,(PPC_FEATURE_HAS_ALTIVEC >> 16)
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beq L(no_vmx)
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diff -urN glibc-2.17-c758a686/sysdeps/powerpc/powerpc32/fpu/setjmp-common.S glibc-2.17-c758a686/sysdeps/powerpc/powerpc32/fpu/setjmp-common.S
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--- glibc-2.17-c758a686/sysdeps/powerpc/powerpc32/fpu/setjmp-common.S 2014-05-27 22:55:23.000000000 -0500
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+++ glibc-2.17-c758a686/sysdeps/powerpc/powerpc32/fpu/setjmp-common.S 2014-05-27 22:55:27.000000000 -0500
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@@ -97,14 +97,14 @@
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# else
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lwz r5,_rtld_global_ro@got(r5)
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# endif
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- lwz r5,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET+4(r5)
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+ lwz r5,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET+LOWORD(r5)
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# else
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lwz r5,_dl_hwcap@got(r5)
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- lwz r5,4(r5)
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+ lwz r5,LOWORD(r5)
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# endif
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# else
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- lis r6,(_dl_hwcap+4)@ha
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- lwz r5,(_dl_hwcap+4)@l(r6)
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+ lis r6,(_dl_hwcap+LOWORD)@ha
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+ lwz r5,(_dl_hwcap+LOWORD)@l(r6)
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# endif
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andis. r5,r5,(PPC_FEATURE_HAS_ALTIVEC >> 16)
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beq L(no_vmx)
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@@ -114,44 +114,43 @@
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stw r0,((JB_VRSAVE)*4)(3)
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addi r6,r5,16
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beq+ L(aligned_save_vmx)
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+
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lvsr v0,0,r5
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- vspltisb v1,-1 /* set v1 to all 1's */
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- vspltisb v2,0 /* set v2 to all 0's */
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- vperm v3,v2,v1,v0 /* v3 contains shift mask with num all 1 bytes on left = misalignment */
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-
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-
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- /* Special case for v20 we need to preserve what is in save area below v20 before obliterating it */
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- lvx v5,0,r5
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- vperm v20,v20,v20,v0
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- vsel v5,v5,v20,v3
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- vsel v20,v20,v2,v3
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- stvx v5,0,r5
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-
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-#define save_2vmx_partial(savevr,prev_savevr,hivr,shiftvr,maskvr,savegpr,addgpr) \
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- addi addgpr,addgpr,32; \
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- vperm savevr,savevr,savevr,shiftvr; \
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- vsel hivr,prev_savevr,savevr,maskvr; \
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- stvx hivr,0,savegpr;
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-
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- save_2vmx_partial(v21,v20,v5,v0,v3,r6,r5)
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- save_2vmx_partial(v22,v21,v5,v0,v3,r5,r6)
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- save_2vmx_partial(v23,v22,v5,v0,v3,r6,r5)
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- save_2vmx_partial(v24,v23,v5,v0,v3,r5,r6)
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- save_2vmx_partial(v25,v24,v5,v0,v3,r6,r5)
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- save_2vmx_partial(v26,v25,v5,v0,v3,r5,r6)
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- save_2vmx_partial(v27,v26,v5,v0,v3,r6,r5)
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- save_2vmx_partial(v28,v27,v5,v0,v3,r5,r6)
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- save_2vmx_partial(v29,v28,v5,v0,v3,r6,r5)
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- save_2vmx_partial(v30,v29,v5,v0,v3,r5,r6)
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-
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- /* Special case for r31 we need to preserve what is in save area above v31 before obliterating it */
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- addi r5,r5,32
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- vperm v31,v31,v31,v0
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- lvx v4,0,r5
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- vsel v5,v30,v31,v3
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- stvx v5,0,r6
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- vsel v4,v31,v4,v3
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- stvx v4,0,r5
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+ lvsl v1,0,r5
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+ addi r6,r5,-16
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+
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+# define save_misaligned_vmx(savevr,prevvr,shiftvr,tmpvr,savegpr,addgpr) \
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+ addi addgpr,addgpr,32; \
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+ vperm tmpvr,prevvr,savevr,shiftvr; \
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+ stvx tmpvr,0,savegpr
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+
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+ /*
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+ * We have to be careful not to corrupt the data below v20 and
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+ * above v31. To keep things simple we just rotate both ends in
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+ * the opposite direction to our main permute so we can use
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+ * the common macro.
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+ */
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+
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+ /* load and rotate data below v20 */
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+ lvx v2,0,r5
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+ vperm v2,v2,v2,v1
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+ save_misaligned_vmx(v20,v2,v0,v3,r5,r6)
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+ save_misaligned_vmx(v21,v20,v0,v3,r6,r5)
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+ save_misaligned_vmx(v22,v21,v0,v3,r5,r6)
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+ save_misaligned_vmx(v23,v22,v0,v3,r6,r5)
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+ save_misaligned_vmx(v24,v23,v0,v3,r5,r6)
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+ save_misaligned_vmx(v25,v24,v0,v3,r6,r5)
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+ save_misaligned_vmx(v26,v25,v0,v3,r5,r6)
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+ save_misaligned_vmx(v27,v26,v0,v3,r6,r5)
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+ save_misaligned_vmx(v28,v27,v0,v3,r5,r6)
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+ save_misaligned_vmx(v29,v28,v0,v3,r6,r5)
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+ save_misaligned_vmx(v30,v29,v0,v3,r5,r6)
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+ save_misaligned_vmx(v31,v30,v0,v3,r6,r5)
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+ /* load and rotate data above v31 */
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+ lvx v2,0,r6
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+ vperm v2,v2,v2,v1
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+ save_misaligned_vmx(v2,v31,v0,v3,r5,r6)
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+
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b L(no_vmx)
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L(aligned_save_vmx):
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diff -urN glibc-2.17-c758a686/sysdeps/powerpc/powerpc64/__longjmp-common.S glibc-2.17-c758a686/sysdeps/powerpc/powerpc64/__longjmp-common.S
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--- glibc-2.17-c758a686/sysdeps/powerpc/powerpc64/__longjmp-common.S 2014-05-27 22:55:23.000000000 -0500
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+++ glibc-2.17-c758a686/sysdeps/powerpc/powerpc64/__longjmp-common.S 2014-05-27 22:55:27.000000000 -0500
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@@ -60,7 +60,7 @@
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beq L(no_vmx)
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la r5,((JB_VRS)*8)(3)
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andi. r6,r5,0xf
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- lwz r0,((JB_VRSAVE)*8)(3)
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+ lwz r0,((JB_VRSAVE)*8)(3) /* 32-bit VRSAVE. */
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mtspr VRSAVE,r0
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beq+ L(aligned_restore_vmx)
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addi r6,r5,16
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@@ -156,7 +156,7 @@
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lfd fp21,((JB_FPRS+7)*8)(r3)
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ld r22,((JB_GPRS+8)*8)(r3)
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lfd fp22,((JB_FPRS+8)*8)(r3)
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- ld r0,(JB_CR*8)(r3)
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+ lwz r0,((JB_CR*8)+4)(r3) /* 32-bit CR. */
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ld r23,((JB_GPRS+9)*8)(r3)
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lfd fp23,((JB_FPRS+9)*8)(r3)
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ld r24,((JB_GPRS+10)*8)(r3)
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diff -urN glibc-2.17-c758a686/sysdeps/powerpc/powerpc64/setjmp-common.S glibc-2.17-c758a686/sysdeps/powerpc/powerpc64/setjmp-common.S
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--- glibc-2.17-c758a686/sysdeps/powerpc/powerpc64/setjmp-common.S 2014-05-27 22:55:23.000000000 -0500
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+++ glibc-2.17-c758a686/sysdeps/powerpc/powerpc64/setjmp-common.S 2014-05-27 22:55:27.000000000 -0500
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@@ -98,7 +98,7 @@
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mfcr r0
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std r16,((JB_GPRS+2)*8)(3)
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stfd fp16,((JB_FPRS+2)*8)(3)
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- std r0,(JB_CR*8)(3)
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+ stw r0,((JB_CR*8)+4)(3) /* 32-bit CR. */
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std r17,((JB_GPRS+3)*8)(3)
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stfd fp17,((JB_FPRS+3)*8)(3)
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std r18,((JB_GPRS+4)*8)(3)
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@@ -142,50 +142,46 @@
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la r5,((JB_VRS)*8)(3)
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andi. r6,r5,0xf
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mfspr r0,VRSAVE
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- stw r0,((JB_VRSAVE)*8)(3)
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+ stw r0,((JB_VRSAVE)*8)(3) /* 32-bit VRSAVE. */
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addi r6,r5,16
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beq+ L(aligned_save_vmx)
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+
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lvsr v0,0,r5
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- vspltisb v1,-1 /* set v1 to all 1's */
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- vspltisb v2,0 /* set v2 to all 0's */
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- vperm v3,v2,v1,v0 /* v3 contains shift mask with num all 1 bytes
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- on left = misalignment */
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-
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-
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- /* Special case for v20 we need to preserve what is in save area
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- below v20 before obliterating it */
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- lvx v5,0,r5
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- vperm v20,v20,v20,v0
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- vsel v5,v5,v20,v3
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- vsel v20,v20,v2,v3
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- stvx v5,0,r5
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-
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-# define save_2vmx_partial(savevr,prev_savevr,hivr,shiftvr,maskvr,savegpr,addgpr) \
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- addi addgpr,addgpr,32; \
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- vperm savevr,savevr,savevr,shiftvr; \
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- vsel hivr,prev_savevr,savevr,maskvr; \
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- stvx hivr,0,savegpr;
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-
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- save_2vmx_partial(v21,v20,v5,v0,v3,r6,r5)
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ce426f |
- save_2vmx_partial(v22,v21,v5,v0,v3,r5,r6)
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ce426f |
- save_2vmx_partial(v23,v22,v5,v0,v3,r6,r5)
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ce426f |
- save_2vmx_partial(v24,v23,v5,v0,v3,r5,r6)
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ce426f |
- save_2vmx_partial(v25,v24,v5,v0,v3,r6,r5)
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ce426f |
- save_2vmx_partial(v26,v25,v5,v0,v3,r5,r6)
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ce426f |
- save_2vmx_partial(v27,v26,v5,v0,v3,r6,r5)
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ce426f |
- save_2vmx_partial(v28,v27,v5,v0,v3,r5,r6)
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ce426f |
- save_2vmx_partial(v29,v28,v5,v0,v3,r6,r5)
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ce426f |
- save_2vmx_partial(v30,v29,v5,v0,v3,r5,r6)
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ce426f |
-
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ce426f |
- /* Special case for r31 we need to preserve what is in save area
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ce426f |
- above v31 before obliterating it */
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ce426f |
- addi r5,r5,32
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ce426f |
- vperm v31,v31,v31,v0
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ce426f |
- lvx v4,0,r5
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ce426f |
- vsel v5,v30,v31,v3
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ce426f |
- stvx v5,0,r6
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ce426f |
- vsel v4,v31,v4,v3
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ce426f |
- stvx v4,0,r5
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ce426f |
+ lvsl v1,0,r5
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ce426f |
+ addi r6,r5,-16
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ce426f |
+
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ce426f |
+# define save_misaligned_vmx(savevr,prevvr,shiftvr,tmpvr,savegpr,addgpr) \
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ce426f |
+ addi addgpr,addgpr,32; \
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ce426f |
+ vperm tmpvr,prevvr,savevr,shiftvr; \
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ce426f |
+ stvx tmpvr,0,savegpr
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ce426f |
+
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ce426f |
+ /*
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ce426f |
+ * We have to be careful not to corrupt the data below v20 and
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ce426f |
+ * above v31. To keep things simple we just rotate both ends in
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ce426f |
+ * the opposite direction to our main permute so we can use
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ce426f |
+ * the common macro.
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ce426f |
+ */
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ce426f |
+
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ce426f |
+ /* load and rotate data below v20 */
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ce426f |
+ lvx v2,0,r5
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ce426f |
+ vperm v2,v2,v2,v1
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ce426f |
+ save_misaligned_vmx(v20,v2,v0,v3,r5,r6)
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ce426f |
+ save_misaligned_vmx(v21,v20,v0,v3,r6,r5)
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ce426f |
+ save_misaligned_vmx(v22,v21,v0,v3,r5,r6)
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ce426f |
+ save_misaligned_vmx(v23,v22,v0,v3,r6,r5)
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ce426f |
+ save_misaligned_vmx(v24,v23,v0,v3,r5,r6)
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ce426f |
+ save_misaligned_vmx(v25,v24,v0,v3,r6,r5)
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ce426f |
+ save_misaligned_vmx(v26,v25,v0,v3,r5,r6)
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ce426f |
+ save_misaligned_vmx(v27,v26,v0,v3,r6,r5)
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ce426f |
+ save_misaligned_vmx(v28,v27,v0,v3,r5,r6)
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ce426f |
+ save_misaligned_vmx(v29,v28,v0,v3,r6,r5)
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ce426f |
+ save_misaligned_vmx(v30,v29,v0,v3,r5,r6)
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ce426f |
+ save_misaligned_vmx(v31,v30,v0,v3,r6,r5)
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ce426f |
+ /* load and rotate data above v31 */
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ce426f |
+ lvx v2,0,r6
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ce426f |
+ vperm v2,v2,v2,v1
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ce426f |
+ save_misaligned_vmx(v2,v31,v0,v3,r5,r6)
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ce426f |
+
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ce426f |
b L(no_vmx)
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ce426f |
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ce426f |
L(aligned_save_vmx):
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