diff --git a/SOURCES/gdb-bare-DW_TAG_lexical_block-2of2.patch b/SOURCES/gdb-bare-DW_TAG_lexical_block-2of2.patch
index ef9a7ba..30fad64 100644
--- a/SOURCES/gdb-bare-DW_TAG_lexical_block-2of2.patch
+++ b/SOURCES/gdb-bare-DW_TAG_lexical_block-2of2.patch
@@ -278,8 +278,8 @@ Index: gdb-7.6.1/gdb/dwarf2read.c
+ .4byte .Labbrev1_begin /* Abbrevs */
+ .byte 4 /* Pointer size */
+ .uleb128 2 /* Abbrev (DW_TAG_compile_unit) */
-+ .4byte main
-+ .4byte main+0x10000
++ .4byte main_label
++ .4byte main_label+0x10000
+.Llabel1:
+ .uleb128 3 /* Abbrev (DW_TAG_base_type) */
+ .sleb128 4
@@ -288,8 +288,8 @@ Index: gdb-7.6.1/gdb/dwarf2read.c
+ .uleb128 4 /* Abbrev (DW_TAG_subprogram) */
+ .ascii "main\0"
+ .byte 1
-+ .4byte main
-+ .4byte main+0x10000
++ .4byte main_label
++ .4byte main_label+0x10000
+ .uleb128 5 /* Abbrev (DW_TAG_lexical_block) */
+ .uleb128 6 /* Abbrev (DW_TAG_variable) */
+ .ascii "testvar\0"
@@ -359,3 +359,13 @@ Index: gdb-7.6.1/gdb/dwarf2read.c
+ .byte 0x0 /* Terminator */
+ .byte 0x0 /* Terminator */
+ .byte 0x0 /* Terminator */
+diff -dup -rup gdb-7.6.1/gdb/testsuite/gdb.dwarf2/main.c gdb-7.6.1-orig/gdb/testsuite/gdb.dwarf2/main.c
+--- gdb-7.6.1/gdb/testsuite/gdb.dwarf2/main.c 2013-01-01 07:41:22.000000000 +0100
++++ gdb-7.6.1-orig/gdb/testsuite/gdb.dwarf2/main.c 2017-03-08 22:20:21.085438961 +0100
+@@ -20,5 +20,6 @@
+ int
+ main()
+ {
++ asm ("main_label: .globl main_label");
+ return 0;
+ }
diff --git a/SOURCES/gdb-ppc-power7-test.patch b/SOURCES/gdb-ppc-power7-test.patch
index 4d4772a..c97dab9 100644
--- a/SOURCES/gdb-ppc-power7-test.patch
+++ b/SOURCES/gdb-ppc-power7-test.patch
@@ -1,6 +1,6 @@
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/powerpc-power7.exp
-@@ -0,0 +1,182 @@
+@@ -0,0 +1,178 @@
+# Copyright 2009 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
@@ -76,17 +76,13 @@
+# [PATCH] Remove support for POWER7 VSX load/store with update instructions
+# http://sourceware.org/ml/binutils/2009-09/msg00680.html
+# http://sourceware.org/ml/binutils-cvs/2009-09/msg00331.html
-+# lxvd2ux vs3,r4,r5
-+func_check 0x4 ".long 0x7c642ed8"
++func_check 0x4 "lxvb16x vs3,r4,r5"
+func_check 0x8 "lxvd2x vs43,r4,r5"
-+# lxvd2ux vs43,r4,r5
-+func_check 0xc ".long 0x7d642ed9"
++func_check 0xc "lxvb16x vs43,r4,r5"
+func_check 0x10 "stxvd2x vs3,r4,r5"
-+# stxvd2ux vs3,r4,r5
-+func_check 0x14 ".long 0x7c642fd8"
++func_check 0x14 "stxvb16x vs3,r4,r5"
+func_check 0x18 "stxvd2x vs43,r4,r5"
-+# stxvd2ux vs43,r4,r5
-+func_check 0x1c ".long 0x7d642fd9"
++func_check 0x1c "stxvb16x vs43,r4,r5"
+func_check 0x20 "xxmrghd vs3,vs4,vs5"
+func_check 0x24 "xxmrghd vs43,vs44,vs45"
+func_check 0x28 "xxmrgld vs3,vs4,vs5"
diff --git a/SOURCES/gdb-rhbz1125820-ppc64le-enablement-08of37.patch b/SOURCES/gdb-rhbz1125820-ppc64le-enablement-08of37.patch
index 9e4c14a..042cdc7 100644
--- a/SOURCES/gdb-rhbz1125820-ppc64le-enablement-08of37.patch
+++ b/SOURCES/gdb-rhbz1125820-ppc64le-enablement-08of37.patch
@@ -271,13 +271,11 @@ Index: gdb-7.6.1/bfd/elf64-ppc.c
rela.r_addend = (h->root.u.def.value
+ h->root.u.def.section->output_offset
+ h->root.u.def.section->output_section->vma
-Index: gdb-7.6.1/include/elf/ppc64.h
-===================================================================
---- gdb-7.6.1.orig/include/elf/ppc64.h
-+++ gdb-7.6.1/include/elf/ppc64.h
-@@ -164,6 +164,13 @@ END_RELOC_NUMBERS (R_PPC64_max)
- #define IS_PPC64_TLS_RELOC(R) \
- ((R) >= R_PPC64_TLS && (R) <= R_PPC64_DTPREL16_HIGHESTA)
+--- a/include/elf/ppc64.h
++++ b/include/elf/ppc64.h
+@@ -173,6 +173,13 @@ END_RELOC_NUMBERS (R_PPC64_max)
+ (((R) >= R_PPC64_TLS && (R) <= R_PPC64_DTPREL16_HIGHESTA) \
+ || ((R) >= R_PPC64_TPREL16_HIGH && (R) <= R_PPC64_DTPREL16_HIGHA))
+
+/* e_flags bits specifying ABI.
diff --git a/SOURCES/gdb-rhbz1261564-aarch64-hw-watchpoint-test.patch b/SOURCES/gdb-rhbz1261564-aarch64-hw-watchpoint-test.patch
index 446ac6b..f2590d3 100644
--- a/SOURCES/gdb-rhbz1261564-aarch64-hw-watchpoint-test.patch
+++ b/SOURCES/gdb-rhbz1261564-aarch64-hw-watchpoint-test.patch
@@ -2,7 +2,7 @@ Index: gdb-7.6.1/gdb/testsuite/gdb.base/rhbz1261564-aarch64-watchpoint.exp
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ gdb-7.6.1/gdb/testsuite/gdb.base/rhbz1261564-aarch64-watchpoint.exp 2016-03-10 22:31:31.152094080 +0100
-@@ -0,0 +1,43 @@
+@@ -0,0 +1,53 @@
+# Copyright (C) 2016 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
@@ -24,7 +24,13 @@ Index: gdb-7.6.1/gdb/testsuite/gdb.base/rhbz1261564-aarch64-watchpoint.exp
+
+if { ! [ runto main ] } then { return 0 }
+
-+gdb_test "rwatch aligned.var4" "Hardware read watchpoint \[0-9\]+: aligned.var4"
++set test "rwatch aligned.var4"
++if [istarget "s390*-*-*"] {
++ gdb_test $test {Target does not support this type of hardware watchpoint\.}
++ untested "s390* does not support hw read watchpoint"
++ return
++}
++gdb_test $test "Hardware read watchpoint \[0-9\]+: aligned.var4"
+
+proc checkvar { address } {
+ global gdb_prompt
@@ -45,6 +51,10 @@ Index: gdb-7.6.1/gdb/testsuite/gdb.base/rhbz1261564-aarch64-watchpoint.exp
+if ![checkvar "4"] { return }
+if ![checkvar "8"] { return }
+
++# Assumes: PPC_PTRACE_GETHWDBGINFO::data_bp_alignment == 8
++# 'lwz' does read only 4 bytes but the hw watchpoint is 8 bytes wide.
++setup_xfail "powerpc*-*-*"
++
+gdb_continue_to_end
Index: gdb-7.6.1/gdb/testsuite/gdb.base/rhbz1261564-aarch64-watchpoint.c
===================================================================
diff --git a/SOURCES/gdb-rhbz1320945-float128-1of9.patch b/SOURCES/gdb-rhbz1320945-float128-1of9.patch
new file mode 100644
index 0000000..1690126
--- /dev/null
+++ b/SOURCES/gdb-rhbz1320945-float128-1of9.patch
@@ -0,0 +1,41 @@
+commit 5f3bceb68dd211be977eb61d5f1ea68e7de51b7a
+Author: Ulrich Weigand <ulrich.weigand@de.ibm.com>
+Date: Tue Sep 6 17:22:51 2016 +0200
+
+ Fix typo in ada_language_arch_info
+
+ This fixes a bug introduced by a wrong replacement here:
+ https://sourceware.org/ml/gdb-patches/2007-06/msg00196.html
+
+ The Ada "long_long_float" type is supposed to correspond to the
+ platform ABI long double type, not double.
+
+ gdb/ChangeLog:
+
+ * ada-lang.c (ada_language_arch_info): Use gdbarch_long_double_bit
+ instead of gdbarch_double_bit for "long_long_float".
+
+ Signed-off-by: Ulrich Weigand <ulrich.weigand@de.ibm.com>
+
+### a/gdb/ChangeLog
+### b/gdb/ChangeLog
+## -1,3 +1,8 @@
++2016-09-05 Ulrich Weigand <uweigand@de.ibm.com>
++
++ * ada-lang.c (ada_language_arch_info): Use gdbarch_long_double_bit
++ instead of gdbarch_double_bit for "long_long_float".
++
+ 2016-09-05 Pedro Alves <palves@redhat.com>
+
+ * NEWS: Mention that a C++ compiler is now required.
+--- a/gdb/ada-lang.c
++++ b/gdb/ada-lang.c
+@@ -14012,7 +14012,7 @@ ada_language_arch_info (struct gdbarch *gdbarch,
+ = arch_integer_type (gdbarch, gdbarch_long_long_bit (gdbarch),
+ 0, "long_long_integer");
+ lai->primitive_type_vector [ada_primitive_type_long_double]
+- = arch_float_type (gdbarch, gdbarch_double_bit (gdbarch),
++ = arch_float_type (gdbarch, gdbarch_long_double_bit (gdbarch),
+ "long_long_float", NULL);
+ lai->primitive_type_vector [ada_primitive_type_natural]
+ = arch_integer_type (gdbarch, gdbarch_int_bit (gdbarch),
diff --git a/SOURCES/gdb-rhbz1320945-float128-2of9.patch b/SOURCES/gdb-rhbz1320945-float128-2of9.patch
new file mode 100644
index 0000000..02ee418
--- /dev/null
+++ b/SOURCES/gdb-rhbz1320945-float128-2of9.patch
@@ -0,0 +1,105 @@
+commit ae438bc5c06b770c00f37e4ed244707ce3ab9ff4
+Author: Ulrich Weigand <ulrich.weigand@de.ibm.com>
+Date: Tue Sep 6 17:25:31 2016 +0200
+
+ Fix TYPE_SPECIFIC_FIELD for types created via arch_type
+
+ A type's TYPE_SPECIFIC_FIELD is supposed to be initialized as appropriate
+ for the type code. This does happen if the type is created via init_type,
+ but not if it created via arch_type.
+
+ Fixed by extracting the initialization logic into a new set_type_code
+ routine, which is then called from both places.
+
+ gdb/ChangeLog:
+
+ * gdbtypes.c (set_type_code): New function.
+ (init_type, arch_type): Use it.
+
+ Signed-off-by: Ulrich Weigand <ulrich.weigand@de.ibm.com>
+
+### a/gdb/ChangeLog
+### b/gdb/ChangeLog
+## -1,5 +1,10 @@
+ 2016-09-05 Ulrich Weigand <uweigand@de.ibm.com>
+
++ * gdbtypes.c (set_type_code): New function.
++ (init_type, arch_type): Use it.
++
++2016-09-05 Ulrich Weigand <uweigand@de.ibm.com>
++
+ * ada-lang.c (ada_language_arch_info): Use gdbarch_long_double_bit
+ instead of gdbarch_double_bit for "long_long_float".
+
+--- a/gdb/gdbtypes.c
++++ b/gdb/gdbtypes.c
+@@ -2681,6 +2681,30 @@ allocate_gnat_aux_type (struct type *type)
+ *(TYPE_GNAT_SPECIFIC (type)) = gnat_aux_default;
+ }
+
++/* Helper function to initialize a newly allocated type. Set type code
++ to CODE and initialize the type-specific fields accordingly. */
++
++static void
++set_type_code (struct type *type, enum type_code code)
++{
++ TYPE_CODE (type) = code;
++
++ switch (code)
++ {
++ case TYPE_CODE_STRUCT:
++ case TYPE_CODE_UNION:
++ case TYPE_CODE_NAMESPACE:
++ INIT_CPLUS_SPECIFIC (type);
++ break;
++ case TYPE_CODE_FLT:
++ TYPE_SPECIFIC_FIELD (type) = TYPE_SPECIFIC_FLOATFORMAT;
++ break;
++ case TYPE_CODE_FUNC:
++ INIT_FUNC_SPECIFIC (type);
++ break;
++ }
++}
++
+ /* Helper function to initialize the standard scalar types.
+
+ If NAME is non-NULL, then it is used to initialize the type name.
+@@ -2694,7 +2718,7 @@ init_type (enum type_code code, int length, int flags,
+ struct type *type;
+
+ type = alloc_type (objfile);
+- TYPE_CODE (type) = code;
++ set_type_code (type, code);
+ TYPE_LENGTH (type) = length;
+
+ gdb_assert (!(flags & (TYPE_FLAG_MIN - 1)));
+@@ -2730,20 +2754,6 @@ init_type (enum type_code code, int length, int flags,
+ if (name && strcmp (name, "char") == 0)
+ TYPE_NOSIGN (type) = 1;
+
+- switch (code)
+- {
+- case TYPE_CODE_STRUCT:
+- case TYPE_CODE_UNION:
+- case TYPE_CODE_NAMESPACE:
+- INIT_CPLUS_SPECIFIC (type);
+- break;
+- case TYPE_CODE_FLT:
+- TYPE_SPECIFIC_FIELD (type) = TYPE_SPECIFIC_FLOATFORMAT;
+- break;
+- case TYPE_CODE_FUNC:
+- INIT_FUNC_SPECIFIC (type);
+- break;
+- }
+ return type;
+ }
+
+@@ -4634,7 +4644,7 @@ arch_type (struct gdbarch *gdbarch,
+ struct type *type;
+
+ type = alloc_type_arch (gdbarch);
+- TYPE_CODE (type) = code;
++ set_type_code (type, code);
+ TYPE_LENGTH (type) = length;
+
+ if (name)
diff --git a/SOURCES/gdb-rhbz1320945-float128-3of9.patch b/SOURCES/gdb-rhbz1320945-float128-3of9.patch
new file mode 100644
index 0000000..7efa934
--- /dev/null
+++ b/SOURCES/gdb-rhbz1320945-float128-3of9.patch
@@ -0,0 +1,193 @@
+commit 88dfca6c43c11dea69db24cfb87e6821e63e29b2
+Author: Ulrich Weigand <ulrich.weigand@de.ibm.com>
+Date: Tue Sep 6 17:26:32 2016 +0200
+
+ Add some missing arch_..._type helpers
+
+ gdbtypes provides a number of helper routines that can be called instead of
+ using arch_type directly to create a type of a particular kind. This patch
+ adds two additional such routines that have been missing so far, to allow
+ creation of TYPE_CODE_DECFLOAT and TYPE_CODE_POINTER types.
+
+ The patch also changes a number of places to use the new helper routines
+ instead of calling arch_type directly. No functional change intended.
+
+ gdb/ChangeLog:
+
+ * gdbtypes.h (arch_decfloat_type): New prototype.
+ (arch_pointer_type): Likewise.
+ * gdbtypes.c (arch_decfloat_type): New function.
+ (arch_pointer_type): Likewise.
+ (gdbtypes_post_init): Use arch_decfloat_type.
+ * avr-tdep.c (avr_gdbarch_init): Use arch_pointer_type.
+ * ft32-tdep.c (ft32_gdbarch_init): Likewise.
+ * m32c-tdep.c (make_types): Likewise.
+ * rl78-tdep.c (rl78_gdbarch_init): Likewise.
+
+ Signed-off-by: Ulrich Weigand <ulrich.weigand@de.ibm.com>
+
+### a/gdb/ChangeLog
+### b/gdb/ChangeLog
+## -1,5 +1,17 @@
+ 2016-09-05 Ulrich Weigand <uweigand@de.ibm.com>
+
++ * gdbtypes.h (arch_decfloat_type): New prototype.
++ (arch_pointer_type): Likewise.
++ * gdbtypes.c (arch_decfloat_type): New function.
++ (arch_pointer_type): Likewise.
++ (gdbtypes_post_init): Use arch_decfloat_type.
++ * avr-tdep.c (avr_gdbarch_init): Use arch_pointer_type.
++ * ft32-tdep.c (ft32_gdbarch_init): Likewise.
++ * m32c-tdep.c (make_types): Likewise.
++ * rl78-tdep.c (rl78_gdbarch_init): Likewise.
++
++2016-09-05 Ulrich Weigand <uweigand@de.ibm.com>
++
+ * gdbtypes.c (set_type_code): New function.
+ (init_type, arch_type): Use it.
+
+Index: gdb-7.6.1/gdb/avr-tdep.c
+===================================================================
+--- gdb-7.6.1.orig/gdb/avr-tdep.c 2017-03-11 21:27:41.914206796 +0100
++++ gdb-7.6.1/gdb/avr-tdep.c 2017-03-11 21:27:46.928242088 +0100
+@@ -1390,9 +1390,8 @@
+ be defined. */
+ tdep->void_type = arch_type (gdbarch, TYPE_CODE_VOID, 1, "void");
+ tdep->func_void_type = make_function_type (tdep->void_type, NULL);
+- tdep->pc_type = arch_type (gdbarch, TYPE_CODE_PTR, 4, NULL);
+- TYPE_TARGET_TYPE (tdep->pc_type) = tdep->func_void_type;
+- TYPE_UNSIGNED (tdep->pc_type) = 1;
++ tdep->pc_type = arch_pointer_type (gdbarch, 4 * TARGET_CHAR_BIT, NULL,
++ tdep->func_void_type);
+
+ set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
+ set_gdbarch_int_bit (gdbarch, 2 * TARGET_CHAR_BIT);
+Index: gdb-7.6.1/gdb/gdbtypes.c
+===================================================================
+--- gdb-7.6.1.orig/gdb/gdbtypes.c 2017-03-11 21:27:41.914206796 +0100
++++ gdb-7.6.1/gdb/gdbtypes.c 2017-03-11 21:29:16.324862413 +0100
+@@ -3932,7 +3932,7 @@
+
+ struct type *
+ arch_type (struct gdbarch *gdbarch,
+- enum type_code code, LONGEST length, char *name)
++ enum type_code code, LONGEST length, const char *name)
+ {
+ struct type *type;
+
+@@ -4023,6 +4023,18 @@
+ return t;
+ }
+
++/* Allocate a TYPE_CODE_DECFLOAT type structure associated with GDBARCH.
++ BIT is the type size in bits. NAME is the type name. */
++
++struct type *
++arch_decfloat_type (struct gdbarch *gdbarch, int bit, const char *name)
++{
++ struct type *t;
++
++ t = arch_type (gdbarch, TYPE_CODE_DECFLOAT, bit / TARGET_CHAR_BIT, name);
++ return t;
++}
++
+ /* Allocate a TYPE_CODE_COMPLEX type structure associated with GDBARCH.
+ NAME is the type name. TARGET_TYPE is the component float type. */
+
+@@ -4038,6 +4050,23 @@
+ return t;
+ }
+
++/* Allocate a TYPE_CODE_PTR type structure associated with GDBARCH.
++ BIT is the pointer type size in bits. NAME is the type name.
++ TARGET_TYPE is the pointer target type. Always sets the pointer type's
++ TYPE_UNSIGNED flag. */
++
++struct type *
++arch_pointer_type (struct gdbarch *gdbarch,
++ int bit, const char *name, struct type *target_type)
++{
++ struct type *t;
++
++ t = arch_type (gdbarch, TYPE_CODE_PTR, bit / TARGET_CHAR_BIT, name);
++ TYPE_TARGET_TYPE (t) = target_type;
++ TYPE_UNSIGNED (t) = 1;
++ return t;
++}
++
+ /* Allocate a TYPE_CODE_FLAGS type structure associated with GDBARCH.
+ NAME is the type name. LENGTH is the size of the flag word in bytes. */
+
+@@ -4235,11 +4264,11 @@
+ /* The following three are about decimal floating point types, which
+ are 32-bits, 64-bits and 128-bits respectively. */
+ builtin_type->builtin_decfloat
+- = arch_type (gdbarch, TYPE_CODE_DECFLOAT, 32 / 8, "_Decimal32");
++ = arch_decfloat_type (gdbarch, 32, "_Decimal32");
+ builtin_type->builtin_decdouble
+- = arch_type (gdbarch, TYPE_CODE_DECFLOAT, 64 / 8, "_Decimal64");
++ = arch_decfloat_type (gdbarch, 64, "_Decimal64");
+ builtin_type->builtin_declong
+- = arch_type (gdbarch, TYPE_CODE_DECFLOAT, 128 / 8, "_Decimal128");
++ = arch_decfloat_type (gdbarch, 128, "_Decimal128");
+
+ /* "True" character types. */
+ builtin_type->builtin_true_char
+Index: gdb-7.6.1/gdb/gdbtypes.h
+===================================================================
+--- gdb-7.6.1.orig/gdb/gdbtypes.h 2017-03-11 21:27:41.914206796 +0100
++++ gdb-7.6.1/gdb/gdbtypes.h 2017-03-11 21:29:02.861770587 +0100
+@@ -1547,14 +1547,17 @@
+
+ /* Helper functions to construct architecture-owned types. */
+ extern struct type *arch_type (struct gdbarch *, enum type_code, LONGEST,
+- char *);
++ const char *);
+ extern struct type *arch_integer_type (struct gdbarch *, int, int, char *);
+ extern struct type *arch_character_type (struct gdbarch *, int, int, char *);
+ extern struct type *arch_boolean_type (struct gdbarch *, int, int, char *);
+ extern struct type *arch_float_type (struct gdbarch *, int, char *,
+ const struct floatformat **);
++extern struct type *arch_decfloat_type (struct gdbarch *, int, const char *);
+ extern struct type *arch_complex_type (struct gdbarch *, char *,
+ struct type *);
++extern struct type *arch_pointer_type (struct gdbarch *, int, const char *,
++ struct type *);
+
+ /* Helper functions to construct a struct or record type. An
+ initially empty type is created using arch_composite_type().
+Index: gdb-7.6.1/gdb/m32c-tdep.c
+===================================================================
+--- gdb-7.6.1.orig/gdb/m32c-tdep.c 2017-03-11 21:27:41.914206796 +0100
++++ gdb-7.6.1/gdb/m32c-tdep.c 2017-03-11 21:27:46.930242102 +0100
+@@ -194,27 +194,18 @@
+ this is called, so we avoid using them. */
+ tdep->voyd = arch_type (arch, TYPE_CODE_VOID, 1, "void");
+ tdep->ptr_voyd
+- = arch_type (arch, TYPE_CODE_PTR, gdbarch_ptr_bit (arch) / TARGET_CHAR_BIT,
+- NULL);
+- TYPE_TARGET_TYPE (tdep->ptr_voyd) = tdep->voyd;
+- TYPE_UNSIGNED (tdep->ptr_voyd) = 1;
++ = arch_pointer_type (arch, gdbarch_ptr_bit (arch), NULL, tdep->voyd);
+ tdep->func_voyd = lookup_function_type (tdep->voyd);
+
+ xsnprintf (type_name, sizeof (type_name), "%s_data_addr_t",
+ gdbarch_bfd_arch_info (arch)->printable_name);
+ tdep->data_addr_reg_type
+- = arch_type (arch, TYPE_CODE_PTR, data_addr_reg_bits / TARGET_CHAR_BIT,
+- xstrdup (type_name));
+- TYPE_TARGET_TYPE (tdep->data_addr_reg_type) = tdep->voyd;
+- TYPE_UNSIGNED (tdep->data_addr_reg_type) = 1;
++ = arch_pointer_type (arch, data_addr_reg_bits, type_name, tdep->voyd);
+
+ xsnprintf (type_name, sizeof (type_name), "%s_code_addr_t",
+ gdbarch_bfd_arch_info (arch)->printable_name);
+ tdep->code_addr_reg_type
+- = arch_type (arch, TYPE_CODE_PTR, code_addr_reg_bits / TARGET_CHAR_BIT,
+- xstrdup (type_name));
+- TYPE_TARGET_TYPE (tdep->code_addr_reg_type) = tdep->func_voyd;
+- TYPE_UNSIGNED (tdep->code_addr_reg_type) = 1;
++ = arch_pointer_type (arch, code_addr_reg_bits, type_name, tdep->func_voyd);
+
+ tdep->uint8 = arch_integer_type (arch, 8, 1, "uint8_t");
+ tdep->uint16 = arch_integer_type (arch, 16, 1, "uint16_t");
diff --git a/SOURCES/gdb-rhbz1320945-float128-4of9.patch b/SOURCES/gdb-rhbz1320945-float128-4of9.patch
new file mode 100644
index 0000000..e3b7dd0
--- /dev/null
+++ b/SOURCES/gdb-rhbz1320945-float128-4of9.patch
@@ -0,0 +1,1295 @@
+commit 19f392bc2a93d9e64d063b884cd6eca547c8dad0
+Author: Ulrich Weigand <ulrich.weigand@de.ibm.com>
+Date: Tue Sep 6 17:27:55 2016 +0200
+
+ Unify init_type and arch_type interface and helpers
+
+ This adds a number of helper routines for creating objfile-owned types;
+ these correspond 1:1 to the already existing helper routines for creating
+ gdbarch-owned types, and are intended to be used instead of init_type.
+ A shared fragment of init_float_type and arch_float_type is extracted into
+ a separate subroutine verify_subroutine.
+
+ The commit also brings the interface of init_type in line with the one for
+ arch_type. In particular, this means removing the FLAGS argument; callers
+ now set the required flags directly. (Since most callers use the new
+ helper routines, very few callers actually need to set any additional
+ flags directly any more.)
+
+ Note that this means all the TYPE_FLAGS_... defined are no longer needed
+ anywhere; they will be removed by a follow-on commit.
+
+ All users of init_type are changed to use on of the new helpers where
+ possible. No functional change intended.
+
+ gdb/ChangeLog:
+
+ * gdbtypes.h (init_type): Remove FLAGS argument. Move OBJFILE
+ argument to first position.
+ (init_integer_type): New prototype.
+ (init_character_type): Likewise.
+ (init_boolean_type): Likewise.
+ (init_float_type): Likewise.
+ (init_decfloat_type): Likewise.
+ (init_complex_type): Likewise.
+ (init_pointer_type): Likewise.
+ * gdbtypes.c (verify_floatflormat): New function.
+ (init_type): Remove FLAGS argument and processing. Move OBJFILE
+ argument to first position.
+ (init_integer_type): New function.
+ (init_character_type): Likewise.
+ (init_boolean_type): Likewise.
+ (init_float_type): Likewise.
+ (init_decfloat_type): Likewise.
+ (init_complex_type): Likewise.
+ (init_pointer_type): Likewise.
+ (arch_float_type): Use verify_floatflormat.
+ (objfile_type): Use init_..._type helpers instead of calling
+ init_type directly.
+ * dwarf2read.c (fixup_go_packaging): Update to changed init_type
+ prototype.
+ (read_namespace_type): Likewise.
+ (read_module_type): Likewise.
+ (read_typedef): Likewise.
+ (read_unspecified_type): Likewise.
+ (build_error_marker_type): Likewise.
+ (read_base_type): Use init_..._type helpers.
+ * mdebugread.c (basic_type): Use init_..._type helpers.
+ (parse_type): Update to changed init_type prototype.
+ (cross_ref): Likewise.
+ * stabsread.c (rs6000_builtin_type): Use init_..._type helpers.
+ (read_sun_builtin_type): Likewise.
+ (read_sun_floating_type): Likewise.
+ (read_range_type): Likewise. Also update to changed init_type
+ prototype.
+
+ Signed-off-by: Ulrich Weigand <ulrich.weigand@de.ibm.com>
+
+### a/gdb/ChangeLog
+### b/gdb/ChangeLog
+## -1,5 +1,46 @@
+ 2016-09-05 Ulrich Weigand <uweigand@de.ibm.com>
+
++ * gdbtypes.h (init_type): Remove FLAGS argument. Move OBJFILE
++ argument to first position.
++ (init_integer_type): New prototype.
++ (init_character_type): Likewise.
++ (init_boolean_type): Likewise.
++ (init_float_type): Likewise.
++ (init_decfloat_type): Likewise.
++ (init_complex_type): Likewise.
++ (init_pointer_type): Likewise.
++ * gdbtypes.c (verify_floatflormat): New function.
++ (init_type): Remove FLAGS argument and processing. Move OBJFILE
++ argument to first position.
++ (init_integer_type): New function.
++ (init_character_type): Likewise.
++ (init_boolean_type): Likewise.
++ (init_float_type): Likewise.
++ (init_decfloat_type): Likewise.
++ (init_complex_type): Likewise.
++ (init_pointer_type): Likewise.
++ (arch_float_type): Use verify_floatflormat.
++ (objfile_type): Use init_..._type helpers instead of calling
++ init_type directly.
++ * dwarf2read.c (fixup_go_packaging): Update to changed init_type
++ prototype.
++ (read_namespace_type): Likewise.
++ (read_module_type): Likewise.
++ (read_typedef): Likewise.
++ (read_unspecified_type): Likewise.
++ (build_error_marker_type): Likewise.
++ (read_base_type): Use init_..._type helpers.
++ * mdebugread.c (basic_type): Use init_..._type helpers.
++ (parse_type): Update to changed init_type prototype.
++ (cross_ref): Likewise.
++ * stabsread.c (rs6000_builtin_type): Use init_..._type helpers.
++ (read_sun_builtin_type): Likewise.
++ (read_sun_floating_type): Likewise.
++ (read_range_type): Likewise. Also update to changed init_type
++ prototype.
++
++2016-09-05 Ulrich Weigand <uweigand@de.ibm.com>
++
+ * gdbtypes.h (arch_decfloat_type): New prototype.
+ (arch_pointer_type): Likewise.
+ * gdbtypes.c (arch_decfloat_type): New function.
+Index: gdb-7.6.1/gdb/dwarf2read.c
+===================================================================
+--- gdb-7.6.1.orig/gdb/dwarf2read.c 2017-03-11 21:42:28.099262777 +0100
++++ gdb-7.6.1/gdb/dwarf2read.c 2017-03-11 21:45:39.098565504 +0100
+@@ -6901,8 +6901,8 @@
+ const char *saved_package_name = obstack_copy0 (&objfile->objfile_obstack,
+ package_name,
+ strlen (package_name));
+- struct type *type = init_type (TYPE_CODE_MODULE, 0, 0,
+- saved_package_name, objfile);
++ struct type *type = init_type (objfile, TYPE_CODE_MODULE, 0,
++ saved_package_name);
+ struct symbol *sym;
+
+ TYPE_TAG_NAME (type) = TYPE_NAME (type);
+@@ -12266,9 +12266,7 @@
+ previous_prefix, name, 0, cu);
+
+ /* Create the type. */
+- type = init_type (TYPE_CODE_NAMESPACE, 0, 0, NULL,
+- objfile);
+- TYPE_NAME (type) = name;
++ type = init_type (objfile, TYPE_CODE_NAMESPACE, 0, name);
+ TYPE_TAG_NAME (type) = TYPE_NAME (type);
+
+ return set_die_type (die, type, cu);
+@@ -12331,7 +12329,7 @@
+ complaint (&symfile_complaints,
+ _("DW_TAG_module has no name, offset 0x%x"),
+ die->offset.sect_off);
+- type = init_type (TYPE_CODE_MODULE, 0, 0, module_name, objfile);
++ type = init_type (objfile, TYPE_CODE_MODULE, 0, module_name);
+
+ /* determine_prefix uses TYPE_TAG_NAME. */
+ TYPE_TAG_NAME (type) = TYPE_NAME (type);
+@@ -12884,9 +12882,8 @@
+ struct type *this_type, *target_type;
+
+ name = dwarf2_full_name (NULL, die, cu);
+- this_type = init_type (TYPE_CODE_TYPEDEF, 0,
+- TYPE_FLAG_TARGET_STUB, NULL, objfile);
+- TYPE_NAME (this_type) = name;
++ this_type = init_type (objfile, TYPE_CODE_TYPEDEF, 0, name);
++ TYPE_TARGET_STUB (this_type) = 1;
+ set_die_type (die, this_type, cu);
+ target_type = die_type (die, cu);
+ if (target_type != this_type)
+@@ -12913,11 +12910,8 @@
+ struct objfile *objfile = cu->objfile;
+ struct type *type;
+ struct attribute *attr;
+- int encoding = 0, size = 0;
++ int encoding = 0, bits = 0;
+ const char *name;
+- enum type_code code = TYPE_CODE_INT;
+- int type_flags = 0;
+- struct type *target_type = NULL;
+
+ attr = dwarf2_attr (die, DW_AT_encoding, cu);
+ if (attr)
+@@ -12927,7 +12921,7 @@
+ attr = dwarf2_attr (die, DW_AT_byte_size, cu);
+ if (attr)
+ {
+- size = DW_UNSND (attr);
++ bits = DW_UNSND (attr) * TARGET_CHAR_BIT;
+ }
+ name = dwarf2_name (die, cu);
+ if (!name)
+@@ -12940,61 +12934,63 @@
+ {
+ case DW_ATE_address:
+ /* Turn DW_ATE_address into a void * pointer. */
+- code = TYPE_CODE_PTR;
+- type_flags |= TYPE_FLAG_UNSIGNED;
+- target_type = init_type (TYPE_CODE_VOID, 1, 0, NULL, objfile);
++ type = init_type (objfile, TYPE_CODE_VOID, 1, NULL);
++ type = init_pointer_type (objfile, bits, name, type);
+ break;
+ case DW_ATE_boolean:
+- code = TYPE_CODE_BOOL;
+- type_flags |= TYPE_FLAG_UNSIGNED;
++ type = init_boolean_type (objfile, bits, 1, name);
+ break;
+ case DW_ATE_complex_float:
+- code = TYPE_CODE_COMPLEX;
+- target_type = init_type (TYPE_CODE_FLT, size / 2, 0, NULL, objfile);
++ type = init_float_type (objfile, bits / 2, NULL, NULL);
++ type = init_complex_type (objfile, name, type);
+ break;
+ case DW_ATE_decimal_float:
+- code = TYPE_CODE_DECFLOAT;
++ type = init_decfloat_type (objfile, bits, name);
+ break;
+ case DW_ATE_float:
+- code = TYPE_CODE_FLT;
++ type = init_float_type (objfile, bits, name, NULL);
+ break;
+ case DW_ATE_signed:
++ type = init_integer_type (objfile, bits, 0, name);
+ break;
+ case DW_ATE_unsigned:
+- type_flags |= TYPE_FLAG_UNSIGNED;
+ if (cu->language == language_fortran
+ && name
+ && strncmp (name, "character(", sizeof ("character(") - 1) == 0)
+- code = TYPE_CODE_CHAR;
++ type = init_character_type (objfile, bits, 1, name);
++ else
++ type = init_integer_type (objfile, bits, 1, name);
+ break;
+ case DW_ATE_signed_char:
+ if (cu->language == language_ada || cu->language == language_m2
+ || cu->language == language_pascal
+ || cu->language == language_fortran)
+- code = TYPE_CODE_CHAR;
++ type = init_character_type (objfile, bits, 0, name);
++ else
++ type = init_integer_type (objfile, bits, 0, name);
+ break;
+ case DW_ATE_unsigned_char:
+ if (cu->language == language_ada || cu->language == language_m2
+ || cu->language == language_pascal
+ || cu->language == language_fortran)
+- code = TYPE_CODE_CHAR;
+- type_flags |= TYPE_FLAG_UNSIGNED;
++ type = init_character_type (objfile, bits, 1, name);
++ else
++ type = init_integer_type (objfile, bits, 1, name);
+ break;
+ case DW_ATE_UTF:
+ /* We just treat this as an integer and then recognize the
+ type by name elsewhere. */
++ type = init_integer_type (objfile, bits, 0, name);
+ break;
+
+ default:
+ complaint (&symfile_complaints, _("unsupported DW_AT_encoding: '%s'"),
+ dwarf_type_encoding_name (encoding));
++ type = init_type (objfile, TYPE_CODE_ERROR,
++ bits / TARGET_CHAR_BIT, name);
+ break;
+ }
+
+- type = init_type (code, size, type_flags, NULL, objfile);
+- TYPE_NAME (type) = name;
+- TYPE_TARGET_TYPE (type) = target_type;
+-
+ if (name && strcmp (name, "char") == 0)
+ TYPE_NOSIGN (type) = 1;
+
+@@ -13287,7 +13283,7 @@
+
+ /* For now, we only support the C meaning of an unspecified type: void. */
+
+- type = init_type (TYPE_CODE_VOID, 0, 0, NULL, cu->objfile);
++ type = init_type (cu->objfile, TYPE_CODE_VOID, 0, NULL);
+ TYPE_NAME (type) = dwarf2_name (die, cu);
+
+ return set_die_type (die, type, cu);
+@@ -16913,7 +16909,7 @@
+ message, strlen (message));
+ xfree (message);
+
+- this_type = init_type (TYPE_CODE_ERROR, 0, 0, saved, objfile);
++ this_type = init_type (objfile, TYPE_CODE_ERROR, 0, saved);
+ }
+
+ return this_type;
+Index: gdb-7.6.1/gdb/gdbtypes.c
+===================================================================
+--- gdb-7.6.1.orig/gdb/gdbtypes.c 2017-03-11 21:45:27.194484312 +0100
++++ gdb-7.6.1/gdb/gdbtypes.c 2017-03-11 21:48:13.551598067 +0100
+@@ -2107,6 +2107,41 @@
+ }
+ }
+
++// RH
++#define FLOATFORMAT_CHAR_BIT 8 // doublest.c
++static size_t
++floatformat_totalsize_bytes (const struct floatformat *fmt)
++{
++ return ((fmt->totalsize + FLOATFORMAT_CHAR_BIT - 1)
++ / FLOATFORMAT_CHAR_BIT);
++}
++
++/* Helper function to verify floating-point format and size.
++ BIT is the type size in bits; if BIT equals -1, the size is
++ determined by the floatformat. Returns size to be used. */
++
++static int
++verify_floatformat (int bit, const struct floatformat **floatformats)
++{
++ if (bit == -1)
++ {
++ gdb_assert (floatformats != NULL);
++ gdb_assert (floatformats[0] != NULL && floatformats[1] != NULL);
++ bit = floatformats[0]->totalsize;
++ }
++ gdb_assert (bit >= 0);
++
++ if (floatformats != NULL)
++ {
++ size_t len = bit / TARGET_CHAR_BIT;
++
++ gdb_assert (len >= floatformat_totalsize_bytes (floatformats[0]));
++ gdb_assert (len >= floatformat_totalsize_bytes (floatformats[1]));
++ }
++
++ return bit;
++}
++
+ /* Helper function to initialize the standard scalar types.
+
+ If NAME is non-NULL, then it is used to initialize the type name.
+@@ -2114,8 +2149,8 @@
+ least as long as OBJFILE. */
+
+ struct type *
+-init_type (enum type_code code, LONGEST length, int flags,
+- const char *name, struct objfile *objfile)
++init_type (struct objfile *objfile, enum type_code code, LONGEST length,
++ const char *name)
+ {
+ struct type *type;
+
+@@ -2123,32 +2158,6 @@
+ set_type_code (type, code);
+ TYPE_LENGTH (type) = length;
+
+- gdb_assert (!(flags & (TYPE_FLAG_MIN - 1)));
+- if (flags & TYPE_FLAG_UNSIGNED)
+- TYPE_UNSIGNED (type) = 1;
+- if (flags & TYPE_FLAG_NOSIGN)
+- TYPE_NOSIGN (type) = 1;
+- if (flags & TYPE_FLAG_STUB)
+- TYPE_STUB (type) = 1;
+- if (flags & TYPE_FLAG_TARGET_STUB)
+- TYPE_TARGET_STUB (type) = 1;
+- if (flags & TYPE_FLAG_STATIC)
+- TYPE_STATIC (type) = 1;
+- if (flags & TYPE_FLAG_PROTOTYPED)
+- TYPE_PROTOTYPED (type) = 1;
+- if (flags & TYPE_FLAG_INCOMPLETE)
+- TYPE_INCOMPLETE (type) = 1;
+- if (flags & TYPE_FLAG_VARARGS)
+- TYPE_VARARGS (type) = 1;
+- if (flags & TYPE_FLAG_VECTOR)
+- TYPE_VECTOR (type) = 1;
+- if (flags & TYPE_FLAG_STUB_SUPPORTED)
+- TYPE_STUB_SUPPORTED (type) = 1;
+- if (flags & TYPE_FLAG_FIXED_INSTANCE)
+- TYPE_FIXED_INSTANCE (type) = 1;
+- if (flags & TYPE_FLAG_GNU_IFUNC)
+- TYPE_GNU_IFUNC (type) = 1;
+-
+ TYPE_NAME (type) = name;
+
+ /* C++ fancies. */
+@@ -2158,6 +2167,121 @@
+
+ return type;
+ }
++
++/* Allocate a TYPE_CODE_INT type structure associated with OBJFILE.
++ BIT is the type size in bits. If UNSIGNED_P is non-zero, set
++ the type's TYPE_UNSIGNED flag. NAME is the type name. */
++
++struct type *
++init_integer_type (struct objfile *objfile,
++ int bit, int unsigned_p, const char *name)
++{
++ struct type *t;
++
++ t = init_type (objfile, TYPE_CODE_INT, bit / TARGET_CHAR_BIT, name);
++ if (unsigned_p)
++ TYPE_UNSIGNED (t) = 1;
++
++ return t;
++}
++
++/* Allocate a TYPE_CODE_CHAR type structure associated with OBJFILE.
++ BIT is the type size in bits. If UNSIGNED_P is non-zero, set
++ the type's TYPE_UNSIGNED flag. NAME is the type name. */
++
++struct type *
++init_character_type (struct objfile *objfile,
++ int bit, int unsigned_p, const char *name)
++{
++ struct type *t;
++
++ t = init_type (objfile, TYPE_CODE_CHAR, bit / TARGET_CHAR_BIT, name);
++ if (unsigned_p)
++ TYPE_UNSIGNED (t) = 1;
++
++ return t;
++}
++
++/* Allocate a TYPE_CODE_BOOL type structure associated with OBJFILE.
++ BIT is the type size in bits. If UNSIGNED_P is non-zero, set
++ the type's TYPE_UNSIGNED flag. NAME is the type name. */
++
++struct type *
++init_boolean_type (struct objfile *objfile,
++ int bit, int unsigned_p, const char *name)
++{
++ struct type *t;
++
++ t = init_type (objfile, TYPE_CODE_BOOL, bit / TARGET_CHAR_BIT, name);
++ if (unsigned_p)
++ TYPE_UNSIGNED (t) = 1;
++
++ return t;
++}
++
++/* Allocate a TYPE_CODE_FLT type structure associated with OBJFILE.
++ BIT is the type size in bits; if BIT equals -1, the size is
++ determined by the floatformat. NAME is the type name. Set the
++ TYPE_FLOATFORMAT from FLOATFORMATS. */
++
++struct type *
++init_float_type (struct objfile *objfile,
++ int bit, const char *name,
++ const struct floatformat **floatformats)
++{
++ struct type *t;
++
++ bit = verify_floatformat (bit, floatformats);
++ t = init_type (objfile, TYPE_CODE_FLT, bit / TARGET_CHAR_BIT, name);
++ TYPE_FLOATFORMAT (t) = floatformats;
++
++ return t;
++}
++
++/* Allocate a TYPE_CODE_DECFLOAT type structure associated with OBJFILE.
++ BIT is the type size in bits. NAME is the type name. */
++
++struct type *
++init_decfloat_type (struct objfile *objfile, int bit, const char *name)
++{
++ struct type *t;
++
++ t = init_type (objfile, TYPE_CODE_DECFLOAT, bit / TARGET_CHAR_BIT, name);
++ return t;
++}
++
++/* Allocate a TYPE_CODE_COMPLEX type structure associated with OBJFILE.
++ NAME is the type name. TARGET_TYPE is the component float type. */
++
++struct type *
++init_complex_type (struct objfile *objfile,
++ const char *name, struct type *target_type)
++{
++ struct type *t;
++
++ t = init_type (objfile, TYPE_CODE_COMPLEX,
++ 2 * TYPE_LENGTH (target_type), name);
++ TYPE_TARGET_TYPE (t) = target_type;
++ return t;
++}
++
++/* Allocate a TYPE_CODE_PTR type structure associated with OBJFILE.
++ BIT is the pointer type size in bits. NAME is the type name.
++ TARGET_TYPE is the pointer target type. Always sets the pointer type's
++ TYPE_UNSIGNED flag. */
++
++struct type *
++init_pointer_type (struct objfile *objfile,
++ int bit, const char *name, struct type *target_type)
++{
++ struct type *t;
++
++ t = init_type (objfile, TYPE_CODE_PTR, bit / TARGET_CHAR_BIT, name);
++ TYPE_TARGET_TYPE (t) = target_type;
++ TYPE_UNSIGNED (t) = 1;
++ return t;
++}
++
+
+ /* Queries on types. */
+
+@@ -4010,14 +4134,7 @@
+ {
+ struct type *t;
+
+- if (bit == -1)
+- {
+- gdb_assert (floatformats != NULL);
+- gdb_assert (floatformats[0] != NULL && floatformats[1] != NULL);
+- bit = floatformats[0]->totalsize;
+- }
+- gdb_assert (bit >= 0);
+-
++ bit = verify_floatformat (bit, floatformats);
+ t = arch_type (gdbarch, TYPE_CODE_FLT, bit / TARGET_CHAR_BIT, name);
+ TYPE_FLOATFORMAT (t) = floatformats;
+ return t;
+@@ -4350,109 +4467,80 @@
+
+ /* Basic types. */
+ objfile_type->builtin_void
+- = init_type (TYPE_CODE_VOID, 1,
+- 0,
+- "void", objfile);
+-
++ = init_type (objfile, TYPE_CODE_VOID, 1, "void");
+ objfile_type->builtin_char
+- = init_type (TYPE_CODE_INT, TARGET_CHAR_BIT / TARGET_CHAR_BIT,
+- (TYPE_FLAG_NOSIGN
+- | (gdbarch_char_signed (gdbarch) ? 0 : TYPE_FLAG_UNSIGNED)),
+- "char", objfile);
++ = init_integer_type (objfile, TARGET_CHAR_BIT,
++ !gdbarch_char_signed (gdbarch), "char");
+ objfile_type->builtin_signed_char
+- = init_type (TYPE_CODE_INT, TARGET_CHAR_BIT / TARGET_CHAR_BIT,
+- 0,
+- "signed char", objfile);
++ = init_integer_type (objfile, TARGET_CHAR_BIT,
++ 0, "signed char");
+ objfile_type->builtin_unsigned_char
+- = init_type (TYPE_CODE_INT, TARGET_CHAR_BIT / TARGET_CHAR_BIT,
+- TYPE_FLAG_UNSIGNED,
+- "unsigned char", objfile);
++ = init_integer_type (objfile, TARGET_CHAR_BIT,
++ 1, "unsigned char");
+ objfile_type->builtin_short
+- = init_type (TYPE_CODE_INT,
+- gdbarch_short_bit (gdbarch) / TARGET_CHAR_BIT,
+- 0, "short", objfile);
++ = init_integer_type (objfile, gdbarch_short_bit (gdbarch),
++ 0, "short");
+ objfile_type->builtin_unsigned_short
+- = init_type (TYPE_CODE_INT,
+- gdbarch_short_bit (gdbarch) / TARGET_CHAR_BIT,
+- TYPE_FLAG_UNSIGNED, "unsigned short", objfile);
++ = init_integer_type (objfile, gdbarch_short_bit (gdbarch),
++ 1, "unsigned short");
+ objfile_type->builtin_int
+- = init_type (TYPE_CODE_INT,
+- gdbarch_int_bit (gdbarch) / TARGET_CHAR_BIT,
+- 0, "int", objfile);
++ = init_integer_type (objfile, gdbarch_int_bit (gdbarch),
++ 0, "int");
+ objfile_type->builtin_unsigned_int
+- = init_type (TYPE_CODE_INT,
+- gdbarch_int_bit (gdbarch) / TARGET_CHAR_BIT,
+- TYPE_FLAG_UNSIGNED, "unsigned int", objfile);
++ = init_integer_type (objfile, gdbarch_int_bit (gdbarch),
++ 1, "unsigned int");
+ objfile_type->builtin_long
+- = init_type (TYPE_CODE_INT,
+- gdbarch_long_bit (gdbarch) / TARGET_CHAR_BIT,
+- 0, "long", objfile);
++ = init_integer_type (objfile, gdbarch_long_bit (gdbarch),
++ 0, "long");
+ objfile_type->builtin_unsigned_long
+- = init_type (TYPE_CODE_INT,
+- gdbarch_long_bit (gdbarch) / TARGET_CHAR_BIT,
+- TYPE_FLAG_UNSIGNED, "unsigned long", objfile);
++ = init_integer_type (objfile, gdbarch_long_bit (gdbarch),
++ 1, "unsigned long");
+ objfile_type->builtin_long_long
+- = init_type (TYPE_CODE_INT,
+- gdbarch_long_long_bit (gdbarch) / TARGET_CHAR_BIT,
+- 0, "long long", objfile);
++ = init_integer_type (objfile, gdbarch_long_long_bit (gdbarch),
++ 0, "long long");
+ objfile_type->builtin_unsigned_long_long
+- = init_type (TYPE_CODE_INT,
+- gdbarch_long_long_bit (gdbarch) / TARGET_CHAR_BIT,
+- TYPE_FLAG_UNSIGNED, "unsigned long long", objfile);
+-
++ = init_integer_type (objfile, gdbarch_long_long_bit (gdbarch),
++ 1, "unsigned long long");
+ objfile_type->builtin_float
+- = init_type (TYPE_CODE_FLT,
+- gdbarch_float_bit (gdbarch) / TARGET_CHAR_BIT,
+- 0, "float", objfile);
+- TYPE_FLOATFORMAT (objfile_type->builtin_float)
+- = gdbarch_float_format (gdbarch);
++ = init_float_type (objfile, gdbarch_float_bit (gdbarch),
++ "float", gdbarch_float_format (gdbarch));
+ objfile_type->builtin_double
+- = init_type (TYPE_CODE_FLT,
+- gdbarch_double_bit (gdbarch) / TARGET_CHAR_BIT,
+- 0, "double", objfile);
+- TYPE_FLOATFORMAT (objfile_type->builtin_double)
+- = gdbarch_double_format (gdbarch);
++ = init_float_type (objfile, gdbarch_double_bit (gdbarch),
++ "double", gdbarch_double_format (gdbarch));
+ objfile_type->builtin_long_double
+- = init_type (TYPE_CODE_FLT,
+- gdbarch_long_double_bit (gdbarch) / TARGET_CHAR_BIT,
+- 0, "long double", objfile);
+- TYPE_FLOATFORMAT (objfile_type->builtin_long_double)
+- = gdbarch_long_double_format (gdbarch);
++ = init_float_type (objfile, gdbarch_long_double_bit (gdbarch),
++ "long double", gdbarch_long_double_format (gdbarch));
+
+ /* This type represents a type that was unrecognized in symbol read-in. */
+ objfile_type->builtin_error
+- = init_type (TYPE_CODE_ERROR, 0, 0, "<unknown type>", objfile);
++ = init_type (objfile, TYPE_CODE_ERROR, 0, "<unknown type>");
+
+ /* The following set of types is used for symbols with no
+ debug information. */
+ objfile_type->nodebug_text_symbol
+- = init_type (TYPE_CODE_FUNC, 1, 0,
+- "<text variable, no debug info>", objfile);
++ = init_type (objfile, TYPE_CODE_FUNC, 1,
++ "<text variable, no debug info>");
+ TYPE_TARGET_TYPE (objfile_type->nodebug_text_symbol)
+ = objfile_type->builtin_int;
+ objfile_type->nodebug_text_gnu_ifunc_symbol
+- = init_type (TYPE_CODE_FUNC, 1, TYPE_FLAG_GNU_IFUNC,
+- "<text gnu-indirect-function variable, no debug info>",
+- objfile);
++ = init_type (objfile, TYPE_CODE_FUNC, 1,
++ "<text gnu-indirect-function variable, no debug info>");
+ TYPE_TARGET_TYPE (objfile_type->nodebug_text_gnu_ifunc_symbol)
+ = objfile_type->nodebug_text_symbol;
++ TYPE_GNU_IFUNC (objfile_type->nodebug_text_gnu_ifunc_symbol) = 1;
+ objfile_type->nodebug_got_plt_symbol
+- = init_type (TYPE_CODE_PTR, gdbarch_addr_bit (gdbarch) / 8, 0,
+- "<text from jump slot in .got.plt, no debug info>",
+- objfile);
+- TYPE_TARGET_TYPE (objfile_type->nodebug_got_plt_symbol)
+- = objfile_type->nodebug_text_symbol;
++ = init_pointer_type (objfile, gdbarch_addr_bit (gdbarch),
++ "<text from jump slot in .got.plt, no debug info>",
++ objfile_type->nodebug_text_symbol);
+ objfile_type->nodebug_data_symbol
+- = init_type (TYPE_CODE_INT,
+- gdbarch_int_bit (gdbarch) / HOST_CHAR_BIT, 0,
+- "<data variable, no debug info>", objfile);
++ = init_integer_type (objfile, gdbarch_int_bit (gdbarch), 0,
++ "<data variable, no debug info>");
+ objfile_type->nodebug_unknown_symbol
+- = init_type (TYPE_CODE_INT, 1, 0,
+- "<variable (not text or data), no debug info>", objfile);
++ = init_integer_type (objfile, TARGET_CHAR_BIT, 0,
++ "<variable (not text or data), no debug info>");
+ objfile_type->nodebug_tls_symbol
+- = init_type (TYPE_CODE_INT,
+- gdbarch_int_bit (gdbarch) / HOST_CHAR_BIT, 0,
+- "<thread local variable, no debug info>", objfile);
++ = init_integer_type (objfile, gdbarch_int_bit (gdbarch), 0,
++ "<thread local variable, no debug info>");
+
+ /* NOTE: on some targets, addresses and pointers are not necessarily
+ the same --- for example, on the D10V, pointers are 16 bits long,
+@@ -4482,9 +4570,8 @@
+ are indeed in the unified virtual address space. */
+
+ objfile_type->builtin_core_addr
+- = init_type (TYPE_CODE_INT,
+- gdbarch_addr_bit (gdbarch) / 8,
+- TYPE_FLAG_UNSIGNED, "__CORE_ADDR", objfile);
++ = init_integer_type (objfile, gdbarch_addr_bit (gdbarch), 1,
++ "__CORE_ADDR");
+
+ set_objfile_data (objfile, objfile_type_data, objfile_type);
+ return objfile_type;
+Index: gdb-7.6.1/gdb/gdbtypes.h
+===================================================================
+--- gdb-7.6.1.orig/gdb/gdbtypes.h 2017-03-11 21:45:27.194484312 +0100
++++ gdb-7.6.1/gdb/gdbtypes.h 2017-03-11 21:45:39.100565518 +0100
+@@ -1542,8 +1542,21 @@
+ extern struct gdbarch *get_type_arch (const struct type *);
+
+ /* Helper function to construct objfile-owned types. */
+-extern struct type *init_type (enum type_code, LONGEST, int, const char *,
+- struct objfile *);
++extern struct type *init_type (struct objfile *, enum type_code, LONGEST,
++ const char *);
++extern struct type *init_integer_type (struct objfile *, int, int,
++ const char *);
++extern struct type *init_character_type (struct objfile *, int, int,
++ const char *);
++extern struct type *init_boolean_type (struct objfile *, int, int,
++ const char *);
++extern struct type *init_float_type (struct objfile *, int, const char *,
++ const struct floatformat **);
++extern struct type *init_decfloat_type (struct objfile *, int, const char *);
++extern struct type *init_complex_type (struct objfile *, const char *,
++ struct type *);
++extern struct type *init_pointer_type (struct objfile *, int, const char *,
++ struct type *);
+
+ /* Helper functions to construct architecture-owned types. */
+ extern struct type *arch_type (struct gdbarch *, enum type_code, LONGEST,
+Index: gdb-7.6.1/gdb/mdebugread.c
+===================================================================
+--- gdb-7.6.1.orig/gdb/mdebugread.c 2017-03-11 21:42:28.099262777 +0100
++++ gdb-7.6.1/gdb/mdebugread.c 2017-03-11 21:45:39.101565525 +0100
+@@ -1374,97 +1374,80 @@
+ break;
+
+ case btAdr:
+- tp = init_type (TYPE_CODE_PTR, 4, TYPE_FLAG_UNSIGNED,
+- "adr_32", objfile);
+- TYPE_TARGET_TYPE (tp) = objfile_type (objfile)->builtin_void;
++ tp = init_pointer_type (objfile, 32, "adr_32",
++ objfile_type (objfile)->builtin_void);
+ break;
+
+ case btChar:
+- tp = init_type (TYPE_CODE_INT, 1, 0,
+- "char", objfile);
++ tp = init_integer_type (objfile, 8, 0, "char");
+ break;
+
+ case btUChar:
+- tp = init_type (TYPE_CODE_INT, 1, TYPE_FLAG_UNSIGNED,
+- "unsigned char", objfile);
++ tp = init_integer_type (objfile, 8, 1, "unsigned char");
+ break;
+
+ case btShort:
+- tp = init_type (TYPE_CODE_INT, 2, 0,
+- "short", objfile);
++ tp = init_integer_type (objfile, 16, 0, "short");
+ break;
+
+ case btUShort:
+- tp = init_type (TYPE_CODE_INT, 2, TYPE_FLAG_UNSIGNED,
+- "unsigned short", objfile);
++ tp = init_integer_type (objfile, 16, 1, "unsigned short");
+ break;
+
+ case btInt:
+- tp = init_type (TYPE_CODE_INT, 4, 0,
+- "int", objfile);
++ tp = init_integer_type (objfile, 32, 0, "int");
+ break;
+
+ case btUInt:
+- tp = init_type (TYPE_CODE_INT, 4, TYPE_FLAG_UNSIGNED,
+- "unsigned int", objfile);
++ tp = init_integer_type (objfile, 32, 1, "unsigned int");
+ break;
+
+ case btLong:
+- tp = init_type (TYPE_CODE_INT, 4, 0,
+- "long", objfile);
++ tp = init_integer_type (objfile, 32, 0, "long");
+ break;
+
+ case btULong:
+- tp = init_type (TYPE_CODE_INT, 4, TYPE_FLAG_UNSIGNED,
+- "unsigned long", objfile);
++ tp = init_integer_type (objfile, 32, 1, "unsigned long");
+ break;
+
+ case btFloat:
+- tp = init_type (TYPE_CODE_FLT,
+- gdbarch_float_bit (gdbarch) / TARGET_CHAR_BIT, 0,
+- "float", objfile);
++ tp = init_float_type (objfile, gdbarch_float_bit (gdbarch),
++ "float", NULL);
+ break;
+
+ case btDouble:
+- tp = init_type (TYPE_CODE_FLT,
+- gdbarch_double_bit (gdbarch) / TARGET_CHAR_BIT, 0,
+- "double", objfile);
++ tp = init_float_type (objfile, gdbarch_double_bit (gdbarch),
++ "double", NULL);
+ break;
+
+ case btComplex:
+- tp = init_type (TYPE_CODE_COMPLEX,
+- 2 * gdbarch_float_bit (gdbarch) / TARGET_CHAR_BIT, 0,
+- "complex", objfile);
+- TYPE_TARGET_TYPE (tp) = basic_type (btFloat, objfile);
++ tp = init_complex_type (objfile, "complex",
++ basic_type (btFloat, objfile));
+ break;
+
+ case btDComplex:
+- tp = init_type (TYPE_CODE_COMPLEX,
+- 2 * gdbarch_double_bit (gdbarch) / TARGET_CHAR_BIT, 0,
+- "double complex", objfile);
+- TYPE_TARGET_TYPE (tp) = basic_type (btDouble, objfile);
++ tp = init_complex_type (objfile, "double complex",
++ basic_type (btFloat, objfile));
+ break;
+
+ case btFixedDec:
+ /* We use TYPE_CODE_INT to print these as integers. Does this do any
+ good? Would we be better off with TYPE_CODE_ERROR? Should
+ TYPE_CODE_ERROR print things in hex if it knows the size? */
+- tp = init_type (TYPE_CODE_INT,
+- gdbarch_int_bit (gdbarch) / TARGET_CHAR_BIT, 0,
+- "fixed decimal", objfile);
++ tp = init_integer_type (objfile, gdbarch_int_bit (gdbarch), 0,
++ "fixed decimal");
+ break;
+
+ case btFloatDec:
+- tp = init_type (TYPE_CODE_ERROR,
+- gdbarch_double_bit (gdbarch) / TARGET_CHAR_BIT, 0,
+- "floating decimal", objfile);
++ tp = init_type (objfile, TYPE_CODE_ERROR,
++ gdbarch_double_bit (gdbarch) / TARGET_CHAR_BIT,
++ "floating decimal");
+ break;
+
+ case btString:
+ /* Is a "string" the way btString means it the same as TYPE_CODE_STRING?
+ FIXME. */
+- tp = init_type (TYPE_CODE_STRING, 1, 0,
+- "string", objfile);
++ tp = init_type (objfile, TYPE_CODE_STRING, 1, "string");
+ break;
+
+ case btVoid:
+@@ -1472,39 +1455,32 @@
+ break;
+
+ case btLong64:
+- tp = init_type (TYPE_CODE_INT, 8, 0,
+- "long", objfile);
++ tp = init_integer_type (objfile, 64, 0, "long");
+ break;
+
+ case btULong64:
+- tp = init_type (TYPE_CODE_INT, 8, TYPE_FLAG_UNSIGNED,
+- "unsigned long", objfile);
++ tp = init_integer_type (objfile, 64, 1, "unsigned long");
+ break;
+
+ case btLongLong64:
+- tp = init_type (TYPE_CODE_INT, 8, 0,
+- "long long", objfile);
++ tp = init_integer_type (objfile, 64, 0, "long long");
+ break;
+
+ case btULongLong64:
+- tp = init_type (TYPE_CODE_INT, 8, TYPE_FLAG_UNSIGNED,
+- "unsigned long long", objfile);
++ tp = init_integer_type (objfile, 64, 1, "unsigned long long");
+ break;
+
+ case btAdr64:
+- tp = init_type (TYPE_CODE_PTR, 8, TYPE_FLAG_UNSIGNED,
+- "adr_64", objfile);
+- TYPE_TARGET_TYPE (tp) = objfile_type (objfile)->builtin_void;
++ tp = init_pointer_type (objfile, 64, "adr_64",
++ objfile_type (objfile)->builtin_void);
+ break;
+
+ case btInt64:
+- tp = init_type (TYPE_CODE_INT, 8, 0,
+- "int", objfile);
++ tp = init_integer_type (objfile, 64, 0, "int");
+ break;
+
+ case btUInt64:
+- tp = init_type (TYPE_CODE_INT, 8, TYPE_FLAG_UNSIGNED,
+- "unsigned int", objfile);
++ tp = init_integer_type (objfile, 64, 1, "unsigned int");
+ break;
+
+ default:
+@@ -1656,7 +1632,7 @@
+ /* Try to cross reference this type, build new type on failure. */
+ ax += cross_ref (fd, ax, &tp, type_code, &name, bigend, sym_name);
+ if (tp == (struct type *) NULL)
+- tp = init_type (type_code, 0, 0, (char *) NULL, mdebugread_objfile);
++ tp = init_type (mdebugread_objfile, type_code, 0, NULL);
+
+ /* DEC c89 produces cross references to qualified aggregate types,
+ dereference them. */
+@@ -1715,7 +1691,7 @@
+ /* Try to cross reference this type, build new type on failure. */
+ ax += cross_ref (fd, ax, &tp, type_code, &name, bigend, sym_name);
+ if (tp == (struct type *) NULL)
+- tp = init_type (type_code, 0, 0, (char *) NULL, mdebugread_objfile);
++ tp = init_type (mdebugread_objfile, type_code, 0, NULL);
+
+ /* Make sure that TYPE_CODE(tp) has an expected type code.
+ Any type may be returned from cross_ref if file indirect entries
+@@ -4433,13 +4409,13 @@
+ }
+
+ /* mips cc uses a rf of -1 for opaque struct definitions.
+- Set TYPE_FLAG_STUB for these types so that check_typedef will
++ Set TYPE_STUB for these types so that check_typedef will
+ resolve them if the struct gets defined in another compilation unit. */
+ if (rf == -1)
+ {
+ *pname = "<undefined>";
+- *tpp = init_type (type_code, 0, TYPE_FLAG_STUB,
+- (char *) NULL, mdebugread_objfile);
++ *tpp = init_type (mdebugread_objfile, type_code, 0, NULL);
++ TYPE_STUB (*tpp) = 1;
+ return result;
+ }
+
+@@ -4525,8 +4501,7 @@
+ switch (tir.bt)
+ {
+ case btVoid:
+- *tpp = init_type (type_code, 0, 0, (char *) NULL,
+- mdebugread_objfile);
++ *tpp = init_type (mdebugread_objfile, type_code, 0, NULL);
+ *pname = "<undefined>";
+ break;
+
+@@ -4561,8 +4536,7 @@
+ complaint (&symfile_complaints,
+ _("illegal bt %d in forward typedef for %s"), tir.bt,
+ sym_name);
+- *tpp = init_type (type_code, 0, 0, (char *) NULL,
+- mdebugread_objfile);
++ *tpp = init_type (mdebugread_objfile, type_code, 0, NULL);
+ break;
+ }
+ return result;
+@@ -4590,7 +4564,7 @@
+ has not been parsed yet.
+ Initialize the type only, it will be filled in when
+ it's definition is parsed. */
+- *tpp = init_type (type_code, 0, 0, (char *) NULL, mdebugread_objfile);
++ *tpp = init_type (mdebugread_objfile, type_code, 0, NULL);
+ }
+ add_pending (fh, esh, *tpp);
+ }
+Index: gdb-7.6.1/gdb/stabsread.c
+===================================================================
+--- gdb-7.6.1.orig/gdb/stabsread.c 2017-03-11 21:42:28.099262777 +0100
++++ gdb-7.6.1/gdb/stabsread.c 2017-03-11 21:45:39.102565532 +0100
+@@ -2098,130 +2098,115 @@
+ is other than 32 bits, then it should use a new negative type
+ number (or avoid negative type numbers for that case).
+ See stabs.texinfo. */
+- rettype = init_type (TYPE_CODE_INT, 4, 0, "int", objfile);
++ rettype = init_integer_type (objfile, 32, 0, "int");
+ break;
+ case 2:
+- rettype = init_type (TYPE_CODE_INT, 1, 0, "char", objfile);
++ rettype = init_integer_type (objfile, 8, 0, "char");
+ break;
+ case 3:
+- rettype = init_type (TYPE_CODE_INT, 2, 0, "short", objfile);
++ rettype = init_integer_type (objfile, 16, 0, "short");
+ break;
+ case 4:
+- rettype = init_type (TYPE_CODE_INT, 4, 0, "long", objfile);
++ rettype = init_integer_type (objfile, 32, 0, "long");
+ break;
+ case 5:
+- rettype = init_type (TYPE_CODE_INT, 1, TYPE_FLAG_UNSIGNED,
+- "unsigned char", objfile);
++ rettype = init_integer_type (objfile, 8, 1, "unsigned char");
+ break;
+ case 6:
+- rettype = init_type (TYPE_CODE_INT, 1, 0, "signed char", objfile);
++ rettype = init_integer_type (objfile, 8, 0, "signed char");
+ break;
+ case 7:
+- rettype = init_type (TYPE_CODE_INT, 2, TYPE_FLAG_UNSIGNED,
+- "unsigned short", objfile);
++ rettype = init_integer_type (objfile, 16, 1, "unsigned short");
+ break;
+ case 8:
+- rettype = init_type (TYPE_CODE_INT, 4, TYPE_FLAG_UNSIGNED,
+- "unsigned int", objfile);
++ rettype = init_integer_type (objfile, 32, 1, "unsigned int");
+ break;
+ case 9:
+- rettype = init_type (TYPE_CODE_INT, 4, TYPE_FLAG_UNSIGNED,
+- "unsigned", objfile);
++ rettype = init_integer_type (objfile, 32, 1, "unsigned");
+ break;
+ case 10:
+- rettype = init_type (TYPE_CODE_INT, 4, TYPE_FLAG_UNSIGNED,
+- "unsigned long", objfile);
++ rettype = init_integer_type (objfile, 32, 1, "unsigned long");
+ break;
+ case 11:
+- rettype = init_type (TYPE_CODE_VOID, 1, 0, "void", objfile);
++ rettype = init_type (objfile, TYPE_CODE_VOID, 1, "void");
+ break;
+ case 12:
+ /* IEEE single precision (32 bit). */
+- rettype = init_type (TYPE_CODE_FLT, 4, 0, "float", objfile);
++ rettype = init_float_type (objfile, 32, "float", NULL);
+ break;
+ case 13:
+ /* IEEE double precision (64 bit). */
+- rettype = init_type (TYPE_CODE_FLT, 8, 0, "double", objfile);
++ rettype = init_float_type (objfile, 64, "double", NULL);
+ break;
+ case 14:
+ /* This is an IEEE double on the RS/6000, and different machines with
+ different sizes for "long double" should use different negative
+ type numbers. See stabs.texinfo. */
+- rettype = init_type (TYPE_CODE_FLT, 8, 0, "long double", objfile);
++ rettype = init_float_type (objfile, 64, "long double", NULL);
+ break;
+ case 15:
+- rettype = init_type (TYPE_CODE_INT, 4, 0, "integer", objfile);
++ rettype = init_integer_type (objfile, 32, 0, "integer");
+ break;
+ case 16:
+- rettype = init_type (TYPE_CODE_BOOL, 4, TYPE_FLAG_UNSIGNED,
+- "boolean", objfile);
++ rettype = init_boolean_type (objfile, 32, 1, "boolean");
+ break;
+ case 17:
+- rettype = init_type (TYPE_CODE_FLT, 4, 0, "short real", objfile);
++ rettype = init_float_type (objfile, 32, "short real", NULL);
+ break;
+ case 18:
+- rettype = init_type (TYPE_CODE_FLT, 8, 0, "real", objfile);
++ rettype = init_float_type (objfile, 64, "real", NULL);
+ break;
+ case 19:
+- rettype = init_type (TYPE_CODE_ERROR, 0, 0, "stringptr", objfile);
++ rettype = init_type (objfile, TYPE_CODE_ERROR, 0, "stringptr");
+ break;
+ case 20:
+- rettype = init_type (TYPE_CODE_CHAR, 1, TYPE_FLAG_UNSIGNED,
+- "character", objfile);
++ rettype = init_character_type (objfile, 8, 1, "character");
+ break;
+ case 21:
+- rettype = init_type (TYPE_CODE_BOOL, 1, TYPE_FLAG_UNSIGNED,
+- "logical*1", objfile);
++ rettype = init_boolean_type (objfile, 8, 1, "logical*1");
+ break;
+ case 22:
+- rettype = init_type (TYPE_CODE_BOOL, 2, TYPE_FLAG_UNSIGNED,
+- "logical*2", objfile);
++ rettype = init_boolean_type (objfile, 16, 1, "logical*2");
+ break;
+ case 23:
+- rettype = init_type (TYPE_CODE_BOOL, 4, TYPE_FLAG_UNSIGNED,
+- "logical*4", objfile);
++ rettype = init_boolean_type (objfile, 32, 1, "logical*4");
+ break;
+ case 24:
+- rettype = init_type (TYPE_CODE_BOOL, 4, TYPE_FLAG_UNSIGNED,
+- "logical", objfile);
++ rettype = init_boolean_type (objfile, 32, 1, "logical");
+ break;
+ case 25:
+ /* Complex type consisting of two IEEE single precision values. */
+- rettype = init_type (TYPE_CODE_COMPLEX, 8, 0, "complex", objfile);
+- TYPE_TARGET_TYPE (rettype) = init_type (TYPE_CODE_FLT, 4, 0, "float",
+- objfile);
++ rettype = init_complex_type (objfile, "complex",
++ rs6000_builtin_type (12, objfile));
+ break;
+ case 26:
+ /* Complex type consisting of two IEEE double precision values. */
+- rettype = init_type (TYPE_CODE_COMPLEX, 16, 0, "double complex", NULL);
+- TYPE_TARGET_TYPE (rettype) = init_type (TYPE_CODE_FLT, 8, 0, "double",
+- objfile);
++ rettype = init_complex_type (objfile, "double complex",
++ rs6000_builtin_type (13, objfile));
+ break;
+ case 27:
+- rettype = init_type (TYPE_CODE_INT, 1, 0, "integer*1", objfile);
++ rettype = init_integer_type (objfile, 8, 0, "integer*1");
+ break;
+ case 28:
+- rettype = init_type (TYPE_CODE_INT, 2, 0, "integer*2", objfile);
++ rettype = init_integer_type (objfile, 16, 0, "integer*2");
+ break;
+ case 29:
+- rettype = init_type (TYPE_CODE_INT, 4, 0, "integer*4", objfile);
++ rettype = init_integer_type (objfile, 32, 0, "integer*4");
+ break;
+ case 30:
+- rettype = init_type (TYPE_CODE_CHAR, 2, 0, "wchar", objfile);
++ rettype = init_character_type (objfile, 16, 0, "wchar");
+ break;
+ case 31:
+- rettype = init_type (TYPE_CODE_INT, 8, 0, "long long", objfile);
++ rettype = init_integer_type (objfile, 64, 0, "long long");
+ break;
+ case 32:
+- rettype = init_type (TYPE_CODE_INT, 8, TYPE_FLAG_UNSIGNED,
+- "unsigned long long", objfile);
++ rettype = init_integer_type (objfile, 64, 1, "unsigned long long");
+ break;
+ case 33:
+- rettype = init_type (TYPE_CODE_INT, 8, TYPE_FLAG_UNSIGNED,
+- "logical*8", objfile);
++ rettype = init_integer_type (objfile, 64, 1, "logical*8");
+ break;
+ case 34:
+- rettype = init_type (TYPE_CODE_INT, 8, 0, "integer*8", objfile);
++ rettype = init_integer_type (objfile, 64, 0, "integer*8");
+ break;
+ }
+ negative_types[-typenum] = rettype;
+@@ -3757,16 +3742,16 @@
+ {
+ int type_bits;
+ int nbits;
+- int signed_type;
+- enum type_code code = TYPE_CODE_INT;
++ int unsigned_type;
++ int boolean_type = 0;
+
+ switch (**pp)
+ {
+ case 's':
+- signed_type = 1;
++ unsigned_type = 0;
+ break;
+ case 'u':
+- signed_type = 0;
++ unsigned_type = 1;
+ break;
+ default:
+ return error_type (pp, objfile);
+@@ -3783,7 +3768,7 @@
+ (*pp)++;
+ else if (**pp == 'b')
+ {
+- code = TYPE_CODE_BOOL;
++ boolean_type = 1;
+ (*pp)++;
+ }
+
+@@ -3814,14 +3799,17 @@
+ ++(*pp);
+
+ if (type_bits == 0)
+- return init_type (TYPE_CODE_VOID, 1,
+- signed_type ? 0 : TYPE_FLAG_UNSIGNED, (char *) NULL,
+- objfile);
++ {
++ struct type *type = init_type (objfile, TYPE_CODE_VOID, 1, NULL);
++ if (unsigned_type)
++ TYPE_UNSIGNED (type) = 1;
++ return type;
++ }
++
++ if (boolean_type)
++ return init_boolean_type (objfile, type_bits, unsigned_type, NULL);
+ else
+- return init_type (code,
+- type_bits / TARGET_CHAR_BIT,
+- signed_type ? 0 : TYPE_FLAG_UNSIGNED, (char *) NULL,
+- objfile);
++ return init_integer_type (objfile, type_bits, unsigned_type, NULL);
+ }
+
+ static struct type *
+@@ -3843,16 +3831,16 @@
+ if (nbits != 0)
+ return error_type (pp, objfile);
+
++ nbits = nbytes * TARGET_CHAR_BIT;
++
+ if (details == NF_COMPLEX || details == NF_COMPLEX16
+ || details == NF_COMPLEX32)
+ {
+- rettype = init_type (TYPE_CODE_COMPLEX, nbytes, 0, NULL, objfile);
+- TYPE_TARGET_TYPE (rettype)
+- = init_type (TYPE_CODE_FLT, nbytes / 2, 0, NULL, objfile);
+- return rettype;
++ rettype = init_float_type (objfile, nbits / 2, NULL, NULL);
++ return init_complex_type (objfile, NULL, rettype);
+ }
+
+- return init_type (TYPE_CODE_FLT, nbytes, 0, NULL, objfile);
++ return init_float_type (objfile, nbits, NULL, NULL);
+ }
+
+ /* Read a number from the string pointed to by *PP.
+@@ -4115,18 +4103,14 @@
+ }
+
+ if (got_signed || got_unsigned)
+- {
+- return init_type (TYPE_CODE_INT, nbits / TARGET_CHAR_BIT,
+- got_unsigned ? TYPE_FLAG_UNSIGNED : 0, NULL,
+- objfile);
+- }
++ return init_integer_type (objfile, nbits, got_unsigned, NULL);
+ else
+ return error_type (pp, objfile);
+ }
+
+ /* A type defined as a subrange of itself, with bounds both 0, is void. */
+ if (self_subrange && n2 == 0 && n3 == 0)
+- return init_type (TYPE_CODE_VOID, 1, 0, NULL, objfile);
++ return init_type (objfile, TYPE_CODE_VOID, 1, NULL);
+
+ /* If n3 is zero and n2 is positive, we want a floating type, and n2
+ is the width in bytes.
+@@ -4143,16 +4127,10 @@
+ if (n3 == 0 && n2 > 0)
+ {
+ struct type *float_type
+- = init_type (TYPE_CODE_FLT, n2, 0, NULL, objfile);
++ = init_float_type (objfile, n2 * TARGET_CHAR_BIT, NULL, NULL);
+
+ if (self_subrange)
+- {
+- struct type *complex_type =
+- init_type (TYPE_CODE_COMPLEX, 2 * n2, 0, NULL, objfile);
+-
+- TYPE_TARGET_TYPE (complex_type) = float_type;
+- return complex_type;
+- }
++ return init_complex_type (objfile, NULL, float_type);
+ else
+ return float_type;
+ }
+@@ -4171,15 +4149,17 @@
+ bits = gdbarch_int_bit (gdbarch);
+ }
+
+- return init_type (TYPE_CODE_INT, bits / TARGET_CHAR_BIT,
+- TYPE_FLAG_UNSIGNED, NULL, objfile);
++ return init_integer_type (objfile, bits, 1, NULL);
+ }
+
+ /* Special case: char is defined (Who knows why) as a subrange of
+ itself with range 0-127. */
+ else if (self_subrange && n2 == 0 && n3 == 127)
+- return init_type (TYPE_CODE_INT, 1, TYPE_FLAG_NOSIGN, NULL, objfile);
+-
++ {
++ struct type *type = init_integer_type (objfile, 1, 0, NULL);
++ TYPE_NOSIGN (type) = 1;
++ return type;
++ }
+ /* We used to do this only for subrange of self or subrange of int. */
+ else if (n2 == 0)
+ {
+@@ -4189,8 +4169,7 @@
+
+ if (n3 < 0)
+ /* n3 actually gives the size. */
+- return init_type (TYPE_CODE_INT, -n3, TYPE_FLAG_UNSIGNED,
+- NULL, objfile);
++ return init_integer_type (objfile, -n3 * TARGET_CHAR_BIT, 1, NULL);
+
+ /* Is n3 == 2**(8n)-1 for some integer n? Then it's an
+ unsigned n-byte integer. But do require n to be a power of
+@@ -4204,8 +4183,7 @@
+ bits >>= 8;
+ if (bits == 0
+ && ((bytes - 1) & bytes) == 0) /* "bytes is a power of two" */
+- return init_type (TYPE_CODE_INT, bytes, TYPE_FLAG_UNSIGNED, NULL,
+- objfile);
++ return init_integer_type (objfile, bytes * TARGET_CHAR_BIT, 1, NULL);
+ }
+ }
+ /* I think this is for Convex "long long". Since I don't know whether
+@@ -4215,15 +4193,15 @@
+ && (self_subrange
+ || n2 == -gdbarch_long_long_bit
+ (gdbarch) / TARGET_CHAR_BIT))
+- return init_type (TYPE_CODE_INT, -n2, 0, NULL, objfile);
++ return init_integer_type (objfile, -n2 * TARGET_CHAR_BIT, 0, NULL);
+ else if (n2 == -n3 - 1)
+ {
+ if (n3 == 0x7f)
+- return init_type (TYPE_CODE_INT, 1, 0, NULL, objfile);
++ return init_integer_type (objfile, 8, 0, NULL);
+ if (n3 == 0x7fff)
+- return init_type (TYPE_CODE_INT, 2, 0, NULL, objfile);
++ return init_integer_type (objfile, 16, 0, NULL);
+ if (n3 == 0x7fffffff)
+- return init_type (TYPE_CODE_INT, 4, 0, NULL, objfile);
++ return init_integer_type (objfile, 32, 0, NULL);
+ }
+
+ /* We have a real range type on our hands. Allocate space and
diff --git a/SOURCES/gdb-rhbz1320945-float128-5of9.patch b/SOURCES/gdb-rhbz1320945-float128-5of9.patch
new file mode 100644
index 0000000..9c9c567
--- /dev/null
+++ b/SOURCES/gdb-rhbz1320945-float128-5of9.patch
@@ -0,0 +1,350 @@
+commit a9ff5f12cff6cd06f74ecf387ac5468984c94c6f
+Author: Ulrich Weigand <ulrich.weigand@de.ibm.com>
+Date: Tue Sep 6 17:29:15 2016 +0200
+
+ Remove obsolete TYPE_FLAG_... values
+
+ Now that init_type no longer takes a FLAGS argument, there is no user of
+ the TYPE_FLAGS_... enum values left. This commit removes them (and all
+ references to them in comments as well).
+
+ This is mostly a no-op, except for a change to the Python type printer,
+ which attempted to use them before. (As best as I can tell, this wasn't
+ really needed anyway, since it was only used to pretty-print type
+ *instance* flags, which only use the instance flags.)
+
+ gdb/ChangeLog:
+
+ * gdbtypes.h (enum type_flag_value): Remove.
+ Remove references to TYPE_FLAG_... in comments throughout.
+ * gdbtypes.c (recursive_dump_type): Do not print TYPE_FLAG_...
+ flags, print the corresponding TYPE_... access macro names.
+ Remove references to TYPE_FLAG_... in comments throughout.
+ * infcall.c: Remove references to TYPE_FLAG_... in comments.
+ * valprint.c: Likewise.
+ * gdb-gdb.py (class TypeFlag): No longer consider TYPE_FLAG_...
+ values, only TYPE_INSTANCE_FLAG_... values.
+ (class TypeFlagsPrinter): Likewise.
+
+ gdb/testsuite/ChangeLog:
+
+ * gdb.cp/hang.exp: Remove reference to TYPE_FLAG_STUB in comment.
+
+ Signed-off-by: Ulrich Weigand <ulrich.weigand@de.ibm.com>
+
+### a/gdb/ChangeLog
+### b/gdb/ChangeLog
+## -1,5 +1,18 @@
+ 2016-09-05 Ulrich Weigand <uweigand@de.ibm.com>
+
++ * gdbtypes.h (enum type_flag_value): Remove.
++ Remove references to TYPE_FLAG_... in comments throughout.
++ * gdbtypes.c (recursive_dump_type): Do not print TYPE_FLAG_...
++ flags, print the corresponding TYPE_... access macro names.
++ Remove references to TYPE_FLAG_... in comments throughout.
++ * infcall.c: Remove references to TYPE_FLAG_... in comments.
++ * valprint.c: Likewise.
++ * gdb-gdb.py (class TypeFlag): No longer consider TYPE_FLAG_...
++ values, only TYPE_INSTANCE_FLAG_... values.
++ (class TypeFlagsPrinter): Likewise.
++
++2016-09-05 Ulrich Weigand <uweigand@de.ibm.com>
++
+ * gdbtypes.h (init_type): Remove FLAGS argument. Move OBJFILE
+ argument to first position.
+ (init_integer_type): New prototype.
+Index: gdb-7.6.1/gdb/gdb-gdb.py
+===================================================================
+--- gdb-7.6.1.orig/gdb/gdb-gdb.py 2017-03-11 21:20:00.381958270 +0100
++++ gdb-7.6.1/gdb/gdb-gdb.py 2017-03-11 21:22:11.333879984 +0100
+@@ -24,29 +24,26 @@
+
+ In the GDB sources, struct type has a component called instance_flags
+ in which the value is the addition of various flags. These flags are
+- defined by two enumerates: type_flag_value, and type_instance_flag_value.
+- This class helps us recreate a list with all these flags that is
+- easy to manipulate and sort. Because all flag names start with either
+- TYPE_FLAG_ or TYPE_INSTANCE_FLAG_, a short_name attribute is provided
+- that strips this prefix.
++ defined by the enumerates type_instance_flag_value. This class helps us
++ recreate a list with all these flags that is easy to manipulate and sort.
++ Because all flag names start with TYPE_INSTANCE_FLAG_, a short_name
++ attribute is provided that strips this prefix.
+
+ ATTRIBUTES
+- name: The enumeration name (eg: "TYPE_FLAG_UNSIGNED").
++ name: The enumeration name (eg: "TYPE_INSTANCE_FLAG_CONST").
+ value: The associated value.
+ short_name: The enumeration name, with the suffix stripped.
+ """
+ def __init__(self, name, value):
+ self.name = name
+ self.value = value
+- self.short_name = name.replace("TYPE_FLAG_", '')
+- if self.short_name == name:
+- self.short_name = name.replace("TYPE_INSTANCE_FLAG_", '')
++ self.short_name = name.replace("TYPE_INSTANCE_FLAG_", '')
+ def __cmp__(self, other):
+ """Sort by value order."""
+ return self.value.__cmp__(other.value)
+
+-# A list of all existing TYPE_FLAGS_* and TYPE_INSTANCE_FLAGS_*
+-# enumerations, stored as TypeFlags objects. Lazy-initialized.
++# A list of all existing TYPE_INSTANCE_FLAGS_* enumerations,
++# stored as TypeFlags objects. Lazy-initialized.
+ TYPE_FLAGS = None
+
+ class TypeFlagsPrinter:
+@@ -86,24 +83,13 @@
+ global TYPE_FLAGS
+ TYPE_FLAGS = []
+ try:
+- flags = gdb.lookup_type("enum type_flag_value")
+- except:
+- print "Warning: Cannot find enum type_flag_value type."
+- print " `struct type' pretty-printer will be degraded"
+- return
+- try:
+ iflags = gdb.lookup_type("enum type_instance_flag_value")
+ except:
+ print "Warning: Cannot find enum type_instance_flag_value type."
+ print " `struct type' pretty-printer will be degraded"
+ return
+- # Note: TYPE_FLAG_MIN is a duplicate of TYPE_FLAG_UNSIGNED,
+- # so exclude it from the list we are building.
+ TYPE_FLAGS = [TypeFlag(field.name, field.enumval)
+- for field in flags.fields()
+- if field.name != 'TYPE_FLAG_MIN']
+- TYPE_FLAGS += [TypeFlag(field.name, field.enumval)
+- for field in iflags.fields()]
++ for field in iflags.fields()]
+ TYPE_FLAGS.sort()
+
+ class StructTypePrettyPrinter:
+Index: gdb-7.6.1/gdb/gdbtypes.c
+===================================================================
+--- gdb-7.6.1.orig/gdb/gdbtypes.c 2017-03-11 21:20:02.353972150 +0100
++++ gdb-7.6.1/gdb/gdbtypes.c 2017-03-11 21:24:10.766720620 +0100
+@@ -3426,73 +3426,73 @@
+ TYPE_INSTANCE_FLAGS (type));
+ if (TYPE_CONST (type))
+ {
+- puts_filtered (" TYPE_FLAG_CONST");
++ puts_filtered (" TYPE_CONST");
+ }
+ if (TYPE_VOLATILE (type))
+ {
+- puts_filtered (" TYPE_FLAG_VOLATILE");
++ puts_filtered (" TYPE_VOLATILE");
+ }
+ if (TYPE_CODE_SPACE (type))
+ {
+- puts_filtered (" TYPE_FLAG_CODE_SPACE");
++ puts_filtered (" TYPE_CODE_SPACE");
+ }
+ if (TYPE_DATA_SPACE (type))
+ {
+- puts_filtered (" TYPE_FLAG_DATA_SPACE");
++ puts_filtered (" TYPE_DATA_SPACE");
+ }
+ if (TYPE_ADDRESS_CLASS_1 (type))
+ {
+- puts_filtered (" TYPE_FLAG_ADDRESS_CLASS_1");
++ puts_filtered (" TYPE_ADDRESS_CLASS_1");
+ }
+ if (TYPE_ADDRESS_CLASS_2 (type))
+ {
+- puts_filtered (" TYPE_FLAG_ADDRESS_CLASS_2");
++ puts_filtered (" TYPE_ADDRESS_CLASS_2");
+ }
+ if (TYPE_RESTRICT (type))
+ {
+- puts_filtered (" TYPE_FLAG_RESTRICT");
++ puts_filtered (" TYPE_RESTRICT");
+ }
+ puts_filtered ("\n");
+
+ printfi_filtered (spaces, "flags");
+ if (TYPE_UNSIGNED (type))
+ {
+- puts_filtered (" TYPE_FLAG_UNSIGNED");
++ puts_filtered (" TYPE_UNSIGNED");
+ }
+ if (TYPE_NOSIGN (type))
+ {
+- puts_filtered (" TYPE_FLAG_NOSIGN");
++ puts_filtered (" TYPE_NOSIGN");
+ }
+ if (TYPE_STUB (type))
+ {
+- puts_filtered (" TYPE_FLAG_STUB");
++ puts_filtered (" TYPE_STUB");
+ }
+ if (TYPE_TARGET_STUB (type))
+ {
+- puts_filtered (" TYPE_FLAG_TARGET_STUB");
++ puts_filtered (" TYPE_TARGET_STUB");
+ }
+ if (TYPE_STATIC (type))
+ {
+- puts_filtered (" TYPE_FLAG_STATIC");
++ puts_filtered (" TYPE_STATIC");
+ }
+ if (TYPE_PROTOTYPED (type))
+ {
+- puts_filtered (" TYPE_FLAG_PROTOTYPED");
++ puts_filtered (" TYPE_PROTOTYPED");
+ }
+ if (TYPE_INCOMPLETE (type))
+ {
+- puts_filtered (" TYPE_FLAG_INCOMPLETE");
++ puts_filtered (" TYPE_INCOMPLETE");
+ }
+ if (TYPE_VARARGS (type))
+ {
+- puts_filtered (" TYPE_FLAG_VARARGS");
++ puts_filtered (" TYPE_VARARGS");
+ }
+ /* This is used for things like AltiVec registers on ppc. Gcc emits
+ an attribute for the array type, which tells whether or not we
+ have a vector, instead of a regular array. */
+ if (TYPE_VECTOR (type))
+ {
+- puts_filtered (" TYPE_FLAG_VECTOR");
++ puts_filtered (" TYPE_VECTOR");
+ }
+ if (TYPE_FIXED_INSTANCE (type))
+ {
+Index: gdb-7.6.1/gdb/gdbtypes.h
+===================================================================
+--- gdb-7.6.1.orig/gdb/gdbtypes.h 2017-03-11 21:20:00.385958298 +0100
++++ gdb-7.6.1/gdb/gdbtypes.h 2017-03-11 21:26:19.829629038 +0100
+@@ -160,35 +160,8 @@
+
+ #define TYPE_CODE_CLASS TYPE_CODE_STRUCT
+
+-/* Some constants representing each bit field in the main_type. See
+- the bit-field-specific macros, below, for documentation of each
+- constant in this enum. These enum values are only used with
+- init_type. Note that the values are chosen not to conflict with
+- type_instance_flag_value; this lets init_type error-check its
+- input. */
+-
+-enum type_flag_value
+-{
+- TYPE_FLAG_UNSIGNED = (1 << 8),
+- TYPE_FLAG_NOSIGN = (1 << 9),
+- TYPE_FLAG_STUB = (1 << 10),
+- TYPE_FLAG_TARGET_STUB = (1 << 11),
+- TYPE_FLAG_STATIC = (1 << 12),
+- TYPE_FLAG_PROTOTYPED = (1 << 13),
+- TYPE_FLAG_INCOMPLETE = (1 << 14),
+- TYPE_FLAG_VARARGS = (1 << 15),
+- TYPE_FLAG_VECTOR = (1 << 16),
+- TYPE_FLAG_FIXED_INSTANCE = (1 << 17),
+- TYPE_FLAG_STUB_SUPPORTED = (1 << 18),
+- TYPE_FLAG_GNU_IFUNC = (1 << 19),
+-
+- /* Used for error-checking. */
+- TYPE_FLAG_MIN = TYPE_FLAG_UNSIGNED
+-};
+-
+ /* Some bits for the type's instance_flags word. See the macros below
+- for documentation on each bit. Note that if you add a value here,
+- you must update the enum type_flag_value as well. */
++ for documentation on each bit. */
+ enum type_instance_flag_value
+ {
+ TYPE_INSTANCE_FLAG_CONST = (1 << 0),
+@@ -202,7 +175,7 @@
+ };
+
+ /* Unsigned integer type. If this is not set for a TYPE_CODE_INT, the
+- type is signed (unless TYPE_FLAG_NOSIGN (below) is set). */
++ type is signed (unless TYPE_NOSIGN (below) is set). */
+
+ #define TYPE_UNSIGNED(t) (TYPE_MAIN_TYPE (t)->flag_unsigned)
+
+@@ -383,11 +356,11 @@
+ architecture's two (or more) address spaces, but this is an extension
+ of the architecture's model.
+
+- If TYPE_FLAG_INST is set, an object of the corresponding type
++ If TYPE_INSTANCE_FLAG_CODE_SPACE is set, an object of the corresponding type
+ resides in instruction memory, even if its address (in the extended
+ flat address space) does not reflect this.
+
+- Similarly, if TYPE_FLAG_DATA is set, then an object of the
++ Similarly, if TYPE_INSTANCE_FLAG_DATA_SPACE is set, then an object of the
+ corresponding type resides in the data memory space, even if
+ this is not indicated by its (flat address space) address.
+
+@@ -403,7 +376,7 @@
+ /* Address class flags. Some environments provide for pointers whose
+ size is different from that of a normal pointer or address types
+ where the bits are interpreted differently than normal addresses. The
+- TYPE_FLAG_ADDRESS_CLASS_n flags may be used in target specific
++ TYPE_ADDRESS_CLASS_n flags may be used in target specific
+ ways to represent these different types of address classes. */
+ #define TYPE_ADDRESS_CLASS_1(t) (TYPE_INSTANCE_FLAGS(t) \
+ & TYPE_INSTANCE_FLAG_ADDRESS_CLASS_1)
+@@ -529,7 +502,7 @@
+
+ This is used for printing only, except by poorly designed C++ code.
+ For looking up a name, look for a symbol in the STRUCT_DOMAIN.
+- One more legitimate use is that if TYPE_FLAG_STUB is set, this is
++ One more legitimate use is that if TYPE_STUB is set, this is
+ the name to use to look for definitions in other files. */
+
+ const char *tag_name;
+Index: gdb-7.6.1/gdb/infcall.c
+===================================================================
+--- gdb-7.6.1.orig/gdb/infcall.c 2017-03-11 21:20:00.386958305 +0100
++++ gdb-7.6.1/gdb/infcall.c 2017-03-11 21:20:02.355972164 +0100
+@@ -58,10 +58,9 @@
+
+ Unfortunately, on certain older platforms, the debug info doesn't
+ indicate reliably how each function was defined. A function type's
+- TYPE_FLAG_PROTOTYPED flag may be clear, even if the function was
+- defined in prototype style. When calling a function whose
+- TYPE_FLAG_PROTOTYPED flag is clear, GDB consults this flag to
+- decide what to do.
++ TYPE_PROTOTYPED flag may be clear, even if the function was defined
++ in prototype style. When calling a function whose TYPE_PROTOTYPED
++ flag is clear, GDB consults this flag to decide what to do.
+
+ For modern targets, it is proper to assume that, if the prototype
+ flag is clear, that can be trusted: `float' arguments should be
+Index: gdb-7.6.1/gdb/testsuite/gdb.cp/hang.exp
+===================================================================
+--- gdb-7.6.1.orig/gdb/testsuite/gdb.cp/hang.exp 2017-03-11 21:20:00.386958305 +0100
++++ gdb-7.6.1/gdb/testsuite/gdb.cp/hang.exp 2017-03-11 21:20:02.356972171 +0100
+@@ -58,8 +58,8 @@
+ #
+ # Since `hang2.o''s psymtab lists `hang1.o' as a dependency, GDB first
+ # reads `hang1.o''s symbols. When GDB sees `(1,3)=xsB:', it creates a
+-# type object for `struct B', sets its TYPE_FLAG_STUB flag, and
+-# records it as type number `(1,3)'.
++# type object for `struct B', sets its TYPE_STUB flag, and records it
++# as type number `(1,3)'.
+ #
+ # When GDB finds the definition of `struct C::B', since the stabs
+ # don't indicate that the type is nested within C, it treats it as
+Index: gdb-7.6.1/gdb/valprint.c
+===================================================================
+--- gdb-7.6.1.orig/gdb/valprint.c 2017-03-11 21:20:00.387958312 +0100
++++ gdb-7.6.1/gdb/valprint.c 2017-03-11 21:20:02.356972171 +0100
+@@ -661,10 +661,9 @@
+ break;
+
+ case TYPE_CODE_UNDEF:
+- /* This happens (without TYPE_FLAG_STUB set) on systems which
+- don't use dbx xrefs (NO_DBX_XREFS in gcc) if a file has a
+- "struct foo *bar" and no complete type for struct foo in that
+- file. */
++ /* This happens (without TYPE_STUB set) on systems which don't use
++ dbx xrefs (NO_DBX_XREFS in gcc) if a file has a "struct foo *bar"
++ and no complete type for struct foo in that file. */
+ fprintf_filtered (stream, _("<incomplete type>"));
+ break;
+
diff --git a/SOURCES/gdb-rhbz1320945-float128-6of9.patch b/SOURCES/gdb-rhbz1320945-float128-6of9.patch
new file mode 100644
index 0000000..8e7f3b1
--- /dev/null
+++ b/SOURCES/gdb-rhbz1320945-float128-6of9.patch
@@ -0,0 +1,114 @@
+commit c413c44801e449f1f0b9828b81770e752b8219af
+Author: Ulrich Weigand <ulrich.weigand@de.ibm.com>
+Date: Tue Sep 6 17:30:13 2016 +0200
+
+ Remove TYPE_NOSIGN "char" hack
+
+ init_type (and arch_integer_type) currently use a special hack to set the
+ TYPE_NOSIGN flag if the type name is exactly "char". This commit moves the
+ hack up to the callers of those routines.
+
+ The special case currently can hit only for types created from dwarf2read,
+ but read_base_type actually implements the "char" check itself, so it is
+ redundant to do it in init_type as well. (Note that stabsread.c and the
+ other type readers always pass NULL as name to init_type, so the special
+ case can never hit for those.)
+
+ A few other cases create pre-definded types with a hard-coded name of "char";
+ the commit simply moves setting the TYPE_NOSIGN flag to those places.
+
+ No functional change intended.
+
+ gdb/ChangeLog:
+
+ * gdbtypes.c (init_type): Remove "char" special case.
+ (arch_integer_type): Likewise.
+ (gdbtypes_post_init): Set TYPE_NOSIGN for "char" type.
+ (objfile_type): Likewise.
+ * mdebugread.c (basic_type): Likewise.
+ * stabsread.c (rs6000_builtin_type): Likewise.
+
+ Signed-off-by: Ulrich Weigand <ulrich.weigand@de.ibm.com>
+
+### a/gdb/ChangeLog
+### b/gdb/ChangeLog
+## -1,5 +1,14 @@
+ 2016-09-05 Ulrich Weigand <uweigand@de.ibm.com>
+
++ * gdbtypes.c (init_type): Remove "char" special case.
++ (arch_integer_type): Likewise.
++ (gdbtypes_post_init): Set TYPE_NOSIGN for "char" type.
++ (objfile_type): Likewise.
++ * mdebugread.c (basic_type): Likewise.
++ * stabsread.c (rs6000_builtin_type): Likewise.
++
++2016-09-05 Ulrich Weigand <uweigand@de.ibm.com>
++
+ * gdbtypes.h (enum type_flag_value): Remove.
+ Remove references to TYPE_FLAG_... in comments throughout.
+ * gdbtypes.c (recursive_dump_type): Do not print TYPE_FLAG_...
+Index: gdb-7.6.1/gdb/gdbtypes.c
+===================================================================
+--- gdb-7.6.1.orig/gdb/gdbtypes.c 2017-03-11 21:26:51.526852141 +0100
++++ gdb-7.6.1/gdb/gdbtypes.c 2017-03-11 21:27:01.268920712 +0100
+@@ -2137,11 +2137,6 @@
+
+ TYPE_NAME (type) = name;
+
+- /* C++ fancies. */
+-
+- if (name && strcmp (name, "char") == 0)
+- TYPE_NOSIGN (type) = 1;
+-
+ return type;
+ }
+
+@@ -4060,8 +4055,6 @@
+ t = arch_type (gdbarch, TYPE_CODE_INT, bit / TARGET_CHAR_BIT, name);
+ if (unsigned_p)
+ TYPE_UNSIGNED (t) = 1;
+- if (name && strcmp (name, "char") == 0)
+- TYPE_NOSIGN (t) = 1;
+
+ return t;
+ }
+@@ -4305,6 +4298,7 @@
+ builtin_type->builtin_char
+ = arch_integer_type (gdbarch, TARGET_CHAR_BIT,
+ !gdbarch_char_signed (gdbarch), "char");
++ TYPE_NOSIGN (builtin_type->builtin_char) = 1;
+ builtin_type->builtin_signed_char
+ = arch_integer_type (gdbarch, TARGET_CHAR_BIT,
+ 0, "signed char");
+@@ -4448,6 +4442,7 @@
+ objfile_type->builtin_char
+ = init_integer_type (objfile, TARGET_CHAR_BIT,
+ !gdbarch_char_signed (gdbarch), "char");
++ TYPE_NOSIGN (objfile_type->builtin_char) = 1;
+ objfile_type->builtin_signed_char
+ = init_integer_type (objfile, TARGET_CHAR_BIT,
+ 0, "signed char");
+Index: gdb-7.6.1/gdb/mdebugread.c
+===================================================================
+--- gdb-7.6.1.orig/gdb/mdebugread.c 2017-03-11 21:26:51.527852149 +0100
++++ gdb-7.6.1/gdb/mdebugread.c 2017-03-11 21:27:01.269920719 +0100
+@@ -1380,6 +1380,7 @@
+
+ case btChar:
+ tp = init_integer_type (objfile, 8, 0, "char");
++ TYPE_NOSIGN (tp) = 1;
+ break;
+
+ case btUChar:
+Index: gdb-7.6.1/gdb/stabsread.c
+===================================================================
+--- gdb-7.6.1.orig/gdb/stabsread.c 2017-03-11 21:26:51.529852163 +0100
++++ gdb-7.6.1/gdb/stabsread.c 2017-03-11 21:27:01.271920733 +0100
+@@ -2102,6 +2102,7 @@
+ break;
+ case 2:
+ rettype = init_integer_type (objfile, 8, 0, "char");
++ TYPE_NOSIGN (rettype) = 1;
+ break;
+ case 3:
+ rettype = init_integer_type (objfile, 16, 0, "short");
diff --git a/SOURCES/gdb-rhbz1320945-float128-7of9.patch b/SOURCES/gdb-rhbz1320945-float128-7of9.patch
new file mode 100644
index 0000000..f1810d2
--- /dev/null
+++ b/SOURCES/gdb-rhbz1320945-float128-7of9.patch
@@ -0,0 +1,215 @@
+commit 49f190bcb7f074ea2e27d4e967e4fae9ed7dafb6
+Author: Ulrich Weigand <ulrich.weigand@de.ibm.com>
+Date: Tue Sep 6 17:31:03 2016 +0200
+
+ Add missing format for built-in floating-point types
+
+ Many callers of init_float_type and arch_float_type still pass a NULL
+ floatformat. This commit changes those callers where the floatformat
+ that is supposed to be use is obvious. There are two categories where
+ this is the case:
+
+ - A number of built-in types are intended to match the platform ABI
+ floating-point types (i.e. types that use gdbarch_float_bit etc.).
+ Those places should use the platform ABI floating-point formats
+ defined via gdbarch_float_format etc.
+
+ - A number of language built-in types should simply use IEEE floating-
+ point formats, since the language actually defines that this is the
+ format that must be used to implement floating-point types for this
+ language. (This affects Java, Go, and Rust.) The same applies for
+ to the predefined "RS/6000" stabs floating-point built-in types.
+
+ gdb/ChangeLog:
+
+ * ada-lang.c (ada_language_arch_info): Use gdbarch-provided
+ platform ABI floating-point formats for built-in types.
+ * d-lang.c (build_d_types): Likewise.
+ * f-lang.c (build_fortran_types): Likewise.
+ * m2-lang.c (build_m2_types): Likewise.
+ * mdebugread.c (basic_type): Likewise.
+
+ * go-lang.c (build_go_types): Use IEEE floating-point formats
+ for language built-in types as mandanted by the language.
+ * jv-lang.c (build_java_types): Likewise.
+ * rust-lang.c (rust_language_arch_info): Likewise.
+ * stabsread.c (rs6000_builtin_type): Likewise.
+
+ Signed-off-by: Ulrich Weigand <ulrich.weigand@de.ibm.com>
+
+### a/gdb/ChangeLog
+### b/gdb/ChangeLog
+## -1,5 +1,20 @@
+ 2016-09-05 Ulrich Weigand <uweigand@de.ibm.com>
+
++ * ada-lang.c (ada_language_arch_info): Use gdbarch-provided
++ platform ABI floating-point formats for built-in types.
++ * d-lang.c (build_d_types): Likewise.
++ * f-lang.c (build_fortran_types): Likewise.
++ * m2-lang.c (build_m2_types): Likewise.
++ * mdebugread.c (basic_type): Likewise.
++
++ * go-lang.c (build_go_types): Use IEEE floating-point formats
++ for language built-in types as mandanted by the language.
++ * jv-lang.c (build_java_types): Likewise.
++ * rust-lang.c (rust_language_arch_info): Likewise.
++ * stabsread.c (rs6000_builtin_type): Likewise.
++
++2016-09-05 Ulrich Weigand <uweigand@de.ibm.com>
++
+ * gdbtypes.c (init_type): Remove "char" special case.
+ (arch_integer_type): Likewise.
+ (gdbtypes_post_init): Set TYPE_NOSIGN for "char" type.
+Index: gdb-7.6.1/gdb/ada-lang.c
+===================================================================
+--- gdb-7.6.1.orig/gdb/ada-lang.c 2017-03-11 21:30:58.630560198 +0100
++++ gdb-7.6.1/gdb/ada-lang.c 2017-03-11 21:31:01.661580871 +0100
+@@ -12666,16 +12666,16 @@
+ = arch_integer_type (gdbarch, TARGET_CHAR_BIT, 0, "character");
+ lai->primitive_type_vector [ada_primitive_type_float]
+ = arch_float_type (gdbarch, gdbarch_float_bit (gdbarch),
+- "float", NULL);
++ "float", gdbarch_float_format (gdbarch));
+ lai->primitive_type_vector [ada_primitive_type_double]
+ = arch_float_type (gdbarch, gdbarch_double_bit (gdbarch),
+- "long_float", NULL);
++ "long_float", gdbarch_double_format (gdbarch));
+ lai->primitive_type_vector [ada_primitive_type_long_long]
+ = arch_integer_type (gdbarch, gdbarch_long_long_bit (gdbarch),
+ 0, "long_long_integer");
+ lai->primitive_type_vector [ada_primitive_type_long_double]
+ = arch_float_type (gdbarch, gdbarch_long_double_bit (gdbarch),
+- "long_long_float", NULL);
++ "long_long_float", gdbarch_long_double_format (gdbarch));
+ lai->primitive_type_vector [ada_primitive_type_natural]
+ = arch_integer_type (gdbarch, gdbarch_int_bit (gdbarch),
+ 0, "natural");
+Index: gdb-7.6.1/gdb/f-lang.c
+===================================================================
+--- gdb-7.6.1.orig/gdb/f-lang.c 2017-03-11 21:30:58.631560204 +0100
++++ gdb-7.6.1/gdb/f-lang.c 2017-03-11 21:31:01.662580878 +0100
+@@ -312,13 +312,13 @@
+
+ builtin_f_type->builtin_real
+ = arch_float_type (gdbarch, gdbarch_float_bit (gdbarch),
+- "real", NULL);
++ "real", gdbarch_float_format (gdbarch));
+ builtin_f_type->builtin_real_s8
+ = arch_float_type (gdbarch, gdbarch_double_bit (gdbarch),
+- "real*8", NULL);
++ "real*8", gdbarch_double_format (gdbarch));
+ builtin_f_type->builtin_real_s16
+ = arch_float_type (gdbarch, gdbarch_long_double_bit (gdbarch),
+- "real*16", NULL);
++ "real*16", gdbarch_long_double_format (gdbarch));
+
+ builtin_f_type->builtin_complex_s8
+ = arch_complex_type (gdbarch, "complex*8",
+Index: gdb-7.6.1/gdb/go-lang.c
+===================================================================
+--- gdb-7.6.1.orig/gdb/go-lang.c 2017-03-11 21:30:58.632560211 +0100
++++ gdb-7.6.1/gdb/go-lang.c 2017-03-11 21:31:01.662580878 +0100
+@@ -634,9 +634,9 @@
+ builtin_go_type->builtin_uint64
+ = arch_integer_type (gdbarch, 64, 1, "uint64");
+ builtin_go_type->builtin_float32
+- = arch_float_type (gdbarch, 32, "float32", NULL);
++ = arch_float_type (gdbarch, 32, "float32", floatformats_ieee_single);
+ builtin_go_type->builtin_float64
+- = arch_float_type (gdbarch, 64, "float64", NULL);
++ = arch_float_type (gdbarch, 64, "float64", floatformats_ieee_double);
+ builtin_go_type->builtin_complex64
+ = arch_complex_type (gdbarch, "complex64",
+ builtin_go_type->builtin_float32);
+Index: gdb-7.6.1/gdb/jv-lang.c
+===================================================================
+--- gdb-7.6.1.orig/gdb/jv-lang.c 2017-03-11 21:30:58.632560211 +0100
++++ gdb-7.6.1/gdb/jv-lang.c 2017-03-11 21:31:01.662580878 +0100
+@@ -1220,9 +1220,9 @@
+ builtin_java_type->builtin_char
+ = arch_character_type (gdbarch, 16, 1, "char");
+ builtin_java_type->builtin_float
+- = arch_float_type (gdbarch, 32, "float", NULL);
++ = arch_float_type (gdbarch, 32, "float", floatformats_ieee_single);
+ builtin_java_type->builtin_double
+- = arch_float_type (gdbarch, 64, "double", NULL);
++ = arch_float_type (gdbarch, 64, "double", floatformats_ieee_double);
+ builtin_java_type->builtin_void
+ = arch_type (gdbarch, TYPE_CODE_VOID, 1, "void");
+
+Index: gdb-7.6.1/gdb/m2-lang.c
+===================================================================
+--- gdb-7.6.1.orig/gdb/m2-lang.c 2017-03-11 21:30:58.633560218 +0100
++++ gdb-7.6.1/gdb/m2-lang.c 2017-03-11 21:31:01.662580878 +0100
+@@ -406,7 +406,8 @@
+ builtin_m2_type->builtin_card
+ = arch_integer_type (gdbarch, gdbarch_int_bit (gdbarch), 1, "CARDINAL");
+ builtin_m2_type->builtin_real
+- = arch_float_type (gdbarch, gdbarch_float_bit (gdbarch), "REAL", NULL);
++ = arch_float_type (gdbarch, gdbarch_float_bit (gdbarch), "REAL",
++ gdbarch_float_format (gdbarch));
+ builtin_m2_type->builtin_char
+ = arch_character_type (gdbarch, TARGET_CHAR_BIT, 1, "CHAR");
+ builtin_m2_type->builtin_bool
+Index: gdb-7.6.1/gdb/mdebugread.c
+===================================================================
+--- gdb-7.6.1.orig/gdb/mdebugread.c 2017-03-11 21:30:58.634560225 +0100
++++ gdb-7.6.1/gdb/mdebugread.c 2017-03-11 21:31:01.664580891 +0100
+@@ -1413,12 +1413,12 @@
+
+ case btFloat:
+ tp = init_float_type (objfile, gdbarch_float_bit (gdbarch),
+- "float", NULL);
++ "float", gdbarch_float_format (gdbarch));
+ break;
+
+ case btDouble:
+ tp = init_float_type (objfile, gdbarch_double_bit (gdbarch),
+- "double", NULL);
++ "double", gdbarch_double_format (gdbarch));
+ break;
+
+ case btComplex:
+Index: gdb-7.6.1/gdb/stabsread.c
+===================================================================
+--- gdb-7.6.1.orig/gdb/stabsread.c 2017-03-11 21:30:58.636560239 +0100
++++ gdb-7.6.1/gdb/stabsread.c 2017-03-11 21:31:01.665580898 +0100
+@@ -2133,17 +2133,20 @@
+ break;
+ case 12:
+ /* IEEE single precision (32 bit). */
+- rettype = init_float_type (objfile, 32, "float", NULL);
++ rettype = init_float_type (objfile, 32, "float",
++ floatformats_ieee_single);
+ break;
+ case 13:
+ /* IEEE double precision (64 bit). */
+- rettype = init_float_type (objfile, 64, "double", NULL);
++ rettype = init_float_type (objfile, 64, "double",
++ floatformats_ieee_double);
+ break;
+ case 14:
+ /* This is an IEEE double on the RS/6000, and different machines with
+ different sizes for "long double" should use different negative
+ type numbers. See stabs.texinfo. */
+- rettype = init_float_type (objfile, 64, "long double", NULL);
++ rettype = init_float_type (objfile, 64, "long double",
++ floatformats_ieee_double);
+ break;
+ case 15:
+ rettype = init_integer_type (objfile, 32, 0, "integer");
+@@ -2152,10 +2155,12 @@
+ rettype = init_boolean_type (objfile, 32, 1, "boolean");
+ break;
+ case 17:
+- rettype = init_float_type (objfile, 32, "short real", NULL);
++ rettype = init_float_type (objfile, 32, "short real",
++ floatformats_ieee_single);
+ break;
+ case 18:
+- rettype = init_float_type (objfile, 64, "real", NULL);
++ rettype = init_float_type (objfile, 64, "real",
++ floatformats_ieee_double);
+ break;
+ case 19:
+ rettype = init_type (objfile, TYPE_CODE_ERROR, 0, "stringptr");
diff --git a/SOURCES/gdb-rhbz1320945-float128-8of9.patch b/SOURCES/gdb-rhbz1320945-float128-8of9.patch
new file mode 100644
index 0000000..3d4a399
--- /dev/null
+++ b/SOURCES/gdb-rhbz1320945-float128-8of9.patch
@@ -0,0 +1,419 @@
+commit 9b790ce7227fa346d08a41462119e9a3e93f5e80
+Author: Ulrich Weigand <ulrich.weigand@de.ibm.com>
+Date: Tue Sep 6 17:31:53 2016 +0200
+
+ Add gdbarch callback to provide formats for debug info float types
+
+ At this point, all TYPE_CODE_FLT types carry their floating-point format,
+ except for those creating from reading DWARF or stabs debug info. Those
+ will be addressed by this commit.
+
+ The main issue here is that we actually have to determine which floating-
+ point format to use. Currently, we only have the type length as input
+ to this decision. In the future, we may hopefully get --at least in
+ DWARF-- additional information to help disambiguate multiple different
+ formats of the same length. For now, we can still look at the type name
+ as a hint.
+
+ This decision logic is encapsulated in a gdbarch callback to allow
+ platform-specific overrides. The default implementation use the same
+ logic (compare type length against the various gdbarch_..._bit sizes)
+ that is currently implemented in floatformat_from_length.
+
+ With this commit, all platforms still use the default logic, so there
+ should be no actual change in behavior. A follow-on commit will add
+ support for __float128 on Intel and Power.
+
+ Once dwarf2read.c and stabsread.c make use of the new callback to
+ determine floating-point formats, we're now sure every TYPE_CODE_FLT
+ type will always carry its format. The commit therefore adds asserts
+ to verify_floatformat to ensure new code will continue to always
+ provide formats, and removes the code in floatformat_from_type that
+ used to handle types with a NULL TYPE_FLOATFORMAT.
+
+ gdb/ChangeLog:
+
+ * gdbarch.sh (floatformat_for_type): New gdbarch callback.
+ * gdbarch.h, gdbarch.c: Re-generate.
+ * arch-utils.h (default_floatformat_for_type): New prototype.
+ * arch-utils.c (default_floatformat_for_type): New function.
+
+ * doublest.c (floatformat_from_length): Remove.
+ (floatformat_from_type): Assume TYPE_FLOATFORMAT is non-NULL.
+ * gdbtypes.c (verify_floatformat): Require non-NULL format.
+
+ * dwarf2read.c (dwarf2_init_float_type): New function.
+ (read_base_type): Use it.
+ * stabsread.c (dbx_init_float_type): New function.
+ (read_sun_floating_type): Use it.
+ (read_range_type): Likewise.
+
+ Signed-off-by: Ulrich Weigand <ulrich.weigand@de.ibm.com>
+
+### a/gdb/ChangeLog
+### b/gdb/ChangeLog
+## -1,5 +1,22 @@
+ 2016-09-05 Ulrich Weigand <uweigand@de.ibm.com>
+
++ * gdbarch.sh (floatformat_for_type): New gdbarch callback.
++ * gdbarch.h, gdbarch.c: Re-generate.
++ * arch-utils.h (default_floatformat_for_type): New prototype.
++ * arch-utils.c (default_floatformat_for_type): New function.
++
++ * doublest.c (floatformat_from_length): Remove.
++ (floatformat_from_type): Assume TYPE_FLOATFORMAT is non-NULL.
++ * gdbtypes.c (verify_floatformat): Require non-NULL format.
++
++ * dwarf2read.c (dwarf2_init_float_type): New function.
++ (read_base_type): Use it.
++ * stabsread.c (dbx_init_float_type): New function.
++ (read_sun_floating_type): Use it.
++ (read_range_type): Likewise.
++
++2016-09-05 Ulrich Weigand <uweigand@de.ibm.com>
++
+ * ada-lang.c (ada_language_arch_info): Use gdbarch-provided
+ platform ABI floating-point formats for built-in types.
+ * d-lang.c (build_d_types): Likewise.
+Index: gdb-7.6.1/gdb/arch-utils.c
+===================================================================
+--- gdb-7.6.1.orig/gdb/arch-utils.c 2017-03-11 21:42:26.681253106 +0100
++++ gdb-7.6.1/gdb/arch-utils.c 2017-03-11 21:48:54.872873908 +0100
+@@ -216,6 +216,34 @@
+ *frame_offset = 0;
+ }
+
++/* Return a floating-point format for a floating-point variable of
++ length LEN in bits. If non-NULL, NAME is the name of its type.
++ If no suitable type is found, return NULL. */
++
++const struct floatformat **
++default_floatformat_for_type (struct gdbarch *gdbarch,
++ const char *name, int len)
++{
++ const struct floatformat **format = NULL;
++
++ if (len == gdbarch_half_bit (gdbarch))
++ format = gdbarch_half_format (gdbarch);
++ else if (len == gdbarch_float_bit (gdbarch))
++ format = gdbarch_float_format (gdbarch);
++ else if (len == gdbarch_double_bit (gdbarch))
++ format = gdbarch_double_format (gdbarch);
++ else if (len == gdbarch_long_double_bit (gdbarch))
++ format = gdbarch_long_double_format (gdbarch);
++ /* On i386 the 'long double' type takes 96 bits,
++ while the real number of used bits is only 80,
++ both in processor and in memory.
++ The code below accepts the real bit size. */
++ else if (gdbarch_long_double_format (gdbarch) != NULL
++ && len == gdbarch_long_double_format (gdbarch)[0]->totalsize)
++ format = gdbarch_long_double_format (gdbarch);
++
++ return format;
++}
+
+ int
+ generic_convert_register_p (struct gdbarch *gdbarch, int regnum,
+Index: gdb-7.6.1/gdb/arch-utils.h
+===================================================================
+--- gdb-7.6.1.orig/gdb/arch-utils.h 2017-03-11 21:42:26.681253106 +0100
++++ gdb-7.6.1/gdb/arch-utils.h 2017-03-11 21:48:54.872873908 +0100
+@@ -88,6 +88,11 @@
+
+ extern gdbarch_virtual_frame_pointer_ftype legacy_virtual_frame_pointer;
+
++/* Default implementation of gdbarch_floatformat_for_type. */
++extern const struct floatformat **
++ default_floatformat_for_type (struct gdbarch *gdbarch,
++ const char *name, int len);
++
+ extern CORE_ADDR generic_skip_trampoline_code (struct frame_info *frame,
+ CORE_ADDR pc);
+
+Index: gdb-7.6.1/gdb/doublest.c
+===================================================================
+--- gdb-7.6.1.orig/gdb/doublest.c 2017-03-11 21:42:26.681253106 +0100
++++ gdb-7.6.1/gdb/doublest.c 2017-03-11 21:51:53.062063411 +0100
+@@ -800,63 +800,16 @@
+ }
+
+
+-/* Return a floating-point format for a floating-point variable of
+- length LEN. If no suitable floating-point format is found, an
+- error is thrown.
+-
+- We need this functionality since information about the
+- floating-point format of a type is not always available to GDB; the
+- debug information typically only tells us the size of a
+- floating-point type.
+-
+- FIXME: kettenis/2001-10-28: In many places, particularly in
+- target-dependent code, the format of floating-point types is known,
+- but not passed on by GDB. This should be fixed. */
+-
+-static const struct floatformat *
+-floatformat_from_length (struct gdbarch *gdbarch, LONGEST len)
+-{
+- const struct floatformat *format;
+-
+- if (len * TARGET_CHAR_BIT == gdbarch_half_bit (gdbarch))
+- format = gdbarch_half_format (gdbarch)
+- [gdbarch_byte_order (gdbarch)];
+- else if (len * TARGET_CHAR_BIT == gdbarch_float_bit (gdbarch))
+- format = gdbarch_float_format (gdbarch)
+- [gdbarch_byte_order (gdbarch)];
+- else if (len * TARGET_CHAR_BIT == gdbarch_double_bit (gdbarch))
+- format = gdbarch_double_format (gdbarch)
+- [gdbarch_byte_order (gdbarch)];
+- else if (len * TARGET_CHAR_BIT == gdbarch_long_double_bit (gdbarch))
+- format = gdbarch_long_double_format (gdbarch)
+- [gdbarch_byte_order (gdbarch)];
+- /* On i386 the 'long double' type takes 96 bits,
+- while the real number of used bits is only 80,
+- both in processor and in memory.
+- The code below accepts the real bit size. */
+- else if ((gdbarch_long_double_format (gdbarch) != NULL)
+- && (len * TARGET_CHAR_BIT
+- == gdbarch_long_double_format (gdbarch)[0]->totalsize))
+- format = gdbarch_long_double_format (gdbarch)
+- [gdbarch_byte_order (gdbarch)];
+- else
+- format = NULL;
+- if (format == NULL)
+- error (_("Unrecognized %s-bit floating-point type."),
+- plongest (len * TARGET_CHAR_BIT));
+- return format;
+-}
++/* Return the floating-point format for a floating-point variable of
++ type TYPE. */
+
+ const struct floatformat *
+ floatformat_from_type (const struct type *type)
+ {
+ struct gdbarch *gdbarch = get_type_arch (type);
+
+- gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
+- if (TYPE_FLOATFORMAT (type) != NULL)
+- return TYPE_FLOATFORMAT (type)[gdbarch_byte_order (gdbarch)];
+- else
+- return floatformat_from_length (gdbarch, TYPE_LENGTH (type));
++ gdb_assert (TYPE_FLOATFORMAT (type));
++ return TYPE_FLOATFORMAT (type)[gdbarch_byte_order (gdbarch)];
+ }
+
+ /* Extract a floating-point number of type TYPE from a target-order
+Index: gdb-7.6.1/gdb/dwarf2read.c
+===================================================================
+--- gdb-7.6.1.orig/gdb/dwarf2read.c 2017-03-11 21:45:39.098565504 +0100
++++ gdb-7.6.1/gdb/dwarf2read.c 2017-03-11 21:48:54.877873941 +0100
+@@ -12901,6 +12901,27 @@
+ return this_type;
+ }
+
++/* Allocate a floating-point type of size BITS and name NAME. Pass NAME_HINT
++ (which may be different from NAME) to the architecture back-end to allow
++ it to guess the correct format if necessary. */
++
++static struct type *
++dwarf2_init_float_type (struct objfile *objfile, int bits, const char *name,
++ const char *name_hint)
++{
++ struct gdbarch *gdbarch = get_objfile_arch (objfile);
++ const struct floatformat **format;
++ struct type *type;
++
++ format = gdbarch_floatformat_for_type (gdbarch, name_hint, bits);
++ if (format)
++ type = init_float_type (objfile, bits, name, format);
++ else
++ type = init_type (objfile, TYPE_CODE_ERROR, bits / TARGET_CHAR_BIT, name);
++
++ return type;
++}
++
+ /* Find a representation of a given base type and install
+ it in the TYPE field of the die. */
+
+@@ -12941,14 +12962,14 @@
+ type = init_boolean_type (objfile, bits, 1, name);
+ break;
+ case DW_ATE_complex_float:
+- type = init_float_type (objfile, bits / 2, NULL, NULL);
++ type = dwarf2_init_float_type (objfile, bits / 2, NULL, name);
+ type = init_complex_type (objfile, name, type);
+ break;
+ case DW_ATE_decimal_float:
+ type = init_decfloat_type (objfile, bits, name);
+ break;
+ case DW_ATE_float:
+- type = init_float_type (objfile, bits, name, NULL);
++ type = dwarf2_init_float_type (objfile, bits, name, name);
+ break;
+ case DW_ATE_signed:
+ type = init_integer_type (objfile, bits, 0, name);
+Index: gdb-7.6.1/gdb/gdbarch.c
+===================================================================
+--- gdb-7.6.1.orig/gdb/gdbarch.c 2017-03-11 21:42:26.681253106 +0100
++++ gdb-7.6.1/gdb/gdbarch.c 2017-03-11 21:49:55.628279481 +0100
+@@ -181,6 +181,7 @@
+ const struct floatformat ** double_format;
+ int long_double_bit;
+ const struct floatformat ** long_double_format;
++ gdbarch_floatformat_for_type_ftype *floatformat_for_type;
+ int ptr_bit;
+ int addr_bit;
+ int dwarf2_addr_size;
+@@ -353,6 +354,7 @@
+ 0, /* double_format */
+ 8 * sizeof (long double), /* long_double_bit */
+ 0, /* long_double_format */
++ default_floatformat_for_type, /* floatformat_for_type */
+ 8 * sizeof (void*), /* ptr_bit */
+ 8 * sizeof (void*), /* addr_bit */
+ sizeof (void*), /* dwarf2_addr_size */
+@@ -438,7 +440,7 @@
+ default_register_reggroup_p, /* register_reggroup_p */
+ 0, /* fetch_pointer_argument */
+ 0, /* regset_from_core_section */
+- 0, /* core_regset_sections */
++ 0, /* iterate_over_regset_sections */
+ 0, /* make_corefile_notes */
+ 0, /* elfcore_write_linux_prpsinfo */
+ 0, /* find_memory_regions */
+@@ -530,6 +532,7 @@
+ gdbarch->float_bit = 4*TARGET_CHAR_BIT;
+ gdbarch->double_bit = 8*TARGET_CHAR_BIT;
+ gdbarch->long_double_bit = 8*TARGET_CHAR_BIT;
++ gdbarch->floatformat_for_type = default_floatformat_for_type;
+ gdbarch->ptr_bit = gdbarch->int_bit;
+ gdbarch->char_signed = -1;
+ gdbarch->virtual_frame_pointer = legacy_virtual_frame_pointer;
+@@ -652,6 +655,7 @@
+ /* Skip verify of long_double_bit, invalid_p == 0 */
+ if (gdbarch->long_double_format == 0)
+ gdbarch->long_double_format = floatformats_ieee_double;
++ /* Skip verify of floatformat_for_type, invalid_p == 0 */
+ /* Skip verify of ptr_bit, invalid_p == 0 */
+ if (gdbarch->addr_bit == 0)
+ gdbarch->addr_bit = gdbarch_ptr_bit (gdbarch);
+@@ -1021,6 +1025,9 @@
+ "gdbarch_dump: float_format = %s\n",
+ pformat (gdbarch->float_format));
+ fprintf_unfiltered (file,
++ "gdbarch_dump: floatformat_for_type = <%s>\n",
++ host_address_to_string (gdbarch->floatformat_for_type));
++ fprintf_unfiltered (file,
+ "gdbarch_dump: fp0_regnum = %s\n",
+ plongest (gdbarch->fp0_regnum));
+ fprintf_unfiltered (file,
+@@ -1738,6 +1745,23 @@
+ gdbarch->long_double_format = long_double_format;
+ }
+
++const struct floatformat **
++gdbarch_floatformat_for_type (struct gdbarch *gdbarch, const char *name, int length)
++{
++ gdb_assert (gdbarch != NULL);
++ gdb_assert (gdbarch->floatformat_for_type != NULL);
++ if (gdbarch_debug >= 2)
++ fprintf_unfiltered (gdb_stdlog, "gdbarch_floatformat_for_type called\n");
++ return gdbarch->floatformat_for_type (gdbarch, name, length);
++}
++
++void
++set_gdbarch_floatformat_for_type (struct gdbarch *gdbarch,
++ gdbarch_floatformat_for_type_ftype floatformat_for_type)
++{
++ gdbarch->floatformat_for_type = floatformat_for_type;
++}
++
+ int
+ gdbarch_ptr_bit (struct gdbarch *gdbarch)
+ {
+Index: gdb-7.6.1/gdb/gdbarch.h
+===================================================================
+--- gdb-7.6.1.orig/gdb/gdbarch.h 2017-03-11 21:42:26.681253106 +0100
++++ gdb-7.6.1/gdb/gdbarch.h 2017-03-11 21:48:54.879873955 +0100
+@@ -176,6 +176,14 @@
+ extern const struct floatformat ** gdbarch_long_double_format (struct gdbarch *gdbarch);
+ extern void set_gdbarch_long_double_format (struct gdbarch *gdbarch, const struct floatformat ** long_double_format);
+
++/* Returns the floating-point format to be used for values of length LENGTH.
++ NAME, if non-NULL, is the type name, which may be used to distinguish
++ different target formats of the same length. */
++
++typedef const struct floatformat ** (gdbarch_floatformat_for_type_ftype) (struct gdbarch *gdbarch, const char *name, int length);
++extern const struct floatformat ** gdbarch_floatformat_for_type (struct gdbarch *gdbarch, const char *name, int length);
++extern void set_gdbarch_floatformat_for_type (struct gdbarch *gdbarch, gdbarch_floatformat_for_type_ftype *floatformat_for_type);
++
+ /* For most targets, a pointer on the target and its representation as an
+ address in GDB have the same size and "look the same". For such a
+ target, you need only set gdbarch_ptr_bit and gdbarch_addr_bit
+Index: gdb-7.6.1/gdb/gdbarch.sh
+===================================================================
+--- gdb-7.6.1.orig/gdb/gdbarch.sh 2017-03-11 21:42:26.681253106 +0100
++++ gdb-7.6.1/gdb/gdbarch.sh 2017-03-11 21:48:54.880873961 +0100
+@@ -383,6 +383,11 @@
+ v:int:long_double_bit:::8 * sizeof (long double):8*TARGET_CHAR_BIT::0
+ v:const struct floatformat **:long_double_format:::::floatformats_ieee_double::pformat (gdbarch->long_double_format)
+
++# Returns the floating-point format to be used for values of length LENGTH.
++# NAME, if non-NULL, is the type name, which may be used to distinguish
++# different target formats of the same length.
++m:const struct floatformat **:floatformat_for_type:const char *name, int length:name, length:0:default_floatformat_for_type::0
++
+ # For most targets, a pointer on the target and its representation as an
+ # address in GDB have the same size and "look the same". For such a
+ # target, you need only set gdbarch_ptr_bit and gdbarch_addr_bit
+Index: gdb-7.6.1/gdb/stabsread.c
+===================================================================
+--- gdb-7.6.1.orig/gdb/stabsread.c 2017-03-11 21:48:47.133822245 +0100
++++ gdb-7.6.1/gdb/stabsread.c 2017-03-11 21:48:54.881873968 +0100
+@@ -338,6 +338,24 @@
+ return (*type_addr);
+ }
+
++/* Allocate a floating-point type of size BITS. */
++
++static struct type *
++dbx_init_float_type (struct objfile *objfile, int bits)
++{
++ struct gdbarch *gdbarch = get_objfile_arch (objfile);
++ const struct floatformat **format;
++ struct type *type;
++
++ format = gdbarch_floatformat_for_type (gdbarch, NULL, bits);
++ if (format)
++ type = init_float_type (objfile, bits, NULL, format);
++ else
++ type = init_type (objfile, TYPE_CODE_ERROR, bits / TARGET_CHAR_BIT, NULL);
++
++ return type;
++}
++
+ /* for all the stabs in a given stab vector, build appropriate types
+ and fix their symbols in given symbol vector. */
+
+@@ -3842,11 +3860,11 @@
+ if (details == NF_COMPLEX || details == NF_COMPLEX16
+ || details == NF_COMPLEX32)
+ {
+- rettype = init_float_type (objfile, nbits / 2, NULL, NULL);
++ rettype = dbx_init_float_type (objfile, nbits / 2);
+ return init_complex_type (objfile, NULL, rettype);
+ }
+
+- return init_float_type (objfile, nbits, NULL, NULL);
++ return dbx_init_float_type (objfile, nbits);
+ }
+
+ /* Read a number from the string pointed to by *PP.
+@@ -4133,7 +4151,7 @@
+ if (n3 == 0 && n2 > 0)
+ {
+ struct type *float_type
+- = init_float_type (objfile, n2 * TARGET_CHAR_BIT, NULL, NULL);
++ = dbx_init_float_type (objfile, n2 * TARGET_CHAR_BIT);
+
+ if (self_subrange)
+ return init_complex_type (objfile, NULL, float_type);
diff --git a/SOURCES/gdb-rhbz1320945-float128-9of9.patch b/SOURCES/gdb-rhbz1320945-float128-9of9.patch
new file mode 100644
index 0000000..3d58132
--- /dev/null
+++ b/SOURCES/gdb-rhbz1320945-float128-9of9.patch
@@ -0,0 +1,439 @@
+commit 00d5215ecec4fa0a78dcc37fec9425593753eb66
+Author: Ulrich Weigand <ulrich.weigand@de.ibm.com>
+Date: Tue Sep 6 17:33:15 2016 +0200
+
+ Support 128-bit IEEE floating-point types on Intel and Power
+
+ Now that all the prerequisites are in place, this commit finally adds support
+ for handling the __float128 type on Intel and Power, by providing appropriate
+ platform-specific versions of the floatformat_for_type callback.
+
+ Since at this point we do not yet have any indication in the debug info to
+ distinguish different floating-point formats of the same length, we simply
+ use the type name as hint. Types named "__float128" get the IEEE format.
+ In addition to handling "__float128" itself, we also recognize "_Float128"
+ and (on Power) "_Float64x", as well as the complex versions of those.
+ (As pointed out by Joseph Myers, starting with GCC 7, __float128 is just
+ a typedef for _Float128 -- but it's good to handle this anyway.)
+
+ A new test case does some simple verification that the format is decoded
+ correctly, using both __float128 and "long double" to make sure using both
+ in the same file still works. Another new test verifies handling of the
+ _FloatN and _FloatNx types supported by GCC 7, as well as the complex
+ versions of those types.
+
+ Note that this still only supports basic format decoding and encoding.
+ We do not yet support the GNU extension 'g' suffix for __float128 constants.
+ In addition, since all *arithmetic* on floating-point values is still
+ performed in native host "long double" arithmetic, if that format is not
+ able to encode all target __float128 values, we may get incorrect results.
+ (To fix this would require implementing fully synthetic target floating-
+ point arithmetic along the lines of GCC's real.c, presumably using MPFR.)
+
+ gdb/ChangeLog:
+
+ * i386-tdep.c (i386_floatformat_for_type): New function.
+ (i386_gdbarch_init): Install it.
+ * ppc-linux-tdep.c (ppc_floatformat_for_type): New function.
+ (ppc_linux_init_abi): Install it.
+
+ gdb/testsuite/ChangeLog:
+
+ * gdb.base/float128.c: New file.
+ * gdb.base/float128.exp: Likewise.
+ * gdb.base/floatn.c: Likewise.
+ * gdb.base/floatn.exp: Likewise.
+
+ Signed-off-by: Ulrich Weigand <ulrich.weigand@de.ibm.com>
+
+### a/gdb/ChangeLog
+### b/gdb/ChangeLog
+## -1,5 +1,12 @@
+ 2016-09-05 Ulrich Weigand <uweigand@de.ibm.com>
+
++ * i386-tdep.c (i386_floatformat_for_type): New function.
++ (i386_gdbarch_init): Install it.
++ * ppc-linux-tdep.c (ppc_floatformat_for_type): New function.
++ (ppc_linux_init_abi): Install it.
++
++2016-09-05 Ulrich Weigand <uweigand@de.ibm.com>
++
+ * gdbarch.sh (floatformat_for_type): New gdbarch callback.
+ * gdbarch.h, gdbarch.c: Re-generate.
+ * arch-utils.h (default_floatformat_for_type): New prototype.
+Index: gdb-7.6.1/gdb/i386-tdep.c
+===================================================================
+--- gdb-7.6.1.orig/gdb/i386-tdep.c 2017-03-11 22:05:54.267721188 +0100
++++ gdb-7.6.1/gdb/i386-tdep.c 2017-03-11 22:07:59.209585676 +0100
+@@ -7495,6 +7495,23 @@
+ }
+ }
+
++/* Return a floating-point format for a floating-point variable of
++ length LEN in bits. If non-NULL, NAME is the name of its type.
++ If no suitable type is found, return NULL. */
++
++static const struct floatformat **
++i386_floatformat_for_type (struct gdbarch *gdbarch,
++ const char *name, int len)
++{
++ if (len == 128 && name)
++ if (strcmp (name, "__float128") == 0
++ || strcmp (name, "_Float128") == 0
++ || strcmp (name, "complex _Float128") == 0)
++ return floatformats_ia64_quad;
++
++ return default_floatformat_for_type (gdbarch, name, len);
++}
++
+ static int
+ i386_validate_tdesc_p (struct gdbarch_tdep *tdep,
+ struct tdesc_arch_data *tdesc_data)
+@@ -7640,6 +7657,9 @@
+ alignment. */
+ set_gdbarch_long_double_bit (gdbarch, 96);
+
++ /* Support for floating-point data type variants. */
++ set_gdbarch_floatformat_for_type (gdbarch, i386_floatformat_for_type);
++
+ /* Register numbers of various important registers. */
+ set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */
+ set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */
+Index: gdb-7.6.1/gdb/ppc-linux-tdep.c
+===================================================================
+--- gdb-7.6.1.orig/gdb/ppc-linux-tdep.c 2017-03-11 22:05:54.267721188 +0100
++++ gdb-7.6.1/gdb/ppc-linux-tdep.c 2017-03-11 22:08:14.080688571 +0100
+@@ -1691,6 +1691,25 @@
+ record_tdep->ioctl_FIOQSIZE = 0x40086680;
+ }
+
++/* Return a floating-point format for a floating-point variable of
++ length LEN in bits. If non-NULL, NAME is the name of its type.
++ If no suitable type is found, return NULL. */
++
++static const struct floatformat **
++ppc_floatformat_for_type (struct gdbarch *gdbarch,
++ const char *name, int len)
++{
++ if (len == 128 && name)
++ if (strcmp (name, "__float128") == 0
++ || strcmp (name, "_Float128") == 0
++ || strcmp (name, "_Float64x") == 0
++ || strcmp (name, "complex _Float128") == 0
++ || strcmp (name, "complex _Float64x") == 0)
++ return floatformats_ia64_quad;
++
++ return default_floatformat_for_type (gdbarch, name, len);
++}
++
+ static void
+ ppc_linux_init_abi (struct gdbarch_info info,
+ struct gdbarch *gdbarch)
+@@ -1713,6 +1732,9 @@
+ set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT);
+ set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double);
+
++ /* Support for floating-point data type variants. */
++ set_gdbarch_floatformat_for_type (gdbarch, ppc_floatformat_for_type);
++
+ /* Handle inferior calls during interrupted system calls. */
+ set_gdbarch_write_pc (gdbarch, ppc_linux_write_pc);
+
+Index: gdb-7.6.1/gdb/testsuite/gdb.base/float128.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ gdb-7.6.1/gdb/testsuite/gdb.base/float128.c 2017-03-11 22:07:59.210585683 +0100
+@@ -0,0 +1,30 @@
++/* This testcase is part of GDB, the GNU debugger.
++
++ Copyright 2016 Free Software Foundation, Inc.
++
++ This program is free software; you can redistribute it and/or modify
++ it under the terms of the GNU General Public License as published by
++ the Free Software Foundation; either version 3 of the License, or
++ (at your option) any later version.
++
++ This program is distributed in the hope that it will be useful,
++ but WITHOUT ANY WARRANTY; without even the implied warranty of
++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ GNU General Public License for more details.
++
++ You should have received a copy of the GNU General Public License
++ along with this program. If not, see <http://www.gnu.org/licenses/>. */
++
++#include <stdio.h>
++#include <stdlib.h>
++
++long double ld;
++__float128 f128;
++
++int main()
++{
++ ld = 1.375l;
++ f128 = 2.375q;
++
++ return 0;
++}
+Index: gdb-7.6.1/gdb/testsuite/gdb.base/float128.exp
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ gdb-7.6.1/gdb/testsuite/gdb.base/float128.exp 2017-03-11 22:07:59.211585690 +0100
+@@ -0,0 +1,76 @@
++# Copyright 2016 Free Software Foundation, Inc.
++
++# This program is free software; you can redistribute it and/or modify
++# it under the terms of the GNU General Public License as published by
++# the Free Software Foundation; either version 3 of the License, or
++# (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program. If not, see <http://www.gnu.org/licenses/>.
++
++# This file is part of the gdb testsuite. It is intended to test that
++# gdb could correctly handle floating point constant with a suffix.
++
++standard_testfile .c
++
++proc do_compile { {opts {}} } {
++ global srcdir subdir srcfile binfile
++ set ccopts {debug quiet}
++ foreach opt $opts {lappend ccopts "additional_flags=$opt"}
++ gdb_compile "${srcdir}/${subdir}/${srcfile}" "$binfile" executable $ccopts
++}
++
++if { [do_compile] != "" && [do_compile {-mfloat128}] != "" } {
++ untested "compiler can't handle __float128 type?"
++ return -1
++}
++
++clean_restart ${binfile}
++
++if ![runto_main] then {
++ perror "couldn't run to breakpoint"
++ continue
++}
++
++# Run to the breakpoint at return.
++gdb_breakpoint [gdb_get_line_number "return"]
++gdb_continue_to_breakpoint "return"
++
++# Print the original value of ld and f128
++gdb_test "print ld" ".* = 1\\.375.*" "The original value of ld is 1.375"
++gdb_test "print f128" ".* = 2\\.375.*" "The original value of f128 is 2.375"
++
++# Test that gdb could correctly recognize float constant expression with a suffix.
++# FIXME: gdb does not yet recognize the GNU extension 'q' suffix for __float128 constants.
++gdb_test "print ld=-1.375l" ".* = -1\\.375.*" "Try to change ld to -1.375 with 'print ld=-1.375l'"
++gdb_test "print f128=-2.375l" ".* = -2\\.375.*" "Try to change f128 to -2.375 with 'print f128=-2.375l'"
++
++# Test that gdb could handle the above correctly with "set var" command.
++set test "set variable ld=10.375l"
++gdb_test_multiple "set var ld=10.375l" "$test" {
++ -re "$gdb_prompt $" {
++ pass "$test"
++ }
++ -re "Invalid number.*$gdb_prompt $" {
++ fail "$test (do not recognize 10.375l)"
++ }
++}
++
++set test "set variable f128=20.375l"
++gdb_test_multiple "set var f128=20.375l" "$test" {
++ -re "$gdb_prompt $" {
++ pass "$test"
++ }
++ -re "Invalid number.*$gdb_prompt $" {
++ fail "$test (do not recognize 20.375l)"
++ }
++}
++
++gdb_test "print ld" ".* = 10\\.375.*" "The value of ld is changed to 10.375"
++gdb_test "print f128" ".* = 20\\.375.*" "The value of f128 is changed to 20.375"
++
+Index: gdb-7.6.1/gdb/testsuite/gdb.base/floatn.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ gdb-7.6.1/gdb/testsuite/gdb.base/floatn.c 2017-03-11 22:07:59.211585690 +0100
+@@ -0,0 +1,48 @@
++/* This testcase is part of GDB, the GNU debugger.
++
++ Copyright 2016 Free Software Foundation, Inc.
++
++ This program is free software; you can redistribute it and/or modify
++ it under the terms of the GNU General Public License as published by
++ the Free Software Foundation; either version 3 of the License, or
++ (at your option) any later version.
++
++ This program is distributed in the hope that it will be useful,
++ but WITHOUT ANY WARRANTY; without even the implied warranty of
++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ GNU General Public License for more details.
++
++ You should have received a copy of the GNU General Public License
++ along with this program. If not, see <http://www.gnu.org/licenses/>. */
++
++#include <stdio.h>
++#include <stdlib.h>
++
++_Float32 f32;
++_Float64 f64;
++_Float128 f128;
++_Float32x f32x;
++_Float64x f64x;
++
++_Complex _Float32 c32;
++_Complex _Float64 c64;
++_Complex _Float128 c128;
++_Complex _Float32x c32x;
++_Complex _Float64x c64x;
++
++int main()
++{
++ f32 = 1.5f32;
++ f64 = 2.25f64;
++ f128 = 3.375f128;
++ f32x = 10.5f32x;
++ f64x = 20.25f64x;
++
++ c32 = 1.5f32 + 1.0if;
++ c64 = 2.25f64 + 1.0if;
++ c128 = 3.375f128 + 1.0if;
++ c32x = 10.5f32x + 1.0if;
++ c64x = 20.25f64x + 1.0if;
++
++ return 0;
++}
+Index: gdb-7.6.1/gdb/testsuite/gdb.base/floatn.exp
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ gdb-7.6.1/gdb/testsuite/gdb.base/floatn.exp 2017-03-11 22:07:59.211585690 +0100
+@@ -0,0 +1,124 @@
++# Copyright 2016 Free Software Foundation, Inc.
++
++# This program is free software; you can redistribute it and/or modify
++# it under the terms of the GNU General Public License as published by
++# the Free Software Foundation; either version 3 of the License, or
++# (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program. If not, see <http://www.gnu.org/licenses/>.
++
++# This file is part of the gdb testsuite. It is intended to test that
++# gdb could correctly handle floating point constant with a suffix.
++
++standard_testfile .c
++
++proc do_compile { {opts {}} } {
++ global srcdir subdir srcfile binfile
++ set ccopts {debug quiet}
++ foreach opt $opts {lappend ccopts "additional_flags=$opt"}
++ gdb_compile "${srcdir}/${subdir}/${srcfile}" "$binfile" executable $ccopts
++}
++
++if { [do_compile] != "" && [do_compile {-mfloat128}] != "" } {
++ untested "compiler can't handle _FloatN/_FloatNx types?"
++ return -1
++}
++
++clean_restart ${binfile}
++
++if ![runto_main] then {
++ perror "couldn't run to breakpoint"
++ continue
++}
++
++# Run to the breakpoint at return.
++gdb_breakpoint [gdb_get_line_number "return"]
++gdb_continue_to_breakpoint "return"
++
++# Print the original values of f32, f64, f128, f32x, f64x.
++gdb_test "print f32" ".* = 1\\.5.*" "The original value of f32 is 1.5"
++gdb_test "print f64" ".* = 2\\.25.*" "The original value of f64 is 2.25"
++gdb_test "print f128" ".* = 3\\.375.*" "The original value of f128 is 3.375"
++gdb_test "print f32x" ".* = 10\\.5.*" "The original value of f32x is 10.5"
++gdb_test "print f64x" ".* = 20\\.25.*" "The original value of f64x is 20.25"
++
++# Test that gdb could correctly recognize float constant expression with a suffix.
++# FIXME: gdb does not yet recognize the suffix for _FloatN/_FloatNx types.
++gdb_test "print f32=-1.5" ".* = -1\\.5.*" "Try to change f32 to -1.5 with 'print f32=-1.5'"
++gdb_test "print f64=-2.25" ".* = -2\\.25.*" "Try to change f64 to -2.25 with 'print f64=-2.25'"
++gdb_test "print f128=-3.375" ".* = -3\\.375.*" "Try to change f128 to -3.375 with 'print f128=-3.375'"
++gdb_test "print f32x=-10.5" ".* = -10\\.5.*" "Try to change f32x to -10.5 with 'print f32=-1.5x'"
++gdb_test "print f64x=-20.25" ".* = -20\\.25.*" "Try to change f64x to -20.25 with 'print f64=-2.25x'"
++
++# Test that gdb could handle the above correctly with "set var" command.
++set test "set variable f32 = 10.5"
++gdb_test_multiple "set var f32=10.5" "$test" {
++ -re "$gdb_prompt $" {
++ pass "$test"
++ }
++ -re "Invalid number.*$gdb_prompt $" {
++ fail "$test (do not recognize 10.5)"
++ }
++}
++
++set test "set variable f64 = 20.25"
++gdb_test_multiple "set var f64=20.25" "$test" {
++ -re "$gdb_prompt $" {
++ pass "$test"
++ }
++ -re "Invalid number.*$gdb_prompt $" {
++ fail "$test (do not recognize 20.25)"
++ }
++}
++
++set test "set variable f128 = 30.375"
++gdb_test_multiple "set var f128=30.375" "$test" {
++ -re "$gdb_prompt $" {
++ pass "$test"
++ }
++ -re "Invalid number.*$gdb_prompt $" {
++ fail "$test (do not recognize 30.375)"
++ }
++}
++
++set test "set variable f32x = 100.5"
++gdb_test_multiple "set var f32x=100.5" "$test" {
++ -re "$gdb_prompt $" {
++ pass "$test"
++ }
++ -re "Invalid number.*$gdb_prompt $" {
++ fail "$test (do not recognize 100.5)"
++ }
++}
++
++set test "set variable f64x = 200.25"
++gdb_test_multiple "set var f64x=200.25" "$test" {
++ -re "$gdb_prompt $" {
++ pass "$test"
++ }
++ -re "Invalid number.*$gdb_prompt $" {
++ fail "$test (do not recognize 200.25)"
++ }
++}
++
++gdb_test "print f32" ".* = 10\\.5.*" "The value of f32 is changed to 10.5"
++gdb_test "print f64" ".* = 20\\.25.*" "The value of f64 is changed to 20.25"
++gdb_test "print f128" ".* = 30\\.375.*" "The value of f128 is changed to 30.375"
++gdb_test "print f32x" ".* = 100\\.5.*" "The value of f32x is changed to 100.5"
++gdb_test "print f64x" ".* = 200\\.25.*" "The value of f64x is changed to 200.25"
++
++# Print the original values of c32, c64, c128, c32x, c64x.
++gdb_test "print c32" ".* = 1\\.5 \\+ 1 \\* I.*" "The original value of c32 is 1.5 + 1 * I"
++gdb_test "print c64" ".* = 2\\.25 \\+ 1 \\* I.*" "The original value of c64 is 2.25 + 1 * I"
++gdb_test "print c128" ".* = 3\\.375 \\+ 1 \\* I.*" "The original value of c128 is 3.375 + 1 * I"
++gdb_test "print c32x" ".* = 10\\.5 \\+ 1 \\* I.*" "The original value of c32x is 10.5 + 1 * I"
++gdb_test "print c64x" ".* = 20\\.25 \\+ 1 \\* I.*" "The original value of c64x is 20.25 + 1 * I"
++
++# FIXME: GDB cannot parse non-trivial complex constants yet.
++
diff --git a/SOURCES/gdb-rhbz1320945-power9-01of38.patch b/SOURCES/gdb-rhbz1320945-power9-01of38.patch
new file mode 100644
index 0000000..5be244b
--- /dev/null
+++ b/SOURCES/gdb-rhbz1320945-power9-01of38.patch
@@ -0,0 +1,187 @@
+commit 27b829ee701e29804216b3803fbaeb629be27491
+Author: Nick Clifton <nickc@redhat.com>
+Date: Wed Jan 29 13:46:39 2014 +0000
+
+ Following up on Tom's suggestion I am checking in a patch to replace the various
+ bfd_xxx_set macros with static inline functions, so that we can avoid compile time
+ warnings about comma expressions with unused values.
+
+ * bfd-in.h (bfd_set_section_vma): Delete.
+ (bfd_set_section_alignment): Delete.
+ (bfd_set_section_userdata): Delete.
+ (bfd_set_cacheable): Delete.
+ * bfd.c (bfd_set_cacheable): New static inline function.
+ * section.c (bfd_set_section_userdata): Likewise.
+ (bfd_set_section_vma): Likewise.
+ (bfd_set_section_alignment): Likewise.
+ * bfd-in2.h: Regenerate.
+
+### a/bfd/ChangeLog
+### b/bfd/ChangeLog
+## -1,3 +1,15 @@
++2014-01-29 Nick Clifton <nickc@redhat.com>
++
++ * bfd-in.h (bfd_set_section_vma): Delete.
++ (bfd_set_section_alignment): Delete.
++ (bfd_set_section_userdata): Delete.
++ (bfd_set_cacheable): Delete.
++ * bfd.c (bfd_set_cacheable): New static inline function.
++ * section.c (bfd_set_section_userdata): Likewise.
++ (bfd_set_section_vma): Likewise.
++ (bfd_set_section_alignment): Likewise.
++ * bfd-in2.h: Regenerate.
++
+ 2014-01-28 Nick Clifton <nickc@redhat.com>
+
+ * dwarf2.c (find_abstract_instance_name): For DW_FORM_ref_addr
+--- a/bfd/bfd-in.h
++++ b/bfd/bfd-in.h
+@@ -292,9 +292,6 @@ typedef struct bfd_section *sec_ptr;
+
+ #define bfd_is_com_section(ptr) (((ptr)->flags & SEC_IS_COMMON) != 0)
+
+-#define bfd_set_section_vma(bfd, ptr, val) (((ptr)->vma = (ptr)->lma = (val)), ((ptr)->user_set_vma = TRUE), TRUE)
+-#define bfd_set_section_alignment(bfd, ptr, val) (((ptr)->alignment_power = (val)),TRUE)
+-#define bfd_set_section_userdata(bfd, ptr, val) (((ptr)->userdata = (val)),TRUE)
+ /* Find the address one past the end of SEC. */
+ #define bfd_get_section_limit(bfd, sec) \
+ (((bfd)->direction != write_direction && (sec)->rawsize != 0 \
+@@ -517,8 +514,6 @@ extern void warn_deprecated (const char *, const char *, int, const char *);
+
+ #define bfd_get_symbol_leading_char(abfd) ((abfd)->xvec->symbol_leading_char)
+
+-#define bfd_set_cacheable(abfd,bool) (((abfd)->cacheable = bool), TRUE)
+-
+ extern bfd_boolean bfd_cache_close
+ (bfd *abfd);
+ /* NB: This declaration should match the autogenerated one in libbfd.h. */
+--- a/bfd/bfd-in2.h
++++ b/bfd/bfd-in2.h
+@@ -299,9 +299,6 @@ typedef struct bfd_section *sec_ptr;
+
+ #define bfd_is_com_section(ptr) (((ptr)->flags & SEC_IS_COMMON) != 0)
+
+-#define bfd_set_section_vma(bfd, ptr, val) (((ptr)->vma = (ptr)->lma = (val)), ((ptr)->user_set_vma = TRUE), TRUE)
+-#define bfd_set_section_alignment(bfd, ptr, val) (((ptr)->alignment_power = (val)),TRUE)
+-#define bfd_set_section_userdata(bfd, ptr, val) (((ptr)->userdata = (val)),TRUE)
+ /* Find the address one past the end of SEC. */
+ #define bfd_get_section_limit(bfd, sec) \
+ (((bfd)->direction != write_direction && (sec)->rawsize != 0 \
+@@ -524,8 +521,6 @@ extern void warn_deprecated (const char *, const char *, int, const char *);
+
+ #define bfd_get_symbol_leading_char(abfd) ((abfd)->xvec->symbol_leading_char)
+
+-#define bfd_set_cacheable(abfd,bool) (((abfd)->cacheable = bool), TRUE)
+-
+ extern bfd_boolean bfd_cache_close
+ (bfd *abfd);
+ /* NB: This declaration should match the autogenerated one in libbfd.h. */
+@@ -1029,7 +1024,7 @@ bfd *bfd_openr (const char *filename, const char *target);
+
+ bfd *bfd_fdopenr (const char *filename, const char *target, int fd);
+
+-bfd *bfd_openstreamr (const char *, const char *, void *);
++bfd *bfd_openstreamr (const char * filename, const char * target, void * stream);
+
+ bfd *bfd_openr_iovec (const char *filename, const char *target,
+ void *(*open_func) (struct bfd *nbfd,
+@@ -1596,6 +1591,32 @@ struct relax_table {
+ int size;
+ };
+
++/* Note: the following are provided as inline functions rather than macros
++ because not all callers use the return value. A macro implementation
++ would use a comma expression, eg: "((ptr)->foo = val, TRUE)" and some
++ compilers will complain about comma expressions that have no effect. */
++static inline bfd_boolean
++bfd_set_section_userdata (bfd * abfd ATTRIBUTE_UNUSED, asection * ptr, void * val)
++{
++ ptr->userdata = val;
++ return TRUE;
++}
++
++static inline bfd_boolean
++bfd_set_section_vma (bfd * abfd ATTRIBUTE_UNUSED, asection * ptr, bfd_vma val)
++{
++ ptr->vma = ptr->lma = val;
++ ptr->user_set_vma = TRUE;
++ return TRUE;
++}
++
++static inline bfd_boolean
++bfd_set_section_alignment (bfd * abfd ATTRIBUTE_UNUSED, asection * ptr, unsigned int val)
++{
++ ptr->alignment_power = val;
++ return TRUE;
++}
++
+ /* These sections are global, and are managed by BFD. The application
+ and target back end are not permitted to change the values in
+ these sections. */
+@@ -6415,6 +6436,14 @@ struct bfd
+ unsigned int selective_search : 1;
+ };
+
++/* See note beside bfd_set_section_userdata. */
++static inline bfd_boolean
++bfd_set_cacheable (bfd * abfd, bfd_boolean val)
++{
++ abfd->cacheable = val;
++ return TRUE;
++}
++
+ typedef enum bfd_error
+ {
+ bfd_error_no_error = 0,
+--- a/bfd/bfd.c
++++ b/bfd/bfd.c
+@@ -311,6 +311,14 @@ CODE_FRAGMENT
+ . unsigned int selective_search : 1;
+ .};
+ .
++.{* See note beside bfd_set_section_userdata. *}
++.static inline bfd_boolean
++.bfd_set_cacheable (bfd * abfd, bfd_boolean val)
++.{
++. abfd->cacheable = val;
++. return TRUE;
++.}
++.
+ */
+
+ #include "sysdep.h"
+--- a/bfd/section.c
++++ b/bfd/section.c
+@@ -542,6 +542,32 @@ CODE_FRAGMENT
+ . int size;
+ .};
+ .
++.{* Note: the following are provided as inline functions rather than macros
++. because not all callers use the return value. A macro implementation
++. would use a comma expression, eg: "((ptr)->foo = val, TRUE)" and some
++. compilers will complain about comma expressions that have no effect. *}
++.static inline bfd_boolean
++.bfd_set_section_userdata (bfd * abfd ATTRIBUTE_UNUSED, asection * ptr, void * val)
++.{
++. ptr->userdata = val;
++. return TRUE;
++.}
++.
++.static inline bfd_boolean
++.bfd_set_section_vma (bfd * abfd ATTRIBUTE_UNUSED, asection * ptr, bfd_vma val)
++.{
++. ptr->vma = ptr->lma = val;
++. ptr->user_set_vma = TRUE;
++. return TRUE;
++.}
++.
++.static inline bfd_boolean
++.bfd_set_section_alignment (bfd * abfd ATTRIBUTE_UNUSED, asection * ptr, unsigned int val)
++.{
++. ptr->alignment_power = val;
++. return TRUE;
++.}
++.
+ .{* These sections are global, and are managed by BFD. The application
+ . and target back end are not permitted to change the values in
+ . these sections. *}
diff --git a/SOURCES/gdb-rhbz1320945-power9-02of38.patch b/SOURCES/gdb-rhbz1320945-power9-02of38.patch
new file mode 100644
index 0000000..79d65ca
--- /dev/null
+++ b/SOURCES/gdb-rhbz1320945-power9-02of38.patch
@@ -0,0 +1,173 @@
+commit 45965137bee4946dca3cd99285f2a7afe6b99aeb
+Author: Alan Modra <amodra@gmail.com>
+Date: Wed Mar 5 19:57:39 2014 +1030
+
+ Support R_PPC64_ADDR64_LOCAL
+
+ This adds support for "func@localentry", an expression that returns the
+ ELFv2 local entry point address of function "func". I've excluded
+ dynamic relocation support because that obviously would require glibc
+ changes.
+
+ include/elf/
+ * ppc64.h (R_PPC64_REL24_NOTOC, R_PPC64_ADDR64_LOCAL): Define.
+ bfd/
+ * elf64-ppc.c (ppc64_elf_howto_raw): Add R_PPC64_ADDR64_LOCAL entry.
+ (ppc64_elf_reloc_type_lookup): Support R_PPC64_ADDR64_LOCAL.
+ (ppc64_elf_check_relocs): Likewise.
+ (ppc64_elf_relocate_section): Likewise.
+ * Add BFD_RELOC_PPC64_ADDR64_LOCAL.
+ * bfd-in2.h: Regenerate.
+ * libbfd.h: Regenerate.
+ gas/
+ * config/tc-ppc.c (ppc_elf_suffix): Support @localentry.
+ (md_apply_fix): Support R_PPC64_ADDR64_LOCAL.
+ ld/testsuite/
+ * ld-powerpc/elfv2-2a.s, ld-powerpc/elfv2-2b.s: New files.
+ * ld-powerpc/elfv2-2exe.d, ld-powerpc/elfv2-2so.d: New files.
+ * ld-powerpc/powerpc.exp: Run new test.
+ elfcpp/
+ * powerpc.h (R_PPC64_REL24_NOTOC, R_PPC64_ADDR64_LOCAL): Define.
+ gold/
+ * powerpc.cc (Target_powerpc::Scan::local, global): Support
+ R_PPC64_ADDR64_LOCAL.
+ (Target_powerpc::Relocate::relocate): Likewise.
+
+### a/bfd/ChangeLog
+### b/bfd/ChangeLog
+## -1,3 +1,13 @@
++2014-03-05 Alan Modra <amodra@gmail.com>
++
++ * elf64-ppc.c (ppc64_elf_howto_raw): Add R_PPC64_ADDR64_LOCAL entry.
++ (ppc64_elf_reloc_type_lookup): Support R_PPC64_ADDR64_LOCAL.
++ (ppc64_elf_check_relocs): Likewise.
++ (ppc64_elf_relocate_section): Likewise.
++ * Add BFD_RELOC_PPC64_ADDR64_LOCAL.
++ * bfd-in2.h: Regenerate.
++ * libbfd.h: Regenerate.
++
+ 2014-03-04 Heiher <r@hev.cc>
+
+ * elfxx-mips.c (mips_set_isa_flags): Use E_MIPS_ARCH_64R2 for
+--- a/bfd/bfd-in2.h
++++ b/bfd/bfd-in2.h
+@@ -3259,6 +3259,7 @@ instruction. */
+ BFD_RELOC_PPC64_PLTGOT16_LO_DS,
+ BFD_RELOC_PPC64_ADDR16_HIGH,
+ BFD_RELOC_PPC64_ADDR16_HIGHA,
++ BFD_RELOC_PPC64_ADDR64_LOCAL,
+
+ /* PowerPC and PowerPC64 thread-local storage relocations. */
+ BFD_RELOC_PPC_TLS,
+--- a/bfd/elf64-ppc.c
++++ b/bfd/elf64-ppc.c
+@@ -2095,6 +2095,21 @@ static reloc_howto_type ppc64_elf_howto_raw[] = {
+ 0xffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
++ /* Like ADDR64, but use local entry point of function. */
++ HOWTO (R_PPC64_ADDR64_LOCAL, /* type */
++ 0, /* rightshift */
++ 4, /* size (0=byte, 1=short, 2=long, 4=64 bits) */
++ 64, /* bitsize */
++ FALSE, /* pc_relative */
++ 0, /* bitpos */
++ complain_overflow_dont, /* complain_on_overflow */
++ bfd_elf_generic_reloc, /* special_function */
++ "R_PPC64_ADDR64_LOCAL", /* name */
++ FALSE, /* partial_inplace */
++ 0, /* src_mask */
++ ONES (64), /* dst_mask */
++ FALSE), /* pcrel_offset */
++
+ /* GNU extension to record C++ vtable hierarchy. */
+ HOWTO (R_PPC64_GNU_VTINHERIT, /* type */
+ 0, /* rightshift */
+@@ -2383,6 +2398,8 @@ ppc64_elf_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
+ break;
+ case BFD_RELOC_HI16_S_PCREL: r = R_PPC64_REL16_HA;
+ break;
++ case BFD_RELOC_PPC64_ADDR64_LOCAL: r = R_PPC64_ADDR64_LOCAL;
++ break;
+ case BFD_RELOC_VTABLE_INHERIT: r = R_PPC64_GNU_VTINHERIT;
+ break;
+ case BFD_RELOC_VTABLE_ENTRY: r = R_PPC64_GNU_VTENTRY;
+@@ -5400,6 +5417,21 @@ ppc64_elf_check_relocs (bfd *abfd, struct bfd_link_info *info,
+ case R_PPC64_REL16_HA:
+ break;
+
++ /* Not supported as a dynamic relocation. */
++ case R_PPC64_ADDR64_LOCAL:
++ if (info->shared)
++ {
++ if (!ppc64_elf_howto_table[R_PPC64_ADDR32])
++ ppc_howto_init ();
++ info->callbacks->einfo (_("%P: %H: %s reloc unsupported "
++ "in shared libraries and PIEs.\n"),
++ abfd, sec, rel->r_offset,
++ ppc64_elf_howto_table[r_type]->name);
++ bfd_set_error (bfd_error_bad_value);
++ return FALSE;
++ }
++ break;
++
+ case R_PPC64_TOC16:
+ case R_PPC64_TOC16_DS:
+ htab->do_multi_toc = 1;
+@@ -14134,6 +14166,12 @@ ppc64_elf_relocate_section (bfd *output_bfd,
+ addend -= htab->elf.tls_sec->vma + DTP_OFFSET;
+ break;
+
++ case R_PPC64_ADDR64_LOCAL:
++ addend += PPC64_LOCAL_ENTRY_OFFSET (h != NULL
++ ? h->elf.other
++ : sym->st_other);
++ break;
++
+ case R_PPC64_DTPMOD64:
+ relocation = 1;
+ addend = 0;
+--- a/bfd/libbfd.h
++++ b/bfd/libbfd.h
+@@ -1401,6 +1401,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
+ "BFD_RELOC_PPC64_PLTGOT16_LO_DS",
+ "BFD_RELOC_PPC64_ADDR16_HIGH",
+ "BFD_RELOC_PPC64_ADDR16_HIGHA",
++ "BFD_RELOC_PPC64_ADDR64_LOCAL",
+ "BFD_RELOC_PPC_TLS",
+ "BFD_RELOC_PPC_TLSGD",
+ "BFD_RELOC_PPC_TLSLD",
+--- a/bfd/reloc.c
++++ b/bfd/reloc.c
+@@ -2899,6 +2899,8 @@ ENUMX
+ BFD_RELOC_PPC64_ADDR16_HIGH
+ ENUMX
+ BFD_RELOC_PPC64_ADDR16_HIGHA
++ENUMX
++ BFD_RELOC_PPC64_ADDR64_LOCAL
+ ENUMDOC
+ Power(rs6000) and PowerPC relocations.
+
+### a/include/elf/ChangeLog
+### b/include/elf/ChangeLog
+## -1,3 +1,7 @@
++2014-03-05 Alan Modra <amodra@gmail.com>
++
++ * ppc64.h (R_PPC64_REL24_NOTOC, R_PPC64_ADDR64_LOCAL): Define.
++
+ 2014-02-06 Andrew Pinski <apinski@cavium.com>
+
+ * mips.h (E_MIPS_MACH_OCTEON3): New machine flag.
+--- a/include/elf/ppc64.h
++++ b/include/elf/ppc64.h
+@@ -149,6 +149,10 @@ START_RELOC_NUMBERS (elf_ppc64_reloc_type)
+ RELOC_NUMBER (R_PPC64_DTPREL16_HIGH, 114)
+ RELOC_NUMBER (R_PPC64_DTPREL16_HIGHA, 115)
+
++/* Added for ELFv2. */
++ RELOC_NUMBER (R_PPC64_REL24_NOTOC, 116)
++ RELOC_NUMBER (R_PPC64_ADDR64_LOCAL, 117)
++
+ #ifndef RELOC_MACROS_GEN_FUNC
+ /* Fake relocation only used internally by ld. */
+ RELOC_NUMBER (R_PPC64_LO_DS_OPT, 128)
diff --git a/SOURCES/gdb-rhbz1320945-power9-03of38.patch b/SOURCES/gdb-rhbz1320945-power9-03of38.patch
new file mode 100644
index 0000000..af7bca6
--- /dev/null
+++ b/SOURCES/gdb-rhbz1320945-power9-03of38.patch
@@ -0,0 +1,228 @@
+commit b80eed39e2e813c37cffcb873dc4fdd03381383c
+Author: Alan Modra <amodra@gmail.com>
+Date: Fri Mar 7 10:14:30 2014 +1030
+
+ Better overflow checking for powerpc64 relocations
+
+ R_PPC64_ADDR16 is used in three contexts:
+ - .short data relocation
+ - 16-bit signed insn fields, eg. addi
+ - 16-bit unsigned insn fields, eg. ori
+ In the first case we want to allow both signed and unsigned 16-bit
+ values, the latter two ought to error if the field exceeds the range
+ of values allowed for 16-bit signed and unsigned integers
+ respectively. These conflicting requirements meant that ld had to
+ choose the least restrictive overflow checks, and thus it is possible
+ to construct testcases where an addi field overflows but is not
+ reported by ld. Many relocations dealing with 16-bit insn fields have
+ this problem. What's more, some relocations that are only ever used
+ for signed fields of instructions woodenly copied the lax overflow
+ checking of R_PPC64_ADDR16.
+
+ bfd/
+ * elf64-ppc.c (ppc64_elf_howto_raw): Use complain_overflow_signed
+ for R_PPC64_ADDR14, R_PPC64_ADDR14_BRTAKEN, R_PPC64_ADDR14_BRNTAKEN,
+ R_PPC64_SECTOFF, R_PPC64_ADDR16_DS, R_PPC64_SECTOFF_DS,
+ R_PPC64_REL16 entries. Use complain_overflow_dont for R_PPC64_TOC.
+ (ppc64_elf_relocate_section): Modify overflow test for 16-bit
+ fields in instructions to signed/unsigned according to whether
+ the field takes a signed or unsigned value.
+ gold/
+ * powerpc.cc (Powerpc_relocate_functions::Overflow_check): Add
+ CHECK_UNSIGNED, CHECK_LOW_INSN, CHECK_HIGH_INSN.
+ (Powerpc_relocate_functions::has_overflow_unsigned): New function.
+ (Powerpc_relocate_functions::has_overflow_bitfield,
+ overflowed): Use the above.
+ (Target_powerpc::Relocate::relocate): Correct overflow checking
+ for a number of relocations. Modify overflow test for 16-bit
+ fields in instructions to signed/unsigned according to whether
+ the field takes a signed or unsigned value.
+
+### a/bfd/ChangeLog
+### b/bfd/ChangeLog
+## -1,3 +1,13 @@
++2014-03-08 Alan Modra <amodra@gmail.com>
++
++ * elf64-ppc.c (ppc64_elf_howto_raw): Use complain_overflow_signed
++ for R_PPC64_ADDR14, R_PPC64_ADDR14_BRTAKEN, R_PPC64_ADDR14_BRNTAKEN,
++ R_PPC64_SECTOFF, R_PPC64_ADDR16_DS, R_PPC64_SECTOFF_DS,
++ R_PPC64_REL16 entries. Use complain_overflow_dont for R_PPC64_TOC.
++ (ppc64_elf_relocate_section): Modify overflow test for 16-bit
++ fields in instructions to signed/unsigned according to whether
++ the field takes a signed or unsigned value.
++
+ 2014-03-07 Pedro Alves <palves@redhat.com>
+
+ * rs6000-core.c (rs6000coff_core_p): Cast pointers to bfd_vma
+--- a/bfd/elf64-ppc.c
++++ b/bfd/elf64-ppc.c
+@@ -357,7 +357,7 @@ static reloc_howto_type ppc64_elf_howto_raw[] = {
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_signed, /* complain_on_overflow */
+ ppc64_elf_branch_reloc, /* special_function */
+ "R_PPC64_ADDR14", /* name */
+ FALSE, /* partial_inplace */
+@@ -374,7 +374,7 @@ static reloc_howto_type ppc64_elf_howto_raw[] = {
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_signed, /* complain_on_overflow */
+ ppc64_elf_brtaken_reloc, /* special_function */
+ "R_PPC64_ADDR14_BRTAKEN",/* name */
+ FALSE, /* partial_inplace */
+@@ -391,7 +391,7 @@ static reloc_howto_type ppc64_elf_howto_raw[] = {
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_signed, /* complain_on_overflow */
+ ppc64_elf_brtaken_reloc, /* special_function */
+ "R_PPC64_ADDR14_BRNTAKEN",/* name */
+ FALSE, /* partial_inplace */
+@@ -632,7 +632,6 @@ static reloc_howto_type ppc64_elf_howto_raw[] = {
+ 32, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+- /* FIXME: Verify. Was complain_overflow_bitfield. */
+ complain_overflow_signed, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_PPC64_REL32", /* name */
+@@ -727,7 +726,7 @@ static reloc_howto_type ppc64_elf_howto_raw[] = {
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_signed, /* complain_on_overflow */
+ ppc64_elf_sectoff_reloc, /* special_function */
+ "R_PPC64_SECTOFF", /* name */
+ FALSE, /* partial_inplace */
+@@ -1015,7 +1014,7 @@ static reloc_howto_type ppc64_elf_howto_raw[] = {
+ 64, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_dont, /* complain_on_overflow */
+ ppc64_elf_toc64_reloc, /* special_function */
+ "R_PPC64_TOC", /* name */
+ FALSE, /* partial_inplace */
+@@ -1103,7 +1102,7 @@ static reloc_howto_type ppc64_elf_howto_raw[] = {
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_signed, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_PPC64_ADDR16_DS", /* name */
+ FALSE, /* partial_inplace */
+@@ -1178,7 +1177,7 @@ static reloc_howto_type ppc64_elf_howto_raw[] = {
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_signed, /* complain_on_overflow */
+ ppc64_elf_sectoff_reloc, /* special_function */
+ "R_PPC64_SECTOFF_DS", /* name */
+ FALSE, /* partial_inplace */
+@@ -1950,7 +1949,7 @@ static reloc_howto_type ppc64_elf_howto_raw[] = {
+ 16, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_signed, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_PPC64_REL16", /* name */
+ FALSE, /* partial_inplace */
+@@ -12943,6 +12942,8 @@ ppc64_elf_relocate_section (bfd *output_bfd,
+ bfd_vma max_br_offset;
+ bfd_vma from;
+ const Elf_Internal_Rela orig_rel = *rel;
++ reloc_howto_type *howto;
++ struct reloc_howto_struct alt_howto;
+
+ r_type = ELF64_R_TYPE (rel->r_info);
+ r_symndx = ELF64_R_SYM (rel->r_info);
+@@ -14507,6 +14508,7 @@ ppc64_elf_relocate_section (bfd *output_bfd,
+ }
+
+ /* Do any further special processing. */
++ howto = ppc64_elf_howto_table[(int) r_type];
+ switch (r_type)
+ {
+ default:
+@@ -14581,7 +14583,7 @@ ppc64_elf_relocate_section (bfd *output_bfd,
+ info->callbacks->einfo
+ (_("%P: %H: error: %s not a multiple of %u\n"),
+ input_bfd, input_section, rel->r_offset,
+- ppc64_elf_howto_table[r_type]->name,
++ howto->name,
+ mask + 1);
+ bfd_set_error (bfd_error_bad_value);
+ ret = FALSE;
+@@ -14602,23 +14604,45 @@ ppc64_elf_relocate_section (bfd *output_bfd,
+ info->callbacks->einfo
+ (_("%P: %H: unresolvable %s against `%T'\n"),
+ input_bfd, input_section, rel->r_offset,
+- ppc64_elf_howto_table[(int) r_type]->name,
++ howto->name,
+ h->elf.root.root.string);
+ ret = FALSE;
+ }
+
+- r = _bfd_final_link_relocate (ppc64_elf_howto_table[(int) r_type],
+- input_bfd,
+- input_section,
+- contents,
+- rel->r_offset,
+- relocation,
+- addend);
++ /* 16-bit fields in insns mostly have signed values, but a
++ few insns have 16-bit unsigned values. Really, we should
++ have different reloc types. */
++ if (howto->complain_on_overflow != complain_overflow_dont
++ && howto->dst_mask == 0xffff
++ && (input_section->flags & SEC_CODE) != 0)
++ {
++ enum complain_overflow complain = complain_overflow_signed;
++
++ insn = bfd_get_32 (input_bfd, contents + (rel->r_offset & ~3));
++ if (howto->rightshift == 0
++ ? ((insn & (0x3f << 26)) == 28u << 26 /* andi */
++ || (insn & (0x3f << 26)) == 24u << 26 /* ori */
++ || (insn & (0x3f << 26)) == 26u << 26 /* xori */
++ || (insn & (0x3f << 26)) == 10u << 26 /* cmpli */)
++ : ((insn & (0x3f << 26)) == 29u << 26 /* andis */
++ || (insn & (0x3f << 26)) == 25u << 26 /* oris */
++ || (insn & (0x3f << 26)) == 27u << 26 /* xoris */))
++ complain = complain_overflow_unsigned;
++ if (howto->complain_on_overflow != complain)
++ {
++ alt_howto = *howto;
++ alt_howto.complain_on_overflow = complain;
++ howto = &alt_howto;
++ }
++ }
++
++ r = _bfd_final_link_relocate (howto, input_bfd, input_section, contents,
++ rel->r_offset, relocation, addend);
+
+ if (r != bfd_reloc_ok)
+ {
+ char *more_info = NULL;
+- const char *reloc_name = ppc64_elf_howto_table[r_type]->name;
++ const char *reloc_name = howto->name;
+
+ if (reloc_dest != DEST_NORMAL)
+ {
+@@ -14638,7 +14662,7 @@ ppc64_elf_relocate_section (bfd *output_bfd,
+ continue;
+ if (h != NULL
+ && h->elf.root.type == bfd_link_hash_undefweak
+- && ppc64_elf_howto_table[r_type]->pc_relative)
++ && howto->pc_relative)
+ {
+ /* Assume this is a call protected by other code that
+ detects the symbol is undefined. If this is the case,
diff --git a/SOURCES/gdb-rhbz1320945-power9-04of38.patch b/SOURCES/gdb-rhbz1320945-power9-04of38.patch
new file mode 100644
index 0000000..29ec134
--- /dev/null
+++ b/SOURCES/gdb-rhbz1320945-power9-04of38.patch
@@ -0,0 +1,819 @@
+commit 86c9573369616e7437481b6e5533aef3a435cdcf
+Author: Alan Modra <amodra@gmail.com>
+Date: Sat Mar 8 13:05:06 2014 +1030
+
+ Better overflow checking for powerpc32 relocations
+
+ Similar to the powerpc64 patch, this improves overflow checking in
+ elf32-ppc.c. Many reloc "howto" entries needed fixes, some just
+ cosmetic.
+
+ The patch also fixes the R_PPC_VLE_SDA21 reloc application code, which
+ was horribly broken. In fact, it may still be broken since Power ISA
+ 2.07 says e_li behaves as
+ RT <- EXTS(li20 1:4 || li20 5:8 || li20 0 || li20 9:19)
+ where li20 is a field taken from bits 17..20, 11..15, 21..31 of the
+ instruction. Freescale VLEPEM says differently, and I assume
+ correctly, that
+ RT <- EXTS(li20 0:3 || li20 4:8 || li20 9:19)
+ The VLE_SDA21 relocation description matches this too.
+
+ Now the VLE_SDA21 relocation specifies in the case where e_addi16 is
+ converted to e_li for symbols in .PPC.EMB.sdata0 or .PPC.EMB.sbss0
+ (no base register), that the field is restricted to 16 bits, with the
+ sign bit being propagated to the top 4 bits. I don't see the sense in
+ restricting the value like this, so have allowed the full 20 bit
+ signed value. This of course is compatible with the reloc description
+ in that values in the 16 bit signed range will result in exactly the
+ same insn field as when the reloc description is followed to the
+ letter.
+
+ * elf32-ppc.c (ppc_elf_howto_raw): Correct overflow check for
+ many relocations. Correct bitsize and rightshift too for a number
+ of VLE relocs. Describe R_PPC_VLE_SDA21 and R_PPC_VLE_SDA21_LO.
+ Correct dst_mask on R_PPC_VLE_SDA21_LO.
+ (ppc_elf_vle_split16): Tidy, delete unnecessary prototype.
+ (ppc_elf_relocate_section): Modify overflow test for 16-bit
+ fields in instructions to signed/unsigned according to whether
+ the field takes a signed or unsigned value. Tidy vle split16 code.
+ Correct R_PPC_VLE_SDA21 and R_PPC_VLE_SDA21_LO handling.
+
+### a/bfd/ChangeLog
+### b/bfd/ChangeLog
+## -1,5 +1,17 @@
+ 2014-03-08 Alan Modra <amodra@gmail.com>
+
++ * elf32-ppc.c (ppc_elf_howto_raw): Correct overflow check for
++ many relocations. Correct bitsize and rightshift too for a number
++ of VLE relocs. Describe R_PPC_VLE_SDA21 and R_PPC_VLE_SDA21_LO.
++ Correct dst_mask on R_PPC_VLE_SDA21_LO.
++ (ppc_elf_vle_split16): Tidy, delete unnecessary prototype.
++ (ppc_elf_relocate_section): Modify overflow test for 16-bit
++ fields in instructions to signed/unsigned according to whether
++ the field takes a signed or unsigned value. Tidy vle split16 code.
++ Correct R_PPC_VLE_SDA21 and R_PPC_VLE_SDA21_LO handling.
++
++2014-03-08 Alan Modra <amodra@gmail.com>
++
+ * elf64-ppc.c (ppc64_elf_howto_raw): Use complain_overflow_signed
+ for R_PPC64_ADDR14, R_PPC64_ADDR14_BRTAKEN, R_PPC64_ADDR14_BRNTAKEN,
+ R_PPC64_SECTOFF, R_PPC64_ADDR16_DS, R_PPC64_SECTOFF_DS,
+--- a/bfd/elf32-ppc.c
++++ b/bfd/elf32-ppc.c
+@@ -50,8 +50,6 @@ static bfd_reloc_status_type ppc_elf_addr16_ha_reloc
+ (bfd *, arelent *, asymbol *, void *, asection *, bfd *, char **);
+ static bfd_reloc_status_type ppc_elf_unhandled_reloc
+ (bfd *, arelent *, asymbol *, void *, asection *, bfd *, char **);
+-static void ppc_elf_vle_split16
+- (bfd *, bfd_byte *, bfd_vma, bfd_vma, split16_format_type);
+
+ /* Branch prediction bit for branch taken relocs. */
+ #define BRANCH_PREDICT_BIT 0x200000
+@@ -192,7 +190,7 @@ static reloc_howto_type ppc_elf_howto_raw[] = {
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_PPC_NONE", /* name */
+ FALSE, /* partial_inplace */
+@@ -207,7 +205,7 @@ static reloc_howto_type ppc_elf_howto_raw[] = {
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_PPC_ADDR32", /* name */
+ FALSE, /* partial_inplace */
+@@ -223,7 +221,7 @@ static reloc_howto_type ppc_elf_howto_raw[] = {
+ 26, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_signed, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_PPC_ADDR24", /* name */
+ FALSE, /* partial_inplace */
+@@ -300,7 +298,7 @@ static reloc_howto_type ppc_elf_howto_raw[] = {
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_signed, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_PPC_ADDR14", /* name */
+ FALSE, /* partial_inplace */
+@@ -317,7 +315,7 @@ static reloc_howto_type ppc_elf_howto_raw[] = {
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_signed, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_PPC_ADDR14_BRTAKEN",/* name */
+ FALSE, /* partial_inplace */
+@@ -334,7 +332,7 @@ static reloc_howto_type ppc_elf_howto_raw[] = {
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_signed, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_PPC_ADDR14_BRNTAKEN",/* name */
+ FALSE, /* partial_inplace */
+@@ -446,7 +444,7 @@ static reloc_howto_type ppc_elf_howto_raw[] = {
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_PPC_GOT16_HI", /* name */
+ FALSE, /* partial_inplace */
+@@ -462,7 +460,7 @@ static reloc_howto_type ppc_elf_howto_raw[] = {
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_dont, /* complain_on_overflow */
+ ppc_elf_addr16_ha_reloc, /* special_function */
+ "R_PPC_GOT16_HA", /* name */
+ FALSE, /* partial_inplace */
+@@ -497,7 +495,7 @@ static reloc_howto_type ppc_elf_howto_raw[] = {
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_PPC_COPY", /* name */
+ FALSE, /* partial_inplace */
+@@ -513,7 +511,7 @@ static reloc_howto_type ppc_elf_howto_raw[] = {
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_PPC_GLOB_DAT", /* name */
+ FALSE, /* partial_inplace */
+@@ -528,7 +526,7 @@ static reloc_howto_type ppc_elf_howto_raw[] = {
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_PPC_JMP_SLOT", /* name */
+ FALSE, /* partial_inplace */
+@@ -545,7 +543,7 @@ static reloc_howto_type ppc_elf_howto_raw[] = {
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_PPC_RELATIVE", /* name */
+ FALSE, /* partial_inplace */
+@@ -577,7 +575,7 @@ static reloc_howto_type ppc_elf_howto_raw[] = {
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_PPC_UADDR32", /* name */
+ FALSE, /* partial_inplace */
+@@ -607,7 +605,7 @@ static reloc_howto_type ppc_elf_howto_raw[] = {
+ 32, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_PPC_REL32", /* name */
+ FALSE, /* partial_inplace */
+@@ -623,7 +621,7 @@ static reloc_howto_type ppc_elf_howto_raw[] = {
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_PPC_PLT32", /* name */
+ FALSE, /* partial_inplace */
+@@ -639,7 +637,7 @@ static reloc_howto_type ppc_elf_howto_raw[] = {
+ 32, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_PPC_PLTREL32", /* name */
+ FALSE, /* partial_inplace */
+@@ -671,7 +669,7 @@ static reloc_howto_type ppc_elf_howto_raw[] = {
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_PPC_PLT16_HI", /* name */
+ FALSE, /* partial_inplace */
+@@ -687,7 +685,7 @@ static reloc_howto_type ppc_elf_howto_raw[] = {
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_dont, /* complain_on_overflow */
+ ppc_elf_addr16_ha_reloc, /* special_function */
+ "R_PPC_PLT16_HA", /* name */
+ FALSE, /* partial_inplace */
+@@ -718,7 +716,7 @@ static reloc_howto_type ppc_elf_howto_raw[] = {
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_signed, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_PPC_SECTOFF", /* name */
+ FALSE, /* partial_inplace */
+@@ -748,7 +746,7 @@ static reloc_howto_type ppc_elf_howto_raw[] = {
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_PPC_SECTOFF_HI", /* name */
+ FALSE, /* partial_inplace */
+@@ -763,7 +761,7 @@ static reloc_howto_type ppc_elf_howto_raw[] = {
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_dont, /* complain_on_overflow */
+ ppc_elf_addr16_ha_reloc, /* special_function */
+ "R_PPC_SECTOFF_HA", /* name */
+ FALSE, /* partial_inplace */
+@@ -1239,7 +1237,7 @@ static reloc_howto_type ppc_elf_howto_raw[] = {
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_PPC_EMB_NADDR32", /* name */
+ FALSE, /* partial_inplace */
+@@ -1254,7 +1252,7 @@ static reloc_howto_type ppc_elf_howto_raw[] = {
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_signed, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_PPC_EMB_NADDR16", /* name */
+ FALSE, /* partial_inplace */
+@@ -1449,10 +1447,10 @@ static reloc_howto_type ppc_elf_howto_raw[] = {
+ HOWTO (R_PPC_VLE_LO16A, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+- 32, /* bitsize */
++ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_PPC_VLE_LO16A", /* name */
+ FALSE, /* partial_inplace */
+@@ -1464,10 +1462,10 @@ static reloc_howto_type ppc_elf_howto_raw[] = {
+ HOWTO (R_PPC_VLE_LO16D, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+- 32, /* bitsize */
++ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_PPC_VLE_LO16D", /* name */
+ FALSE, /* partial_inplace */
+@@ -1477,12 +1475,12 @@ static reloc_howto_type ppc_elf_howto_raw[] = {
+
+ /* Bits 16-31 split16a format. */
+ HOWTO (R_PPC_VLE_HI16A, /* type */
+- 0, /* rightshift */
++ 16, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+- 32, /* bitsize */
++ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_PPC_VLE_HI16A", /* name */
+ FALSE, /* partial_inplace */
+@@ -1492,12 +1490,12 @@ static reloc_howto_type ppc_elf_howto_raw[] = {
+
+ /* Bits 16-31 split16d format. */
+ HOWTO (R_PPC_VLE_HI16D, /* type */
+- 0, /* rightshift */
++ 16, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+- 32, /* bitsize */
++ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_PPC_VLE_HI16D", /* name */
+ FALSE, /* partial_inplace */
+@@ -1507,12 +1505,12 @@ static reloc_howto_type ppc_elf_howto_raw[] = {
+
+ /* Bits 16-31 (High Adjusted) in split16a format. */
+ HOWTO (R_PPC_VLE_HA16A, /* type */
+- 0, /* rightshift */
++ 16, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+- 32, /* bitsize */
++ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_PPC_VLE_HA16A", /* name */
+ FALSE, /* partial_inplace */
+@@ -1522,12 +1520,12 @@ static reloc_howto_type ppc_elf_howto_raw[] = {
+
+ /* Bits 16-31 (High Adjusted) in split16d format. */
+ HOWTO (R_PPC_VLE_HA16D, /* type */
+- 0, /* rightshift */
++ 16, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+- 32, /* bitsize */
++ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_PPC_VLE_HA16D", /* name */
+ FALSE, /* partial_inplace */
+@@ -1535,14 +1533,16 @@ static reloc_howto_type ppc_elf_howto_raw[] = {
+ 0x1f07ff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+- /* This reloc does nothing. */
+- HOWTO (R_PPC_VLE_SDA21, /* type */
++ /* This reloc is like R_PPC_EMB_SDA21 but only applies to e_add16i
++ instructions. If the register base is 0 then the linker changes
++ the e_add16i to an e_li instruction. */
++ HOWTO (R_PPC_VLE_SDA21, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+- 32, /* bitsize */
++ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_signed, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_PPC_VLE_SDA21", /* name */
+ FALSE, /* partial_inplace */
+@@ -1550,29 +1550,29 @@ static reloc_howto_type ppc_elf_howto_raw[] = {
+ 0xffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+- /* This reloc does nothing. */
++ /* Like R_PPC_VLE_SDA21 but ignore overflow. */
+ HOWTO (R_PPC_VLE_SDA21_LO, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+- 32, /* bitsize */
++ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_PPC_VLE_SDA21_LO", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+- 0, /* dst_mask */
++ 0xffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* The 16 LSBS relative to _SDA_BASE_ in split16a format. */
+ HOWTO (R_PPC_VLE_SDAREL_LO16A,/* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+- 32, /* bitsize */
++ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_PPC_VLE_SDAREL_LO16A", /* name */
+ FALSE, /* partial_inplace */
+@@ -1581,14 +1581,13 @@ static reloc_howto_type ppc_elf_howto_raw[] = {
+ FALSE), /* pcrel_offset */
+
+ /* The 16 LSBS relative to _SDA_BASE_ in split16d format. */
+- /* This reloc does nothing. */
+ HOWTO (R_PPC_VLE_SDAREL_LO16D, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+- 32, /* bitsize */
++ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_PPC_VLE_SDAREL_LO16D", /* name */
+ FALSE, /* partial_inplace */
+@@ -1598,12 +1597,12 @@ static reloc_howto_type ppc_elf_howto_raw[] = {
+
+ /* Bits 16-31 relative to _SDA_BASE_ in split16a format. */
+ HOWTO (R_PPC_VLE_SDAREL_HI16A, /* type */
+- 0, /* rightshift */
++ 16, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+- 32, /* bitsize */
++ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_PPC_VLE_SDAREL_HI16A", /* name */
+ FALSE, /* partial_inplace */
+@@ -1613,12 +1612,12 @@ static reloc_howto_type ppc_elf_howto_raw[] = {
+
+ /* Bits 16-31 relative to _SDA_BASE_ in split16d format. */
+ HOWTO (R_PPC_VLE_SDAREL_HI16D, /* type */
+- 0, /* rightshift */
++ 16, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+- 32, /* bitsize */
++ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_PPC_VLE_SDAREL_HI16D", /* name */
+ FALSE, /* partial_inplace */
+@@ -1628,12 +1627,12 @@ static reloc_howto_type ppc_elf_howto_raw[] = {
+
+ /* Bits 16-31 (HA) relative to _SDA_BASE split16a format. */
+ HOWTO (R_PPC_VLE_SDAREL_HA16A, /* type */
+- 0, /* rightshift */
++ 16, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+- 32, /* bitsize */
++ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_PPC_VLE_SDAREL_HA16A", /* name */
+ FALSE, /* partial_inplace */
+@@ -1643,12 +1642,12 @@ static reloc_howto_type ppc_elf_howto_raw[] = {
+
+ /* Bits 16-31 (HA) relative to _SDA_BASE split16d format. */
+ HOWTO (R_PPC_VLE_SDAREL_HA16D, /* type */
+- 0, /* rightshift */
++ 16, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+- 32, /* bitsize */
++ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_PPC_VLE_SDAREL_HA16D", /* name */
+ FALSE, /* partial_inplace */
+@@ -1662,7 +1661,7 @@ static reloc_howto_type ppc_elf_howto_raw[] = {
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_PPC_IRELATIVE", /* name */
+ FALSE, /* partial_inplace */
+@@ -1677,7 +1676,7 @@ static reloc_howto_type ppc_elf_howto_raw[] = {
+ 16, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_signed, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_PPC_REL16", /* name */
+ FALSE, /* partial_inplace */
+@@ -4790,20 +4789,19 @@ ppc_elf_merge_private_bfd_data (bfd *ibfd, bfd *obfd)
+ }
+
+ static void
+-ppc_elf_vle_split16 (bfd *output_bfd, bfd_byte *contents,
+- bfd_vma offset, bfd_vma relocation,
+- split16_format_type split16_format)
++ppc_elf_vle_split16 (bfd *output_bfd, bfd_byte *loc,
++ bfd_vma value,
++ split16_format_type split16_format)
+
+ {
+- bfd_vma insn, top5, bottom11;
++ unsigned int insn, top5;
+
+- insn = bfd_get_32 (output_bfd, contents + offset);
+- top5 = relocation >> 11;
+- top5 = top5 << (split16_format == split16a_type ? 20 : 16);
+- bottom11 = relocation & 0x7ff;
++ insn = bfd_get_32 (output_bfd, loc);
++ top5 = value & 0xf800;
++ top5 = top5 << (split16_format == split16a_type ? 9 : 5);
+ insn |= top5;
+- insn |= bottom11;
+- bfd_put_32 (output_bfd, insn, contents + offset);
++ insn |= value & 0x7ff;
++ bfd_put_32 (output_bfd, insn, loc);
+ }
+
+
+@@ -7570,6 +7568,7 @@ ppc_elf_relocate_section (bfd *output_bfd,
+ bfd_boolean warned;
+ unsigned int tls_type, tls_mask, tls_gd;
+ struct plt_entry **ifunc;
++ struct reloc_howto_struct alt_howto;
+
+ r_type = ELF32_R_TYPE (rel->r_info);
+ sym = NULL;
+@@ -8252,9 +8251,9 @@ ppc_elf_relocate_section (bfd *output_bfd,
+ howto->name,
+ sym_name);
+ }
+- break;
++ break;
+
+- /* Relocations that need no special processing. */
++ /* Relocations that need no special processing. */
+ case R_PPC_LOCAL24PC:
+ /* It makes no sense to point a local relocation
+ at a symbol not in this object. */
+@@ -8743,45 +8742,39 @@ ppc_elf_relocate_section (bfd *output_bfd,
+ break;
+
+ case R_PPC_VLE_LO16A:
+- relocation = (relocation + addend) & 0xffff;
+- ppc_elf_vle_split16 (output_bfd, contents, rel->r_offset,
+- relocation, split16a_type);
++ relocation = relocation + addend;
++ ppc_elf_vle_split16 (output_bfd, contents + rel->r_offset,
++ relocation, split16a_type);
+ continue;
+
+ case R_PPC_VLE_LO16D:
+- relocation = (relocation + addend) & 0xffff;
+- ppc_elf_vle_split16 (output_bfd, contents, rel->r_offset,
+- relocation, split16d_type);
++ relocation = relocation + addend;
++ ppc_elf_vle_split16 (output_bfd, contents + rel->r_offset,
++ relocation, split16d_type);
+ continue;
+
+ case R_PPC_VLE_HI16A:
+- relocation = ((relocation + addend) >> 16) & 0xffff;
+- ppc_elf_vle_split16 (output_bfd, contents, rel->r_offset,
+- relocation, split16a_type);
++ relocation = (relocation + addend) >> 16;
++ ppc_elf_vle_split16 (output_bfd, contents + rel->r_offset,
++ relocation, split16a_type);
+ continue;
+
+ case R_PPC_VLE_HI16D:
+- relocation = ((relocation + addend) >> 16) & 0xffff;
+- ppc_elf_vle_split16 (output_bfd, contents, rel->r_offset,
+- relocation, split16d_type);
++ relocation = (relocation + addend) >> 16;
++ ppc_elf_vle_split16 (output_bfd, contents + rel->r_offset,
++ relocation, split16d_type);
+ continue;
+
+ case R_PPC_VLE_HA16A:
+- {
+- bfd_vma value = relocation + addend;
+- value = (((value >> 16) + ((value & 0x8000) ? 1 : 0)) & 0xffff);
+- ppc_elf_vle_split16 (output_bfd, contents, rel->r_offset,
+- value, split16a_type);
+- }
++ relocation = (relocation + addend + 0x8000) >> 16;
++ ppc_elf_vle_split16 (output_bfd, contents + rel->r_offset,
++ relocation, split16a_type);
+ continue;
+
+ case R_PPC_VLE_HA16D:
+- {
+- bfd_vma value = relocation + addend;
+- value = (((value >> 16) + ((value & 0x8000) ? 1 : 0)) & 0xffff);
+- ppc_elf_vle_split16 (output_bfd, contents, rel->r_offset,
+- value, split16d_type);
+- }
++ relocation = (relocation + addend + 0x8000) >> 16;
++ ppc_elf_vle_split16 (output_bfd, contents + rel->r_offset,
++ relocation, split16d_type);
+ continue;
+
+ /* Relocate against either _SDA_BASE_, _SDA2_BASE_, or 0. */
+@@ -8792,6 +8785,7 @@ ppc_elf_relocate_section (bfd *output_bfd,
+ {
+ const char *name;
+ int reg;
++ unsigned int insn;
+ struct elf_link_hash_entry *sda = NULL;
+
+ if (sec == NULL || sec->output_section == NULL)
+@@ -8845,32 +8839,40 @@ ppc_elf_relocate_section (bfd *output_bfd,
+ addend -= SYM_VAL (sda);
+ }
+
++ insn = bfd_get_32 (output_bfd, contents + rel->r_offset);
+ if (reg == 0
+ && (r_type == R_PPC_VLE_SDA21
+ || r_type == R_PPC_VLE_SDA21_LO))
+ {
+- /* Use the split20 format. */
+- bfd_vma insn, bits12to15, bits21to31;
+- bfd_vma value = (relocation + rel->r_offset) & 0xffff;
+- /* Propagate sign bit, if necessary. */
+- insn = (value & 0x8000) ? 0x70107800 : 0x70000000;
+- bits12to15 = value & 0x700;
+- bits21to31 = value & 0x7ff;
+- insn |= bits12to15;
+- insn |= bits21to31;
+- bfd_put_32 (output_bfd, insn, contents + rel->r_offset);
+- continue;
++ relocation = relocation + addend;
++ addend = 0;
++
++ /* Force e_li insn, keeping RT from original insn. */
++ insn &= 0x1f << 21;
++ insn |= 28u << 26;
++
++ /* We have an li20 field, bits 17..20, 11..15, 21..31. */
++ /* Top 4 bits of value to 17..20. */
++ insn |= (relocation & 0xf0000) >> 5;
++ /* Next 5 bits of the value to 11..15. */
++ insn |= (relocation & 0xf800) << 5;
++ /* And the final 11 bits of the value to bits 21 to 31. */
++ insn |= relocation & 0x7ff;
++
++ /* Use _bfd_final_link_relocate to report overflow,
++ but do so with a value that won't modify the insn. */
++ if (relocation + 0x80000 > 0x100000)
++ addend = 0x100000;
++ relocation = 0;
+ }
+ else if (r_type == R_PPC_EMB_SDA21
+ || r_type == R_PPC_VLE_SDA21
+ || r_type == R_PPC_VLE_SDA21_LO)
+ {
+- bfd_vma insn; /* Fill in register field. */
+-
+- insn = bfd_get_32 (output_bfd, contents + rel->r_offset);
++ /* Fill in register field. */
+ insn = (insn & ~RA_REGISTER_MASK) | (reg << RA_REGISTER_SHIFT);
+- bfd_put_32 (output_bfd, insn, contents + rel->r_offset);
+ }
++ bfd_put_32 (output_bfd, insn, contents + rel->r_offset);
+ }
+ break;
+
+@@ -8931,46 +8933,39 @@ ppc_elf_relocate_section (bfd *output_bfd,
+ }
+ }
+
+- value = sda->root.u.def.section->output_section->vma
+- + sda->root.u.def.section->output_offset;
+-
+- if (r_type == R_PPC_VLE_SDAREL_LO16A)
+- {
+- value = (value + addend) & 0xffff;
+- ppc_elf_vle_split16 (output_bfd, contents, rel->r_offset,
+- value, split16a_type);
+- }
+- else if (r_type == R_PPC_VLE_SDAREL_LO16D)
+- {
+- value = (value + addend) & 0xffff;
+- ppc_elf_vle_split16 (output_bfd, contents, rel->r_offset,
+- value, split16d_type);
+- }
+- else if (r_type == R_PPC_VLE_SDAREL_HI16A)
++ value = (sda->root.u.def.section->output_section->vma
++ + sda->root.u.def.section->output_offset
++ + addend);
++
++ if (r_type == R_PPC_VLE_SDAREL_LO16A)
++ ppc_elf_vle_split16 (output_bfd, contents + rel->r_offset,
++ value, split16a_type);
++ else if (r_type == R_PPC_VLE_SDAREL_LO16D)
++ ppc_elf_vle_split16 (output_bfd, contents + rel->r_offset,
++ value, split16d_type);
++ else if (r_type == R_PPC_VLE_SDAREL_HI16A)
+ {
+- value = ((value + addend) >> 16) & 0xffff;
+- ppc_elf_vle_split16 (output_bfd, contents, rel->r_offset,
+- value, split16a_type);
++ value = value >> 16;
++ ppc_elf_vle_split16 (output_bfd, contents + rel->r_offset,
++ value, split16a_type);
+ }
+- else if (r_type == R_PPC_VLE_SDAREL_HI16D)
++ else if (r_type == R_PPC_VLE_SDAREL_HI16D)
+ {
+- value = ((value + addend) >> 16) & 0xffff;
+- ppc_elf_vle_split16 (output_bfd, contents, rel->r_offset,
+- value, split16d_type);
++ value = value >> 16;
++ ppc_elf_vle_split16 (output_bfd, contents + rel->r_offset,
++ value, split16d_type);
+ }
+- else if (r_type == R_PPC_VLE_SDAREL_HA16A)
++ else if (r_type == R_PPC_VLE_SDAREL_HA16A)
+ {
+- value += addend;
+- value = (((value >> 16) + ((value & 0x8000) ? 1 : 0)) & 0xffff);
+- ppc_elf_vle_split16 (output_bfd, contents, rel->r_offset,
+- value, split16a_type);
++ value = (value + 0x8000) >> 16;
++ ppc_elf_vle_split16 (output_bfd, contents + rel->r_offset,
++ value, split16a_type);
+ }
+- else if (r_type == R_PPC_VLE_SDAREL_HA16D)
++ else if (r_type == R_PPC_VLE_SDAREL_HA16D)
+ {
+- value += addend;
+- value = (((value >> 16) + ((value & 0x8000) ? 1 : 0)) & 0xffff);
+- ppc_elf_vle_split16 (output_bfd, contents, rel->r_offset,
+- value, split16d_type);
++ value = (value + 0x8000) >> 16;
++ ppc_elf_vle_split16 (output_bfd, contents + rel->r_offset,
++ value, split16d_type);
+ }
+ }
+ continue;
+@@ -9130,13 +9125,36 @@ ppc_elf_relocate_section (bfd *output_bfd,
+ ret = FALSE;
+ }
+
+- r = _bfd_final_link_relocate (howto,
+- input_bfd,
+- input_section,
+- contents,
+- rel->r_offset,
+- relocation,
+- addend);
++ /* 16-bit fields in insns mostly have signed values, but a
++ few insns have 16-bit unsigned values. Really, we should
++ have different reloc types. */
++ if (howto->complain_on_overflow != complain_overflow_dont
++ && howto->dst_mask == 0xffff
++ && (input_section->flags & SEC_CODE) != 0)
++ {
++ enum complain_overflow complain = complain_overflow_signed;
++
++ if ((elf_section_flags (input_section) & SHF_PPC_VLE) == 0)
++ {
++ unsigned int insn;
++
++ insn = bfd_get_32 (input_bfd, contents + (rel->r_offset & ~3));
++ if ((insn & (0x3f << 26)) == 28u << 26 /* andi */
++ || (insn & (0x3f << 26)) == 24u << 26 /* ori */
++ || (insn & (0x3f << 26)) == 26u << 26 /* xori */
++ || (insn & (0x3f << 26)) == 10u << 26 /* cmpli */)
++ complain = complain_overflow_unsigned;
++ }
++ if (howto->complain_on_overflow != complain)
++ {
++ alt_howto = *howto;
++ alt_howto.complain_on_overflow = complain;
++ howto = &alt_howto;
++ }
++ }
++
++ r = _bfd_final_link_relocate (howto, input_bfd, input_section, contents,
++ rel->r_offset, relocation, addend);
+
+ if (r != bfd_reloc_ok)
+ {
diff --git a/SOURCES/gdb-rhbz1320945-power9-05of38.patch b/SOURCES/gdb-rhbz1320945-power9-05of38.patch
new file mode 100644
index 0000000..98999b3
--- /dev/null
+++ b/SOURCES/gdb-rhbz1320945-power9-05of38.patch
@@ -0,0 +1,123 @@
+commit a47622ac1badbd906c7533ef6011b6bb021271ee
+Author: Alan Modra <amodra@gmail.com>
+Date: Sat Jun 7 12:09:04 2014 +0930
+
+ Allow both signed and unsigned fields in PowerPC cmpli insn
+
+ There are legitimate reasons to allow a signed value in a cmpli insn
+ field, for example to test for a "stw r1,lock@sdarel(r13)" instruction
+ in user code, a kernel might use
+ subis r3,r3,STW_R1_0R13@ha # subtract off high part
+ cmplwi r3,lock@sdarel # is low part accessing lock?
+ Since the lock@sdarel may take a range of -32768 to 32767,
+ the allowed range of cmpli immediate must be at least [-32768,65535].
+
+ bfd/
+ * elf32-ppc.c (ppc_elf_relocate_section): Treat field of cmpli
+ insn as a bitfield; Use complain_overflow_bitfield.
+ * elf64-ppc.c (ppc64_elf_relocate_section): Likewise.
+ opcodes/
+ * ppc-opc.c (UISIGNOPT): Define and use with cmpli.
+ gas/
+ * config/tc-ppc.c (ppc_insert_operand): Handle PPC_OPERAND_SIGNOPT
+ on unsigned fields. Comment on PPC_OPERAND_SIGNOPT signed fields
+ in 64-bit mode.
+ gold/
+ * powerpc.cc (relocate): Treat field of cmpli insn as a bitfield.
+
+### a/bfd/ChangeLog
+### b/bfd/ChangeLog
+## -1,3 +1,9 @@
++2014-06-07 Alan Modra <amodra@gmail.com>
++
++ * elf32-ppc.c (ppc_elf_relocate_section): Treat field of cmpli
++ insn as a bitfield; Use complain_overflow_bitfield.
++ * elf64-ppc.c (ppc64_elf_relocate_section): Likewise.
++
+ 2014-06-05 Joel Brobecker <brobecker@adacore.com>
+
+ * development.sh: New file.
+--- a/bfd/elf32-ppc.c
++++ b/bfd/elf32-ppc.c
+@@ -9147,10 +9147,11 @@ ppc_elf_relocate_section (bfd *output_bfd,
+ unsigned int insn;
+
+ insn = bfd_get_32 (input_bfd, contents + (rel->r_offset & ~3));
+- if ((insn & (0x3f << 26)) == 28u << 26 /* andi */
+- || (insn & (0x3f << 26)) == 24u << 26 /* ori */
+- || (insn & (0x3f << 26)) == 26u << 26 /* xori */
+- || (insn & (0x3f << 26)) == 10u << 26 /* cmpli */)
++ if ((insn & (0x3f << 26)) == 10u << 26 /* cmpli */)
++ complain = complain_overflow_bitfield;
++ else if ((insn & (0x3f << 26)) == 28u << 26 /* andi */
++ || (insn & (0x3f << 26)) == 24u << 26 /* ori */
++ || (insn & (0x3f << 26)) == 26u << 26 /* xori */)
+ complain = complain_overflow_unsigned;
+ }
+ if (howto->complain_on_overflow != complain)
+--- a/bfd/elf64-ppc.c
++++ b/bfd/elf64-ppc.c
+@@ -14648,14 +14648,15 @@ ppc64_elf_relocate_section (bfd *output_bfd,
+ enum complain_overflow complain = complain_overflow_signed;
+
+ insn = bfd_get_32 (input_bfd, contents + (rel->r_offset & ~3));
+- if (howto->rightshift == 0
+- ? ((insn & (0x3f << 26)) == 28u << 26 /* andi */
+- || (insn & (0x3f << 26)) == 24u << 26 /* ori */
+- || (insn & (0x3f << 26)) == 26u << 26 /* xori */
+- || (insn & (0x3f << 26)) == 10u << 26 /* cmpli */)
+- : ((insn & (0x3f << 26)) == 29u << 26 /* andis */
+- || (insn & (0x3f << 26)) == 25u << 26 /* oris */
+- || (insn & (0x3f << 26)) == 27u << 26 /* xoris */))
++ if ((insn & (0x3f << 26)) == 10u << 26 /* cmpli */)
++ complain = complain_overflow_bitfield;
++ else if (howto->rightshift == 0
++ ? ((insn & (0x3f << 26)) == 28u << 26 /* andi */
++ || (insn & (0x3f << 26)) == 24u << 26 /* ori */
++ || (insn & (0x3f << 26)) == 26u << 26 /* xori */)
++ : ((insn & (0x3f << 26)) == 29u << 26 /* andis */
++ || (insn & (0x3f << 26)) == 25u << 26 /* oris */
++ || (insn & (0x3f << 26)) == 27u << 26 /* xoris */))
+ complain = complain_overflow_unsigned;
+ if (howto->complain_on_overflow != complain)
+ {
+### a/opcodes/ChangeLog
+### b/opcodes/ChangeLog
+## -1,3 +1,7 @@
++2014-06-07 Alan Modra <amodra@gmail.com>
++
++ * ppc-opc.c (UISIGNOPT): Define and use with cmpli.
++
+ 2014-06-05 Joel Brobecker <brobecker@adacore.com>
+
+ * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add dependency on
+--- a/opcodes/ppc-opc.c
++++ b/opcodes/ppc-opc.c
+@@ -654,8 +654,11 @@ const struct powerpc_operand powerpc_operands[] =
+ #define UI TO + 1
+ { 0xffff, 0, NULL, NULL, 0 },
+
++#define UISIGNOPT UI + 1
++ { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNOPT },
++
+ /* The IMM field in an SE_IM5 instruction. */
+-#define UI5 UI + 1
++#define UI5 UISIGNOPT + 1
+ { 0x1f, 4, NULL, NULL, 0 },
+
+ /* The OIMM field in an SE_OIM5 instruction. */
+@@ -3500,10 +3503,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+
+ {"dozi", OP(9), OP_MASK, M601, PPCNONE, {RT, RA, SI}},
+
+-{"cmplwi", OPL(10,0), OPL_MASK, PPCCOM, PPCNONE, {OBF, RA, UI}},
+-{"cmpldi", OPL(10,1), OPL_MASK, PPC64, PPCNONE, {OBF, RA, UI}},
+-{"cmpli", OP(10), OP_MASK, PPC, PPCNONE, {BF, L, RA, UI}},
+-{"cmpli", OP(10), OP_MASK, PWRCOM, PPC, {BF, RA, UI}},
++{"cmplwi", OPL(10,0), OPL_MASK, PPCCOM, PPCNONE, {OBF, RA, UISIGNOPT}},
++{"cmpldi", OPL(10,1), OPL_MASK, PPC64, PPCNONE, {OBF, RA, UISIGNOPT}},
++{"cmpli", OP(10), OP_MASK, PPC, PPCNONE, {BF, L, RA, UISIGNOPT}},
++{"cmpli", OP(10), OP_MASK, PWRCOM, PPC, {BF, RA, UISIGNOPT}},
+
+ {"cmpwi", OPL(11,0), OPL_MASK, PPCCOM, PPCNONE, {OBF, RA, SI}},
+ {"cmpdi", OPL(11,1), OPL_MASK, PPC64, PPCNONE, {OBF, RA, SI}},
diff --git a/SOURCES/gdb-rhbz1320945-power9-06of38.patch b/SOURCES/gdb-rhbz1320945-power9-06of38.patch
new file mode 100644
index 0000000..dd7ff0b
--- /dev/null
+++ b/SOURCES/gdb-rhbz1320945-power9-06of38.patch
@@ -0,0 +1,39 @@
+commit 12e87fac5c760b04eed4f5a5948c2dfd6ec8f6d8
+Author: Jan Beulich <jbeulich@novell.com>
+Date: Tue Oct 21 09:56:38 2014 +0200
+
+ ppc: enable msgclr and msgsnd on Power8
+
+ According to my reading of the spec it was an oversight for them to
+ not having got enabled when Power8 support got added.
+
+### a/opcodes/ChangeLog
+### b/opcodes/ChangeLog
+## -1,3 +1,7 @@
++2014-10-21 Jan Beulich <jbeulich@suse.com>
++
++ * ppc-opc.c (powerpc_opcodes): Enable msgclr and msgsnd on Power8.
++
+ 2014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * sparc-opc.c (sparc-opcodes): Fix several misplaced hwcap
+--- a/opcodes/ppc-opc.c
++++ b/opcodes/ppc-opc.c
+@@ -4653,7 +4653,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"addze.", XO(31,202,0,1), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}},
+ {"aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
+
+-{"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RB}},
++{"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8|PPCVLE, PPCNONE, {RB}},
+
+ {"mtsr", X(31,210), XRB_MASK|(1<<20), COM, NON32, {SR, RS}},
+
+@@ -4700,7 +4700,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
+
+ {"icblce", X(31,238), X_MASK, PPCCHLK, E500MC|PPCA2, {CT, RA, RB}},
+-{"msgclr", XRTRA(31,238,0,0),XRTRA_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RB}},
++{"msgclr", XRTRA(31,238,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8|PPCVLE, PPCNONE, {RB}},
+ {"mtsrin", X(31,242), XRA_MASK, PPC, NON32, {RS, RB}},
+ {"mtsri", X(31,242), XRA_MASK, POWER, NON32, {RS, RB}},
+
diff --git a/SOURCES/gdb-rhbz1320945-power9-07of38.patch b/SOURCES/gdb-rhbz1320945-power9-07of38.patch
new file mode 100644
index 0000000..8438c54
--- /dev/null
+++ b/SOURCES/gdb-rhbz1320945-power9-07of38.patch
@@ -0,0 +1,73 @@
+commit 8514e4db84ccafaf3be07e842be2fa2001ba876e
+Author: Alan Modra <amodra@gmail.com>
+Date: Fri Nov 28 13:21:52 2014 +1030
+
+ Don't deprecate powerpc mftb insn
+
+ mftb is marked phased out in the architecture manual, but we can keep
+ it as an extended mnemonic for mftbl.
+
+ * ppc-opc.c (powerpc_opcodes <mftb>): Don't deprecate for power7.
+ (TB): Delete.
+ (insert_tbr, extract_tbr): Validate tbr number.
+
+### a/opcodes/ChangeLog
+### b/opcodes/ChangeLog
+## -1,3 +1,9 @@
++2014-11-28 Alan Modra <amodra@gmail.com>
++
++ * ppc-opc.c (powerpc_opcodes <mftb>): Don't deprecate for power7.
++ (TB): Delete.
++ (insert_tbr, extract_tbr): Validate tbr number.
++
+ 2014-11-24 H.J. Lu <hongjiu.lu@intel.com>
+
+ * configure: Regenerated.
+--- a/opcodes/ppc-opc.c
++++ b/opcodes/ppc-opc.c
+@@ -1872,28 +1872,30 @@ extract_sprg (unsigned long insn,
+ much, since the architecture manual does not define mftb as
+ accepting any values other than 268 or 269. */
+
+-#define TB (268)
+-
+ static unsigned long
+ insert_tbr (unsigned long insn,
+ long value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+- const char **errmsg ATTRIBUTE_UNUSED)
++ const char **errmsg)
+ {
+ if (value == 0)
+- value = TB;
++ value = 268;
++ if (value != 268 && value != 269)
++ *errmsg = _("invalid tbr number");
+ return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
+ }
+
+ static long
+ extract_tbr (unsigned long insn,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+- int *invalid ATTRIBUTE_UNUSED)
++ int *invalid)
+ {
+ long ret;
+
+ ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
+- if (ret == TB)
++ if (ret != 268 && ret != 269)
++ *invalid = 1;
++ if (ret == 268)
+ ret = 0;
+ return ret;
+ }
+@@ -5051,7 +5053,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+
+ {"mftbl", XSPR(31,371,268), XSPR_MASK, PPC, NO371, {RT}},
+ {"mftbu", XSPR(31,371,269), XSPR_MASK, PPC, NO371, {RT}},
+-{"mftb", X(31,371), X_MASK, PPC|PPCA2, NO371|POWER7, {RT, TBR}},
++{"mftb", X(31,371), X_MASK, PPC|PPCA2, NO371, {RT, TBR}},
+
+ {"lwaux", X(31,373), X_MASK, PPC64|PPCVLE, PPCNONE, {RT, RAL, RB}},
+
diff --git a/SOURCES/gdb-rhbz1320945-power9-08of38.patch b/SOURCES/gdb-rhbz1320945-power9-08of38.patch
new file mode 100644
index 0000000..150fb33
--- /dev/null
+++ b/SOURCES/gdb-rhbz1320945-power9-08of38.patch
@@ -0,0 +1,56 @@
+commit db76a70026ab100148eb274322fac01f1a1dd466
+Author: Alan Modra <amodra@gmail.com>
+Date: Sat Nov 29 19:13:17 2014 +1030
+
+ Power4 should treat mftb as extended mfspr mnemonic
+
+ On further reading of ISA manual it appears gas should have been
+ treating mftb and mftbu as extended mnemonics for mfspr, for ISA 2.03
+ and later.
+
+ opcodes/
+ * ppc-opc.c (powerpc_opcodes): Make mftb* generate mfspr for
+ power4 and later.
+ gas/testsuite/
+ * gas/ppc/a2.d: Update for mftb change.
+ * gas/ppc/476.d: Likewise.
+
+### a/opcodes/ChangeLog
+### b/opcodes/ChangeLog
+## -1,3 +1,8 @@
++2014-11-30 Alan Modra <amodra@gmail.com>
++
++ * ppc-opc.c (powerpc_opcodes): Make mftb* generate mfspr for
++ power4 and later.
++
+ 2014-11-28 Sandra Loosemore <sandra@codesourcery.com>
+
+ * nios2-opc.c (nios2_r1_opcodes): Remove deleted attributes
+--- a/opcodes/ppc-opc.c
++++ b/opcodes/ppc-opc.c
+@@ -4880,9 +4880,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RT}},
+ {"mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RT}},
+ {"mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RT}},
+-{"mftb", XSPR(31,339,268), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+-{"mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+-{"mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
++{"mftbu", XSPR(31,339,269), XSPR_MASK, POWER4|BOOKE|PPCVLE, PPCNONE, {RT}},
++{"mftb", X(31,339), X_MASK, POWER4|BOOKE|PPCVLE, PPCNONE, {RT, TBR}},
++{"mftbl", XSPR(31,339,268), XSPR_MASK, POWER4|BOOKE|PPCVLE, PPCNONE, {RT}},
+ {"mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC|PPCVLE, PPCNONE, {RT}},
+ {"mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC|PPCVLE, PPCNONE, {RT}},
+ {"mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC|PPCVLE, PPCNONE, {RT}},
+@@ -5051,9 +5051,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+
+ {"tlbia", X(31,370), 0xffffffff, PPC, TITAN, {0}},
+
+-{"mftbl", XSPR(31,371,268), XSPR_MASK, PPC, NO371, {RT}},
+-{"mftbu", XSPR(31,371,269), XSPR_MASK, PPC, NO371, {RT}},
+-{"mftb", X(31,371), X_MASK, PPC|PPCA2, NO371, {RT, TBR}},
++{"mftbu", XSPR(31,371,269), XSPR_MASK, PPC, NO371|POWER4, {RT}},
++{"mftb", X(31,371), X_MASK, PPC, NO371|POWER4, {RT, TBR}},
++{"mftbl", XSPR(31,371,268), XSPR_MASK, PPC, NO371|POWER4, {RT}},
+
+ {"lwaux", X(31,373), X_MASK, PPC64|PPCVLE, PPCNONE, {RT, RAL, RB}},
+
diff --git a/SOURCES/gdb-rhbz1320945-power9-09of38.patch b/SOURCES/gdb-rhbz1320945-power9-09of38.patch
new file mode 100644
index 0000000..80e3e75
--- /dev/null
+++ b/SOURCES/gdb-rhbz1320945-power9-09of38.patch
@@ -0,0 +1,807 @@
+commit 5860e3f883597cf6b8a937547015394edc1e8784
+Author: Nick Clifton <nickc@redhat.com>
+Date: Mon Dec 22 20:59:00 2014 +0000
+
+ More fixes for memory access violations exposed by fuzzed binaries.
+
+ PR binutils/17512
+ * archive.c (do_slurp_bsd_armap): Return if the parsed_size is
+ zero.
+ (bfd_slurp_armap): Zero terminate the name.
+ (bfd_generic_stat_arch_elt): If there is no header, fail.
+ * elf32-arc.c (arc_info_to_howto_rel): Replace BFD_ASSERT with
+ error message.
+ * elf32-avr.c (avr_info_to_howto_rela): Likewise.
+ * elf32-cr16c.c (elf_cr16c_info_to_howto_rel): Likewise.
+ * elf32-cris.c (cris_info_to_howto_rela): Likewise.
+ * elf32-d10v.c (d10v_info_to_howto_rel): Likewise.
+ * elf32-d30v.c (d30v_info_to_howto_rel): Likewise.
+ * elf32-dlx.c (dlx_rtype_to_howto): Likewise.
+ * elf32-epiphany.c (epiphany_info_to_howto_rela): Likewise.
+ * elf32-fr30.c (fr30_info_to_howto_rela): Likewise.
+ * elf32-frv.c (frv_info_to_howto_rela): Likewise.
+ * elf32-i960.c (elf32_i960_info_to_howto_rel): Likewise.
+ * elf32-ip2k.c (ip2k_info_to_howto_rela): Likewise.
+ * elf32-iq2000.c (iq2000_info_to_howto_rela): Likewise.
+ * elf32-lm32.c (lm32_info_to_howto_rela): Likewise.
+ * elf32-m32c.c (m32c_info_to_howto_rela): Likewise.
+ * elf32-m32r.c (m32r_info_to_howto_rel): Likewise.
+ * elf32-m68hc11.c (m68hc11_info_to_howto_rel): Likewise.
+ * elf32-m68hc12.c (m68hc11_info_to_howto_rel): Likewise.
+ * elf32-mep.c (mep_info_to_howto_rela): Likewise.
+ * elf32-metag.c (metag_info_to_howto_rela): Likewise.
+ * elf32-moxie.c (moxie_info_to_howto_rela): Likewise.
+ * elf32-msp430.c (msp430_info_to_howto_rela): Likewise.
+ * elf32-mt.c (mt_info_to_howto_rela): Likewise.
+ * elf32-nds32.c (nds32_info_to_howto_rel): Likewise.
+ * elf32-or1k.c (or1k_info_to_howto_rela): Likewise.
+ * elf32-rl78.c (rl78_info_to_howto_rela): Likewise.
+ * elf32-rx.c (rx_info_to_howto_rela): Likewise.
+ * elf32-v850.c (v850_elf_info_to_howto_rel): Likewise.
+ * elf32-visium.c (visium_info_to_howto_rela): Likewise.
+ * elf32-xgate.c (xgate_info_to_howto_rel): Likewise.
+ * elf32-xtensa.c (elf_xtensa_info_to_howto_rela): Likewise.
+ * elf64-mmix.c (mmix_info_to_howto_rela): Likewise.
+ * elf64-x86-64.c (elf_x86_64_reloc_type_lookup): Likewise.
+ * elfnn-aarch64.c (elfNN_aarch64_bfd_reloc_from_type): Likewise.
+ * elf64-sparc.c (elf64_sparc_slurp_one_reloc_table): Add range
+ checking of reloc symbol index.
+ * mach-o.c (bfd_mach_o_canonicalize_one_reloc): If no symbols have
+ been provided then set the reloc's symbol to undefined.
+ * reloc.c (bfd_generic_get_relocated_section_contents): Add range
+ checking of the reloc to be applied.
+ * versados.c (process_otr): Add more range checks.
+ (versados_canonicalize_reloc): If the section is unknown, set the
+ symbol to undefined.
+ * vms-alpha.c (_bfd_vms_slurp_eisd): Add range checks.
+ (alpha_vms_object_p): Likewise.
+
+### a/bfd/ChangeLog
+### b/bfd/ChangeLog
+## -1,3 +1,57 @@
++2014-12-22 Nick Clifton <nickc@redhat.com>
++
++ PR binutils/17512
++ * archive.c (do_slurp_bsd_armap): Return if the parsed_size is
++ zero.
++ (bfd_slurp_armap): Zero terminate the name.
++ (bfd_generic_stat_arch_elt): If there is no header, fail.
++ * elf32-arc.c (arc_info_to_howto_rel): Replace BFD_ASSERT with
++ error message.
++ * elf32-avr.c (avr_info_to_howto_rela): Likewise.
++ * elf32-cr16c.c (elf_cr16c_info_to_howto_rel): Likewise.
++ * elf32-cris.c (cris_info_to_howto_rela): Likewise.
++ * elf32-d10v.c (d10v_info_to_howto_rel): Likewise.
++ * elf32-d30v.c (d30v_info_to_howto_rel): Likewise.
++ * elf32-dlx.c (dlx_rtype_to_howto): Likewise.
++ * elf32-epiphany.c (epiphany_info_to_howto_rela): Likewise.
++ * elf32-fr30.c (fr30_info_to_howto_rela): Likewise.
++ * elf32-frv.c (frv_info_to_howto_rela): Likewise.
++ * elf32-i960.c (elf32_i960_info_to_howto_rel): Likewise.
++ * elf32-ip2k.c (ip2k_info_to_howto_rela): Likewise.
++ * elf32-iq2000.c (iq2000_info_to_howto_rela): Likewise.
++ * elf32-lm32.c (lm32_info_to_howto_rela): Likewise.
++ * elf32-m32c.c (m32c_info_to_howto_rela): Likewise.
++ * elf32-m32r.c (m32r_info_to_howto_rel): Likewise.
++ * elf32-m68hc11.c (m68hc11_info_to_howto_rel): Likewise.
++ * elf32-m68hc12.c (m68hc11_info_to_howto_rel): Likewise.
++ * elf32-mep.c (mep_info_to_howto_rela): Likewise.
++ * elf32-metag.c (metag_info_to_howto_rela): Likewise.
++ * elf32-moxie.c (moxie_info_to_howto_rela): Likewise.
++ * elf32-msp430.c (msp430_info_to_howto_rela): Likewise.
++ * elf32-mt.c (mt_info_to_howto_rela): Likewise.
++ * elf32-nds32.c (nds32_info_to_howto_rel): Likewise.
++ * elf32-or1k.c (or1k_info_to_howto_rela): Likewise.
++ * elf32-rl78.c (rl78_info_to_howto_rela): Likewise.
++ * elf32-rx.c (rx_info_to_howto_rela): Likewise.
++ * elf32-v850.c (v850_elf_info_to_howto_rel): Likewise.
++ * elf32-visium.c (visium_info_to_howto_rela): Likewise.
++ * elf32-xgate.c (xgate_info_to_howto_rel): Likewise.
++ * elf32-xtensa.c (elf_xtensa_info_to_howto_rela): Likewise.
++ * elf64-mmix.c (mmix_info_to_howto_rela): Likewise.
++ * elf64-x86-64.c (elf_x86_64_reloc_type_lookup): Likewise.
++ * elfnn-aarch64.c (elfNN_aarch64_bfd_reloc_from_type): Likewise.
++ * elf64-sparc.c (elf64_sparc_slurp_one_reloc_table): Add range
++ checking of reloc symbol index.
++ * mach-o.c (bfd_mach_o_canonicalize_one_reloc): If no symbols have
++ been provided then set the reloc's symbol to undefined.
++ * reloc.c (bfd_generic_get_relocated_section_contents): Add range
++ checking of the reloc to be applied.
++ * versados.c (process_otr): Add more range checks.
++ (versados_canonicalize_reloc): If the section is unknown, set the
++ symbol to undefined.
++ * vms-alpha.c (_bfd_vms_slurp_eisd): Add range checks.
++ (alpha_vms_object_p): Likewise.
++
+ 2014-12-18 Richard Henderson <rth@redhat.com>
+
+ * elf32-ppc.c (ELF_COMMONPAGESIZE): Set to 64k.
+--- a/bfd/archive.c
++++ b/bfd/archive.c
+@@ -902,6 +902,9 @@ do_slurp_bsd_armap (bfd *abfd)
+ return FALSE;
+ parsed_size = mapdata->parsed_size;
+ free (mapdata);
++ /* PR 17512: file: 883ff754. */
++ if (parsed_size == 0)
++ return FALSE;
+
+ raw_armap = (bfd_byte *) bfd_zalloc (abfd, parsed_size);
+ if (raw_armap == NULL)
+@@ -917,7 +920,6 @@ do_slurp_bsd_armap (bfd *abfd)
+ }
+
+ ardata->symdef_count = H_GET_32 (abfd, raw_armap) / BSD_SYMDEF_SIZE;
+-
+ if (ardata->symdef_count * BSD_SYMDEF_SIZE >
+ parsed_size - BSD_SYMDEF_COUNT_SIZE)
+ {
+@@ -1138,6 +1140,7 @@ bfd_slurp_armap (bfd *abfd)
+ return FALSE;
+ if (bfd_seek (abfd, -(file_ptr) (sizeof (hdr) + 20), SEEK_CUR) != 0)
+ return FALSE;
++ extname[20] = 0;
+ if (CONST_STRNEQ (extname, "__.SYMDEF SORTED")
+ || CONST_STRNEQ (extname, "__.SYMDEF"))
+ return do_slurp_bsd_armap (abfd);
+@@ -1971,7 +1974,9 @@ bfd_generic_stat_arch_elt (bfd *abfd, struct stat *buf)
+ }
+
+ hdr = arch_hdr (abfd);
+-
++ /* PR 17512: file: 3d9e9fe9. */
++ if (hdr == NULL)
++ return -1;
+ #define foo(arelt, stelt, size) \
+ buf->stelt = strtol (hdr->arelt, &aloser, size); \
+ if (aloser == hdr->arelt) \
+--- a/bfd/elf32-arc.c
++++ b/bfd/elf32-arc.c
+@@ -172,7 +172,11 @@ arc_info_to_howto_rel (bfd *abfd ATTRIBUTE_UNUSED,
+ unsigned int r_type;
+
+ r_type = ELF32_R_TYPE (dst->r_info);
+- BFD_ASSERT (r_type < (unsigned int) R_ARC_max);
++ if (r_type >= (unsigned int) R_ARC_max)
++ {
++ _bfd_error_handler (_("%A: invalid ARC reloc number: %d"), abfd, r_type);
++ r_type = 0;
++ }
+ cache_ptr->howto = &elf_arc_howto_table[r_type];
+ }
+
+--- a/bfd/elf32-avr.c
++++ b/bfd/elf32-avr.c
+@@ -859,7 +859,11 @@ avr_info_to_howto_rela (bfd *abfd ATTRIBUTE_UNUSED,
+ unsigned int r_type;
+
+ r_type = ELF32_R_TYPE (dst->r_info);
+- BFD_ASSERT (r_type < (unsigned int) R_AVR_max);
++ if (r_type >= (unsigned int) R_AVR_max)
++ {
++ _bfd_error_handler (_("%A: invalid AVR reloc number: %d"), abfd, r_type);
++ r_type = 0;
++ }
+ cache_ptr->howto = &elf_avr_howto_table[r_type];
+ }
+
+--- a/bfd/elf32-cr16c.c
++++ b/bfd/elf32-cr16c.c
+@@ -180,7 +180,11 @@ elf_cr16c_info_to_howto_rel (bfd *abfd ATTRIBUTE_UNUSED,
+ {
+ unsigned int r_type = ELF32_R_TYPE (dst->r_info);
+
+- BFD_ASSERT (r_type < (unsigned int) RINDEX_16C_MAX);
++ if (r_type >= RINDEX_16C_MAX)
++ {
++ _bfd_error_handler (_("%A; invalid CR16C reloc number: %d"), abfd, r_type);
++ r_type = 0;
++ }
+ cache_ptr->howto = &elf_howto_table[r_type];
+ }
+
+--- a/bfd/elf32-cris.c
++++ b/bfd/elf32-cris.c
+@@ -461,7 +461,11 @@ cris_info_to_howto_rela (bfd * abfd ATTRIBUTE_UNUSED,
+ enum elf_cris_reloc_type r_type;
+
+ r_type = ELF32_R_TYPE (dst->r_info);
+- BFD_ASSERT (r_type < (unsigned int) R_CRIS_max);
++ if (r_type >= R_CRIS_max)
++ {
++ _bfd_error_handler (_("%A: invalid CRIS reloc number: %d"), abfd, r_type);
++ r_type = 0;
++ }
+ cache_ptr->howto = & cris_elf_howto_table [r_type];
+ }
+
+--- a/bfd/elf32-d10v.c
++++ b/bfd/elf32-d10v.c
+@@ -228,7 +228,11 @@ d10v_info_to_howto_rel (bfd *abfd ATTRIBUTE_UNUSED,
+ unsigned int r_type;
+
+ r_type = ELF32_R_TYPE (dst->r_info);
+- BFD_ASSERT (r_type < (unsigned int) R_D10V_max);
++ if (r_type >= (unsigned int) R_D10V_max)
++ {
++ _bfd_error_handler (_("%A: invalid D10V reloc number: %d"), abfd, r_type);
++ r_type = 0;
++ }
+ cache_ptr->howto = &elf_d10v_howto_table[r_type];
+ }
+
+--- a/bfd/elf32-d30v.c
++++ b/bfd/elf32-d30v.c
+@@ -516,7 +516,11 @@ d30v_info_to_howto_rel (bfd *abfd ATTRIBUTE_UNUSED,
+ unsigned int r_type;
+
+ r_type = ELF32_R_TYPE (dst->r_info);
+- BFD_ASSERT (r_type < (unsigned int) R_D30V_max);
++ if (r_type >= (unsigned int) R_D30V_max)
++ {
++ _bfd_error_handler (_("%A: invalid D30V reloc number: %d"), abfd, r_type);
++ r_type = 0;
++ }
+ cache_ptr->howto = &elf_d30v_howto_table[r_type];
+ }
+
+@@ -530,7 +534,11 @@ d30v_info_to_howto_rela (bfd *abfd ATTRIBUTE_UNUSED,
+ unsigned int r_type;
+
+ r_type = ELF32_R_TYPE (dst->r_info);
+- BFD_ASSERT (r_type < (unsigned int) R_D30V_max);
++ if (r_type >= (unsigned int) R_D30V_max)
++ {
++ _bfd_error_handler (_("%A: invalid D30V reloc number: %d"), abfd, r_type);
++ r_type = 0;
++ }
+ cache_ptr->howto = &elf_d30v_howto_table[r_type];
+ }
+
+--- a/bfd/elf32-dlx.c
++++ b/bfd/elf32-dlx.c
+@@ -546,7 +546,11 @@ dlx_rtype_to_howto (unsigned int r_type)
+ case R_DLX_RELOC_16_LO:
+ return & elf_dlx_reloc_16_lo;
+ default:
+- BFD_ASSERT (r_type < (unsigned int) R_DLX_max);
++ if (r_type >= (unsigned int) R_DLX_max)
++ {
++ _bfd_error_handler (_("Invalid DLX reloc number: %d"), r_type);
++ r_type = 0;
++ }
+ return & dlx_elf_howto_table[r_type];
+ }
+ }
+--- a/bfd/elf32-epiphany.c
++++ b/bfd/elf32-epiphany.c
+@@ -370,6 +370,11 @@ epiphany_info_to_howto_rela (bfd * abfd ATTRIBUTE_UNUSED,
+ unsigned int r_type;
+
+ r_type = ELF32_R_TYPE (dst->r_info);
++ if (r_type >= (unsigned int) R_EPIPHANY_max)
++ {
++ _bfd_error_handler (_("%A: invalid Epiphany reloc number: %d"), abfd, r_type);
++ r_type = 0;
++ }
+ cache_ptr->howto = & epiphany_elf_howto_table [r_type];
+ }
+
+--- a/bfd/elf32-fr30.c
++++ b/bfd/elf32-fr30.c
+@@ -375,7 +375,11 @@ fr30_info_to_howto_rela (bfd *abfd ATTRIBUTE_UNUSED,
+ unsigned int r_type;
+
+ r_type = ELF32_R_TYPE (dst->r_info);
+- BFD_ASSERT (r_type < (unsigned int) R_FR30_max);
++ if (r_type >= (unsigned int) R_FR30_max)
++ {
++ _bfd_error_handler (_("%A: invalid FR30 reloc number: %d"), abfd, r_type);
++ r_type = 0;
++ }
+ cache_ptr->howto = & fr30_elf_howto_table [r_type];
+ }
+
+--- a/bfd/elf32-frv.c
++++ b/bfd/elf32-frv.c
+@@ -2557,6 +2557,11 @@ frv_info_to_howto_rela (bfd *abfd ATTRIBUTE_UNUSED,
+ break;
+
+ default:
++ if (r_type >= (unsigned int) R_FRV_max)
++ {
++ _bfd_error_handler (_("%A: invalid FRV reloc number: %d"), abfd, r_type);
++ r_type = 0;
++ }
+ cache_ptr->howto = & elf32_frv_howto_table [r_type];
+ break;
+ }
+--- a/bfd/elf32-i960.c
++++ b/bfd/elf32-i960.c
+@@ -132,7 +132,13 @@ elf32_i960_info_to_howto_rel (bfd *abfd ATTRIBUTE_UNUSED,
+ enum elf_i960_reloc_type type;
+
+ type = (enum elf_i960_reloc_type) ELF32_R_TYPE (dst->r_info);
+- BFD_ASSERT (type < R_960_max);
++
++ /* PR 17521: file: 9609b8d6. */
++ if (type >= R_960_max)
++ {
++ _bfd_error_handler (_("%A; invalid i960 reloc number: %d"), abfd, type);
++ type = 0;
++ }
+
+ cache_ptr->howto = &elf_howto_table[(int) type];
+ }
+--- a/bfd/elf32-ip2k.c
++++ b/bfd/elf32-ip2k.c
+@@ -1239,6 +1239,11 @@ ip2k_info_to_howto_rela (bfd * abfd ATTRIBUTE_UNUSED,
+ unsigned int r_type;
+
+ r_type = ELF32_R_TYPE (dst->r_info);
++ if (r_type >= (unsigned int) R_IP2K_max)
++ {
++ _bfd_error_handler (_("%A: invalid IP2K reloc number: %d"), abfd, r_type);
++ r_type = 0;
++ }
+ cache_ptr->howto = & ip2k_elf_howto_table [r_type];
+ }
+
+--- a/bfd/elf32-iq2000.c
++++ b/bfd/elf32-iq2000.c
+@@ -435,6 +435,11 @@ iq2000_info_to_howto_rela (bfd * abfd ATTRIBUTE_UNUSED,
+ break;
+
+ default:
++ if (r_type >= (unsigned int) R_IQ2000_max)
++ {
++ _bfd_error_handler (_("%A: invalid IQ2000 reloc number: %d"), abfd, r_type);
++ r_type = 0;
++ }
+ cache_ptr->howto = & iq2000_elf_howto_table [r_type];
+ break;
+ }
+--- a/bfd/elf32-lm32.c
++++ b/bfd/elf32-lm32.c
+@@ -588,7 +588,11 @@ lm32_info_to_howto_rela (bfd *abfd ATTRIBUTE_UNUSED,
+ unsigned int r_type;
+
+ r_type = ELF32_R_TYPE (dst->r_info);
+- BFD_ASSERT (r_type < (unsigned int) R_LM32_max);
++ if (r_type >= (unsigned int) R_LM32_max)
++ {
++ _bfd_error_handler (_("%A: invalid LM32 reloc number: %d"), abfd, r_type);
++ r_type = 0;
++ }
+ cache_ptr->howto = &lm32_elf_howto_table[r_type];
+ }
+
+--- a/bfd/elf32-m32c.c
++++ b/bfd/elf32-m32c.c
+@@ -297,7 +297,11 @@ m32c_info_to_howto_rela
+ unsigned int r_type;
+
+ r_type = ELF32_R_TYPE (dst->r_info);
+- BFD_ASSERT (r_type < (unsigned int) R_M32C_max);
++ if (r_type >= (unsigned int) R_M32C_max)
++ {
++ _bfd_error_handler (_("%A: invalid M32C reloc number: %d"), abfd, r_type);
++ r_type = 0;
++ }
+ cache_ptr->howto = & m32c_elf_howto_table [r_type];
+ }
+
+--- a/bfd/elf32-m32r.c
++++ b/bfd/elf32-m32r.c
+@@ -1280,7 +1280,11 @@ m32r_info_to_howto_rel (bfd *abfd ATTRIBUTE_UNUSED,
+ unsigned int r_type;
+
+ r_type = ELF32_R_TYPE (dst->r_info);
+- BFD_ASSERT (ELF32_R_TYPE(dst->r_info) <= (unsigned int) R_M32R_GNU_VTENTRY);
++ if (r_type > (unsigned int) R_M32R_GNU_VTENTRY)
++ {
++ _bfd_error_handler (_("%A: invalid M32R reloc number: %d"), abfd, r_type);
++ r_type = 0;
++ }
+ cache_ptr->howto = &m32r_elf_howto_table[r_type];
+ }
+
+--- a/bfd/elf32-m68hc11.c
++++ b/bfd/elf32-m68hc11.c
+@@ -384,7 +384,11 @@ m68hc11_info_to_howto_rel (bfd *abfd ATTRIBUTE_UNUSED,
+ unsigned int r_type;
+
+ r_type = ELF32_R_TYPE (dst->r_info);
+- BFD_ASSERT (r_type < (unsigned int) R_M68HC11_max);
++ if (r_type >= (unsigned int) R_M68HC11_max)
++ {
++ _bfd_error_handler (_("%A: invalid M68HC11 reloc number: %d"), abfd, r_type);
++ r_type = 0;
++ }
+ cache_ptr->howto = &elf_m68hc11_howto_table[r_type];
+ }
+
+--- a/bfd/elf32-m68hc12.c
++++ b/bfd/elf32-m68hc12.c
+@@ -504,7 +504,11 @@ m68hc11_info_to_howto_rel (bfd *abfd ATTRIBUTE_UNUSED,
+ unsigned int r_type;
+
+ r_type = ELF32_R_TYPE (dst->r_info);
+- BFD_ASSERT (r_type < (unsigned int) R_M68HC11_max);
++ if (r_type >= (unsigned int) R_M68HC11_max)
++ {
++ _bfd_error_handler (_("%A: invalid M68HC12 reloc number: %d"), abfd, r_type);
++ r_type = 0;
++ }
+ cache_ptr->howto = &elf_m68hc11_howto_table[r_type];
+ }
+
+--- a/bfd/elf32-mep.c
++++ b/bfd/elf32-mep.c
+@@ -400,6 +400,11 @@ mep_info_to_howto_rela
+ unsigned int r_type;
+
+ r_type = ELF32_R_TYPE (dst->r_info);
++ if (r_type >= R_MEP_max)
++ {
++ _bfd_error_handler (_("%A: invalid MEP reloc number: %d"), abfd, r_type);
++ r_type = 0;
++ }
+ cache_ptr->howto = & mep_elf_howto_table [r_type];
+ }
+
+--- a/bfd/elf32-metag.c
++++ b/bfd/elf32-metag.c
+@@ -896,7 +896,11 @@ metag_info_to_howto_rela (bfd *abfd ATTRIBUTE_UNUSED,
+ unsigned int r_type;
+
+ r_type = ELF32_R_TYPE (dst->r_info);
+- BFD_ASSERT (r_type < (unsigned int) R_METAG_MAX);
++ if (r_type >= (unsigned int) R_METAG_MAX)
++ {
++ _bfd_error_handler (_("%A: invalid METAG reloc number: %d"), abfd, r_type);
++ r_type = 0;
++ }
+ cache_ptr->howto = & elf_metag_howto_table [r_type];
+ }
+
+--- a/bfd/elf32-moxie.c
++++ b/bfd/elf32-moxie.c
+@@ -131,7 +131,11 @@ moxie_info_to_howto_rela (bfd *abfd ATTRIBUTE_UNUSED,
+ unsigned int r_type;
+
+ r_type = ELF32_R_TYPE (dst->r_info);
+- BFD_ASSERT (r_type < (unsigned int) R_MOXIE_max);
++ if (r_type >= (unsigned int) R_MOXIE_max)
++ {
++ _bfd_error_handler (_("%A: invalid Moxie reloc number: %d"), abfd, r_type);
++ r_type = 0;
++ }
+ cache_ptr->howto = & moxie_elf_howto_table [r_type];
+ }
+
+#--- a/bfd/elf32-msp430.c
+#+++ b/bfd/elf32-msp430.c
+#@@ -617,12 +617,20 @@ msp430_info_to_howto_rela (bfd * abfd ATTRIBUTE_UNUSED,
+#
+# if (uses_msp430x_relocs (abfd))
+# {
+#- BFD_ASSERT (r_type < (unsigned int) R_MSP430x_max);
+#+ if (r_type >= (unsigned int) R_MSP430x_max)
+#+ {
+#+ _bfd_error_handler (_("%A: invalid MSP430X reloc number: %d"), abfd, r_type);
+#+ r_type = 0;
+#+ }
+# cache_ptr->howto = elf_msp430x_howto_table + r_type;
+# return;
+# }
+#
+#- BFD_ASSERT (r_type < (unsigned int) R_MSP430_max);
+#+ if (r_type >= (unsigned int) R_MSP430_max)
+#+ {
+#+ _bfd_error_handler (_("%A: invalid MSP430 reloc number: %d"), abfd, r_type);
+#+ r_type = 0;
+#+ }
+# cache_ptr->howto = &elf_msp430_howto_table[r_type];
+# }
+#
+--- a/bfd/elf32-mt.c
++++ b/bfd/elf32-mt.c
+@@ -236,6 +236,11 @@ mt_info_to_howto_rela
+ unsigned int r_type;
+
+ r_type = ELF32_R_TYPE (dst->r_info);
++ if (r_type >= (unsigned int) R_MT_max)
++ {
++ _bfd_error_handler (_("%A: invalid MT reloc number: %d"), abfd, r_type);
++ r_type = 0;
++ }
+ cache_ptr->howto = & mt_elf_howto_table [r_type];
+ }
+
+#--- a/bfd/elf32-nds32.c
+#+++ b/bfd/elf32-nds32.c
+#@@ -2965,7 +2965,11 @@ nds32_info_to_howto_rel (bfd *abfd ATTRIBUTE_UNUSED, arelent *cache_ptr,
+# enum elf_nds32_reloc_type r_type;
+#
+# r_type = ELF32_R_TYPE (dst->r_info);
+#- BFD_ASSERT (ELF32_R_TYPE (dst->r_info) <= R_NDS32_GNU_VTENTRY);
+#+ if (r_type > R_NDS32_GNU_VTENTRY)
+#+ {
+#+ _bfd_error_handler (_("%A: invalid NDS32 reloc number: %d"), abfd, r_type);
+#+ r_type = 0;
+#+ }
+# cache_ptr->howto = bfd_elf32_bfd_reloc_type_table_lookup (r_type);
+# }
+#
+#--- a/bfd/elf32-or1k.c
+#+++ b/bfd/elf32-or1k.c
+#@@ -738,7 +738,11 @@ or1k_info_to_howto_rela (bfd * abfd ATTRIBUTE_UNUSED,
+# unsigned int r_type;
+#
+# r_type = ELF32_R_TYPE (dst->r_info);
+#- BFD_ASSERT (r_type < (unsigned int) R_OR1K_max);
+#+ if (r_type >= (unsigned int) R_OR1K_max)
+#+ {
+#+ _bfd_error_handler (_("%A: invalid OR1K reloc number: %d"), abfd, r_type);
+#+ r_type = 0;
+#+ }
+# cache_ptr->howto = & or1k_elf_howto_table[r_type];
+# }
+#
+--- a/bfd/elf32-rl78.c
++++ b/bfd/elf32-rl78.c
+@@ -276,7 +276,11 @@ rl78_info_to_howto_rela (bfd * abfd ATTRIBUTE_UNUSED,
+ unsigned int r_type;
+
+ r_type = ELF32_R_TYPE (dst->r_info);
+- BFD_ASSERT (r_type < (unsigned int) R_RL78_max);
++ if (r_type >= (unsigned int) R_RL78_max)
++ {
++ _bfd_error_handler (_("%A: invalid RL78 reloc number: %d"), abfd, r_type);
++ r_type = 0;
++ }
+ cache_ptr->howto = rl78_elf_howto_table + r_type;
+ }
+
+--- a/bfd/elf32-rx.c
++++ b/bfd/elf32-rx.c
+@@ -307,7 +307,11 @@ rx_info_to_howto_rela (bfd * abfd ATTRIBUTE_UNUSED,
+ unsigned int r_type;
+
+ r_type = ELF32_R_TYPE (dst->r_info);
+- BFD_ASSERT (r_type < (unsigned int) R_RX_max);
++ if (r_type >= (unsigned int) R_RX_max)
++ {
++ _bfd_error_handler (_("%A: invalid RX reloc number: %d"), abfd, r_type);
++ r_type = 0;
++ }
+ cache_ptr->howto = rx_elf_howto_table + r_type;
+ }
+
+--- a/bfd/elf32-v850.c
++++ b/bfd/elf32-v850.c
+@@ -1896,7 +1896,11 @@ v850_elf_info_to_howto_rel (bfd *abfd ATTRIBUTE_UNUSED,
+ unsigned int r_type;
+
+ r_type = ELF32_R_TYPE (dst->r_info);
+- BFD_ASSERT (r_type < (unsigned int) R_V850_max);
++ if (r_type >= (unsigned int) R_V850_max)
++ {
++ _bfd_error_handler (_("%A: invalid V850 reloc number: %d"), abfd, r_type);
++ r_type = 0;
++ }
+ cache_ptr->howto = &v850_elf_howto_table[r_type];
+ }
+
+#--- a/bfd/elf32-visium.c
+#+++ b/bfd/elf32-visium.c
+#@@ -501,6 +501,11 @@ visium_info_to_howto_rela (bfd *abfd ATTRIBUTE_UNUSED, arelent *cache_ptr,
+# break;
+#
+# default:
+#+ if (r_type >= (unsigned int) R_VISIUM_max)
+#+ {
+#+ _bfd_error_handler (_("%A: invalid Visium reloc number: %d"), abfd, r_type);
+#+ r_type = 0;
+#+ }
+# cache_ptr->howto = &visium_elf_howto_table[r_type];
+# break;
+# }
+--- a/bfd/elf32-xgate.c
++++ b/bfd/elf32-xgate.c
+@@ -422,7 +422,11 @@ xgate_info_to_howto_rel (bfd *abfd ATTRIBUTE_UNUSED,
+ unsigned int r_type;
+
+ r_type = ELF32_R_TYPE (dst->r_info);
+- BFD_ASSERT(r_type < (unsigned int) R_XGATE_max);
++ if (r_type >= (unsigned int) R_XGATE_max)
++ {
++ _bfd_error_handler (_("%A: invalid XGate reloc number: %d"), abfd, r_type);
++ r_type = 0;
++ }
+ cache_ptr->howto = &elf_xgate_howto_table[r_type];
+ }
+
+--- a/bfd/elf32-xtensa.c
++++ b/bfd/elf32-xtensa.c
+@@ -479,7 +479,11 @@ elf_xtensa_info_to_howto_rela (bfd *abfd ATTRIBUTE_UNUSED,
+ {
+ unsigned int r_type = ELF32_R_TYPE (dst->r_info);
+
+- BFD_ASSERT (r_type < (unsigned int) R_XTENSA_max);
++ if (r_type >= (unsigned int) R_XTENSA_max)
++ {
++ _bfd_error_handler (_("%A: invalid XTENSA reloc number: %d"), abfd, r_type);
++ r_type = 0;
++ }
+ cache_ptr->howto = &elf_howto_table[r_type];
+ }
+
+--- a/bfd/elf64-mmix.c
++++ b/bfd/elf64-mmix.c
+@@ -1259,7 +1259,11 @@ mmix_info_to_howto_rela (bfd *abfd ATTRIBUTE_UNUSED,
+ unsigned int r_type;
+
+ r_type = ELF64_R_TYPE (dst->r_info);
+- BFD_ASSERT (r_type < (unsigned int) R_MMIX_max);
++ if (r_type >= (unsigned int) R_MMIX_max)
++ {
++ _bfd_error_handler (_("%A: invalid MMIX reloc number: %d"), abfd, r_type);
++ r_type = 0;
++ }
+ cache_ptr->howto = &elf_mmix_howto_table[r_type];
+ }
+
+--- a/bfd/elf64-sparc.c
++++ b/bfd/elf64-sparc.c
+@@ -97,7 +97,9 @@ elf64_sparc_slurp_one_reloc_table (bfd *abfd, asection *asect,
+ else
+ relent->address = rela.r_offset - asect->vma;
+
+- if (ELF64_R_SYM (rela.r_info) == STN_UNDEF)
++ if (ELF64_R_SYM (rela.r_info) == STN_UNDEF
++ /* PR 17512: file: 996185f8. */
++ || ELF64_R_SYM (rela.r_info) > bfd_get_symcount (abfd))
+ relent->sym_ptr_ptr = bfd_abs_section_ptr->symbol_ptr_ptr;
+ else
+ {
+--- a/bfd/elf64-x86-64.c
++++ b/bfd/elf64-x86-64.c
+@@ -302,7 +302,7 @@ elf_x86_64_reloc_type_lookup (bfd *abfd,
+ return elf_x86_64_rtype_to_howto (abfd,
+ x86_64_reloc_map[i].elf_reloc_val);
+ }
+- return 0;
++ return NULL;
+ }
+
+ static reloc_howto_type *
+#--- a/bfd/elfnn-aarch64.c
+#+++ b/bfd/elfnn-aarch64.c
+#@@ -1431,6 +1431,14 @@ elfNN_aarch64_bfd_reloc_from_type (unsigned int r_type)
+# if (r_type == R_AARCH64_NONE || r_type == R_AARCH64_NULL)
+# return BFD_RELOC_AARCH64_NONE;
+#
+#+ /* PR 17512: file: b371e70a. */
+#+ if (r_type >= R_AARCH64_end)
+#+ {
+#+ _bfd_error_handler (_("Invalid AArch64 reloc number: %d"), r_type);
+#+ bfd_set_error (bfd_error_bad_value);
+#+ return BFD_RELOC_AARCH64_NONE;
+#+ }
+#+
+# return BFD_RELOC_AARCH64_RELOC_START + offsets[r_type];
+# }
+#
+#--- a/bfd/mach-o.c
+#+++ b/bfd/mach-o.c
+#@@ -1352,6 +1352,8 @@ bfd_mach_o_canonicalize_one_reloc (bfd *abfd,
+# /* PR 17512: file: 8396-1185-0.004. */
+# if (bfd_get_symcount (abfd) > 0 && num > bfd_get_symcount (abfd))
+# sym = bfd_und_section_ptr->symbol_ptr_ptr;
+#+ else if (syms == NULL)
+#+ sym = bfd_und_section_ptr->symbol_ptr_ptr;
+# else
+# /* An external symbol number. */
+# sym = syms + num;
+--- a/bfd/reloc.c
++++ b/bfd/reloc.c
+@@ -7623,6 +7623,10 @@ bfd_generic_get_relocated_section_contents (bfd *abfd,
+ (*parent)->howto = &none_howto;
+ r = bfd_reloc_ok;
+ }
++ /* PR 17512: file: c146ab8b. */
++ else if ((*parent)->address * bfd_octets_per_byte (abfd)
++ >= bfd_get_section_size (input_section))
++ r = bfd_reloc_outofrange;
+ else
+ r = bfd_perform_relocation (input_bfd,
+ *parent,
+#--- a/bfd/versados.c
+#+++ b/bfd/versados.c
+#@@ -373,10 +373,17 @@ process_otr (bfd *abfd, struct ext_otr *otr, int pass)
+# | (otr->map[3] << 0);
+#
+# struct esdid *esdid = &EDATA (abfd, otr->esdid - 1);
+#- unsigned char *contents = esdid->contents;
+#+ unsigned char *contents;
+# bfd_boolean need_contents = FALSE;
+#- unsigned int dst_idx = esdid->pc;
+#-
+#+ unsigned int dst_idx;
+#+
+#+ /* PR 17512: file: ac7da425. */
+#+ if (otr->esdid == 0)
+#+ return;
+#+
+#+ contents = esdid->contents;
+#+ dst_idx = esdid->pc;
+#+
+# for (shift = ((unsigned long) 1 << 31); shift && srcp < endp; shift >>= 1)
+# {
+# if (bits & shift)
+#@@ -399,7 +406,7 @@ process_otr (bfd *abfd, struct ext_otr *otr, int pass)
+#
+# if (pass == 1)
+# need_contents = TRUE;
+#- else if (contents)
+#+ else if (contents && dst_idx < esdid->section->size - sizeinwords * 2)
+# for (j = 0; j < sizeinwords * 2; j++)
+# {
+# contents[dst_idx + (sizeinwords * 2) - j - 1] = val;
+#@@ -421,10 +428,13 @@ process_otr (bfd *abfd, struct ext_otr *otr, int pass)
+# }
+# else
+# {
+#- arelent *n =
+#- EDATA (abfd, otr->esdid - 1).section->relocation + rn;
+#- n->address = dst_idx;
+#+ arelent *n;
+#
+#+ /* PR 17512: file: 54f733e0. */
+#+ if (EDATA (abfd, otr->esdid - 1).section == NULL)
+#+ continue;
+#+ n = EDATA (abfd, otr->esdid - 1).section->relocation + rn;
+#+ n->address = dst_idx;
+# n->sym_ptr_ptr = (asymbol **) (size_t) id;
+# n->addend = 0;
+# n->howto = versados_howto_table + ((j & 1) * 2) + (sizeinwords - 1);
+#@@ -798,7 +808,11 @@ versados_canonicalize_reloc (bfd *abfd,
+# /* Section relative thing. */
+# struct esdid *e = &EDATA (abfd, esdid - 1);
+#
+#- src[count].sym_ptr_ptr = e->section->symbol_ptr_ptr;
+#+ /* PR 17512: file:cd92277c. */
+#+ if (e->section)
+#+ src[count].sym_ptr_ptr = e->section->symbol_ptr_ptr;
+#+ else
+#+ src[count].sym_ptr_ptr = bfd_und_section_ptr->symbol_ptr_ptr;
+# }
+# /* PR 17512: file:3757-2936-0.004. */
+# else if ((unsigned) (esdid - ES_BASE) >= bfd_get_symcount (abfd))
+--- a/bfd/vms-alpha.c
++++ b/bfd/vms-alpha.c
+@@ -521,9 +521,11 @@ _bfd_vms_slurp_eisd (bfd *abfd, unsigned int offset)
+ asection *section;
+ flagword bfd_flags;
+
++ /* PR 17512: file: 3d9e9fe9. */
++ if (offset >= PRIV (recrd.rec_size))
++ return FALSE;
+ eisd = (struct vms_eisd *)(PRIV (recrd.rec) + offset);
+ rec_size = bfd_getl32 (eisd->eisdsize);
+-
+ if (rec_size == 0)
+ break;
+
+@@ -2527,6 +2529,9 @@ alpha_vms_object_p (bfd *abfd)
+ /* Reset the record pointer. */
+ PRIV (recrd.rec) = buf;
+
++ /* PR 17512: file: 7d7c57c2. */
++ if (PRIV (recrd.rec_size) < sizeof (struct vms_eihd))
++ goto error_ret;
+ vms_debug2 ((2, "file type is image\n"));
+
+ if (_bfd_vms_slurp_eihd (abfd, &eisd_offset, &eihs_offset) != TRUE)
diff --git a/SOURCES/gdb-rhbz1320945-power9-10of38.patch b/SOURCES/gdb-rhbz1320945-power9-10of38.patch
new file mode 100644
index 0000000..446f06c
--- /dev/null
+++ b/SOURCES/gdb-rhbz1320945-power9-10of38.patch
@@ -0,0 +1,62 @@
+commit ec93045b400ec68b0c5716d75f27a87533b57058
+Author: Nick Clifton <nickc@redhat.com>
+Date: Tue Jan 6 17:54:02 2015 +0000
+
+ Fix memory access violations for objdump triggered by fuzzed binaries.
+
+ PR binutils/17512
+ * reloc.c (bfd_get_reloc_size): Handle a reloc size of -1.
+ (bfd_perform_relocation): Include the size of the reloc in the
+ test for an out of range relocation.
+ (bfd_generic_get_relocated_section_contents): Remove reloc range
+ test.
+
+### a/bfd/ChangeLog
+### b/bfd/ChangeLog
+## -1,6 +1,12 @@
+ 2015-01-06 Nick Clifton <nickc@redhat.com>
+
+ PR binutils/17512
++ * reloc.c (bfd_get_reloc_size): Handle a reloc size of -1.
++ (bfd_perform_relocation): Include the size of the reloc in the
++ test for an out of range relocation.
++ (bfd_generic_get_relocated_section_contents): Remove reloc range
++ test.
++
+ * coff-i860.c (CALC_ADDEND): Always set an addend value.
+ * tekhex.c (getvalue): Add an end pointer parameter. Use it to
+ avoid reading off the end of the buffer.
+--- a/bfd/reloc.c
++++ b/bfd/reloc.c
+@@ -437,6 +437,7 @@ bfd_get_reloc_size (reloc_howto_type *howto)
+ case 3: return 0;
+ case 4: return 8;
+ case 8: return 16;
++ case -1: return 2;
+ case -2: return 4;
+ default: abort ();
+ }
+@@ -618,7 +619,11 @@ bfd_perform_relocation (bfd *abfd,
+ }
+
+ /* Is the address of the relocation really within the section? */
+- if (reloc_entry->address > bfd_get_section_limit (abfd, input_section))
++ if (reloc_entry->address > bfd_get_section_limit (abfd, input_section)
++ /* PR 17512: file: c146ab8b.
++ PR 17512: file: 46dff27f.
++ Include the size of the reloc in the test for out of range addresses. */
++ - bfd_get_reloc_size (howto))
+ return bfd_reloc_outofrange;
+
+ /* Work out which section the relocation is targeted at and the
+@@ -7623,10 +7628,6 @@ bfd_generic_get_relocated_section_contents (bfd *abfd,
+ (*parent)->howto = &none_howto;
+ r = bfd_reloc_ok;
+ }
+- /* PR 17512: file: c146ab8b. */
+- else if ((*parent)->address * bfd_octets_per_byte (abfd)
+- >= bfd_get_section_size (input_section))
+- r = bfd_reloc_outofrange;
+ else
+ r = bfd_perform_relocation (input_bfd,
+ *parent,
diff --git a/SOURCES/gdb-rhbz1320945-power9-11of38.patch b/SOURCES/gdb-rhbz1320945-power9-11of38.patch
new file mode 100644
index 0000000..1e7b628
--- /dev/null
+++ b/SOURCES/gdb-rhbz1320945-power9-11of38.patch
@@ -0,0 +1,437 @@
+commit cd21f5daad4335b50366b838664ade64bec29957
+Author: Nick Clifton <nickc@redhat.com>
+Date: Thu Jan 15 16:22:55 2015 +0000
+
+ Fix memory access violations triggered by running objdump on fuzzed binaries.
+
+ PR binutils/17512
+ * elf-m10300.c (mn10300_info_to_howto): Replace assertion with an
+ error message. Never return an invalid howto pointer.
+ * elf32-cr16.c (cr16_info_to_howto): Likewise.
+ * elf32-crx.c (elf_crx_info_to_howto): Likewise.
+ * elf32-i370.c (i370_elf_info_to_howto): Likewise.
+ * elf32-mcore.c (mcore_elf_info_to_howto): Likewise.
+ * elf32-microblaze.c (microblaze_elf_info_to_howto): Likewise.
+ * elf32-mips.c (mips_elf32_rtype_to_howto): Likewise.
+ * elf32-pj.c (pj_elf_info_to_howto): Likewise.
+ * elf32-ppc.c (ppc_elf_info_to_howto): Likewise.
+ * elf32-spu.c (spu_elf_info_to_howto): Likewise.
+ * elf32-v850.c (v850_elf_info_to_howto_rela): Likewise.
+ * elf32-vax.c (rtype_to_howto): Likewise.
+ * elf64-alpha.c (elf64_alpha_info_to_howto): Likewise.
+ * elf64-mips.c (mips_elf64_rtype_to_howto): Likewise.
+ * elfn32-mips.c (sh_elf_info_to_howto): Likewise.
+ * elf32-sh.c (sh_elf_info_to_howto): Likewise.
+ (sh_elf_reloc): Check that the reloc is in range.
+ * reloc.c (bfd_perform_relocation): Check that the section is big
+ enough for the entire reloc.
+ (bfd_generic_get_relocated_section_contents): Report unexpected
+ return values from perform_reloc.
+
+### a/bfd/ChangeLog
+### b/bfd/ChangeLog
+## -1,5 +1,31 @@
+ 2015-01-15 Nick Clifton <nickc@redhat.com>
+
++ PR binutils/17512
++ * elf-m10300.c (mn10300_info_to_howto): Replace assertion with an
++ error message. Never return an invalid howto pointer.
++ * elf32-cr16.c (cr16_info_to_howto): Likewise.
++ * elf32-crx.c (elf_crx_info_to_howto): Likewise.
++ * elf32-i370.c (i370_elf_info_to_howto): Likewise.
++ * elf32-mcore.c (mcore_elf_info_to_howto): Likewise.
++ * elf32-microblaze.c (microblaze_elf_info_to_howto): Likewise.
++ * elf32-mips.c (mips_elf32_rtype_to_howto): Likewise.
++ * elf32-pj.c (pj_elf_info_to_howto): Likewise.
++ * elf32-ppc.c (ppc_elf_info_to_howto): Likewise.
++ * elf32-spu.c (spu_elf_info_to_howto): Likewise.
++ * elf32-v850.c (v850_elf_info_to_howto_rela): Likewise.
++ * elf32-vax.c (rtype_to_howto): Likewise.
++ * elf64-alpha.c (elf64_alpha_info_to_howto): Likewise.
++ * elf64-mips.c (mips_elf64_rtype_to_howto): Likewise.
++ * elfn32-mips.c (sh_elf_info_to_howto): Likewise.
++ * elf32-sh.c (sh_elf_info_to_howto): Likewise.
++ (sh_elf_reloc): Check that the reloc is in range.
++ * reloc.c (bfd_perform_relocation): Check that the section is big
++ enough for the entire reloc.
++ (bfd_generic_get_relocated_section_contents): Report unexpected
++ return values from perform_reloc.
++
++2015-01-15 Nick Clifton <nickc@redhat.com>
++
+ * elf32-msp430.c (msp430_elf_relax_section): Skip unhandled
+ relocs. Include PC-relative adjustment for R_MSP430X_ABS16
+ relaxation.
+--- a/bfd/elf-m10300.c
++++ b/bfd/elf-m10300.c
+@@ -806,7 +806,13 @@ mn10300_info_to_howto (bfd *abfd ATTRIBUTE_UNUSED,
+ unsigned int r_type;
+
+ r_type = ELF32_R_TYPE (dst->r_info);
+- BFD_ASSERT (r_type < (unsigned int) R_MN10300_MAX);
++ if (r_type >= R_MN10300_MAX)
++ {
++ (*_bfd_error_handler) (_("%A: unrecognised MN10300 reloc number: %d"),
++ abfd, r_type);
++ bfd_set_error (bfd_error_bad_value);
++ r_type = R_MN10300_NONE;
++ }
+ cache_ptr->howto = elf_mn10300_howto_table + r_type;
+ }
+
+--- a/bfd/elf32-cr16.c
++++ b/bfd/elf32-cr16.c
+@@ -673,7 +673,13 @@ elf_cr16_info_to_howto (bfd *abfd ATTRIBUTE_UNUSED, arelent *cache_ptr,
+ {
+ unsigned int r_type = ELF32_R_TYPE (dst->r_info);
+
+- BFD_ASSERT (r_type < (unsigned int) R_CR16_MAX);
++ if (r_type >= R_CR16_MAX)
++ {
++ (*_bfd_error_handler) (_("%A: unrecognised CR16 reloc number: %d"),
++ abfd, r_type);
++ bfd_set_error (bfd_error_bad_value);
++ r_type = R_CR16_NONE;
++ }
+ cache_ptr->howto = cr16_elf_howto_table + r_type;
+ }
+
+--- a/bfd/elf32-crx.c
++++ b/bfd/elf32-crx.c
+@@ -423,7 +423,13 @@ elf_crx_info_to_howto (bfd *abfd ATTRIBUTE_UNUSED, arelent *cache_ptr,
+ Elf_Internal_Rela *dst)
+ {
+ unsigned int r_type = ELF32_R_TYPE (dst->r_info);
+- BFD_ASSERT (r_type < (unsigned int) R_CRX_MAX);
++ if (r_type >= R_CRX_MAX)
++ {
++ (*_bfd_error_handler) (_("%A: unrecognised CRX reloc number: %d"),
++ abfd, r_type);
++ bfd_set_error (bfd_error_bad_value);
++ r_type = R_CRX_NONE;
++ }
+ cache_ptr->howto = &crx_elf_howto_table[r_type];
+ }
+
+--- a/bfd/elf32-i370.c
++++ b/bfd/elf32-i370.c
+@@ -294,12 +294,21 @@ i370_elf_info_to_howto (bfd *abfd ATTRIBUTE_UNUSED,
+ arelent *cache_ptr,
+ Elf_Internal_Rela *dst)
+ {
++ unsigned int r_type;
++
+ if (!i370_elf_howto_table[ R_I370_ADDR31 ])
+ /* Initialize howto table. */
+ i370_elf_howto_init ();
+
+- BFD_ASSERT (ELF32_R_TYPE (dst->r_info) < (unsigned int) R_I370_max);
+- cache_ptr->howto = i370_elf_howto_table[ELF32_R_TYPE (dst->r_info)];
++ r_type = ELF32_R_TYPE (dst->r_info);
++ if (r_type >= R_I370_max)
++ {
++ (*_bfd_error_handler) (_("%A: unrecognised I370 reloc number: %d"),
++ abfd, r_type);
++ bfd_set_error (bfd_error_bad_value);
++ r_type = R_I370_NONE;
++ }
++ cache_ptr->howto = i370_elf_howto_table[r_type];
+ }
+
+ /* Hack alert -- the following several routines look generic to me ...
+--- a/bfd/elf32-mcore.c
++++ b/bfd/elf32-mcore.c
+@@ -340,13 +340,22 @@ mcore_elf_info_to_howto (bfd * abfd ATTRIBUTE_UNUSED,
+ arelent * cache_ptr,
+ Elf_Internal_Rela * dst)
+ {
++ unsigned int r_type;
++
+ if (! mcore_elf_howto_table [R_MCORE_PCRELIMM8BY4])
+ /* Initialize howto table if needed. */
+ mcore_elf_howto_init ();
+
+- BFD_ASSERT (ELF32_R_TYPE (dst->r_info) < (unsigned int) R_MCORE_max);
++ r_type = ELF32_R_TYPE (dst->r_info);
++ if (r_type >= R_MCORE_max)
++ {
++ (*_bfd_error_handler) (_("%A: unrecognised MCore reloc number: %d"),
++ abfd, r_type);
++ bfd_set_error (bfd_error_bad_value);
++ r_type = R_MCORE_NONE;
++ }
+
+- cache_ptr->howto = mcore_elf_howto_table [ELF32_R_TYPE (dst->r_info)];
++ cache_ptr->howto = mcore_elf_howto_table [r_type];
+ }
+
+ /* The RELOCATE_SECTION function is called by the ELF backend linker
+--- a/bfd/elf32-microblaze.c
++++ b/bfd/elf32-microblaze.c
+@@ -643,13 +643,22 @@ microblaze_elf_info_to_howto (bfd * abfd ATTRIBUTE_UNUSED,
+ arelent * cache_ptr,
+ Elf_Internal_Rela * dst)
+ {
++ unsigned int r_type;
++
+ if (!microblaze_elf_howto_table [R_MICROBLAZE_32])
+ /* Initialize howto table if needed. */
+ microblaze_elf_howto_init ();
+
+- BFD_ASSERT (ELF32_R_TYPE (dst->r_info) < (unsigned int) R_MICROBLAZE_max);
++ r_type = ELF32_R_TYPE (dst->r_info);
++ if (r_type >= R_MICROBLAZE_max)
++ {
++ (*_bfd_error_handler) (_("%A: unrecognised MicroBlaze reloc number: %d"),
++ abfd, r_type);
++ bfd_set_error (bfd_error_bad_value);
++ r_type = R_MICROBLAZE_NONE;
++ }
+
+- cache_ptr->howto = microblaze_elf_howto_table [ELF32_R_TYPE (dst->r_info)];
++ cache_ptr->howto = microblaze_elf_howto_table [r_type];
+ }
+
+ /* Microblaze ELF local labels start with 'L.' or '$L', not '.L'. */
+--- a/bfd/elf32-mips.c
++++ b/bfd/elf32-mips.c
+@@ -2204,7 +2204,12 @@ mips_elf32_rtype_to_howto (unsigned int r_type,
+ return &elf_micromips_howto_table_rel[r_type - R_MICROMIPS_min];
+ if (r_type >= R_MIPS16_min && r_type < R_MIPS16_max)
+ return &elf_mips16_howto_table_rel[r_type - R_MIPS16_min];
+- BFD_ASSERT (r_type < (unsigned int) R_MIPS_max);
++ if (r_type >= (unsigned int) R_MIPS_max)
++ {
++ (*_bfd_error_handler) (_("Unrecognised MIPS reloc number: %d"), r_type);
++ bfd_set_error (bfd_error_bad_value);
++ r_type = R_MIPS_NONE;
++ }
+ return &elf_mips_howto_table_rel[r_type];
+ }
+ }
+--- a/bfd/elf32-pj.c
++++ b/bfd/elf32-pj.c
+@@ -319,7 +319,13 @@ pj_elf_info_to_howto (bfd *abfd ATTRIBUTE_UNUSED,
+
+ r = ELF32_R_TYPE (dst->r_info);
+
+- BFD_ASSERT (r < (unsigned int) R_PJ_max);
++ if (r >= R_PJ_max)
++ {
++ (*_bfd_error_handler) (_("%A: unrecognised PicoJava reloc number: %d"),
++ abfd, r);
++ bfd_set_error (bfd_error_bad_value);
++ r = R_PJ_NONE;
++ }
+
+ cache_ptr->howto = &pj_elf_howto_table[r];
+ }
+--- a/bfd/elf32-ppc.c
++++ b/bfd/elf32-ppc.c
+@@ -2019,19 +2019,28 @@ ppc_elf_info_to_howto (bfd *abfd ATTRIBUTE_UNUSED,
+ arelent *cache_ptr,
+ Elf_Internal_Rela *dst)
+ {
++ unsigned int r_type;
++
+ /* Initialize howto table if not already done. */
+ if (!ppc_elf_howto_table[R_PPC_ADDR32])
+ ppc_elf_howto_init ();
+
+- BFD_ASSERT (ELF32_R_TYPE (dst->r_info) < (unsigned int) R_PPC_max);
+- cache_ptr->howto = ppc_elf_howto_table[ELF32_R_TYPE (dst->r_info)];
++ r_type = ELF32_R_TYPE (dst->r_info);
++ if (r_type >= R_PPC_max)
++ {
++ (*_bfd_error_handler) (_("%A: unrecognised PPC reloc number: %d"),
++ abfd, r_type);
++ bfd_set_error (bfd_error_bad_value);
++ r_type = R_PPC_NONE;
++ }
++ cache_ptr->howto = ppc_elf_howto_table[r_type];
+
+ /* Just because the above assert didn't trigger doesn't mean that
+ ELF32_R_TYPE (dst->r_info) is necessarily a valid relocation. */
+ if (!cache_ptr->howto)
+ {
+ (*_bfd_error_handler) (_("%B: invalid relocation type %d"),
+- abfd, ELF32_R_TYPE (dst->r_info));
++ abfd, r_type);
+ bfd_set_error (bfd_error_bad_value);
+
+ cache_ptr->howto = ppc_elf_howto_table[R_PPC_NONE];
+--- a/bfd/elf32-sh.c
++++ b/bfd/elf32-sh.c
+@@ -255,6 +255,13 @@ sh_elf_reloc (bfd *abfd, arelent *reloc_entry, asymbol *symbol_in,
+ && bfd_is_und_section (symbol_in->section))
+ return bfd_reloc_undefined;
+
++ /* PR 17512: file: 9891ca98. */
++ if (addr > bfd_get_section_limit (abfd, input_section)
++ - bfd_get_reloc_size (reloc_entry->howto)
++ || bfd_get_reloc_size (reloc_entry->howto)
++ > bfd_get_section_limit (abfd, input_section))
++ return bfd_reloc_outofrange;
++
+ if (bfd_is_com_section (symbol_in->section))
+ sym_value = 0;
+ else
+@@ -474,13 +481,19 @@ sh_elf_info_to_howto (bfd *abfd, arelent *cache_ptr, Elf_Internal_Rela *dst)
+
+ r = ELF32_R_TYPE (dst->r_info);
+
+- BFD_ASSERT (r < (unsigned int) R_SH_max);
+- BFD_ASSERT (r < R_SH_FIRST_INVALID_RELOC || r > R_SH_LAST_INVALID_RELOC);
+- BFD_ASSERT (r < R_SH_FIRST_INVALID_RELOC_2 || r > R_SH_LAST_INVALID_RELOC_2);
+- BFD_ASSERT (r < R_SH_FIRST_INVALID_RELOC_3 || r > R_SH_LAST_INVALID_RELOC_3);
+- BFD_ASSERT (r < R_SH_FIRST_INVALID_RELOC_4 || r > R_SH_LAST_INVALID_RELOC_4);
+- BFD_ASSERT (r < R_SH_FIRST_INVALID_RELOC_5 || r > R_SH_LAST_INVALID_RELOC_5);
+- BFD_ASSERT (r < R_SH_FIRST_INVALID_RELOC_6 || r > R_SH_LAST_INVALID_RELOC_6);
++ if (r >= R_SH_max
++ || (r >= R_SH_FIRST_INVALID_RELOC && r <= R_SH_LAST_INVALID_RELOC)
++ || (r >= R_SH_FIRST_INVALID_RELOC_2 && r <= R_SH_LAST_INVALID_RELOC_2)
++ || (r >= R_SH_FIRST_INVALID_RELOC_3 && r <= R_SH_LAST_INVALID_RELOC_3)
++ || (r >= R_SH_FIRST_INVALID_RELOC_4 && r <= R_SH_LAST_INVALID_RELOC_4)
++ || (r >= R_SH_FIRST_INVALID_RELOC_5 && r <= R_SH_LAST_INVALID_RELOC_5)
++ || (r >= R_SH_FIRST_INVALID_RELOC_6 && r <= R_SH_LAST_INVALID_RELOC_6))
++ {
++ (*_bfd_error_handler) (_("%A: unrecognised SH reloc number: %d"),
++ abfd, r);
++ bfd_set_error (bfd_error_bad_value);
++ r = R_SH_NONE;
++ }
+
+ cache_ptr->howto = get_howto_table (abfd) + r;
+ }
+--- a/bfd/elf32-spu.c
++++ b/bfd/elf32-spu.c
+@@ -151,7 +151,14 @@ spu_elf_info_to_howto (bfd *abfd ATTRIBUTE_UNUSED,
+ enum elf_spu_reloc_type r_type;
+
+ r_type = (enum elf_spu_reloc_type) ELF32_R_TYPE (dst->r_info);
+- BFD_ASSERT (r_type < R_SPU_max);
++ /* PR 17512: file: 90c2a92e. */
++ if (r_type >= R_SPU_max)
++ {
++ (*_bfd_error_handler) (_("%A: unrecognised SPU reloc number: %d"),
++ abfd, r_type);
++ bfd_set_error (bfd_error_bad_value);
++ r_type = R_SPU_NONE;
++ }
+ cache_ptr->howto = &elf_howto_table[(int) r_type];
+ }
+
+--- a/bfd/elf32-v850.c
++++ b/bfd/elf32-v850.c
+@@ -1914,7 +1914,11 @@ v850_elf_info_to_howto_rela (bfd *abfd ATTRIBUTE_UNUSED,
+ unsigned int r_type;
+
+ r_type = ELF32_R_TYPE (dst->r_info);
+- BFD_ASSERT (r_type < (unsigned int) R_V850_max);
++ if (r_type >= (unsigned int) R_V850_max)
++ {
++ _bfd_error_handler (_("%A: invalid V850 reloc number: %d"), abfd, r_type);
++ r_type = 0;
++ }
+ cache_ptr->howto = &v850_elf_howto_table[r_type];
+ }
+
+--- a/bfd/elf32-vax.c
++++ b/bfd/elf32-vax.c
+@@ -283,8 +283,17 @@ static void
+ rtype_to_howto (bfd *abfd ATTRIBUTE_UNUSED, arelent *cache_ptr,
+ Elf_Internal_Rela *dst)
+ {
+- BFD_ASSERT (ELF32_R_TYPE(dst->r_info) < (unsigned int) R_VAX_max);
+- cache_ptr->howto = &howto_table[ELF32_R_TYPE(dst->r_info)];
++ unsigned int r_type;
++
++ r_type = ELF32_R_TYPE (dst->r_info);
++ if (r_type >= R_VAX_max)
++ {
++ (*_bfd_error_handler) (_("%A: unrecognised VAX reloc number: %d"),
++ abfd, r_type);
++ bfd_set_error (bfd_error_bad_value);
++ r_type = R_VAX_NONE;
++ }
++ cache_ptr->howto = &howto_table[r_type];
+ }
+
+ #define elf_info_to_howto rtype_to_howto
+--- a/bfd/elf64-alpha.c
++++ b/bfd/elf64-alpha.c
+@@ -1105,7 +1105,14 @@ elf64_alpha_info_to_howto (bfd *abfd ATTRIBUTE_UNUSED, arelent *cache_ptr,
+ Elf_Internal_Rela *dst)
+ {
+ unsigned r_type = ELF64_R_TYPE(dst->r_info);
+- BFD_ASSERT (r_type < (unsigned int) R_ALPHA_max);
++
++ if (r_type >= R_ALPHA_max)
++ {
++ (*_bfd_error_handler) (_("%A: unrecognised Alpha reloc number: %d"),
++ abfd, r_type);
++ bfd_set_error (bfd_error_bad_value);
++ r_type = R_ALPHA_NONE;
++ }
+ cache_ptr->howto = &elf64_alpha_howto_table[r_type];
+ }
+
+--- a/bfd/elf64-mips.c
++++ b/bfd/elf64-mips.c
+@@ -3585,7 +3585,12 @@ mips_elf64_rtype_to_howto (unsigned int r_type, bfd_boolean rela_p)
+ else
+ return &mips16_elf64_howto_table_rel[r_type - R_MIPS16_min];
+ }
+- BFD_ASSERT (r_type < (unsigned int) R_MIPS_max);
++ if (r_type >= R_MIPS_max)
++ {
++ (*_bfd_error_handler) (_("unrecognised MIPS reloc number: %d"), r_type);
++ bfd_set_error (bfd_error_bad_value);
++ r_type = R_MIPS_NONE;
++ }
+ if (rela_p)
+ return &mips_elf64_howto_table_rela[r_type];
+ else
+--- a/bfd/elfn32-mips.c
++++ b/bfd/elfn32-mips.c
+@@ -3403,7 +3403,12 @@ mips_elf_n32_rtype_to_howto (unsigned int r_type, bfd_boolean rela_p)
+ else
+ return &elf_mips16_howto_table_rel[r_type - R_MIPS16_min];
+ }
+- BFD_ASSERT (r_type < (unsigned int) R_MIPS_max);
++ if (r_type >= R_MIPS_max)
++ {
++ (*_bfd_error_handler) (_("unrecognised MIPS reloc number: %d"), r_type);
++ bfd_set_error (bfd_error_bad_value);
++ r_type = R_MIPS_NONE;
++ }
+ if (rela_p)
+ return &elf_mips_howto_table_rela[r_type];
+ else
+--- a/bfd/reloc.c
++++ b/bfd/reloc.c
+@@ -623,7 +623,10 @@ bfd_perform_relocation (bfd *abfd,
+ /* PR 17512: file: c146ab8b.
+ PR 17512: file: 46dff27f.
+ Include the size of the reloc in the test for out of range addresses. */
+- - bfd_get_reloc_size (howto))
++ - bfd_get_reloc_size (howto)
++ /* PR 17512: file: 38e53ebf
++ Add make sure that there is enough room for the relocation to be applied. */
++ || bfd_get_reloc_size (howto) > bfd_get_section_limit (abfd, input_section))
+ return bfd_reloc_outofrange;
+
+ /* Work out which section the relocation is targeted at and the
+@@ -7691,7 +7694,11 @@ bfd_generic_get_relocated_section_contents (bfd *abfd,
+ goto error_return;
+
+ default:
+- abort ();
++ /* PR 17512; file: 90c2a92e.
++ Report unexpected results, without aborting. */
++ link_info->callbacks->einfo
++ (_("%X%P: %B(%A): relocation \"%R\" returns an unrecognized value %x\n"),
++ abfd, input_section, * parent, r);
+ break;
+ }
+
diff --git a/SOURCES/gdb-rhbz1320945-power9-12of38.patch b/SOURCES/gdb-rhbz1320945-power9-12of38.patch
new file mode 100644
index 0000000..7637d23
--- /dev/null
+++ b/SOURCES/gdb-rhbz1320945-power9-12of38.patch
@@ -0,0 +1,1626 @@
+commit 6346d5ca43719ba6fc3176c29fd58a83d439f011
+Author: Alan Modra <amodra@gmail.com>
+Date: Mon Jan 19 10:36:26 2015 +1030
+
+ Fallout from recent bfd_reloc_outofrange changes
+
+ Commit ec93045b and cd21f5da introduced a large number of tic4x and
+ tic54x regressions, due to the new checks being wrong for targets
+ with octets_per_byte != 1. To fix that I introduced a new
+ bfd_get_section_limit_octets and performed the check on octets rather
+ than byte adresses, reducing the number of bfd_octets_per_byte calls.
+ bfd_octets_per_byte is rather expensive..
+
+ I then wondered why the same bfd_reloc_outofrange check added to
+ bfd_perform_relocation wasn't also added to bfd_install_relocation.
+ The two functions are virtually identical and ought to remain that
+ way. However, adding the same check to bfd_install_relocation
+ resulted in ld-elf "FAIL Link eh-group.o to eh-group" on many ELF
+ targets, including x64_64-linux. The reason being that eh-group.o
+ has NONE relocs at the end of a section, and most targets give NONE
+ relocs a non-zero size. So if we are to keep the new outofrange
+ check it appears that NONE relocs must have a zero size.
+
+ * bfd-in.h (bfd_get_section_limit_octets): New define, extracted from..
+ (bfd_get_section_limit): ..here.
+ * reloc.c (bfd_perform_relocation): Correct bfd_reloc_outofrange check.
+ (bfd_install_relocation, _bfd_final_link_relocate): Add same check here.
+ * elf32-sh.c (sh_elf_reloc): Correct bfd_reloc_outofrange check.
+ * elf32-ppc.c (ppc_elf_addr16_ha_reloc): Remove duplicated
+ bfd_reloc_outofrange check.
+ * bfd-in2.h: Regenerate.
+
+ * cpu-ns32k.c (_bfd_do_ns32k_reloc_contents): Return bfd_reloc_ok
+ on zero size relocs.
+ * ecoff.c (ecoff_reloc_link_order): Likewise.
+ * elf32-nds32.c (nds32_relocate_contents): Likewise.
+ * elfxx-aarch64.c (_bfd_aarch64_elf_put_addend): Likewise.
+
+ * reloc.c (_bfd_relocate_contents): Don't bomb on zero size relocs.
+ (_bfd_clear_contents): Likewise.
+ * elfxx-mips.c (mips_elf_obtain_contents): Likewise.
+ (mips_elf_perform_relocation): Likewise.
+
+ * aoutx.h (aout_link_reloc_link_order): Allow for NULL return
+ from malloc on zero size alloc.
+ * cofflink.c (_bfd_coff_reloc_link_order): Likewise.
+ * elflink.c (elf_reloc_link_order): Likewise.
+ * linker.c (_bfd_generic_reloc_link_order): Likewise.
+ * pdp11.c (aout_link_reloc_link_order): Likewise.
+ * xcofflink.c (xcoff_reloc_link_order): Likewise.
+
+ * aoutx.h (howto_table_ext): Ensure NONE relocs have size 3,
+ bitsize 0, and complain_overflow_dont.
+ * coff-sparc.c (coff_sparc_howto_table): Likewise.
+ * elf-hppa.h (elf_hppa_howto_table): Likewise.
+ * elf-m10200.c (elf_mn10200_howto_table): Likewise.
+ * elf-m10300.c (elf_mn10300_howto_table): Likewise.
+ * elf32-arc.c (elf_arc_howto_table): Likewise.
+ * elf32-arm.c (elf32_arm_howto_table_1): Likewise.
+ * elf32-avr.c (elf_avr_howto_table): Likewise.
+ * elf32-bfin.c (bfin_howto_table): Likewise.
+ * elf32-cr16.c (cr16_elf_howto_table): Likewise.
+ * elf32-cris.c (cris_elf_howto_table): Likewise.
+ * elf32-crx.c (crx_elf_howto_table): Likewise.
+ * elf32-d10v.c (elf_d10v_howto_table): Likewise.
+ * elf32-d30v.c (elf_d30v_howto_table): Likewise.
+ * elf32-dlx.c (dlx_elf_howto_table): Likewise.
+ * elf32-epiphany.c (epiphany_elf_howto_table): Likewise.
+ * elf32-fr30.c (fr30_elf_howto_table): Likewise.
+ * elf32-frv.c (elf32_frv_howto_table): Likewise.
+ * elf32-h8300.c (h8_elf_howto_table): Likewise.
+ * elf32-i370.c (i370_elf_howto_raw): Likewise.
+ * elf32-i386.c (elf_howto_table): Likewise.
+ * elf32-i860.c (elf32_i860_howto_table): Likewise.
+ * elf32-i960.c (elf32_i960_relocate): Likewise.
+ * elf32-ip2k.c (ip2k_elf_howto_table): Likewise.
+ * elf32-iq2000.c (iq2000_elf_howto_table): Likewise.
+ * elf32-lm32.c (lm32_elf_howto_table): Likewise.
+ * elf32-m32c.c (m32c_elf_howto_table): Likewise.
+ * elf32-m32r.c (m32r_elf_howto_table): Likewise.
+ * elf32-m68hc11.c (elf_m68hc11_howto_table): Likewise.
+ * elf32-m68hc12.c (elf_m68hc11_howto_table): Likewise.
+ * elf32-m68k.c (howto_table): Likewise.
+ * elf32-mcore.c (mcore_elf_howto_raw): Likewise.
+ * elf32-mep.c (mep_elf_howto_table): Likewise.
+ * elf32-metag.c (elf_metag_howto_table): Likewise.
+ * elf32-microblaze.c (microblaze_elf_howto_raw): Likewise.
+ * elf32-mips.c (elf_mips_howto_table_rel): Likewise.
+ * elf32-moxie.c (moxie_elf_howto_table): Likewise.
+ * elf32-msp430.c (elf_msp430_howto_table): Likewise.
+ * elf32-mt.c (mt_elf_howto_table): Likewise.
+ * elf32-nds32.c (nds32_elf_howto_table): Likewise.
+ * elf32-nios2.c (elf_nios2_howto_table_rel): Likewise.
+ * elf32-or1k.c (or1k_elf_howto_table): Likewise.
+ * elf32-pj.c (pj_elf_howto_table): Likewise.
+ * elf32-ppc.c (ppc_elf_howto_raw): Likewise.
+ * elf32-rl78.c (rl78_elf_howto_table): Likewise.
+ * elf32-rx.c (rx_elf_howto_table): Likewise.
+ * elf32-s390.c (elf_howto_table): Likewise.
+ * elf32-score.c (elf32_score_howto_table): Likewise.
+ * elf32-score7.c (elf32_score_howto_table): Likewise.
+ * elf32-sh-relocs.h (R_SH_NONE): Likewise.
+ * elf32-spu.c (elf_howto_table): Likewise.
+ * elf32-tic6x.c (elf32_tic6x_howto_table): Likewise.
+ * elf32-tilepro.c (tilepro_elf_howto_table): Likewise.
+ * elf32-v850.c (v850_elf_howto_table): Likewise.
+ * elf32-vax.c (howto_table): Likewise.
+ * elf32-visium.c (visium_elf_howto_table): Likewise.
+ * elf32-xc16x.c (xc16x_elf_howto_table): Likewise.
+ * elf32-xgate.c (elf_xgate_howto_table): Likewise.
+ * elf32-xstormy16.c (xstormy16_elf_howto_table): Likewise.
+ * elf32-xtensa.c (elf_howto_table): Likewise.
+ * elf64-alpha.c (elf64_alpha_howto_table): Likewise.
+ * elf64-mips.c (mips_elf64_howto_table_rel): Likewise.
+ * elf64-mmix.c (elf_mmix_howto_table): Likewise.
+ * elf64-ppc.c (ppc64_elf_howto_raw): Likewise.
+ * elf64-s390.c (elf_howto_table): Likewise.
+ * elf64-sh64.c (sh_elf64_howto_table): Likewise.
+ * elf64-x86-64.c (x86_64_elf_howto_table): Likewise.
+ * elfn32-mips.c (elf_mips_howto_table_rel): Likewise.
+ * elfnn-aarch64.c (elfNN_aarch64_howto_table): Likewise.
+ (elfNN_aarch64_howto_none): Likewise.
+ * elfxx-ia64.c (ia64_howto_table): Likewise.
+ * elfxx-sparc.c (_bfd_sparc_elf_howto_table): Likewise.
+ * elfxx-tilegx.c (tilegx_elf_howto_table): Likewise.
+ * nlm32-sparc.c (nlm32_sparc_howto_table): Likewise.
+
+### a/bfd/ChangeLog
+### b/bfd/ChangeLog
+## -1,3 +1,109 @@
++2015-01-19 Alan Modra <amodra@gmail.com>
++
++ * bfd-in.h (bfd_get_section_limit_octets): New define, extracted from..
++ (bfd_get_section_limit): ..here.
++ * reloc.c (bfd_perform_relocation): Correct bfd_reloc_outofrange check.
++ (bfd_install_relocation, _bfd_final_link_relocate): Add same check here.
++ * elf32-sh.c (sh_elf_reloc): Correct bfd_reloc_outofrange check.
++ * elf32-ppc.c (ppc_elf_addr16_ha_reloc): Remove duplicated
++ bfd_reloc_outofrange check.
++ * bfd-in2.h: Regenerate.
++
++ * cpu-ns32k.c (_bfd_do_ns32k_reloc_contents): Return bfd_reloc_ok
++ on zero size relocs.
++ * ecoff.c (ecoff_reloc_link_order): Likewise.
++ * elf32-nds32.c (nds32_relocate_contents): Likewise.
++ * elfxx-aarch64.c (_bfd_aarch64_elf_put_addend): Likewise.
++
++ * reloc.c (_bfd_relocate_contents): Don't bomb on zero size relocs.
++ (_bfd_clear_contents): Likewise.
++ * elfxx-mips.c (mips_elf_obtain_contents): Likewise.
++ (mips_elf_perform_relocation): Likewise.
++
++ * aoutx.h (aout_link_reloc_link_order): Allow for NULL return
++ from malloc on zero size alloc.
++ * cofflink.c (_bfd_coff_reloc_link_order): Likewise.
++ * elflink.c (elf_reloc_link_order): Likewise.
++ * linker.c (_bfd_generic_reloc_link_order): Likewise.
++ * pdp11.c (aout_link_reloc_link_order): Likewise.
++ * xcofflink.c (xcoff_reloc_link_order): Likewise.
++
++ * aoutx.h (howto_table_ext): Ensure NONE relocs have size 3,
++ bitsize 0, and complain_overflow_dont.
++ * coff-sparc.c (coff_sparc_howto_table): Likewise.
++ * elf-hppa.h (elf_hppa_howto_table): Likewise.
++ * elf-m10200.c (elf_mn10200_howto_table): Likewise.
++ * elf-m10300.c (elf_mn10300_howto_table): Likewise.
++ * elf32-arc.c (elf_arc_howto_table): Likewise.
++ * elf32-arm.c (elf32_arm_howto_table_1): Likewise.
++ * elf32-avr.c (elf_avr_howto_table): Likewise.
++ * elf32-bfin.c (bfin_howto_table): Likewise.
++ * elf32-cr16.c (cr16_elf_howto_table): Likewise.
++ * elf32-cris.c (cris_elf_howto_table): Likewise.
++ * elf32-crx.c (crx_elf_howto_table): Likewise.
++ * elf32-d10v.c (elf_d10v_howto_table): Likewise.
++ * elf32-d30v.c (elf_d30v_howto_table): Likewise.
++ * elf32-dlx.c (dlx_elf_howto_table): Likewise.
++ * elf32-epiphany.c (epiphany_elf_howto_table): Likewise.
++ * elf32-fr30.c (fr30_elf_howto_table): Likewise.
++ * elf32-frv.c (elf32_frv_howto_table): Likewise.
++ * elf32-h8300.c (h8_elf_howto_table): Likewise.
++ * elf32-i370.c (i370_elf_howto_raw): Likewise.
++ * elf32-i386.c (elf_howto_table): Likewise.
++ * elf32-i860.c (elf32_i860_howto_table): Likewise.
++ * elf32-i960.c (elf32_i960_relocate): Likewise.
++ * elf32-ip2k.c (ip2k_elf_howto_table): Likewise.
++ * elf32-iq2000.c (iq2000_elf_howto_table): Likewise.
++ * elf32-lm32.c (lm32_elf_howto_table): Likewise.
++ * elf32-m32c.c (m32c_elf_howto_table): Likewise.
++ * elf32-m32r.c (m32r_elf_howto_table): Likewise.
++ * elf32-m68hc11.c (elf_m68hc11_howto_table): Likewise.
++ * elf32-m68hc12.c (elf_m68hc11_howto_table): Likewise.
++ * elf32-m68k.c (howto_table): Likewise.
++ * elf32-mcore.c (mcore_elf_howto_raw): Likewise.
++ * elf32-mep.c (mep_elf_howto_table): Likewise.
++ * elf32-metag.c (elf_metag_howto_table): Likewise.
++ * elf32-microblaze.c (microblaze_elf_howto_raw): Likewise.
++ * elf32-mips.c (elf_mips_howto_table_rel): Likewise.
++ * elf32-moxie.c (moxie_elf_howto_table): Likewise.
++ * elf32-msp430.c (elf_msp430_howto_table): Likewise.
++ * elf32-mt.c (mt_elf_howto_table): Likewise.
++ * elf32-nds32.c (nds32_elf_howto_table): Likewise.
++ * elf32-nios2.c (elf_nios2_howto_table_rel): Likewise.
++ * elf32-or1k.c (or1k_elf_howto_table): Likewise.
++ * elf32-pj.c (pj_elf_howto_table): Likewise.
++ * elf32-ppc.c (ppc_elf_howto_raw): Likewise.
++ * elf32-rl78.c (rl78_elf_howto_table): Likewise.
++ * elf32-rx.c (rx_elf_howto_table): Likewise.
++ * elf32-s390.c (elf_howto_table): Likewise.
++ * elf32-score.c (elf32_score_howto_table): Likewise.
++ * elf32-score7.c (elf32_score_howto_table): Likewise.
++ * elf32-sh-relocs.h (R_SH_NONE): Likewise.
++ * elf32-spu.c (elf_howto_table): Likewise.
++ * elf32-tic6x.c (elf32_tic6x_howto_table): Likewise.
++ * elf32-tilepro.c (tilepro_elf_howto_table): Likewise.
++ * elf32-v850.c (v850_elf_howto_table): Likewise.
++ * elf32-vax.c (howto_table): Likewise.
++ * elf32-visium.c (visium_elf_howto_table): Likewise.
++ * elf32-xc16x.c (xc16x_elf_howto_table): Likewise.
++ * elf32-xgate.c (elf_xgate_howto_table): Likewise.
++ * elf32-xstormy16.c (xstormy16_elf_howto_table): Likewise.
++ * elf32-xtensa.c (elf_howto_table): Likewise.
++ * elf64-alpha.c (elf64_alpha_howto_table): Likewise.
++ * elf64-mips.c (mips_elf64_howto_table_rel): Likewise.
++ * elf64-mmix.c (elf_mmix_howto_table): Likewise.
++ * elf64-ppc.c (ppc64_elf_howto_raw): Likewise.
++ * elf64-s390.c (elf_howto_table): Likewise.
++ * elf64-sh64.c (sh_elf64_howto_table): Likewise.
++ * elf64-x86-64.c (x86_64_elf_howto_table): Likewise.
++ * elfn32-mips.c (elf_mips_howto_table_rel): Likewise.
++ * elfnn-aarch64.c (elfNN_aarch64_howto_table): Likewise.
++ (elfNN_aarch64_howto_none): Likewise.
++ * elfxx-ia64.c (ia64_howto_table): Likewise.
++ * elfxx-sparc.c (_bfd_sparc_elf_howto_table): Likewise.
++ * elfxx-tilegx.c (tilegx_elf_howto_table): Likewise.
++ * nlm32-sparc.c (nlm32_sparc_howto_table): Likewise.
++
+ 2015-01-15 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR ld/17847
+--- a/bfd/aoutx.h
++++ b/bfd/aoutx.h
+@@ -203,8 +203,8 @@ reloc_howto_type howto_table_ext[] =
+ HOWTO (RELOC_GLOB_DAT,0, 2, 0, FALSE, 0, complain_overflow_bitfield, 0, "GLOB_DAT", FALSE, 0, 0x00000000, FALSE),
+ HOWTO (RELOC_JMP_SLOT,0, 2, 0, FALSE, 0, complain_overflow_bitfield, 0, "JMP_SLOT", FALSE, 0, 0x00000000, FALSE),
+ HOWTO (RELOC_RELATIVE,0, 2, 0, FALSE, 0, complain_overflow_bitfield, 0, "RELATIVE", FALSE, 0, 0x00000000, FALSE),
+- HOWTO (0, 0, 0, 0, FALSE, 0, complain_overflow_dont, 0, "R_SPARC_NONE",FALSE, 0, 0x00000000, TRUE),
+- HOWTO (0, 0, 0, 0, FALSE, 0, complain_overflow_dont, 0, "R_SPARC_NONE",FALSE, 0, 0x00000000, TRUE),
++ HOWTO (0, 0, 3, 0, FALSE, 0, complain_overflow_dont, 0, "R_SPARC_NONE",FALSE, 0, 0x00000000, TRUE),
++ HOWTO (0, 0, 3, 0, FALSE, 0, complain_overflow_dont, 0, "R_SPARC_NONE",FALSE, 0, 0x00000000, TRUE),
+ #define RELOC_SPARC_REV32 RELOC_WDISP19
+ HOWTO (RELOC_SPARC_REV32, 0, 2, 32, FALSE, 0, complain_overflow_dont, 0,"R_SPARC_REV32",FALSE, 0, 0xffffffff, FALSE),
+ };
+@@ -3816,7 +3816,7 @@ aout_link_reloc_link_order (struct aout_final_link_info *flaginfo,
+
+ size = bfd_get_reloc_size (howto);
+ buf = (bfd_byte *) bfd_zmalloc (size);
+- if (buf == NULL)
++ if (buf == NULL && size != 0)
+ return FALSE;
+ r = MY_relocate_contents (howto, flaginfo->output_bfd,
+ (bfd_vma) pr->addend, buf);
+--- a/bfd/bfd-in.h
++++ b/bfd/bfd-in.h
+@@ -292,10 +292,13 @@ typedef struct bfd_section *sec_ptr;
+
+ #define bfd_is_com_section(ptr) (((ptr)->flags & SEC_IS_COMMON) != 0)
+
++#define bfd_get_section_limit_octets(bfd, sec) \
++ ((bfd)->direction != write_direction && (sec)->rawsize != 0 \
++ ? (sec)->rawsize : (sec)->size)
++
+ /* Find the address one past the end of SEC. */
+ #define bfd_get_section_limit(bfd, sec) \
+- (((bfd)->direction != write_direction && (sec)->rawsize != 0 \
+- ? (sec)->rawsize : (sec)->size) / bfd_octets_per_byte (bfd))
++ (bfd_get_section_limit_octets(bfd, sec) / bfd_octets_per_byte (bfd))
+
+ /* Return TRUE if input section SEC has been discarded. */
+ #define discarded_section(sec) \
+--- a/bfd/bfd-in2.h
++++ b/bfd/bfd-in2.h
+@@ -299,10 +299,13 @@ typedef struct bfd_section *sec_ptr;
+
+ #define bfd_is_com_section(ptr) (((ptr)->flags & SEC_IS_COMMON) != 0)
+
++#define bfd_get_section_limit_octets(bfd, sec) \
++ ((bfd)->direction != write_direction && (sec)->rawsize != 0 \
++ ? (sec)->rawsize : (sec)->size)
++
+ /* Find the address one past the end of SEC. */
+ #define bfd_get_section_limit(bfd, sec) \
+- (((bfd)->direction != write_direction && (sec)->rawsize != 0 \
+- ? (sec)->rawsize : (sec)->size) / bfd_octets_per_byte (bfd))
++ (bfd_get_section_limit_octets(bfd, sec) / bfd_octets_per_byte (bfd))
+
+ /* Return TRUE if input section SEC has been discarded. */
+ #define discarded_section(sec) \
+--- a/bfd/coff-sparc.c
++++ b/bfd/coff-sparc.c
+@@ -74,7 +74,7 @@ bfd_coff_generic_reloc (bfd *abfd ATTRIBUTE_UNUSED,
+
+ static reloc_howto_type coff_sparc_howto_table[] =
+ {
+- HOWTO(R_SPARC_NONE, 0,0, 0,FALSE,0,complain_overflow_dont, bfd_coff_generic_reloc,"R_SPARC_NONE", FALSE,0,0x00000000,TRUE),
++ HOWTO(R_SPARC_NONE, 0,3, 0,FALSE,0,complain_overflow_dont, bfd_coff_generic_reloc,"R_SPARC_NONE", FALSE,0,0x00000000,TRUE),
+ HOWTO(R_SPARC_8, 0,0, 8,FALSE,0,complain_overflow_bitfield,bfd_coff_generic_reloc,"R_SPARC_8", FALSE,0,0x000000ff,TRUE),
+ HOWTO(R_SPARC_16, 0,1,16,FALSE,0,complain_overflow_bitfield,bfd_coff_generic_reloc,"R_SPARC_16", FALSE,0,0x0000ffff,TRUE),
+ HOWTO(R_SPARC_32, 0,2,32,FALSE,0,complain_overflow_bitfield,bfd_coff_generic_reloc,"R_SPARC_32", FALSE,0,0xffffffff,TRUE),
+--- a/bfd/cofflink.c
++++ b/bfd/cofflink.c
+@@ -2789,7 +2789,7 @@ _bfd_coff_reloc_link_order (bfd *output_bfd,
+
+ size = bfd_get_reloc_size (howto);
+ buf = (bfd_byte *) bfd_zmalloc (size);
+- if (buf == NULL)
++ if (buf == NULL && size != 0)
+ return FALSE;
+
+ rstat = _bfd_relocate_contents (howto, output_bfd,
+--- a/bfd/cpu-ns32k.c
++++ b/bfd/cpu-ns32k.c
+@@ -585,8 +585,9 @@ _bfd_do_ns32k_reloc_contents (reloc_howto_type *howto,
+ switch (size)
+ {
+ default:
+- case 0:
+ abort ();
++ case 0:
++ return bfd_reloc_ok;
+ case 1:
+ case 2:
+ case 4:
+--- a/bfd/ecoff.c
++++ b/bfd/ecoff.c
+@@ -3999,7 +3999,7 @@ ecoff_reloc_link_order (bfd *output_bfd,
+
+ size = bfd_get_reloc_size (rel.howto);
+ buf = (bfd_byte *) bfd_zmalloc (size);
+- if (buf == NULL)
++ if (buf == NULL && size != 0)
+ return FALSE;
+ rstat = _bfd_relocate_contents (rel.howto, output_bfd,
+ (bfd_vma) addend, buf);
+--- a/bfd/elf-hppa.h
++++ b/bfd/elf-hppa.h
+@@ -47,7 +47,7 @@
+
+ static reloc_howto_type elf_hppa_howto_table[ELF_HOWTO_TABLE_SIZE] =
+ {
+- { R_PARISC_NONE, 0, 0, 0, FALSE, 0, complain_overflow_bitfield,
++ { R_PARISC_NONE, 0, 3, 0, FALSE, 0, complain_overflow_dont,
+ bfd_elf_generic_reloc, "R_PARISC_NONE", FALSE, 0, 0, FALSE },
+
+ /* The values in DIR32 are to placate the check in
+--- a/bfd/elf-m10200.c
++++ b/bfd/elf-m10200.c
+@@ -46,11 +46,11 @@ static reloc_howto_type elf_mn10200_howto_table[] =
+ /* Dummy relocation. Does nothing. */
+ HOWTO (R_MN10200_NONE,
+ 0,
+- 2,
+- 16,
++ 3,
++ 0,
+ FALSE,
+ 0,
+- complain_overflow_bitfield,
++ complain_overflow_dont,
+ bfd_elf_generic_reloc,
+ "R_MN10200_NONE",
+ FALSE,
+--- a/bfd/elf-m10300.c
++++ b/bfd/elf-m10300.c
+@@ -142,11 +142,11 @@ static reloc_howto_type elf_mn10300_howto_table[] =
+ /* Dummy relocation. Does nothing. */
+ HOWTO (R_MN10300_NONE,
+ 0,
+- 2,
+- 16,
++ 3,
++ 0,
+ FALSE,
+ 0,
+- complain_overflow_bitfield,
++ complain_overflow_dont,
+ bfd_elf_generic_reloc,
+ "R_MN10300_NONE",
+ FALSE,
+--- a/bfd/elf32-arc.c
++++ b/bfd/elf32-arc.c
+@@ -58,8 +58,8 @@ static reloc_howto_type elf_arc_howto_table[] =
+ /* This reloc does nothing. */
+ HOWTO (R_ARC_NONE, /* Type. */
+ 0, /* Rightshift. */
+- 2, /* Size (0 = byte, 1 = short, 2 = long). */
+- 32, /* Bitsize. */
++ 3, /* Size (0 = byte, 1 = short, 2 = long). */
++ 0, /* Bitsize. */
+ FALSE, /* PC_relative. */
+ 0, /* Bitpos. */
+ complain_overflow_bitfield, /* Complain_on_overflow. */
+--- a/bfd/elf32-arm.c
++++ b/bfd/elf32-arm.c
+@@ -79,7 +79,7 @@ static reloc_howto_type elf32_arm_howto_table_1[] =
+ /* No relocation. */
+ HOWTO (R_ARM_NONE, /* type */
+ 0, /* rightshift */
+- 0, /* size (0 = byte, 1 = short, 2 = long) */
++ 3, /* size (0 = byte, 1 = short, 2 = long) */
+ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+--- a/bfd/elf32-avr.c
++++ b/bfd/elf32-avr.c
+@@ -121,11 +121,11 @@ static reloc_howto_type elf_avr_howto_table[] =
+ {
+ HOWTO (R_AVR_NONE, /* type */
+ 0, /* rightshift */
+- 2, /* size (0 = byte, 1 = short, 2 = long) */
+- 32, /* bitsize */
++ 3, /* size (0 = byte, 1 = short, 2 = long) */
++ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_AVR_NONE", /* name */
+ FALSE, /* partial_inplace */
+--- a/bfd/elf32-bfin.c
++++ b/bfd/elf32-bfin.c
+@@ -423,11 +423,11 @@ static reloc_howto_type bfin_howto_table [] =
+ /* This reloc does nothing. . */
+ HOWTO (R_BFIN_UNUSED0, /* type. */
+ 0, /* rightshift. */
+- 2, /* size (0 = byte, 1 = short, 2 = long). */
+- 32, /* bitsize. */
++ 3, /* size (0 = byte, 1 = short, 2 = long). */
++ 0, /* bitsize. */
+ FALSE, /* pc_relative. */
+ 0, /* bitpos. */
+- complain_overflow_bitfield, /* complain_on_overflow. */
++ complain_overflow_dont, /* complain_on_overflow. */
+ bfd_elf_generic_reloc, /* special_function. */
+ "R_BFIN_UNUSED0", /* name. */
+ FALSE, /* partial_inplace. */
+@@ -451,11 +451,11 @@ static reloc_howto_type bfin_howto_table [] =
+
+ HOWTO (R_BFIN_UNUSED1, /* type. */
+ 0, /* rightshift. */
+- 2, /* size (0 = byte, 1 = short, 2 = long). */
+- 32, /* bitsize. */
++ 3, /* size (0 = byte, 1 = short, 2 = long). */
++ 0, /* bitsize. */
+ FALSE, /* pc_relative. */
+ 0, /* bitpos. */
+- complain_overflow_bitfield, /* complain_on_overflow. */
++ complain_overflow_dont, /* complain_on_overflow. */
+ bfd_elf_generic_reloc, /* special_function. */
+ "R_BFIN_UNUSED1", /* name. */
+ FALSE, /* partial_inplace. */
+@@ -581,8 +581,8 @@ static reloc_howto_type bfin_howto_table [] =
+
+ HOWTO (R_BFIN_UNUSEDB, /* type. */
+ 0, /* rightshift. */
+- 2, /* size (0 = byte, 1 = short, 2 = long). */
+- 32, /* bitsize. */
++ 3, /* size (0 = byte, 1 = short, 2 = long). */
++ 0, /* bitsize. */
+ FALSE, /* pc_relative. */
+ 0, /* bitpos. */
+ complain_overflow_dont, /* complain_on_overflow. */
+@@ -595,8 +595,8 @@ static reloc_howto_type bfin_howto_table [] =
+
+ HOWTO (R_BFIN_UNUSEDC, /* type. */
+ 0, /* rightshift. */
+- 2, /* size (0 = byte, 1 = short, 2 = long). */
+- 32, /* bitsize. */
++ 3, /* size (0 = byte, 1 = short, 2 = long). */
++ 0, /* bitsize. */
+ FALSE, /* pc_relative. */
+ 0, /* bitpos. */
+ complain_overflow_dont, /* complain_on_overflow. */
+--- a/bfd/elf32-cr16.c
++++ b/bfd/elf32-cr16.c
+@@ -115,8 +115,8 @@ static reloc_howto_type cr16_elf_howto_table[] =
+ {
+ HOWTO (R_CR16_NONE, /* type */
+ 0, /* rightshift */
+- 2, /* size */
+- 32, /* bitsize */
++ 3, /* size */
++ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+--- a/bfd/elf32-cris.c
++++ b/bfd/elf32-cris.c
+@@ -40,11 +40,11 @@ static reloc_howto_type cris_elf_howto_table [] =
+ /* This reloc does nothing. */
+ HOWTO (R_CRIS_NONE, /* type */
+ 0, /* rightshift */
+- 2, /* size (0 = byte, 1 = short, 2 = long) */
+- 32, /* bitsize */
++ 3, /* size (0 = byte, 1 = short, 2 = long) */
++ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_CRIS_NONE", /* name */
+ FALSE, /* partial_inplace */
+--- a/bfd/elf32-crx.c
++++ b/bfd/elf32-crx.c
+@@ -82,8 +82,8 @@ static reloc_howto_type crx_elf_howto_table[] =
+ {
+ HOWTO (R_CRX_NONE, /* type */
+ 0, /* rightshift */
+- 2, /* size */
+- 32, /* bitsize */
++ 3, /* size */
++ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont,/* complain_on_overflow */
+--- a/bfd/elf32-d10v.c
++++ b/bfd/elf32-d10v.c
+@@ -33,8 +33,8 @@ static reloc_howto_type elf_d10v_howto_table[] =
+ /* This reloc does nothing. */
+ HOWTO (R_D10V_NONE, /* Type. */
+ 0, /* Rightshift. */
+- 2, /* Size (0 = byte, 1 = short, 2 = long). */
+- 32, /* Bitsize. */
++ 3, /* Size (0 = byte, 1 = short, 2 = long). */
++ 0, /* Bitsize. */
+ FALSE, /* PC_relative. */
+ 0, /* Bitpos. */
+ complain_overflow_dont,/* Complain_on_overflow. */
+--- a/bfd/elf32-d30v.c
++++ b/bfd/elf32-d30v.c
+@@ -254,11 +254,11 @@ static reloc_howto_type elf_d30v_howto_table[] =
+ /* This reloc does nothing. */
+ HOWTO (R_D30V_NONE, /* Type. */
+ 0, /* Rightshift. */
+- 2, /* Size (0 = byte, 1 = short, 2 = long). */
+- 32, /* Bitsize. */
++ 3, /* Size (0 = byte, 1 = short, 2 = long). */
++ 0, /* Bitsize. */
+ FALSE, /* PC_relative. */
+ 0, /* Bitpos. */
+- complain_overflow_bitfield, /* Complain_on_overflow. */
++ complain_overflow_dont, /* Complain_on_overflow. */
+ bfd_elf_generic_reloc, /* Special_function. */
+ "R_D30V_NONE", /* Name. */
+ FALSE, /* Partial_inplace. */
+--- a/bfd/elf32-dlx.c
++++ b/bfd/elf32-dlx.c
+@@ -237,7 +237,7 @@ static reloc_howto_type dlx_elf_howto_table[]=
+ /* No relocation. */
+ HOWTO (R_DLX_NONE, /* Type. */
+ 0, /* Rightshift. */
+- 0, /* size (0 = byte, 1 = short, 2 = long). */
++ 3, /* size (0 = byte, 1 = short, 2 = long). */
+ 0, /* Bitsize. */
+ FALSE, /* PC_relative. */
+ 0, /* Bitpos. */
+--- a/bfd/elf32-epiphany.c
++++ b/bfd/elf32-epiphany.c
+@@ -63,7 +63,7 @@ static reloc_howto_type epiphany_elf_howto_table [] =
+ pr) /* pcrel_offset */
+
+ /* This reloc does nothing. */
+- AHOW (R_EPIPHANY_NONE, 0, 0,32, FALSE, 0, complain_overflow_dont, "R_EPIPHANY_NONE", 0, 0),
++ AHOW (R_EPIPHANY_NONE, 0, 3,0, FALSE, 0, complain_overflow_dont, "R_EPIPHANY_NONE", 0, 0),
+
+ /* 8 bit absolute (not likely) */
+ AHOW (R_EPIPHANY_8, 0, 0, 8, FALSE, 0, complain_overflow_bitfield, "R_EPIPHANY_8", 0x000000ff, 0x000000ff),
+--- a/bfd/elf32-fr30.c
++++ b/bfd/elf32-fr30.c
+@@ -37,11 +37,11 @@ static reloc_howto_type fr30_elf_howto_table [] =
+ /* This reloc does nothing. */
+ HOWTO (R_FR30_NONE, /* type */
+ 0, /* rightshift */
+- 2, /* size (0 = byte, 1 = short, 2 = long) */
+- 32, /* bitsize */
++ 3, /* size (0 = byte, 1 = short, 2 = long) */
++ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_FR30_NONE", /* name */
+ FALSE, /* partial_inplace */
+--- a/bfd/elf32-frv.c
++++ b/bfd/elf32-frv.c
+@@ -34,11 +34,11 @@ static reloc_howto_type elf32_frv_howto_table [] =
+ /* This reloc does nothing. */
+ HOWTO (R_FRV_NONE, /* type */
+ 0, /* rightshift */
+- 2, /* size (0 = byte, 1 = short, 2 = long) */
+- 32, /* bitsize */
++ 3, /* size (0 = byte, 1 = short, 2 = long) */
++ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_FRV_NONE", /* name */
+ FALSE, /* partial_inplace */
+--- a/bfd/elf32-h8300.c
++++ b/bfd/elf32-h8300.c
+@@ -61,7 +61,7 @@ static reloc_howto_type h8_elf_howto_table[] =
+ #define R_H8_NONE_X 0
+ HOWTO (R_H8_NONE, /* type */
+ 0, /* rightshift */
+- 0, /* size (0 = byte, 1 = short, 2 = long) */
++ 3, /* size (0 = byte, 1 = short, 2 = long) */
+ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+--- a/bfd/elf32-i370.c
++++ b/bfd/elf32-i370.c
+@@ -40,11 +40,11 @@ static reloc_howto_type i370_elf_howto_raw[] =
+ /* This reloc does nothing. */
+ HOWTO (R_I370_NONE, /* type */
+ 0, /* rightshift */
+- 2, /* size (0 = byte, 1 = short, 2 = long) */
+- 32, /* bitsize */
++ 3, /* size (0 = byte, 1 = short, 2 = long) */
++ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_I370_NONE", /* name */
+ FALSE, /* partial_inplace */
+--- a/bfd/elf32-i386.c
++++ b/bfd/elf32-i386.c
+@@ -37,7 +37,7 @@
+
+ static reloc_howto_type elf_howto_table[]=
+ {
+- HOWTO(R_386_NONE, 0, 0, 0, FALSE, 0, complain_overflow_bitfield,
++ HOWTO(R_386_NONE, 0, 3, 0, FALSE, 0, complain_overflow_dont,
+ bfd_elf_generic_reloc, "R_386_NONE",
+ TRUE, 0x00000000, 0x00000000, FALSE),
+ HOWTO(R_386_32, 0, 2, 32, FALSE, 0, complain_overflow_bitfield,
+--- a/bfd/elf32-i860.c
++++ b/bfd/elf32-i860.c
+@@ -264,11 +264,11 @@ static reloc_howto_type elf32_i860_howto_table [] =
+ /* This relocation does nothing. */
+ HOWTO (R_860_NONE, /* type */
+ 0, /* rightshift */
+- 2, /* size (0 = byte, 1 = short, 2 = long) */
+- 32, /* bitsize */
++ 3, /* size (0 = byte, 1 = short, 2 = long) */
++ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_860_NONE", /* name */
+ FALSE, /* partial_inplace */
+--- a/bfd/elf32-i960.c
++++ b/bfd/elf32-i960.c
+@@ -83,7 +83,7 @@ elf32_i960_relocate (bfd *abfd ATTRIBUTE_UNUSED,
+
+ static reloc_howto_type elf_howto_table[]=
+ {
+- HOWTO (R_960_NONE, 0, 0, 0, FALSE, 0, complain_overflow_bitfield,
++ HOWTO (R_960_NONE, 0, 3, 0, FALSE, 0, complain_overflow_dont,
+ elf32_i960_relocate, "R_960_NONE", TRUE,
+ 0x00000000, 0x00000000, FALSE),
+ EMPTY_HOWTO (1),
+--- a/bfd/elf32-ip2k.c
++++ b/bfd/elf32-ip2k.c
+@@ -141,7 +141,7 @@ static reloc_howto_type ip2k_elf_howto_table [] =
+ pr) /* pcrel_offset */
+
+ /* This reloc does nothing. */
+- IP2K_HOWTO (R_IP2K_NONE, 0,2,32, FALSE, 0, "R_IP2K_NONE", 0, 0),
++ IP2K_HOWTO (R_IP2K_NONE, 0,3,0, FALSE, 0, "R_IP2K_NONE", 0, 0),
+ /* A 16 bit absolute relocation. */
+ IP2K_HOWTO (R_IP2K_16, 0,1,16, FALSE, 0, "R_IP2K_16", 0, 0xffff),
+ /* A 32 bit absolute relocation. */
+--- a/bfd/elf32-iq2000.c
++++ b/bfd/elf32-iq2000.c
+@@ -34,11 +34,11 @@ static reloc_howto_type iq2000_elf_howto_table [] =
+
+ HOWTO (R_IQ2000_NONE, /* type */
+ 0, /* rightshift */
+- 2, /* size (0 = byte, 1 = short, 2 = long) */
+- 32, /* bitsize */
++ 3, /* size (0 = byte, 1 = short, 2 = long) */
++ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_IQ2000_NONE", /* name */
+ FALSE, /* partial_inplace */
+--- a/bfd/elf32-lm32.c
++++ b/bfd/elf32-lm32.c
+@@ -262,11 +262,11 @@ static reloc_howto_type lm32_elf_howto_table [] =
+ /* This reloc does nothing. */
+ HOWTO (R_LM32_NONE, /* type */
+ 0, /* rightshift */
+- 2, /* size (0 = byte, 1 = short, 2 = long) */
+- 32, /* bitsize */
++ 3, /* size (0 = byte, 1 = short, 2 = long) */
++ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield,/* complain_on_overflow */
++ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_LM32_NONE", /* name */
+ FALSE, /* partial_inplace */
+--- a/bfd/elf32-m32c.c
++++ b/bfd/elf32-m32c.c
+@@ -47,11 +47,11 @@ static reloc_howto_type m32c_elf_howto_table [] =
+ /* This reloc does nothing. */
+ HOWTO (R_M32C_NONE, /* type */
+ 0, /* rightshift */
+- 0, /* size (0 = byte, 1 = short, 2 = long) */
+- 32, /* bitsize */
++ 3, /* size (0 = byte, 1 = short, 2 = long) */
++ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_M32C_NONE", /* name */
+ FALSE, /* partial_inplace */
+--- a/bfd/elf32-m32r.c
++++ b/bfd/elf32-m32r.c
+@@ -474,11 +474,11 @@ static reloc_howto_type m32r_elf_howto_table[] =
+ /* This reloc does nothing. */
+ HOWTO (R_M32R_NONE, /* type */
+ 0, /* rightshift */
+- 2, /* size (0 = byte, 1 = short, 2 = long) */
+- 32, /* bitsize */
++ 3, /* size (0 = byte, 1 = short, 2 = long) */
++ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_M32R_NONE", /* name */
+ FALSE, /* partial_inplace */
+--- a/bfd/elf32-m68hc11.c
++++ b/bfd/elf32-m68hc11.c
+@@ -65,8 +65,8 @@ static reloc_howto_type elf_m68hc11_howto_table[] = {
+ /* This reloc does nothing. */
+ HOWTO (R_M68HC11_NONE, /* type */
+ 0, /* rightshift */
+- 2, /* size (0 = byte, 1 = short, 2 = long) */
+- 32, /* bitsize */
++ 3, /* size (0 = byte, 1 = short, 2 = long) */
++ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont,/* complain_on_overflow */
+--- a/bfd/elf32-m68hc12.c
++++ b/bfd/elf32-m68hc12.c
+@@ -107,8 +107,8 @@ static reloc_howto_type elf_m68hc11_howto_table[] = {
+ /* This reloc does nothing. */
+ HOWTO (R_M68HC11_NONE, /* type */
+ 0, /* rightshift */
+- 2, /* size (0 = byte, 1 = short, 2 = long) */
+- 32, /* bitsize */
++ 3, /* size (0 = byte, 1 = short, 2 = long) */
++ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont,/* complain_on_overflow */
+--- a/bfd/elf32-m68k.c
++++ b/bfd/elf32-m68k.c
+@@ -31,7 +31,7 @@ elf_m68k_discard_copies (struct elf_link_hash_entry *, void *);
+
+ static reloc_howto_type howto_table[] =
+ {
+- HOWTO(R_68K_NONE, 0, 0, 0, FALSE,0, complain_overflow_dont, bfd_elf_generic_reloc, "R_68K_NONE", FALSE, 0, 0x00000000,FALSE),
++ HOWTO(R_68K_NONE, 0, 3, 0, FALSE,0, complain_overflow_dont, bfd_elf_generic_reloc, "R_68K_NONE", FALSE, 0, 0x00000000,FALSE),
+ HOWTO(R_68K_32, 0, 2,32, FALSE,0, complain_overflow_bitfield, bfd_elf_generic_reloc, "R_68K_32", FALSE, 0, 0xffffffff,FALSE),
+ HOWTO(R_68K_16, 0, 1,16, FALSE,0, complain_overflow_bitfield, bfd_elf_generic_reloc, "R_68K_16", FALSE, 0, 0x0000ffff,FALSE),
+ HOWTO(R_68K_8, 0, 0, 8, FALSE,0, complain_overflow_bitfield, bfd_elf_generic_reloc, "R_68K_8", FALSE, 0, 0x000000ff,FALSE),
+--- a/bfd/elf32-mcore.c
++++ b/bfd/elf32-mcore.c
+@@ -110,11 +110,11 @@ static reloc_howto_type mcore_elf_howto_raw[] =
+ /* This reloc does nothing. */
+ HOWTO (R_MCORE_NONE, /* type */
+ 0, /* rightshift */
+- 2, /* size (0 = byte, 1 = short, 2 = long) */
+- 32, /* bitsize */
++ 3, /* size (0 = byte, 1 = short, 2 = long) */
++ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_dont, /* complain_on_overflow */
+ NULL, /* special_function */
+ "R_MCORE_NONE", /* name */
+ FALSE, /* partial_inplace */
+--- a/bfd/elf32-mep.c
++++ b/bfd/elf32-mep.c
+@@ -42,7 +42,7 @@ static bfd_reloc_status_type mep_reloc (bfd *, arelent *, struct bfd_symbol *,
+ static reloc_howto_type mep_elf_howto_table [] =
+ {
+ /* type, size, bits, leftshift, rightshift, pcrel, OD/OS/OU, mask. */
+- MEPREL (R_MEP_NONE, 0, 0, 0, 0, 0, N, 0),
++ MEPREL (R_MEP_NONE, 3, 0, 0, 0, 0, N, 0),
+ MEPREL (R_RELC, 0, 0, 0, 0, 0, N, 0),
+ /* MEPRELOC:HOWTO */
+ /* This section generated from bfd/mep-relocs.pl from include/elf/mep.h. */
+--- a/bfd/elf32-metag.c
++++ b/bfd/elf32-metag.c
+@@ -142,7 +142,7 @@ static reloc_howto_type elf_metag_howto_table[] =
+ /* No relocation. */
+ HOWTO (R_METAG_NONE, /* type */
+ 0, /* rightshift */
+- 0, /* size (0 = byte, 1 = short, 2 = long) */
++ 3, /* size (0 = byte, 1 = short, 2 = long) */
+ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+--- a/bfd/elf32-microblaze.c
++++ b/bfd/elf32-microblaze.c
+@@ -44,11 +44,11 @@ static reloc_howto_type microblaze_elf_howto_raw[] =
+ /* This reloc does nothing. */
+ HOWTO (R_MICROBLAZE_NONE, /* Type. */
+ 0, /* Rightshift. */
+- 2, /* Size (0 = byte, 1 = short, 2 = long). */
+- 32, /* Bitsize. */
++ 3, /* Size (0 = byte, 1 = short, 2 = long). */
++ 0, /* Bitsize. */
+ FALSE, /* PC_relative. */
+ 0, /* Bitpos. */
+- complain_overflow_bitfield, /* Complain on overflow. */
++ complain_overflow_dont, /* Complain on overflow. */
+ NULL, /* Special Function. */
+ "R_MICROBLAZE_NONE", /* Name. */
+ FALSE, /* Partial Inplace. */
+@@ -179,11 +179,11 @@ static reloc_howto_type microblaze_elf_howto_raw[] =
+ /* This reloc does nothing. Used for relaxation. */
+ HOWTO (R_MICROBLAZE_64_NONE, /* Type. */
+ 0, /* Rightshift. */
+- 2, /* Size (0 = byte, 1 = short, 2 = long). */
+- 32, /* Bitsize. */
++ 3, /* Size (0 = byte, 1 = short, 2 = long). */
++ 0, /* Bitsize. */
+ TRUE, /* PC_relative. */
+ 0, /* Bitpos. */
+- complain_overflow_bitfield, /* Complain on overflow. */
++ complain_overflow_dont, /* Complain on overflow. */
+ NULL, /* Special Function. */
+ "R_MICROBLAZE_64_NONE",/* Name. */
+ FALSE, /* Partial Inplace. */
+--- a/bfd/elf32-mips.c
++++ b/bfd/elf32-mips.c
+@@ -107,7 +107,7 @@ static reloc_howto_type elf_mips_howto_table_rel[] =
+ /* No relocation. */
+ HOWTO (R_MIPS_NONE, /* type */
+ 0, /* rightshift */
+- 0, /* size (0 = byte, 1 = short, 2 = long) */
++ 3, /* size (0 = byte, 1 = short, 2 = long) */
+ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+--- a/bfd/elf32-moxie.c
++++ b/bfd/elf32-moxie.c
+@@ -34,11 +34,11 @@ static reloc_howto_type moxie_elf_howto_table [] =
+ /* This reloc does nothing. */
+ HOWTO (R_MOXIE_NONE, /* type */
+ 0, /* rightshift */
+- 2, /* size (0 = byte, 1 = short, 2 = long) */
+- 32, /* bitsize */
++ 3, /* size (0 = byte, 1 = short, 2 = long) */
++ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_MOXIE_NONE", /* name */
+ FALSE, /* partial_inplace */
+#--- a/bfd/elf32-msp430.c
+#+++ b/bfd/elf32-msp430.c
+#@@ -30,11 +30,11 @@ static reloc_howto_type elf_msp430_howto_table[] =
+# {
+# HOWTO (R_MSP430_NONE, /* type */
+# 0, /* rightshift */
+#- 2, /* size (0 = byte, 1 = short, 2 = long) */
+#- 32, /* bitsize */
+#+ 3, /* size (0 = byte, 1 = short, 2 = long) */
+#+ 0, /* bitsize */
+# FALSE, /* pc_relative */
+# 0, /* bitpos */
+#- complain_overflow_bitfield,/* complain_on_overflow */
+#+ complain_overflow_dont,/* complain_on_overflow */
+# bfd_elf_generic_reloc, /* special_function */
+# "R_MSP430_NONE", /* name */
+# FALSE, /* partial_inplace */
+#@@ -197,11 +197,11 @@ static reloc_howto_type elf_msp430x_howto_table[] =
+# {
+# HOWTO (R_MSP430_NONE, /* type */
+# 0, /* rightshift */
+#- 2, /* size (0 = byte, 1 = short, 2 = long) */
+#- 32, /* bitsize */
+#+ 3, /* size (0 = byte, 1 = short, 2 = long) */
+#+ 0, /* bitsize */
+# FALSE, /* pc_relative */
+# 0, /* bitpos */
+#- complain_overflow_bitfield,/* complain_on_overflow */
+#+ complain_overflow_dont,/* complain_on_overflow */
+# bfd_elf_generic_reloc, /* special_function */
+# "R_MSP430_NONE", /* name */
+# FALSE, /* partial_inplace */
+--- a/bfd/elf32-mt.c
++++ b/bfd/elf32-mt.c
+@@ -48,8 +48,8 @@ static reloc_howto_type mt_elf_howto_table [] =
+ /* This reloc does nothing. */
+ HOWTO (R_MT_NONE, /* type */
+ 0, /* rightshift */
+- 2, /* size (0 = byte, 1 = short, 2 = long) */
+- 32, /* bitsize */
++ 3, /* size (0 = byte, 1 = short, 2 = long) */
++ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+#--- a/bfd/elf32-nds32.c
+#+++ b/bfd/elf32-nds32.c
+#@@ -321,11 +321,11 @@ static reloc_howto_type nds32_elf_howto_table[] =
+# /* This reloc does nothing. */
+# HOWTO (R_NDS32_NONE, /* type */
+# 0, /* rightshift */
+#- 2, /* size (0 = byte, 1 = short, 2 = long) */
+#- 32, /* bitsize */
+#+ 3, /* size (0 = byte, 1 = short, 2 = long) */
+#+ 0, /* bitsize */
+# FALSE, /* pc_relative */
+# 0, /* bitpos */
+#- complain_overflow_bitfield, /* complain_on_overflow */
+#+ complain_overflow_dont, /* complain_on_overflow */
+# bfd_elf_generic_reloc, /* special_function */
+# "R_NDS32_NONE", /* name */
+# FALSE, /* partial_inplace */
+#@@ -4186,11 +4186,10 @@ nds32_relocate_contents (reloc_howto_type *howto, bfd *input_bfd,
+# switch (size)
+# {
+# default:
+#- case 0:
+#- case 1:
+#- case 8:
+# abort ();
+# break;
+#+ case 0:
+#+ return bfd_reloc_ok;
+# case 2:
+# x = bfd_getb16 (location);
+# break;
+--- a/bfd/elf32-nios2.c
++++ b/bfd/elf32-nios2.c
+@@ -80,7 +80,7 @@ static reloc_howto_type elf_nios2_howto_table_rel[] = {
+ /* No relocation. */
+ HOWTO (R_NIOS2_NONE, /* type */
+ 0, /* rightshift */
+- 0, /* size (0 = byte, 1 = short, 2 = long) */
++ 3, /* size (0 = byte, 1 = short, 2 = long) */
+ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+#--- a/bfd/elf32-or1k.c
+#+++ b/bfd/elf32-or1k.c
+#@@ -60,8 +60,8 @@ static reloc_howto_type or1k_elf_howto_table[] =
+# /* This reloc does nothing. */
+# HOWTO (R_OR1K_NONE, /* type */
+# 0, /* rightshift */
+#- 2, /* size (0 = byte, 1 = short, 2 = long) */
+#- 32, /* bitsize */
+#+ 3, /* size (0 = byte, 1 = short, 2 = long) */
+#+ 0, /* bitsize */
+# FALSE, /* pc_relative */
+# 0, /* bitpos */
+# complain_overflow_dont, /* complain_on_overflow */
+--- a/bfd/elf32-pj.c
++++ b/bfd/elf32-pj.c
+@@ -113,7 +113,7 @@ static reloc_howto_type pj_elf_howto_table[] =
+ /* No relocation. */
+ HOWTO (R_PJ_NONE, /* type */
+ 0, /* rightshift */
+- 0, /* size (0 = byte, 1 = short, 2 = long) */
++ 3, /* size (0 = byte, 1 = short, 2 = long) */
+ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+--- a/bfd/elf32-ppc.c
++++ b/bfd/elf32-ppc.c
+@@ -187,8 +187,8 @@ static reloc_howto_type ppc_elf_howto_raw[] = {
+ /* This reloc does nothing. */
+ HOWTO (R_PPC_NONE, /* type */
+ 0, /* rightshift */
+- 2, /* size (0 = byte, 1 = short, 2 = long) */
+- 32, /* bitsize */
++ 3, /* size (0 = byte, 1 = short, 2 = long) */
++ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+@@ -2066,9 +2066,6 @@ ppc_elf_addr16_ha_reloc (bfd *abfd ATTRIBUTE_UNUSED,
+ return bfd_reloc_ok;
+ }
+
+- if (reloc_entry->address > bfd_get_section_limit (abfd, input_section))
+- return bfd_reloc_outofrange;
+-
+ if (bfd_is_com_section (symbol->section))
+ relocation = 0;
+ else
+--- a/bfd/elf32-rl78.c
++++ b/bfd/elf32-rl78.c
+@@ -37,7 +37,7 @@
+
+ static reloc_howto_type rl78_elf_howto_table [] =
+ {
+- RL78REL (NONE, 0, 0, 0, dont, FALSE),
++ RL78REL (NONE, 3, 0, 0, dont, FALSE),
+ RL78REL (DIR32, 2, 32, 0, signed, FALSE),
+ RL78REL (DIR24S, 2, 24, 0, signed, FALSE),
+ RL78REL (DIR16, 1, 16, 0, dont, FALSE),
+--- a/bfd/elf32-rx.c
++++ b/bfd/elf32-rx.c
+@@ -49,7 +49,7 @@ void rx_dump_symtab (bfd *, void *, void *);
+
+ static reloc_howto_type rx_elf_howto_table [] =
+ {
+- RXREL (NONE, 0, 0, 0, dont, FALSE),
++ RXREL (NONE, 3, 0, 0, dont, FALSE),
+ RXREL (DIR32, 2, 32, 0, signed, FALSE),
+ RXREL (DIR24S, 2, 24, 0, signed, FALSE),
+ RXREL (DIR16, 1, 16, 0, dont, FALSE),
+--- a/bfd/elf32-s390.c
++++ b/bfd/elf32-s390.c
+@@ -39,7 +39,7 @@ static reloc_howto_type elf_howto_table[] =
+ {
+ HOWTO (R_390_NONE, /* type */
+ 0, /* rightshift */
+- 0, /* size (0 = byte, 1 = 2 byte, 2 = 4 byte) */
++ 3, /* size (0 = byte, 1 = 2 byte, 2 = 4 byte) */
+ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+--- a/bfd/elf32-score.c
++++ b/bfd/elf32-score.c
+@@ -645,7 +645,7 @@ static reloc_howto_type elf32_score_howto_table[] =
+ /* No relocation. */
+ HOWTO (R_SCORE_NONE, /* type */
+ 0, /* rightshift */
+- 0, /* size (0 = byte, 1 = short, 2 = long) */
++ 3, /* size (0 = byte, 1 = short, 2 = long) */
+ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+--- a/bfd/elf32-score7.c
++++ b/bfd/elf32-score7.c
+@@ -546,7 +546,7 @@ static reloc_howto_type elf32_score_howto_table[] =
+ /* No relocation. */
+ HOWTO (R_SCORE_NONE, /* type */
+ 0, /* rightshift */
+- 0, /* size (0 = byte, 1 = short, 2 = long) */
++ 3, /* size (0 = byte, 1 = short, 2 = long) */
+ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+--- a/bfd/elf32-sh-relocs.h
++++ b/bfd/elf32-sh-relocs.h
+@@ -20,7 +20,7 @@
+ /* No relocation. */
+ HOWTO (R_SH_NONE, /* type */
+ 0, /* rightshift */
+- 0, /* size (0 = byte, 1 = short, 2 = long) */
++ 3, /* size (0 = byte, 1 = short, 2 = long) */
+ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+--- a/bfd/elf32-sh.c
++++ b/bfd/elf32-sh.c
+@@ -256,10 +256,8 @@ sh_elf_reloc (bfd *abfd, arelent *reloc_entry, asymbol *symbol_in,
+ return bfd_reloc_undefined;
+
+ /* PR 17512: file: 9891ca98. */
+- if (addr > bfd_get_section_limit (abfd, input_section)
+- - bfd_get_reloc_size (reloc_entry->howto)
+- || bfd_get_reloc_size (reloc_entry->howto)
+- > bfd_get_section_limit (abfd, input_section))
++ if (addr * bfd_octets_per_byte (abfd) + bfd_get_reloc_size (reloc_entry->howto)
++ > bfd_get_section_limit_octets (abfd, input_section))
+ return bfd_reloc_outofrange;
+
+ if (bfd_is_com_section (symbol_in->section))
+--- a/bfd/elf32-spu.c
++++ b/bfd/elf32-spu.c
+@@ -37,7 +37,7 @@ static bfd_reloc_status_type spu_elf_rel9 (bfd *, arelent *, asymbol *,
+ array, so it must be declared in the order of that type. */
+
+ static reloc_howto_type elf_howto_table[] = {
+- HOWTO (R_SPU_NONE, 0, 0, 0, FALSE, 0, complain_overflow_dont,
++ HOWTO (R_SPU_NONE, 0, 3, 0, FALSE, 0, complain_overflow_dont,
+ bfd_elf_generic_reloc, "SPU_NONE",
+ FALSE, 0, 0x00000000, FALSE),
+ HOWTO (R_SPU_ADDR10, 4, 2, 10, FALSE, 14, complain_overflow_bitfield,
+--- a/bfd/elf32-tic6x.c
++++ b/bfd/elf32-tic6x.c
+@@ -152,7 +152,7 @@ static reloc_howto_type elf32_tic6x_howto_table[] =
+ {
+ HOWTO (R_C6000_NONE, /* type */
+ 0, /* rightshift */
+- 0, /* size (0 = byte, 1 = short, 2 = long) */
++ 3, /* size (0 = byte, 1 = short, 2 = long) */
+ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+@@ -820,7 +820,7 @@ static reloc_howto_type elf32_tic6x_howto_table_rel[] =
+ {
+ HOWTO (R_C6000_NONE, /* type */
+ 0, /* rightshift */
+- 0, /* size (0 = byte, 1 = short, 2 = long) */
++ 3, /* size (0 = byte, 1 = short, 2 = long) */
+ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+--- a/bfd/elf32-tilepro.c
++++ b/bfd/elf32-tilepro.c
+@@ -34,11 +34,11 @@ static reloc_howto_type tilepro_elf_howto_table [] =
+ /* This reloc does nothing. */
+ HOWTO (R_TILEPRO_NONE, /* type */
+ 0, /* rightshift */
+- 2, /* size (0 = byte, 1 = short, 2 = long) */
+- 32, /* bitsize */
++ 3, /* size (0 = byte, 1 = short, 2 = long) */
++ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_TILEPRO_NONE", /* name */
+ FALSE, /* partial_inplace */
+--- a/bfd/elf32-v850.c
++++ b/bfd/elf32-v850.c
+@@ -895,11 +895,11 @@ static reloc_howto_type v850_elf_howto_table[] =
+ /* This reloc does nothing. */
+ HOWTO (R_V850_NONE, /* Type. */
+ 0, /* Rightshift. */
+- 2, /* Size (0 = byte, 1 = short, 2 = long). */
+- 32, /* Bitsize. */
++ 3, /* Size (0 = byte, 1 = short, 2 = long). */
++ 0, /* Bitsize. */
+ FALSE, /* PC_relative. */
+ 0, /* Bitpos. */
+- complain_overflow_bitfield, /* Complain_on_overflow. */
++ complain_overflow_dont, /* Complain_on_overflow. */
+ bfd_elf_generic_reloc, /* Special_function. */
+ "R_V850_NONE", /* Name. */
+ FALSE, /* Partial_inplace. */
+--- a/bfd/elf32-vax.c
++++ b/bfd/elf32-vax.c
+@@ -56,7 +56,7 @@ static bfd_boolean elf32_vax_print_private_bfd_data (bfd *, void *);
+ static reloc_howto_type howto_table[] = {
+ HOWTO (R_VAX_NONE, /* type */
+ 0, /* rightshift */
+- 0, /* size (0 = byte, 1 = short, 2 = long) */
++ 3, /* size (0 = byte, 1 = short, 2 = long) */
+ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+#--- a/bfd/elf32-visium.c
+#+++ b/bfd/elf32-visium.c
+#@@ -33,11 +33,11 @@ static reloc_howto_type visium_elf_howto_table[] = {
+# /* This reloc does nothing. */
+# HOWTO (R_VISIUM_NONE, /* type */
+# 0, /* rightshift */
+#- 2, /* size (0 = byte, 1 = short, 2 = long) */
+#- 32, /* bitsize */
+#+ 3, /* size (0 = byte, 1 = short, 2 = long) */
+#+ 0, /* bitsize */
+# FALSE, /* pc_relative */
+# 0, /* bitpos */
+#- complain_overflow_bitfield, /* complain_on_overflow */
+#+ complain_overflow_dont, /* complain_on_overflow */
+# bfd_elf_generic_reloc, /* special_function */
+# "R_VISIUM_NONE", /* name */
+# FALSE, /* partial_inplace */
+--- a/bfd/elf32-xc16x.c
++++ b/bfd/elf32-xc16x.c
+@@ -32,11 +32,11 @@ static reloc_howto_type xc16x_elf_howto_table [] =
+ /* This reloc does nothing. */
+ HOWTO (R_XC16X_NONE, /* type */
+ 0, /* rightshift */
+- 1, /* size (0 = byte, 1 = short, 2 = long) */
+- 16, /* bitsize */
++ 3, /* size (0 = byte, 1 = short, 2 = long) */
++ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_XC16X_NONE", /* name */
+ FALSE, /* partial_inplace */
+--- a/bfd/elf32-xgate.c
++++ b/bfd/elf32-xgate.c
+@@ -52,8 +52,8 @@ static reloc_howto_type elf_xgate_howto_table[] =
+ /* This reloc does nothing. */
+ HOWTO (R_XGATE_NONE, /* type */
+ 0, /* rightshift */
+- 2, /* size (0 = byte, 1 = short, 2 = long) */
+- 32, /* bitsize */
++ 3, /* size (0 = byte, 1 = short, 2 = long) */
++ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont,/* complain_on_overflow */
+--- a/bfd/elf32-xstormy16.c
++++ b/bfd/elf32-xstormy16.c
+@@ -73,11 +73,11 @@ static reloc_howto_type xstormy16_elf_howto_table [] =
+ /* This reloc does nothing. */
+ HOWTO (R_XSTORMY16_NONE, /* type */
+ 0, /* rightshift */
+- 2, /* size (0 = byte, 1 = short, 2 = long) */
+- 32, /* bitsize */
++ 3, /* size (0 = byte, 1 = short, 2 = long) */
++ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_XSTORMY16_NONE", /* name */
+ FALSE, /* partial_inplace */
+--- a/bfd/elf32-xtensa.c
++++ b/bfd/elf32-xtensa.c
+@@ -161,7 +161,7 @@ int elf32xtensa_no_literal_movement = 1;
+
+ static reloc_howto_type elf_howto_table[] =
+ {
+- HOWTO (R_XTENSA_NONE, 0, 0, 0, FALSE, 0, complain_overflow_dont,
++ HOWTO (R_XTENSA_NONE, 0, 3, 0, FALSE, 0, complain_overflow_dont,
+ bfd_elf_xtensa_reloc, "R_XTENSA_NONE",
+ FALSE, 0, 0, FALSE),
+ HOWTO (R_XTENSA_32, 0, 2, 32, FALSE, 0, complain_overflow_bitfield,
+--- a/bfd/elf64-alpha.c
++++ b/bfd/elf64-alpha.c
+@@ -486,8 +486,8 @@ static reloc_howto_type elf64_alpha_howto_table[] =
+ {
+ HOWTO (R_ALPHA_NONE, /* type */
+ 0, /* rightshift */
+- 0, /* size (0 = byte, 1 = short, 2 = long) */
+- 8, /* bitsize */
++ 3, /* size (0 = byte, 1 = short, 2 = long) */
++ 0, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+--- a/bfd/elf64-mips.c
++++ b/bfd/elf64-mips.c
+@@ -145,7 +145,7 @@ static reloc_howto_type mips_elf64_howto_table_rel[] =
+ /* No relocation. */
+ HOWTO (R_MIPS_NONE, /* type */
+ 0, /* rightshift */
+- 0, /* size (0 = byte, 1 = short, 2 = long) */
++ 3, /* size (0 = byte, 1 = short, 2 = long) */
+ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+@@ -908,7 +908,7 @@ static reloc_howto_type mips_elf64_howto_table_rela[] =
+ /* No relocation. */
+ HOWTO (R_MIPS_NONE, /* type */
+ 0, /* rightshift */
+- 0, /* size (0 = byte, 1 = short, 2 = long) */
++ 3, /* size (0 = byte, 1 = short, 2 = long) */
+ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+--- a/bfd/elf64-mmix.c
++++ b/bfd/elf64-mmix.c
+@@ -192,11 +192,11 @@ static reloc_howto_type elf_mmix_howto_table[] =
+ /* This reloc does nothing. */
+ HOWTO (R_MMIX_NONE, /* type */
+ 0, /* rightshift */
+- 2, /* size (0 = byte, 1 = short, 2 = long) */
+- 32, /* bitsize */
++ 3, /* size (0 = byte, 1 = short, 2 = long) */
++ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_MMIX_NONE", /* name */
+ FALSE, /* partial_inplace */
+--- a/bfd/elf64-ppc.c
++++ b/bfd/elf64-ppc.c
+@@ -258,8 +258,8 @@ static reloc_howto_type ppc64_elf_howto_raw[] = {
+ /* This reloc does nothing. */
+ HOWTO (R_PPC64_NONE, /* type */
+ 0, /* rightshift */
+- 2, /* size (0 = byte, 1 = short, 2 = long) */
+- 32, /* bitsize */
++ 3, /* size (0 = byte, 1 = short, 2 = long) */
++ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+--- a/bfd/elf64-s390.c
++++ b/bfd/elf64-s390.c
+@@ -42,7 +42,7 @@ static reloc_howto_type elf_howto_table[] =
+ {
+ HOWTO (R_390_NONE, /* type */
+ 0, /* rightshift */
+- 0, /* size (0 = byte, 1 = 2 byte, 2 = 4 byte) */
++ 3, /* size (0 = byte, 1 = 2 byte, 2 = 4 byte) */
+ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+--- a/bfd/elf64-sh64.c
++++ b/bfd/elf64-sh64.c
+@@ -105,7 +105,7 @@ static reloc_howto_type sh_elf64_howto_table[] = {
+ /* No relocation. */
+ HOWTO (R_SH_NONE, /* type */
+ 0, /* rightshift */
+- 0, /* size (0 = byte, 1 = short, 2 = long) */
++ 3, /* size (0 = byte, 1 = short, 2 = long) */
+ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+--- a/bfd/elf64-x86-64.c
++++ b/bfd/elf64-x86-64.c
+@@ -54,7 +54,7 @@
+ special_function, name, partial_inplace, src_mask, dst_mask, pcrel_offset. */
+ static reloc_howto_type x86_64_elf_howto_table[] =
+ {
+- HOWTO(R_X86_64_NONE, 0, 0, 0, FALSE, 0, complain_overflow_dont,
++ HOWTO(R_X86_64_NONE, 0, 3, 0, FALSE, 0, complain_overflow_dont,
+ bfd_elf_generic_reloc, "R_X86_64_NONE", FALSE, 0x00000000, 0x00000000,
+ FALSE),
+ HOWTO(R_X86_64_64, 0, 4, 64, FALSE, 0, complain_overflow_bitfield,
+--- a/bfd/elflink.c
++++ b/bfd/elflink.c
+@@ -10329,7 +10329,7 @@ elf_reloc_link_order (bfd *output_bfd,
+
+ size = (bfd_size_type) bfd_get_reloc_size (howto);
+ buf = (bfd_byte *) bfd_zmalloc (size);
+- if (buf == NULL)
++ if (buf == NULL && size != 0)
+ return FALSE;
+ rstat = _bfd_relocate_contents (howto, output_bfd, addend, buf);
+ switch (rstat)
+--- a/bfd/elfn32-mips.c
++++ b/bfd/elfn32-mips.c
+@@ -108,7 +108,7 @@ static reloc_howto_type elf_mips_howto_table_rel[] =
+ /* No relocation. */
+ HOWTO (R_MIPS_NONE, /* type */
+ 0, /* rightshift */
+- 0, /* size (0 = byte, 1 = short, 2 = long) */
++ 3, /* size (0 = byte, 1 = short, 2 = long) */
+ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+#--- a/bfd/elfnn-aarch64.c
+#+++ b/bfd/elfnn-aarch64.c
+#@@ -296,7 +296,7 @@ static reloc_howto_type elfNN_aarch64_howto_table[] =
+# #if ARCH_SIZE == 64
+# HOWTO (R_AARCH64_NULL, /* type */
+# 0, /* rightshift */
+#- 0, /* size (0 = byte, 1 = short, 2 = long) */
+#+ 3, /* size (0 = byte, 1 = short, 2 = long) */
+# 0, /* bitsize */
+# FALSE, /* pc_relative */
+# 0, /* bitpos */
+#@@ -310,7 +310,7 @@ static reloc_howto_type elfNN_aarch64_howto_table[] =
+# #else
+# HOWTO (R_AARCH64_NONE, /* type */
+# 0, /* rightshift */
+#- 0, /* size (0 = byte, 1 = short, 2 = long) */
+#+ 3, /* size (0 = byte, 1 = short, 2 = long) */
+# 0, /* bitsize */
+# FALSE, /* pc_relative */
+# 0, /* bitpos */
+#@@ -1377,7 +1377,7 @@ static reloc_howto_type elfNN_aarch64_howto_table[] =
+# static reloc_howto_type elfNN_aarch64_howto_none =
+# HOWTO (R_AARCH64_NONE, /* type */
+# 0, /* rightshift */
+#- 0, /* size (0 = byte, 1 = short, 2 = long) */
+#+ 3, /* size (0 = byte, 1 = short, 2 = long) */
+# 0, /* bitsize */
+# FALSE, /* pc_relative */
+# 0, /* bitpos */
+#--- a/bfd/elfxx-aarch64.c
+#+++ b/bfd/elfxx-aarch64.c
+#@@ -187,6 +187,8 @@ _bfd_aarch64_elf_put_addend (bfd *abfd,
+# size = bfd_get_reloc_size (howto);
+# switch (size)
+# {
+#+ case 0:
+#+ return status;
+# case 2:
+# contents = bfd_get_16 (abfd, address);
+# break;
+--- a/bfd/elfxx-ia64.c
++++ b/bfd/elfxx-ia64.c
+@@ -91,7 +91,7 @@ ia64_elf_reloc (bfd *abfd ATTRIBUTE_UNUSED, arelent *reloc,
+ TYPE field. */
+ static reloc_howto_type ia64_howto_table[] =
+ {
+- IA64_HOWTO (R_IA64_NONE, "NONE", 0, FALSE, TRUE),
++ IA64_HOWTO (R_IA64_NONE, "NONE", 3, FALSE, TRUE),
+
+ IA64_HOWTO (R_IA64_IMM14, "IMM14", 0, FALSE, TRUE),
+ IA64_HOWTO (R_IA64_IMM22, "IMM22", 0, FALSE, TRUE),
+--- a/bfd/elfxx-mips.c
++++ b/bfd/elfxx-mips.c
+@@ -6194,11 +6194,13 @@ mips_elf_obtain_contents (reloc_howto_type *howto,
+ const Elf_Internal_Rela *relocation,
+ bfd *input_bfd, bfd_byte *contents)
+ {
+- bfd_vma x;
++ bfd_vma x = 0;
+ bfd_byte *location = contents + relocation->r_offset;
++ unsigned int size = bfd_get_reloc_size (howto);
+
+ /* Obtain the bytes. */
+- x = bfd_get ((8 * bfd_get_reloc_size (howto)), input_bfd, location);
++ if (size != 0)
++ x = bfd_get (8 * size, input_bfd, location);
+
+ return x;
+ }
+@@ -6223,6 +6225,7 @@ mips_elf_perform_relocation (struct bfd_link_info *info,
+ bfd_vma x;
+ bfd_byte *location;
+ int r_type = ELF_R_TYPE (input_bfd, relocation->r_info);
++ unsigned int size;
+
+ /* Figure out where the relocation is occurring. */
+ location = contents + relocation->r_offset;
+@@ -6316,7 +6319,9 @@ mips_elf_perform_relocation (struct bfd_link_info *info,
+ }
+
+ /* Put the value into the output. */
+- bfd_put (8 * bfd_get_reloc_size (howto), input_bfd, x, location);
++ size = bfd_get_reloc_size (howto);
++ if (size != 0)
++ bfd_put (8 * size, input_bfd, x, location);
+
+ _bfd_mips_elf_reloc_shuffle (input_bfd, r_type, !info->relocatable,
+ location);
+--- a/bfd/elfxx-sparc.c
++++ b/bfd/elfxx-sparc.c
+@@ -209,7 +209,7 @@ sparc_elf_lox10_reloc (bfd *abfd, arelent *reloc_entry, asymbol *symbol,
+
+ static reloc_howto_type _bfd_sparc_elf_howto_table[] =
+ {
+- HOWTO(R_SPARC_NONE, 0,0, 0,FALSE,0,complain_overflow_dont, bfd_elf_generic_reloc, "R_SPARC_NONE", FALSE,0,0x00000000,TRUE),
++ HOWTO(R_SPARC_NONE, 0,3, 0,FALSE,0,complain_overflow_dont, bfd_elf_generic_reloc, "R_SPARC_NONE", FALSE,0,0x00000000,TRUE),
+ HOWTO(R_SPARC_8, 0,0, 8,FALSE,0,complain_overflow_bitfield,bfd_elf_generic_reloc, "R_SPARC_8", FALSE,0,0x000000ff,TRUE),
+ HOWTO(R_SPARC_16, 0,1,16,FALSE,0,complain_overflow_bitfield,bfd_elf_generic_reloc, "R_SPARC_16", FALSE,0,0x0000ffff,TRUE),
+ HOWTO(R_SPARC_32, 0,2,32,FALSE,0,complain_overflow_bitfield,bfd_elf_generic_reloc, "R_SPARC_32", FALSE,0,0xffffffff,TRUE),
+--- a/bfd/elfxx-tilegx.c
++++ b/bfd/elfxx-tilegx.c
+@@ -72,11 +72,11 @@ static reloc_howto_type tilegx_elf_howto_table [] =
+ /* This reloc does nothing. */
+ HOWTO (R_TILEGX_NONE, /* type */
+ 0, /* rightshift */
+- 2, /* size (0 = byte, 1 = short, 2 = long) */
+- 32, /* bitsize */
++ 3, /* size (0 = byte, 1 = short, 2 = long) */
++ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_bitfield, /* complain_on_overflow */
++ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_TILEGX_NONE", /* name */
+ FALSE, /* partial_inplace */
+--- a/bfd/linker.c
++++ b/bfd/linker.c
+@@ -2434,7 +2434,7 @@ _bfd_generic_reloc_link_order (bfd *abfd,
+
+ size = bfd_get_reloc_size (r->howto);
+ buf = (bfd_byte *) bfd_zmalloc (size);
+- if (buf == NULL)
++ if (buf == NULL && size != 0)
+ return FALSE;
+ rstat = _bfd_relocate_contents (r->howto, abfd,
+ (bfd_vma) link_order->u.reloc.p->addend,
+--- a/bfd/nlm32-sparc.c
++++ b/bfd/nlm32-sparc.c
+@@ -49,7 +49,7 @@ enum reloc_type
+
+ static reloc_howto_type nlm32_sparc_howto_table[] =
+ {
+- HOWTO (R_SPARC_NONE, 0,0, 0,FALSE,0,complain_overflow_dont, 0,"R_SPARC_NONE", FALSE,0,0x00000000,TRUE),
++ HOWTO (R_SPARC_NONE, 0,3, 0,FALSE,0,complain_overflow_dont, 0,"R_SPARC_NONE", FALSE,0,0x00000000,TRUE),
+ HOWTO (R_SPARC_8, 0,0, 8,FALSE,0,complain_overflow_bitfield,0,"R_SPARC_8", FALSE,0,0x000000ff,TRUE),
+ HOWTO (R_SPARC_16, 0,1,16,FALSE,0,complain_overflow_bitfield,0,"R_SPARC_16", FALSE,0,0x0000ffff,TRUE),
+ HOWTO (R_SPARC_32, 0,2,32,FALSE,0,complain_overflow_bitfield,0,"R_SPARC_32", FALSE,0,0xffffffff,TRUE),
+--- a/bfd/pdp11.c
++++ b/bfd/pdp11.c
+@@ -3152,7 +3152,7 @@ aout_link_reloc_link_order (struct aout_final_link_info *flaginfo,
+
+ size = bfd_get_reloc_size (howto);
+ buf = bfd_zmalloc (size);
+- if (buf == NULL)
++ if (buf == NULL && size != 0)
+ return FALSE;
+ r = MY_relocate_contents (howto, flaginfo->output_bfd,
+ pr->addend, buf);
+--- a/bfd/reloc.c
++++ b/bfd/reloc.c
+@@ -579,7 +579,7 @@ bfd_perform_relocation (bfd *abfd,
+ {
+ bfd_vma relocation;
+ bfd_reloc_status_type flag = bfd_reloc_ok;
+- bfd_size_type octets = reloc_entry->address * bfd_octets_per_byte (abfd);
++ bfd_size_type octets;
+ bfd_vma output_base = 0;
+ reloc_howto_type *howto = reloc_entry->howto;
+ asection *reloc_target_output_section;
+@@ -618,15 +618,12 @@ bfd_perform_relocation (bfd *abfd,
+ return cont;
+ }
+
+- /* Is the address of the relocation really within the section? */
+- if (reloc_entry->address > bfd_get_section_limit (abfd, input_section)
+- /* PR 17512: file: c146ab8b.
+- PR 17512: file: 46dff27f.
+- Include the size of the reloc in the test for out of range addresses. */
+- - bfd_get_reloc_size (howto)
+- /* PR 17512: file: 38e53ebf
+- Add make sure that there is enough room for the relocation to be applied. */
+- || bfd_get_reloc_size (howto) > bfd_get_section_limit (abfd, input_section))
++ /* Is the address of the relocation really within the section?
++ Include the size of the reloc in the test for out of range addresses.
++ PR 17512: file: c146ab8b, 46dff27f, 38e53ebf. */
++ octets = reloc_entry->address * bfd_octets_per_byte (abfd);
++ if (octets + bfd_get_reloc_size (howto)
++ > bfd_get_section_limit_octets (abfd, input_section))
+ return bfd_reloc_outofrange;
+
+ /* Work out which section the relocation is targeted at and the
+@@ -976,7 +973,7 @@ bfd_install_relocation (bfd *abfd,
+ {
+ bfd_vma relocation;
+ bfd_reloc_status_type flag = bfd_reloc_ok;
+- bfd_size_type octets = reloc_entry->address * bfd_octets_per_byte (abfd);
++ bfd_size_type octets;
+ bfd_vma output_base = 0;
+ reloc_howto_type *howto = reloc_entry->howto;
+ asection *reloc_target_output_section;
+@@ -1009,7 +1006,9 @@ bfd_install_relocation (bfd *abfd,
+ }
+
+ /* Is the address of the relocation really within the section? */
+- if (reloc_entry->address > bfd_get_section_limit (abfd, input_section))
++ octets = reloc_entry->address * bfd_octets_per_byte (abfd);
++ if (octets + bfd_get_reloc_size (howto)
++ > bfd_get_section_limit_octets (abfd, input_section))
+ return bfd_reloc_outofrange;
+
+ /* Work out which section the relocation is targeted at and the
+@@ -1344,9 +1343,11 @@ _bfd_final_link_relocate (reloc_howto_type *howto,
+ bfd_vma addend)
+ {
+ bfd_vma relocation;
++ bfd_size_type octets = address * bfd_octets_per_byte (input_bfd);
+
+ /* Sanity check the address. */
+- if (address > bfd_get_section_limit (input_bfd, input_section))
++ if (octets + bfd_get_reloc_size (howto)
++ > bfd_get_section_limit_octets (input_bfd, input_section))
+ return bfd_reloc_outofrange;
+
+ /* This function assumes that we are dealing with a basic relocation
+@@ -1401,8 +1402,9 @@ _bfd_relocate_contents (reloc_howto_type *howto,
+ switch (size)
+ {
+ default:
+- case 0:
+ abort ();
++ case 0:
++ return bfd_reloc_ok;
+ case 1:
+ x = bfd_get_8 (input_bfd, location);
+ break;
+@@ -1569,8 +1571,9 @@ _bfd_clear_contents (reloc_howto_type *howto,
+ switch (size)
+ {
+ default:
+- case 0:
+ abort ();
++ case 0:
++ return;
+ case 1:
+ x = bfd_get_8 (input_bfd, location);
+ break;
+--- a/bfd/xcofflink.c
++++ b/bfd/xcofflink.c
+@@ -5738,7 +5738,7 @@ xcoff_reloc_link_order (bfd *output_bfd,
+
+ size = bfd_get_reloc_size (howto);
+ buf = bfd_zmalloc (size);
+- if (buf == NULL)
++ if (buf == NULL && size != 0)
+ return FALSE;
+
+ rstat = _bfd_relocate_contents (howto, output_bfd, addend, buf);
diff --git a/SOURCES/gdb-rhbz1320945-power9-13of38.patch b/SOURCES/gdb-rhbz1320945-power9-13of38.patch
new file mode 100644
index 0000000..2f4d7d7
--- /dev/null
+++ b/SOURCES/gdb-rhbz1320945-power9-13of38.patch
@@ -0,0 +1,32 @@
+commit c4e676f196560500d41ff8652d6be0c735758001
+Author: Anton Blanchard <anton@samba.org>
+Date: Wed Mar 25 13:43:18 2015 +1100
+
+ powerpc: Add slbfee. instruction
+
+ opcodes/ChangeLog:
+ 2015-03-25 Anton Blanchard <anton@samba.org>
+
+ * ppc-opc.c (powerpc_opcodes): Add slbfee.
+
+### a/opcodes/ChangeLog
+### b/opcodes/ChangeLog
+## -1,3 +1,7 @@
++2015-03-25 Anton Blanchard <anton@samba.org>
++
++ * ppc-opc.c (powerpc_opcodes): Add slbfee.
++
+ 2015-03-24 Terry Guo <terry.guo@arm.com>
+
+ * arm-dis.c (opcode32): Updated to use new arm feature struct.
+--- a/opcodes/ppc-opc.c
++++ b/opcodes/ppc-opc.c
+@@ -5795,6 +5795,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, PPCNONE, {RT, RA}},
+ {"tlbwe", X(31,978), X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RSO, RAOPT, SHO}},
+
++{"slbfee.", XRC(31,979,1), XRA_MASK, POWER6, PPCNONE, {RT, RB}},
++
+ {"stbcix", X(31,981), X_MASK, POWER6, PPCNONE, {RS, RA0, RB}},
+
+ {"icbi", X(31,982), XRT_MASK, PPC|PPCVLE, PPCNONE, {RA0, RB}},
diff --git a/SOURCES/gdb-rhbz1320945-power9-14of38.patch b/SOURCES/gdb-rhbz1320945-power9-14of38.patch
new file mode 100644
index 0000000..eadd7ed
--- /dev/null
+++ b/SOURCES/gdb-rhbz1320945-power9-14of38.patch
@@ -0,0 +1,140 @@
+commit 4fff86c517abb5ba454befe0ec0f284f720dde00
+Author: Peter Bergner <bergner@vnet.ibm.com>
+Date: Mon Apr 27 11:06:54 2015 -0500
+
+ opcodes/
+
+ * ppc-opc.c (DCBT_EO): New define.
+ (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
+ <lharx>: Likewise.
+ <stbcx.>: Likewise.
+ <sthcx.>: Likewise.
+ <waitrsv>: Do not enable for POWER7 and later.
+ <waitimpl>: Likewise.
+ <dcbt>: Default to the two operand form of the instruction for all
+ "old" cpus. For "new" cpus, use the operand ordering that matches
+ whether the cpu is server or embedded.
+ <dcbtst>: Likewise.
+
+ gas/testsuite/
+
+ * gas/ppc/a2.s: Fixup test case due to dcbt/dcbtst embedded operand
+ ordering change.
+ * gas/ppc/a2.d: Likewise.
+ * gas/ppc/476.d: Likewise.
+ * gas/ppc/booke.s: Remove invalid 3 operand dcbt tests.
+ * gas/ppc/booke.d: Likewise.
+ * gas/ppc/power7.s: Remove lbarx, lharx, stbcx., sthcx., waitrsv
+ and waitimpl tests.
+ * gas/ppc/power7.d: Likewise.
+
+### a/opcodes/ChangeLog
+### b/opcodes/ChangeLog
+## -1,3 +1,17 @@
++2015-04-27 Peter Bergner <bergner@vnet.ibm.com>
++
++ * ppc-opc.c (DCBT_EO): New define.
++ (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
++ <lharx>: Likewise.
++ <stbcx.>: Likewise.
++ <sthcx.>: Likewise.
++ <waitrsv>: Do not enable for POWER7 and later.
++ <waitimpl>: Likewise.
++ <dcbt>: Default to the two operand form of the instruction for all
++ "old" cpus. For "new" cpus, use the operand ordering that matches
++ whether the cpu is server or embedded.
++ <dcbtst>: Likewise.
++
+ 2015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
+
+ * s390-opc.c: New instruction type VV0UU2.
+--- a/opcodes/ppc-opc.c
++++ b/opcodes/ppc-opc.c
+@@ -2756,6 +2756,12 @@ extract_vleil (unsigned long insn,
+ #define E6500 PPC_OPCODE_E6500
+ #define PPCVLE PPC_OPCODE_VLE
+ #define PPCHTM PPC_OPCODE_HTM
++/* The list of embedded processors that use the embedded operand ordering
++ for the 3 operand dcbt and dcbtst instructions. */
++#define DCBT_EO (PPC_OPCODE_E500 | PPC_OPCODE_E500MC | PPC_OPCODE_476 \
++ | PPC_OPCODE_A2 | PPC_OPCODE_VLE)
++
++
+
+ /* The opcode table.
+
+@@ -4463,7 +4469,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"mfvrd", X(31,51)|1, XX1RB_MASK|1, PPCVSX2, PPCNONE, {RA, VS}},
+ {"eratilx", X(31,51), X_MASK, PPCA2, PPCNONE, {ERAT_T, RA, RB}},
+
+-{"lbarx", X(31,52), XEH_MASK, POWER7|PPCVLE, PPCNONE, {RT, RA0, RB, EH}},
++{"lbarx", X(31,52), XEH_MASK, POWER8|PPCVLE, PPCNONE, {RT, RA0, RB, EH}},
+
+ {"ldux", X(31,53), X_MASK, PPC64|PPCVLE, PPCNONE, {RT, RAL, RB}},
+
+@@ -4478,8 +4484,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"andc", XRC(31,60,0), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
+ {"andc.", XRC(31,60,1), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
+
+-{"waitrsv", X(31,62)|(1<<21), 0xffffffff, POWER7|E500MC|PPCA2, PPCNONE, {0}},
+-{"waitimpl", X(31,62)|(2<<21), 0xffffffff, POWER7|E500MC|PPCA2, PPCNONE, {0}},
++{"waitrsv", X(31,62)|(1<<21), 0xffffffff, E500MC|PPCA2, PPCNONE, {0}},
++{"waitimpl", X(31,62)|(2<<21), 0xffffffff, E500MC|PPCA2, PPCNONE, {0}},
+ {"wait", X(31,62), XWC_MASK, POWER7|E500MC|PPCA2|PPCVLE, PPCNONE, {WC}},
+
+ {"dcbstep", XRT(31,63,0), XRT_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RA0, RB}},
+@@ -4543,7 +4549,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"mfvrwz", X(31,115)|1, XX1RB_MASK|1, PPCVSX2, PPCNONE, {RA, VS}},
+ {"mfvsrwz", X(31,115), XX1RB_MASK, PPCVSX2, PPCNONE, {RA, XS6}},
+
+-{"lharx", X(31,116), XEH_MASK, POWER7|PPCVLE, PPCNONE, {RT, RA0, RB, EH}},
++{"lharx", X(31,116), XEH_MASK, POWER8|PPCVLE, PPCNONE, {RT, RA0, RB, EH}},
+
+ {"clf", X(31,118), XTO_MASK, POWER, PPCNONE, {RA, RB}},
+
+@@ -4711,9 +4717,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"mtvsrwz", X(31,243), XX1RB_MASK, PPCVSX2, PPCNONE, {XT6, RA}},
+
+ {"dcbtstt", XRT(31,246,0x10), XRT_MASK, POWER7, PPCNONE, {RA0, RB}},
+-{"dcbtst", X(31,246), X_MASK, POWER4, PPCNONE, {RA0, RB, CT}},
+-{"dcbtst", X(31,246), X_MASK, PPC|PPCVLE, POWER4, {CT, RA0, RB}},
+-
++{"dcbtst", X(31,246), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}},
++{"dcbtst", X(31,246), X_MASK, DCBT_EO, PPCNONE, {CT, RA0, RB}},
++{"dcbtst", X(31,246), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}},
++
+ {"stbux", X(31,247), X_MASK, COM|PPCVLE, PPCNONE, {RS, RAS, RB}},
+
+ {"slliq", XRC(31,248,0), X_MASK, M601, PPCNONE, {RA, RS, SH}},
+@@ -4753,9 +4760,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"lscbx.", XRC(31,277,1), X_MASK, M601, PPCNONE, {RT, RA, RB}},
+
+ {"dcbtt", XRT(31,278,0x10), XRT_MASK, POWER7, PPCNONE, {RA0, RB}},
+-{"dcbt", X(31,278), X_MASK, POWER4, PPCNONE, {RA0, RB, CT}},
+-{"dcbt", X(31,278), X_MASK, PPC|PPCVLE, POWER4, {CT, RA0, RB}},
+-
++{"dcbt", X(31,278), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}},
++{"dcbt", X(31,278), X_MASK, DCBT_EO, PPCNONE, {CT, RA0, RB}},
++{"dcbt", X(31,278), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}},
++
+ {"lhzx", X(31,279), X_MASK, COM|PPCVLE, PPCNONE, {RT, RA0, RB}},
+
+ {"cdtbcd", X(31,282), XRB_MASK, POWER6, PPCNONE, {RA, RS}},
+@@ -5531,7 +5539,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"tendall.", XRC(31,686,1)|(1<<25), XRTRARB_MASK, PPCHTM, PPCNONE, {0}},
+ {"tend.", XRC(31,686,1), XRTARARB_MASK, PPCHTM, PPCNONE, {HTM_A}},
+
+-{"stbcx.", XRC(31,694,1), X_MASK, POWER7, PPCNONE, {RS, RA0, RB}},
++{"stbcx.", XRC(31,694,1), X_MASK, POWER8, PPCNONE, {RS, RA0, RB}},
+
+ {"stfsux", X(31,695), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},
+
+@@ -5561,7 +5569,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"stswi", X(31,725), X_MASK, PPCCOM|PPCVLE, E500|E500MC, {RS, RA0, NB}},
+ {"stsi", X(31,725), X_MASK, PWRCOM, PPCNONE, {RS, RA0, NB}},
+
+-{"sthcx.", XRC(31,726,1), X_MASK, POWER7, PPCNONE, {RS, RA0, RB}},
++{"sthcx.", XRC(31,726,1), X_MASK, POWER8, PPCNONE, {RS, RA0, RB}},
+
+ {"stfdx", X(31,727), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
+
diff --git a/SOURCES/gdb-rhbz1320945-power9-15of38.patch b/SOURCES/gdb-rhbz1320945-power9-15of38.patch
new file mode 100644
index 0000000..c0c7c13
--- /dev/null
+++ b/SOURCES/gdb-rhbz1320945-power9-15of38.patch
@@ -0,0 +1,81 @@
+commit 4bc0608a8b693f033555aa5705fdd5fc44cb9a9a
+Author: Peter Bergner <bergner@vnet.ibm.com>
+Date: Thu May 14 20:57:50 2015 -0500
+
+ Fix some PPC assembler errors.
+
+ Remove the wait instructions for server processors, since they were never
+ implemented. Also add the extra operands added to the tlbie and slbia
+ instructions with ISA 2.06 and ISA 2.05 respectively.
+
+ binutils/
+ * MAINTAINERS: Add myself as PPC maintainer.
+
+ opcodes/
+ * ppc-opc.c (IH) New define.
+ (powerpc_opcodes) <wait>: Do not enable for POWER7.
+ <tlbie>: Add RS operand for POWER7.
+ <slbia>: Add IH operand for POWER6.
+
+ gas/testsuite/
+ * gas/ppc/power4.d: Add a slbia test.
+ * gas/ppc/power4.s: Likewise.
+ * gas/ppc/power6.d: Add slbia and tlbie tests.
+ * gas/ppc/power6.s: Likewise.
+ * gas/ppc/power7.d: Remove wait tests. Add a tlbie test.
+ * gas/ppc/power7.s: Likewise.
+
+### a/opcodes/ChangeLog
+### b/opcodes/ChangeLog
+## -1,3 +1,10 @@
++2015-05-14 Peter Bergner <bergner@vnet.ibm.com>
++
++ * ppc-opc.c (IH) New define.
++ (powerpc_opcodes) <wait>: Do not enable for POWER7.
++ <tlbie>: Add RS operand for POWER7.
++ <slbia>: Add IH operand for POWER6.
++
+ 2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
+
+ * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
+--- a/opcodes/ppc-opc.c
++++ b/opcodes/ppc-opc.c
+@@ -866,6 +866,9 @@ const struct powerpc_operand powerpc_operands[] =
+
+ #define ERAT_T UIM + 1
+ { 0x7, 21, NULL, NULL, 0 },
++
++#define IH ERAT_T + 1
++ { 0x7, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
+ };
+
+ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
+@@ -4486,7 +4489,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+
+ {"waitrsv", X(31,62)|(1<<21), 0xffffffff, E500MC|PPCA2, PPCNONE, {0}},
+ {"waitimpl", X(31,62)|(2<<21), 0xffffffff, E500MC|PPCA2, PPCNONE, {0}},
+-{"wait", X(31,62), XWC_MASK, POWER7|E500MC|PPCA2|PPCVLE, PPCNONE, {WC}},
++{"wait", X(31,62), XWC_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {WC}},
+
+ {"dcbstep", XRT(31,63,0), XRT_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RA0, RB}},
+
+@@ -4780,7 +4783,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+
+ {"mfbhrbe", X(31,302), X_MASK, POWER8, PPCNONE, {RT, BHRBE}},
+
+-{"tlbie", X(31,306), XRTLRA_MASK, PPC, TITAN, {RB, L}},
++{"tlbie", X(31,306), XRA_MASK, POWER7, TITAN, {RB, RS}},
++{"tlbie", X(31,306), XRTLRA_MASK, PPC, POWER7|TITAN, {RB, L}},
+ {"tlbi", X(31,306), XRT_MASK, POWER, PPCNONE, {RA0, RB}},
+
+ {"eciwx", X(31,310), X_MASK, PPC, TITAN, {RT, RA0, RB}},
+@@ -5372,7 +5376,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+
+ {"icbtlse", X(31,494), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},
+
+-{"slbia", X(31,498), 0xffffffff, PPC64, PPCNONE, {0}},
++{"slbia", X(31,498), 0xff1fffff, POWER6, PPCNONE, {IH}},
++{"slbia", X(31,498), 0xffffffff, PPC64, POWER6, {0}},
+
+ {"cli", X(31,502), XRB_MASK, POWER, PPCNONE, {RT, RA}},
+
diff --git a/SOURCES/gdb-rhbz1320945-power9-16of38.patch b/SOURCES/gdb-rhbz1320945-power9-16of38.patch
new file mode 100644
index 0000000..71cae19
--- /dev/null
+++ b/SOURCES/gdb-rhbz1320945-power9-16of38.patch
@@ -0,0 +1,30 @@
+commit dc302c00611b6973fbc55e9fdd643ad24c370bd1
+Author: Peter Bergner <bergner@vnet.ibm.com>
+Date: Thu Jun 4 20:27:03 2015 -0500
+
+ Add hwsync extended mnemonic.
+
+ This commit adds a new extended menmonic for "sync 0" (same as "sync").
+ The ISA documentation doesn't explicitly mention hwsync as an extended
+ mnemonic (yet), but it does mention "heavyweight sync" and "hwsync" as
+ the operation that gets performed when the sync's L field is 0.
+ This is only enabled for POWER4 and later.
+
+ opcodes/
+ * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
+
+ gas/testsuite/
+ * gas/ppc/a2.d: Fixup test case due to new extended mnemonic.
+ * gas/ppc/power4.s <hwsync, lwsync, ptesync, sync>: Add tests.
+ * gas/ppc/power4.d: Likewise.
+
+--- a/opcodes/ppc-opc.c
++++ b/opcodes/ppc-opc.c
+@@ -5465,6 +5465,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"lswi", X(31,597), X_MASK, PPCCOM|PPCVLE, E500|E500MC, {RT, RAX, NBI}},
+ {"lsi", X(31,597), X_MASK, PWRCOM, PPCNONE, {RT, RA0, NB}},
+
++{"hwsync", XSYNC(31,598,0), 0xffffffff, POWER4, BOOKE|PPC476, {0}},
+ {"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, E500, {0}},
+ {"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, PPCNONE, {0}},
+ {"sync", X(31,598), XSYNCLE_MASK,E6500, PPCNONE, {LS, ESYNC}},
diff --git a/SOURCES/gdb-rhbz1320945-power9-17of38.patch b/SOURCES/gdb-rhbz1320945-power9-17of38.patch
new file mode 100644
index 0000000..3ea8521
--- /dev/null
+++ b/SOURCES/gdb-rhbz1320945-power9-17of38.patch
@@ -0,0 +1,43 @@
+commit 99a2c56121247207d4846fe7e28b5e7e18e0bfa0
+Author: Peter Bergner <bergner@vnet.ibm.com>
+Date: Fri Jun 12 15:06:07 2015 -0500
+
+ Remove unused MTMSRD_L macro and re-add accidentally deleted comment.
+
+ In the commit that added PowerPC Pair Singles, Ben accidentally removed
+ a comment and re-added an unused MTMSRD_L macro Alan had recently deleted.
+ This was probably just an oversite when he was refreshing his patch to
+ trunk.
+
+ opcodes/
+ * ppc-opc.c: Add comment accidentally removed by old commit.
+ (MTMSRD_L): Delete.
+
+### a/opcodes/ChangeLog
+### b/opcodes/ChangeLog
+## -1,3 +1,8 @@
++2015-06-12 Peter Bergner <bergner@vnet.ibm.com>
++
++ * ppc-opc.c: Add comment accidentally removed by old commit.
++ (MTMSRD_L): Delete.
++
+ 2015-06-04 Nick Clifton <nickc@redhat.com>
+
+ PR 18474
+--- a/opcodes/ppc-opc.c
++++ b/opcodes/ppc-opc.c
+@@ -747,12 +747,12 @@ const struct powerpc_operand powerpc_operands[] =
+ #define PSD PSQM + 1
+ { 0xfff, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
+
++ /* The L field in an mtmsrd or A form instruction or W in an X form. */
+ #define A_L PSD + 1
+ #define W A_L
+-#define MTMSRD_L W
+ { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
+
+-#define RMC MTMSRD_L + 1
++#define RMC A_L + 1
+ { 0x3, 9, NULL, NULL, 0 },
+
+ #define R RMC + 1
diff --git a/SOURCES/gdb-rhbz1320945-power9-18of38.patch b/SOURCES/gdb-rhbz1320945-power9-18of38.patch
new file mode 100644
index 0000000..33b0a0c
--- /dev/null
+++ b/SOURCES/gdb-rhbz1320945-power9-18of38.patch
@@ -0,0 +1,233 @@
+commit 11a0cf2ec0ed6e70ff25e9a50c2223dcd98c1c10
+Author: Peter Bergner <bergner@vnet.ibm.com>
+Date: Fri Jun 19 17:17:07 2015 -0500
+
+ Allow for optional operands with non-zero default values.
+
+ ISA 2.07 (ie, POWER8) added the rfebb instruction which takes one operand
+ with the value of either a 0 or 1. It also defines an extended mnemonic
+ with no operands (ie, "rfebb") that is supposed to be equivalent to "rfebb 1".
+ I implemented rfebb's lone operand with PPC_OPERAND_OPTIONAL, but the
+ problem is, optional operands that are ommitted always default to the
+ value 0, which is wrong in this case. I have added support for allowing
+ non-zero default values by adding an additional flag PPC_OPERAND_OPTIONAL_VALUE
+ that specifies that the default operand value to be used is stored in the
+ SHIFT field of the operand field immediately following this one.
+
+ This fixes the rfebb issue. I also fixed the mftb and mfcr instructions
+ so they use the same mechanism. This allows us to flag invalid uses of
+ mfcr where we explicitly pass in a zero FXM value, like the use in a2.[sd].
+
+ include/opcode/
+
+ * ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New.
+ (ppc_optional_operand_value): New inline function.
+
+ opcodes/
+ * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
+ * ppc-opc.c (FXM4): Add non-zero optional value.
+ (TBR): Likewise.
+ (SXL): Likewise.
+ (insert_fxm): Handle new default operand value.
+ (extract_fxm): Likewise.
+ (insert_tbr): Likewise.
+ (extract_tbr): Likewise.
+
+ gas/
+ * config/tc-ppc.c (md_assemble): Use ppc_optional_operand_value.
+ Allow for optional operands without insert functions.
+
+ gas/testsuite/
+ * gas/ppc/power8.d: Fixup rfebb test results.
+ * gas/ppc/a2.s: Fix invalid mfcr test.
+ * gas/ppc/a2.d: Likewise.
+
+### a/include/opcode/ChangeLog
+### b/include/opcode/ChangeLog
+## -1,3 +1,8 @@
++2015-06-19 Peter Bergner <bergner@vnet.ibm.com>
++
++ * ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New.
++ (ppc_optional_operand_value): New inline function.
++
+ 2015-06-04 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64.h (AARCH64_V8_1): New.
+--- a/include/opcode/ppc.h
++++ b/include/opcode/ppc.h
+@@ -380,6 +380,11 @@ extern const unsigned int num_powerpc_operands;
+
+ /* This is a CR FIELD that does not use symbolic names. */
+ #define PPC_OPERAND_CR_REG (0x200000)
++
++/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
++ is omitted, then the value it should use for the operand is stored
++ in the SHIFT field of the immediatly following operand field. */
++#define PPC_OPERAND_OPTIONAL_VALUE (0x400000)
+
+ /* The POWER and PowerPC assemblers use a few macros. We keep them
+ with the operands table for simplicity. The macro table is an
+@@ -409,4 +414,12 @@ extern const int powerpc_num_macros;
+
+ extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, ppc_cpu_t *, const char *);
+
++static inline long
++ppc_optional_operand_value (const struct powerpc_operand *operand)
++{
++ if ((operand->flags & PPC_OPERAND_OPTIONAL_VALUE) != 0)
++ return (operand+1)->shift;
++ return 0;
++}
++
+ #endif /* PPC_H */
+### a/opcodes/ChangeLog
+### b/opcodes/ChangeLog
+## -1,3 +1,14 @@
++2015-06-19 Peter Bergner <bergner@vnet.ibm.com>
++
++ * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
++ * ppc-opc.c (FXM4): Add non-zero optional value.
++ (TBR): Likewise.
++ (SXL): Likewise.
++ (insert_fxm): Handle new default operand value.
++ (extract_fxm): Likewise.
++ (insert_tbr): Likewise.
++ (extract_tbr): Likewise.
++
+ 2015-06-16 Matthew Wahab <matthew.wahab@arm.com>
+
+ * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
+--- a/opcodes/ppc-dis.c
++++ b/opcodes/ppc-dis.c
+@@ -452,7 +452,8 @@ skip_optional_operands (const unsigned char *opindex,
+ operand = &powerpc_operands[*opindex];
+ if ((operand->flags & PPC_OPERAND_NEXT) != 0
+ || ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
+- && operand_value_powerpc (operand, insn, dialect) != 0))
++ && operand_value_powerpc (operand, insn, dialect) !=
++ ppc_optional_operand_value (operand)))
+ return 0;
+ }
+
+--- a/opcodes/ppc-opc.c
++++ b/opcodes/ppc-opc.c
+@@ -382,10 +382,12 @@ const struct powerpc_operand powerpc_operands[] =
+
+ /* Power4 version for mfcr. */
+ #define FXM4 FXM + 1
+- { 0xff, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL },
++ { 0xff, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE},
++ /* If the FXM4 operand is ommitted, use the sentinel value -1. */
++ { -1, -1, NULL, NULL, 0},
+
+ /* The IMM20 field in an LI instruction. */
+-#define IMM20 FXM4 + 1
++#define IMM20 FXM4 + 2
+ { 0xfffff, PPC_OPSHIFT_INV, insert_li20, extract_li20, PPC_OPERAND_SIGNED},
+
+ /* The L field in a D or X form instruction. */
+@@ -642,10 +644,12 @@ const struct powerpc_operand powerpc_operands[] =
+ /* The TBR field in an XFX form instruction. This is like the SPR
+ field, but it is optional. */
+ #define TBR SV + 1
+- { 0x3ff, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
++ { 0x3ff, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE},
++ /* If the TBR operand is ommitted, use the value 268. */
++ { -1, 268, NULL, NULL, 0},
+
+ /* The TO field in a D or X form instruction. */
+-#define TO TBR + 1
++#define TO TBR + 2
+ #define DUI TO
+ #define TO_MASK (0x1f << 21)
+ { 0x1f, 21, NULL, NULL, 0 },
+@@ -766,10 +770,12 @@ const struct powerpc_operand powerpc_operands[] =
+
+ /* The S field in a XL form instruction. */
+ #define SXL S + 1
+- { 0x1, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
++ { 0x1, 11, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE},
++ /* If the SXL operand is ommitted, use the value 1. */
++ { -1, 1, NULL, NULL, 0},
+
+ /* SH field starting at bit position 16. */
+-#define SH16 SXL + 1
++#define SH16 SXL + 2
+ /* The DCM and DGM fields in a Z form instruction. */
+ #define DCM SH16
+ #define DGM DCM
+@@ -1284,19 +1290,13 @@ insert_fxm (unsigned long insn,
+ }
+ }
+
+- /* If the optional field on mfcr is missing that means we want to use
+- the old form of the instruction that moves the whole cr. In that
+- case we'll have VALUE zero. There doesn't seem to be a way to
+- distinguish this from the case where someone writes mfcr %r3,0. */
+- else if (value == 0)
+- ;
+-
+ /* If only one bit of the FXM field is set, we can use the new form
+ of the instruction, which is faster. Unlike the Power4 branch hint
+ encoding, this is not backward compatible. Do not generate the
+ new form unless -mpower4 has been given, or -many and the two
+ operand form of mfcr was used. */
+- else if ((value & -value) == value
++ else if (value > 0
++ && (value & -value) == value
+ && ((dialect & PPC_OPCODE_POWER4) != 0
+ || ((dialect & PPC_OPCODE_ANY) != 0
+ && (insn & (0x3ff << 1)) == 19 << 1)))
+@@ -1305,7 +1305,10 @@ insert_fxm (unsigned long insn,
+ /* Any other value on mfcr is an error. */
+ else if ((insn & (0x3ff << 1)) == 19 << 1)
+ {
+- *errmsg = _("ignoring invalid mfcr mask");
++ /* A value of -1 means we used the one operand form of
++ mfcr which is valid. */
++ if (value != -1)
++ *errmsg = _("ignoring invalid mfcr mask");
+ value = 0;
+ }
+
+@@ -1332,6 +1335,8 @@ extract_fxm (unsigned long insn,
+ {
+ if (mask != 0)
+ *invalid = 1;
++ else
++ mask = -1;
+ }
+
+ return mask;
+@@ -1868,12 +1873,7 @@ extract_sprg (unsigned long insn,
+ }
+
+ /* The TBR field in an XFX instruction. This is just like SPR, but it
+- is optional. When TBR is omitted, it must be inserted as 268 (the
+- magic number of the TB register). These functions treat 0
+- (indicating an omitted optional operand) as 268. This means that
+- ``mftb 4,0'' is not handled correctly. This does not matter very
+- much, since the architecture manual does not define mftb as
+- accepting any values other than 268 or 269. */
++ is optional. */
+
+ static unsigned long
+ insert_tbr (unsigned long insn,
+@@ -1881,8 +1881,6 @@ insert_tbr (unsigned long insn,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg)
+ {
+- if (value == 0)
+- value = 268;
+ if (value != 268 && value != 269)
+ *errmsg = _("invalid tbr number");
+ return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
+@@ -1898,8 +1896,6 @@ extract_tbr (unsigned long insn,
+ ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
+ if (ret != 268 && ret != 269)
+ *invalid = 1;
+- if (ret == 268)
+- ret = 0;
+ return ret;
+ }
+
diff --git a/SOURCES/gdb-rhbz1320945-power9-19of38.patch b/SOURCES/gdb-rhbz1320945-power9-19of38.patch
new file mode 100644
index 0000000..8f9a72a
--- /dev/null
+++ b/SOURCES/gdb-rhbz1320945-power9-19of38.patch
@@ -0,0 +1,148 @@
+commit 7b9341139a693eac8d316275004b2d752b1f0cb8
+Author: Peter Bergner <bergner@vnet.ibm.com>
+Date: Mon Jun 22 14:55:24 2015 -0500
+
+ PPC sync instruction accepts invalid and incompatible operands
+
+ ISA 2.07 added a new category called Elemental Memory Barriers that modifies
+ the sync instruction to accept an additional operand ESYNC. Edmar added
+ support for this insruction varient here:
+
+ https://sourceware.org/ml/binutils/2012-02/msg00221.html
+
+ Looking at this closer, I see that the insert_ls() function is misnamed
+ (since it's attached to the ESYNC operand, not the LS operand) but more
+ importantly, it is silently modifying the LS operand value behind the
+ users back when the LS operand is either invalid or is incompatible with
+ the new ESYNC operand. The ISA 2.07 doc has an Assembler Note that clearly
+ states that assemblers that support the ESYNC operand should report all
+ invalid uses of LS and ESYNC. This patch changes the assembler to
+ error out on invalid and incompatible operand usage.
+
+ opcodes/
+ * ppc-opc.c (insert_ls): Test for invalid LS operands.
+ (insert_esync): New function.
+ (LS, WC): Use insert_ls.
+ (ESYNC): Use insert_esync.
+
+ gas/testsuite/
+ * gas/ppc/e6500.s <sync>: Fix invalid test.
+ * gas/ppc/e6500.d: Likewise.
+
+### a/opcodes/ChangeLog
+### b/opcodes/ChangeLog
+## -1,3 +1,10 @@
++2015-06-22 Peter Bergner <bergner@vnet.ibm.com>
++
++ * ppc-opc.c (insert_ls): Test for invalid LS operands.
++ (insert_esync): New function.
++ (LS, WC): Use insert_ls.
++ (ESYNC): Use insert_esync.
++
+ 2015-06-22 Nick Clifton <nickc@redhat.com>
+
+ * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
+--- a/opcodes/ppc-opc.c
++++ b/opcodes/ppc-opc.c
+@@ -53,6 +53,7 @@ static unsigned long insert_bo (unsigned long, long, ppc_cpu_t, const char **);
+ static long extract_bo (unsigned long, ppc_cpu_t, int *);
+ static unsigned long insert_boe (unsigned long, long, ppc_cpu_t, const char **);
+ static long extract_boe (unsigned long, ppc_cpu_t, int *);
++static unsigned long insert_esync (unsigned long, long, ppc_cpu_t, const char **);
+ static unsigned long insert_fxm (unsigned long, long, ppc_cpu_t, const char **);
+ static long extract_fxm (unsigned long, ppc_cpu_t, int *);
+ static unsigned long insert_li20 (unsigned long, long, ppc_cpu_t, const char **);
+@@ -417,7 +418,7 @@ const struct powerpc_operand powerpc_operands[] =
+ /* The LS or WC field in an X (sync or wait) form instruction. */
+ #define LS LIA + 1
+ #define WC LS
+- { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
++ { 0x3, 21, insert_ls, NULL, PPC_OPERAND_OPTIONAL },
+
+ /* The ME field in an M form instruction. */
+ #define ME LS + 1
+@@ -635,7 +636,7 @@ const struct powerpc_operand powerpc_operands[] =
+
+ /* The ESYNC field in an X (sync) form instruction. */
+ #define ESYNC STRM + 1
+- { 0xf, 16, insert_ls, NULL, PPC_OPERAND_OPTIONAL },
++ { 0xf, 16, insert_esync, NULL, PPC_OPERAND_OPTIONAL },
+
+ /* The SV field in a POWER SC form instruction. */
+ #define SV ESYNC + 1
+@@ -1365,17 +1366,40 @@ extract_li20 (unsigned long insn,
+ | (insn & 0x7ff);
+ }
+
+-/* The LS field in a sync instruction that accepts 2 operands
+- Values 2 and 3 are reserved,
+- must be treated as 0 for future compatibility
+- Values 0 and 1 can be accepted, if field ESYNC is zero
+- Otherwise L = complement of ESYNC-bit2 (1<<18) */
++/* The 2-bit L field in a SYNC or WC field in a WAIT instruction.
++ For SYNC, some L values are reserved:
++ * Value 3 is reserved on newer server cpus.
++ * Values 2 and 3 are reserved on all other cpus. */
+
+ static unsigned long
+ insert_ls (unsigned long insn,
+ long value,
+- ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+- const char **errmsg ATTRIBUTE_UNUSED)
++ ppc_cpu_t dialect,
++ const char **errmsg)
++{
++ /* For SYNC, some L values are illegal. */
++ if (((insn >> 1) & 0x3ff) == 598)
++ {
++ long max_lvalue = (dialect & PPC_OPCODE_POWER4) ? 2 : 1;
++ if (value > max_lvalue)
++ {
++ *errmsg = _("illegal L operand value");
++ return insn;
++ }
++ }
++
++ return insn | ((value & 0x3) << 21);
++}
++
++/* The 4-bit E field in a sync instruction that accepts 2 operands.
++ If ESYNC is non-zero, then the L field must be either 0 or 1 and
++ the complement of ESYNC-bit2. */
++
++static unsigned long
++insert_esync (unsigned long insn,
++ long value,
++ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
++ const char **errmsg)
+ {
+ unsigned long ls;
+
+@@ -1383,12 +1407,15 @@ insert_ls (unsigned long insn,
+ if (value == 0)
+ {
+ if (ls > 1)
+- return insn & ~(0x3 << 21);
++ *errmsg = _("illegal L operand value");
+ return insn;
+ }
+- if ((value & 0x2) != 0)
+- return (insn & ~(0x3 << 21)) | ((value & 0xf) << 16);
+- return (insn & ~(0x3 << 21)) | (0x1 << 21) | ((value & 0xf) << 16);
++
++ if ((ls & ~0x1)
++ || (((value >> 1) & 0x1) ^ ls) == 0)
++ *errmsg = _("incompatible L operand value");
++
++ return insn | ((value & 0xf) << 16);
+ }
+
+ /* The MB and ME fields in an M form instruction expressed as a single
+@@ -2024,6 +2051,7 @@ extract_dm (unsigned long insn,
+ *invalid = 1;
+ return (value) ? 1 : 0;
+ }
++
+ /* The VLESIMM field in an I16A form instruction. This is split. */
+
+ static unsigned long
diff --git a/SOURCES/gdb-rhbz1320945-power9-20of38.patch b/SOURCES/gdb-rhbz1320945-power9-20of38.patch
new file mode 100644
index 0000000..bffabd8
--- /dev/null
+++ b/SOURCES/gdb-rhbz1320945-power9-20of38.patch
@@ -0,0 +1,106 @@
+commit ef5a96d564a22a25d31533c7377eede42c12b25c
+Author: Alan Modra <amodra@gmail.com>
+Date: Fri Jul 3 10:56:26 2015 +0930
+
+ Remove ppc860, ppc750cl, ppc7450 insns from common ppc.
+
+ Back in the day support for these processors was added, we probably
+ didn't want to waste PPC_OPCODE bits on minor variations. I've had a
+ complaint that disassembly of mfspr/mtspr was wrong for power8. This
+ patch fixes that problem.
+
+ Note that since -m860/-m850/-m821 are new gas options enabling the
+ mpc8xx specific mfspr/mtspr variants it is possible that this change
+ will break some mpc8xx assembly code. ie. you might need to modify
+ makefiles to pass -m860 to gas.
+
+ include/opcode/
+ * ppc.h (PPC_OPCODE_750, PPC_OPCODE_7450, PPC_OPCODE_860): Define.
+ opcodes/
+ * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
+ * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
+ PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
+ gas/
+ * config/tc-ppc.c (md_show_usage): Add -m821, -m850, -m860.
+ * doc/c-ppc.texi (PowerPC-Opts): Likewise.
+ gas/testsuite/
+ * gas/ppc/titan.d: Correct mfmcsrr0 disassembly.
+
+### a/include/opcode/ChangeLog
+### b/include/opcode/ChangeLog
+## -1,3 +1,7 @@
++2015-07-03 Alan Modra <amodra@gmail.com>
++
++ * ppc.h (PPC_OPCODE_750, PPC_OPCODE_7450, PPC_OPCODE_860): Define.
++
+ 2015-07-01 Sandra Loosemore <sandra@codesourcery.com>
+ Cesar Philippidis <cesar@codesourcery.com>
+
+--- a/include/opcode/ppc.h
++++ b/include/opcode/ppc.h
+@@ -195,6 +195,15 @@ extern const int vle_num_opcodes;
+ that isn't a superset of POWER8, we can define this to its own mask. */
+ #define PPC_OPCODE_HTM PPC_OPCODE_POWER8
+
++/* Opcode is supported by ppc750cl. */
++#define PPC_OPCODE_750 0x4000000000ull
++
++/* Opcode is supported by ppc7450. */
++#define PPC_OPCODE_7450 0x8000000000ull
++
++/* Opcode is supported by ppc821/850/860. */
++#define PPC_OPCODE_860 0x10000000000ull
++
+ /* A macro to extract the major opcode from an instruction. */
+ #define PPC_OP(i) (((i) >> 26) & 0x3f)
+
+### a/opcodes/ChangeLog
+### b/opcodes/ChangeLog
+## -1,3 +1,9 @@
++2015-07-03 Alan Modra <amodra@gmail.com>
++
++ * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
++ * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
++ PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
++
+ 2015-07-01 Sandra Loosemore <sandra@codesourcery.com>
+ Cesar Philippidis <cesar@codesourcery.com>
+
+--- a/opcodes/ppc-dis.c
++++ b/opcodes/ppc-dis.c
+@@ -76,12 +76,18 @@ struct ppc_mopt ppc_opts[] = {
+ 0 },
+ { "7410", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
+ 0 },
+- { "7450", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
++ { "7450", (PPC_OPCODE_PPC | PPC_OPCODE_7450 | PPC_OPCODE_ALTIVEC),
+ 0 },
+ { "7455", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
+ 0 },
+- { "750cl", (PPC_OPCODE_PPC | PPC_OPCODE_PPCPS)
++ { "750cl", (PPC_OPCODE_PPC | PPC_OPCODE_750 | PPC_OPCODE_PPCPS)
+ , 0 },
++ { "821", (PPC_OPCODE_PPC | PPC_OPCODE_860),
++ 0 },
++ { "850", (PPC_OPCODE_PPC | PPC_OPCODE_860),
++ 0 },
++ { "860", (PPC_OPCODE_PPC | PPC_OPCODE_860),
++ 0 },
+ { "a2", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_POWER4
+ | PPC_OPCODE_POWER5 | PPC_OPCODE_CACHELCK | PPC_OPCODE_64
+ | PPC_OPCODE_A2),
+--- a/opcodes/ppc-opc.c
++++ b/opcodes/ppc-opc.c
+@@ -2747,9 +2747,9 @@ extract_vleil (unsigned long insn,
+ #define PPC440 PPC_OPCODE_440
+ #define PPC464 PPC440
+ #define PPC476 PPC_OPCODE_476
+-#define PPC750 PPC
+-#define PPC7450 PPC
+-#define PPC860 PPC
++#define PPC750 PPC_OPCODE_750
++#define PPC7450 PPC_OPCODE_7450
++#define PPC860 PPC_OPCODE_860
+ #define PPCPS PPC_OPCODE_PPCPS
+ #define PPCVEC PPC_OPCODE_ALTIVEC
+ #define PPCVEC2 PPC_OPCODE_ALTIVEC2
diff --git a/SOURCES/gdb-rhbz1320945-power9-21of38.patch b/SOURCES/gdb-rhbz1320945-power9-21of38.patch
new file mode 100644
index 0000000..9f98640
--- /dev/null
+++ b/SOURCES/gdb-rhbz1320945-power9-21of38.patch
@@ -0,0 +1,79 @@
+commit 36f7a9411dcd7dbeb3483bc83a1acbb3dd235deb
+Author: Tom Rix <tom@bumblecow.com>
+Date: Mon Sep 28 12:09:32 2015 +0930
+
+ Patches for illegal ppc 500 instructions
+
+ This change marks a few opcodes as invalid for ppc e500 as well as adds
+ a test to verify the change.
+
+### a/opcodes/ChangeLog
+### b/opcodes/ChangeLog
+## -1,3 +1,7 @@
++2015-09-28 Tom Rix <tom@bumblecow.com>
++
++ * ppc-opc.c (PPC500): Mark some opcodes as invalid
++
+ 2015-09-23 Nick Clifton <nickc@redhat.com>
+
+ * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
+--- a/opcodes/ppc-opc.c
++++ b/opcodes/ppc-opc.c
+@@ -4779,7 +4779,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+
+ {"tlbiel", X(31,274), XRTLRA_MASK, POWER4, PPC476, {RB, L}},
+
+-{"mfapidi", X(31,275), X_MASK, BOOKE, TITAN, {RT, RA}},
++{"mfapidi", X(31,275), X_MASK, BOOKE, E500|TITAN, {RT, RA}},
+
+ {"lqarx", X(31,276), XEH_MASK, POWER8, PPCNONE, {RTQ, RAX, RBX, EH}},
+
+@@ -4808,10 +4808,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"mfbhrbe", X(31,302), X_MASK, POWER8, PPCNONE, {RT, BHRBE}},
+
+ {"tlbie", X(31,306), XRA_MASK, POWER7, TITAN, {RB, RS}},
+-{"tlbie", X(31,306), XRTLRA_MASK, PPC, POWER7|TITAN, {RB, L}},
++{"tlbie", X(31,306), XRTLRA_MASK, PPC, E500|POWER7|TITAN, {RB, L}},
+ {"tlbi", X(31,306), XRT_MASK, POWER, PPCNONE, {RA0, RB}},
+
+-{"eciwx", X(31,310), X_MASK, PPC, TITAN, {RT, RA0, RB}},
++{"eciwx", X(31,310), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
+
+ {"lhzux", X(31,311), X_MASK, COM|PPCVLE, PPCNONE, {RT, RAL, RB}},
+
+@@ -4856,7 +4856,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, PPCNONE, {RT}},
+ {"mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, PPCNONE, {RT}},
+ {"mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mfdcr", X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476|PPCVLE, TITAN, {RT, SPR}},
++{"mfdcr", X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476|PPCVLE, E500|TITAN, {RT, SPR}},
+ {"mfdcr.", XRC(31,323,1), X_MASK, PPCA2, PPCNONE, {RT, SPR}},
+
+ {"lvexwx", X(31,325), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
+@@ -5087,7 +5087,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"divs", XO(31,363,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
+ {"divs.", XO(31,363,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
+
+-{"tlbia", X(31,370), 0xffffffff, PPC, TITAN, {0}},
++{"tlbia", X(31,370), 0xffffffff, PPC, E500|TITAN, {0}},
+
+ {"mftbu", XSPR(31,371,269), XSPR_MASK, PPC, NO371|POWER4, {RT}},
+ {"mftb", X(31,371), X_MASK, PPC, NO371|POWER4, {RT, TBR}},
+@@ -5145,7 +5145,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+
+ {"slbie", X(31,434), XRTRA_MASK, PPC64, PPCNONE, {RB}},
+
+-{"ecowx", X(31,438), X_MASK, PPC, TITAN, {RT, RA0, RB}},
++{"ecowx", X(31,438), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
+
+ {"sthux", X(31,439), X_MASK, COM|PPCVLE, PPCNONE, {RS, RAS, RB}},
+
+@@ -5197,7 +5197,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, PPCNONE, {RS}},
+ {"mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, PPCNONE, {RS}},
+ {"mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mtdcr", X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476|PPCVLE, TITAN, {SPR, RS}},
++{"mtdcr", X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476|PPCVLE, E500|TITAN, {SPR, RS}},
+ {"mtdcr.", XRC(31,451,1), X_MASK, PPCA2, PPCNONE, {SPR, RS}},
+
+ {"stvexwx", X(31,453), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
diff --git a/SOURCES/gdb-rhbz1320945-power9-22of38.patch b/SOURCES/gdb-rhbz1320945-power9-22of38.patch
new file mode 100644
index 0000000..e31d44a
--- /dev/null
+++ b/SOURCES/gdb-rhbz1320945-power9-22of38.patch
@@ -0,0 +1,20973 @@
+commit 43e65147c07b1400ae0dbb6694882eceb2363713
+Author: H.J. Lu <hjl.tools@gmail.com>
+Date: Wed Aug 12 04:45:07 2015 -0700
+
+ Remove trailing spaces in opcodes
+
+--- a/opcodes/ChangeLog-2006
++++ b/opcodes/ChangeLog-2006
+@@ -193,11 +193,11 @@
+
+ 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
+
+- * i386-dis.c (dis386): Add support for the change in POPCNT opcode in
++ * i386-dis.c (dis386): Add support for the change in POPCNT opcode in
+ amdfam10 architecture.
+ (PREGRP37): NEW.
+ (print_insn): Disallow REP prefix for POPCNT.
+-
++
+ 2006-10-20 Andrew Stubbs <andrew.stubbs@st.com>
+
+ * sh-dis.c (print_insn_sh): Remove 0x from output to prevent GDB
+@@ -274,9 +274,9 @@
+ * i386-dis.c (MXC,EMC): Define.
+ (OP_MXC): New function to handle cvt* (convert instructions) between
+ %xmm and %mm register correctly.
+- (OP_EMC): ditto.
+- (prefix_user_table): Modified cvtpi2pd,cvtpd2pi and cvttpd2pi
+- instruction operands in PREGRP2,PREGRP3,PREGRP4 appropriately
++ (OP_EMC): ditto.
++ (prefix_user_table): Modified cvtpi2pd,cvtpd2pi and cvttpd2pi
++ instruction operands in PREGRP2,PREGRP3,PREGRP4 appropriately
+ with EMC/MXC.
+
+ 2006-07-29 Richard Sandiford <richard@codesourcery.com>
+@@ -689,7 +689,7 @@
+ New cases '$' and '%' for read/write hyperprivileged register.
+ * sparc-opc.c (sparc_opcodes): Add new entries for UA2005
+ window handling and rdhpr/wrhpr instructions.
+-
++
+ 2006-02-24 DJ Delorie <dj@redhat.com>
+
+ * m32c-desc.c: Regenerate with linker relaxation attributes.
+@@ -742,13 +742,13 @@
+
+ * xc16x-desc.h: New file
+ * xc16x-desc.c: New file
+- * xc16x-opc.h: New file
++ * xc16x-opc.h: New file
+ * xc16x-opc.c: New file
+ * xc16x-ibld.c: New file
+ * xc16x-asm.c: New file
+ * xc16x-dis.c: New file
+- * Makefile.am: Entries for xc16x
+- * Makefile.in: Regenerate
++ * Makefile.am: Entries for xc16x
++ * Makefile.in: Regenerate
+ * cofigure.in: Add xc16x target information.
+ * configure: Regenerate.
+ * disassemble.c: Add xc16x target information.
+@@ -783,7 +783,7 @@
+
+ * z80-dis.c (struct buffer, prt_d, prt_d_n, arit_d, ld_r_d,
+ ld_d_r, pref_xd_cb): Use signed char to hold data to be
+- disassembled.
++ disassembled.
+ * z80-dis.c (TXTSIZ): Increase buffer size to 24, this fixes
+ buffer overflows when disassembling instructions like
+ ld (ix+123),0x23
+--- a/opcodes/ChangeLog-2007
++++ b/opcodes/ChangeLog-2007
+@@ -1071,7 +1071,7 @@
+ * s390-mkopc.c (struct s390_cond_ext_format): New global struct.
+ (s390_cond_ext_format): New global variable.
+ (expandConditionalJump): New function.
+- (main): Invoke expandConditionalJump for mnemonics containing '*'.
++ (main): Invoke expandConditionalJump for mnemonics containing '*'.
+ * s390-opc.txt: Replace mnemonics with conditional
+ mask extensions with instructions using the newly introduced '*' tag.
+
+@@ -1096,7 +1096,7 @@
+ * ia64-gen.c: (main): Add missing newline to copyright message.
+ * ia64-ic.tbl (fp-non-arith): Add xmpy.
+ * ia64-asmtab.c: Regenerate.
+-
++
+ 2007-08-01 Michael Snyder <msnyder@access-company.com>
+
+ * i386-dis.c (print_insn): Guard against NULL.
+#--- a/opcodes/Makefile.am
+#+++ b/opcodes/Makefile.am
+#@@ -6,12 +6,12 @@
+# # it under the terms of the GNU General Public License as published by
+# # the Free Software Foundation; either version 3 of the License, or
+# # (at your option) any later version.
+#-#
+#+#
+# # This program is distributed in the hope that it will be useful,
+# # but WITHOUT ANY WARRANTY; without even the implied warranty of
+# # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# # GNU General Public License for more details.
+#-#
+#+#
+# # You should have received a copy of the GNU General Public License
+# # along with this program; see the file COPYING3. If not see
+# # <http://www.gnu.org/licenses/>.
+#@@ -392,15 +392,15 @@ EPIPHANY_DEPS =
+# FR30_DEPS =
+# FRV_DEPS =
+# IP2K_DEPS =
+#-IQ2000_DEPS =
+#-LM32_DEPS =
+#+IQ2000_DEPS =
+#+LM32_DEPS =
+# M32C_DEPS =
+# M32R_DEPS =
+# MEP_DEPS =
+# MT_DEPS =
+#-OR1K_DEPS =
+#-XC16X_DEPS =
+#-XSTORMY16_DEPS =
+#+OR1K_DEPS =
+#+XC16X_DEPS =
+#+XSTORMY16_DEPS =
+# endif
+#
+# run-cgen:
+#@@ -546,7 +546,7 @@ i386-gen.o: i386-gen.c i386-opc.h $(srcdir)/../include/opcode/i386.h \
+# config.h i386-opc.h sysdep.h
+# $(COMPILE_FOR_BUILD) -c $(srcdir)/i386-gen.c
+#
+#-$(srcdir)/i386-tbl.h: $(srcdir)/i386-init.h
+#+$(srcdir)/i386-tbl.h: $(srcdir)/i386-init.h
+# @echo $@
+#
+# $(srcdir)/i386-init.h: @MAINT@ i386-gen$(EXEEXT_FOR_BUILD) i386-opc.tbl i386-reg.tbl
+--- a/opcodes/Makefile.in
++++ b/opcodes/Makefile.in
+@@ -22,12 +22,12 @@
+ # it under the terms of the GNU General Public License as published by
+ # the Free Software Foundation; either version 3 of the License, or
+ # (at your option) any later version.
+-#
++#
+ # This program is distributed in the hope that it will be useful,
+ # but WITHOUT ANY WARRANTY; without even the implied warranty of
+ # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ # GNU General Public License for more details.
+-#
++#
+ # You should have received a copy of the GNU General Public License
+ # along with this program; see the file COPYING3. If not see
+ # <http://www.gnu.org/licenses/>.
+@@ -1416,7 +1416,7 @@ i386-gen.o: i386-gen.c i386-opc.h $(srcdir)/../include/opcode/i386.h \
+ config.h i386-opc.h sysdep.h
+ $(COMPILE_FOR_BUILD) -c $(srcdir)/i386-gen.c
+
+-$(srcdir)/i386-tbl.h: $(srcdir)/i386-init.h
++$(srcdir)/i386-tbl.h: $(srcdir)/i386-init.h
+ @echo $@
+
+ $(srcdir)/i386-init.h: @MAINT@ i386-gen$(EXEEXT_FOR_BUILD) i386-opc.tbl i386-reg.tbl
+--- a/opcodes/aarch64-gen.c
++++ b/opcodes/aarch64-gen.c
+@@ -209,7 +209,7 @@ static int max_num_opcodes_at_leaf_node = 0;
+ is decided to be undividable and OPCODE will be assigned to BITTREE->LIST.
+
+ The function recursively call itself until OPCODE is undividable.
+-
++
+ N.B. the nature of this algrithm determines that given any value in the
+ 32-bit space, the computed decision tree will always be able to find one or
+ more opcodes entries for it, regardless whether there is a valid instruction
+--- a/opcodes/alpha-opc.c
++++ b/opcodes/alpha-opc.c
+@@ -274,7 +274,7 @@ const struct alpha_operand alpha_operands[] =
+
+ /* The signed "23-bit" aligned displacement of Branch format insns. */
+ #define BDISP (MDISP + 1)
+- { 21, 0, BFD_RELOC_23_PCREL_S2,
++ { 21, 0, BFD_RELOC_23_PCREL_S2,
+ AXP_OPERAND_RELATIVE, insert_bdisp, extract_bdisp },
+
+ /* The 26-bit PALcode function */
+--- a/opcodes/arc-dis.c
++++ b/opcodes/arc-dis.c
+@@ -35,18 +35,18 @@
+ #define dbg (0)
+ #endif
+
+-/* Classification of the opcodes for the decoder to print
++/* Classification of the opcodes for the decoder to print
+ the instructions. */
+
+ typedef enum
+ {
+- CLASS_A4_ARITH,
++ CLASS_A4_ARITH,
+ CLASS_A4_OP3_GENERAL,
+ CLASS_A4_FLAG,
+ /* All branches other than JC. */
+ CLASS_A4_BRANCH,
+ CLASS_A4_JC ,
+- /* All loads other than immediate
++ /* All loads other than immediate
+ indexed loads. */
+ CLASS_A4_LD0,
+ CLASS_A4_LD1,
+--- a/opcodes/arc-dis.h
++++ b/opcodes/arc-dis.h
+@@ -21,14 +21,14 @@
+ #ifndef ARCDIS_H
+ #define ARCDIS_H
+
+-enum
++enum
+ {
+ BR_exec_when_no_jump,
+ BR_exec_always,
+ BR_exec_when_jump
+ };
+
+-enum Flow
++enum Flow
+ {
+ noflow,
+ direct_jump,
+@@ -41,7 +41,7 @@ enum Flow
+ enum { no_reg = 99 };
+ enum { allOperandsSize = 256 };
+
+-struct arcDisState
++struct arcDisState
+ {
+ void *_this;
+ int instructionLen;
+@@ -50,7 +50,7 @@ struct arcDisState
+ const char *(*auxRegName)(void*, int);
+ const char *(*condCodeName)(void*, int);
+ const char *(*instName)(void*, int, int, int*);
+-
++
+ unsigned char* instruction;
+ unsigned index;
+ const char *comm[6]; /* instr name, cond, NOP, 3 operands */
+--- a/opcodes/arc-ext.h
++++ b/opcodes/arc-ext.h
+@@ -30,20 +30,20 @@ enum {NUM_EXT_INST = (0x1f-0x10+1) + (0x3f-0x09+1)};
+ enum {NUM_EXT_CORE = 59-32+1};
+ enum {NUM_EXT_COND = 0x1f-0x10+1};
+
+-struct ExtInstruction
++struct ExtInstruction
+ {
+ char flags;
+ char *name;
+-};
++};
+
+-struct ExtAuxRegister
++struct ExtAuxRegister
+ {
+ long address;
+ char *name;
+- struct ExtAuxRegister *next;
++ struct ExtAuxRegister *next;
+ };
+
+-struct arcExtMap
++struct arcExtMap
+ {
+ struct ExtAuxRegister *auxRegisters;
+ struct ExtInstruction *instructions[NUM_EXT_INST];
+--- a/opcodes/arm-dis.c
++++ b/opcodes/arm-dis.c
+@@ -125,7 +125,7 @@ struct opcode16
+ %<bitfield>'c print specified char iff bitfield is all ones
+ %<bitfield>`c print specified char iff bitfield is all zeroes
+ %<bitfield>?ab... select from array of values in big endian order
+-
++
+ %L print as an iWMMXt N/M width field.
+ %Z print the Immediate of a WSHUFH instruction.
+ %l like 'A' except use byte offsets for 'B' & 'H'
+@@ -920,7 +920,7 @@ static const struct opcode32 coprocessor_opcodes[] =
+ %<bitfield>Sn print byte scaled width limited by n
+ %<bitfield>Tn print short scaled width limited by n
+ %<bitfield>Un print long scaled width limited by n
+-
++
+ %<bitfield>'c print specified char iff bitfield is all ones
+ %<bitfield>`c print specified char iff bitfield is all zeroes
+ %<bitfield>?ab... select from array of values in big endian order. */
+@@ -1539,10 +1539,10 @@ static const struct opcode32 neon_opcodes[] =
+ %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
+ %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
+ %<bitfield>d print the bitfield in decimal
+- %<bitfield>W print the bitfield plus one in decimal
++ %<bitfield>W print the bitfield plus one in decimal
+ %<bitfield>x print the bitfield in hex
+ %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
+-
++
+ %<bitfield>'c print specified char iff bitfield is all ones
+ %<bitfield>`c print specified char iff bitfield is all zeroes
+ %<bitfield>?ab... select from array of values in big endian order
+@@ -3084,8 +3084,8 @@ arm_decode_bitfield (const char *ptr,
+ {
+ unsigned long value = 0;
+ int width = 0;
+-
+- do
++
++ do
+ {
+ int start, end;
+ int bits;
+@@ -3310,7 +3310,7 @@ print_insn_coprocessor (bfd_vma pc,
+ func (stream, "\t; ");
+ /* For unaligned PCs, apply off-by-alignment
+ correction. */
+- info->print_address_func (offset + pc
++ info->print_address_func (offset + pc
+ + info->bytes_per_chunk * 2
+ - (pc & 3),
+ info);
+@@ -3897,7 +3897,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
+ else
+ return FALSE;
+ }
+-
++
+ for (insn = neon_opcodes; insn->assembler; insn++)
+ {
+ if ((given & insn->mask) == insn->value)
+@@ -3928,7 +3928,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
+
+ case 'A':
+ {
+- static const unsigned char enc[16] =
++ static const unsigned char enc[16] =
+ {
+ 0x4, 0x14, /* st4 0,1 */
+ 0x4, /* st1 2 */
+@@ -3950,7 +3950,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
+ int n = enc[type] & 0xf;
+ int stride = (enc[type] >> 4) + 1;
+ int ix;
+-
++
+ func (stream, "{");
+ if (stride > 1)
+ for (ix = 0; ix != n; ix++)
+@@ -3969,7 +3969,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
+ func (stream, ", %s", arm_regnames[rm]);
+ }
+ break;
+-
++
+ case 'B':
+ {
+ int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
+@@ -3985,7 +3985,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
+
+ if (length > 1 && size > 0)
+ stride = (idx_align & (1 << size)) ? 2 : 1;
+-
++
+ switch (length)
+ {
+ case 1:
+@@ -4002,19 +4002,19 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
+ }
+ }
+ break;
+-
++
+ case 2:
+ if (size == 2 && (idx_align & 2) != 0)
+ return FALSE;
+ align = (idx_align & 1) ? 16 << size : 0;
+ break;
+-
++
+ case 3:
+ if ((size == 2 && (idx_align & 3) != 0)
+ || (idx_align & 1) != 0)
+ return FALSE;
+ break;
+-
++
+ case 4:
+ if (size == 2)
+ {
+@@ -4025,11 +4025,11 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
+ else
+ align = (idx_align & 1) ? 32 << size : 0;
+ break;
+-
++
+ default:
+ abort ();
+ }
+-
++
+ func (stream, "{");
+ for (i = 0; i < length; i++)
+ func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
+@@ -4044,7 +4044,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
+ func (stream, ", %s", arm_regnames[rm]);
+ }
+ break;
+-
++
+ case 'C':
+ {
+ int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
+@@ -4056,12 +4056,12 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
+ int n = type + 1;
+ int stride = ((given >> 5) & 0x1);
+ int ix;
+-
++
+ if (stride && (n == 1))
+ n++;
+ else
+ stride++;
+-
++
+ func (stream, "{");
+ if (stride > 1)
+ for (ix = 0; ix != n; ix++)
+@@ -4088,18 +4088,18 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
+ func (stream, ", %s", arm_regnames[rm]);
+ }
+ break;
+-
++
+ case 'D':
+ {
+ int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
+ int size = (given >> 20) & 3;
+ int reg = raw_reg & ((4 << size) - 1);
+ int ix = raw_reg >> size >> 2;
+-
++
+ func (stream, "d%d[%d]", reg, ix);
+ }
+ break;
+-
++
+ case 'E':
+ /* Neon encoded constant for mov, mvn, vorr, vbic. */
+ {
+@@ -4110,11 +4110,11 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
+ unsigned shift;
+ int size = 0;
+ int isfloat = 0;
+-
++
+ bits |= ((given >> 24) & 1) << 7;
+ bits |= ((given >> 16) & 7) << 4;
+ bits |= ((given >> 0) & 15) << 0;
+-
++
+ if (cmode < 8)
+ {
+ shift = (cmode >> 1) & 3;
+@@ -4141,7 +4141,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
+ /* Bit replication into bytes. */
+ int ix;
+ unsigned long mask;
+-
++
+ value = 0;
+ hival = 0;
+ for (ix = 7; ix >= 0; ix--)
+@@ -4165,7 +4165,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
+ {
+ /* Floating point encoding. */
+ int tmp;
+-
++
+ value = (unsigned long) (bits & 0x7f) << 19;
+ value |= (unsigned long) (bits & 0x80) << 24;
+ tmp = bits & 0x40 ? 0x3c : 0x40;
+@@ -4185,7 +4185,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
+ case 8:
+ func (stream, "#%ld\t; 0x%.2lx", value, value);
+ break;
+-
++
+ case 16:
+ func (stream, "#%ld\t; 0x%.4lx", value, value);
+ break;
+@@ -4195,24 +4195,24 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
+ {
+ unsigned char valbytes[4];
+ double fvalue;
+-
++
+ /* Do this a byte at a time so we don't have to
+ worry about the host's endianness. */
+ valbytes[0] = value & 0xff;
+ valbytes[1] = (value >> 8) & 0xff;
+ valbytes[2] = (value >> 16) & 0xff;
+ valbytes[3] = (value >> 24) & 0xff;
+-
+- floatformat_to_double
++
++ floatformat_to_double
+ (& floatformat_ieee_single_little, valbytes,
+ & fvalue);
+-
++
+ func (stream, "#%.7g\t; 0x%.8lx", fvalue,
+ value);
+ }
+ else
+ func (stream, "#%ld\t; 0x%.8lx",
+- (long) (((value & 0x80000000L) != 0)
++ (long) (((value & 0x80000000L) != 0)
+ ? value | ~0xffffffffL : value),
+ value);
+ break;
+@@ -4220,18 +4220,18 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
+ case 64:
+ func (stream, "#0x%.8lx%.8lx", hival, value);
+ break;
+-
++
+ default:
+ abort ();
+ }
+ }
+ break;
+-
++
+ case 'F':
+ {
+ int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
+ int num = (given >> 8) & 0x3;
+-
++
+ if (!num)
+ func (stream, "{d%d}", regno);
+ else if (num + regno >= 32)
+@@ -4249,7 +4249,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
+ unsigned long value;
+
+ c = arm_decode_bitfield (c, given, &value, &width);
+-
++
+ switch (*c)
+ {
+ case 'r':
+@@ -4262,7 +4262,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
+ case 'e':
+ func (stream, "%ld", (1ul << width) - value);
+ break;
+-
++
+ case 'S':
+ case 'T':
+ case 'U':
+@@ -4302,7 +4302,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
+ else
+ func (stream, "q%ld", value >> 1);
+ break;
+-
++
+ case '`':
+ c++;
+ if (value == 0)
+@@ -4345,20 +4345,20 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
+
+ /* Return the name of a v7A special register. */
+
+-static const char *
++static const char *
+ banked_regname (unsigned reg)
+ {
+ switch (reg)
+ {
+ case 15: return "CPSR";
+- case 32: return "R8_usr";
++ case 32: return "R8_usr";
+ case 33: return "R9_usr";
+ case 34: return "R10_usr";
+ case 35: return "R11_usr";
+ case 36: return "R12_usr";
+ case 37: return "SP_usr";
+ case 38: return "LR_usr";
+- case 40: return "R8_fiq";
++ case 40: return "R8_fiq";
+ case 41: return "R9_fiq";
+ case 42: return "R10_fiq";
+ case 43: return "R11_fiq";
+@@ -4739,7 +4739,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
+ }
+ else
+ {
+- func (stream, "%cPSR_",
++ func (stream, "%cPSR_",
+ (given & 0x00400000) ? 'S' : 'C');
+ if (given & 0x80000)
+ func (stream, "f");
+@@ -4753,7 +4753,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
+ break;
+
+ case 'U':
+- if ((given & 0xf0) == 0x60)
++ if ((given & 0xf0) == 0x60)
+ {
+ switch (given & 0xf)
+ {
+@@ -4762,8 +4762,8 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
+ func (stream, "#%d", (int) given & 0xf);
+ break;
+ }
+- }
+- else
++ }
++ else
+ {
+ const char * opt = data_barrier_option (given & 0xf);
+ if (opt != NULL)
+@@ -4780,7 +4780,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
+ unsigned long value;
+
+ c = arm_decode_bitfield (c, given, &value, &width);
+-
++
+ switch (*c)
+ {
+ case 'R':
+@@ -5317,7 +5317,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
+ value_in_comment = imm;
+ }
+ break;
+-
++
+ case 'J':
+ {
+ unsigned int imm = 0;
+@@ -5647,7 +5647,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
+ break;
+
+ case 'U':
+- if ((given & 0xf0) == 0x60)
++ if ((given & 0xf0) == 0x60)
+ {
+ switch (given & 0xf)
+ {
+@@ -5657,7 +5657,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
+ break;
+ }
+ }
+- else
++ else
+ {
+ const char * opt = data_barrier_option (given & 0xf);
+ if (opt != NULL)
+@@ -5688,7 +5688,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
+ sysm |= (given & 0x30);
+ sysm |= (given & 0x00100000) >> 14;
+ name = banked_regname (sysm);
+-
++
+ if (name != NULL)
+ func (stream, "%s", name);
+ else
+@@ -5727,7 +5727,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
+ unsigned long val;
+
+ c = arm_decode_bitfield (c, given, &val, &width);
+-
++
+ switch (*c)
+ {
+ case 'd':
+@@ -5766,7 +5766,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
+ if (val == ((1ul << width) - 1))
+ func (stream, "%c", *c);
+ break;
+-
++
+ case '`':
+ c++;
+ if (val == 0)
+@@ -5777,7 +5777,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
+ func (stream, "%c", c[(1 << width) - (int) val]);
+ c += 1 << width;
+ break;
+-
++
+ case 'x':
+ func (stream, "0x%lx", val & 0xffffffffUL);
+ break;
+@@ -5855,7 +5855,7 @@ arm_symbol_is_valid (asymbol * sym,
+ struct disassemble_info * info ATTRIBUTE_UNUSED)
+ {
+ const char * name;
+-
++
+ if (sym == NULL)
+ return FALSE;
+
+@@ -5918,7 +5918,7 @@ parse_disassembler_options (char *options)
+ ++ options;
+ /* Skip forward past seperators. */
+ while (ISSPACE (*options) || (*options == ','))
+- ++ options;
++ ++ options;
+ }
+ }
+
+@@ -6151,7 +6151,7 @@ print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
+ if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
+ /* If the user did not use the -m command line switch then default to
+ disassembling all types of ARM instruction.
+-
++
+ The info->mach value has to be ignored as this will be based on
+ the default archictecture for the target and/or hints in the notes
+ section, but it will never be greater than the current largest arm
+#--- a/opcodes/avr-dis.c
+#+++ b/opcodes/avr-dis.c
+#@@ -62,7 +62,7 @@ avr_operand (unsigned int insn, unsigned int insn2, unsigned int pc, int constra
+# insn = (insn & 0xf) | ((insn & 0x0200) >> 5); /* Source register. */
+# else
+# insn = (insn & 0x01f0) >> 4; /* Destination register. */
+#-
+#+
+# sprintf (buf, "r%d", insn);
+# break;
+#
+#@@ -72,11 +72,11 @@ avr_operand (unsigned int insn, unsigned int insn2, unsigned int pc, int constra
+# else
+# sprintf (buf, "r%d", 16 + ((insn & 0xf0) >> 4));
+# break;
+#-
+#+
+# case 'w':
+# sprintf (buf, "r%d", 24 + ((insn & 0x30) >> 3));
+# break;
+#-
+#+
+# case 'a':
+# if (regs)
+# sprintf (buf, "r%d", 16 + (insn & 7));
+#@@ -138,11 +138,11 @@ avr_operand (unsigned int insn, unsigned int insn2, unsigned int pc, int constra
+# case 'b':
+# {
+# unsigned int x;
+#-
+#+
+# x = (insn & 7);
+# x |= (insn >> 7) & (3 << 3);
+# x |= (insn >> 8) & (1 << 5);
+#-
+#+
+# if (insn & 0x8)
+# *buf++ = 'Y';
+# else
+#@@ -151,17 +151,17 @@ avr_operand (unsigned int insn, unsigned int insn2, unsigned int pc, int constra
+# sprintf (comment, "0x%02x", x);
+# }
+# break;
+#-
+#+
+# case 'h':
+# *sym = 1;
+# *sym_addr = ((((insn & 1) | ((insn & 0x1f0) >> 3)) << 16) | insn2) * 2;
+# /* See PR binutils/2454. Ideally we would like to display the hex
+# value of the address only once, but this would mean recoding
+# objdump_print_address() which would affect many targets. */
+#- sprintf (buf, "%#lx", (unsigned long) *sym_addr);
+#+ sprintf (buf, "%#lx", (unsigned long) *sym_addr);
+# strcpy (comment, comment_start);
+# break;
+#-
+#+
+# case 'L':
+# {
+# int rel_addr = (((insn & 0xfff) ^ 0x800) - 0x800) * 2;
+#@@ -197,7 +197,7 @@ avr_operand (unsigned int insn, unsigned int insn2, unsigned int pc, int constra
+# sprintf (buf, "%d", val);
+# }
+# break;
+#-
+#+
+# case 'M':
+# sprintf (buf, "0x%02X", ((insn & 0xf00) >> 4) | (insn & 0xf));
+# sprintf (comment, "%d", ((insn & 0xf00) >> 4) | (insn & 0xf));
+#@@ -208,7 +208,7 @@ avr_operand (unsigned int insn, unsigned int insn2, unsigned int pc, int constra
+# fprintf (stderr, _("Internal disassembler error"));
+# ok = 0;
+# break;
+#-
+#+
+# case 'K':
+# {
+# unsigned int x;
+#@@ -218,15 +218,15 @@ avr_operand (unsigned int insn, unsigned int insn2, unsigned int pc, int constra
+# sprintf (comment, "%d", x);
+# }
+# break;
+#-
+#+
+# case 's':
+# sprintf (buf, "%d", insn & 7);
+# break;
+#-
+#+
+# case 'S':
+# sprintf (buf, "%d", (insn >> 4) & 7);
+# break;
+#-
+#+
+# case 'P':
+# {
+# unsigned int x;
+#@@ -241,21 +241,21 @@ avr_operand (unsigned int insn, unsigned int insn2, unsigned int pc, int constra
+# case 'p':
+# {
+# unsigned int x;
+#-
+#+
+# x = (insn >> 3) & 0x1f;
+# sprintf (buf, "0x%02x", x);
+# sprintf (comment, "%d", x);
+# }
+# break;
+#-
+#+
+# case 'E':
+# sprintf (buf, "%d", (insn >> 4) & 15);
+# break;
+#-
+#+
+# case '?':
+# *buf = '\0';
+# break;
+#-
+#+
+# default:
+# sprintf (buf, "??");
+# fprintf (stderr, _("unknown constraint `%c'"), constraint);
+#@@ -309,7 +309,7 @@ print_insn_avr (bfd_vma addr, disassemble_info *info)
+# comment_start = " ";
+#
+# nopcodes = sizeof (avr_opcodes) / sizeof (struct avr_opcodes_s);
+#-
+#+
+# avr_bin_masks = xmalloc (nopcodes * sizeof (unsigned int));
+#
+# for (opcode = avr_opcodes, maskptr = avr_bin_masks;
+#@@ -319,7 +319,7 @@ print_insn_avr (bfd_vma addr, disassemble_info *info)
+# char * s;
+# unsigned int bin = 0;
+# unsigned int mask = 0;
+#-
+#+
+# for (s = opcode->opcode; *s; ++s)
+# {
+# bin <<= 1;
+#@@ -336,7 +336,7 @@ print_insn_avr (bfd_vma addr, disassemble_info *info)
+# }
+#
+# insn = avrdis_opcode (addr, info);
+#-
+#+
+# for (opcode = avr_opcodes, maskptr = avr_bin_masks;
+# opcode->name;
+# opcode++, maskptr++)
+#@@ -346,7 +346,7 @@ print_insn_avr (bfd_vma addr, disassemble_info *info)
+# if ((insn & *maskptr) == opcode->bin_opcode)
+# break;
+# }
+#-
+#+
+# /* Special case: disassemble `ldd r,b+0' as `ld r,b', and
+# `std b+0,r' as `st b,r' (next entry in the table). */
+#
+--- a/opcodes/cgen-asm.c
++++ b/opcodes/cgen-asm.c
+@@ -212,7 +212,7 @@ cgen_parse_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ character of the suffix ('.') is special. */
+ if (*p)
+ ++p;
+-
++
+ /* Allow letters, digits, and any special characters. */
+ while (((p - start) < (int) sizeof (buf))
+ && *p
+--- a/opcodes/cgen-asm.in
++++ b/opcodes/cgen-asm.in
+@@ -60,9 +60,9 @@ static const char * parse_insn_normal
+
+ Returns NULL for success, an error message for failure. */
+
+-char *
++char *
+ @arch@_cgen_build_insn_regex (CGEN_INSN *insn)
+-{
++{
+ CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
+ const char *mnem = CGEN_INSN_MNEMONIC (insn);
+ char rxbuf[CGEN_MAX_RX_ELEMENTS];
+@@ -101,18 +101,18 @@ char *
+ /* Copy any remaining literals from the syntax string into the rx. */
+ for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn)
+ {
+- if (CGEN_SYNTAX_CHAR_P (* syn))
++ if (CGEN_SYNTAX_CHAR_P (* syn))
+ {
+ char c = CGEN_SYNTAX_CHAR (* syn);
+
+- switch (c)
++ switch (c)
+ {
+ /* Escape any regex metacharacters in the syntax. */
+- case '.': case '[': case '\\':
+- case '*': case '^': case '$':
++ case '.': case '[': case '\\':
++ case '*': case '^': case '$':
+
+ #ifdef CGEN_ESCAPE_EXTENDED_REGEX
+- case '?': case '{': case '}':
++ case '?': case '{': case '}':
+ case '(': case ')': case '*':
+ case '|': case '+': case ']':
+ #endif
+@@ -142,20 +142,20 @@ char *
+ }
+
+ /* Trailing whitespace ok. */
+- * rx++ = '[';
+- * rx++ = ' ';
+- * rx++ = '\t';
+- * rx++ = ']';
+- * rx++ = '*';
++ * rx++ = '[';
++ * rx++ = ' ';
++ * rx++ = '\t';
++ * rx++ = ']';
++ * rx++ = '*';
+
+ /* But anchor it after that. */
+- * rx++ = '$';
++ * rx++ = '$';
+ * rx = '\0';
+
+ CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t));
+ reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB);
+
+- if (reg_err == 0)
++ if (reg_err == 0)
+ return NULL;
+ else
+ {
+@@ -354,7 +354,7 @@ const CGEN_INSN *
+ const CGEN_INSN *insn = ilist->insn;
+ recognized_mnemonic = 1;
+
+-#ifdef CGEN_VALIDATE_INSN_SUPPORTED
++#ifdef CGEN_VALIDATE_INSN_SUPPORTED
+ /* Not usually needed as unsupported opcodes
+ shouldn't be in the hash lists. */
+ /* Is this insn supported by the selected cpu? */
+@@ -414,7 +414,7 @@ const CGEN_INSN *
+ if (strlen (start) > 50)
+ /* xgettext:c-format */
+ sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start);
+- else
++ else
+ /* xgettext:c-format */
+ sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start);
+ }
+@@ -423,11 +423,11 @@ const CGEN_INSN *
+ if (strlen (start) > 50)
+ /* xgettext:c-format */
+ sprintf (errbuf, _("bad instruction `%.50s...'"), start);
+- else
++ else
+ /* xgettext:c-format */
+ sprintf (errbuf, _("bad instruction `%.50s'"), start);
+ }
+-
++
+ *errmsg = errbuf;
+ return NULL;
+ }
+--- a/opcodes/cgen-dis.c
++++ b/opcodes/cgen-dis.c
+@@ -49,7 +49,7 @@ count_decodable_bits (const CGEN_INSN *insn)
+ return bits;
+ }
+
+-/* Add an instruction to the hash chain. */
++/* Add an instruction to the hash chain. */
+ static void
+ add_insn_to_hash_chain (CGEN_INSN_LIST *hentbuf,
+ const CGEN_INSN *insn,
+--- a/opcodes/cgen-dis.in
++++ b/opcodes/cgen-dis.in
+@@ -231,7 +231,7 @@ print_insn (CGEN_CPU_DESC cd,
+ int length;
+ unsigned long insn_value_cropped;
+
+-#ifdef CGEN_VALIDATE_INSN_SUPPORTED
++#ifdef CGEN_VALIDATE_INSN_SUPPORTED
+ /* Not needed as insn shouldn't be in hash lists if not supported. */
+ /* Supported by this cpu? */
+ if (! @arch@_cgen_insn_supported (cd, insn))
+@@ -249,7 +249,7 @@ print_insn (CGEN_CPU_DESC cd,
+ relevant part from the buffer. */
+ if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
+ (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
+- insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
++ insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
+ info->endian == BFD_ENDIAN_BIG);
+ else
+ insn_value_cropped = insn_value;
+@@ -368,7 +368,7 @@ print_insn_@arch@ (bfd_vma pc, disassemble_info *info)
+ arch = info->arch;
+ if (arch == bfd_arch_unknown)
+ arch = CGEN_BFD_ARCH;
+-
++
+ /* There's no standard way to compute the machine or isa number
+ so we leave it to the target. */
+ #ifdef CGEN_COMPUTE_MACH
+@@ -409,7 +409,7 @@ print_insn_@arch@ (bfd_vma pc, disassemble_info *info)
+ break;
+ }
+ }
+- }
++ }
+
+ /* If we haven't initialized yet, initialize the opcode table. */
+ if (! cd)
+--- a/opcodes/cgen-ibld.in
++++ b/opcodes/cgen-ibld.in
+@@ -154,7 +154,7 @@ insert_normal (CGEN_CPU_DESC cd,
+ {
+ long minval = - (1L << (length - 1));
+ unsigned long maxval = mask;
+-
++
+ if ((value > 0 && (unsigned long) value > maxval)
+ || value < minval)
+ {
+@@ -192,7 +192,7 @@ insert_normal (CGEN_CPU_DESC cd,
+ {
+ long minval = - (1L << (length - 1));
+ long maxval = (1L << (length - 1)) - 1;
+-
++
+ if (value < minval || value > maxval)
+ {
+ sprintf
+--- a/opcodes/cgen-opc.c
++++ b/opcodes/cgen-opc.c
+@@ -127,7 +127,7 @@ cgen_keyword_add (CGEN_KEYWORD *kt, CGEN_KEYWORD_ENTRY *ke)
+ && ! strchr (kt->nonalpha_chars, ke->name[i]))
+ {
+ size_t idx = strlen (kt->nonalpha_chars);
+-
++
+ /* If you hit this limit, please don't just
+ increase the size of the field, instead
+ look for a better algorithm. */
+@@ -369,7 +369,7 @@ cgen_get_insn_value (CGEN_CPU_DESC cd, unsigned char *buf, int length)
+ segments, and endian-convert them, one at a time. */
+ int i;
+
+- /* Enforce divisibility. */
++ /* Enforce divisibility. */
+ if ((length % insn_chunk_bitsize) != 0)
+ abort ();
+
+@@ -408,7 +408,7 @@ cgen_put_insn_value (CGEN_CPU_DESC cd,
+ segments, and endian-convert them, one at a time. */
+ int i;
+
+- /* Enforce divisibility. */
++ /* Enforce divisibility. */
+ if ((length % insn_chunk_bitsize) != 0)
+ abort ();
+
+--- a/opcodes/cgen.sh
++++ b/opcodes/cgen.sh
+@@ -26,7 +26,7 @@
+ # cgen.sh action srcdir cgen cgendir cgenflags arch prefix \
+ # arch-file opc-file options [extrafiles]
+ #
+-# ACTION is currently always "opcodes". It exists to be consistent with the
++# ACTION is currently always "opcodes". It exists to be consistent with the
+ # simulator.
+ # ARCH is the name of the architecture.
+ # It is substituted into @arch@ and @ARCH@ in the generated files.
+#--- a/opcodes/configure.ac
+#+++ b/opcodes/configure.ac
+#@@ -6,12 +6,12 @@ dnl This file is free software; you can redistribute it and/or modify
+# dnl it under the terms of the GNU General Public License as published by
+# dnl the Free Software Foundation; either version 3 of the License, or
+# dnl (at your option) any later version.
+#-dnl
+#+dnl
+# dnl This program is distributed in the hope that it will be useful,
+# dnl but WITHOUT ANY WARRANTY; without even the implied warranty of
+# dnl MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# dnl GNU General Public License for more details.
+#-dnl
+#+dnl
+# dnl You should have received a copy of the GNU General Public License
+# dnl along with this program; see the file COPYING3. If not see
+# dnl <http://www.gnu.org/licenses/>.
+#@@ -234,7 +234,7 @@ do
+# . $srcdir/../bfd/config.bfd
+# selarchs="$selarchs $targ_archs"
+# fi
+#-done
+#+done
+#
+# # Utility var, documents generic cgen support files.
+#
+--- a/opcodes/configure.com
++++ b/opcodes/configure.com
+@@ -12,12 +12,12 @@ $! This file is free software; you can redistribute it and/or modify
+ $! it under the terms of the GNU General Public License as published by
+ $! the Free Software Foundation; either version 3 of the License, or
+ $! (at your option) any later version.
+-$!
++$!
+ $! This program is distributed in the hope that it will be useful,
+ $! but WITHOUT ANY WARRANTY; without even the implied warranty of
+ $! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ $! GNU General Public License for more details.
+-$!
++$!
+ $! You should have received a copy of the GNU General Public License
+ $! along with this program; see the file COPYING3. If not see
+ $! <http://www.gnu.org/licenses/>.
+--- a/opcodes/cr16-dis.c
++++ b/opcodes/cr16-dis.c
+@@ -358,7 +358,7 @@ make_argument (argument * a, int start_bits)
+ switch (a->type)
+ {
+ case arg_r:
+- p = makelongparameter (cr16_allWords,
++ p = makelongparameter (cr16_allWords,
+ inst_bit_size - (start_bits + a->size),
+ inst_bit_size - start_bits);
+ a->r = p.val;
+@@ -386,7 +386,7 @@ make_argument (argument * a, int start_bits)
+ break;
+
+ case arg_ic:
+- p = makelongparameter (cr16_allWords,
++ p = makelongparameter (cr16_allWords,
+ inst_bit_size - (start_bits + a->size),
+ inst_bit_size - start_bits);
+ a->constant = p.val;
+@@ -466,7 +466,7 @@ make_argument (argument * a, int start_bits)
+ }
+ else if (instruction->size == 2)
+ {
+- p = makelongparameter (cr16_allWords, inst_bit_size - 16,
++ p = makelongparameter (cr16_allWords, inst_bit_size - 16,
+ inst_bit_size);
+ a->constant = p.val;
+ }
+@@ -795,7 +795,7 @@ get_words_at_PC (bfd_vma memaddr, struct disassemble_info *info)
+ for (i = 0, mem = memaddr; i < 3; i++, mem += 2)
+ cr16_words[i] = get_word_at_PC (mem, info);
+
+- cr16_allWords = ((ULONGLONG) cr16_words[0] << 32)
++ cr16_allWords = ((ULONGLONG) cr16_words[0] << 32)
+ + ((unsigned long) cr16_words[1] << 16) + cr16_words[2];
+ }
+
+--- a/opcodes/cris-dis.c
++++ b/opcodes/cris-dis.c
+@@ -813,7 +813,7 @@ print_with_operands (const struct cris_opcode *opcodep,
+ *tp++ = 'c';
+ *tp++ = 'r';
+ break;
+-
++
+ case '[':
+ case ']':
+ case ',':
+--- a/opcodes/crx-dis.c
++++ b/opcodes/crx-dis.c
+@@ -60,9 +60,9 @@ cinv_entry;
+ /* CRX 'cinv' options. */
+ const cinv_entry crx_cinvs[] =
+ {
+- {"[i]", 2}, {"[i,u]", 3}, {"[d]", 4}, {"[d,u]", 5},
+- {"[d,i]", 6}, {"[d,i,u]", 7}, {"[b]", 8},
+- {"[b,i]", 10}, {"[b,i,u]", 11}, {"[b,d]", 12},
++ {"[i]", 2}, {"[i,u]", 3}, {"[d]", 4}, {"[d,u]", 5},
++ {"[d,i]", 6}, {"[d,i,u]", 7}, {"[b]", 8},
++ {"[b,i]", 10}, {"[b,i,u]", 11}, {"[b,d]", 12},
+ {"[b,d,u]", 13}, {"[b,d,i]", 14}, {"[b,d,i,u]", 15}
+ };
+
+@@ -76,7 +76,7 @@ typedef enum REG_ARG_TYPE
+ /* CO-Processor register (c<N>). */
+ COP_ARG,
+ /* CO-Processor special register (cs<N>). */
+- COPS_ARG
++ COPS_ARG
+ }
+ REG_ARG_TYPE;
+
+@@ -534,8 +534,8 @@ print_arg (argument *a, bfd_vma memaddr, struct disassemble_info *info)
+
+ else if (INST_HAS_REG_LIST)
+ {
+- REG_ARG_TYPE reg_arg_type = IS_INSN_TYPE (COP_REG_INS) ?
+- COP_ARG : IS_INSN_TYPE (COPS_REG_INS) ?
++ REG_ARG_TYPE reg_arg_type = IS_INSN_TYPE (COP_REG_INS) ?
++ COP_ARG : IS_INSN_TYPE (COPS_REG_INS) ?
+ COPS_ARG : (instruction->flags & USER_REG) ?
+ USER_REG_ARG : REG_ARG;
+
+#--- a/opcodes/d10v-opc.c
+#+++ b/opcodes/d10v-opc.c
+#@@ -89,7 +89,7 @@ const struct pd_reg d10v_predefined_registers[] =
+# { "sp", NULL, OPERAND_SP|(OPERAND_GPR+15) },
+# };
+#
+#-int
+#+int
+# d10v_reg_name_cnt (void)
+# {
+# return (sizeof(d10v_predefined_registers) / sizeof(struct pd_reg));
+--- a/opcodes/d30v-opc.c
++++ b/opcodes/d30v-opc.c
+@@ -194,7 +194,7 @@ const struct pd_reg pre_defined_registers[] =
+ { "va", NULL, OPERAND_FLAG + 6 },
+ };
+
+-int
++int
+ reg_name_cnt (void)
+ {
+ return sizeof (pre_defined_registers) / sizeof (struct pd_reg);
+--- a/opcodes/dis-buf.c
++++ b/opcodes/dis-buf.c
+@@ -33,7 +33,7 @@ buffer_read_memory (bfd_vma memaddr,
+ {
+ unsigned int opb = info->octets_per_byte;
+ unsigned int end_addr_offset = length / opb;
+- unsigned int max_addr_offset = info->buffer_length / opb;
++ unsigned int max_addr_offset = info->buffer_length / opb;
+ unsigned int octets = (memaddr - info->buffer_vma) * opb;
+
+ if (memaddr < info->buffer_vma
+--- a/opcodes/dlx-dis.c
++++ b/opcodes/dlx-dis.c
+@@ -295,7 +295,7 @@ dlx_aluI_type (struct disassemble_info* info)
+ { OPC(SGTUIOP), "sgtui" }, /* Store word. */
+ { OPC(SLEUIOP), "sleui" }, /* Store word. */
+ { OPC(SGEUIOP), "sgeui" }, /* Store word. */
+-#if 0
++#if 0
+ { OPC(MVTSOP), "mvts" }, /* Store word. */
+ { OPC(MVFSOP), "mvfs" }, /* Store word. */
+ #endif
+--- a/opcodes/epiphany-asm.c
++++ b/opcodes/epiphany-asm.c
+@@ -458,7 +458,7 @@ epiphany_cgen_parse_operand (CGEN_CPU_DESC cd,
+ return errmsg;
+ }
+
+-cgen_parse_fn * const epiphany_cgen_parse_handlers[] =
++cgen_parse_fn * const epiphany_cgen_parse_handlers[] =
+ {
+ parse_insn_normal,
+ };
+@@ -488,9 +488,9 @@ CGEN_ASM_INIT_HOOK
+
+ Returns NULL for success, an error message for failure. */
+
+-char *
++char *
+ epiphany_cgen_build_insn_regex (CGEN_INSN *insn)
+-{
++{
+ CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
+ const char *mnem = CGEN_INSN_MNEMONIC (insn);
+ char rxbuf[CGEN_MAX_RX_ELEMENTS];
+@@ -529,18 +529,18 @@ epiphany_cgen_build_insn_regex (CGEN_INSN *insn)
+ /* Copy any remaining literals from the syntax string into the rx. */
+ for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn)
+ {
+- if (CGEN_SYNTAX_CHAR_P (* syn))
++ if (CGEN_SYNTAX_CHAR_P (* syn))
+ {
+ char c = CGEN_SYNTAX_CHAR (* syn);
+
+- switch (c)
++ switch (c)
+ {
+ /* Escape any regex metacharacters in the syntax. */
+- case '.': case '[': case '\\':
+- case '*': case '^': case '$':
++ case '.': case '[': case '\\':
++ case '*': case '^': case '$':
+
+ #ifdef CGEN_ESCAPE_EXTENDED_REGEX
+- case '?': case '{': case '}':
++ case '?': case '{': case '}':
+ case '(': case ')': case '*':
+ case '|': case '+': case ']':
+ #endif
+@@ -570,20 +570,20 @@ epiphany_cgen_build_insn_regex (CGEN_INSN *insn)
+ }
+
+ /* Trailing whitespace ok. */
+- * rx++ = '[';
+- * rx++ = ' ';
+- * rx++ = '\t';
+- * rx++ = ']';
+- * rx++ = '*';
++ * rx++ = '[';
++ * rx++ = ' ';
++ * rx++ = '\t';
++ * rx++ = ']';
++ * rx++ = '*';
+
+ /* But anchor it after that. */
+- * rx++ = '$';
++ * rx++ = '$';
+ * rx = '\0';
+
+ CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t));
+ reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB);
+
+- if (reg_err == 0)
++ if (reg_err == 0)
+ return NULL;
+ else
+ {
+@@ -782,7 +782,7 @@ epiphany_cgen_assemble_insn (CGEN_CPU_DESC cd,
+ const CGEN_INSN *insn = ilist->insn;
+ recognized_mnemonic = 1;
+
+-#ifdef CGEN_VALIDATE_INSN_SUPPORTED
++#ifdef CGEN_VALIDATE_INSN_SUPPORTED
+ /* Not usually needed as unsupported opcodes
+ shouldn't be in the hash lists. */
+ /* Is this insn supported by the selected cpu? */
+@@ -842,7 +842,7 @@ epiphany_cgen_assemble_insn (CGEN_CPU_DESC cd,
+ if (strlen (start) > 50)
+ /* xgettext:c-format */
+ sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start);
+- else
++ else
+ /* xgettext:c-format */
+ sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start);
+ }
+@@ -851,11 +851,11 @@ epiphany_cgen_assemble_insn (CGEN_CPU_DESC cd,
+ if (strlen (start) > 50)
+ /* xgettext:c-format */
+ sprintf (errbuf, _("bad instruction `%.50s...'"), start);
+- else
++ else
+ /* xgettext:c-format */
+ sprintf (errbuf, _("bad instruction `%.50s'"), start);
+ }
+-
++
+ *errmsg = errbuf;
+ return NULL;
+ }
+--- a/opcodes/epiphany-desc.c
++++ b/opcodes/epiphany-desc.c
+@@ -534,367 +534,367 @@ const CGEN_OPERAND epiphany_cgen_operand_table[] =
+ {
+ /* pc: program counter */
+ { "pc", EPIPHANY_OPERAND_PC, HW_H_PC, 0, 0,
+- { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_NIL] } },
++ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_NIL] } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* zbit: integer zero bit */
+ { "zbit", EPIPHANY_OPERAND_ZBIT, HW_H_ZBIT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* nbit: integer neg bit */
+ { "nbit", EPIPHANY_OPERAND_NBIT, HW_H_NBIT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* cbit: integer carry bit */
+ { "cbit", EPIPHANY_OPERAND_CBIT, HW_H_CBIT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* vbit: integer overflow bit */
+ { "vbit", EPIPHANY_OPERAND_VBIT, HW_H_VBIT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* bzbit: floating point zero bit */
+ { "bzbit", EPIPHANY_OPERAND_BZBIT, HW_H_BZBIT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* bnbit: floating point neg bit */
+ { "bnbit", EPIPHANY_OPERAND_BNBIT, HW_H_BNBIT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* bvbit: floating point ovfl bit */
+ { "bvbit", EPIPHANY_OPERAND_BVBIT, HW_H_BVBIT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* bcbit: floating point carry bit */
+ { "bcbit", EPIPHANY_OPERAND_BCBIT, HW_H_BCBIT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* bubit: floating point underfl bit */
+ { "bubit", EPIPHANY_OPERAND_BUBIT, HW_H_BUBIT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* bibit: floating point invalid bit */
+ { "bibit", EPIPHANY_OPERAND_BIBIT, HW_H_BIBIT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* vsbit: integer overflow sticky */
+ { "vsbit", EPIPHANY_OPERAND_VSBIT, HW_H_VSBIT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* bvsbit: floating point overflow sticky */
+ { "bvsbit", EPIPHANY_OPERAND_BVSBIT, HW_H_BVSBIT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* bisbit: floating point invalid sticky */
+ { "bisbit", EPIPHANY_OPERAND_BISBIT, HW_H_BISBIT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* busbit: floating point underflow sticky */
+ { "busbit", EPIPHANY_OPERAND_BUSBIT, HW_H_BUSBIT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* expcause0bit: exceprion cause bit0 */
+ { "expcause0bit", EPIPHANY_OPERAND_EXPCAUSE0BIT, HW_H_EXPCAUSE0BIT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* expcause1bit: exceprion cause bit1 */
+ { "expcause1bit", EPIPHANY_OPERAND_EXPCAUSE1BIT, HW_H_EXPCAUSE1BIT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* expcause2bit: external load stalled bit */
+ { "expcause2bit", EPIPHANY_OPERAND_EXPCAUSE2BIT, HW_H_EXPCAUSE2BIT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* extFstallbit: external fetch stalled bit */
+ { "extFstallbit", EPIPHANY_OPERAND_EXTFSTALLBIT, HW_H_EXTFSTALLBIT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* trmbit: 0=round to nearest, 1=trunacte selct bit */
+ { "trmbit", EPIPHANY_OPERAND_TRMBIT, HW_H_TRMBIT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* invExcEnbit: invalid exception enable bit */
+ { "invExcEnbit", EPIPHANY_OPERAND_INVEXCENBIT, HW_H_INVEXCENBIT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* ovfExcEnbit: overflow exception enable bit */
+ { "ovfExcEnbit", EPIPHANY_OPERAND_OVFEXCENBIT, HW_H_OVFEXCENBIT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* unExcEnbit: underflow exception enable bit */
+ { "unExcEnbit", EPIPHANY_OPERAND_UNEXCENBIT, HW_H_UNEXCENBIT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* timer0bit0: timer 0 mode selection 0 */
+ { "timer0bit0", EPIPHANY_OPERAND_TIMER0BIT0, HW_H_TIMER0BIT0, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* timer0bit1: timer 0 mode selection 1 */
+ { "timer0bit1", EPIPHANY_OPERAND_TIMER0BIT1, HW_H_TIMER0BIT1, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* timer0bit2: timer 0 mode selection 2 */
+ { "timer0bit2", EPIPHANY_OPERAND_TIMER0BIT2, HW_H_TIMER0BIT2, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* timer0bit3: timer 0 mode selection 3 */
+ { "timer0bit3", EPIPHANY_OPERAND_TIMER0BIT3, HW_H_TIMER0BIT3, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* timer1bit0: timer 1 mode selection 0 */
+ { "timer1bit0", EPIPHANY_OPERAND_TIMER1BIT0, HW_H_TIMER1BIT0, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* timer1bit1: timer 1 mode selection 1 */
+ { "timer1bit1", EPIPHANY_OPERAND_TIMER1BIT1, HW_H_TIMER1BIT1, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* timer1bit2: timer 1 mode selection 2 */
+ { "timer1bit2", EPIPHANY_OPERAND_TIMER1BIT2, HW_H_TIMER1BIT2, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* timer1bit3: timer 1 mode selection 3 */
+ { "timer1bit3", EPIPHANY_OPERAND_TIMER1BIT3, HW_H_TIMER1BIT3, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* mbkptEnbit: multicore bkpt enable */
+ { "mbkptEnbit", EPIPHANY_OPERAND_MBKPTENBIT, HW_H_MBKPTENBIT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* clockGateEnbit: clock gate enable enable */
+ { "clockGateEnbit", EPIPHANY_OPERAND_CLOCKGATEENBIT, HW_H_CLOCKGATEENBIT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* arithmetic-modebit0: arithmetic mode bit0 */
+ { "arithmetic-modebit0", EPIPHANY_OPERAND_ARITHMETIC_MODEBIT0, HW_H_ARITHMETIC_MODEBIT0, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* arithmetic-modebit1: arithmetic mode bit1 */
+ { "arithmetic-modebit1", EPIPHANY_OPERAND_ARITHMETIC_MODEBIT1, HW_H_ARITHMETIC_MODEBIT1, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* arithmetic-modebit2: arithmetic mode bit2 */
+ { "arithmetic-modebit2", EPIPHANY_OPERAND_ARITHMETIC_MODEBIT2, HW_H_ARITHMETIC_MODEBIT2, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* coreCfgResBit12: core config bit 12 */
+ { "coreCfgResBit12", EPIPHANY_OPERAND_CORECFGRESBIT12, HW_H_CORECFGRESBIT12, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* coreCfgResBit13: core config bit 13 */
+ { "coreCfgResBit13", EPIPHANY_OPERAND_CORECFGRESBIT13, HW_H_CORECFGRESBIT13, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* coreCfgResBit14: core config bit 14 */
+ { "coreCfgResBit14", EPIPHANY_OPERAND_CORECFGRESBIT14, HW_H_CORECFGRESBIT14, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* coreCfgResBit15: core config bit 15 */
+ { "coreCfgResBit15", EPIPHANY_OPERAND_CORECFGRESBIT15, HW_H_CORECFGRESBIT15, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* coreCfgResBit16: core config bit 16 */
+ { "coreCfgResBit16", EPIPHANY_OPERAND_CORECFGRESBIT16, HW_H_CORECFGRESBIT16, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* coreCfgResBit20: core config bit 20 */
+ { "coreCfgResBit20", EPIPHANY_OPERAND_CORECFGRESBIT20, HW_H_CORECFGRESBIT20, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* coreCfgResBit21: core config bit 21 */
+ { "coreCfgResBit21", EPIPHANY_OPERAND_CORECFGRESBIT21, HW_H_CORECFGRESBIT21, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* coreCfgResBit24: core config bit 24 */
+ { "coreCfgResBit24", EPIPHANY_OPERAND_CORECFGRESBIT24, HW_H_CORECFGRESBIT24, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* coreCfgResBit25: core config bit 25 */
+ { "coreCfgResBit25", EPIPHANY_OPERAND_CORECFGRESBIT25, HW_H_CORECFGRESBIT25, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* coreCfgResBit26: core config bit 26 */
+ { "coreCfgResBit26", EPIPHANY_OPERAND_CORECFGRESBIT26, HW_H_CORECFGRESBIT26, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* coreCfgResBit27: core config bit 27 */
+ { "coreCfgResBit27", EPIPHANY_OPERAND_CORECFGRESBIT27, HW_H_CORECFGRESBIT27, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* coreCfgResBit28: core config bit 28 */
+ { "coreCfgResBit28", EPIPHANY_OPERAND_CORECFGRESBIT28, HW_H_CORECFGRESBIT28, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* coreCfgResBit29: core config bit 29 */
+ { "coreCfgResBit29", EPIPHANY_OPERAND_CORECFGRESBIT29, HW_H_CORECFGRESBIT29, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* coreCfgResBit30: core config bit 30 */
+ { "coreCfgResBit30", EPIPHANY_OPERAND_CORECFGRESBIT30, HW_H_CORECFGRESBIT30, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* coreCfgResBit31: core config bit 31 */
+ { "coreCfgResBit31", EPIPHANY_OPERAND_CORECFGRESBIT31, HW_H_CORECFGRESBIT31, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* gidisablebit: global interrupt disable bit */
+ { "gidisablebit", EPIPHANY_OPERAND_GIDISABLEBIT, HW_H_GIDISABLEBIT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* kmbit: kernel mode bit */
+ { "kmbit", EPIPHANY_OPERAND_KMBIT, HW_H_KMBIT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* caibit: core actibe indicator bit */
+ { "caibit", EPIPHANY_OPERAND_CAIBIT, HW_H_CAIBIT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* sflagbit: sflag bit */
+ { "sflagbit", EPIPHANY_OPERAND_SFLAGBIT, HW_H_SFLAGBIT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* memaddr: memory effective address */
+ { "memaddr", EPIPHANY_OPERAND_MEMADDR, HW_H_MEMADDR, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* simm24: branch address pc-relative */
+ { "simm24", EPIPHANY_OPERAND_SIMM24, HW_H_IADDR, 31, 24,
+- { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SIMM24] } },
++ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SIMM24] } },
+ { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
+ /* simm8: branch address pc-relative */
+ { "simm8", EPIPHANY_OPERAND_SIMM8, HW_H_IADDR, 15, 8,
+- { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SIMM8] } },
++ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SIMM8] } },
+ { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
+ /* rd: destination register */
+ { "rd", EPIPHANY_OPERAND_RD, HW_H_REGISTERS, 15, 3,
+- { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RD] } },
++ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RD] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* rn: source register */
+ { "rn", EPIPHANY_OPERAND_RN, HW_H_REGISTERS, 12, 3,
+- { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RN] } },
++ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RN] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* rm: source register */
+ { "rm", EPIPHANY_OPERAND_RM, HW_H_REGISTERS, 9, 3,
+- { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RM] } },
++ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RM] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* frd: fp destination register */
+ { "frd", EPIPHANY_OPERAND_FRD, HW_H_FPREGISTERS, 15, 3,
+- { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RD] } },
++ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RD] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* frn: fp source register */
+ { "frn", EPIPHANY_OPERAND_FRN, HW_H_FPREGISTERS, 12, 3,
+- { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RN] } },
++ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RN] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* frm: fp source register */
+ { "frm", EPIPHANY_OPERAND_FRM, HW_H_FPREGISTERS, 9, 3,
+- { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RM] } },
++ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RM] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* rd6: destination register */
+ { "rd6", EPIPHANY_OPERAND_RD6, HW_H_REGISTERS, 15, 6,
+- { 2, { (const PTR) &EPIPHANY_F_RD6_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &EPIPHANY_F_RD6_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+ /* rn6: source register */
+ { "rn6", EPIPHANY_OPERAND_RN6, HW_H_REGISTERS, 12, 6,
+- { 2, { (const PTR) &EPIPHANY_F_RN6_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &EPIPHANY_F_RN6_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+ /* rm6: source register */
+ { "rm6", EPIPHANY_OPERAND_RM6, HW_H_REGISTERS, 9, 6,
+- { 2, { (const PTR) &EPIPHANY_F_RM6_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &EPIPHANY_F_RM6_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+ /* frd6: fp destination register */
+ { "frd6", EPIPHANY_OPERAND_FRD6, HW_H_FPREGISTERS, 15, 6,
+- { 2, { (const PTR) &EPIPHANY_F_RD6_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &EPIPHANY_F_RD6_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+ /* frn6: fp source register */
+ { "frn6", EPIPHANY_OPERAND_FRN6, HW_H_FPREGISTERS, 12, 6,
+- { 2, { (const PTR) &EPIPHANY_F_RN6_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &EPIPHANY_F_RN6_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+ /* frm6: fp source register */
+ { "frm6", EPIPHANY_OPERAND_FRM6, HW_H_FPREGISTERS, 9, 6,
+- { 2, { (const PTR) &EPIPHANY_F_RM6_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &EPIPHANY_F_RM6_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+ /* sd: special destination */
+ { "sd", EPIPHANY_OPERAND_SD, HW_H_CORE_REGISTERS, 15, 3,
+- { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SD] } },
++ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SD] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* sn: special source */
+ { "sn", EPIPHANY_OPERAND_SN, HW_H_CORE_REGISTERS, 12, 3,
+- { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SN] } },
++ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SN] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* sd6: special destination register */
+ { "sd6", EPIPHANY_OPERAND_SD6, HW_H_CORE_REGISTERS, 15, 6,
+- { 2, { (const PTR) &EPIPHANY_F_SD6_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &EPIPHANY_F_SD6_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+ /* sn6: special source register */
+ { "sn6", EPIPHANY_OPERAND_SN6, HW_H_CORE_REGISTERS, 12, 6,
+- { 2, { (const PTR) &EPIPHANY_F_SN6_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &EPIPHANY_F_SN6_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+ /* sddma: dma register */
+ { "sddma", EPIPHANY_OPERAND_SDDMA, HW_H_COREDMA_REGISTERS, 15, 6,
+- { 2, { (const PTR) &EPIPHANY_F_SD6_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &EPIPHANY_F_SD6_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+ /* sndma: dma register */
+ { "sndma", EPIPHANY_OPERAND_SNDMA, HW_H_COREDMA_REGISTERS, 12, 6,
+- { 2, { (const PTR) &EPIPHANY_F_SN6_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &EPIPHANY_F_SN6_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+ /* sdmem: mem register */
+ { "sdmem", EPIPHANY_OPERAND_SDMEM, HW_H_COREMEM_REGISTERS, 15, 6,
+- { 2, { (const PTR) &EPIPHANY_F_SD6_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &EPIPHANY_F_SD6_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+ /* snmem: mem register */
+ { "snmem", EPIPHANY_OPERAND_SNMEM, HW_H_COREMEM_REGISTERS, 12, 6,
+- { 2, { (const PTR) &EPIPHANY_F_SN6_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &EPIPHANY_F_SN6_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+ /* sdmesh: mesh register */
+ { "sdmesh", EPIPHANY_OPERAND_SDMESH, HW_H_COREMESH_REGISTERS, 15, 6,
+- { 2, { (const PTR) &EPIPHANY_F_SD6_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &EPIPHANY_F_SD6_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+ /* snmesh: mesh register */
+ { "snmesh", EPIPHANY_OPERAND_SNMESH, HW_H_COREMESH_REGISTERS, 12, 6,
+- { 2, { (const PTR) &EPIPHANY_F_SN6_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &EPIPHANY_F_SN6_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+ /* simm3: signed 3-bit literal */
+ { "simm3", EPIPHANY_OPERAND_SIMM3, HW_H_SINT, 9, 3,
+- { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SDISP3] } },
++ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SDISP3] } },
+ { 0|A(RELAX), { { { (1<<MACH_BASE), 0 } } } } },
+ /* simm11: signed 11-bit literal */
+ { "simm11", EPIPHANY_OPERAND_SIMM11, HW_H_SINT, 9, 11,
+- { 2, { (const PTR) &EPIPHANY_F_SDISP11_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &EPIPHANY_F_SDISP11_MULTI_IFIELD[0] } },
+ { 0|A(RELAX)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+ /* disp3: short data displacement */
+ { "disp3", EPIPHANY_OPERAND_DISP3, HW_H_UINT, 9, 3,
+- { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_DISP3] } },
++ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_DISP3] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* trapnum6: parameter for swi or trap */
+ { "trapnum6", EPIPHANY_OPERAND_TRAPNUM6, HW_H_UINT, 15, 6,
+- { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_TRAP_NUM] } },
++ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_TRAP_NUM] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* swi_num: unsigned 6-bit swi# */
+ { "swi_num", EPIPHANY_OPERAND_SWI_NUM, HW_H_UINT, 15, 6,
+- { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_TRAP_NUM] } },
++ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_TRAP_NUM] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* disp11: sign-magnitude data displacement */
+ { "disp11", EPIPHANY_OPERAND_DISP11, HW_H_UINT, 9, 11,
+- { 2, { (const PTR) &EPIPHANY_F_DISP11_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &EPIPHANY_F_DISP11_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+ /* shift: immediate shift amount */
+ { "shift", EPIPHANY_OPERAND_SHIFT, HW_H_UINT, 9, 5,
+- { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SHIFT] } },
++ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SHIFT] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* imm16: 16-bit unsigned literal */
+ { "imm16", EPIPHANY_OPERAND_IMM16, HW_H_ADDR, 12, 16,
+- { 2, { (const PTR) &EPIPHANY_F_IMM16_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &EPIPHANY_F_IMM16_MULTI_IFIELD[0] } },
+ { 0|A(RELAX)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+ /* imm8: 8-bit unsigned literal */
+ { "imm8", EPIPHANY_OPERAND_IMM8, HW_H_ADDR, 12, 8,
+- { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_IMM8] } },
++ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_IMM8] } },
+ { 0|A(RELAX), { { { (1<<MACH_BASE), 0 } } } } },
+ /* direction: +/- indexing */
+ { "direction", EPIPHANY_OPERAND_DIRECTION, HW_H_UINT, 20, 1,
+- { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_ADDSUBX] } },
++ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_ADDSUBX] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* dpmi: +/- magnitude immediate displacement */
+ { "dpmi", EPIPHANY_OPERAND_DPMI, HW_H_UINT, 24, 1,
+- { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SUBD] } },
++ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SUBD] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* sentinel */
+ { 0, 0, 0, 0, 0,
+@@ -2212,7 +2212,7 @@ epiphany_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
+
+ /* Default to not allowing signed overflow. */
+ cd->signed_overflow_ok_p = 0;
+-
++
+ return (CGEN_CPU_DESC) cd;
+ }
+
+@@ -2252,7 +2252,7 @@ epiphany_cgen_cpu_close (CGEN_CPU_DESC cd)
+ for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
+ if (CGEN_INSN_RX (insns))
+ regfree (CGEN_INSN_RX (insns));
+- }
++ }
+
+ if (cd->macro_insn_table.init_entries)
+ free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
+--- a/opcodes/epiphany-dis.c
++++ b/opcodes/epiphany-dis.c
+@@ -279,7 +279,7 @@ epiphany_cgen_print_operand (CGEN_CPU_DESC cd,
+ }
+ }
+
+-cgen_print_fn * const epiphany_cgen_print_handlers[] =
++cgen_print_fn * const epiphany_cgen_print_handlers[] =
+ {
+ print_insn_normal,
+ };
+@@ -469,7 +469,7 @@ print_insn (CGEN_CPU_DESC cd,
+ int length;
+ unsigned long insn_value_cropped;
+
+-#ifdef CGEN_VALIDATE_INSN_SUPPORTED
++#ifdef CGEN_VALIDATE_INSN_SUPPORTED
+ /* Not needed as insn shouldn't be in hash lists if not supported. */
+ /* Supported by this cpu? */
+ if (! epiphany_cgen_insn_supported (cd, insn))
+@@ -487,7 +487,7 @@ print_insn (CGEN_CPU_DESC cd,
+ relevant part from the buffer. */
+ if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
+ (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
+- insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
++ insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
+ info->endian == BFD_ENDIAN_BIG);
+ else
+ insn_value_cropped = insn_value;
+@@ -606,7 +606,7 @@ print_insn_epiphany (bfd_vma pc, disassemble_info *info)
+ arch = info->arch;
+ if (arch == bfd_arch_unknown)
+ arch = CGEN_BFD_ARCH;
+-
++
+ /* There's no standard way to compute the machine or isa number
+ so we leave it to the target. */
+ #ifdef CGEN_COMPUTE_MACH
+@@ -647,7 +647,7 @@ print_insn_epiphany (bfd_vma pc, disassemble_info *info)
+ break;
+ }
+ }
+- }
++ }
+
+ /* If we haven't initialized yet, initialize the opcode table. */
+ if (! cd)
+--- a/opcodes/epiphany-ibld.c
++++ b/opcodes/epiphany-ibld.c
+@@ -154,7 +154,7 @@ insert_normal (CGEN_CPU_DESC cd,
+ {
+ long minval = - (1L << (length - 1));
+ unsigned long maxval = mask;
+-
++
+ if ((value > 0 && (unsigned long) value > maxval)
+ || value < minval)
+ {
+@@ -192,7 +192,7 @@ insert_normal (CGEN_CPU_DESC cd,
+ {
+ long minval = - (1L << (length - 1));
+ long maxval = (1L << (length - 1)) - 1;
+-
++
+ if (value < minval || value > maxval)
+ {
+ sprintf
+@@ -1170,12 +1170,12 @@ epiphany_cgen_extract_operand (CGEN_CPU_DESC cd,
+ return length;
+ }
+
+-cgen_insert_fn * const epiphany_cgen_insert_handlers[] =
++cgen_insert_fn * const epiphany_cgen_insert_handlers[] =
+ {
+ insert_insn_normal,
+ };
+
+-cgen_extract_fn * const epiphany_cgen_extract_handlers[] =
++cgen_extract_fn * const epiphany_cgen_extract_handlers[] =
+ {
+ extract_insn_normal,
+ };
+--- a/opcodes/fr30-asm.c
++++ b/opcodes/fr30-asm.c
+@@ -313,7 +313,7 @@ fr30_cgen_parse_operand (CGEN_CPU_DESC cd,
+ return errmsg;
+ }
+
+-cgen_parse_fn * const fr30_cgen_parse_handlers[] =
++cgen_parse_fn * const fr30_cgen_parse_handlers[] =
+ {
+ parse_insn_normal,
+ };
+@@ -343,9 +343,9 @@ CGEN_ASM_INIT_HOOK
+
+ Returns NULL for success, an error message for failure. */
+
+-char *
++char *
+ fr30_cgen_build_insn_regex (CGEN_INSN *insn)
+-{
++{
+ CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
+ const char *mnem = CGEN_INSN_MNEMONIC (insn);
+ char rxbuf[CGEN_MAX_RX_ELEMENTS];
+@@ -384,18 +384,18 @@ fr30_cgen_build_insn_regex (CGEN_INSN *insn)
+ /* Copy any remaining literals from the syntax string into the rx. */
+ for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn)
+ {
+- if (CGEN_SYNTAX_CHAR_P (* syn))
++ if (CGEN_SYNTAX_CHAR_P (* syn))
+ {
+ char c = CGEN_SYNTAX_CHAR (* syn);
+
+- switch (c)
++ switch (c)
+ {
+ /* Escape any regex metacharacters in the syntax. */
+- case '.': case '[': case '\\':
+- case '*': case '^': case '$':
++ case '.': case '[': case '\\':
++ case '*': case '^': case '$':
+
+ #ifdef CGEN_ESCAPE_EXTENDED_REGEX
+- case '?': case '{': case '}':
++ case '?': case '{': case '}':
+ case '(': case ')': case '*':
+ case '|': case '+': case ']':
+ #endif
+@@ -425,20 +425,20 @@ fr30_cgen_build_insn_regex (CGEN_INSN *insn)
+ }
+
+ /* Trailing whitespace ok. */
+- * rx++ = '[';
+- * rx++ = ' ';
+- * rx++ = '\t';
+- * rx++ = ']';
+- * rx++ = '*';
++ * rx++ = '[';
++ * rx++ = ' ';
++ * rx++ = '\t';
++ * rx++ = ']';
++ * rx++ = '*';
+
+ /* But anchor it after that. */
+- * rx++ = '$';
++ * rx++ = '$';
+ * rx = '\0';
+
+ CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t));
+ reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB);
+
+- if (reg_err == 0)
++ if (reg_err == 0)
+ return NULL;
+ else
+ {
+@@ -637,7 +637,7 @@ fr30_cgen_assemble_insn (CGEN_CPU_DESC cd,
+ const CGEN_INSN *insn = ilist->insn;
+ recognized_mnemonic = 1;
+
+-#ifdef CGEN_VALIDATE_INSN_SUPPORTED
++#ifdef CGEN_VALIDATE_INSN_SUPPORTED
+ /* Not usually needed as unsupported opcodes
+ shouldn't be in the hash lists. */
+ /* Is this insn supported by the selected cpu? */
+@@ -697,7 +697,7 @@ fr30_cgen_assemble_insn (CGEN_CPU_DESC cd,
+ if (strlen (start) > 50)
+ /* xgettext:c-format */
+ sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start);
+- else
++ else
+ /* xgettext:c-format */
+ sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start);
+ }
+@@ -706,11 +706,11 @@ fr30_cgen_assemble_insn (CGEN_CPU_DESC cd,
+ if (strlen (start) > 50)
+ /* xgettext:c-format */
+ sprintf (errbuf, _("bad instruction `%.50s...'"), start);
+- else
++ else
+ /* xgettext:c-format */
+ sprintf (errbuf, _("bad instruction `%.50s'"), start);
+ }
+-
++
+ *errmsg = errbuf;
+ return NULL;
+ }
+--- a/opcodes/fr30-desc.c
++++ b/opcodes/fr30-desc.c
+@@ -364,199 +364,199 @@ const CGEN_OPERAND fr30_cgen_operand_table[] =
+ {
+ /* pc: program counter */
+ { "pc", FR30_OPERAND_PC, HW_H_PC, 0, 0,
+- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_NIL] } },
++ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_NIL] } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* Ri: destination register */
+ { "Ri", FR30_OPERAND_RI, HW_H_GR, 12, 4,
+- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RI] } },
++ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RI] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* Rj: source register */
+ { "Rj", FR30_OPERAND_RJ, HW_H_GR, 8, 4,
+- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RJ] } },
++ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RJ] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* Ric: target register coproc insn */
+ { "Ric", FR30_OPERAND_RIC, HW_H_GR, 12, 4,
+- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RIC] } },
++ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RIC] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* Rjc: source register coproc insn */
+ { "Rjc", FR30_OPERAND_RJC, HW_H_GR, 8, 4,
+- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RJC] } },
++ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RJC] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* CRi: coprocessor register */
+ { "CRi", FR30_OPERAND_CRI, HW_H_CR, 12, 4,
+- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CRI] } },
++ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CRI] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* CRj: coprocessor register */
+ { "CRj", FR30_OPERAND_CRJ, HW_H_CR, 8, 4,
+- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CRJ] } },
++ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CRJ] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* Rs1: dedicated register */
+ { "Rs1", FR30_OPERAND_RS1, HW_H_DR, 8, 4,
+- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RS1] } },
++ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RS1] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* Rs2: dedicated register */
+ { "Rs2", FR30_OPERAND_RS2, HW_H_DR, 12, 4,
+- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RS2] } },
++ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RS2] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* R13: General Register 13 */
+ { "R13", FR30_OPERAND_R13, HW_H_R13, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* R14: General Register 14 */
+ { "R14", FR30_OPERAND_R14, HW_H_R14, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* R15: General Register 15 */
+ { "R15", FR30_OPERAND_R15, HW_H_R15, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* ps: Program Status register */
+ { "ps", FR30_OPERAND_PS, HW_H_PS, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* u4: 4 bit unsigned immediate */
+ { "u4", FR30_OPERAND_U4, HW_H_UINT, 8, 4,
+- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U4] } },
++ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U4] } },
+ { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
+ /* u4c: 4 bit unsigned immediate */
+ { "u4c", FR30_OPERAND_U4C, HW_H_UINT, 12, 4,
+- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U4C] } },
++ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U4C] } },
+ { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
+ /* u8: 8 bit unsigned immediate */
+ { "u8", FR30_OPERAND_U8, HW_H_UINT, 8, 8,
+- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U8] } },
++ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U8] } },
+ { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
+ /* i8: 8 bit unsigned immediate */
+ { "i8", FR30_OPERAND_I8, HW_H_UINT, 4, 8,
+- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_I8] } },
++ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_I8] } },
+ { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
+ /* udisp6: 6 bit unsigned immediate */
+ { "udisp6", FR30_OPERAND_UDISP6, HW_H_UINT, 8, 4,
+- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_UDISP6] } },
++ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_UDISP6] } },
+ { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
+ /* disp8: 8 bit signed immediate */
+ { "disp8", FR30_OPERAND_DISP8, HW_H_SINT, 4, 8,
+- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DISP8] } },
++ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DISP8] } },
+ { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
+ /* disp9: 9 bit signed immediate */
+ { "disp9", FR30_OPERAND_DISP9, HW_H_SINT, 4, 8,
+- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DISP9] } },
++ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DISP9] } },
+ { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
+ /* disp10: 10 bit signed immediate */
+ { "disp10", FR30_OPERAND_DISP10, HW_H_SINT, 4, 8,
+- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DISP10] } },
++ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DISP10] } },
+ { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
+ /* s10: 10 bit signed immediate */
+ { "s10", FR30_OPERAND_S10, HW_H_SINT, 8, 8,
+- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_S10] } },
++ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_S10] } },
+ { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
+ /* u10: 10 bit unsigned immediate */
+ { "u10", FR30_OPERAND_U10, HW_H_UINT, 8, 8,
+- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U10] } },
++ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U10] } },
+ { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
+ /* i32: 32 bit immediate */
+ { "i32", FR30_OPERAND_I32, HW_H_UINT, 0, 32,
+- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_I32] } },
++ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_I32] } },
+ { 0|A(HASH_PREFIX)|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } },
+ /* m4: 4 bit negative immediate */
+ { "m4", FR30_OPERAND_M4, HW_H_SINT, 8, 4,
+- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_M4] } },
++ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_M4] } },
+ { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
+ /* i20: 20 bit immediate */
+ { "i20", FR30_OPERAND_I20, HW_H_UINT, 0, 20,
+- { 2, { (const PTR) &FR30_F_I20_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &FR30_F_I20_MULTI_IFIELD[0] } },
+ { 0|A(HASH_PREFIX)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+ /* dir8: 8 bit direct address */
+ { "dir8", FR30_OPERAND_DIR8, HW_H_UINT, 8, 8,
+- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DIR8] } },
++ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DIR8] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* dir9: 9 bit direct address */
+ { "dir9", FR30_OPERAND_DIR9, HW_H_UINT, 8, 8,
+- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DIR9] } },
++ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DIR9] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* dir10: 10 bit direct address */
+ { "dir10", FR30_OPERAND_DIR10, HW_H_UINT, 8, 8,
+- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DIR10] } },
++ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DIR10] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* label9: 9 bit pc relative address */
+ { "label9", FR30_OPERAND_LABEL9, HW_H_IADDR, 8, 8,
+- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REL9] } },
++ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REL9] } },
+ { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
+ /* label12: 12 bit pc relative address */
+ { "label12", FR30_OPERAND_LABEL12, HW_H_IADDR, 5, 11,
+- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REL12] } },
++ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REL12] } },
+ { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
+ /* reglist_low_ld: 8 bit low register mask for ldm */
+ { "reglist_low_ld", FR30_OPERAND_REGLIST_LOW_LD, HW_H_UINT, 8, 8,
+- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_LOW_LD] } },
++ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_LOW_LD] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* reglist_hi_ld: 8 bit high register mask for ldm */
+ { "reglist_hi_ld", FR30_OPERAND_REGLIST_HI_LD, HW_H_UINT, 8, 8,
+- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_HI_LD] } },
++ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_HI_LD] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* reglist_low_st: 8 bit low register mask for stm */
+ { "reglist_low_st", FR30_OPERAND_REGLIST_LOW_ST, HW_H_UINT, 8, 8,
+- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_LOW_ST] } },
++ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_LOW_ST] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* reglist_hi_st: 8 bit high register mask for stm */
+ { "reglist_hi_st", FR30_OPERAND_REGLIST_HI_ST, HW_H_UINT, 8, 8,
+- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_HI_ST] } },
++ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_HI_ST] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* cc: condition codes */
+ { "cc", FR30_OPERAND_CC, HW_H_UINT, 4, 4,
+- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CC] } },
++ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CC] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* ccc: coprocessor calc */
+ { "ccc", FR30_OPERAND_CCC, HW_H_UINT, 0, 8,
+- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CCC] } },
++ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CCC] } },
+ { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
+ /* nbit: negative bit */
+ { "nbit", FR30_OPERAND_NBIT, HW_H_NBIT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* vbit: overflow bit */
+ { "vbit", FR30_OPERAND_VBIT, HW_H_VBIT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* zbit: zero bit */
+ { "zbit", FR30_OPERAND_ZBIT, HW_H_ZBIT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* cbit: carry bit */
+ { "cbit", FR30_OPERAND_CBIT, HW_H_CBIT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* ibit: interrupt bit */
+ { "ibit", FR30_OPERAND_IBIT, HW_H_IBIT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* sbit: stack bit */
+ { "sbit", FR30_OPERAND_SBIT, HW_H_SBIT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* tbit: trace trap bit */
+ { "tbit", FR30_OPERAND_TBIT, HW_H_TBIT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* d0bit: division 0 bit */
+ { "d0bit", FR30_OPERAND_D0BIT, HW_H_D0BIT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* d1bit: division 1 bit */
+ { "d1bit", FR30_OPERAND_D1BIT, HW_H_D1BIT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* ccr: condition code bits */
+ { "ccr", FR30_OPERAND_CCR, HW_H_CCR, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* scr: system condition bits */
+ { "scr", FR30_OPERAND_SCR, HW_H_SCR, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* ilm: interrupt level mask */
+ { "ilm", FR30_OPERAND_ILM, HW_H_ILM, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* sentinel */
+ { 0, 0, 0, 0, 0,
+@@ -1689,7 +1689,7 @@ fr30_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
+
+ /* Default to not allowing signed overflow. */
+ cd->signed_overflow_ok_p = 0;
+-
++
+ return (CGEN_CPU_DESC) cd;
+ }
+
+@@ -1729,7 +1729,7 @@ fr30_cgen_cpu_close (CGEN_CPU_DESC cd)
+ for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
+ if (CGEN_INSN_RX (insns))
+ regfree (CGEN_INSN_RX (insns));
+- }
++ }
+
+ if (cd->macro_insn_table.init_entries)
+ free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
+--- a/opcodes/fr30-dis.c
++++ b/opcodes/fr30-dis.c
+@@ -79,7 +79,7 @@ print_register_list (void * dis_info,
+ (*info->fprintf_func) (info->stream, "r%li", reg_index + offset);
+ comma = ",";
+ }
+-
++
+ for (reg_index = 1; reg_index <= 7; ++reg_index)
+ {
+ if (load_store)
+@@ -301,7 +301,7 @@ fr30_cgen_print_operand (CGEN_CPU_DESC cd,
+ }
+ }
+
+-cgen_print_fn * const fr30_cgen_print_handlers[] =
++cgen_print_fn * const fr30_cgen_print_handlers[] =
+ {
+ print_insn_normal,
+ };
+@@ -491,7 +491,7 @@ print_insn (CGEN_CPU_DESC cd,
+ int length;
+ unsigned long insn_value_cropped;
+
+-#ifdef CGEN_VALIDATE_INSN_SUPPORTED
++#ifdef CGEN_VALIDATE_INSN_SUPPORTED
+ /* Not needed as insn shouldn't be in hash lists if not supported. */
+ /* Supported by this cpu? */
+ if (! fr30_cgen_insn_supported (cd, insn))
+@@ -509,7 +509,7 @@ print_insn (CGEN_CPU_DESC cd,
+ relevant part from the buffer. */
+ if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
+ (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
+- insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
++ insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
+ info->endian == BFD_ENDIAN_BIG);
+ else
+ insn_value_cropped = insn_value;
+@@ -628,7 +628,7 @@ print_insn_fr30 (bfd_vma pc, disassemble_info *info)
+ arch = info->arch;
+ if (arch == bfd_arch_unknown)
+ arch = CGEN_BFD_ARCH;
+-
++
+ /* There's no standard way to compute the machine or isa number
+ so we leave it to the target. */
+ #ifdef CGEN_COMPUTE_MACH
+@@ -669,7 +669,7 @@ print_insn_fr30 (bfd_vma pc, disassemble_info *info)
+ break;
+ }
+ }
+- }
++ }
+
+ /* If we haven't initialized yet, initialize the opcode table. */
+ if (! cd)
+--- a/opcodes/fr30-ibld.c
++++ b/opcodes/fr30-ibld.c
+@@ -154,7 +154,7 @@ insert_normal (CGEN_CPU_DESC cd,
+ {
+ long minval = - (1L << (length - 1));
+ unsigned long maxval = mask;
+-
++
+ if ((value > 0 && (unsigned long) value > maxval)
+ || value < minval)
+ {
+@@ -192,7 +192,7 @@ insert_normal (CGEN_CPU_DESC cd,
+ {
+ long minval = - (1L << (length - 1));
+ long maxval = (1L << (length - 1)) - 1;
+-
++
+ if (value < minval || value > maxval)
+ {
+ sprintf
+@@ -936,12 +936,12 @@ fr30_cgen_extract_operand (CGEN_CPU_DESC cd,
+ return length;
+ }
+
+-cgen_insert_fn * const fr30_cgen_insert_handlers[] =
++cgen_insert_fn * const fr30_cgen_insert_handlers[] =
+ {
+ insert_insn_normal,
+ };
+
+-cgen_extract_fn * const fr30_cgen_extract_handlers[] =
++cgen_extract_fn * const fr30_cgen_extract_handlers[] =
+ {
+ extract_insn_normal,
+ };
+--- a/opcodes/frv-asm.c
++++ b/opcodes/frv-asm.c
+@@ -99,10 +99,10 @@ parse_ldd_annotation (CGEN_CPU_DESC cd,
+ return errmsg;
+ }
+ }
+-
++
+ while (**strp == ' ' || **strp == '\t')
+ ++*strp;
+-
++
+ if (**strp != '@')
+ return "missing `@'";
+
+@@ -138,10 +138,10 @@ parse_call_annotation (CGEN_CPU_DESC cd,
+ return errmsg;
+ }
+ }
+-
++
+ while (**strp == ' ' || **strp == '\t')
+ ++*strp;
+-
++
+ if (**strp != '@')
+ return "missing `@'";
+
+@@ -177,10 +177,10 @@ parse_ld_annotation (CGEN_CPU_DESC cd,
+ return errmsg;
+ }
+ }
+-
++
+ while (**strp == ' ' || **strp == '\t')
+ ++*strp;
+-
++
+ if (**strp != '@')
+ return "missing `@'";
+
+@@ -198,7 +198,7 @@ parse_ulo16 (CGEN_CPU_DESC cd,
+ const char *errmsg;
+ enum cgen_parse_operand_result result_type;
+ bfd_vma value;
+-
++
+ if (**strp == '#' || **strp == '%')
+ {
+ if (strncasecmp (*strp + 1, "lo(", 3) == 0)
+@@ -324,7 +324,7 @@ parse_uslo16 (CGEN_CPU_DESC cd,
+ const char *errmsg;
+ enum cgen_parse_operand_result result_type;
+ bfd_vma value;
+-
++
+ if (**strp == '#' || **strp == '%')
+ {
+ if (strncasecmp (*strp + 1, "lo(", 3) == 0)
+@@ -450,7 +450,7 @@ parse_uhi16 (CGEN_CPU_DESC cd,
+ const char *errmsg;
+ enum cgen_parse_operand_result result_type;
+ bfd_vma value;
+-
++
+ if (**strp == '#' || **strp == '%')
+ {
+ if (strncasecmp (*strp + 1, "hi(", 3) == 0)
+@@ -635,7 +635,7 @@ parse_d12 (CGEN_CPU_DESC cd,
+ const char *errmsg;
+ enum cgen_parse_operand_result result_type;
+ bfd_vma value;
+-
++
+ /* Check for small data reference. */
+ if (**strp == '#' || **strp == '%')
+ {
+@@ -748,7 +748,7 @@ parse_s12 (CGEN_CPU_DESC cd,
+ const char *errmsg;
+ enum cgen_parse_operand_result result_type;
+ bfd_vma value;
+-
++
+ /* Check for small data reference. */
+ if (**strp == '#' || **strp == '%')
+ {
+@@ -864,7 +864,7 @@ parse_u12 (CGEN_CPU_DESC cd,
+ const char *errmsg;
+ enum cgen_parse_operand_result result_type;
+ bfd_vma value;
+-
++
+ /* Check for small data reference. */
+ if ((**strp == '#' || **strp == '%')
+ && strncasecmp (*strp + 1, "gprel12(", 8) == 0)
+@@ -895,7 +895,7 @@ parse_A (CGEN_CPU_DESC cd,
+ unsigned long A)
+ {
+ const char *errmsg;
+-
++
+ if (**strp == '#')
+ ++*strp;
+
+@@ -957,7 +957,7 @@ parse_call_label (CGEN_CPU_DESC cd,
+ {
+ const char *errmsg;
+ bfd_vma value;
+-
++
+ /* Check for small data reference. */
+ if (opinfo == 0 && (**strp == '#' || **strp == '%'))
+ {
+@@ -1266,7 +1266,7 @@ frv_cgen_parse_operand (CGEN_CPU_DESC cd,
+ return errmsg;
+ }
+
+-cgen_parse_fn * const frv_cgen_parse_handlers[] =
++cgen_parse_fn * const frv_cgen_parse_handlers[] =
+ {
+ parse_insn_normal,
+ };
+@@ -1296,9 +1296,9 @@ CGEN_ASM_INIT_HOOK
+
+ Returns NULL for success, an error message for failure. */
+
+-char *
++char *
+ frv_cgen_build_insn_regex (CGEN_INSN *insn)
+-{
++{
+ CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
+ const char *mnem = CGEN_INSN_MNEMONIC (insn);
+ char rxbuf[CGEN_MAX_RX_ELEMENTS];
+@@ -1337,18 +1337,18 @@ frv_cgen_build_insn_regex (CGEN_INSN *insn)
+ /* Copy any remaining literals from the syntax string into the rx. */
+ for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn)
+ {
+- if (CGEN_SYNTAX_CHAR_P (* syn))
++ if (CGEN_SYNTAX_CHAR_P (* syn))
+ {
+ char c = CGEN_SYNTAX_CHAR (* syn);
+
+- switch (c)
++ switch (c)
+ {
+ /* Escape any regex metacharacters in the syntax. */
+- case '.': case '[': case '\\':
+- case '*': case '^': case '$':
++ case '.': case '[': case '\\':
++ case '*': case '^': case '$':
+
+ #ifdef CGEN_ESCAPE_EXTENDED_REGEX
+- case '?': case '{': case '}':
++ case '?': case '{': case '}':
+ case '(': case ')': case '*':
+ case '|': case '+': case ']':
+ #endif
+@@ -1378,20 +1378,20 @@ frv_cgen_build_insn_regex (CGEN_INSN *insn)
+ }
+
+ /* Trailing whitespace ok. */
+- * rx++ = '[';
+- * rx++ = ' ';
+- * rx++ = '\t';
+- * rx++ = ']';
+- * rx++ = '*';
++ * rx++ = '[';
++ * rx++ = ' ';
++ * rx++ = '\t';
++ * rx++ = ']';
++ * rx++ = '*';
+
+ /* But anchor it after that. */
+- * rx++ = '$';
++ * rx++ = '$';
+ * rx = '\0';
+
+ CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t));
+ reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB);
+
+- if (reg_err == 0)
++ if (reg_err == 0)
+ return NULL;
+ else
+ {
+@@ -1590,7 +1590,7 @@ frv_cgen_assemble_insn (CGEN_CPU_DESC cd,
+ const CGEN_INSN *insn = ilist->insn;
+ recognized_mnemonic = 1;
+
+-#ifdef CGEN_VALIDATE_INSN_SUPPORTED
++#ifdef CGEN_VALIDATE_INSN_SUPPORTED
+ /* Not usually needed as unsupported opcodes
+ shouldn't be in the hash lists. */
+ /* Is this insn supported by the selected cpu? */
+@@ -1650,7 +1650,7 @@ frv_cgen_assemble_insn (CGEN_CPU_DESC cd,
+ if (strlen (start) > 50)
+ /* xgettext:c-format */
+ sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start);
+- else
++ else
+ /* xgettext:c-format */
+ sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start);
+ }
+@@ -1659,11 +1659,11 @@ frv_cgen_assemble_insn (CGEN_CPU_DESC cd,
+ if (strlen (start) > 50)
+ /* xgettext:c-format */
+ sprintf (errbuf, _("bad instruction `%.50s...'"), start);
+- else
++ else
+ /* xgettext:c-format */
+ sprintf (errbuf, _("bad instruction `%.50s'"), start);
+ }
+-
++
+ *errmsg = errbuf;
+ return NULL;
+ }
+--- a/opcodes/frv-desc.c
++++ b/opcodes/frv-desc.c
+@@ -2054,359 +2054,359 @@ const CGEN_OPERAND frv_cgen_operand_table[] =
+ {
+ /* pc: program counter */
+ { "pc", FRV_OPERAND_PC, HW_H_PC, 0, 0,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_NIL] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_NIL] } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* pack: packing bit */
+ { "pack", FRV_OPERAND_PACK, HW_H_PACK, 31, 1,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_PACK] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_PACK] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* GRi: source register 1 */
+ { "GRi", FRV_OPERAND_GRI, HW_H_GR, 17, 6,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRI] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRI] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* GRj: source register 2 */
+ { "GRj", FRV_OPERAND_GRJ, HW_H_GR, 5, 6,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRJ] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRJ] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* GRk: destination register */
+ { "GRk", FRV_OPERAND_GRK, HW_H_GR, 30, 6,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRK] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRK] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* GRkhi: destination register */
+ { "GRkhi", FRV_OPERAND_GRKHI, HW_H_GR_HI, 30, 6,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRK] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRK] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* GRklo: destination register */
+ { "GRklo", FRV_OPERAND_GRKLO, HW_H_GR_LO, 30, 6,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRK] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRK] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* GRdoublek: destination register */
+ { "GRdoublek", FRV_OPERAND_GRDOUBLEK, HW_H_GR_DOUBLE, 30, 6,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRK] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRK] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* ACC40Si: signed accumulator */
+ { "ACC40Si", FRV_OPERAND_ACC40SI, HW_H_ACC40S, 17, 6,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACC40SI] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACC40SI] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* ACC40Ui: unsigned accumulator */
+ { "ACC40Ui", FRV_OPERAND_ACC40UI, HW_H_ACC40U, 17, 6,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACC40UI] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACC40UI] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* ACC40Sk: target accumulator */
+ { "ACC40Sk", FRV_OPERAND_ACC40SK, HW_H_ACC40S, 30, 6,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACC40SK] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACC40SK] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* ACC40Uk: target accumulator */
+ { "ACC40Uk", FRV_OPERAND_ACC40UK, HW_H_ACC40U, 30, 6,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACC40UK] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACC40UK] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* ACCGi: source register */
+ { "ACCGi", FRV_OPERAND_ACCGI, HW_H_ACCG, 17, 6,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACCGI] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACCGI] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* ACCGk: target register */
+ { "ACCGk", FRV_OPERAND_ACCGK, HW_H_ACCG, 30, 6,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACCGK] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACCGK] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* CPRi: source register */
+ { "CPRi", FRV_OPERAND_CPRI, HW_H_CPR, 17, 6,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CPRI] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CPRI] } },
+ { 0, { { { (1<<MACH_FRV), 0 } } } } },
+ /* CPRj: source register */
+ { "CPRj", FRV_OPERAND_CPRJ, HW_H_CPR, 5, 6,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CPRJ] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CPRJ] } },
+ { 0, { { { (1<<MACH_FRV), 0 } } } } },
+ /* CPRk: destination register */
+ { "CPRk", FRV_OPERAND_CPRK, HW_H_CPR, 30, 6,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CPRK] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CPRK] } },
+ { 0, { { { (1<<MACH_FRV), 0 } } } } },
+ /* CPRdoublek: destination register */
+ { "CPRdoublek", FRV_OPERAND_CPRDOUBLEK, HW_H_CPR_DOUBLE, 30, 6,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CPRK] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CPRK] } },
+ { 0, { { { (1<<MACH_FRV), 0 } } } } },
+ /* FRinti: source register 1 */
+ { "FRinti", FRV_OPERAND_FRINTI, HW_H_FR_INT, 17, 6,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* FRintj: source register 2 */
+ { "FRintj", FRV_OPERAND_FRINTJ, HW_H_FR_INT, 5, 6,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* FRintk: target register */
+ { "FRintk", FRV_OPERAND_FRINTK, HW_H_FR_INT, 30, 6,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* FRi: source register 1 */
+ { "FRi", FRV_OPERAND_FRI, HW_H_FR, 17, 6,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* FRj: source register 2 */
+ { "FRj", FRV_OPERAND_FRJ, HW_H_FR, 5, 6,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* FRk: destination register */
+ { "FRk", FRV_OPERAND_FRK, HW_H_FR, 30, 6,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* FRkhi: destination register */
+ { "FRkhi", FRV_OPERAND_FRKHI, HW_H_FR_HI, 30, 6,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* FRklo: destination register */
+ { "FRklo", FRV_OPERAND_FRKLO, HW_H_FR_LO, 30, 6,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* FRdoublei: source register 1 */
+ { "FRdoublei", FRV_OPERAND_FRDOUBLEI, HW_H_FR_DOUBLE, 17, 6,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* FRdoublej: source register 2 */
+ { "FRdoublej", FRV_OPERAND_FRDOUBLEJ, HW_H_FR_DOUBLE, 5, 6,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* FRdoublek: target register */
+ { "FRdoublek", FRV_OPERAND_FRDOUBLEK, HW_H_FR_DOUBLE, 30, 6,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* CRi: source register 1 */
+ { "CRi", FRV_OPERAND_CRI, HW_H_CCCR, 14, 3,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRI] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRI] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* CRj: source register 2 */
+ { "CRj", FRV_OPERAND_CRJ, HW_H_CCCR, 2, 3,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRJ] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRJ] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* CRj_int: destination register */
+ { "CRj_int", FRV_OPERAND_CRJ_INT, HW_H_CCCR, 26, 2,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRJ_INT] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRJ_INT] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* CRj_float: destination register */
+ { "CRj_float", FRV_OPERAND_CRJ_FLOAT, HW_H_CCCR, 26, 2,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRJ_FLOAT] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRJ_FLOAT] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* CRk: destination register */
+ { "CRk", FRV_OPERAND_CRK, HW_H_CCCR, 27, 3,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRK] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRK] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* CCi: condition register */
+ { "CCi", FRV_OPERAND_CCI, HW_H_CCCR, 11, 3,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CCI] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CCI] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* ICCi_1: condition register */
+ { "ICCi_1", FRV_OPERAND_ICCI_1, HW_H_ICCR, 11, 2,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ICCI_1] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ICCI_1] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* ICCi_2: condition register */
+ { "ICCi_2", FRV_OPERAND_ICCI_2, HW_H_ICCR, 26, 2,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ICCI_2] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ICCI_2] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* ICCi_3: condition register */
+ { "ICCi_3", FRV_OPERAND_ICCI_3, HW_H_ICCR, 1, 2,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ICCI_3] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ICCI_3] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* FCCi_1: condition register */
+ { "FCCi_1", FRV_OPERAND_FCCI_1, HW_H_FCCR, 11, 2,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FCCI_1] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FCCI_1] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* FCCi_2: condition register */
+ { "FCCi_2", FRV_OPERAND_FCCI_2, HW_H_FCCR, 26, 2,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FCCI_2] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FCCI_2] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* FCCi_3: condition register */
+ { "FCCi_3", FRV_OPERAND_FCCI_3, HW_H_FCCR, 1, 2,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FCCI_3] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FCCI_3] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* FCCk: condition register */
+ { "FCCk", FRV_OPERAND_FCCK, HW_H_FCCR, 26, 2,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FCCK] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FCCK] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* eir: exception insn reg */
+ { "eir", FRV_OPERAND_EIR, HW_H_UINT, 17, 6,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_EIR] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_EIR] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* s10: 10 bit signed immediate */
+ { "s10", FRV_OPERAND_S10, HW_H_SINT, 9, 10,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S10] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S10] } },
+ { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
+ /* u16: 16 bit unsigned immediate */
+ { "u16", FRV_OPERAND_U16, HW_H_UINT, 15, 16,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U16] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U16] } },
+ { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
+ /* s16: 16 bit signed immediate */
+ { "s16", FRV_OPERAND_S16, HW_H_SINT, 15, 16,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S16] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S16] } },
+ { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
+ /* s6: 6 bit signed immediate */
+ { "s6", FRV_OPERAND_S6, HW_H_SINT, 5, 6,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S6] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S6] } },
+ { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
+ /* s6_1: 6 bit signed immediate */
+ { "s6_1", FRV_OPERAND_S6_1, HW_H_SINT, 11, 6,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S6_1] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S6_1] } },
+ { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
+ /* u6: 6 bit unsigned immediate */
+ { "u6", FRV_OPERAND_U6, HW_H_UINT, 5, 6,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U6] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U6] } },
+ { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
+ /* s5: 5 bit signed immediate */
+ { "s5", FRV_OPERAND_S5, HW_H_SINT, 4, 5,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S5] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S5] } },
+ { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
+ /* cond: conditional arithmetic */
+ { "cond", FRV_OPERAND_COND, HW_H_UINT, 8, 1,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_COND] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_COND] } },
+ { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
+ /* ccond: lr branch condition */
+ { "ccond", FRV_OPERAND_CCOND, HW_H_UINT, 12, 1,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CCOND] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CCOND] } },
+ { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
+ /* hint: 2 bit branch predictor */
+ { "hint", FRV_OPERAND_HINT, HW_H_UINT, 17, 2,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_HINT] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_HINT] } },
+ { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
+ /* hint_taken: 2 bit branch predictor */
+ { "hint_taken", FRV_OPERAND_HINT_TAKEN, HW_H_HINT_TAKEN, 17, 2,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_HINT] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_HINT] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* hint_not_taken: 2 bit branch predictor */
+ { "hint_not_taken", FRV_OPERAND_HINT_NOT_TAKEN, HW_H_HINT_NOT_TAKEN, 17, 2,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_HINT] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_HINT] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* LI: link indicator */
+ { "LI", FRV_OPERAND_LI, HW_H_UINT, 25, 1,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LI] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LI] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* lock: cache lock indicator */
+ { "lock", FRV_OPERAND_LOCK, HW_H_UINT, 25, 1,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LOCK] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LOCK] } },
+ { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
+ /* debug: debug mode indicator */
+ { "debug", FRV_OPERAND_DEBUG, HW_H_UINT, 25, 1,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_DEBUG] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_DEBUG] } },
+ { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
+ /* ae: all entries indicator */
+ { "ae", FRV_OPERAND_AE, HW_H_UINT, 25, 1,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_AE] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_AE] } },
+ { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
+ /* label16: 18 bit pc relative address */
+ { "label16", FRV_OPERAND_LABEL16, HW_H_IADDR, 15, 16,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LABEL16] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LABEL16] } },
+ { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
+ /* LRAE: Load Real Address E flag */
+ { "LRAE", FRV_OPERAND_LRAE, HW_H_UINT, 5, 1,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LRAE] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LRAE] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* LRAD: Load Real Address D flag */
+ { "LRAD", FRV_OPERAND_LRAD, HW_H_UINT, 4, 1,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LRAD] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LRAD] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* LRAS: Load Real Address S flag */
+ { "LRAS", FRV_OPERAND_LRAS, HW_H_UINT, 3, 1,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LRAS] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LRAS] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* TLBPRopx: TLB Probe operation number */
+ { "TLBPRopx", FRV_OPERAND_TLBPROPX, HW_H_UINT, 28, 3,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_TLBPROPX] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_TLBPROPX] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* TLBPRL: TLB Probe L flag */
+ { "TLBPRL", FRV_OPERAND_TLBPRL, HW_H_UINT, 25, 1,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_TLBPRL] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_TLBPRL] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* A0: A==0 operand of mclracc */
+ { "A0", FRV_OPERAND_A0, HW_H_UINT, 17, 1,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_A] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_A] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* A1: A==1 operand of mclracc */
+ { "A1", FRV_OPERAND_A1, HW_H_UINT, 17, 1,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_A] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_A] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* FRintieven: (even) source register 1 */
+ { "FRintieven", FRV_OPERAND_FRINTIEVEN, HW_H_FR_INT, 17, 6,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* FRintjeven: (even) source register 2 */
+ { "FRintjeven", FRV_OPERAND_FRINTJEVEN, HW_H_FR_INT, 5, 6,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* FRintkeven: (even) target register */
+ { "FRintkeven", FRV_OPERAND_FRINTKEVEN, HW_H_FR_INT, 30, 6,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* d12: 12 bit signed immediate */
+ { "d12", FRV_OPERAND_D12, HW_H_SINT, 11, 12,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_D12] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_D12] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* s12: 12 bit signed immediate */
+ { "s12", FRV_OPERAND_S12, HW_H_SINT, 11, 12,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_D12] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_D12] } },
+ { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
+ /* u12: 12 bit signed immediate */
+ { "u12", FRV_OPERAND_U12, HW_H_SINT, 5, 12,
+- { 2, { (const PTR) &FRV_F_U12_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &FRV_F_U12_MULTI_IFIELD[0] } },
+ { 0|A(HASH_PREFIX)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+ /* spr: special purpose register */
+ { "spr", FRV_OPERAND_SPR, HW_H_SPR, 17, 12,
+- { 2, { (const PTR) &FRV_F_SPR_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &FRV_F_SPR_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+ /* ulo16: 16 bit unsigned immediate, for #lo() */
+ { "ulo16", FRV_OPERAND_ULO16, HW_H_UINT, 15, 16,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U16] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U16] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* slo16: 16 bit unsigned immediate, for #lo() */
+ { "slo16", FRV_OPERAND_SLO16, HW_H_SINT, 15, 16,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S16] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S16] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* uhi16: 16 bit unsigned immediate, for #hi() */
+ { "uhi16", FRV_OPERAND_UHI16, HW_H_UINT, 15, 16,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U16] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U16] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* label24: 26 bit pc relative address */
+ { "label24", FRV_OPERAND_LABEL24, HW_H_IADDR, 17, 24,
+- { 2, { (const PTR) &FRV_F_LABEL24_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &FRV_F_LABEL24_MULTI_IFIELD[0] } },
+ { 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+ /* psr_esr: PSR.ESR bit */
+ { "psr_esr", FRV_OPERAND_PSR_ESR, HW_H_PSR_ESR, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* psr_s: PSR.S bit */
+ { "psr_s", FRV_OPERAND_PSR_S, HW_H_PSR_S, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* psr_ps: PSR.PS bit */
+ { "psr_ps", FRV_OPERAND_PSR_PS, HW_H_PSR_PS, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* psr_et: PSR.ET bit */
+ { "psr_et", FRV_OPERAND_PSR_ET, HW_H_PSR_ET, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* bpsr_bs: BPSR.BS bit */
+ { "bpsr_bs", FRV_OPERAND_BPSR_BS, HW_H_BPSR_BS, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* bpsr_bet: BPSR.BET bit */
+ { "bpsr_bet", FRV_OPERAND_BPSR_BET, HW_H_BPSR_BET, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* tbr_tba: TBR.TBA */
+ { "tbr_tba", FRV_OPERAND_TBR_TBA, HW_H_TBR_TBA, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* tbr_tt: TBR.TT */
+ { "tbr_tt", FRV_OPERAND_TBR_TT, HW_H_TBR_TT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* ldann: ld annotation */
+ { "ldann", FRV_OPERAND_LDANN, HW_H_RELOC_ANN, 0, 0,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_RELOC_ANN] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_RELOC_ANN] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* lddann: ldd annotation */
+ { "lddann", FRV_OPERAND_LDDANN, HW_H_RELOC_ANN, 0, 0,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_RELOC_ANN] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_RELOC_ANN] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* callann: call annotation */
+ { "callann", FRV_OPERAND_CALLANN, HW_H_RELOC_ANN, 0, 0,
+- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_RELOC_ANN] } },
++ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_RELOC_ANN] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* sentinel */
+ { 0, 0, 0, 0, 0,
+@@ -6429,7 +6429,7 @@ frv_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
+
+ /* Default to not allowing signed overflow. */
+ cd->signed_overflow_ok_p = 0;
+-
++
+ return (CGEN_CPU_DESC) cd;
+ }
+
+@@ -6469,7 +6469,7 @@ frv_cgen_cpu_close (CGEN_CPU_DESC cd)
+ for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
+ if (CGEN_INSN_RX (insns))
+ regfree (CGEN_INSN_RX (insns));
+- }
++ }
+
+ if (cd->macro_insn_table.init_entries)
+ free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
+--- a/opcodes/frv-dis.c
++++ b/opcodes/frv-dis.c
+@@ -69,7 +69,7 @@ print_at (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ disassemble_info *info = (disassemble_info *) dis_info;
+
+ (*info->fprintf_func) (info->stream, "@");
+-}
++}
+
+ static void
+ print_spr (CGEN_CPU_DESC cd,
+@@ -398,7 +398,7 @@ frv_cgen_print_operand (CGEN_CPU_DESC cd,
+ }
+ }
+
+-cgen_print_fn * const frv_cgen_print_handlers[] =
++cgen_print_fn * const frv_cgen_print_handlers[] =
+ {
+ print_insn_normal,
+ };
+@@ -588,7 +588,7 @@ print_insn (CGEN_CPU_DESC cd,
+ int length;
+ unsigned long insn_value_cropped;
+
+-#ifdef CGEN_VALIDATE_INSN_SUPPORTED
++#ifdef CGEN_VALIDATE_INSN_SUPPORTED
+ /* Not needed as insn shouldn't be in hash lists if not supported. */
+ /* Supported by this cpu? */
+ if (! frv_cgen_insn_supported (cd, insn))
+@@ -606,7 +606,7 @@ print_insn (CGEN_CPU_DESC cd,
+ relevant part from the buffer. */
+ if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
+ (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
+- insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
++ insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
+ info->endian == BFD_ENDIAN_BIG);
+ else
+ insn_value_cropped = insn_value;
+@@ -725,7 +725,7 @@ print_insn_frv (bfd_vma pc, disassemble_info *info)
+ arch = info->arch;
+ if (arch == bfd_arch_unknown)
+ arch = CGEN_BFD_ARCH;
+-
++
+ /* There's no standard way to compute the machine or isa number
+ so we leave it to the target. */
+ #ifdef CGEN_COMPUTE_MACH
+@@ -766,7 +766,7 @@ print_insn_frv (bfd_vma pc, disassemble_info *info)
+ break;
+ }
+ }
+- }
++ }
+
+ /* If we haven't initialized yet, initialize the opcode table. */
+ if (! cd)
+--- a/opcodes/frv-ibld.c
++++ b/opcodes/frv-ibld.c
+@@ -154,7 +154,7 @@ insert_normal (CGEN_CPU_DESC cd,
+ {
+ long minval = - (1L << (length - 1));
+ unsigned long maxval = mask;
+-
++
+ if ((value > 0 && (unsigned long) value > maxval)
+ || value < minval)
+ {
+@@ -192,7 +192,7 @@ insert_normal (CGEN_CPU_DESC cd,
+ {
+ long minval = - (1L << (length - 1));
+ long maxval = (1L << (length - 1)) - 1;
+-
++
+ if (value < minval || value > maxval)
+ {
+ sprintf
+@@ -1174,12 +1174,12 @@ frv_cgen_extract_operand (CGEN_CPU_DESC cd,
+ return length;
+ }
+
+-cgen_insert_fn * const frv_cgen_insert_handlers[] =
++cgen_insert_fn * const frv_cgen_insert_handlers[] =
+ {
+ insert_insn_normal,
+ };
+
+-cgen_extract_fn * const frv_cgen_extract_handlers[] =
++cgen_extract_fn * const frv_cgen_extract_handlers[] =
+ {
+ extract_insn_normal,
+ };
+--- a/opcodes/frv-opc.c
++++ b/opcodes/frv-opc.c
+@@ -234,7 +234,7 @@ static CGEN_ATTR_VALUE_ENUM_TYPE fr400_unit_mapping[] =
+ /* NIL */ UNIT_NIL,
+ /* I0 */ UNIT_I0,
+ /* I1 */ UNIT_I1,
+-/* I01 */ UNIT_I01,
++/* I01 */ UNIT_I01,
+ /* I2 */ UNIT_NIL, /* no I2 or I3 unit */
+ /* I3 */ UNIT_NIL,
+ /* IALL */ UNIT_I01, /* only I0 and I1 units */
+@@ -269,7 +269,7 @@ static CGEN_ATTR_VALUE_ENUM_TYPE fr450_unit_mapping[] =
+ /* NIL */ UNIT_NIL,
+ /* I0 */ UNIT_I0,
+ /* I1 */ UNIT_I1,
+-/* I01 */ UNIT_I01,
++/* I01 */ UNIT_I01,
+ /* I2 */ UNIT_NIL, /* no I2 or I3 unit */
+ /* I3 */ UNIT_NIL,
+ /* IALL */ UNIT_I01, /* only I0 and I1 units */
+@@ -301,7 +301,7 @@ static CGEN_ATTR_VALUE_ENUM_TYPE fr500_unit_mapping[] =
+ /* NIL */ UNIT_NIL,
+ /* I0 */ UNIT_I0,
+ /* I1 */ UNIT_I1,
+-/* I01 */ UNIT_I01,
++/* I01 */ UNIT_I01,
+ /* I2 */ UNIT_NIL, /* no I2 or I3 unit */
+ /* I3 */ UNIT_NIL,
+ /* IALL */ UNIT_I01, /* only I0 and I1 units */
+@@ -333,10 +333,10 @@ static CGEN_ATTR_VALUE_ENUM_TYPE fr550_unit_mapping[] =
+ /* NIL */ UNIT_NIL,
+ /* I0 */ UNIT_I0,
+ /* I1 */ UNIT_I1,
+-/* I01 */ UNIT_I01,
++/* I01 */ UNIT_I01,
+ /* I2 */ UNIT_I2,
+ /* I3 */ UNIT_I3,
+-/* IALL */ UNIT_IALL,
++/* IALL */ UNIT_IALL,
+ /* FM0 */ UNIT_FM0,
+ /* FM1 */ UNIT_FM1,
+ /* FM01 */ UNIT_FM01,
+--- a/opcodes/h8300-dis.c
++++ b/opcodes/h8300-dis.c
+@@ -269,14 +269,14 @@ print_one_arg (disassemble_info *info,
+ {
+ outfn (stream, ".%s%d (0x%lx)",
+ (short) cst > 0 ? "+" : "",
+- (short) cst,
++ (short) cst,
+ (long)(addr + (short) cst + len));
+ }
+ else
+ {
+ outfn (stream, ".%s%d (0x%lx)",
+ (char) cst > 0 ? "+" : "",
+- (char) cst,
++ (char) cst,
+ (long)(addr + (char) cst + len));
+ }
+ }
+@@ -285,12 +285,12 @@ print_one_arg (disassemble_info *info,
+
+ else if ((x & MODE) == INDEXB)
+ /* Always take low half of reg. */
+- outfn (stream, "@(0x%x:%d,%s.b)", cst, cstlen,
++ outfn (stream, "@(0x%x:%d,%s.b)", cst, cstlen,
+ regnames[rdisp_n < 8 ? rdisp_n + 8 : rdisp_n]);
+
+ else if ((x & MODE) == INDEXW)
+ /* Always take low half of reg. */
+- outfn (stream, "@(0x%x:%d,%s.w)", cst, cstlen,
++ outfn (stream, "@(0x%x:%d,%s.w)", cst, cstlen,
+ wregnames[rdisp_n < 8 ? rdisp_n : rdisp_n - 8]);
+
+ else if ((x & MODE) == INDEXL)
+@@ -460,8 +460,8 @@ bfd_h8_disassemble (bfd_vma addr, disassemble_info *info, int mach)
+ || (looking_for & MODE) == INDEXW
+ || (looking_for & MODE) == INDEXL)
+ {
+- extract_immediate (stream, looking_for, thisnib,
+- data + len / 2, cst + opnr,
++ extract_immediate (stream, looking_for, thisnib,
++ data + len / 2, cst + opnr,
+ cstlen + opnr, q);
+ /* Even address == bra, odd == bra/s. */
+ if (q->how == O (O_BRAS, SB))
+@@ -529,8 +529,8 @@ bfd_h8_disassemble (bfd_vma addr, disassemble_info *info, int mach)
+ {
+ int i = len / 2;
+
+- cst[opnr] = ((data[i] << 24)
+- | (data[i + 1] << 16)
++ cst[opnr] = ((data[i] << 24)
++ | (data[i + 1] << 16)
+ | (data[i + 2] << 8)
+ | (data[i + 3]));
+
+@@ -540,7 +540,7 @@ bfd_h8_disassemble (bfd_vma addr, disassemble_info *info, int mach)
+ {
+ int i = len / 2;
+
+- cst[opnr] =
++ cst[opnr] =
+ (data[i] << 16) | (data[i + 1] << 8) | (data[i + 2]);
+ cstlen[opnr] = 24;
+ }
+@@ -633,21 +633,21 @@ bfd_h8_disassemble (bfd_vma addr, disassemble_info *info, int mach)
+ if (args[1] == (op_type) E)
+ {
+ /* Short form. */
+- print_one_arg (info, addr, args[0], cst[0],
+- cstlen[0], dispregno[0], regno[0],
++ print_one_arg (info, addr, args[0], cst[0],
++ cstlen[0], dispregno[0], regno[0],
+ pregnames, qi->length);
+ outfn (stream, ",er%d", dispregno[0]);
+ }
+ else
+ {
+ outfn (stream, "@(0x%x:%d,", cst[0], cstlen[0]);
+- print_one_arg (info, addr, args[1], cst[1],
+- cstlen[1], dispregno[1], regno[1],
++ print_one_arg (info, addr, args[1], cst[1],
++ cstlen[1], dispregno[1], regno[1],
+ pregnames, qi->length);
+ outfn (stream, ".%c),",
+ (args[0] & MODE) == INDEXB ? 'b' : 'w');
+- print_one_arg (info, addr, args[2], cst[2],
+- cstlen[2], dispregno[2], regno[2],
++ print_one_arg (info, addr, args[2], cst[2],
++ cstlen[2], dispregno[2], regno[2],
+ pregnames, qi->length);
+ }
+ return qi->length;
+@@ -669,7 +669,7 @@ bfd_h8_disassemble (bfd_vma addr, disassemble_info *info, int mach)
+ return qi->length;
+ }
+
+- for (nargs = 0;
++ for (nargs = 0;
+ nargs < 3 && args[nargs] != (op_type) E;
+ nargs++)
+ {
+--- a/opcodes/i370-opc.c
++++ b/opcodes/i370-opc.c
+@@ -257,7 +257,7 @@ const struct i370_operand i370_operands[] =
+ #define SS_D2 (SS_B2 + 1)
+ #define SS_D2_MASK (0xfff)
+ { 12, 0, insert_ss_d2, extract_ss_d2, I370_OPERAND_RELATIVE, "SS D2" },
+-
++
+ };
+
+
+#--- a/opcodes/i386-opc.h
+#+++ b/opcodes/i386-opc.h
+#@@ -196,7 +196,7 @@ enum
+# CpuAVX512VBMI,
+# /* mwaitx instruction required */
+# CpuMWAITX,
+#- /* Clzero instruction required */
+#+ /* Clzero instruction required */
+# CpuCLZERO,
+# /* 64bit support required */
+# Cpu64,
+--- a/opcodes/i860-dis.c
++++ b/opcodes/i860-dis.c
+@@ -28,14 +28,14 @@
+ #define I860_REG_PREFIX "%"
+
+ /* Integer register names (encoded as 0..31 in the instruction). */
+-static const char *const grnames[] =
++static const char *const grnames[] =
+ {"r0", "r1", "sp", "fp", "r4", "r5", "r6", "r7",
+ "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
+ "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
+ "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"};
+
+ /* FP register names (encoded as 0..31 in the instruction). */
+-static const char *const frnames[] =
++static const char *const frnames[] =
+ {"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
+ "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
+ "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
+@@ -43,7 +43,7 @@ static const char *const frnames[] =
+
+ /* Control/status register names (encoded as 0..11 in the instruction).
+ Registers bear, ccr, p0, p1, p2 and p3 are XP only. */
+-static const char *const crnames[] =
++static const char *const crnames[] =
+ {"fir", "psr", "dirbase", "db", "fsr", "epsr", "bear", "ccr",
+ "p0", "p1", "p2", "p3", "--", "--", "--", "--" };
+
+@@ -78,9 +78,9 @@ print_br_address (disassemble_info *info, bfd_vma memaddr, long val)
+ long adj = (long)memaddr + 4 + (val << 2);
+
+ (*info->fprintf_func) (info->stream, "0x%08lx", adj);
+-
++
+ /* Attempt to obtain a symbol for the target address. */
+-
++
+ if (info->print_address_func && adj != 0)
+ {
+ (*info->fprintf_func) (info->stream, "\t// ");
+@@ -134,7 +134,7 @@ print_insn_i860 (bfd_vma memaddr, disassemble_info *info)
+ int val;
+
+ /* If this a flop (or a shrd) and its dual bit is set,
+- prefix with 'd.'. */
++ prefix with 'd.'. */
+ if (((insn & 0xfc000000) == 0x48000000
+ || (insn & 0xfc000000) == 0xb0000000)
+ && (insn & 0x200))
+--- a/opcodes/ia64-asmtab.c
++++ b/opcodes/ia64-asmtab.c
+@@ -413,1379 +413,1379 @@ dependencies[] = {
+ };
+
+ static const unsigned short dep0[] = {
+- 100, 288, 2143, 2333,
++ 100, 288, 2143, 2333,
+ };
+
+ static const unsigned short dep1[] = {
+- 41, 42, 100, 161, 165, 178, 188, 288, 2141, 2142, 2143, 2169, 2170, 2173,
+- 2176, 2333, 4136, 20619,
++ 41, 42, 100, 161, 165, 178, 188, 288, 2141, 2142, 2143, 2169, 2170, 2173,
++ 2176, 2333, 4136, 20619,
+ };
+
+ static const unsigned short dep2[] = {
+- 100, 288, 2169, 2170, 2172, 2173, 2175, 2176, 2178, 2350, 2353, 2354, 2357,
+- 2358, 2361, 2362,
++ 100, 288, 2169, 2170, 2172, 2173, 2175, 2176, 2178, 2350, 2353, 2354, 2357,
++ 2358, 2361, 2362,
+ };
+
+ static const unsigned short dep3[] = {
+- 41, 42, 100, 161, 165, 178, 188, 288, 2141, 2142, 2143, 2169, 2170, 2173,
+- 2176, 2350, 2353, 2354, 2357, 2358, 2361, 2362, 4136, 20619,
++ 41, 42, 100, 161, 165, 178, 188, 288, 2141, 2142, 2143, 2169, 2170, 2173,
++ 2176, 2350, 2353, 2354, 2357, 2358, 2361, 2362, 4136, 20619,
+ };
+
+ static const unsigned short dep4[] = {
+- 100, 288, 22649, 22650, 22652, 22653, 22655, 22656, 22658, 22830, 22833, 22834,
+- 22837, 22838, 22841, 22842,
++ 100, 288, 22649, 22650, 22652, 22653, 22655, 22656, 22658, 22830, 22833, 22834,
++ 22837, 22838, 22841, 22842,
+ };
+
+ static const unsigned short dep5[] = {
+- 41, 42, 100, 161, 165, 178, 188, 288, 2141, 2142, 2143, 2169, 2170, 2173,
+- 2176, 4136, 20619, 22830, 22833, 22834, 22837, 22838, 22841, 22842,
++ 41, 42, 100, 161, 165, 178, 188, 288, 2141, 2142, 2143, 2169, 2170, 2173,
++ 2176, 4136, 20619, 22830, 22833, 22834, 22837, 22838, 22841, 22842,
+ };
+
+ static const unsigned short dep6[] = {
+- 100, 288, 2169, 2170, 2172, 2173, 2175, 2176, 2178, 2350, 2351, 2353, 2355,
+- 2357, 2359, 2361,
++ 100, 288, 2169, 2170, 2172, 2173, 2175, 2176, 2178, 2350, 2351, 2353, 2355,
++ 2357, 2359, 2361,
+ };
+
+ static const unsigned short dep7[] = {
+- 41, 42, 100, 161, 165, 178, 188, 288, 2141, 2142, 2143, 2169, 2170, 2173,
+- 2176, 2350, 2351, 2354, 2355, 2358, 2359, 2362, 4136, 20619,
++ 41, 42, 100, 161, 165, 178, 188, 288, 2141, 2142, 2143, 2169, 2170, 2173,
++ 2176, 2350, 2351, 2354, 2355, 2358, 2359, 2362, 4136, 20619,
+ };
+
+ static const unsigned short dep8[] = {
+- 100, 288, 2169, 2170, 2172, 2173, 2175, 2176, 2178, 2350, 2352, 2354, 2356,
+- 2358, 2360, 2362,
++ 100, 288, 2169, 2170, 2172, 2173, 2175, 2176, 2178, 2350, 2352, 2354, 2356,
++ 2358, 2360, 2362,
+ };
+
+ static const unsigned short dep9[] = {
+- 41, 42, 100, 161, 165, 178, 188, 288, 2141, 2142, 2143, 2169, 2170, 2173,
+- 2176, 2350, 2352, 2353, 2356, 2357, 2360, 2361, 4136, 20619,
++ 41, 42, 100, 161, 165, 178, 188, 288, 2141, 2142, 2143, 2169, 2170, 2173,
++ 2176, 2350, 2352, 2353, 2356, 2357, 2360, 2361, 4136, 20619,
+ };
+
+ static const unsigned short dep10[] = {
+- 100, 288, 2169, 2170, 2172, 2173, 2175, 2176, 2178, 2350, 2351, 2352, 2353,
+- 2354, 2355, 2356, 2357, 2358, 2359, 2360, 2361, 2362,
++ 100, 288, 2169, 2170, 2172, 2173, 2175, 2176, 2178, 2350, 2351, 2352, 2353,
++ 2354, 2355, 2356, 2357, 2358, 2359, 2360, 2361, 2362,
+ };
+
+ static const unsigned short dep11[] = {
+- 41, 42, 100, 161, 165, 178, 188, 288, 2141, 2142, 2143, 2169, 2170, 2173,
+- 2176, 2350, 2351, 2352, 2353, 2354, 2355, 2356, 2357, 2358, 2359, 2360, 2361,
+- 2362, 4136, 20619,
++ 41, 42, 100, 161, 165, 178, 188, 288, 2141, 2142, 2143, 2169, 2170, 2173,
++ 2176, 2350, 2351, 2352, 2353, 2354, 2355, 2356, 2357, 2358, 2359, 2360, 2361,
++ 2362, 4136, 20619,
+ };
+
+ static const unsigned short dep12[] = {
+- 100, 288, 2401,
++ 100, 288, 2401,
+ };
+
+ static const unsigned short dep13[] = {
+- 41, 42, 100, 161, 165, 167, 178, 188, 189, 191, 288, 2083, 2084, 2169, 2171,
+- 2172, 2174, 2175, 2177, 2178, 4136,
++ 41, 42, 100, 161, 165, 167, 178, 188, 189, 191, 288, 2083, 2084, 2169, 2171,
++ 2172, 2174, 2175, 2177, 2178, 4136,
+ };
+
+ static const unsigned short dep14[] = {
+- 100, 166, 288, 331, 2401, 28869, 29024,
++ 100, 166, 288, 331, 2401, 28869, 29024,
+ };
+
+ static const unsigned short dep15[] = {
+- 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21,
+- 22, 23, 24, 25, 26, 28, 29, 30, 31, 32, 33, 34, 41, 42, 100, 153, 155, 161,
+- 165, 167, 178, 188, 189, 191, 288, 331, 2083, 2084, 2169, 2171, 2172, 2174,
+- 2175, 2177, 2178, 4136, 28869, 29024,
++ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21,
++ 22, 23, 24, 25, 26, 28, 29, 30, 31, 32, 33, 34, 41, 42, 100, 153, 155, 161,
++ 165, 167, 178, 188, 189, 191, 288, 331, 2083, 2084, 2169, 2171, 2172, 2174,
++ 2175, 2177, 2178, 4136, 28869, 29024,
+ };
+
+ static const unsigned short dep16[] = {
+- 1, 6, 41, 77, 100, 140, 199, 204, 245, 272, 288, 318, 2401, 28869, 29024,
+-
++ 1, 6, 41, 77, 100, 140, 199, 204, 245, 272, 288, 318, 2401, 28869, 29024,
++
+ };
+
+ static const unsigned short dep17[] = {
+- 1, 25, 27, 39, 41, 42, 100, 161, 165, 167, 169, 170, 178, 188, 189, 191, 199,
+- 204, 245, 272, 288, 318, 2083, 2084, 2169, 2171, 2172, 2174, 2175, 2177, 2178,
+- 4136, 28869, 29024,
++ 1, 25, 27, 39, 41, 42, 100, 161, 165, 167, 169, 170, 178, 188, 189, 191, 199,
++ 204, 245, 272, 288, 318, 2083, 2084, 2169, 2171, 2172, 2174, 2175, 2177, 2178,
++ 4136, 28869, 29024,
+ };
+
+ static const unsigned short dep18[] = {
+- 1, 41, 52, 100, 199, 245, 252, 288, 28869, 29024,
++ 1, 41, 52, 100, 199, 245, 252, 288, 28869, 29024,
+ };
+
+ static const unsigned short dep19[] = {
+- 1, 39, 41, 42, 100, 161, 163, 164, 165, 178, 188, 193, 194, 199, 245, 252,
+- 288, 4136, 28869, 29024,
++ 1, 39, 41, 42, 100, 161, 163, 164, 165, 178, 188, 193, 194, 199, 245, 252,
++ 288, 4136, 28869, 29024,
+ };
+
+ static const unsigned short dep20[] = {
+- 41, 100, 245, 288,
++ 41, 100, 245, 288,
+ };
+
+ static const unsigned short dep21[] = {
+- 100, 161, 165, 178, 188, 245, 288,
++ 100, 161, 165, 178, 188, 245, 288,
+ };
+
+ static const unsigned short dep22[] = {
+- 1, 41, 100, 134, 138, 139, 141, 142, 145, 146, 149, 152, 155, 158, 159, 160,
+- 161, 164, 165, 166, 167, 170, 171, 172, 173, 176, 177, 178, 181, 184, 187,
+- 188, 191, 192, 194, 199, 245, 272, 288, 315, 316, 317, 318, 319, 320, 321,
+- 322, 323, 324, 325, 326, 327, 328, 329, 330, 331, 332, 333, 334, 336, 337,
+- 339, 340, 341, 342, 343, 344, 345, 346, 347, 348, 349, 350, 28869, 29024,
+-
++ 1, 41, 100, 134, 138, 139, 141, 142, 145, 146, 149, 152, 155, 158, 159, 160,
++ 161, 164, 165, 166, 167, 170, 171, 172, 173, 176, 177, 178, 181, 184, 187,
++ 188, 191, 192, 194, 199, 245, 272, 288, 315, 316, 317, 318, 319, 320, 321,
++ 322, 323, 324, 325, 326, 327, 328, 329, 330, 331, 332, 333, 334, 336, 337,
++ 339, 340, 341, 342, 343, 344, 345, 346, 347, 348, 349, 350, 28869, 29024,
++
+ };
+
+ static const unsigned short dep23[] = {
+- 1, 39, 41, 42, 51, 52, 57, 60, 75, 100, 140, 141, 161, 165, 178, 188, 193,
+- 194, 199, 245, 272, 288, 315, 316, 317, 318, 319, 320, 321, 322, 323, 324,
+- 325, 326, 327, 328, 329, 330, 331, 332, 333, 334, 336, 337, 339, 340, 341,
+- 342, 343, 344, 345, 346, 347, 348, 349, 350, 4136, 28869, 29024,
++ 1, 39, 41, 42, 51, 52, 57, 60, 75, 100, 140, 141, 161, 165, 178, 188, 193,
++ 194, 199, 245, 272, 288, 315, 316, 317, 318, 319, 320, 321, 322, 323, 324,
++ 325, 326, 327, 328, 329, 330, 331, 332, 333, 334, 336, 337, 339, 340, 341,
++ 342, 343, 344, 345, 346, 347, 348, 349, 350, 4136, 28869, 29024,
+ };
+
+ static const unsigned short dep24[] = {
+- 100, 139, 288, 317,
++ 100, 139, 288, 317,
+ };
+
+ static const unsigned short dep25[] = {
+- 100, 140, 141, 161, 165, 178, 188, 193, 194, 288, 317,
++ 100, 140, 141, 161, 165, 178, 188, 193, 194, 288, 317,
+ };
+
+ static const unsigned short dep26[] = {
+- 100, 140, 288, 318,
++ 100, 140, 288, 318,
+ };
+
+ static const unsigned short dep27[] = {
+- 25, 26, 100, 101, 104, 108, 111, 140, 141, 161, 165, 167, 178, 188, 288, 318,
+-
++ 25, 26, 100, 101, 104, 108, 111, 140, 141, 161, 165, 167, 178, 188, 288, 318,
++
+ };
+
+ static const unsigned short dep28[] = {
+- 100, 193, 288, 350,
++ 100, 193, 288, 350,
+ };
+
+ static const unsigned short dep29[] = {
+- 100, 101, 104, 108, 111, 140, 141, 161, 165, 167, 178, 188, 288, 350,
++ 100, 101, 104, 108, 111, 140, 141, 161, 165, 167, 178, 188, 288, 350,
+ };
+
+ static const unsigned short dep30[] = {
+- 41, 42, 100, 161, 165, 178, 188, 288, 2169, 2171, 2172, 2174, 2175, 2177,
+- 2178, 4136,
++ 41, 42, 100, 161, 165, 178, 188, 288, 2169, 2171, 2172, 2174, 2175, 2177,
++ 2178, 4136,
+ };
+
+ static const unsigned short dep31[] = {
+- 1, 25, 41, 77, 100, 199, 231, 232, 245, 272, 288, 2083, 2289, 2292, 2401,
+- 28869, 29024,
++ 1, 25, 41, 77, 100, 199, 231, 232, 245, 272, 288, 2083, 2289, 2292, 2401,
++ 28869, 29024,
+ };
+
+ static const unsigned short dep32[] = {
+- 1, 6, 39, 41, 42, 77, 100, 140, 141, 161, 165, 167, 178, 188, 189, 191, 199,
+- 231, 233, 245, 272, 288, 2083, 2084, 2169, 2171, 2172, 2174, 2175, 2177, 2178,
+- 2290, 2292, 4136, 28869, 29024,
++ 1, 6, 39, 41, 42, 77, 100, 140, 141, 161, 165, 167, 178, 188, 189, 191, 199,
++ 231, 233, 245, 272, 288, 2083, 2084, 2169, 2171, 2172, 2174, 2175, 2177, 2178,
++ 2290, 2292, 4136, 28869, 29024,
+ };
+
+ static const unsigned short dep33[] = {
+- 100, 288,
++ 100, 288,
+ };
+
+ static const unsigned short dep34[] = {
+- 100, 161, 165, 178, 188, 288, 2083, 2085,
++ 100, 161, 165, 178, 188, 288, 2083, 2085,
+ };
+
+ static const unsigned short dep35[] = {
+- 41, 42, 100, 161, 165, 167, 178, 188, 189, 191, 288, 2169, 2171, 2172, 2174,
+- 2175, 2177, 2178, 4136,
++ 41, 42, 100, 161, 165, 167, 178, 188, 189, 191, 288, 2169, 2171, 2172, 2174,
++ 2175, 2177, 2178, 4136,
+ };
+
+ static const unsigned short dep36[] = {
+- 6, 38, 39, 40, 100, 128, 129, 204, 245, 288, 313, 314, 2401,
++ 6, 38, 39, 40, 100, 128, 129, 204, 245, 288, 313, 314, 2401,
+ };
+
+ static const unsigned short dep37[] = {
+- 6, 38, 41, 42, 100, 161, 165, 167, 178, 188, 189, 191, 204, 245, 288, 313,
+- 314, 353, 2169, 2171, 2172, 2174, 2175, 2177, 2178, 4136,
++ 6, 38, 41, 42, 100, 161, 165, 167, 178, 188, 189, 191, 204, 245, 288, 313,
++ 314, 353, 2169, 2171, 2172, 2174, 2175, 2177, 2178, 4136,
+ };
+
+ static const unsigned short dep38[] = {
+- 24, 100, 230, 288, 2401,
++ 24, 100, 230, 288, 2401,
+ };
+
+ static const unsigned short dep39[] = {
+- 24, 41, 42, 100, 161, 165, 167, 178, 188, 189, 191, 230, 288, 2169, 2171,
+- 2172, 2174, 2175, 2177, 2178, 4136,
++ 24, 41, 42, 100, 161, 165, 167, 178, 188, 189, 191, 230, 288, 2169, 2171,
++ 2172, 2174, 2175, 2177, 2178, 4136,
+ };
+
+ static const unsigned short dep40[] = {
+- 6, 24, 38, 39, 40, 100, 128, 129, 204, 230, 245, 288, 313, 314, 2401,
++ 6, 24, 38, 39, 40, 100, 128, 129, 204, 230, 245, 288, 313, 314, 2401,
+ };
+
+ static const unsigned short dep41[] = {
+- 6, 24, 38, 41, 42, 100, 161, 165, 167, 178, 188, 189, 191, 204, 230, 245,
+- 288, 313, 314, 353, 2169, 2171, 2172, 2174, 2175, 2177, 2178, 4136,
++ 6, 24, 38, 41, 42, 100, 161, 165, 167, 178, 188, 189, 191, 204, 230, 245,
++ 288, 313, 314, 353, 2169, 2171, 2172, 2174, 2175, 2177, 2178, 4136,
+ };
+
+ static const unsigned short dep42[] = {
+- 1, 6, 39, 41, 42, 77, 100, 140, 141, 161, 165, 167, 178, 188, 189, 191, 199,
+- 231, 233, 245, 272, 288, 2169, 2171, 2172, 2174, 2175, 2177, 2178, 2290, 2292,
+- 4136, 28869, 29024,
++ 1, 6, 39, 41, 42, 77, 100, 140, 141, 161, 165, 167, 178, 188, 189, 191, 199,
++ 231, 233, 245, 272, 288, 2169, 2171, 2172, 2174, 2175, 2177, 2178, 2290, 2292,
++ 4136, 28869, 29024,
+ };
+
+ static const unsigned short dep43[] = {
+- 100, 161, 165, 178, 188, 288,
++ 100, 161, 165, 178, 188, 288,
+ };
+
+ static const unsigned short dep44[] = {
+- 15, 100, 213, 214, 288, 2139, 2331, 18604, 18605, 18767, 18768, 18770, 18771,
+- 22649, 22650, 22651, 22653, 22654, 22656, 22657, 22830, 22833, 22834, 22837,
+- 22838, 22841, 22842,
++ 15, 100, 213, 214, 288, 2139, 2331, 18604, 18605, 18767, 18768, 18770, 18771,
++ 22649, 22650, 22651, 22653, 22654, 22656, 22657, 22830, 22833, 22834, 22837,
++ 22838, 22841, 22842,
+ };
+
+ static const unsigned short dep45[] = {
+- 11, 19, 20, 41, 42, 100, 161, 165, 178, 188, 213, 215, 288, 2138, 2139, 2140,
+- 2169, 2170, 2173, 2176, 2331, 4136, 16531, 16533, 16534, 16536, 18767, 18769,
+- 18770, 18772, 22830, 22833, 22834, 22837, 22838, 22841, 22842,
++ 11, 19, 20, 41, 42, 100, 161, 165, 178, 188, 213, 215, 288, 2138, 2139, 2140,
++ 2169, 2170, 2173, 2176, 2331, 4136, 16531, 16533, 16534, 16536, 18767, 18769,
++ 18770, 18772, 22830, 22833, 22834, 22837, 22838, 22841, 22842,
+ };
+
+ static const unsigned short dep46[] = {
+- 15, 16, 17, 18, 100, 213, 214, 216, 217, 219, 220, 222, 223, 288, 2139, 2331,
+- 18604, 18605, 18767, 18768, 18770, 18771, 22649, 22650, 22651, 22653, 22654,
+- 22656, 22657, 22830, 22833, 22834, 22837, 22838, 22841, 22842,
++ 15, 16, 17, 18, 100, 213, 214, 216, 217, 219, 220, 222, 223, 288, 2139, 2331,
++ 18604, 18605, 18767, 18768, 18770, 18771, 22649, 22650, 22651, 22653, 22654,
++ 22656, 22657, 22830, 22833, 22834, 22837, 22838, 22841, 22842,
+ };
+
+ static const unsigned short dep47[] = {
+- 11, 12, 13, 14, 19, 20, 41, 42, 100, 161, 165, 178, 188, 213, 215, 216, 218,
+- 219, 221, 222, 224, 288, 2138, 2139, 2140, 2169, 2170, 2173, 2176, 2331, 4136,
+- 16531, 16533, 16534, 16536, 18767, 18769, 18770, 18772, 22830, 22833, 22834,
+- 22837, 22838, 22841, 22842,
++ 11, 12, 13, 14, 19, 20, 41, 42, 100, 161, 165, 178, 188, 213, 215, 216, 218,
++ 219, 221, 222, 224, 288, 2138, 2139, 2140, 2169, 2170, 2173, 2176, 2331, 4136,
++ 16531, 16533, 16534, 16536, 18767, 18769, 18770, 18772, 22830, 22833, 22834,
++ 22837, 22838, 22841, 22842,
+ };
+
+ static const unsigned short dep48[] = {
+- 16, 100, 216, 217, 288, 2139, 2331, 18604, 18605, 18767, 18768, 18770, 18771,
+- 22649, 22650, 22651, 22653, 22654, 22656, 22657, 22830, 22833, 22834, 22837,
+- 22838, 22841, 22842,
++ 16, 100, 216, 217, 288, 2139, 2331, 18604, 18605, 18767, 18768, 18770, 18771,
++ 22649, 22650, 22651, 22653, 22654, 22656, 22657, 22830, 22833, 22834, 22837,
++ 22838, 22841, 22842,
+ };
+
+ static const unsigned short dep49[] = {
+- 12, 19, 20, 41, 42, 100, 161, 165, 178, 188, 216, 218, 288, 2138, 2139, 2140,
+- 2169, 2170, 2173, 2176, 2331, 4136, 16531, 16533, 16534, 16536, 18767, 18769,
+- 18770, 18772, 22830, 22833, 22834, 22837, 22838, 22841, 22842,
++ 12, 19, 20, 41, 42, 100, 161, 165, 178, 188, 216, 218, 288, 2138, 2139, 2140,
++ 2169, 2170, 2173, 2176, 2331, 4136, 16531, 16533, 16534, 16536, 18767, 18769,
++ 18770, 18772, 22830, 22833, 22834, 22837, 22838, 22841, 22842,
+ };
+
+ static const unsigned short dep50[] = {
+- 17, 100, 219, 220, 288, 2139, 2331, 18604, 18605, 18767, 18768, 18770, 18771,
+- 22649, 22650, 22651, 22653, 22654, 22656, 22657, 22830, 22833, 22834, 22837,
+- 22838, 22841, 22842,
++ 17, 100, 219, 220, 288, 2139, 2331, 18604, 18605, 18767, 18768, 18770, 18771,
++ 22649, 22650, 22651, 22653, 22654, 22656, 22657, 22830, 22833, 22834, 22837,
++ 22838, 22841, 22842,
+ };
+
+ static const unsigned short dep51[] = {
+- 13, 19, 20, 41, 42, 100, 161, 165, 178, 188, 219, 221, 288, 2138, 2139, 2140,
+- 2169, 2170, 2173, 2176, 2331, 4136, 16531, 16533, 16534, 16536, 18767, 18769,
+- 18770, 18772, 22830, 22833, 22834, 22837, 22838, 22841, 22842,
++ 13, 19, 20, 41, 42, 100, 161, 165, 178, 188, 219, 221, 288, 2138, 2139, 2140,
++ 2169, 2170, 2173, 2176, 2331, 4136, 16531, 16533, 16534, 16536, 18767, 18769,
++ 18770, 18772, 22830, 22833, 22834, 22837, 22838, 22841, 22842,
+ };
+
+ static const unsigned short dep52[] = {
+- 18, 100, 222, 223, 288, 2139, 2331, 18604, 18605, 18767, 18768, 18770, 18771,
+- 22649, 22650, 22651, 22653, 22654, 22656, 22657, 22830, 22833, 22834, 22837,
+- 22838, 22841, 22842,
++ 18, 100, 222, 223, 288, 2139, 2331, 18604, 18605, 18767, 18768, 18770, 18771,
++ 22649, 22650, 22651, 22653, 22654, 22656, 22657, 22830, 22833, 22834, 22837,
++ 22838, 22841, 22842,
+ };
+
+ static const unsigned short dep53[] = {
+- 14, 19, 20, 41, 42, 100, 161, 165, 178, 188, 222, 224, 288, 2138, 2139, 2140,
+- 2169, 2170, 2173, 2176, 2331, 4136, 16531, 16533, 16534, 16536, 18767, 18769,
+- 18770, 18772, 22830, 22833, 22834, 22837, 22838, 22841, 22842,
++ 14, 19, 20, 41, 42, 100, 161, 165, 178, 188, 222, 224, 288, 2138, 2139, 2140,
++ 2169, 2170, 2173, 2176, 2331, 4136, 16531, 16533, 16534, 16536, 18767, 18769,
++ 18770, 18772, 22830, 22833, 22834, 22837, 22838, 22841, 22842,
+ };
+
+ static const unsigned short dep54[] = {
+- 15, 100, 213, 214, 288, 2139, 2331, 18604, 18605, 18767, 18768, 18770, 18771,
+-
++ 15, 100, 213, 214, 288, 2139, 2331, 18604, 18605, 18767, 18768, 18770, 18771,
++
+ };
+
+ static const unsigned short dep55[] = {
+- 11, 19, 20, 41, 42, 100, 161, 165, 178, 188, 213, 215, 288, 2138, 2139, 2140,
+- 2169, 2170, 2173, 2176, 2331, 4136, 16531, 16533, 16534, 16536, 18767, 18769,
+- 18770, 18772,
++ 11, 19, 20, 41, 42, 100, 161, 165, 178, 188, 213, 215, 288, 2138, 2139, 2140,
++ 2169, 2170, 2173, 2176, 2331, 4136, 16531, 16533, 16534, 16536, 18767, 18769,
++ 18770, 18772,
+ };
+
+ static const unsigned short dep56[] = {
+- 15, 16, 17, 18, 100, 213, 214, 216, 217, 219, 220, 222, 223, 288, 2139, 2331,
+- 18604, 18605, 18767, 18768, 18770, 18771,
++ 15, 16, 17, 18, 100, 213, 214, 216, 217, 219, 220, 222, 223, 288, 2139, 2331,
++ 18604, 18605, 18767, 18768, 18770, 18771,
+ };
+
+ static const unsigned short dep57[] = {
+- 11, 12, 13, 14, 19, 20, 41, 42, 100, 161, 165, 178, 188, 213, 215, 216, 218,
+- 219, 221, 222, 224, 288, 2138, 2139, 2140, 2169, 2170, 2173, 2176, 2331, 4136,
+- 16531, 16533, 16534, 16536, 18767, 18769, 18770, 18772,
++ 11, 12, 13, 14, 19, 20, 41, 42, 100, 161, 165, 178, 188, 213, 215, 216, 218,
++ 219, 221, 222, 224, 288, 2138, 2139, 2140, 2169, 2170, 2173, 2176, 2331, 4136,
++ 16531, 16533, 16534, 16536, 18767, 18769, 18770, 18772,
+ };
+
+ static const unsigned short dep58[] = {
+- 16, 100, 216, 217, 288, 2139, 2331, 18604, 18605, 18767, 18768, 18770, 18771,
+-
++ 16, 100, 216, 217, 288, 2139, 2331, 18604, 18605, 18767, 18768, 18770, 18771,
++
+ };
+
+ static const unsigned short dep59[] = {
+- 12, 19, 20, 41, 42, 100, 161, 165, 178, 188, 216, 218, 288, 2138, 2139, 2140,
+- 2169, 2170, 2173, 2176, 2331, 4136, 16531, 16533, 16534, 16536, 18767, 18769,
+- 18770, 18772,
++ 12, 19, 20, 41, 42, 100, 161, 165, 178, 188, 216, 218, 288, 2138, 2139, 2140,
++ 2169, 2170, 2173, 2176, 2331, 4136, 16531, 16533, 16534, 16536, 18767, 18769,
++ 18770, 18772,
+ };
+
+ static const unsigned short dep60[] = {
+- 17, 100, 219, 220, 288, 2139, 2331, 18604, 18605, 18767, 18768, 18770, 18771,
+-
++ 17, 100, 219, 220, 288, 2139, 2331, 18604, 18605, 18767, 18768, 18770, 18771,
++
+ };
+
+ static const unsigned short dep61[] = {
+- 13, 19, 20, 41, 42, 100, 161, 165, 178, 188, 219, 221, 288, 2138, 2139, 2140,
+- 2169, 2170, 2173, 2176, 2331, 4136, 16531, 16533, 16534, 16536, 18767, 18769,
+- 18770, 18772,
++ 13, 19, 20, 41, 42, 100, 161, 165, 178, 188, 219, 221, 288, 2138, 2139, 2140,
++ 2169, 2170, 2173, 2176, 2331, 4136, 16531, 16533, 16534, 16536, 18767, 18769,
++ 18770, 18772,
+ };
+
+ static const unsigned short dep62[] = {
+- 18, 100, 222, 223, 288, 2139, 2331, 18604, 18605, 18767, 18768, 18770, 18771,
+-
++ 18, 100, 222, 223, 288, 2139, 2331, 18604, 18605, 18767, 18768, 18770, 18771,
++
+ };
+
+ static const unsigned short dep63[] = {
+- 14, 19, 20, 41, 42, 100, 161, 165, 178, 188, 222, 224, 288, 2138, 2139, 2140,
+- 2169, 2170, 2173, 2176, 2331, 4136, 16531, 16533, 16534, 16536, 18767, 18769,
+- 18770, 18772,
++ 14, 19, 20, 41, 42, 100, 161, 165, 178, 188, 222, 224, 288, 2138, 2139, 2140,
++ 2169, 2170, 2173, 2176, 2331, 4136, 16531, 16533, 16534, 16536, 18767, 18769,
++ 18770, 18772,
+ };
+
+ static const unsigned short dep64[] = {
+- 100, 288, 2139, 2331, 18604, 18605, 18767, 18768, 18770, 18771,
++ 100, 288, 2139, 2331, 18604, 18605, 18767, 18768, 18770, 18771,
+ };
+
+ static const unsigned short dep65[] = {
+- 41, 42, 100, 161, 165, 178, 188, 288, 2138, 2139, 2140, 2169, 2170, 2173,
+- 2176, 2331, 4136, 16531, 16533, 16534, 16536, 18767, 18769, 18770, 18772,
+-
++ 41, 42, 100, 161, 165, 178, 188, 288, 2138, 2139, 2140, 2169, 2170, 2173,
++ 2176, 2331, 4136, 16531, 16533, 16534, 16536, 18767, 18769, 18770, 18772,
++
+ };
+
+ static const unsigned short dep66[] = {
+- 11, 100, 209, 288,
++ 11, 100, 209, 288,
+ };
+
+ static const unsigned short dep67[] = {
+- 11, 41, 42, 100, 161, 165, 178, 188, 209, 288, 2169, 2170, 2173, 2176, 4136,
+-
++ 11, 41, 42, 100, 161, 165, 178, 188, 209, 288, 2169, 2170, 2173, 2176, 4136,
++
+ };
+
+ static const unsigned short dep68[] = {
+- 11, 41, 42, 100, 161, 165, 178, 188, 288, 2169, 2170, 2173, 2176, 4136,
++ 11, 41, 42, 100, 161, 165, 178, 188, 288, 2169, 2170, 2173, 2176, 4136,
+ };
+
+ static const unsigned short dep69[] = {
+- 12, 100, 210, 288,
++ 12, 100, 210, 288,
+ };
+
+ static const unsigned short dep70[] = {
+- 11, 41, 42, 100, 161, 165, 178, 188, 210, 288, 2169, 2170, 2173, 2176, 4136,
+-
++ 11, 41, 42, 100, 161, 165, 178, 188, 210, 288, 2169, 2170, 2173, 2176, 4136,
++
+ };
+
+ static const unsigned short dep71[] = {
+- 13, 100, 211, 288,
++ 13, 100, 211, 288,
+ };
+
+ static const unsigned short dep72[] = {
+- 11, 41, 42, 100, 161, 165, 178, 188, 211, 288, 2169, 2170, 2173, 2176, 4136,
+-
++ 11, 41, 42, 100, 161, 165, 178, 188, 211, 288, 2169, 2170, 2173, 2176, 4136,
++
+ };
+
+ static const unsigned short dep73[] = {
+- 14, 100, 212, 288,
++ 14, 100, 212, 288,
+ };
+
+ static const unsigned short dep74[] = {
+- 11, 41, 42, 100, 161, 165, 178, 188, 212, 288, 2169, 2170, 2173, 2176, 4136,
+-
++ 11, 41, 42, 100, 161, 165, 178, 188, 212, 288, 2169, 2170, 2173, 2176, 4136,
++
+ };
+
+ static const unsigned short dep75[] = {
+- 15, 100, 214, 215, 288,
++ 15, 100, 214, 215, 288,
+ };
+
+ static const unsigned short dep76[] = {
+- 41, 42, 100, 161, 165, 178, 188, 214, 215, 288, 2169, 2170, 2173, 2176, 4136,
+-
++ 41, 42, 100, 161, 165, 178, 188, 214, 215, 288, 2169, 2170, 2173, 2176, 4136,
++
+ };
+
+ static const unsigned short dep77[] = {
+- 41, 42, 100, 161, 165, 178, 188, 288, 2169, 2170, 2173, 2176, 4136,
++ 41, 42, 100, 161, 165, 178, 188, 288, 2169, 2170, 2173, 2176, 4136,
+ };
+
+ static const unsigned short dep78[] = {
+- 16, 100, 217, 218, 288,
++ 16, 100, 217, 218, 288,
+ };
+
+ static const unsigned short dep79[] = {
+- 41, 42, 100, 161, 165, 178, 188, 217, 218, 288, 2169, 2170, 2173, 2176, 4136,
+-
++ 41, 42, 100, 161, 165, 178, 188, 217, 218, 288, 2169, 2170, 2173, 2176, 4136,
++
+ };
+
+ static const unsigned short dep80[] = {
+- 17, 100, 220, 221, 288,
++ 17, 100, 220, 221, 288,
+ };
+
+ static const unsigned short dep81[] = {
+- 41, 42, 100, 161, 165, 178, 188, 220, 221, 288, 2169, 2170, 2173, 2176, 4136,
+-
++ 41, 42, 100, 161, 165, 178, 188, 220, 221, 288, 2169, 2170, 2173, 2176, 4136,
++
+ };
+
+ static const unsigned short dep82[] = {
+- 18, 100, 223, 224, 288,
++ 18, 100, 223, 224, 288,
+ };
+
+ static const unsigned short dep83[] = {
+- 41, 42, 100, 161, 165, 178, 188, 223, 224, 288, 2169, 2170, 2173, 2176, 4136,
+-
++ 41, 42, 100, 161, 165, 178, 188, 223, 224, 288, 2169, 2170, 2173, 2176, 4136,
++
+ };
+
+ static const unsigned short dep84[] = {
+- 15, 19, 20, 41, 42, 100, 161, 165, 167, 178, 188, 189, 191, 288, 2169, 2170,
+- 2173, 2176, 4136,
++ 15, 19, 20, 41, 42, 100, 161, 165, 167, 178, 188, 189, 191, 288, 2169, 2170,
++ 2173, 2176, 4136,
+ };
+
+ static const unsigned short dep85[] = {
+- 15, 16, 19, 20, 41, 42, 100, 161, 165, 167, 178, 188, 189, 191, 288, 2169,
+- 2170, 2173, 2176, 4136,
++ 15, 16, 19, 20, 41, 42, 100, 161, 165, 167, 178, 188, 189, 191, 288, 2169,
++ 2170, 2173, 2176, 4136,
+ };
+
+ static const unsigned short dep86[] = {
+- 15, 17, 19, 20, 41, 42, 100, 161, 165, 167, 178, 188, 189, 191, 288, 2169,
+- 2170, 2173, 2176, 4136,
++ 15, 17, 19, 20, 41, 42, 100, 161, 165, 167, 178, 188, 189, 191, 288, 2169,
++ 2170, 2173, 2176, 4136,
+ };
+
+ static const unsigned short dep87[] = {
+- 15, 18, 19, 20, 41, 42, 100, 161, 165, 167, 178, 188, 189, 191, 288, 2169,
+- 2170, 2173, 2176, 4136,
++ 15, 18, 19, 20, 41, 42, 100, 161, 165, 167, 178, 188, 189, 191, 288, 2169,
++ 2170, 2173, 2176, 4136,
+ };
+
+ static const unsigned short dep88[] = {
+- 15, 100, 213, 214, 288,
++ 15, 100, 213, 214, 288,
+ };
+
+ static const unsigned short dep89[] = {
+- 11, 19, 20, 41, 42, 100, 161, 165, 178, 188, 213, 215, 288, 2169, 2170, 2173,
+- 2176, 4136,
++ 11, 19, 20, 41, 42, 100, 161, 165, 178, 188, 213, 215, 288, 2169, 2170, 2173,
++ 2176, 4136,
+ };
+
+ static const unsigned short dep90[] = {
+- 15, 16, 17, 18, 100, 213, 214, 216, 217, 219, 220, 222, 223, 288,
++ 15, 16, 17, 18, 100, 213, 214, 216, 217, 219, 220, 222, 223, 288,
+ };
+
+ static const unsigned short dep91[] = {
+- 11, 12, 13, 14, 19, 20, 41, 42, 100, 161, 165, 178, 188, 213, 215, 216, 218,
+- 219, 221, 222, 224, 288, 2169, 2170, 2173, 2176, 4136,
++ 11, 12, 13, 14, 19, 20, 41, 42, 100, 161, 165, 178, 188, 213, 215, 216, 218,
++ 219, 221, 222, 224, 288, 2169, 2170, 2173, 2176, 4136,
+ };
+
+ static const unsigned short dep92[] = {
+- 16, 100, 216, 217, 288,
++ 16, 100, 216, 217, 288,
+ };
+
+ static const unsigned short dep93[] = {
+- 12, 19, 20, 41, 42, 100, 161, 165, 178, 188, 216, 218, 288, 2169, 2170, 2173,
+- 2176, 4136,
++ 12, 19, 20, 41, 42, 100, 161, 165, 178, 188, 216, 218, 288, 2169, 2170, 2173,
++ 2176, 4136,
+ };
+
+ static const unsigned short dep94[] = {
+- 17, 100, 219, 220, 288,
++ 17, 100, 219, 220, 288,
+ };
+
+ static const unsigned short dep95[] = {
+- 13, 19, 20, 41, 42, 100, 161, 165, 178, 188, 219, 221, 288, 2169, 2170, 2173,
+- 2176, 4136,
++ 13, 19, 20, 41, 42, 100, 161, 165, 178, 188, 219, 221, 288, 2169, 2170, 2173,
++ 2176, 4136,
+ };
+
+ static const unsigned short dep96[] = {
+- 18, 100, 222, 223, 288,
++ 18, 100, 222, 223, 288,
+ };
+
+ static const unsigned short dep97[] = {
+- 14, 19, 20, 41, 42, 100, 161, 165, 178, 188, 222, 224, 288, 2169, 2170, 2173,
+- 2176, 4136,
++ 14, 19, 20, 41, 42, 100, 161, 165, 178, 188, 222, 224, 288, 2169, 2170, 2173,
++ 2176, 4136,
+ };
+
+ static const unsigned short dep98[] = {
+- 15, 100, 213, 214, 288, 2169, 2170, 2171, 2173, 2174, 2176, 2177, 2350, 2353,
+- 2354, 2357, 2358, 2361, 2362,
++ 15, 100, 213, 214, 288, 2169, 2170, 2171, 2173, 2174, 2176, 2177, 2350, 2353,
++ 2354, 2357, 2358, 2361, 2362,
+ };
+
+ static const unsigned short dep99[] = {
+- 11, 19, 20, 41, 42, 100, 161, 165, 178, 188, 213, 215, 288, 2138, 2139, 2140,
+- 2169, 2170, 2173, 2176, 2350, 2353, 2354, 2357, 2358, 2361, 2362, 4136, 16531,
+- 16533, 16534, 16536,
++ 11, 19, 20, 41, 42, 100, 161, 165, 178, 188, 213, 215, 288, 2138, 2139, 2140,
++ 2169, 2170, 2173, 2176, 2350, 2353, 2354, 2357, 2358, 2361, 2362, 4136, 16531,
++ 16533, 16534, 16536,
+ };
+
+ static const unsigned short dep100[] = {
+- 15, 16, 17, 18, 100, 213, 214, 216, 217, 219, 220, 222, 223, 288, 2169, 2170,
+- 2171, 2173, 2174, 2176, 2177, 2350, 2353, 2354, 2357, 2358, 2361, 2362,
++ 15, 16, 17, 18, 100, 213, 214, 216, 217, 219, 220, 222, 223, 288, 2169, 2170,
++ 2171, 2173, 2174, 2176, 2177, 2350, 2353, 2354, 2357, 2358, 2361, 2362,
+ };
+
+ static const unsigned short dep101[] = {
+- 11, 12, 13, 14, 19, 20, 41, 42, 100, 161, 165, 178, 188, 213, 215, 216, 218,
+- 219, 221, 222, 224, 288, 2138, 2139, 2140, 2169, 2170, 2173, 2176, 2350, 2353,
+- 2354, 2357, 2358, 2361, 2362, 4136, 16531, 16533, 16534, 16536,
++ 11, 12, 13, 14, 19, 20, 41, 42, 100, 161, 165, 178, 188, 213, 215, 216, 218,
++ 219, 221, 222, 224, 288, 2138, 2139, 2140, 2169, 2170, 2173, 2176, 2350, 2353,
++ 2354, 2357, 2358, 2361, 2362, 4136, 16531, 16533, 16534, 16536,
+ };
+
+ static const unsigned short dep102[] = {
+- 16, 100, 216, 217, 288, 2169, 2170, 2171, 2173, 2174, 2176, 2177, 2350, 2353,
+- 2354, 2357, 2358, 2361, 2362,
++ 16, 100, 216, 217, 288, 2169, 2170, 2171, 2173, 2174, 2176, 2177, 2350, 2353,
++ 2354, 2357, 2358, 2361, 2362,
+ };
+
+ static const unsigned short dep103[] = {
+- 12, 19, 20, 41, 42, 100, 161, 165, 178, 188, 216, 218, 288, 2138, 2139, 2140,
+- 2169, 2170, 2173, 2176, 2350, 2353, 2354, 2357, 2358, 2361, 2362, 4136, 16531,
+- 16533, 16534, 16536,
++ 12, 19, 20, 41, 42, 100, 161, 165, 178, 188, 216, 218, 288, 2138, 2139, 2140,
++ 2169, 2170, 2173, 2176, 2350, 2353, 2354, 2357, 2358, 2361, 2362, 4136, 16531,
++ 16533, 16534, 16536,
+ };
+
+ static const unsigned short dep104[] = {
+- 17, 100, 219, 220, 288, 2169, 2170, 2171, 2173, 2174, 2176, 2177, 2350, 2353,
+- 2354, 2357, 2358, 2361, 2362,
++ 17, 100, 219, 220, 288, 2169, 2170, 2171, 2173, 2174, 2176, 2177, 2350, 2353,
++ 2354, 2357, 2358, 2361, 2362,
+ };
+
+ static const unsigned short dep105[] = {
+- 13, 19, 20, 41, 42, 100, 161, 165, 178, 188, 219, 221, 288, 2138, 2139, 2140,
+- 2169, 2170, 2173, 2176, 2350, 2353, 2354, 2357, 2358, 2361, 2362, 4136, 16531,
+- 16533, 16534, 16536,
++ 13, 19, 20, 41, 42, 100, 161, 165, 178, 188, 219, 221, 288, 2138, 2139, 2140,
++ 2169, 2170, 2173, 2176, 2350, 2353, 2354, 2357, 2358, 2361, 2362, 4136, 16531,
++ 16533, 16534, 16536,
+ };
+
+ static const unsigned short dep106[] = {
+- 18, 100, 222, 223, 288, 2169, 2170, 2171, 2173, 2174, 2176, 2177, 2350, 2353,
+- 2354, 2357, 2358, 2361, 2362,
++ 18, 100, 222, 223, 288, 2169, 2170, 2171, 2173, 2174, 2176, 2177, 2350, 2353,
++ 2354, 2357, 2358, 2361, 2362,
+ };
+
+ static const unsigned short dep107[] = {
+- 14, 19, 20, 41, 42, 100, 161, 165, 178, 188, 222, 224, 288, 2138, 2139, 2140,
+- 2169, 2170, 2173, 2176, 2350, 2353, 2354, 2357, 2358, 2361, 2362, 4136, 16531,
+- 16533, 16534, 16536,
++ 14, 19, 20, 41, 42, 100, 161, 165, 178, 188, 222, 224, 288, 2138, 2139, 2140,
++ 2169, 2170, 2173, 2176, 2350, 2353, 2354, 2357, 2358, 2361, 2362, 4136, 16531,
++ 16533, 16534, 16536,
+ };
+
+ static const unsigned short dep108[] = {
+- 15, 100, 213, 214, 288, 22649, 22650, 22651, 22653, 22654, 22656, 22657, 22830,
+- 22833, 22834, 22837, 22838, 22841, 22842,
++ 15, 100, 213, 214, 288, 22649, 22650, 22651, 22653, 22654, 22656, 22657, 22830,
++ 22833, 22834, 22837, 22838, 22841, 22842,
+ };
+
+ static const unsigned short dep109[] = {
+- 11, 19, 20, 41, 42, 100, 161, 165, 178, 188, 213, 215, 288, 2138, 2139, 2140,
+- 2169, 2170, 2173, 2176, 4136, 16531, 16533, 16534, 16536, 22830, 22833, 22834,
+- 22837, 22838, 22841, 22842,
++ 11, 19, 20, 41, 42, 100, 161, 165, 178, 188, 213, 215, 288, 2138, 2139, 2140,
++ 2169, 2170, 2173, 2176, 4136, 16531, 16533, 16534, 16536, 22830, 22833, 22834,
++ 22837, 22838, 22841, 22842,
+ };
+
+ static const unsigned short dep110[] = {
+- 15, 16, 17, 18, 100, 213, 214, 216, 217, 219, 220, 222, 223, 288, 22649, 22650,
+- 22651, 22653, 22654, 22656, 22657, 22830, 22833, 22834, 22837, 22838, 22841,
+- 22842,
++ 15, 16, 17, 18, 100, 213, 214, 216, 217, 219, 220, 222, 223, 288, 22649, 22650,
++ 22651, 22653, 22654, 22656, 22657, 22830, 22833, 22834, 22837, 22838, 22841,
++ 22842,
+ };
+
+ static const unsigned short dep111[] = {
+- 11, 12, 13, 14, 19, 20, 41, 42, 100, 161, 165, 178, 188, 213, 215, 216, 218,
+- 219, 221, 222, 224, 288, 2138, 2139, 2140, 2169, 2170, 2173, 2176, 4136, 16531,
+- 16533, 16534, 16536, 22830, 22833, 22834, 22837, 22838, 22841, 22842,
++ 11, 12, 13, 14, 19, 20, 41, 42, 100, 161, 165, 178, 188, 213, 215, 216, 218,
++ 219, 221, 222, 224, 288, 2138, 2139, 2140, 2169, 2170, 2173, 2176, 4136, 16531,
++ 16533, 16534, 16536, 22830, 22833, 22834, 22837, 22838, 22841, 22842,
+ };
+
+ static const unsigned short dep112[] = {
+- 16, 100, 216, 217, 288, 22649, 22650, 22651, 22653, 22654, 22656, 22657, 22830,
+- 22833, 22834, 22837, 22838, 22841, 22842,
++ 16, 100, 216, 217, 288, 22649, 22650, 22651, 22653, 22654, 22656, 22657, 22830,
++ 22833, 22834, 22837, 22838, 22841, 22842,
+ };
+
+ static const unsigned short dep113[] = {
+- 12, 19, 20, 41, 42, 100, 161, 165, 178, 188, 216, 218, 288, 2138, 2139, 2140,
+- 2169, 2170, 2173, 2176, 4136, 16531, 16533, 16534, 16536, 22830, 22833, 22834,
+- 22837, 22838, 22841, 22842,
++ 12, 19, 20, 41, 42, 100, 161, 165, 178, 188, 216, 218, 288, 2138, 2139, 2140,
++ 2169, 2170, 2173, 2176, 4136, 16531, 16533, 16534, 16536, 22830, 22833, 22834,
++ 22837, 22838, 22841, 22842,
+ };
+
+ static const unsigned short dep114[] = {
+- 17, 100, 219, 220, 288, 22649, 22650, 22651, 22653, 22654, 22656, 22657, 22830,
+- 22833, 22834, 22837, 22838, 22841, 22842,
++ 17, 100, 219, 220, 288, 22649, 22650, 22651, 22653, 22654, 22656, 22657, 22830,
++ 22833, 22834, 22837, 22838, 22841, 22842,
+ };
+
+ static const unsigned short dep115[] = {
+- 13, 19, 20, 41, 42, 100, 161, 165, 178, 188, 219, 221, 288, 2138, 2139, 2140,
+- 2169, 2170, 2173, 2176, 4136, 16531, 16533, 16534, 16536, 22830, 22833, 22834,
+- 22837, 22838, 22841, 22842,
++ 13, 19, 20, 41, 42, 100, 161, 165, 178, 188, 219, 221, 288, 2138, 2139, 2140,
++ 2169, 2170, 2173, 2176, 4136, 16531, 16533, 16534, 16536, 22830, 22833, 22834,
++ 22837, 22838, 22841, 22842,
+ };
+
+ static const unsigned short dep116[] = {
+- 18, 100, 222, 223, 288, 22649, 22650, 22651, 22653, 22654, 22656, 22657, 22830,
+- 22833, 22834, 22837, 22838, 22841, 22842,
++ 18, 100, 222, 223, 288, 22649, 22650, 22651, 22653, 22654, 22656, 22657, 22830,
++ 22833, 22834, 22837, 22838, 22841, 22842,
+ };
+
+ static const unsigned short dep117[] = {
+- 14, 19, 20, 41, 42, 100, 161, 165, 178, 188, 222, 224, 288, 2138, 2139, 2140,
+- 2169, 2170, 2173, 2176, 4136, 16531, 16533, 16534, 16536, 22830, 22833, 22834,
+- 22837, 22838, 22841, 22842,
++ 14, 19, 20, 41, 42, 100, 161, 165, 178, 188, 222, 224, 288, 2138, 2139, 2140,
++ 2169, 2170, 2173, 2176, 4136, 16531, 16533, 16534, 16536, 22830, 22833, 22834,
++ 22837, 22838, 22841, 22842,
+ };
+
+ static const unsigned short dep118[] = {
+- 100, 288, 2169, 2170, 2171, 2173, 2174, 2176, 2177, 2350, 2353, 2354, 2357,
+- 2358, 2361, 2362,
++ 100, 288, 2169, 2170, 2171, 2173, 2174, 2176, 2177, 2350, 2353, 2354, 2357,
++ 2358, 2361, 2362,
+ };
+
+ static const unsigned short dep119[] = {
+- 41, 42, 100, 161, 165, 178, 188, 288, 2138, 2139, 2140, 2169, 2170, 2173,
+- 2176, 2350, 2353, 2354, 2357, 2358, 2361, 2362, 4136, 16531, 16533, 16534,
+- 16536,
++ 41, 42, 100, 161, 165, 178, 188, 288, 2138, 2139, 2140, 2169, 2170, 2173,
++ 2176, 2350, 2353, 2354, 2357, 2358, 2361, 2362, 4136, 16531, 16533, 16534,
++ 16536,
+ };
+
+ static const unsigned short dep120[] = {
+- 100, 288, 22649, 22650, 22651, 22653, 22654, 22656, 22657, 22830, 22833, 22834,
+- 22837, 22838, 22841, 22842,
++ 100, 288, 22649, 22650, 22651, 22653, 22654, 22656, 22657, 22830, 22833, 22834,
++ 22837, 22838, 22841, 22842,
+ };
+
+ static const unsigned short dep121[] = {
+- 41, 42, 100, 161, 165, 178, 188, 288, 2138, 2139, 2140, 2169, 2170, 2173,
+- 2176, 4136, 16531, 16533, 16534, 16536, 22830, 22833, 22834, 22837, 22838,
+- 22841, 22842,
++ 41, 42, 100, 161, 165, 178, 188, 288, 2138, 2139, 2140, 2169, 2170, 2173,
++ 2176, 4136, 16531, 16533, 16534, 16536, 22830, 22833, 22834, 22837, 22838,
++ 22841, 22842,
+ };
+
+ static const unsigned short dep122[] = {
+- 19, 20, 41, 42, 100, 161, 165, 178, 188, 288, 2138, 2139, 2140, 2169, 2170,
+- 2173, 2176, 2331, 4136, 16531, 16533, 16534, 16536, 18767, 18769, 18770, 18772,
+-
++ 19, 20, 41, 42, 100, 161, 165, 178, 188, 288, 2138, 2139, 2140, 2169, 2170,
++ 2173, 2176, 2331, 4136, 16531, 16533, 16534, 16536, 18767, 18769, 18770, 18772,
++
+ };
+
+ static const unsigned short dep123[] = {
+- 41, 42, 100, 161, 165, 167, 178, 188, 189, 191, 288, 2141, 2142, 2143, 2169,
+- 2170, 2173, 2176, 4136, 20619,
++ 41, 42, 100, 161, 165, 167, 178, 188, 189, 191, 288, 2141, 2142, 2143, 2169,
++ 2170, 2173, 2176, 4136, 20619,
+ };
+
+ static const unsigned short dep124[] = {
+- 100, 288, 2084, 2085, 2290, 2291,
++ 100, 288, 2084, 2085, 2290, 2291,
+ };
+
+ static const unsigned short dep125[] = {
+- 41, 42, 100, 161, 165, 178, 188, 288, 2141, 2142, 2143, 2169, 2170, 2173,
+- 2176, 2289, 2291, 4136, 20619,
++ 41, 42, 100, 161, 165, 178, 188, 288, 2141, 2142, 2143, 2169, 2170, 2173,
++ 2176, 2289, 2291, 4136, 20619,
+ };
+
+ static const unsigned short dep126[] = {
+- 41, 42, 100, 161, 165, 178, 188, 288, 2083, 2085, 2169, 2170, 2173, 2176,
+- 2333, 4136, 20619,
++ 41, 42, 100, 161, 165, 178, 188, 288, 2083, 2085, 2169, 2170, 2173, 2176,
++ 2333, 4136, 20619,
+ };
+
+ static const unsigned short dep127[] = {
+- 100, 288, 14458, 14460, 14461, 14463, 14464, 14466, 14641, 14642, 14645, 14646,
+- 14649, 14650,
++ 100, 288, 14458, 14460, 14461, 14463, 14464, 14466, 14641, 14642, 14645, 14646,
++ 14649, 14650,
+ };
+
+ static const unsigned short dep128[] = {
+- 41, 42, 100, 161, 165, 178, 188, 288, 2141, 2142, 2143, 4136, 14641, 14642,
+- 14645, 14646, 14649, 14650, 20619, 24697, 24698, 24701, 24704,
++ 41, 42, 100, 161, 165, 178, 188, 288, 2141, 2142, 2143, 4136, 14641, 14642,
++ 14645, 14646, 14649, 14650, 20619, 24697, 24698, 24701, 24704,
+ };
+
+ static const unsigned short dep129[] = {
+- 100, 125, 127, 128, 130, 288, 309, 310, 313, 314,
++ 100, 125, 127, 128, 130, 288, 309, 310, 313, 314,
+ };
+
+ static const unsigned short dep130[] = {
+- 41, 42, 100, 161, 165, 178, 188, 288, 309, 310, 313, 314, 4136, 24697, 24698,
+- 24701, 24704,
++ 41, 42, 100, 161, 165, 178, 188, 288, 309, 310, 313, 314, 4136, 24697, 24698,
++ 24701, 24704,
+ };
+
+ static const unsigned short dep131[] = {
+- 41, 42, 100, 161, 165, 178, 188, 288, 2169, 2170, 2173, 2176, 2333, 4136,
+- 20619,
++ 41, 42, 100, 161, 165, 178, 188, 288, 2169, 2170, 2173, 2176, 2333, 4136,
++ 20619,
+ };
+
+ static const unsigned short dep132[] = {
+- 41, 42, 100, 122, 125, 128, 161, 165, 178, 188, 288, 2333, 4136, 20619, 24697,
+-
++ 41, 42, 100, 122, 125, 128, 161, 165, 178, 188, 288, 2333, 4136, 20619, 24697,
++
+ };
+
+ static const unsigned short dep133[] = {
+- 6, 24, 26, 27, 100, 204, 230, 233, 288, 2082, 2288,
++ 6, 24, 26, 27, 100, 204, 230, 233, 288, 2082, 2288,
+ };
+
+ static const unsigned short dep134[] = {
+- 41, 42, 100, 161, 165, 178, 188, 204, 230, 232, 288, 2141, 2142, 2143, 2169,
+- 2170, 2173, 2176, 2288, 4136, 20619,
++ 41, 42, 100, 161, 165, 178, 188, 204, 230, 232, 288, 2141, 2142, 2143, 2169,
++ 2170, 2173, 2176, 2288, 4136, 20619,
+ };
+
+ static const unsigned short dep135[] = {
+- 6, 24, 25, 26, 41, 42, 100, 161, 165, 178, 188, 288, 2082, 2169, 2170, 2173,
+- 2176, 2333, 4136, 20619,
++ 6, 24, 25, 26, 41, 42, 100, 161, 165, 178, 188, 288, 2082, 2169, 2170, 2173,
++ 2176, 2333, 4136, 20619,
+ };
+
+ static const unsigned short dep136[] = {
+- 41, 42, 100, 161, 165, 178, 188, 288, 2169, 2170, 2173, 2176, 2350, 2353,
+- 2354, 2357, 2358, 2361, 2362, 4136,
++ 41, 42, 100, 161, 165, 178, 188, 288, 2169, 2170, 2173, 2176, 2350, 2353,
++ 2354, 2357, 2358, 2361, 2362, 4136,
+ };
+
+ static const unsigned short dep137[] = {
+- 41, 42, 100, 161, 165, 178, 188, 288, 2169, 2170, 2173, 2176, 4136, 22830,
+- 22833, 22834, 22837, 22838, 22841, 22842,
++ 41, 42, 100, 161, 165, 178, 188, 288, 2169, 2170, 2173, 2176, 4136, 22830,
++ 22833, 22834, 22837, 22838, 22841, 22842,
+ };
+
+ static const unsigned short dep138[] = {
+- 41, 42, 100, 161, 165, 178, 188, 288, 2169, 2170, 2173, 2176, 2350, 2351,
+- 2354, 2355, 2358, 2359, 2362, 4136,
++ 41, 42, 100, 161, 165, 178, 188, 288, 2169, 2170, 2173, 2176, 2350, 2351,
++ 2354, 2355, 2358, 2359, 2362, 4136,
+ };
+
+ static const unsigned short dep139[] = {
+- 41, 42, 100, 161, 165, 178, 188, 288, 2169, 2170, 2173, 2176, 2350, 2352,
+- 2353, 2356, 2357, 2360, 2361, 4136,
++ 41, 42, 100, 161, 165, 178, 188, 288, 2169, 2170, 2173, 2176, 2350, 2352,
++ 2353, 2356, 2357, 2360, 2361, 4136,
+ };
+
+ static const unsigned short dep140[] = {
+- 41, 42, 100, 161, 165, 178, 188, 288, 2169, 2170, 2173, 2176, 2350, 2351,
+- 2352, 2353, 2354, 2355, 2356, 2357, 2358, 2359, 2360, 2361, 2362, 4136,
++ 41, 42, 100, 161, 165, 178, 188, 288, 2169, 2170, 2173, 2176, 2350, 2351,
++ 2352, 2353, 2354, 2355, 2356, 2357, 2358, 2359, 2360, 2361, 2362, 4136,
+ };
+
+ static const unsigned short dep141[] = {
+- 0, 41, 42, 100, 161, 165, 167, 178, 188, 189, 191, 288, 2169, 2170, 2173,
+- 2176, 4136,
++ 0, 41, 42, 100, 161, 165, 167, 178, 188, 189, 191, 288, 2169, 2170, 2173,
++ 2176, 4136,
+ };
+
+ static const unsigned short dep142[] = {
+- 0, 100, 198, 288,
++ 0, 100, 198, 288,
+ };
+
+ static const unsigned short dep143[] = {
+- 0, 41, 42, 100, 161, 165, 167, 178, 188, 189, 191, 198, 288, 2169, 2170, 2173,
+- 2176, 4136,
++ 0, 41, 42, 100, 161, 165, 167, 178, 188, 189, 191, 198, 288, 2169, 2170, 2173,
++ 2176, 4136,
+ };
+
+ static const unsigned short dep144[] = {
+- 41, 42, 100, 161, 165, 178, 188, 198, 288, 2169, 2170, 2173, 2176, 4136,
++ 41, 42, 100, 161, 165, 178, 188, 198, 288, 2169, 2170, 2173, 2176, 4136,
+ };
+
+ static const unsigned short dep145[] = {
+- 2, 28, 100, 200, 234, 288, 28869, 29024,
++ 2, 28, 100, 200, 234, 288, 28869, 29024,
+ };
+
+ static const unsigned short dep146[] = {
+- 1, 2, 28, 29, 100, 161, 165, 178, 180, 181, 188, 200, 234, 288, 28869, 29024,
+-
++ 1, 2, 28, 29, 100, 161, 165, 178, 180, 181, 188, 200, 234, 288, 28869, 29024,
++
+ };
+
+ static const unsigned short dep147[] = {
+- 1, 28, 29, 39, 41, 42, 100, 161, 165, 178, 180, 181, 188, 200, 234, 288, 4136,
+- 28869, 29024,
++ 1, 28, 29, 39, 41, 42, 100, 161, 165, 178, 180, 181, 188, 200, 234, 288, 4136,
++ 28869, 29024,
+ };
+
+ static const unsigned short dep148[] = {
+- 0, 41, 42, 100, 161, 165, 178, 188, 198, 288, 2169, 2170, 2173, 2176, 4136,
+-
++ 0, 41, 42, 100, 161, 165, 178, 188, 198, 288, 2169, 2170, 2173, 2176, 4136,
++
+ };
+
+ static const unsigned short dep149[] = {
+- 1, 2, 3, 4, 5, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22,
+- 28, 29, 30, 31, 32, 100, 199, 200, 201, 202, 203, 205, 206, 207, 208, 209,
+- 210, 211, 212, 214, 215, 217, 218, 220, 221, 223, 224, 225, 226, 227, 228,
+- 234, 235, 236, 237, 238, 272, 288, 2071, 2082, 2277, 2288, 28869, 29024,
++ 1, 2, 3, 4, 5, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22,
++ 28, 29, 30, 31, 32, 100, 199, 200, 201, 202, 203, 205, 206, 207, 208, 209,
++ 210, 211, 212, 214, 215, 217, 218, 220, 221, 223, 224, 225, 226, 227, 228,
++ 234, 235, 236, 237, 238, 272, 288, 2071, 2082, 2277, 2288, 28869, 29024,
+ };
+
+ static const unsigned short dep150[] = {
+- 29, 41, 42, 100, 140, 141, 161, 165, 178, 188, 193, 194, 199, 200, 201, 202,
+- 203, 205, 206, 207, 208, 209, 210, 211, 212, 214, 215, 217, 218, 220, 221,
+- 223, 224, 225, 226, 227, 228, 234, 235, 236, 237, 238, 272, 288, 2141, 2142,
+- 2143, 2169, 2170, 2173, 2176, 2277, 2288, 4136, 20619, 28869, 29024,
++ 29, 41, 42, 100, 140, 141, 161, 165, 178, 188, 193, 194, 199, 200, 201, 202,
++ 203, 205, 206, 207, 208, 209, 210, 211, 212, 214, 215, 217, 218, 220, 221,
++ 223, 224, 225, 226, 227, 228, 234, 235, 236, 237, 238, 272, 288, 2141, 2142,
++ 2143, 2169, 2170, 2173, 2176, 2277, 2288, 4136, 20619, 28869, 29024,
+ };
+
+ static const unsigned short dep151[] = {
+- 77, 272,
++ 77, 272,
+ };
+
+ static const unsigned short dep152[] = {
+- 272,
++ 272,
+ };
+
+ static const unsigned short dep153[] = {
+- 100, 288, 14467, 14469, 14471, 14473, 14508, 14509, 14528, 14651, 14652, 14672,
+- 14673, 14675, 14676, 14685,
++ 100, 288, 14467, 14469, 14471, 14473, 14508, 14509, 14528, 14651, 14652, 14672,
++ 14673, 14675, 14676, 14685,
+ };
+
+ static const unsigned short dep154[] = {
+- 41, 42, 100, 161, 165, 178, 186, 187, 188, 288, 2169, 2170, 2173, 2176, 4136,
+- 14651, 14652, 14672, 14673, 14675, 14676, 14685,
++ 41, 42, 100, 161, 165, 178, 186, 187, 188, 288, 2169, 2170, 2173, 2176, 4136,
++ 14651, 14652, 14672, 14673, 14675, 14676, 14685,
+ };
+
+ static const unsigned short dep155[] = {
+- 14467, 14469, 14471, 14473, 14508, 14509, 14528, 14651, 14652, 14672, 14673,
+- 14675, 14676, 14685,
++ 14467, 14469, 14471, 14473, 14508, 14509, 14528, 14651, 14652, 14672, 14673,
++ 14675, 14676, 14685,
+ };
+
+ static const unsigned short dep156[] = {
+- 186, 187, 14651, 14652, 14672, 14673, 14675, 14676, 14685,
++ 186, 187, 14651, 14652, 14672, 14673, 14675, 14676, 14685,
+ };
+
+ static const unsigned short dep157[] = {
+- 100, 288, 14468, 14469, 14472, 14473, 14483, 14484, 14486, 14487, 14489, 14490,
+- 14492, 14493, 14496, 14498, 14499, 14508, 14509, 14510, 14511, 14513, 14518,
+- 14519, 14521, 14522, 14528, 14651, 14652, 14658, 14659, 14660, 14661, 14663,
+- 14665, 14672, 14673, 14675, 14676, 14677, 14678, 14681, 14682, 14685,
++ 100, 288, 14468, 14469, 14472, 14473, 14483, 14484, 14486, 14487, 14489, 14490,
++ 14492, 14493, 14496, 14498, 14499, 14508, 14509, 14510, 14511, 14513, 14518,
++ 14519, 14521, 14522, 14528, 14651, 14652, 14658, 14659, 14660, 14661, 14663,
++ 14665, 14672, 14673, 14675, 14676, 14677, 14678, 14681, 14682, 14685,
+ };
+
+ static const unsigned short dep158[] = {
+- 41, 42, 100, 140, 141, 161, 165, 178, 188, 193, 194, 288, 2169, 2170, 2173,
+- 2176, 4136, 14651, 14652, 14658, 14659, 14660, 14661, 14663, 14665, 14672,
+- 14673, 14675, 14676, 14677, 14678, 14681, 14682, 14685, 34890,
++ 41, 42, 100, 140, 141, 161, 165, 178, 188, 193, 194, 288, 2169, 2170, 2173,
++ 2176, 4136, 14651, 14652, 14658, 14659, 14660, 14661, 14663, 14665, 14672,
++ 14673, 14675, 14676, 14677, 14678, 14681, 14682, 14685, 34890,
+ };
+
+ static const unsigned short dep159[] = {
+- 41, 42, 100, 140, 141, 161, 165, 178, 188, 193, 194, 288, 2169, 2170, 2173,
+- 2176, 4136, 14651, 14652, 14658, 14659, 14660, 14661, 14663, 14665, 14672,
+- 14673, 14675, 14676, 14677, 14678, 14681, 14682, 14685,
++ 41, 42, 100, 140, 141, 161, 165, 178, 188, 193, 194, 288, 2169, 2170, 2173,
++ 2176, 4136, 14651, 14652, 14658, 14659, 14660, 14661, 14663, 14665, 14672,
++ 14673, 14675, 14676, 14677, 14678, 14681, 14682, 14685,
+ };
+
+ static const unsigned short dep160[] = {
+- 1, 2, 3, 4, 5, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22,
+- 28, 29, 30, 31, 32, 41, 42, 100, 140, 141, 161, 165, 178, 183, 184, 188, 193,
+- 194, 288, 2071, 2082, 2169, 2170, 2173, 2176, 2333, 4136, 20619, 28869,
++ 1, 2, 3, 4, 5, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22,
++ 28, 29, 30, 31, 32, 41, 42, 100, 140, 141, 161, 165, 178, 183, 184, 188, 193,
++ 194, 288, 2071, 2082, 2169, 2170, 2173, 2176, 2333, 4136, 20619, 28869,
+ };
+
+ static const unsigned short dep161[] = {
+- 44, 45, 46, 47, 48, 49, 50, 51, 53, 54, 55, 56, 57, 58, 59, 60, 62, 63, 64,
+- 65, 66, 67, 69, 71, 72, 73, 74, 75, 97, 99, 100, 247, 248, 249, 250, 251,
+- 252, 253, 254, 255, 256, 257, 258, 260, 261, 262, 263, 264, 266, 268, 269,
+- 270, 287, 288, 2118, 2315,
++ 44, 45, 46, 47, 48, 49, 50, 51, 53, 54, 55, 56, 57, 58, 59, 60, 62, 63, 64,
++ 65, 66, 67, 69, 71, 72, 73, 74, 75, 97, 99, 100, 247, 248, 249, 250, 251,
++ 252, 253, 254, 255, 256, 257, 258, 260, 261, 262, 263, 264, 266, 268, 269,
++ 270, 287, 288, 2118, 2315,
+ };
+
+ static const unsigned short dep162[] = {
+- 41, 42, 99, 100, 140, 141, 161, 163, 164, 165, 178, 188, 193, 194, 247, 248,
+- 249, 250, 251, 252, 253, 254, 255, 256, 257, 258, 260, 261, 262, 263, 264,
+- 266, 268, 269, 270, 287, 288, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 2315,
+- 4136, 20619,
++ 41, 42, 99, 100, 140, 141, 161, 163, 164, 165, 178, 188, 193, 194, 247, 248,
++ 249, 250, 251, 252, 253, 254, 255, 256, 257, 258, 260, 261, 262, 263, 264,
++ 266, 268, 269, 270, 287, 288, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 2315,
++ 4136, 20619,
+ };
+
+ static const unsigned short dep163[] = {
+- 61, 98, 100, 259, 287, 288, 2143, 2333,
++ 61, 98, 100, 259, 287, 288, 2143, 2333,
+ };
+
+ static const unsigned short dep164[] = {
+- 41, 42, 44, 45, 47, 49, 50, 52, 53, 54, 55, 56, 58, 59, 62, 63, 65, 66, 67,
+- 68, 69, 71, 72, 73, 97, 98, 100, 140, 141, 161, 163, 164, 165, 178, 188, 193,
+- 194, 259, 287, 288, 2109, 2118, 2169, 2170, 2173, 2176, 2333, 4136, 20619,
+-
++ 41, 42, 44, 45, 47, 49, 50, 52, 53, 54, 55, 56, 58, 59, 62, 63, 65, 66, 67,
++ 68, 69, 71, 72, 73, 97, 98, 100, 140, 141, 161, 163, 164, 165, 178, 188, 193,
++ 194, 259, 287, 288, 2109, 2118, 2169, 2170, 2173, 2176, 2333, 4136, 20619,
++
+ };
+
+ static const unsigned short dep165[] = {
+- 2, 28, 42, 100, 200, 234, 245, 288, 2143, 2333, 28869, 29024,
++ 2, 28, 42, 100, 200, 234, 245, 288, 2143, 2333, 28869, 29024,
+ };
+
+ static const unsigned short dep166[] = {
+- 2, 25, 26, 28, 29, 39, 41, 42, 100, 161, 165, 178, 180, 181, 188, 200, 234,
+- 245, 288, 2333, 4136, 20619, 28869, 29024,
++ 2, 25, 26, 28, 29, 39, 41, 42, 100, 161, 165, 178, 180, 181, 188, 200, 234,
++ 245, 288, 2333, 4136, 20619, 28869, 29024,
+ };
+
+ static const unsigned short dep167[] = {
+- 100, 132, 133, 136, 137, 143, 144, 147, 148, 150, 151, 153, 154, 156, 157,
+- 160, 162, 163, 168, 169, 172, 173, 174, 175, 177, 179, 180, 182, 183, 185,
+- 186, 189, 190, 192, 288, 315, 316, 320, 322, 323, 324, 325, 327, 329, 333,
+- 336, 337, 339, 340, 341, 342, 344, 345, 346, 348, 349,
++ 100, 132, 133, 136, 137, 143, 144, 147, 148, 150, 151, 153, 154, 156, 157,
++ 160, 162, 163, 168, 169, 172, 173, 174, 175, 177, 179, 180, 182, 183, 185,
++ 186, 189, 190, 192, 288, 315, 316, 320, 322, 323, 324, 325, 327, 329, 333,
++ 336, 337, 339, 340, 341, 342, 344, 345, 346, 348, 349,
+ };
+
+ static const unsigned short dep168[] = {
+- 41, 42, 100, 140, 141, 161, 165, 178, 188, 193, 194, 288, 315, 316, 320, 322,
+- 323, 324, 325, 327, 329, 333, 336, 337, 339, 340, 341, 342, 344, 345, 346,
+- 348, 349, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 4136, 20619, 34890,
++ 41, 42, 100, 140, 141, 161, 165, 178, 188, 193, 194, 288, 315, 316, 320, 322,
++ 323, 324, 325, 327, 329, 333, 336, 337, 339, 340, 341, 342, 344, 345, 346,
++ 348, 349, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 4136, 20619, 34890,
+ };
+
+ static const unsigned short dep169[] = {
+- 100, 131, 133, 135, 137, 172, 173, 192, 288, 315, 316, 336, 337, 339, 340,
+- 349,
++ 100, 131, 133, 135, 137, 172, 173, 192, 288, 315, 316, 336, 337, 339, 340,
++ 349,
+ };
+
+ static const unsigned short dep170[] = {
+- 41, 42, 100, 161, 165, 178, 186, 187, 188, 288, 315, 316, 336, 337, 339, 340,
+- 349, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 4136, 20619,
++ 41, 42, 100, 161, 165, 178, 186, 187, 188, 288, 315, 316, 336, 337, 339, 340,
++ 349, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 4136, 20619,
+ };
+
+ static const unsigned short dep171[] = {
+- 41, 42, 100, 133, 134, 137, 138, 140, 141, 144, 145, 148, 149, 151, 152, 154,
+- 155, 157, 158, 160, 161, 162, 164, 165, 167, 168, 170, 171, 172, 173, 175,
+- 176, 177, 178, 179, 181, 182, 184, 185, 187, 188, 190, 191, 192, 193, 194,
+- 288, 2169, 2170, 2173, 2176, 2333, 4136, 20619,
++ 41, 42, 100, 133, 134, 137, 138, 140, 141, 144, 145, 148, 149, 151, 152, 154,
++ 155, 157, 158, 160, 161, 162, 164, 165, 167, 168, 170, 171, 172, 173, 175,
++ 176, 177, 178, 179, 181, 182, 184, 185, 187, 188, 190, 191, 192, 193, 194,
++ 288, 2169, 2170, 2173, 2176, 2333, 4136, 20619,
+ };
+
+ static const unsigned short dep172[] = {
+- 41, 42, 100, 133, 134, 137, 138, 161, 165, 172, 173, 178, 188, 192, 288, 2169,
+- 2170, 2173, 2176, 2333, 4136, 20619,
++ 41, 42, 100, 133, 134, 137, 138, 161, 165, 172, 173, 178, 188, 192, 288, 2169,
++ 2170, 2173, 2176, 2333, 4136, 20619,
+ };
+
+ static const unsigned short dep173[] = {
+- 41, 42, 72, 79, 80, 85, 87, 100, 114, 140, 141, 156, 158, 161, 165, 174, 176,
+- 178, 188, 195, 288, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 2333, 4136,
+- 20619,
++ 41, 42, 72, 79, 80, 85, 87, 100, 114, 140, 141, 156, 158, 161, 165, 174, 176,
++ 178, 188, 195, 288, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 2333, 4136,
++ 20619,
+ };
+
+ static const unsigned short dep174[] = {
+- 41, 42, 72, 79, 80, 85, 87, 100, 114, 140, 141, 142, 143, 145, 146, 156, 158,
+- 161, 165, 174, 176, 178, 188, 195, 288, 2141, 2142, 2143, 2169, 2170, 2173,
+- 2176, 4136, 20619,
++ 41, 42, 72, 79, 80, 85, 87, 100, 114, 140, 141, 142, 143, 145, 146, 156, 158,
++ 161, 165, 174, 176, 178, 188, 195, 288, 2141, 2142, 2143, 2169, 2170, 2173,
++ 2176, 4136, 20619,
+ };
+
+ static const unsigned short dep175[] = {
+- 80, 81, 100, 104, 105, 275, 276, 288, 290, 291,
++ 80, 81, 100, 104, 105, 275, 276, 288, 290, 291,
+ };
+
+ static const unsigned short dep176[] = {
+- 41, 42, 48, 64, 81, 83, 89, 100, 102, 105, 140, 141, 161, 163, 164, 165, 178,
+- 188, 193, 194, 195, 275, 276, 288, 290, 291, 2141, 2142, 2143, 2169, 2170,
+- 2173, 2176, 4136, 20619,
++ 41, 42, 48, 64, 81, 83, 89, 100, 102, 105, 140, 141, 161, 163, 164, 165, 178,
++ 188, 193, 194, 195, 275, 276, 288, 290, 291, 2141, 2142, 2143, 2169, 2170,
++ 2173, 2176, 4136, 20619,
+ };
+
+ static const unsigned short dep177[] = {
+- 41, 42, 48, 64, 81, 83, 100, 102, 105, 107, 109, 140, 141, 161, 163, 164,
+- 165, 178, 188, 193, 194, 195, 275, 276, 288, 290, 291, 2141, 2142, 2143, 2169,
+- 2170, 2173, 2176, 4136, 20619,
++ 41, 42, 48, 64, 81, 83, 100, 102, 105, 107, 109, 140, 141, 161, 163, 164,
++ 165, 178, 188, 193, 194, 195, 275, 276, 288, 290, 291, 2141, 2142, 2143, 2169,
++ 2170, 2173, 2176, 4136, 20619,
+ };
+
+ static const unsigned short dep178[] = {
+- 100, 288, 12483, 12484, 12639,
++ 100, 288, 12483, 12484, 12639,
+ };
+
+ static const unsigned short dep179[] = {
+- 41, 42, 100, 140, 141, 161, 165, 178, 188, 193, 194, 288, 2141, 2142, 2143,
+- 2169, 2170, 2173, 2176, 4136, 12639, 20619,
++ 41, 42, 100, 140, 141, 161, 165, 178, 188, 193, 194, 288, 2141, 2142, 2143,
++ 2169, 2170, 2173, 2176, 4136, 12639, 20619,
+ };
+
+ static const unsigned short dep180[] = {
+- 100, 288, 6222, 6223, 6417,
++ 100, 288, 6222, 6223, 6417,
+ };
+
+ static const unsigned short dep181[] = {
+- 41, 42, 100, 140, 141, 161, 165, 178, 188, 193, 194, 288, 2141, 2142, 2143,
+- 2169, 2170, 2173, 2176, 4136, 6417, 20619,
++ 41, 42, 100, 140, 141, 161, 165, 178, 188, 193, 194, 288, 2141, 2142, 2143,
++ 2169, 2170, 2173, 2176, 4136, 6417, 20619,
+ };
+
+ static const unsigned short dep182[] = {
+- 100, 288, 6240, 6430,
++ 100, 288, 6240, 6430,
+ };
+
+ static const unsigned short dep183[] = {
+- 41, 42, 100, 140, 141, 161, 165, 178, 188, 193, 194, 288, 2141, 2142, 2143,
+- 2169, 2170, 2173, 2176, 4136, 6430, 20619,
++ 41, 42, 100, 140, 141, 161, 165, 178, 188, 193, 194, 288, 2141, 2142, 2143,
++ 2169, 2170, 2173, 2176, 4136, 6430, 20619,
+ };
+
+ static const unsigned short dep184[] = {
+- 100, 288, 6258, 6259, 6260, 6261, 6441, 6443, 8490,
++ 100, 288, 6258, 6259, 6260, 6261, 6441, 6443, 8490,
+ };
+
+ static const unsigned short dep185[] = {
+- 41, 42, 100, 140, 141, 161, 165, 178, 188, 193, 194, 288, 2141, 2142, 2143,
+- 2169, 2170, 2173, 2176, 4136, 6261, 6442, 6443, 8307, 8489, 20619,
++ 41, 42, 100, 140, 141, 161, 165, 178, 188, 193, 194, 288, 2141, 2142, 2143,
++ 2169, 2170, 2173, 2176, 4136, 6261, 6442, 6443, 8307, 8489, 20619,
+ };
+
+ static const unsigned short dep186[] = {
+- 100, 288, 6262, 6263, 6444,
++ 100, 288, 6262, 6263, 6444,
+ };
+
+ static const unsigned short dep187[] = {
+- 41, 42, 100, 140, 141, 161, 165, 178, 188, 193, 194, 288, 2141, 2142, 2143,
+- 2169, 2170, 2173, 2176, 4136, 6444, 20619,
++ 41, 42, 100, 140, 141, 161, 165, 178, 188, 193, 194, 288, 2141, 2142, 2143,
++ 2169, 2170, 2173, 2176, 4136, 6444, 20619,
+ };
+
+ static const unsigned short dep188[] = {
+- 100, 288, 6264, 6445,
++ 100, 288, 6264, 6445,
+ };
+
+ static const unsigned short dep189[] = {
+- 41, 42, 100, 140, 141, 161, 165, 178, 188, 193, 194, 288, 2141, 2142, 2143,
+- 2169, 2170, 2173, 2176, 4136, 6445, 20619,
++ 41, 42, 100, 140, 141, 161, 165, 178, 188, 193, 194, 288, 2141, 2142, 2143,
++ 2169, 2170, 2173, 2176, 4136, 6445, 20619,
+ };
+
+ static const unsigned short dep190[] = {
+- 100, 288, 10353, 10536,
++ 100, 288, 10353, 10536,
+ };
+
+ static const unsigned short dep191[] = {
+- 41, 42, 100, 140, 141, 161, 165, 178, 188, 193, 194, 288, 2141, 2142, 2143,
+- 2169, 2170, 2173, 2176, 4136, 10536, 20619,
++ 41, 42, 100, 140, 141, 161, 165, 178, 188, 193, 194, 288, 2141, 2142, 2143,
++ 2169, 2170, 2173, 2176, 4136, 10536, 20619,
+ };
+
+ static const unsigned short dep192[] = {
+- 80, 81, 85, 86, 100, 104, 105, 275, 276, 278, 279, 288, 290, 291,
++ 80, 81, 85, 86, 100, 104, 105, 275, 276, 278, 279, 288, 290, 291,
+ };
+
+ static const unsigned short dep193[] = {
+- 41, 42, 48, 64, 81, 83, 86, 89, 100, 102, 105, 140, 141, 161, 163, 164, 165,
+- 178, 188, 193, 194, 195, 275, 276, 278, 280, 288, 290, 291, 2141, 2142, 2143,
+- 2169, 2170, 2173, 2176, 4136, 20619,
++ 41, 42, 48, 64, 81, 83, 86, 89, 100, 102, 105, 140, 141, 161, 163, 164, 165,
++ 178, 188, 193, 194, 195, 275, 276, 278, 280, 288, 290, 291, 2141, 2142, 2143,
++ 2169, 2170, 2173, 2176, 4136, 20619,
+ };
+
+ static const unsigned short dep194[] = {
+- 80, 81, 100, 104, 105, 107, 108, 275, 276, 288, 290, 291, 292, 293,
++ 80, 81, 100, 104, 105, 107, 108, 275, 276, 288, 290, 291, 292, 293,
+ };
+
+ static const unsigned short dep195[] = {
+- 41, 42, 48, 64, 81, 83, 100, 102, 105, 107, 109, 140, 141, 161, 163, 164,
+- 165, 178, 188, 193, 194, 195, 275, 276, 288, 290, 291, 292, 293, 2141, 2142,
+- 2143, 2169, 2170, 2173, 2176, 4136, 20619,
++ 41, 42, 48, 64, 81, 83, 100, 102, 105, 107, 109, 140, 141, 161, 163, 164,
++ 165, 178, 188, 193, 194, 195, 275, 276, 288, 290, 291, 292, 293, 2141, 2142,
++ 2143, 2169, 2170, 2173, 2176, 4136, 20619,
+ };
+
+ static const unsigned short dep196[] = {
+- 41, 42, 100, 140, 141, 161, 165, 178, 188, 193, 194, 288, 2141, 2142, 2143,
+- 2169, 2170, 2173, 2176, 2333, 4136, 12484, 20619,
++ 41, 42, 100, 140, 141, 161, 165, 178, 188, 193, 194, 288, 2141, 2142, 2143,
++ 2169, 2170, 2173, 2176, 2333, 4136, 12484, 20619,
+ };
+
+ static const unsigned short dep197[] = {
+- 41, 42, 100, 140, 141, 161, 165, 178, 188, 193, 194, 288, 2141, 2142, 2143,
+- 2169, 2170, 2173, 2176, 2333, 4136, 6222, 20619,
++ 41, 42, 100, 140, 141, 161, 165, 178, 188, 193, 194, 288, 2141, 2142, 2143,
++ 2169, 2170, 2173, 2176, 2333, 4136, 6222, 20619,
+ };
+
+ static const unsigned short dep198[] = {
+- 41, 42, 100, 140, 141, 161, 165, 178, 188, 193, 194, 288, 2141, 2142, 2143,
+- 2169, 2170, 2173, 2176, 2333, 4136, 6240, 20619,
++ 41, 42, 100, 140, 141, 161, 165, 178, 188, 193, 194, 288, 2141, 2142, 2143,
++ 2169, 2170, 2173, 2176, 2333, 4136, 6240, 20619,
+ };
+
+ static const unsigned short dep199[] = {
+- 41, 42, 100, 140, 141, 161, 165, 178, 188, 193, 194, 288, 2141, 2142, 2143,
+- 2169, 2170, 2173, 2176, 2333, 4136, 6260, 8306, 20619,
++ 41, 42, 100, 140, 141, 161, 165, 178, 188, 193, 194, 288, 2141, 2142, 2143,
++ 2169, 2170, 2173, 2176, 2333, 4136, 6260, 8306, 20619,
+ };
+
+ static const unsigned short dep200[] = {
+- 41, 42, 100, 140, 141, 161, 165, 178, 188, 193, 194, 288, 2141, 2142, 2143,
+- 2169, 2170, 2173, 2176, 2333, 4136, 6262, 20619,
++ 41, 42, 100, 140, 141, 161, 165, 178, 188, 193, 194, 288, 2141, 2142, 2143,
++ 2169, 2170, 2173, 2176, 2333, 4136, 6262, 20619,
+ };
+
+ static const unsigned short dep201[] = {
+- 41, 42, 100, 140, 141, 161, 165, 178, 186, 187, 188, 288, 2141, 2142, 2143,
+- 2169, 2170, 2173, 2176, 2333, 4136, 6263, 6264, 20619,
++ 41, 42, 100, 140, 141, 161, 165, 178, 186, 187, 188, 288, 2141, 2142, 2143,
++ 2169, 2170, 2173, 2176, 2333, 4136, 6263, 6264, 20619,
+ };
+
+ static const unsigned short dep202[] = {
+- 41, 42, 100, 161, 165, 178, 188, 288, 2141, 2142, 2143, 2169, 2170, 2173,
+- 2176, 2333, 4136, 10353, 20619,
++ 41, 42, 100, 161, 165, 178, 188, 288, 2141, 2142, 2143, 2169, 2170, 2173,
++ 2176, 2333, 4136, 10353, 20619,
+ };
+
+ static const unsigned short dep203[] = {
+- 41, 42, 100, 161, 165, 178, 188, 193, 194, 288, 2141, 2142, 2143, 2169, 2170,
+- 2173, 2176, 2333, 4136, 6187, 20619,
++ 41, 42, 100, 161, 165, 178, 188, 193, 194, 288, 2141, 2142, 2143, 2169, 2170,
++ 2173, 2176, 2333, 4136, 6187, 20619,
+ };
+
+ static const unsigned short dep204[] = {
+- 80, 82, 83, 100, 101, 102, 103, 274, 275, 288, 289, 290,
++ 80, 82, 83, 100, 101, 102, 103, 274, 275, 288, 289, 290,
+ };
+
+ static const unsigned short dep205[] = {
+- 41, 42, 81, 82, 86, 88, 100, 103, 105, 107, 110, 140, 141, 161, 165, 178,
+- 188, 193, 194, 195, 274, 276, 288, 289, 291, 2141, 2142, 2143, 2169, 2170,
+- 2173, 2176, 4136, 20619,
++ 41, 42, 81, 82, 86, 88, 100, 103, 105, 107, 110, 140, 141, 161, 165, 178,
++ 188, 193, 194, 195, 274, 276, 288, 289, 291, 2141, 2142, 2143, 2169, 2170,
++ 2173, 2176, 4136, 20619,
+ };
+
+ static const unsigned short dep206[] = {
+- 80, 82, 83, 84, 100, 101, 102, 103, 106, 274, 275, 277, 288, 289, 290,
++ 80, 82, 83, 84, 100, 101, 102, 103, 106, 274, 275, 277, 288, 289, 290,
+ };
+
+ static const unsigned short dep207[] = {
+- 41, 42, 81, 82, 84, 86, 88, 100, 103, 105, 106, 107, 110, 140, 141, 161, 165,
+- 178, 188, 193, 194, 195, 274, 276, 277, 288, 289, 291, 2141, 2142, 2143, 2169,
+- 2170, 2173, 2176, 4136, 20619,
++ 41, 42, 81, 82, 84, 86, 88, 100, 103, 105, 106, 107, 110, 140, 141, 161, 165,
++ 178, 188, 193, 194, 195, 274, 276, 277, 288, 289, 291, 2141, 2142, 2143, 2169,
++ 2170, 2173, 2176, 4136, 20619,
+ };
+
+ static const unsigned short dep208[] = {
+- 80, 82, 83, 87, 88, 89, 100, 101, 102, 103, 274, 275, 280, 281, 288, 289,
+- 290,
++ 80, 82, 83, 87, 88, 89, 100, 101, 102, 103, 274, 275, 280, 281, 288, 289,
++ 290,
+ };
+
+ static const unsigned short dep209[] = {
+- 41, 42, 81, 82, 86, 88, 100, 103, 105, 140, 141, 161, 165, 178, 188, 193,
+- 194, 195, 274, 276, 279, 281, 288, 289, 291, 2141, 2142, 2143, 2169, 2170,
+- 2173, 2176, 4136, 20619,
++ 41, 42, 81, 82, 86, 88, 100, 103, 105, 140, 141, 161, 165, 178, 188, 193,
++ 194, 195, 274, 276, 279, 281, 288, 289, 291, 2141, 2142, 2143, 2169, 2170,
++ 2173, 2176, 4136, 20619,
+ };
+
+ static const unsigned short dep210[] = {
+- 80, 82, 83, 100, 101, 102, 103, 109, 110, 111, 274, 275, 288, 289, 290, 293,
+- 294,
++ 80, 82, 83, 100, 101, 102, 103, 109, 110, 111, 274, 275, 288, 289, 290, 293,
++ 294,
+ };
+
+ static const unsigned short dep211[] = {
+- 41, 42, 81, 82, 100, 103, 105, 107, 110, 140, 141, 161, 165, 178, 188, 193,
+- 194, 195, 274, 276, 288, 289, 291, 292, 294, 2141, 2142, 2143, 2169, 2170,
+- 2173, 2176, 4136, 20619,
++ 41, 42, 81, 82, 100, 103, 105, 107, 110, 140, 141, 161, 165, 178, 188, 193,
++ 194, 195, 274, 276, 288, 289, 291, 292, 294, 2141, 2142, 2143, 2169, 2170,
++ 2173, 2176, 4136, 20619,
+ };
+
+ static const unsigned short dep212[] = {
+- 41, 42, 47, 72, 100, 161, 165, 178, 188, 193, 194, 195, 288, 2141, 2142, 2143,
+- 2169, 2170, 2173, 2176, 2333, 4136, 20619,
++ 41, 42, 47, 72, 100, 161, 165, 178, 188, 193, 194, 195, 288, 2141, 2142, 2143,
++ 2169, 2170, 2173, 2176, 2333, 4136, 20619,
+ };
+
+ static const unsigned short dep213[] = {
+- 41, 42, 100, 161, 165, 178, 188, 193, 194, 195, 288, 2141, 2142, 2143, 2169,
+- 2170, 2173, 2176, 2333, 4136, 20619,
++ 41, 42, 100, 161, 165, 178, 188, 193, 194, 195, 288, 2141, 2142, 2143, 2169,
++ 2170, 2173, 2176, 2333, 4136, 20619,
+ };
+
+ static const unsigned short dep214[] = {
+- 41, 42, 72, 80, 85, 87, 100, 140, 141, 156, 158, 161, 165, 178, 188, 193,
+- 194, 195, 288, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 2333, 4136, 20619,
+-
++ 41, 42, 72, 80, 85, 87, 100, 140, 141, 156, 158, 161, 165, 178, 188, 193,
++ 194, 195, 288, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 2333, 4136, 20619,
++
+ };
+
+ static const unsigned short dep215[] = {
+- 41, 42, 100, 161, 165, 167, 178, 188, 189, 191, 288, 2138, 2139, 2140, 2141,
+- 2142, 2143, 2169, 2170, 2173, 2176, 4136, 16531, 16533, 16534, 16536, 20619,
+-
++ 41, 42, 100, 161, 165, 167, 178, 188, 189, 191, 288, 2138, 2139, 2140, 2141,
++ 2142, 2143, 2169, 2170, 2173, 2176, 4136, 16531, 16533, 16534, 16536, 20619,
++
+ };
+
+ static const unsigned short dep216[] = {
+- 41, 42, 72, 80, 85, 87, 100, 156, 158, 161, 165, 178, 188, 195, 288, 2141,
+- 2142, 2143, 2169, 2170, 2173, 2176, 4136, 20619,
++ 41, 42, 72, 80, 85, 87, 100, 156, 158, 161, 165, 178, 188, 195, 288, 2141,
++ 2142, 2143, 2169, 2170, 2173, 2176, 4136, 20619,
+ };
+
+ static const unsigned short dep217[] = {
+- 41, 42, 81, 82, 100, 103, 140, 141, 161, 165, 178, 188, 193, 194, 274, 276,
+- 288, 289, 291, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 4136, 20619,
++ 41, 42, 81, 82, 100, 103, 140, 141, 161, 165, 178, 188, 193, 194, 274, 276,
++ 288, 289, 291, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 4136, 20619,
+ };
+
+ static const unsigned short dep218[] = {
+- 41, 42, 72, 77, 79, 80, 85, 87, 100, 112, 114, 131, 132, 134, 135, 136, 138,
+- 140, 141, 142, 143, 145, 146, 156, 158, 161, 165, 174, 176, 178, 188, 193,
+- 194, 195, 288, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 2333, 4136, 20619,
+-
++ 41, 42, 72, 77, 79, 80, 85, 87, 100, 112, 114, 131, 132, 134, 135, 136, 138,
++ 140, 141, 142, 143, 145, 146, 156, 158, 161, 165, 174, 176, 178, 188, 193,
++ 194, 195, 288, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 2333, 4136, 20619,
++
+ };
+
+ static const unsigned short dep219[] = {
+- 41, 42, 45, 72, 77, 79, 80, 85, 87, 100, 112, 114, 131, 132, 134, 135, 136,
+- 138, 140, 141, 142, 143, 145, 146, 156, 158, 159, 161, 165, 174, 176, 178,
+- 188, 193, 194, 195, 288, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 2333, 4136,
+- 20619,
++ 41, 42, 45, 72, 77, 79, 80, 85, 87, 100, 112, 114, 131, 132, 134, 135, 136,
++ 138, 140, 141, 142, 143, 145, 146, 156, 158, 159, 161, 165, 174, 176, 178,
++ 188, 193, 194, 195, 288, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 2333, 4136,
++ 20619,
+ };
+
+ static const unsigned short dep220[] = {
+- 0, 100, 198, 288, 2143, 2333,
++ 0, 100, 198, 288, 2143, 2333,
+ };
+
+ static const unsigned short dep221[] = {
+- 0, 41, 42, 72, 77, 79, 80, 85, 87, 100, 112, 114, 131, 132, 134, 135, 136,
+- 138, 140, 141, 142, 143, 145, 146, 156, 158, 161, 165, 174, 176, 178, 188,
+- 193, 194, 195, 198, 288, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 2333, 4136,
+- 20619,
++ 0, 41, 42, 72, 77, 79, 80, 85, 87, 100, 112, 114, 131, 132, 134, 135, 136,
++ 138, 140, 141, 142, 143, 145, 146, 156, 158, 161, 165, 174, 176, 178, 188,
++ 193, 194, 195, 198, 288, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 2333, 4136,
++ 20619,
+ };
+
+ static const unsigned short dep222[] = {
+- 0, 41, 42, 45, 72, 77, 79, 80, 85, 87, 100, 112, 114, 131, 132, 134, 135,
+- 136, 138, 140, 141, 142, 143, 145, 146, 156, 158, 159, 161, 165, 174, 176,
+- 178, 188, 193, 194, 195, 198, 288, 2141, 2142, 2143, 2169, 2170, 2173, 2176,
+- 2333, 4136, 20619,
++ 0, 41, 42, 45, 72, 77, 79, 80, 85, 87, 100, 112, 114, 131, 132, 134, 135,
++ 136, 138, 140, 141, 142, 143, 145, 146, 156, 158, 159, 161, 165, 174, 176,
++ 178, 188, 193, 194, 195, 198, 288, 2141, 2142, 2143, 2169, 2170, 2173, 2176,
++ 2333, 4136, 20619,
+ };
+
+ static const unsigned short dep223[] = {
+- 32, 41, 42, 72, 77, 79, 80, 85, 87, 100, 112, 114, 131, 132, 134, 135, 136,
+- 138, 140, 141, 142, 143, 145, 146, 156, 158, 161, 165, 174, 176, 178, 188,
+- 193, 194, 195, 288, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 2333, 4136,
+- 20619,
++ 32, 41, 42, 72, 77, 79, 80, 85, 87, 100, 112, 114, 131, 132, 134, 135, 136,
++ 138, 140, 141, 142, 143, 145, 146, 156, 158, 161, 165, 174, 176, 178, 188,
++ 193, 194, 195, 288, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 2333, 4136,
++ 20619,
+ };
+
+ static const unsigned short dep224[] = {
+- 0, 100, 198, 288, 2333, 26718,
++ 0, 100, 198, 288, 2333, 26718,
+ };
+
+ static const unsigned short dep225[] = {
+- 5, 100, 203, 288, 2143, 2333,
++ 5, 100, 203, 288, 2143, 2333,
+ };
+
+ static const unsigned short dep226[] = {
+- 41, 42, 72, 77, 79, 80, 85, 87, 100, 112, 114, 131, 132, 134, 135, 136, 138,
+- 140, 141, 142, 143, 145, 146, 156, 158, 161, 165, 174, 176, 178, 188, 193,
+- 194, 195, 203, 288, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 2333, 4136,
+- 20619,
++ 41, 42, 72, 77, 79, 80, 85, 87, 100, 112, 114, 131, 132, 134, 135, 136, 138,
++ 140, 141, 142, 143, 145, 146, 156, 158, 161, 165, 174, 176, 178, 188, 193,
++ 194, 195, 203, 288, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 2333, 4136,
++ 20619,
+ };
+
+ static const unsigned short dep227[] = {
+- 0, 100, 112, 198, 288, 295,
++ 0, 100, 112, 198, 288, 295,
+ };
+
+ static const unsigned short dep228[] = {
+- 0, 41, 42, 72, 77, 79, 80, 85, 87, 100, 114, 131, 132, 134, 135, 136, 138,
+- 140, 141, 142, 143, 145, 146, 156, 158, 161, 165, 174, 176, 178, 188, 193,
+- 194, 195, 198, 288, 295, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 4136, 20619,
+-
++ 0, 41, 42, 72, 77, 79, 80, 85, 87, 100, 114, 131, 132, 134, 135, 136, 138,
++ 140, 141, 142, 143, 145, 146, 156, 158, 161, 165, 174, 176, 178, 188, 193,
++ 194, 195, 198, 288, 295, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 4136, 20619,
++
+ };
+
+ static const unsigned short dep229[] = {
+- 0, 5, 41, 42, 72, 77, 79, 80, 85, 87, 100, 114, 131, 132, 134, 135, 136, 138,
+- 140, 141, 142, 143, 145, 146, 156, 158, 161, 165, 174, 176, 178, 188, 193,
+- 194, 195, 198, 288, 295, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 4136, 20619,
+-
++ 0, 5, 41, 42, 72, 77, 79, 80, 85, 87, 100, 114, 131, 132, 134, 135, 136, 138,
++ 140, 141, 142, 143, 145, 146, 156, 158, 161, 165, 174, 176, 178, 188, 193,
++ 194, 195, 198, 288, 295, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 4136, 20619,
++
+ };
+
+ static const unsigned short dep230[] = {
+- 0, 32, 100, 112, 198, 238, 288, 295,
++ 0, 32, 100, 112, 198, 238, 288, 295,
+ };
+
+ static const unsigned short dep231[] = {
+- 0, 41, 42, 72, 77, 79, 80, 85, 87, 100, 114, 131, 132, 134, 135, 136, 138,
+- 140, 141, 142, 143, 145, 146, 156, 158, 161, 165, 174, 176, 178, 188, 193,
+- 194, 195, 198, 238, 288, 295, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 4136,
+- 20619,
++ 0, 41, 42, 72, 77, 79, 80, 85, 87, 100, 114, 131, 132, 134, 135, 136, 138,
++ 140, 141, 142, 143, 145, 146, 156, 158, 161, 165, 174, 176, 178, 188, 193,
++ 194, 195, 198, 238, 288, 295, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 4136,
++ 20619,
+ };
+
+ static const unsigned short dep232[] = {
+- 0, 100, 112, 198, 288, 295, 2143, 2333,
++ 0, 100, 112, 198, 288, 295, 2143, 2333,
+ };
+
+ static const unsigned short dep233[] = {
+- 0, 3, 41, 42, 72, 77, 79, 80, 85, 87, 100, 112, 114, 131, 132, 134, 135, 136,
+- 138, 140, 141, 142, 143, 145, 146, 156, 158, 161, 165, 174, 176, 178, 188,
+- 193, 194, 195, 198, 288, 295, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 2333,
+- 4136, 20619,
++ 0, 3, 41, 42, 72, 77, 79, 80, 85, 87, 100, 112, 114, 131, 132, 134, 135, 136,
++ 138, 140, 141, 142, 143, 145, 146, 156, 158, 161, 165, 174, 176, 178, 188,
++ 193, 194, 195, 198, 288, 295, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 2333,
++ 4136, 20619,
+ };
+
+ static const unsigned short dep234[] = {
+- 0, 3, 5, 41, 42, 72, 77, 79, 80, 85, 87, 100, 112, 114, 131, 132, 134, 135,
+- 136, 138, 140, 141, 142, 143, 145, 146, 156, 158, 161, 165, 174, 176, 178,
+- 188, 193, 194, 195, 198, 288, 295, 2141, 2142, 2143, 2169, 2170, 2173, 2176,
+- 2333, 4136, 20619,
++ 0, 3, 5, 41, 42, 72, 77, 79, 80, 85, 87, 100, 112, 114, 131, 132, 134, 135,
++ 136, 138, 140, 141, 142, 143, 145, 146, 156, 158, 161, 165, 174, 176, 178,
++ 188, 193, 194, 195, 198, 288, 295, 2141, 2142, 2143, 2169, 2170, 2173, 2176,
++ 2333, 4136, 20619,
+ };
+
+ static const unsigned short dep235[] = {
+- 0, 41, 42, 72, 77, 79, 80, 85, 87, 100, 112, 114, 131, 132, 134, 135, 136,
+- 138, 140, 141, 142, 143, 145, 146, 156, 158, 161, 165, 174, 176, 178, 188,
+- 193, 194, 195, 198, 288, 295, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 2333,
+- 4136, 20619,
++ 0, 41, 42, 72, 77, 79, 80, 85, 87, 100, 112, 114, 131, 132, 134, 135, 136,
++ 138, 140, 141, 142, 143, 145, 146, 156, 158, 161, 165, 174, 176, 178, 188,
++ 193, 194, 195, 198, 288, 295, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 2333,
++ 4136, 20619,
+ };
+
+ static const unsigned short dep236[] = {
+- 41, 42, 100, 161, 165, 178, 188, 288, 2138, 2139, 2140, 2169, 2170, 2173,
+- 2176, 2333, 4136, 16531, 16533, 16534, 16536, 20619,
++ 41, 42, 100, 161, 165, 178, 188, 288, 2138, 2139, 2140, 2169, 2170, 2173,
++ 2176, 2333, 4136, 16531, 16533, 16534, 16536, 20619,
+ };
+
+ static const unsigned short dep237[] = {
+- 0, 41, 42, 72, 77, 79, 80, 85, 87, 100, 114, 131, 132, 134, 135, 136, 138,
+- 140, 141, 142, 143, 145, 146, 156, 158, 161, 165, 174, 176, 178, 188, 193,
+- 194, 195, 198, 288, 295, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 2333, 4136,
+- 20619,
++ 0, 41, 42, 72, 77, 79, 80, 85, 87, 100, 114, 131, 132, 134, 135, 136, 138,
++ 140, 141, 142, 143, 145, 146, 156, 158, 161, 165, 174, 176, 178, 188, 193,
++ 194, 195, 198, 288, 295, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 2333, 4136,
++ 20619,
+ };
+
+ static const unsigned short dep238[] = {
+- 0, 32, 100, 112, 198, 238, 288, 295, 2143, 2333,
++ 0, 32, 100, 112, 198, 238, 288, 295, 2143, 2333,
+ };
+
+ static const unsigned short dep239[] = {
+- 0, 41, 42, 72, 77, 79, 80, 85, 87, 100, 114, 131, 132, 134, 135, 136, 138,
+- 140, 141, 142, 143, 145, 146, 156, 158, 161, 165, 174, 176, 178, 188, 193,
+- 194, 195, 198, 238, 288, 295, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 2333,
+- 4136, 20619,
++ 0, 41, 42, 72, 77, 79, 80, 85, 87, 100, 114, 131, 132, 134, 135, 136, 138,
++ 140, 141, 142, 143, 145, 146, 156, 158, 161, 165, 174, 176, 178, 188, 193,
++ 194, 195, 198, 238, 288, 295, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 2333,
++ 4136, 20619,
+ };
+
+ static const unsigned short dep240[] = {
+- 41, 42, 72, 77, 79, 80, 85, 87, 100, 112, 114, 131, 132, 134, 135, 136, 138,
+- 140, 141, 142, 143, 145, 146, 156, 158, 161, 165, 174, 176, 178, 188, 193,
+- 194, 195, 288, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 2331, 4136, 16531,
+- 16533, 16534, 16536, 18767, 18769, 18770, 18772, 20619,
++ 41, 42, 72, 77, 79, 80, 85, 87, 100, 112, 114, 131, 132, 134, 135, 136, 138,
++ 140, 141, 142, 143, 145, 146, 156, 158, 161, 165, 174, 176, 178, 188, 193,
++ 194, 195, 288, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 2331, 4136, 16531,
++ 16533, 16534, 16536, 18767, 18769, 18770, 18772, 20619,
+ };
+
+ static const unsigned short dep241[] = {
+- 41, 42, 45, 72, 77, 79, 80, 85, 87, 100, 112, 114, 131, 132, 134, 135, 136,
+- 138, 140, 141, 142, 143, 145, 146, 156, 158, 159, 161, 165, 174, 176, 178,
+- 188, 193, 194, 195, 288, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 2331, 4136,
+- 16531, 16533, 16534, 16536, 18767, 18769, 18770, 18772, 20619,
++ 41, 42, 45, 72, 77, 79, 80, 85, 87, 100, 112, 114, 131, 132, 134, 135, 136,
++ 138, 140, 141, 142, 143, 145, 146, 156, 158, 159, 161, 165, 174, 176, 178,
++ 188, 193, 194, 195, 288, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 2331, 4136,
++ 16531, 16533, 16534, 16536, 18767, 18769, 18770, 18772, 20619,
+ };
+
+ static const unsigned short dep242[] = {
+- 0, 100, 198, 288, 2139, 2331, 18604, 18605, 18767, 18768, 18770, 18771,
++ 0, 100, 198, 288, 2139, 2331, 18604, 18605, 18767, 18768, 18770, 18771,
+ };
+
+ static const unsigned short dep243[] = {
+- 0, 41, 42, 72, 77, 79, 80, 85, 87, 100, 112, 114, 131, 132, 134, 135, 136,
+- 138, 140, 141, 142, 143, 145, 146, 156, 158, 161, 165, 174, 176, 178, 188,
+- 193, 194, 195, 198, 288, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 2331, 4136,
+- 16531, 16533, 16534, 16536, 18767, 18769, 18770, 18772, 20619,
++ 0, 41, 42, 72, 77, 79, 80, 85, 87, 100, 112, 114, 131, 132, 134, 135, 136,
++ 138, 140, 141, 142, 143, 145, 146, 156, 158, 161, 165, 174, 176, 178, 188,
++ 193, 194, 195, 198, 288, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 2331, 4136,
++ 16531, 16533, 16534, 16536, 18767, 18769, 18770, 18772, 20619,
+ };
+
+ static const unsigned short dep244[] = {
+- 0, 41, 42, 45, 72, 77, 79, 80, 85, 87, 100, 112, 114, 131, 132, 134, 135,
+- 136, 138, 140, 141, 142, 143, 145, 146, 156, 158, 159, 161, 165, 174, 176,
+- 178, 188, 193, 194, 195, 198, 288, 2141, 2142, 2143, 2169, 2170, 2173, 2176,
+- 2331, 4136, 16531, 16533, 16534, 16536, 18767, 18769, 18770, 18772, 20619,
+-
++ 0, 41, 42, 45, 72, 77, 79, 80, 85, 87, 100, 112, 114, 131, 132, 134, 135,
++ 136, 138, 140, 141, 142, 143, 145, 146, 156, 158, 159, 161, 165, 174, 176,
++ 178, 188, 193, 194, 195, 198, 288, 2141, 2142, 2143, 2169, 2170, 2173, 2176,
++ 2331, 4136, 16531, 16533, 16534, 16536, 18767, 18769, 18770, 18772, 20619,
++
+ };
+
+ static const unsigned short dep245[] = {
+- 0, 100, 198, 288, 2140, 2331, 18604, 18605, 18767, 18768, 18770, 18771,
++ 0, 100, 198, 288, 2140, 2331, 18604, 18605, 18767, 18768, 18770, 18771,
+ };
+
+ static const unsigned short dep246[] = {
+- 100, 288, 2139, 2143, 2331, 2333, 18604, 18605, 18767, 18768, 18770, 18771,
+-
++ 100, 288, 2139, 2143, 2331, 2333, 18604, 18605, 18767, 18768, 18770, 18771,
++
+ };
+
+ static const unsigned short dep247[] = {
+- 41, 42, 72, 77, 79, 80, 85, 87, 100, 112, 114, 131, 132, 134, 135, 136, 138,
+- 140, 141, 142, 143, 145, 146, 156, 158, 161, 165, 174, 176, 178, 188, 193,
+- 194, 195, 288, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 2331, 2333, 4136,
+- 16531, 16533, 16534, 16536, 18767, 18769, 18770, 18772, 20619,
++ 41, 42, 72, 77, 79, 80, 85, 87, 100, 112, 114, 131, 132, 134, 135, 136, 138,
++ 140, 141, 142, 143, 145, 146, 156, 158, 161, 165, 174, 176, 178, 188, 193,
++ 194, 195, 288, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 2331, 2333, 4136,
++ 16531, 16533, 16534, 16536, 18767, 18769, 18770, 18772, 20619,
+ };
+
+ static const unsigned short dep248[] = {
+- 41, 42, 45, 72, 77, 79, 80, 85, 87, 100, 112, 114, 131, 132, 134, 135, 136,
+- 138, 140, 141, 142, 143, 145, 146, 156, 158, 159, 161, 165, 174, 176, 178,
+- 188, 193, 194, 195, 288, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 2331, 2333,
+- 4136, 16531, 16533, 16534, 16536, 18767, 18769, 18770, 18772, 20619,
++ 41, 42, 45, 72, 77, 79, 80, 85, 87, 100, 112, 114, 131, 132, 134, 135, 136,
++ 138, 140, 141, 142, 143, 145, 146, 156, 158, 159, 161, 165, 174, 176, 178,
++ 188, 193, 194, 195, 288, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 2331, 2333,
++ 4136, 16531, 16533, 16534, 16536, 18767, 18769, 18770, 18772, 20619,
+ };
+
+ static const unsigned short dep249[] = {
+- 0, 100, 198, 288, 2139, 2143, 2331, 2333, 18604, 18605, 18767, 18768, 18770,
+- 18771,
++ 0, 100, 198, 288, 2139, 2143, 2331, 2333, 18604, 18605, 18767, 18768, 18770,
++ 18771,
+ };
+
+ static const unsigned short dep250[] = {
+- 0, 41, 42, 72, 77, 79, 80, 85, 87, 100, 112, 114, 131, 132, 134, 135, 136,
+- 138, 140, 141, 142, 143, 145, 146, 156, 158, 161, 165, 174, 176, 178, 188,
+- 193, 194, 195, 198, 288, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 2331, 2333,
+- 4136, 16531, 16533, 16534, 16536, 18767, 18769, 18770, 18772, 20619,
++ 0, 41, 42, 72, 77, 79, 80, 85, 87, 100, 112, 114, 131, 132, 134, 135, 136,
++ 138, 140, 141, 142, 143, 145, 146, 156, 158, 161, 165, 174, 176, 178, 188,
++ 193, 194, 195, 198, 288, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 2331, 2333,
++ 4136, 16531, 16533, 16534, 16536, 18767, 18769, 18770, 18772, 20619,
+ };
+
+ static const unsigned short dep251[] = {
+- 0, 41, 42, 45, 72, 77, 79, 80, 85, 87, 100, 112, 114, 131, 132, 134, 135,
+- 136, 138, 140, 141, 142, 143, 145, 146, 156, 158, 159, 161, 165, 174, 176,
+- 178, 188, 193, 194, 195, 198, 288, 2141, 2142, 2143, 2169, 2170, 2173, 2176,
+- 2331, 2333, 4136, 16531, 16533, 16534, 16536, 18767, 18769, 18770, 18772,
+- 20619,
++ 0, 41, 42, 45, 72, 77, 79, 80, 85, 87, 100, 112, 114, 131, 132, 134, 135,
++ 136, 138, 140, 141, 142, 143, 145, 146, 156, 158, 159, 161, 165, 174, 176,
++ 178, 188, 193, 194, 195, 198, 288, 2141, 2142, 2143, 2169, 2170, 2173, 2176,
++ 2331, 2333, 4136, 16531, 16533, 16534, 16536, 18767, 18769, 18770, 18772,
++ 20619,
+ };
+
+ static const unsigned short dep252[] = {
+- 0, 100, 198, 288, 2140, 2143, 2331, 2333, 18604, 18605, 18767, 18768, 18770,
+- 18771,
++ 0, 100, 198, 288, 2140, 2143, 2331, 2333, 18604, 18605, 18767, 18768, 18770,
++ 18771,
+ };
+
+ static const unsigned short dep253[] = {
+- 0, 41, 42, 72, 77, 79, 80, 85, 87, 100, 114, 131, 132, 134, 135, 136, 138,
+- 140, 141, 142, 143, 145, 146, 156, 158, 161, 165, 174, 176, 178, 188, 193,
+- 194, 195, 198, 288, 295, 2138, 2139, 2140, 2141, 2142, 2143, 2169, 2170, 2173,
+- 2176, 4136, 16531, 16533, 16534, 16536, 20619,
++ 0, 41, 42, 72, 77, 79, 80, 85, 87, 100, 114, 131, 132, 134, 135, 136, 138,
++ 140, 141, 142, 143, 145, 146, 156, 158, 161, 165, 174, 176, 178, 188, 193,
++ 194, 195, 198, 288, 295, 2138, 2139, 2140, 2141, 2142, 2143, 2169, 2170, 2173,
++ 2176, 4136, 16531, 16533, 16534, 16536, 20619,
+ };
+
+ static const unsigned short dep254[] = {
+- 41, 42, 72, 79, 80, 85, 87, 100, 140, 141, 142, 143, 145, 146, 156, 158, 159,
+- 161, 165, 174, 176, 178, 188, 195, 288, 2169, 2170, 2173, 2176, 4136,
++ 41, 42, 72, 79, 80, 85, 87, 100, 140, 141, 142, 143, 145, 146, 156, 158, 159,
++ 161, 165, 174, 176, 178, 188, 195, 288, 2169, 2170, 2173, 2176, 4136,
+ };
+
+ static const unsigned short dep255[] = {
+- 41, 42, 72, 79, 80, 85, 87, 100, 140, 141, 142, 143, 145, 146, 156, 158, 159,
+- 161, 165, 174, 176, 178, 188, 195, 288, 2141, 2142, 2143, 2169, 2170, 2173,
+- 2176, 2333, 4136, 20619,
++ 41, 42, 72, 79, 80, 85, 87, 100, 140, 141, 142, 143, 145, 146, 156, 158, 159,
++ 161, 165, 174, 176, 178, 188, 195, 288, 2141, 2142, 2143, 2169, 2170, 2173,
++ 2176, 2333, 4136, 20619,
+ };
+
+ static const unsigned short dep256[] = {
+- 41, 42, 100, 161, 165, 178, 188, 288, 2141, 2142, 2143, 2169, 2170, 2173,
+- 2176, 2331, 4136, 16531, 16533, 16534, 16536, 18767, 18769, 18770, 18772,
+- 20619,
++ 41, 42, 100, 161, 165, 178, 188, 288, 2141, 2142, 2143, 2169, 2170, 2173,
++ 2176, 2331, 4136, 16531, 16533, 16534, 16536, 18767, 18769, 18770, 18772,
++ 20619,
+ };
+
+ static const unsigned short dep257[] = {
+- 0, 41, 42, 72, 77, 79, 80, 85, 87, 100, 114, 131, 132, 134, 135, 136, 138,
+- 140, 141, 142, 143, 145, 146, 156, 158, 161, 165, 174, 176, 178, 188, 193,
+- 194, 195, 198, 288, 295, 2138, 2139, 2140, 2141, 2142, 2143, 2169, 2170, 2173,
+- 2176, 2333, 4136, 16531, 16533, 16534, 16536, 20619,
++ 0, 41, 42, 72, 77, 79, 80, 85, 87, 100, 114, 131, 132, 134, 135, 136, 138,
++ 140, 141, 142, 143, 145, 146, 156, 158, 161, 165, 174, 176, 178, 188, 193,
++ 194, 195, 198, 288, 295, 2138, 2139, 2140, 2141, 2142, 2143, 2169, 2170, 2173,
++ 2176, 2333, 4136, 16531, 16533, 16534, 16536, 20619,
+ };
+
+ static const unsigned short dep258[] = {
+- 1, 6, 39, 41, 42, 100, 140, 141, 161, 165, 167, 178, 188, 189, 191, 199, 231,
+- 233, 245, 272, 288, 2169, 2171, 2172, 2174, 2175, 2177, 2178, 2290, 2292,
+- 4136, 28869, 29024,
++ 1, 6, 39, 41, 42, 100, 140, 141, 161, 165, 167, 178, 188, 189, 191, 199, 231,
++ 233, 245, 272, 288, 2169, 2171, 2172, 2174, 2175, 2177, 2178, 2290, 2292,
++ 4136, 28869, 29024,
+ };
+
+ static const unsigned short dep259[] = {
+- 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21,
+- 22, 24, 26, 27, 28, 29, 30, 31, 32, 100, 199, 200, 201, 202, 203, 204, 205,
+- 206, 207, 208, 209, 210, 211, 212, 214, 215, 217, 218, 220, 221, 223, 224,
+- 225, 226, 227, 228, 230, 233, 234, 235, 236, 237, 238, 272, 288, 2071, 2082,
+- 2143, 2277, 2288, 2333, 28869, 29024,
++ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21,
++ 22, 24, 26, 27, 28, 29, 30, 31, 32, 100, 199, 200, 201, 202, 203, 204, 205,
++ 206, 207, 208, 209, 210, 211, 212, 214, 215, 217, 218, 220, 221, 223, 224,
++ 225, 226, 227, 228, 230, 233, 234, 235, 236, 237, 238, 272, 288, 2071, 2082,
++ 2143, 2277, 2288, 2333, 28869, 29024,
+ };
+
+ static const unsigned short dep260[] = {
+- 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21,
+- 22, 24, 25, 26, 28, 29, 30, 31, 32, 41, 42, 100, 140, 141, 161, 165, 178,
+- 183, 184, 188, 193, 194, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208,
+- 209, 210, 211, 212, 214, 215, 217, 218, 220, 221, 223, 224, 225, 226, 227,
+- 228, 230, 232, 234, 235, 236, 237, 238, 272, 288, 2071, 2082, 2141, 2142,
+- 2143, 2169, 2170, 2173, 2176, 2277, 2288, 2333, 4136, 20619, 28869, 29024,
+-
++ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21,
++ 22, 24, 25, 26, 28, 29, 30, 31, 32, 41, 42, 100, 140, 141, 161, 165, 178,
++ 183, 184, 188, 193, 194, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208,
++ 209, 210, 211, 212, 214, 215, 217, 218, 220, 221, 223, 224, 225, 226, 227,
++ 228, 230, 232, 234, 235, 236, 237, 238, 272, 288, 2071, 2082, 2141, 2142,
++ 2143, 2169, 2170, 2173, 2176, 2277, 2288, 2333, 4136, 20619, 28869, 29024,
++
+ };
+
+ #define NELS(X) (sizeof(X)/sizeof(X[0]))
+@@ -6395,802 +6395,802 @@ main_table[] = {
+ };
+
+ static const char dis_table[] = {
+-0xa1, 0x02, 0x78, 0xa0, 0x2f, 0x28, 0xa0, 0x2d, 0x10, 0xa0, 0x1c, 0x40,
+-0x98, 0xb0, 0x02, 0x50, 0x90, 0x50, 0x90, 0x28, 0x24, 0x52, 0x40, 0x24,
+-0x52, 0x38, 0x90, 0x28, 0x24, 0x52, 0x30, 0x24, 0x52, 0x28, 0x91, 0x60,
+-0x90, 0x28, 0x24, 0x52, 0x18, 0x10, 0x10, 0x58, 0x41, 0x62, 0x90, 0x80,
+-0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+-0x10, 0x10, 0x52, 0xc0, 0xc0, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+-0x10, 0x10, 0x10, 0x24, 0x3d, 0x90, 0x90, 0x28, 0x24, 0x52, 0x08, 0x24,
+-0x52, 0x00, 0xa8, 0x0b, 0x88, 0x15, 0x60, 0x97, 0x60, 0x96, 0x08, 0x9a,
+-0xf8, 0x05, 0x78, 0x91, 0x58, 0x90, 0xe0, 0x90, 0xa0, 0x80, 0x90, 0x20,
+-0x37, 0xc9, 0x90, 0x20, 0x37, 0xc6, 0xcb, 0xa1, 0xf1, 0x00, 0xa4, 0x37,
+-0xf8, 0x37, 0x00, 0x80, 0xa4, 0x4f, 0xb8, 0x39, 0xfc, 0x90, 0x50, 0x90,
+-0x28, 0x80, 0x39, 0xf2, 0x80, 0x37, 0xaa, 0x81, 0x37, 0x03, 0x90, 0xe0,
+-0x90, 0x70, 0x90, 0x38, 0xa4, 0x3d, 0x30, 0x37, 0xa7, 0xa4, 0x38, 0x10,
+-0x37, 0xa4, 0x90, 0x38, 0xa4, 0x51, 0xb8, 0x3a, 0x3d, 0xa4, 0x51, 0x60,
+-0x3a, 0x31, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x50, 0x38, 0x3a, 0x12, 0xa4,
+-0x50, 0x10, 0x3a, 0x0d, 0x80, 0xa4, 0x3d, 0x10, 0x37, 0xa3, 0x92, 0x18,
+-0x91, 0xc0, 0x80, 0x91, 0x80, 0x90, 0xf8, 0xdb, 0x84, 0x61, 0xc1, 0x80,
+-0xc0, 0xc0, 0x80, 0xa4, 0x5b, 0x80, 0x8c, 0x5c, 0xe0, 0x84, 0x3b, 0xa6,
+-0xc0, 0xc0, 0x80, 0xa4, 0x5b, 0x70, 0x8c, 0x5c, 0xc0, 0x84, 0x3b, 0xa4,
+-0xd3, 0x82, 0x40, 0x50, 0xc0, 0xc0, 0x81, 0x3b, 0x58, 0x50, 0xc0, 0xc0,
+-0x81, 0x3b, 0x56, 0xa4, 0x38, 0x20, 0x37, 0x05, 0x80, 0x90, 0x28, 0x80,
+-0x37, 0x01, 0x80, 0x37, 0xac, 0x81, 0x90, 0x38, 0xa4, 0x3d, 0xa0, 0x37,
+-0xaf, 0xa4, 0x3d, 0x68, 0x37, 0xa9, 0xc0, 0x40, 0x10, 0x10, 0x90, 0x38,
+-0xa4, 0x37, 0xe8, 0x36, 0xfe, 0xa4, 0x37, 0xd8, 0x36, 0xfc, 0x18, 0x24,
+-0x3e, 0x18, 0x83, 0x90, 0xa8, 0xd3, 0x82, 0xc0, 0xc0, 0xc0, 0x80, 0xa4,
+-0x5b, 0x50, 0x3b, 0x90, 0xc0, 0xc0, 0x80, 0xa4, 0x5b, 0x40, 0x3b, 0x8c,
+-0xd3, 0x82, 0x40, 0x50, 0xc0, 0xc0, 0x81, 0x3b, 0x52, 0x50, 0xc0, 0xc0,
+-0x81, 0x3b, 0x50, 0x92, 0xb8, 0x99, 0x84, 0x3d, 0x88, 0x90, 0x78, 0x90,
+-0x50, 0x10, 0x10, 0x80, 0xa4, 0x4f, 0xb0, 0x39, 0xfb, 0x82, 0x39, 0xf1,
+-0x90, 0x80, 0x10, 0x10, 0x90, 0x38, 0xa4, 0x51, 0xb0, 0x3a, 0x3c, 0xa4,
+-0x51, 0x58, 0x3a, 0x30, 0x80, 0x90, 0x38, 0xa4, 0x50, 0x30, 0x3a, 0x11,
+-0xa4, 0x50, 0x08, 0x3a, 0x0c, 0x83, 0x90, 0xa8, 0xd3, 0x82, 0xc0, 0xc0,
+-0xc0, 0x80, 0xa4, 0x5b, 0x20, 0x3b, 0x84, 0xc0, 0xc0, 0x80, 0xa4, 0x5b,
+-0x10, 0x3b, 0x80, 0xd3, 0x82, 0x40, 0x50, 0xc0, 0xc0, 0x81, 0x3b, 0x4c,
+-0x50, 0xc0, 0xc0, 0x81, 0x3b, 0x4a, 0x18, 0x24, 0x3d, 0x98, 0x83, 0x90,
+-0xa8, 0xd3, 0x82, 0xc0, 0xc0, 0xc0, 0x80, 0xa4, 0x5a, 0xf0, 0x3b, 0x78,
+-0xc0, 0xc0, 0x80, 0xa4, 0x5a, 0xe0, 0x3b, 0x74, 0xd3, 0x82, 0x40, 0x50,
+-0xc0, 0xc0, 0x81, 0x3b, 0x46, 0x50, 0xc0, 0xc0, 0x81, 0x3b, 0x44, 0x94,
+-0x50, 0x92, 0xf8, 0x99, 0x84, 0x38, 0x50, 0x90, 0x78, 0x90, 0x50, 0x10,
+-0x10, 0x80, 0xa4, 0x4f, 0xa8, 0x39, 0xfa, 0x82, 0x39, 0xf0, 0x90, 0x80,
+-0x10, 0x10, 0x90, 0x38, 0xa4, 0x51, 0xa8, 0x3a, 0x3b, 0xa4, 0x51, 0x50,
+-0x3a, 0x2f, 0x80, 0x90, 0x38, 0xa4, 0x50, 0x28, 0x3a, 0x10, 0xa4, 0x50,
+-0x00, 0x3a, 0x0b, 0x83, 0x90, 0xe8, 0xd3, 0x83, 0xc0, 0xc0, 0xc0, 0x80,
+-0xa4, 0x5b, 0x90, 0x8c, 0x5d, 0x00, 0x84, 0x3b, 0xa8, 0xc0, 0xc0, 0x80,
+-0xa4, 0x5b, 0x78, 0x8c, 0x5c, 0xd0, 0x84, 0x3b, 0xa5, 0xd3, 0x82, 0x40,
+-0x50, 0xc0, 0xc0, 0x81, 0x3b, 0x5a, 0x50, 0xc0, 0xc0, 0x81, 0x3b, 0x57,
+-0x18, 0x24, 0x38, 0x48, 0x83, 0x90, 0xa8, 0xd3, 0x82, 0xc0, 0xc0, 0xc0,
+-0x80, 0xa4, 0x5b, 0x60, 0x3b, 0x94, 0xc0, 0xc0, 0x80, 0xa4, 0x5b, 0x48,
+-0x3b, 0x8e, 0xd3, 0x82, 0x40, 0x50, 0xc0, 0xc0, 0x81, 0x3b, 0x54, 0x50,
+-0xc0, 0xc0, 0x81, 0x3b, 0x51, 0x92, 0xb8, 0x99, 0x84, 0x38, 0x40, 0x90,
+-0x78, 0x90, 0x50, 0x10, 0x10, 0x80, 0xa4, 0x4f, 0xa0, 0x39, 0xf9, 0x82,
+-0x39, 0xef, 0x90, 0x80, 0x10, 0x10, 0x90, 0x38, 0xa4, 0x51, 0xa0, 0x3a,
+-0x3a, 0xa4, 0x51, 0x48, 0x3a, 0x2e, 0x80, 0x90, 0x38, 0xa4, 0x50, 0x20,
+-0x3a, 0x0f, 0xa4, 0x4f, 0xf8, 0x3a, 0x0a, 0x83, 0x90, 0xa8, 0xd3, 0x82,
+-0xc0, 0xc0, 0xc0, 0x80, 0xa4, 0x5b, 0x30, 0x3b, 0x88, 0xc0, 0xc0, 0x80,
+-0xa4, 0x5b, 0x18, 0x3b, 0x82, 0xd3, 0x82, 0x40, 0x50, 0xc0, 0xc0, 0x81,
+-0x3b, 0x4e, 0x50, 0xc0, 0xc0, 0x81, 0x3b, 0x4b, 0x18, 0x20, 0x01, 0x48,
+-0x83, 0x90, 0xa8, 0xd3, 0x82, 0xc0, 0xc0, 0xc0, 0x80, 0xa4, 0x5b, 0x00,
+-0x3b, 0x7c, 0xc0, 0xc0, 0x80, 0xa4, 0x5a, 0xe8, 0x3b, 0x76, 0xd3, 0x82,
+-0x40, 0x50, 0xc0, 0xc0, 0x81, 0x3b, 0x48, 0x50, 0xc0, 0xc0, 0x81, 0x3b,
+-0x45, 0xda, 0x06, 0xe1, 0xc1, 0xc0, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x3e,
+-0x08, 0x37, 0xbf, 0x80, 0x37, 0xbc, 0x90, 0x38, 0xa4, 0x3d, 0xb0, 0x37,
+-0xba, 0x80, 0x37, 0xb7, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x3d, 0xf0, 0x37,
+-0xc0, 0x80, 0x37, 0xbd, 0x90, 0x38, 0xa4, 0x3d, 0xc8, 0x37, 0xbb, 0x80,
+-0x37, 0xb8, 0xc8, 0x40, 0x19, 0x00, 0x91, 0x58, 0x90, 0x60, 0x82, 0x90,
+-0x20, 0x39, 0xee, 0xa4, 0x4f, 0x60, 0x39, 0xed, 0x90, 0xc0, 0x80, 0x90,
+-0x90, 0x90, 0x48, 0xc9, 0xe2, 0x89, 0xc0, 0x85, 0x3a, 0x26, 0xc9, 0xe2,
+-0x89, 0x00, 0x85, 0x3a, 0x23, 0x80, 0x3a, 0x22, 0x10, 0x10, 0x81, 0x39,
+-0xfe, 0x90, 0xa8, 0x10, 0x10, 0x90, 0x28, 0x81, 0x3a, 0x1c, 0x90, 0x38,
+-0xa4, 0x50, 0xb8, 0x3a, 0x18, 0xa4, 0x50, 0xa8, 0x3a, 0x16, 0x90, 0x70,
+-0x10, 0x10, 0x90, 0x38, 0xa4, 0x50, 0xd0, 0x3a, 0x1b, 0x80, 0x3a, 0x19,
+-0x90, 0x60, 0x90, 0x28, 0x24, 0x51, 0x08, 0xa4, 0x50, 0xf8, 0x3a, 0x20,
+-0x80, 0xa4, 0x50, 0xe8, 0x3a, 0x1e, 0x80, 0x90, 0xf8, 0x90, 0x90, 0x90,
+-0x50, 0x90, 0x28, 0x80, 0x3b, 0x3a, 0x80, 0x3b, 0x43, 0x80, 0xa4, 0x5a,
+-0x08, 0x3b, 0x42, 0x90, 0x28, 0x81, 0x3b, 0x40, 0x80, 0xa4, 0x59, 0xf0,
+-0x3b, 0x3f, 0x90, 0x28, 0x82, 0x3b, 0x3d, 0x81, 0xa4, 0x59, 0xd8, 0x3b,
+-0x3c, 0x98, 0xe8, 0x01, 0xb0, 0x90, 0x88, 0x90, 0x60, 0xa4, 0x4f, 0x50,
+-0x10, 0x10, 0x10, 0x10, 0x83, 0x36, 0xd5, 0x24, 0x4f, 0x48, 0x90, 0x28,
+-0x24, 0x4f, 0x40, 0x24, 0x4f, 0x38, 0x90, 0x88, 0x90, 0x60, 0xa4, 0x4f,
+-0x28, 0x10, 0x10, 0x10, 0x10, 0x83, 0x36, 0xd4, 0x24, 0x4f, 0x20, 0x90,
+-0x28, 0x24, 0x4f, 0x18, 0x24, 0x4f, 0x10, 0xa8, 0x09, 0x10, 0x0e, 0x30,
+-0x96, 0x58, 0x95, 0xf8, 0x93, 0x38, 0x91, 0xa0, 0x90, 0xd0, 0x90, 0x70,
+-0x90, 0x38, 0xa4, 0x37, 0x58, 0x36, 0xec, 0xa4, 0x37, 0x48, 0x36, 0xea,
+-0x90, 0x38, 0xa4, 0x37, 0x38, 0x36, 0xe8, 0x80, 0x36, 0xe6, 0x90, 0x60,
+-0x90, 0x28, 0x24, 0x36, 0xf0, 0xa4, 0x36, 0xe0, 0x36, 0xdd, 0x90, 0x38,
+-0xa4, 0x36, 0xd0, 0x36, 0xdb, 0xa4, 0x37, 0x20, 0x36, 0xe5, 0x90, 0xe0,
+-0x90, 0x70, 0x90, 0x38, 0xa4, 0x37, 0x10, 0x36, 0xe3, 0xa4, 0x37, 0x00,
+-0x36, 0xe1, 0x90, 0x38, 0xa4, 0x4e, 0xc8, 0x39, 0xdf, 0xa4, 0x4e, 0x68,
+-0x39, 0xd3, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x4b, 0xa8, 0x39, 0x81, 0xa4,
+-0x4b, 0x78, 0x39, 0x7b, 0x10, 0x10, 0xa4, 0x36, 0xc0, 0x36, 0xd9, 0x99,
+-0x70, 0x02, 0x80, 0x90, 0xa0, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x37, 0x88,
+-0x36, 0xdf, 0x80, 0x36, 0xf9, 0x80, 0xa4, 0x37, 0x90, 0x36, 0xf7, 0x90,
+-0x50, 0x90, 0x28, 0x24, 0x37, 0x98, 0x80, 0x36, 0xfa, 0x90, 0x38, 0xa4,
+-0x37, 0xa0, 0x36, 0xf8, 0xa4, 0x37, 0x68, 0x36, 0xee, 0x90, 0xe0, 0x90,
+-0x70, 0x90, 0x38, 0xa4, 0x4e, 0x00, 0x39, 0xc8, 0xa4, 0x4d, 0x60, 0x39,
+-0xb5, 0x90, 0x38, 0xa4, 0x4c, 0xf8, 0x39, 0xa6, 0xa4, 0x4c, 0x68, 0x39,
+-0x95, 0x81, 0xa4, 0x37, 0x78, 0x36, 0xf0, 0xe4, 0xa2, 0xcd, 0x00, 0x3b,
+-0x36, 0x18, 0x24, 0x36, 0xb8, 0xe4, 0xe2, 0xcb, 0x80, 0x3b, 0x30, 0x92,
+-0x40, 0x91, 0x08, 0x10, 0x10, 0x90, 0x80, 0x10, 0x10, 0x90, 0x38, 0xa4,
+-0x4e, 0xc0, 0x39, 0xde, 0xa4, 0x4e, 0x60, 0x39, 0xd2, 0x80, 0x90, 0x38,
+-0xa4, 0x4b, 0xa0, 0x39, 0x80, 0xa4, 0x4b, 0x70, 0x39, 0x7a, 0x18, 0x20,
+-0x00, 0xf8, 0x80, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x4d, 0xf0, 0x39, 0xc7,
+-0xa4, 0x4d, 0x58, 0x39, 0xb3, 0x90, 0x38, 0xa4, 0x4c, 0xe8, 0x39, 0xa5,
+-0xa4, 0x4c, 0x60, 0x39, 0x93, 0xe4, 0xa2, 0xca, 0x00, 0x3b, 0x2a, 0x18,
+-0x24, 0x36, 0xb0, 0xe4, 0xe2, 0xc8, 0x80, 0x3b, 0x24, 0x92, 0x90, 0x92,
+-0x40, 0x91, 0x08, 0x10, 0x10, 0x90, 0x80, 0x10, 0x10, 0x90, 0x38, 0xa4,
+-0x4e, 0xb8, 0x39, 0xdd, 0xa4, 0x4e, 0x58, 0x39, 0xd1, 0x80, 0x90, 0x38,
+-0xa4, 0x4b, 0x98, 0x39, 0x7f, 0xa4, 0x4b, 0x68, 0x39, 0x79, 0x18, 0x20,
+-0x00, 0xf8, 0x80, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x4d, 0xe0, 0x39, 0xc6,
+-0xa4, 0x4d, 0x50, 0x39, 0xb1, 0x90, 0x38, 0xa4, 0x4c, 0xd8, 0x39, 0xa4,
+-0xa4, 0x4c, 0x58, 0x39, 0x91, 0xe4, 0xa2, 0xcd, 0x40, 0x3b, 0x38, 0x10,
+-0x10, 0xe4, 0xe2, 0xcb, 0xc0, 0x3b, 0x32, 0x92, 0x50, 0x99, 0x1c, 0x37,
+-0xa8, 0x10, 0x10, 0x90, 0x80, 0x10, 0x10, 0x90, 0x38, 0xa4, 0x4e, 0xb0,
+-0x39, 0xdc, 0xa4, 0x4e, 0x50, 0x39, 0xd0, 0x80, 0x90, 0x38, 0xa4, 0x4b,
+-0x90, 0x39, 0x7e, 0xa4, 0x4b, 0x60, 0x39, 0x78, 0x18, 0x20, 0x00, 0xf8,
+-0x80, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x4d, 0xd0, 0x39, 0xc5, 0xa4, 0x4d,
+-0x48, 0x39, 0xaf, 0x90, 0x38, 0xa4, 0x4c, 0xc8, 0x39, 0xa3, 0xa4, 0x4c,
+-0x50, 0x39, 0x8f, 0xe4, 0xa2, 0xca, 0x40, 0x3b, 0x2c, 0x10, 0x10, 0xe4,
+-0xe2, 0xc8, 0xc0, 0x3b, 0x26, 0xc0, 0x40, 0x80, 0x10, 0x10, 0x81, 0x90,
+-0x90, 0x90, 0x48, 0xc9, 0xe2, 0x61, 0x40, 0x85, 0x39, 0x89, 0xc9, 0xe2,
+-0x61, 0xc0, 0x85, 0x39, 0x86, 0x80, 0x39, 0x84, 0x80, 0xd8, 0x47, 0x80,
+-0x0d, 0xc0, 0xc0, 0x80, 0x10, 0x10, 0x82, 0x90, 0x58, 0xd5, 0x81, 0x80,
+-0x80, 0x3b, 0x20, 0x80, 0x3b, 0x1e, 0xd5, 0x81, 0x80, 0x80, 0x3b, 0x1c,
+-0x80, 0x3b, 0x1a, 0xc0, 0x80, 0x10, 0x10, 0x82, 0x90, 0x58, 0xd5, 0x81,
+-0x80, 0x80, 0x3b, 0x21, 0x80, 0x3b, 0x1f, 0xd5, 0x81, 0x80, 0x80, 0x3b,
+-0x1d, 0x80, 0x3b, 0x1b, 0xc0, 0x80, 0x83, 0xa4, 0x58, 0xc0, 0x3b, 0x19,
+-0xa0, 0x79, 0x20, 0xa0, 0x61, 0xa0, 0xa8, 0x3e, 0x70, 0x54, 0x48, 0xa0,
+-0x21, 0x30, 0xa0, 0x14, 0xe0, 0xa0, 0x0a, 0xd8, 0x9d, 0x60, 0x0a, 0x90,
+-0x92, 0xa0, 0x91, 0x50, 0x90, 0xb0, 0x90, 0x58, 0xa4, 0x20, 0x60, 0xe1,
+-0xe1, 0xb3, 0x00, 0x36, 0xd3, 0xa4, 0x20, 0x80, 0xe1, 0xe1, 0xb2, 0xc0,
+-0x36, 0xd1, 0x90, 0x48, 0x80, 0xe1, 0xe1, 0xb2, 0x80, 0x36, 0xcf, 0xa4,
+-0x20, 0x70, 0xe1, 0xe1, 0xb2, 0x40, 0x36, 0xcd, 0x90, 0xb0, 0x90, 0x58,
+-0xa4, 0x20, 0x00, 0xe1, 0xe1, 0x9a, 0x40, 0x36, 0x70, 0xa4, 0x20, 0x20,
+-0xe1, 0xe1, 0x9a, 0x00, 0x36, 0x6e, 0x90, 0x48, 0x80, 0xe1, 0xe1, 0x99,
+-0xc0, 0x36, 0x6c, 0xa4, 0x20, 0x10, 0xe1, 0xe1, 0x99, 0x80, 0x36, 0x6a,
+-0x91, 0x50, 0x90, 0xb0, 0x90, 0x58, 0xa4, 0x1f, 0xa0, 0xe1, 0xe1, 0x81,
+-0x80, 0x36, 0x0d, 0xa4, 0x1f, 0xc0, 0xe1, 0xe1, 0x81, 0x40, 0x36, 0x0b,
+-0x90, 0x48, 0x80, 0xe1, 0xe1, 0x81, 0x00, 0x36, 0x09, 0xa4, 0x1f, 0xb0,
+-0xe1, 0xe1, 0x80, 0xc0, 0x36, 0x07, 0x90, 0xc0, 0x90, 0x68, 0xa4, 0x1f,
+-0x40, 0xe9, 0xe1, 0x68, 0xe1, 0x44, 0x00, 0x35, 0xaa, 0xa4, 0x1f, 0x60,
+-0xe1, 0xe1, 0x68, 0x80, 0x35, 0xa8, 0x90, 0x48, 0x80, 0xe1, 0xe1, 0x68,
+-0x40, 0x35, 0xa6, 0xa4, 0x1f, 0x50, 0xe1, 0xe1, 0x68, 0x00, 0x35, 0xa4,
+-0x92, 0xa0, 0x91, 0x50, 0x90, 0xb0, 0x90, 0x58, 0xa4, 0x20, 0x30, 0xe1,
+-0xe1, 0xb0, 0x80, 0x36, 0xbe, 0xa4, 0x20, 0x50, 0xe1, 0xe1, 0xb0, 0x40,
+-0x36, 0xc7, 0x90, 0x48, 0x80, 0xe1, 0xe1, 0xb0, 0x00, 0x36, 0xc5, 0xa4,
+-0x20, 0x40, 0xe1, 0xe1, 0xaf, 0xc0, 0x36, 0xc3, 0x90, 0xb0, 0x90, 0x58,
+-0xa4, 0x1f, 0xd0, 0xe1, 0xe1, 0x97, 0xc0, 0x36, 0x5b, 0xa4, 0x1f, 0xf0,
+-0xe1, 0xe1, 0x97, 0x80, 0x36, 0x64, 0x90, 0x48, 0x80, 0xe1, 0xe1, 0x97,
+-0x40, 0x36, 0x62, 0xa4, 0x1f, 0xe0, 0xe1, 0xe1, 0x97, 0x00, 0x36, 0x60,
+-0x91, 0x50, 0x90, 0xb0, 0x90, 0x58, 0xa4, 0x1f, 0x70, 0xe1, 0xe1, 0x7f,
+-0x00, 0x35, 0xf8, 0xa4, 0x1f, 0x90, 0xe1, 0xe1, 0x7e, 0xc0, 0x36, 0x01,
+-0x90, 0x48, 0x80, 0xe1, 0xe1, 0x7e, 0x80, 0x35, 0xff, 0xa4, 0x1f, 0x80,
+-0xe1, 0xe1, 0x7e, 0x40, 0x35, 0xfd, 0x90, 0xb0, 0x90, 0x58, 0xa4, 0x1f,
+-0x10, 0xe1, 0xe1, 0x66, 0x40, 0x35, 0x95, 0xa4, 0x1f, 0x30, 0xe1, 0xe1,
+-0x66, 0x00, 0x35, 0x9e, 0x90, 0x48, 0x80, 0xe1, 0xe1, 0x65, 0xc0, 0x35,
+-0x9c, 0xa4, 0x1f, 0x20, 0xe1, 0xe1, 0x65, 0x80, 0x35, 0x9a, 0xe4, 0xe2,
+-0x54, 0x00, 0x39, 0x64, 0x9d, 0x50, 0x09, 0xc0, 0x92, 0xa0, 0x91, 0x50,
+-0x90, 0xb0, 0x90, 0x58, 0xa4, 0x1e, 0xa8, 0xe1, 0xe1, 0xad, 0xc0, 0x36,
+-0xb3, 0xa4, 0x1e, 0xa0, 0xe1, 0xe1, 0xad, 0x80, 0x36, 0xbc, 0x90, 0x48,
+-0x80, 0xe1, 0xe1, 0xad, 0x40, 0x36, 0xba, 0xa4, 0x1e, 0x98, 0xe1, 0xe1,
+-0xad, 0x00, 0x36, 0xb8, 0x90, 0xb0, 0x90, 0x58, 0xa4, 0x1e, 0x90, 0xe1,
+-0xe1, 0x95, 0x00, 0x36, 0x50, 0xa4, 0x1e, 0x88, 0xe1, 0xe1, 0x94, 0xc0,
+-0x36, 0x59, 0x90, 0x48, 0x80, 0xe1, 0xe1, 0x94, 0x80, 0x36, 0x57, 0xa4,
+-0x1e, 0x80, 0xe1, 0xe1, 0x94, 0x40, 0x36, 0x55, 0x91, 0x50, 0x90, 0xb0,
+-0x90, 0x58, 0xa4, 0x1e, 0x78, 0xe1, 0xe1, 0x7c, 0x40, 0x35, 0xed, 0xa4,
+-0x1e, 0x70, 0xe1, 0xe1, 0x7c, 0x00, 0x35, 0xf6, 0x90, 0x48, 0x80, 0xe1,
+-0xe1, 0x7b, 0xc0, 0x35, 0xf4, 0xa4, 0x1e, 0x68, 0xe1, 0xe1, 0x7b, 0x80,
+-0x35, 0xf2, 0x90, 0xb0, 0x90, 0x58, 0xa4, 0x1e, 0x60, 0xe1, 0xe1, 0x63,
+-0x80, 0x35, 0x8a, 0xa4, 0x1e, 0x58, 0xe1, 0xe1, 0x63, 0x40, 0x35, 0x93,
+-0x90, 0x48, 0x80, 0xe1, 0xe1, 0x63, 0x00, 0x35, 0x91, 0xa4, 0x1e, 0x50,
+-0xe1, 0xe1, 0x62, 0xc0, 0x35, 0x8f, 0x92, 0x40, 0x91, 0x20, 0x90, 0x90,
+-0x90, 0x48, 0x80, 0xe1, 0xe1, 0xab, 0x00, 0x36, 0xa8, 0x80, 0xe1, 0xe1,
+-0xaa, 0xc0, 0x36, 0xb1, 0x90, 0x48, 0x80, 0xe1, 0xe1, 0xaa, 0x80, 0x36,
+-0xaf, 0x80, 0xe1, 0xe1, 0xaa, 0x40, 0x36, 0xad, 0x90, 0x90, 0x90, 0x48,
+-0x80, 0xe1, 0xe1, 0x92, 0x40, 0x36, 0x45, 0x80, 0xe1, 0xe1, 0x92, 0x00,
+-0x36, 0x4e, 0x90, 0x48, 0x80, 0xe1, 0xe1, 0x91, 0xc0, 0x36, 0x4c, 0x80,
+-0xe1, 0xe1, 0x91, 0x80, 0x36, 0x4a, 0x91, 0x20, 0x90, 0x90, 0x90, 0x48,
+-0x80, 0xe1, 0xe1, 0x79, 0x80, 0x35, 0xe2, 0x80, 0xe1, 0xe1, 0x79, 0x40,
+-0x35, 0xeb, 0x90, 0x48, 0x80, 0xe1, 0xe1, 0x79, 0x00, 0x35, 0xe9, 0x80,
+-0xe1, 0xe1, 0x78, 0xc0, 0x35, 0xe7, 0x90, 0x90, 0x90, 0x48, 0x80, 0xe1,
+-0xe1, 0x60, 0xc0, 0x35, 0x7f, 0x80, 0xe1, 0xe1, 0x60, 0x80, 0x35, 0x88,
+-0x90, 0x48, 0x80, 0xe1, 0xe1, 0x60, 0x40, 0x35, 0x86, 0x80, 0xe1, 0xe1,
+-0x60, 0x00, 0x35, 0x84, 0xe4, 0xe2, 0x2f, 0x00, 0x38, 0xe4, 0xa0, 0x0a,
+-0x08, 0x9c, 0xf0, 0x09, 0xc0, 0x92, 0x40, 0x91, 0x20, 0x90, 0x90, 0x90,
+-0x48, 0x80, 0xe1, 0xe1, 0xa8, 0x40, 0x36, 0x9d, 0x80, 0xe1, 0xe1, 0xa8,
+-0x00, 0x36, 0xa6, 0x90, 0x48, 0x80, 0xe1, 0xe1, 0xa7, 0xc0, 0x36, 0xa4,
+-0x80, 0xe1, 0xe1, 0xa7, 0x80, 0x36, 0xa2, 0x90, 0x90, 0x90, 0x48, 0x80,
+-0xe1, 0xe1, 0x8f, 0x80, 0x36, 0x3a, 0x80, 0xe1, 0xe1, 0x8f, 0x40, 0x36,
+-0x43, 0x90, 0x48, 0x80, 0xe1, 0xe1, 0x8f, 0x00, 0x36, 0x41, 0x80, 0xe1,
+-0xe1, 0x8e, 0xc0, 0x36, 0x3f, 0x91, 0x50, 0x90, 0xb0, 0x90, 0x58, 0xa4,
+-0x1e, 0x38, 0xe1, 0xe1, 0x76, 0xc0, 0x35, 0xd7, 0xa4, 0x1e, 0x48, 0xe1,
+-0xe1, 0x76, 0x80, 0x35, 0xe0, 0x90, 0x48, 0x80, 0xe1, 0xe1, 0x76, 0x40,
+-0x35, 0xde, 0xa4, 0x1e, 0x40, 0xe1, 0xe1, 0x76, 0x00, 0x35, 0xdc, 0x90,
+-0xb0, 0x90, 0x58, 0xa4, 0x1e, 0x08, 0xe1, 0xe1, 0x5e, 0x00, 0x35, 0x74,
+-0xa4, 0x1e, 0x18, 0xe1, 0xe1, 0x5d, 0xc0, 0x35, 0x7d, 0x90, 0x48, 0x80,
+-0xe1, 0xe1, 0x5d, 0x80, 0x35, 0x7b, 0xa4, 0x1e, 0x10, 0xe1, 0xe1, 0x5d,
+-0x40, 0x35, 0x79, 0x92, 0x40, 0x91, 0x20, 0x90, 0x90, 0x90, 0x48, 0x80,
+-0xe1, 0xe1, 0xa5, 0x80, 0x36, 0x92, 0x80, 0xe1, 0xe1, 0xa5, 0x40, 0x36,
+-0x9b, 0x90, 0x48, 0x80, 0xe1, 0xe1, 0xa5, 0x00, 0x36, 0x99, 0x80, 0xe1,
+-0xe1, 0xa4, 0xc0, 0x36, 0x97, 0x90, 0x90, 0x90, 0x48, 0x80, 0xe1, 0xe1,
+-0x8c, 0xc0, 0x36, 0x2f, 0x80, 0xe1, 0xe1, 0x8c, 0x80, 0x36, 0x38, 0x90,
+-0x48, 0x80, 0xe1, 0xe1, 0x8c, 0x40, 0x36, 0x36, 0x80, 0xe1, 0xe1, 0x8c,
+-0x00, 0x36, 0x34, 0x91, 0x50, 0x90, 0xb0, 0x90, 0x58, 0xa4, 0x1e, 0x20,
+-0xe1, 0xe1, 0x74, 0x00, 0x35, 0xcc, 0xa4, 0x1e, 0x30, 0xe1, 0xe1, 0x73,
+-0xc0, 0x35, 0xd5, 0x90, 0x48, 0x80, 0xe1, 0xe1, 0x73, 0x80, 0x35, 0xd3,
+-0xa4, 0x1e, 0x28, 0xe1, 0xe1, 0x73, 0x40, 0x35, 0xd1, 0x90, 0xb0, 0x90,
+-0x58, 0xa4, 0x1d, 0xf0, 0xe1, 0xe1, 0x5b, 0x40, 0x35, 0x69, 0xa4, 0x1e,
+-0x00, 0xe1, 0xe1, 0x5b, 0x00, 0x35, 0x72, 0x90, 0x48, 0x80, 0xe1, 0xe1,
+-0x5a, 0xc0, 0x35, 0x70, 0xa4, 0x1d, 0xf8, 0xe1, 0xe1, 0x5a, 0x80, 0x35,
+-0x6e, 0xe4, 0xe2, 0x53, 0x00, 0x39, 0x60, 0x99, 0x50, 0x02, 0x00, 0x10,
+-0x10, 0x10, 0x10, 0x90, 0x90, 0x90, 0x48, 0x80, 0xe1, 0xe1, 0x58, 0x80,
+-0x35, 0x5e, 0x80, 0xe1, 0xe1, 0x58, 0x40, 0x35, 0x67, 0x90, 0x48, 0x80,
+-0xe1, 0xe1, 0x58, 0x00, 0x35, 0x65, 0x80, 0xe1, 0xe1, 0x57, 0xc0, 0x35,
+-0x63, 0x90, 0x60, 0x90, 0x30, 0x60, 0xa0, 0xef, 0x40, 0x60, 0xa0, 0xef,
+-0x00, 0x90, 0x30, 0x60, 0xa0, 0xee, 0xc0, 0x60, 0xa0, 0xee, 0x80, 0xe4,
+-0xe2, 0x2d, 0x00, 0x38, 0xdc, 0xa0, 0x10, 0x98, 0xa0, 0x09, 0xa8, 0x9c,
+-0xc0, 0x09, 0x60, 0x92, 0x70, 0x91, 0x50, 0x90, 0xb0, 0x90, 0x58, 0xa4,
+-0x1e, 0xe0, 0xe1, 0xe1, 0xa2, 0xc0, 0x36, 0x7c, 0xa4, 0x1f, 0x00, 0xe1,
+-0xe1, 0xa2, 0x80, 0x36, 0x90, 0x90, 0x48, 0x80, 0xe1, 0xe1, 0xa2, 0x40,
+-0x36, 0x8e, 0xa4, 0x1e, 0xf0, 0xe1, 0xe1, 0xa2, 0x00, 0x36, 0x8c, 0x90,
+-0x90, 0x90, 0x48, 0x80, 0xe1, 0xe1, 0x8a, 0x00, 0x36, 0x19, 0x80, 0xe1,
+-0xe1, 0x89, 0xc0, 0x36, 0x2d, 0x90, 0x48, 0x80, 0xe1, 0xe1, 0x89, 0x80,
+-0x36, 0x2b, 0x80, 0xe1, 0xe1, 0x89, 0x40, 0x36, 0x29, 0x91, 0x20, 0x90,
+-0x90, 0x90, 0x48, 0x80, 0xe1, 0xe1, 0x71, 0x40, 0x35, 0xb6, 0x80, 0xe1,
+-0xe1, 0x71, 0x00, 0x35, 0xca, 0x90, 0x48, 0x80, 0xe1, 0xe1, 0x70, 0xc0,
+-0x35, 0xc8, 0x80, 0xe1, 0xe1, 0x70, 0x80, 0x35, 0xc6, 0x90, 0x90, 0x90,
+-0x48, 0x80, 0xe1, 0xe1, 0x55, 0xc0, 0x35, 0x48, 0x80, 0xe1, 0xe1, 0x55,
+-0x80, 0x35, 0x5c, 0x90, 0x48, 0x80, 0xe1, 0xe1, 0x55, 0x40, 0x35, 0x5a,
+-0x80, 0xe1, 0xe1, 0x55, 0x00, 0x35, 0x58, 0x92, 0x70, 0x91, 0x50, 0x90,
+-0xb0, 0x90, 0x58, 0xa4, 0x1e, 0xb0, 0xe1, 0xe1, 0x9d, 0x40, 0x36, 0x71,
+-0xa4, 0x1e, 0xd0, 0xe1, 0xe1, 0x9d, 0x00, 0x36, 0x7a, 0x90, 0x48, 0x80,
+-0xe1, 0xe1, 0x9c, 0xc0, 0x36, 0x78, 0xa4, 0x1e, 0xc0, 0xe1, 0xe1, 0x9c,
+-0x80, 0x36, 0x76, 0x90, 0x90, 0x90, 0x48, 0x80, 0xe1, 0xe1, 0x84, 0x80,
+-0x36, 0x0e, 0x80, 0xe1, 0xe1, 0x84, 0x40, 0x36, 0x17, 0x90, 0x48, 0x80,
+-0xe1, 0xe1, 0x84, 0x00, 0x36, 0x15, 0x80, 0xe1, 0xe1, 0x83, 0xc0, 0x36,
+-0x13, 0x91, 0x20, 0x90, 0x90, 0x90, 0x48, 0x80, 0xe1, 0xe1, 0x6b, 0xc0,
+-0x35, 0xab, 0x80, 0xe1, 0xe1, 0x6b, 0x80, 0x35, 0xb4, 0x90, 0x48, 0x80,
+-0xe1, 0xe1, 0x6b, 0x40, 0x35, 0xb2, 0x80, 0xe1, 0xe1, 0x6b, 0x00, 0x35,
+-0xb0, 0x90, 0x90, 0x90, 0x48, 0x80, 0xe1, 0xe1, 0x50, 0x40, 0x35, 0x3d,
+-0x80, 0xe1, 0xe1, 0x50, 0x00, 0x35, 0x46, 0x90, 0x48, 0x80, 0xe1, 0xe1,
+-0x4f, 0xc0, 0x35, 0x44, 0x80, 0xe1, 0xe1, 0x4f, 0x80, 0x35, 0x42, 0xe4,
+-0xe2, 0x52, 0x00, 0x39, 0x5c, 0x9d, 0x70, 0x06, 0xa8, 0x93, 0x20, 0x92,
+-0x00, 0x91, 0x00, 0x90, 0x80, 0x90, 0x40, 0xe1, 0xe1, 0xa0, 0x40, 0x36,
+-0x7d, 0xe1, 0xe1, 0x4b, 0x40, 0x35, 0x3b, 0x90, 0x40, 0xe1, 0xe1, 0xa0,
+-0x00, 0x36, 0x86, 0xe1, 0xe1, 0x4a, 0xc0, 0x35, 0x37, 0x90, 0x80, 0x90,
+-0x40, 0xe1, 0xe1, 0x9f, 0xc0, 0x36, 0x84, 0xe1, 0xe1, 0x4a, 0x40, 0x35,
+-0x33, 0x90, 0x40, 0xe1, 0xe1, 0x9f, 0x80, 0x36, 0x82, 0xe1, 0xe1, 0x49,
+-0xc0, 0x35, 0x2f, 0x90, 0x90, 0x90, 0x48, 0x80, 0xe1, 0xe1, 0x87, 0x80,
+-0x36, 0x1a, 0x80, 0xe1, 0xe1, 0x87, 0x40, 0x36, 0x23, 0x90, 0x48, 0x80,
+-0xe1, 0xe1, 0x87, 0x00, 0x36, 0x21, 0x80, 0xe1, 0xe1, 0x86, 0xc0, 0x36,
+-0x1f, 0x91, 0x20, 0x90, 0x90, 0x90, 0x48, 0x80, 0xe1, 0xe1, 0x6e, 0xc0,
+-0x35, 0xb7, 0x80, 0xe1, 0xe1, 0x6e, 0x80, 0x35, 0xc0, 0x90, 0x48, 0x80,
+-0xe1, 0xe1, 0x6e, 0x40, 0x35, 0xbe, 0x80, 0xe1, 0xe1, 0x6e, 0x00, 0x35,
+-0xbc, 0x90, 0x90, 0x90, 0x48, 0x80, 0xe1, 0xe1, 0x53, 0x40, 0x35, 0x49,
+-0x80, 0xe1, 0xe1, 0x53, 0x00, 0x35, 0x52, 0x90, 0x48, 0x80, 0xe1, 0xe1,
+-0x52, 0xc0, 0x35, 0x50, 0x80, 0xe1, 0xe1, 0x52, 0x80, 0x35, 0x4e, 0x81,
+-0x90, 0xa0, 0x90, 0x50, 0x10, 0x10, 0xe1, 0xe1, 0x46, 0x40, 0x35, 0x11,
+-0x10, 0x10, 0xe1, 0xe1, 0x45, 0xc0, 0x35, 0x23, 0x90, 0x50, 0x10, 0x10,
+-0xe1, 0xe1, 0x45, 0x40, 0x35, 0x1f, 0x10, 0x10, 0xe1, 0xe1, 0x44, 0xc0,
+-0x35, 0x1b, 0xe4, 0xe2, 0x2b, 0x00, 0x38, 0xd4, 0xa0, 0x0b, 0x08, 0x9d,
+-0x70, 0x0a, 0xc0, 0x93, 0x20, 0x92, 0x00, 0x91, 0x00, 0x90, 0x80, 0x90,
+-0x40, 0xe3, 0xa1, 0x26, 0x40, 0x34, 0xa0, 0xe3, 0xa1, 0x0b, 0x80, 0x34,
+-0x3c, 0x90, 0x40, 0xe3, 0xa1, 0x26, 0x00, 0x34, 0x9e, 0xe3, 0xa1, 0x0b,
+-0x00, 0x34, 0x38, 0x90, 0x80, 0x90, 0x40, 0xe3, 0xa1, 0x25, 0xc0, 0x34,
+-0x9c, 0xe3, 0xa1, 0x0a, 0x80, 0x34, 0x34, 0x90, 0x40, 0xe3, 0xa1, 0x25,
+-0x80, 0x34, 0x9a, 0xe3, 0xa1, 0x0a, 0x00, 0x34, 0x30, 0x90, 0x90, 0x90,
+-0x48, 0x80, 0xe3, 0xa1, 0x20, 0xc0, 0x34, 0x8a, 0x80, 0xe3, 0xa1, 0x20,
+-0x80, 0x34, 0x88, 0x90, 0x48, 0x80, 0xe3, 0xa1, 0x20, 0x40, 0x34, 0x86,
+-0x80, 0xe3, 0xa1, 0x20, 0x00, 0x34, 0x84, 0x91, 0x20, 0x90, 0x90, 0x90,
+-0x48, 0x80, 0xe3, 0xa1, 0x1b, 0x40, 0x34, 0x74, 0x80, 0xe3, 0xa1, 0x1b,
+-0x00, 0x34, 0x72, 0x90, 0x48, 0x80, 0xe3, 0xa1, 0x1a, 0xc0, 0x34, 0x70,
+-0x80, 0xe3, 0xa1, 0x1a, 0x80, 0x34, 0x6e, 0x90, 0x90, 0x90, 0x48, 0x80,
+-0xe3, 0xa1, 0x15, 0xc0, 0x34, 0x5e, 0x80, 0xe3, 0xa1, 0x15, 0x80, 0x34,
+-0x5c, 0x90, 0x48, 0x80, 0xe3, 0xa1, 0x15, 0x40, 0x34, 0x5a, 0x80, 0xe3,
+-0xa1, 0x15, 0x00, 0x34, 0x58, 0x93, 0x20, 0x92, 0x00, 0x91, 0x00, 0x90,
+-0x80, 0x90, 0x40, 0xe3, 0xa1, 0x23, 0xc0, 0x34, 0x8b, 0xe3, 0xa1, 0x06,
+-0x80, 0x34, 0x12, 0x90, 0x40, 0xe3, 0xa1, 0x23, 0x80, 0x34, 0x94, 0xe3,
+-0xa1, 0x06, 0x00, 0x34, 0x24, 0x90, 0x80, 0x90, 0x40, 0xe3, 0xa1, 0x23,
+-0x40, 0x34, 0x92, 0xe3, 0xa1, 0x05, 0x80, 0x34, 0x20, 0x90, 0x40, 0xe3,
+-0xa1, 0x23, 0x00, 0x34, 0x90, 0xe3, 0xa1, 0x05, 0x00, 0x34, 0x1c, 0x90,
+-0x90, 0x90, 0x48, 0x80, 0xe3, 0xa1, 0x1e, 0x40, 0x34, 0x75, 0x80, 0xe3,
+-0xa1, 0x1e, 0x00, 0x34, 0x7e, 0x90, 0x48, 0x80, 0xe3, 0xa1, 0x1d, 0xc0,
+-0x34, 0x7c, 0x80, 0xe3, 0xa1, 0x1d, 0x80, 0x34, 0x7a, 0x91, 0x20, 0x90,
+-0x90, 0x90, 0x48, 0x80, 0xe3, 0xa1, 0x18, 0xc0, 0x34, 0x5f, 0x80, 0xe3,
+-0xa1, 0x18, 0x80, 0x34, 0x68, 0x90, 0x48, 0x80, 0xe3, 0xa1, 0x18, 0x40,
+-0x34, 0x66, 0x80, 0xe3, 0xa1, 0x18, 0x00, 0x34, 0x64, 0x90, 0x90, 0x90,
+-0x48, 0x80, 0xe3, 0xa1, 0x13, 0x40, 0x34, 0x49, 0x80, 0xe3, 0xa1, 0x13,
+-0x00, 0x34, 0x52, 0x90, 0x48, 0x80, 0xe3, 0xa1, 0x12, 0xc0, 0x34, 0x50,
+-0x80, 0xe3, 0xa1, 0x12, 0x80, 0x34, 0x4e, 0xe4, 0xe2, 0x51, 0x00, 0x39,
+-0x58, 0x88, 0x01, 0x48, 0x10, 0x10, 0x10, 0x10, 0x90, 0x90, 0x90, 0x48,
+-0x80, 0xe3, 0xa1, 0x10, 0x80, 0x34, 0x3e, 0x80, 0xe3, 0xa1, 0x10, 0x40,
+-0x34, 0x47, 0x90, 0x48, 0x80, 0xe3, 0xa1, 0x10, 0x00, 0x34, 0x45, 0x80,
+-0xe3, 0xa1, 0x0f, 0xc0, 0x34, 0x43, 0xe4, 0xe2, 0x29, 0x00, 0x38, 0xcc,
+-0xa0, 0x0e, 0x80, 0xa0, 0x09, 0x08, 0x94, 0x80, 0x9a, 0x30, 0x04, 0x40,
+-0x91, 0x10, 0x90, 0x88, 0x90, 0x50, 0x90, 0x28, 0x80, 0x35, 0x0f, 0x80,
+-0x35, 0x0e, 0x10, 0x10, 0x80, 0x35, 0x0d, 0x90, 0x50, 0x90, 0x28, 0x80,
+-0x34, 0xf4, 0x80, 0x34, 0xf3, 0x10, 0x10, 0x80, 0x34, 0xf2, 0x90, 0x88,
+-0x90, 0x50, 0x90, 0x28, 0x80, 0x34, 0xd9, 0x80, 0x34, 0xd8, 0x10, 0x10,
+-0x80, 0x34, 0xd7, 0x90, 0x50, 0x90, 0x28, 0x80, 0x34, 0xbe, 0x80, 0x34,
+-0xbd, 0x10, 0x10, 0x80, 0x34, 0xbc, 0x91, 0x10, 0x90, 0x88, 0x90, 0x50,
+-0x90, 0x28, 0x80, 0x35, 0x0a, 0x80, 0x35, 0x0c, 0x10, 0x10, 0x80, 0x35,
+-0x0b, 0x90, 0x50, 0x90, 0x28, 0x80, 0x34, 0xef, 0x80, 0x34, 0xf1, 0x10,
+-0x10, 0x80, 0x34, 0xf0, 0x90, 0x88, 0x90, 0x50, 0x90, 0x28, 0x80, 0x34,
+-0xd4, 0x80, 0x34, 0xd6, 0x10, 0x10, 0x80, 0x34, 0xd5, 0x90, 0x50, 0x90,
+-0x28, 0x80, 0x34, 0xb9, 0x80, 0x34, 0xbb, 0x10, 0x10, 0x80, 0x34, 0xba,
+-0xe4, 0xe2, 0x43, 0x00, 0x39, 0x34, 0x9a, 0x30, 0x04, 0x40, 0x91, 0x10,
+-0x90, 0x88, 0x90, 0x50, 0x90, 0x28, 0x80, 0x35, 0x07, 0x80, 0x35, 0x09,
+-0x10, 0x10, 0x80, 0x35, 0x08, 0x90, 0x50, 0x90, 0x28, 0x80, 0x34, 0xec,
+-0x80, 0x34, 0xee, 0x10, 0x10, 0x80, 0x34, 0xed, 0x90, 0x88, 0x90, 0x50,
+-0x90, 0x28, 0x80, 0x34, 0xd1, 0x80, 0x34, 0xd3, 0x10, 0x10, 0x80, 0x34,
+-0xd2, 0x90, 0x50, 0x90, 0x28, 0x80, 0x34, 0xb6, 0x80, 0x34, 0xb8, 0x10,
+-0x10, 0x80, 0x34, 0xb7, 0x91, 0x10, 0x90, 0x88, 0x90, 0x50, 0x90, 0x28,
+-0x80, 0x35, 0x04, 0x80, 0x35, 0x06, 0x10, 0x10, 0x80, 0x35, 0x05, 0x90,
+-0x50, 0x90, 0x28, 0x80, 0x34, 0xe9, 0x80, 0x34, 0xeb, 0x10, 0x10, 0x80,
+-0x34, 0xea, 0x90, 0x88, 0x90, 0x50, 0x90, 0x28, 0x80, 0x34, 0xce, 0x80,
+-0x34, 0xd0, 0x10, 0x10, 0x80, 0x34, 0xcf, 0x90, 0x50, 0x90, 0x28, 0x80,
+-0x34, 0xb3, 0x80, 0x34, 0xb5, 0x10, 0x10, 0x80, 0x34, 0xb4, 0xe4, 0xe2,
+-0x22, 0x00, 0x38, 0x9c, 0x94, 0x80, 0x9a, 0x30, 0x04, 0x40, 0x91, 0x10,
+-0x90, 0x88, 0x90, 0x50, 0x90, 0x28, 0x80, 0x35, 0x01, 0x80, 0x35, 0x03,
+-0x10, 0x10, 0x80, 0x35, 0x02, 0x90, 0x50, 0x90, 0x28, 0x80, 0x34, 0xe6,
+-0x80, 0x34, 0xe8, 0x10, 0x10, 0x80, 0x34, 0xe7, 0x90, 0x88, 0x90, 0x50,
+-0x90, 0x28, 0x80, 0x34, 0xcb, 0x80, 0x34, 0xcd, 0x10, 0x10, 0x80, 0x34,
+-0xcc, 0x90, 0x50, 0x90, 0x28, 0x80, 0x34, 0xb0, 0x80, 0x34, 0xb2, 0x10,
+-0x10, 0x80, 0x34, 0xb1, 0x91, 0x10, 0x90, 0x88, 0x90, 0x50, 0x90, 0x28,
+-0x80, 0x34, 0xfe, 0x80, 0x35, 0x00, 0x10, 0x10, 0x80, 0x34, 0xff, 0x90,
+-0x50, 0x90, 0x28, 0x80, 0x34, 0xe3, 0x80, 0x34, 0xe5, 0x10, 0x10, 0x80,
+-0x34, 0xe4, 0x90, 0x88, 0x90, 0x50, 0x90, 0x28, 0x80, 0x34, 0xc8, 0x80,
+-0x34, 0xca, 0x10, 0x10, 0x80, 0x34, 0xc9, 0x90, 0x50, 0x90, 0x28, 0x80,
+-0x34, 0xad, 0x80, 0x34, 0xaf, 0x10, 0x10, 0x80, 0x34, 0xae, 0xe4, 0xe2,
+-0x41, 0x00, 0x39, 0x2c, 0x88, 0x00, 0xb0, 0x10, 0x10, 0x10, 0x10, 0x90,
+-0x50, 0x90, 0x28, 0x80, 0x34, 0xaa, 0x80, 0x34, 0xac, 0x10, 0x10, 0x80,
+-0x34, 0xab, 0xe4, 0xe2, 0x21, 0x00, 0x38, 0x98, 0x96, 0xe8, 0x94, 0x80,
+-0x9a, 0x30, 0x04, 0x40, 0x91, 0x10, 0x90, 0x88, 0x90, 0x50, 0x90, 0x28,
+-0x80, 0x34, 0xf8, 0x80, 0x34, 0xfd, 0x10, 0x10, 0x80, 0x34, 0xfc, 0x90,
+-0x50, 0x90, 0x28, 0x80, 0x34, 0xdd, 0x80, 0x34, 0xe2, 0x10, 0x10, 0x80,
+-0x34, 0xe1, 0x90, 0x88, 0x90, 0x50, 0x90, 0x28, 0x80, 0x34, 0xc2, 0x80,
+-0x34, 0xc7, 0x10, 0x10, 0x80, 0x34, 0xc6, 0x90, 0x50, 0x90, 0x28, 0x80,
+-0x34, 0xa4, 0x80, 0x34, 0xa9, 0x10, 0x10, 0x80, 0x34, 0xa8, 0x91, 0x10,
+-0x90, 0x88, 0x90, 0x50, 0x90, 0x28, 0x80, 0x34, 0xf5, 0x80, 0x34, 0xf7,
+-0x10, 0x10, 0x80, 0x34, 0xf6, 0x90, 0x50, 0x90, 0x28, 0x80, 0x34, 0xda,
+-0x80, 0x34, 0xdc, 0x10, 0x10, 0x80, 0x34, 0xdb, 0x90, 0x88, 0x90, 0x50,
+-0x90, 0x28, 0x80, 0x34, 0xbf, 0x80, 0x34, 0xc1, 0x10, 0x10, 0x80, 0x34,
+-0xc0, 0x90, 0x50, 0x90, 0x28, 0x80, 0x34, 0xa1, 0x80, 0x34, 0xa3, 0x10,
+-0x10, 0x80, 0x34, 0xa2, 0xe4, 0xe2, 0x3f, 0x00, 0x39, 0x24, 0x88, 0x02,
+-0x28, 0x91, 0x10, 0x90, 0x88, 0x90, 0x50, 0x90, 0x28, 0x80, 0x34, 0xf9,
+-0x80, 0x34, 0xfb, 0x10, 0x10, 0x80, 0x34, 0xfa, 0x90, 0x50, 0x90, 0x28,
+-0x80, 0x34, 0xde, 0x80, 0x34, 0xe0, 0x10, 0x10, 0x80, 0x34, 0xdf, 0x90,
+-0x88, 0x90, 0x50, 0x90, 0x28, 0x80, 0x34, 0xc3, 0x80, 0x34, 0xc5, 0x10,
+-0x10, 0x80, 0x34, 0xc4, 0x90, 0x50, 0x90, 0x28, 0x80, 0x34, 0xa5, 0x80,
+-0x34, 0xa7, 0x10, 0x10, 0x80, 0x34, 0xa6, 0xe4, 0xe2, 0x20, 0x00, 0x38,
+-0x94, 0x90, 0x40, 0xe5, 0x22, 0x3d, 0x00, 0x39, 0x1c, 0xe5, 0x22, 0x1f,
+-0x00, 0x38, 0x90, 0x9e, 0xb4, 0x3d, 0x08, 0x93, 0x70, 0x91, 0xd8, 0xd5,
+-0x07, 0x80, 0xd0, 0xc4, 0x40, 0x90, 0x48, 0x80, 0x8c, 0x58, 0x50, 0x84,
+-0x3b, 0x14, 0xa4, 0x56, 0x30, 0x3a, 0xde, 0x90, 0x28, 0x24, 0x55, 0x70,
+-0xa4, 0x53, 0xf0, 0x3a, 0x96, 0xd0, 0xc4, 0x40, 0x90, 0x48, 0x80, 0x8c,
+-0x58, 0x30, 0x84, 0x3b, 0x12, 0xa4, 0x56, 0x20, 0x3a, 0xdc, 0x90, 0x28,
+-0x24, 0x55, 0x60, 0xa4, 0x53, 0xe0, 0x3a, 0x94, 0xd5, 0x06, 0x80, 0xd0,
+-0xc3, 0x40, 0x90, 0x28, 0x80, 0x3a, 0xfe, 0xa4, 0x56, 0x00, 0x3a, 0xd8,
+-0x90, 0x28, 0x24, 0x55, 0x40, 0xa4, 0x53, 0xc0, 0x3a, 0x90, 0xd0, 0xc3,
+-0x40, 0x90, 0x28, 0x80, 0x3a, 0xfa, 0xa4, 0x55, 0xf0, 0x3a, 0xd6, 0x90,
+-0x28, 0x24, 0x55, 0x30, 0xa4, 0x53, 0xb0, 0x3a, 0x8e, 0x91, 0x98, 0xd5,
+-0x06, 0x80, 0xd0, 0xc3, 0x40, 0x90, 0x28, 0x80, 0x3a, 0xf2, 0xa4, 0x55,
+-0xd0, 0x3a, 0xd2, 0x90, 0x28, 0x24, 0x55, 0x10, 0xa4, 0x53, 0x90, 0x3a,
+-0x8a, 0xd0, 0xc3, 0x40, 0x90, 0x28, 0x80, 0x3a, 0xee, 0xa4, 0x55, 0xc0,
+-0x3a, 0xd0, 0x90, 0x28, 0x24, 0x55, 0x00, 0xa4, 0x53, 0x80, 0x3a, 0x88,
+-0xd5, 0x06, 0x80, 0xd0, 0xc3, 0x40, 0x90, 0x28, 0x80, 0x3a, 0xe6, 0xa4,
+-0x55, 0xa0, 0x3a, 0xcc, 0x90, 0x28, 0x24, 0x54, 0xe0, 0xa4, 0x53, 0x60,
+-0x3a, 0x84, 0xd0, 0xc3, 0x40, 0x90, 0x28, 0x80, 0x3a, 0xe2, 0xa4, 0x55,
+-0x90, 0x3a, 0xca, 0x90, 0x28, 0x24, 0x54, 0xd0, 0xa4, 0x53, 0x50, 0x3a,
+-0x82, 0x93, 0x70, 0x91, 0xd8, 0xd5, 0x07, 0x80, 0xd0, 0xc4, 0x40, 0x90,
+-0x48, 0x80, 0x8c, 0x58, 0x70, 0x84, 0x3b, 0x16, 0xa4, 0x56, 0x40, 0x3a,
+-0xe0, 0x90, 0x28, 0x24, 0x55, 0x80, 0xa4, 0x54, 0x00, 0x3a, 0x98, 0xd0,
+-0xc4, 0x40, 0x90, 0x48, 0x80, 0x8c, 0x58, 0x40, 0x84, 0x3b, 0x13, 0xa4,
+-0x56, 0x28, 0x3a, 0xdd, 0x90, 0x28, 0x24, 0x55, 0x68, 0xa4, 0x53, 0xe8,
+-0x3a, 0x95, 0xd5, 0x06, 0x80, 0xd0, 0xc3, 0x40, 0x90, 0x28, 0x80, 0x3b,
+-0x02, 0xa4, 0x56, 0x10, 0x3a, 0xda, 0x90, 0x28, 0x24, 0x55, 0x50, 0xa4,
+-0x53, 0xd0, 0x3a, 0x92, 0xd0, 0xc3, 0x40, 0x90, 0x28, 0x80, 0x3a, 0xfc,
+-0xa4, 0x55, 0xf8, 0x3a, 0xd7, 0x90, 0x28, 0x24, 0x55, 0x38, 0xa4, 0x53,
+-0xb8, 0x3a, 0x8f, 0x91, 0x98, 0xd5, 0x06, 0x80, 0xd0, 0xc3, 0x40, 0x90,
+-0x28, 0x80, 0x3a, 0xf6, 0xa4, 0x55, 0xe0, 0x3a, 0xd4, 0x90, 0x28, 0x24,
+-0x55, 0x20, 0xa4, 0x53, 0xa0, 0x3a, 0x8c, 0xd0, 0xc3, 0x40, 0x90, 0x28,
+-0x80, 0x3a, 0xf0, 0xa4, 0x55, 0xc8, 0x3a, 0xd1, 0x90, 0x28, 0x24, 0x55,
+-0x08, 0xa4, 0x53, 0x88, 0x3a, 0x89, 0xd5, 0x06, 0x80, 0xd0, 0xc3, 0x40,
+-0x90, 0x28, 0x80, 0x3a, 0xea, 0xa4, 0x55, 0xb0, 0x3a, 0xce, 0x90, 0x28,
+-0x24, 0x54, 0xf0, 0xa4, 0x53, 0x70, 0x3a, 0x86, 0xd0, 0xc3, 0x40, 0x90,
+-0x28, 0x80, 0x3a, 0xe4, 0xa4, 0x55, 0x98, 0x3a, 0xcb, 0x90, 0x28, 0x24,
+-0x54, 0xd8, 0xa4, 0x53, 0x58, 0x3a, 0x83, 0x99, 0xd8, 0x03, 0x90, 0x81,
+-0x90, 0xe0, 0x5b, 0x41, 0x40, 0x03, 0x40, 0x51, 0x40, 0xc0, 0xa4, 0x3c,
+-0xa0, 0x37, 0x84, 0xd1, 0x42, 0x00, 0xa4, 0x3b, 0xa0, 0x37, 0x64, 0xa4,
+-0x3a, 0xa0, 0x37, 0x44, 0x5b, 0x41, 0x40, 0x03, 0x40, 0x51, 0x40, 0xc0,
+-0xa4, 0x3b, 0xc0, 0x37, 0x88, 0xd1, 0x42, 0x00, 0xa4, 0x3a, 0xc0, 0x37,
+-0x68, 0xa4, 0x39, 0xc0, 0x37, 0x48, 0x81, 0x90, 0xe0, 0x5b, 0x41, 0x40,
+-0x03, 0x40, 0x51, 0x40, 0xc0, 0xa4, 0x3c, 0x00, 0x37, 0x90, 0xd1, 0x42,
+-0x00, 0xa4, 0x3b, 0x00, 0x37, 0x70, 0xa4, 0x3a, 0x00, 0x37, 0x50, 0x5b,
+-0x41, 0x40, 0x03, 0x40, 0x51, 0x40, 0xc0, 0xa4, 0x3b, 0xe0, 0x37, 0x8c,
+-0xd1, 0x42, 0x00, 0xa4, 0x3a, 0xe0, 0x37, 0x6c, 0xa4, 0x39, 0xe0, 0x37,
+-0x4c, 0xa8, 0x0b, 0x18, 0x13, 0xa8, 0x96, 0x80, 0x93, 0x40, 0x99, 0x90,
+-0x03, 0x00, 0x90, 0xc0, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x1d, 0xc0, 0x33,
+-0xb9, 0x24, 0x1d, 0xb8, 0x90, 0x38, 0xa4, 0x1c, 0xe8, 0x33, 0x9e, 0x24,
+-0x1c, 0xe0, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x1c, 0x10, 0x33, 0x83, 0x24,
+-0x1c, 0x08, 0x90, 0x38, 0xa4, 0x1b, 0x38, 0x33, 0x68, 0x24, 0x1b, 0x30,
+-0x90, 0xc0, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x1d, 0xb0, 0x33, 0xb4, 0x24,
+-0x1d, 0xa8, 0x90, 0x38, 0xa4, 0x1c, 0xd8, 0x33, 0x99, 0x24, 0x1c, 0xd0,
+-0x90, 0x60, 0x90, 0x38, 0xa4, 0x1c, 0x00, 0x33, 0x7e, 0x24, 0x1b, 0xf8,
+-0x90, 0x38, 0xa4, 0x1b, 0x28, 0x33, 0x63, 0x24, 0x1b, 0x20, 0xe4, 0xe2,
+-0x99, 0x00, 0x3a, 0x66, 0x99, 0x90, 0x03, 0x00, 0x90, 0xc0, 0x90, 0x60,
+-0x90, 0x38, 0xa4, 0x1d, 0x98, 0x33, 0xb1, 0x24, 0x1d, 0x90, 0x90, 0x38,
+-0xa4, 0x1c, 0xc0, 0x33, 0x96, 0x24, 0x1c, 0xb8, 0x90, 0x60, 0x90, 0x38,
+-0xa4, 0x1b, 0xe8, 0x33, 0x7b, 0x24, 0x1b, 0xe0, 0x90, 0x38, 0xa4, 0x1b,
+-0x10, 0x33, 0x60, 0x24, 0x1b, 0x08, 0x90, 0xc0, 0x90, 0x60, 0x90, 0x38,
+-0xa4, 0x1d, 0x80, 0x33, 0xae, 0x24, 0x1d, 0x78, 0x90, 0x38, 0xa4, 0x1c,
+-0xa8, 0x33, 0x93, 0x24, 0x1c, 0xa0, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x1b,
+-0xd0, 0x33, 0x78, 0x24, 0x1b, 0xc8, 0x90, 0x38, 0xa4, 0x1a, 0xf8, 0x33,
+-0x5d, 0x24, 0x1a, 0xf0, 0xe4, 0xe2, 0x97, 0x80, 0x3a, 0x60, 0x93, 0x78,
+-0x99, 0x90, 0x03, 0x00, 0x90, 0xc0, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x1d,
+-0x68, 0x33, 0xab, 0x24, 0x1d, 0x60, 0x90, 0x38, 0xa4, 0x1c, 0x90, 0x33,
+-0x90, 0x24, 0x1c, 0x88, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x1b, 0xb8, 0x33,
+-0x75, 0x24, 0x1b, 0xb0, 0x90, 0x38, 0xa4, 0x1a, 0xe0, 0x33, 0x5a, 0x24,
+-0x1a, 0xd8, 0x90, 0xc0, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x1d, 0x50, 0x33,
+-0xa8, 0x24, 0x1d, 0x48, 0x90, 0x38, 0xa4, 0x1c, 0x78, 0x33, 0x8d, 0x24,
+-0x1c, 0x70, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x1b, 0xa0, 0x33, 0x72, 0x24,
+-0x1b, 0x98, 0x90, 0x38, 0xa4, 0x1a, 0xc8, 0x33, 0x57, 0x24, 0x1a, 0xc0,
+-0xec, 0xa1, 0xe7, 0x00, 0x02, 0x00, 0x37, 0x9e, 0xa4, 0x52, 0xc0, 0x3a,
+-0x5a, 0x88, 0x00, 0x88, 0x10, 0x10, 0x10, 0x10, 0x90, 0x38, 0xa4, 0x1a,
+-0xb0, 0x33, 0x54, 0x24, 0x1a, 0xa8, 0xe9, 0x61, 0xe6, 0x40, 0x02, 0x00,
+-0x37, 0x9a, 0xe3, 0x62, 0x94, 0x80, 0x3a, 0x54, 0x95, 0x08, 0x93, 0x40,
+-0x99, 0x90, 0x03, 0x00, 0x90, 0xc0, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x1d,
+-0x38, 0x33, 0xa2, 0x24, 0x1d, 0x30, 0x90, 0x38, 0xa4, 0x1c, 0x60, 0x33,
+-0x87, 0x24, 0x1c, 0x58, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x1b, 0x88, 0x33,
+-0x6c, 0x24, 0x1b, 0x80, 0x90, 0x38, 0xa4, 0x1a, 0x98, 0x33, 0x4e, 0x24,
+-0x1a, 0x90, 0x90, 0xc0, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x1d, 0x08, 0x33,
+-0x9f, 0x24, 0x1d, 0x00, 0x90, 0x38, 0xa4, 0x1c, 0x30, 0x33, 0x84, 0x24,
+-0x1c, 0x28, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x1b, 0x58, 0x33, 0x69, 0x24,
+-0x1b, 0x50, 0x90, 0x38, 0xa4, 0x1a, 0x68, 0x33, 0x4b, 0x24, 0x1a, 0x60,
+-0xe4, 0xe2, 0x99, 0x40, 0x3a, 0x68, 0x88, 0x01, 0x88, 0x90, 0xc0, 0x90,
+-0x60, 0x90, 0x38, 0xa4, 0x1d, 0x28, 0x33, 0xa3, 0x24, 0x1d, 0x20, 0x90,
+-0x38, 0xa4, 0x1c, 0x50, 0x33, 0x88, 0x24, 0x1c, 0x48, 0x90, 0x60, 0x90,
+-0x38, 0xa4, 0x1b, 0x78, 0x33, 0x6d, 0x24, 0x1b, 0x70, 0x90, 0x38, 0xa4,
+-0x1a, 0x88, 0x33, 0x4f, 0x24, 0x1a, 0x80, 0xe4, 0xe2, 0x97, 0xc0, 0x3a,
+-0x62, 0x92, 0xd0, 0x99, 0x50, 0x02, 0x80, 0x90, 0xa0, 0x90, 0x50, 0x90,
+-0x28, 0x80, 0x33, 0x4a, 0x24, 0x1a, 0x48, 0x90, 0x28, 0x80, 0x33, 0x46,
+-0x24, 0x1a, 0x28, 0x90, 0x50, 0x90, 0x28, 0x80, 0x33, 0x42, 0x24, 0x1a,
+-0x08, 0x90, 0x28, 0x80, 0x33, 0x3e, 0x24, 0x19, 0xe8, 0x90, 0xa0, 0x90,
+-0x50, 0x90, 0x28, 0x80, 0x33, 0x47, 0x24, 0x1a, 0x40, 0x90, 0x28, 0x80,
+-0x33, 0x43, 0x24, 0x1a, 0x20, 0x90, 0x50, 0x90, 0x28, 0x80, 0x33, 0x3f,
+-0x24, 0x1a, 0x00, 0x90, 0x28, 0x80, 0x33, 0x3b, 0x24, 0x19, 0xe0, 0xec,
+-0xe2, 0x96, 0x61, 0xe8, 0x00, 0x3a, 0x5c, 0x88, 0x00, 0x78, 0x10, 0x10,
+-0x10, 0x10, 0x90, 0x28, 0x80, 0x33, 0x39, 0x24, 0x19, 0xd0, 0xec, 0xe2,
+-0x94, 0xe1, 0xe6, 0x00, 0x3a, 0x56, 0xe5, 0xa2, 0x1e, 0x00, 0x38, 0x74,
+-0xa0, 0x41, 0xe0, 0xa8, 0x2c, 0x30, 0x41, 0xa8, 0xa0, 0x16, 0x68, 0xa0,
+-0x14, 0x50, 0xa0, 0x0a, 0x28, 0x95, 0x10, 0x92, 0x70, 0x91, 0x20, 0x90,
+-0x90, 0x90, 0x48, 0x80, 0xe1, 0xe0, 0x9a, 0xc0, 0x32, 0x72, 0x80, 0xe1,
+-0xe0, 0x9a, 0x80, 0x32, 0x70, 0x90, 0x48, 0x80, 0xe1, 0xe0, 0x9a, 0x40,
+-0x32, 0x6e, 0x80, 0xe1, 0xe0, 0x9a, 0x00, 0x32, 0x6c, 0x90, 0xb0, 0x90,
+-0x58, 0xa4, 0x0b, 0xf8, 0xe1, 0xe0, 0xab, 0x40, 0x32, 0xb4, 0xa4, 0x0b,
+-0xf0, 0xe1, 0xe0, 0xab, 0x00, 0x32, 0xb2, 0x90, 0x48, 0x80, 0xe1, 0xe0,
+-0xaa, 0xc0, 0x32, 0xb0, 0xa4, 0x0b, 0xe8, 0xe1, 0xe0, 0xaa, 0x80, 0x32,
+-0xae, 0x91, 0x50, 0x90, 0xb0, 0x90, 0x58, 0xa4, 0x0d, 0x18, 0xe1, 0xe0,
+-0xcc, 0x40, 0x33, 0x38, 0xa4, 0x0d, 0x10, 0xe1, 0xe0, 0xcc, 0x00, 0x33,
+-0x36, 0x90, 0x48, 0x80, 0xe1, 0xe0, 0xcb, 0xc0, 0x33, 0x34, 0xa4, 0x0d,
+-0x08, 0xe1, 0xe0, 0xcb, 0x80, 0x33, 0x32, 0x90, 0xb0, 0x90, 0x58, 0xa4,
+-0x0c, 0x88, 0xe1, 0xe0, 0xbb, 0xc0, 0x32, 0xf6, 0xa4, 0x0c, 0x80, 0xe1,
+-0xe0, 0xbb, 0x80, 0x32, 0xf4, 0x90, 0x48, 0x80, 0xe1, 0xe0, 0xbb, 0x40,
+-0x32, 0xf2, 0xa4, 0x0c, 0x78, 0xe1, 0xe0, 0xbb, 0x00, 0x32, 0xf0, 0x92,
+-0x70, 0x91, 0x20, 0x90, 0x90, 0x90, 0x48, 0x80, 0xe1, 0xe0, 0x98, 0x40,
+-0x32, 0x5d, 0x80, 0xe1, 0xe0, 0x98, 0x00, 0x32, 0x66, 0x90, 0x48, 0x80,
+-0xe1, 0xe0, 0x97, 0xc0, 0x32, 0x64, 0x80, 0xe1, 0xe0, 0x97, 0x80, 0x32,
+-0x62, 0x90, 0xb0, 0x90, 0x58, 0xa4, 0x0b, 0xd0, 0xe1, 0xe0, 0xa8, 0xc0,
+-0x32, 0x9f, 0xa4, 0x0b, 0xe0, 0xe1, 0xe0, 0xa8, 0x80, 0x32, 0xa8, 0x90,
+-0x48, 0x80, 0xe1, 0xe0, 0xa8, 0x40, 0x32, 0xa6, 0xa4, 0x0b, 0xd8, 0xe1,
+-0xe0, 0xa8, 0x00, 0x32, 0xa4, 0x91, 0x50, 0x90, 0xb0, 0x90, 0x58, 0xa4,
+-0x0c, 0xf0, 0xe1, 0xe0, 0xc9, 0xc0, 0x33, 0x23, 0xa4, 0x0d, 0x00, 0xe1,
+-0xe0, 0xc9, 0x80, 0x33, 0x2c, 0x90, 0x48, 0x80, 0xe1, 0xe0, 0xc9, 0x40,
+-0x33, 0x2a, 0xa4, 0x0c, 0xf8, 0xe1, 0xe0, 0xc9, 0x00, 0x33, 0x28, 0x90,
+-0xb0, 0x90, 0x58, 0xa4, 0x0c, 0x60, 0xe1, 0xe0, 0xb9, 0x40, 0x32, 0xe1,
+-0xa4, 0x0c, 0x70, 0xe1, 0xe0, 0xb9, 0x00, 0x32, 0xea, 0x90, 0x48, 0x80,
+-0xe1, 0xe0, 0xb8, 0xc0, 0x32, 0xe8, 0xa4, 0x0c, 0x68, 0xe1, 0xe0, 0xb8,
+-0x80, 0x32, 0xe6, 0x95, 0x10, 0x92, 0x70, 0x91, 0x20, 0x90, 0x90, 0x90,
+-0x48, 0x80, 0xe1, 0xe0, 0x95, 0x80, 0x32, 0x52, 0x80, 0xe1, 0xe0, 0x95,
+-0x40, 0x32, 0x5b, 0x90, 0x48, 0x80, 0xe1, 0xe0, 0x95, 0x00, 0x32, 0x59,
+-0x80, 0xe1, 0xe0, 0x94, 0xc0, 0x32, 0x57, 0x90, 0xb0, 0x90, 0x58, 0xa4,
+-0x0b, 0xb8, 0xe1, 0xe0, 0xa6, 0x00, 0x32, 0x94, 0xa4, 0x0b, 0xc8, 0xe1,
+-0xe0, 0xa5, 0xc0, 0x32, 0x9d, 0x90, 0x48, 0x80, 0xe1, 0xe0, 0xa5, 0x80,
+-0x32, 0x9b, 0xa4, 0x0b, 0xc0, 0xe1, 0xe0, 0xa5, 0x40, 0x32, 0x99, 0x91,
+-0x50, 0x90, 0xb0, 0x90, 0x58, 0xa4, 0x0c, 0xd8, 0xe1, 0xe0, 0xc7, 0x00,
+-0x33, 0x18, 0xa4, 0x0c, 0xe8, 0xe1, 0xe0, 0xc6, 0xc0, 0x33, 0x21, 0x90,
+-0x48, 0x80, 0xe1, 0xe0, 0xc6, 0x80, 0x33, 0x1f, 0xa4, 0x0c, 0xe0, 0xe1,
+-0xe0, 0xc6, 0x40, 0x33, 0x1d, 0x90, 0xb0, 0x90, 0x58, 0xa4, 0x0c, 0x48,
+-0xe1, 0xe0, 0xb6, 0x80, 0x32, 0xd6, 0xa4, 0x0c, 0x58, 0xe1, 0xe0, 0xb6,
+-0x40, 0x32, 0xdf, 0x90, 0x48, 0x80, 0xe1, 0xe0, 0xb6, 0x00, 0x32, 0xdd,
+-0xa4, 0x0c, 0x50, 0xe1, 0xe0, 0xb5, 0xc0, 0x32, 0xdb, 0x92, 0x70, 0x91,
+-0x20, 0x90, 0x90, 0x90, 0x48, 0x80, 0xe1, 0xe0, 0x92, 0xc0, 0x32, 0x47,
+-0x80, 0xe1, 0xe0, 0x92, 0x80, 0x32, 0x50, 0x90, 0x48, 0x80, 0xe1, 0xe0,
+-0x92, 0x40, 0x32, 0x4e, 0x80, 0xe1, 0xe0, 0x92, 0x00, 0x32, 0x4c, 0x90,
+-0xb0, 0x90, 0x58, 0xa4, 0x0b, 0xa0, 0xe1, 0xe0, 0xa3, 0x40, 0x32, 0x89,
+-0xa4, 0x0b, 0xb0, 0xe1, 0xe0, 0xa3, 0x00, 0x32, 0x92, 0x90, 0x48, 0x80,
+-0xe1, 0xe0, 0xa2, 0xc0, 0x32, 0x90, 0xa4, 0x0b, 0xa8, 0xe1, 0xe0, 0xa2,
+-0x80, 0x32, 0x8e, 0x91, 0x50, 0x90, 0xb0, 0x90, 0x58, 0xa4, 0x0c, 0xc0,
+-0xe1, 0xe0, 0xc4, 0x40, 0x33, 0x0d, 0xa4, 0x0c, 0xd0, 0xe1, 0xe0, 0xc4,
+-0x00, 0x33, 0x16, 0x90, 0x48, 0x80, 0xe1, 0xe0, 0xc3, 0xc0, 0x33, 0x14,
+-0xa4, 0x0c, 0xc8, 0xe1, 0xe0, 0xc3, 0x80, 0x33, 0x12, 0x90, 0xb0, 0x90,
+-0x58, 0xa4, 0x0c, 0x30, 0xe1, 0xe0, 0xb3, 0xc0, 0x32, 0xcb, 0xa4, 0x0c,
+-0x40, 0xe1, 0xe0, 0xb3, 0x80, 0x32, 0xd4, 0x90, 0x48, 0x80, 0xe1, 0xe0,
+-0xb3, 0x40, 0x32, 0xd2, 0xa4, 0x0c, 0x38, 0xe1, 0xe0, 0xb3, 0x00, 0x32,
+-0xd0, 0x10, 0x10, 0x91, 0x40, 0x10, 0x10, 0x10, 0x10, 0x90, 0x90, 0x90,
+-0x48, 0x80, 0xe1, 0xe0, 0x8a, 0x80, 0x32, 0x26, 0x80, 0xe1, 0xe0, 0x8a,
+-0x40, 0x32, 0x2f, 0x90, 0x48, 0x80, 0xe1, 0xe0, 0x8a, 0x00, 0x32, 0x2d,
+-0x80, 0xe1, 0xe0, 0x89, 0xc0, 0x32, 0x2b, 0x90, 0x60, 0x90, 0x30, 0x60,
+-0xa0, 0x32, 0xc0, 0x60, 0xa0, 0x32, 0x80, 0x90, 0x30, 0x60, 0xa0, 0x32,
+-0x40, 0x60, 0xa0, 0x32, 0x00, 0xa0, 0x0f, 0xe0, 0xa0, 0x0a, 0x28, 0x95,
+-0x10, 0x92, 0x70, 0x91, 0x20, 0x90, 0x90, 0x90, 0x48, 0x80, 0xe1, 0xe0,
+-0x90, 0x00, 0x32, 0x3c, 0x80, 0xe1, 0xe0, 0x8f, 0xc0, 0x32, 0x45, 0x90,
+-0x48, 0x80, 0xe1, 0xe0, 0x8f, 0x80, 0x32, 0x43, 0x80, 0xe1, 0xe0, 0x8f,
+-0x40, 0x32, 0x41, 0x90, 0xb0, 0x90, 0x58, 0xa4, 0x0b, 0x88, 0xe1, 0xe0,
+-0xa0, 0x80, 0x32, 0x7e, 0xa4, 0x0b, 0x98, 0xe1, 0xe0, 0xa0, 0x40, 0x32,
+-0x87, 0x90, 0x48, 0x80, 0xe1, 0xe0, 0xa0, 0x00, 0x32, 0x85, 0xa4, 0x0b,
+-0x90, 0xe1, 0xe0, 0x9f, 0xc0, 0x32, 0x83, 0x91, 0x50, 0x90, 0xb0, 0x90,
+-0x58, 0xa4, 0x0c, 0xa8, 0xe1, 0xe0, 0xc1, 0x80, 0x33, 0x02, 0xa4, 0x0c,
+-0xb8, 0xe1, 0xe0, 0xc1, 0x40, 0x33, 0x0b, 0x90, 0x48, 0x80, 0xe1, 0xe0,
+-0xc1, 0x00, 0x33, 0x09, 0xa4, 0x0c, 0xb0, 0xe1, 0xe0, 0xc0, 0xc0, 0x33,
+-0x07, 0x90, 0xb0, 0x90, 0x58, 0xa4, 0x0c, 0x18, 0xe1, 0xe0, 0xb1, 0x00,
+-0x32, 0xc0, 0xa4, 0x0c, 0x28, 0xe1, 0xe0, 0xb0, 0xc0, 0x32, 0xc9, 0x90,
+-0x48, 0x80, 0xe1, 0xe0, 0xb0, 0x80, 0x32, 0xc7, 0xa4, 0x0c, 0x20, 0xe1,
+-0xe0, 0xb0, 0x40, 0x32, 0xc5, 0x92, 0x70, 0x91, 0x20, 0x90, 0x90, 0x90,
+-0x48, 0x80, 0xe1, 0xe0, 0x8d, 0x40, 0x32, 0x31, 0x80, 0xe1, 0xe0, 0x8d,
+-0x00, 0x32, 0x3a, 0x90, 0x48, 0x80, 0xe1, 0xe0, 0x8c, 0xc0, 0x32, 0x38,
+-0x80, 0xe1, 0xe0, 0x8c, 0x80, 0x32, 0x36, 0x90, 0xb0, 0x90, 0x58, 0xa4,
+-0x0b, 0x70, 0xe1, 0xe0, 0x9d, 0xc0, 0x32, 0x73, 0xa4, 0x0b, 0x80, 0xe1,
+-0xe0, 0x9d, 0x80, 0x32, 0x7c, 0x90, 0x48, 0x80, 0xe1, 0xe0, 0x9d, 0x40,
+-0x32, 0x7a, 0xa4, 0x0b, 0x78, 0xe1, 0xe0, 0x9d, 0x00, 0x32, 0x78, 0x91,
+-0x50, 0x90, 0xb0, 0x90, 0x58, 0xa4, 0x0c, 0x90, 0xe1, 0xe0, 0xbe, 0xc0,
+-0x32, 0xf7, 0xa4, 0x0c, 0xa0, 0xe1, 0xe0, 0xbe, 0x80, 0x33, 0x00, 0x90,
+-0x48, 0x80, 0xe1, 0xe0, 0xbe, 0x40, 0x32, 0xfe, 0xa4, 0x0c, 0x98, 0xe1,
+-0xe0, 0xbe, 0x00, 0x32, 0xfc, 0x90, 0xb0, 0x90, 0x58, 0xa4, 0x0c, 0x00,
+-0xe1, 0xe0, 0xae, 0x40, 0x32, 0xb5, 0xa4, 0x0c, 0x10, 0xe1, 0xe0, 0xae,
+-0x00, 0x32, 0xbe, 0x90, 0x48, 0x80, 0xe1, 0xe0, 0xad, 0xc0, 0x32, 0xbc,
+-0xa4, 0x0c, 0x08, 0xe1, 0xe0, 0xad, 0x80, 0x32, 0xba, 0x10, 0x10, 0x93,
+-0x60, 0x92, 0x40, 0x91, 0x20, 0x90, 0x90, 0x80, 0xd1, 0xc2, 0x40, 0xe1,
+-0xa0, 0x4b, 0xc0, 0x31, 0x36, 0xe1, 0xa0, 0x40, 0x40, 0x30, 0xfc, 0x80,
+-0xd1, 0xc2, 0x40, 0xe1, 0xa0, 0x4b, 0x80, 0x31, 0x34, 0xe1, 0xa0, 0x40,
+-0x00, 0x31, 0x06, 0x90, 0x90, 0x80, 0xd1, 0xc2, 0x40, 0xe1, 0xa0, 0x4b,
+-0x40, 0x31, 0x32, 0xe1, 0xa0, 0x3f, 0xc0, 0x31, 0x04, 0x80, 0xd1, 0xc2,
+-0x40, 0xe1, 0xa0, 0x4b, 0x00, 0x31, 0x30, 0xe1, 0xa0, 0x3f, 0x80, 0x31,
+-0x02, 0x90, 0x90, 0x90, 0x48, 0x80, 0xe3, 0xa0, 0x49, 0x40, 0x31, 0x20,
+-0x80, 0xe3, 0xa0, 0x49, 0x00, 0x31, 0x2a, 0x90, 0x48, 0x80, 0xe3, 0xa0,
+-0x48, 0xc0, 0x31, 0x28, 0x80, 0xe3, 0xa0, 0x48, 0x80, 0x31, 0x26, 0x91,
+-0x20, 0x90, 0x90, 0x90, 0x48, 0x80, 0xe3, 0xa0, 0x46, 0x40, 0x31, 0x08,
+-0x80, 0xe3, 0xa0, 0x46, 0x00, 0x31, 0x1e, 0x90, 0x48, 0x80, 0xe3, 0xa0,
+-0x45, 0xc0, 0x31, 0x1c, 0x80, 0xe3, 0xa0, 0x45, 0x80, 0x31, 0x1a, 0x90,
+-0x90, 0x90, 0x48, 0x80, 0xe3, 0xa0, 0x43, 0xc0, 0x31, 0x0a, 0x80, 0xe3,
+-0xa0, 0x43, 0x80, 0x31, 0x14, 0x90, 0x48, 0x80, 0xe3, 0xa0, 0x43, 0x40,
+-0x31, 0x12, 0x80, 0xe3, 0xa0, 0x43, 0x00, 0x31, 0x10, 0x94, 0x88, 0x80,
+-0x92, 0x40, 0x91, 0x20, 0x90, 0x90, 0x90, 0x48, 0x80, 0xe3, 0xa0, 0x6c,
+-0x80, 0x31, 0xb9, 0x80, 0xe3, 0xa0, 0x6c, 0x40, 0x31, 0xb7, 0x90, 0x48,
+-0x80, 0xe3, 0xa0, 0x6c, 0x00, 0x31, 0xb5, 0x80, 0xe3, 0xa0, 0x6b, 0xc0,
+-0x31, 0xb3, 0x90, 0x90, 0x90, 0x48, 0x80, 0xe3, 0xa0, 0x6f, 0x40, 0x31,
+-0xc4, 0x80, 0xe3, 0xa0, 0x6f, 0x00, 0x31, 0xc2, 0x90, 0x48, 0x80, 0xe3,
+-0xa0, 0x6e, 0xc0, 0x31, 0xc0, 0x80, 0xe3, 0xa0, 0x6e, 0x80, 0x31, 0xbe,
+-0x91, 0x20, 0x90, 0x90, 0x90, 0x48, 0x80, 0xe3, 0xa0, 0x74, 0xc0, 0x31,
+-0xda, 0x80, 0xe3, 0xa0, 0x74, 0x80, 0x31, 0xd8, 0x90, 0x48, 0x80, 0xe3,
+-0xa0, 0x74, 0x40, 0x31, 0xd6, 0x80, 0xe3, 0xa0, 0x74, 0x00, 0x31, 0xd4,
+-0x90, 0x90, 0x90, 0x48, 0x80, 0xe3, 0xa0, 0x72, 0x00, 0x31, 0xcf, 0x80,
+-0xe3, 0xa0, 0x71, 0xc0, 0x31, 0xcd, 0x90, 0x48, 0x80, 0xe3, 0xa0, 0x71,
+-0x80, 0x31, 0xcb, 0x80, 0xe3, 0xa0, 0x71, 0x40, 0x31, 0xc9, 0x80, 0x10,
+-0x10, 0x10, 0x10, 0x90, 0x90, 0x90, 0x48, 0x80, 0xe3, 0xa0, 0x6a, 0x00,
+-0x31, 0xa4, 0x80, 0xe3, 0xa0, 0x69, 0xc0, 0x31, 0xad, 0x90, 0x48, 0x80,
+-0xe3, 0xa0, 0x69, 0x80, 0x31, 0xab, 0x80, 0xe3, 0xa0, 0x69, 0x40, 0x31,
+-0xa9, 0xa0, 0x0b, 0x90, 0xa0, 0x0a, 0xc8, 0x95, 0x60, 0x92, 0xb0, 0x91,
+-0x40, 0x90, 0x88, 0x90, 0x50, 0x90, 0x28, 0x80, 0x31, 0xef, 0x80, 0x31,
+-0xee, 0x10, 0x10, 0x80, 0x31, 0xed, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x0a,
+-0x48, 0x32, 0x01, 0xa4, 0x0a, 0x40, 0x32, 0x00, 0x10, 0x10, 0xa4, 0x0a,
+-0x38, 0x31, 0xff, 0x90, 0xb8, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x0b, 0x68,
+-0x32, 0x25, 0xa4, 0x0b, 0x60, 0x32, 0x24, 0x10, 0x10, 0xa4, 0x0b, 0x58,
+-0x32, 0x23, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x0a, 0xd8, 0x32, 0x13, 0xa4,
+-0x0a, 0xd0, 0x32, 0x12, 0x10, 0x10, 0xa4, 0x0a, 0xc8, 0x32, 0x11, 0x91,
+-0x40, 0x90, 0x88, 0x90, 0x50, 0x90, 0x28, 0x80, 0x31, 0xea, 0x80, 0x31,
+-0xec, 0x10, 0x10, 0x80, 0x31, 0xeb, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x0a,
+-0x20, 0x31, 0xfc, 0xa4, 0x0a, 0x30, 0x31, 0xfe, 0x10, 0x10, 0xa4, 0x0a,
+-0x28, 0x31, 0xfd, 0x90, 0xb8, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x0b, 0x40,
+-0x32, 0x20, 0xa4, 0x0b, 0x50, 0x32, 0x22, 0x10, 0x10, 0xa4, 0x0b, 0x48,
+-0x32, 0x21, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x0a, 0xb0, 0x32, 0x0e, 0xa4,
+-0x0a, 0xc0, 0x32, 0x10, 0x10, 0x10, 0xa4, 0x0a, 0xb8, 0x32, 0x0f, 0x92,
+-0xb0, 0x91, 0x40, 0x90, 0x88, 0x90, 0x50, 0x90, 0x28, 0x80, 0x31, 0xe7,
+-0x80, 0x31, 0xe9, 0x10, 0x10, 0x80, 0x31, 0xe8, 0x90, 0x70, 0x90, 0x38,
+-0xa4, 0x0a, 0x08, 0x31, 0xf9, 0xa4, 0x0a, 0x18, 0x31, 0xfb, 0x10, 0x10,
+-0xa4, 0x0a, 0x10, 0x31, 0xfa, 0x90, 0xb8, 0x90, 0x70, 0x90, 0x38, 0xa4,
+-0x0b, 0x28, 0x32, 0x1d, 0xa4, 0x0b, 0x38, 0x32, 0x1f, 0x10, 0x10, 0xa4,
+-0x0b, 0x30, 0x32, 0x1e, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x0a, 0x98, 0x32,
+-0x0b, 0xa4, 0x0a, 0xa8, 0x32, 0x0d, 0x10, 0x10, 0xa4, 0x0a, 0xa0, 0x32,
+-0x0c, 0x91, 0x40, 0x90, 0x88, 0x90, 0x50, 0x90, 0x28, 0x80, 0x31, 0xe4,
+-0x80, 0x31, 0xe6, 0x10, 0x10, 0x80, 0x31, 0xe5, 0x90, 0x70, 0x90, 0x38,
+-0xa4, 0x09, 0xf0, 0x31, 0xf6, 0xa4, 0x0a, 0x00, 0x31, 0xf8, 0x10, 0x10,
+-0xa4, 0x09, 0xf8, 0x31, 0xf7, 0x90, 0xb8, 0x90, 0x70, 0x90, 0x38, 0xa4,
+-0x0b, 0x10, 0x32, 0x1a, 0xa4, 0x0b, 0x20, 0x32, 0x1c, 0x10, 0x10, 0xa4,
+-0x0b, 0x18, 0x32, 0x1b, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x0a, 0x80, 0x32,
+-0x08, 0xa4, 0x0a, 0x90, 0x32, 0x0a, 0x10, 0x10, 0xa4, 0x0a, 0x88, 0x32,
+-0x09, 0x10, 0x10, 0x80, 0x10, 0x10, 0x10, 0x10, 0x90, 0x50, 0x90, 0x28,
+-0x80, 0x31, 0xdb, 0x80, 0x31, 0xdd, 0x10, 0x10, 0x80, 0x31, 0xdc, 0x80,
+-0x95, 0x60, 0x92, 0xb0, 0x91, 0x40, 0x90, 0x88, 0x90, 0x50, 0x90, 0x28,
+-0x80, 0x31, 0xe1, 0x80, 0x31, 0xe3, 0x10, 0x10, 0x80, 0x31, 0xe2, 0x90,
+-0x70, 0x90, 0x38, 0xa4, 0x09, 0xd8, 0x31, 0xf3, 0xa4, 0x09, 0xe8, 0x31,
+-0xf5, 0x10, 0x10, 0xa4, 0x09, 0xe0, 0x31, 0xf4, 0x90, 0xb8, 0x90, 0x70,
+-0x90, 0x38, 0xa4, 0x0a, 0xf8, 0x32, 0x17, 0xa4, 0x0b, 0x08, 0x32, 0x19,
+-0x10, 0x10, 0xa4, 0x0b, 0x00, 0x32, 0x18, 0x90, 0x70, 0x90, 0x38, 0xa4,
+-0x0a, 0x68, 0x32, 0x05, 0xa4, 0x0a, 0x78, 0x32, 0x07, 0x10, 0x10, 0xa4,
+-0x0a, 0x70, 0x32, 0x06, 0x91, 0x40, 0x90, 0x88, 0x90, 0x50, 0x90, 0x28,
+-0x80, 0x31, 0xde, 0x80, 0x31, 0xe0, 0x10, 0x10, 0x80, 0x31, 0xdf, 0x90,
+-0x70, 0x90, 0x38, 0xa4, 0x09, 0xc0, 0x31, 0xf0, 0xa4, 0x09, 0xd0, 0x31,
+-0xf2, 0x10, 0x10, 0xa4, 0x09, 0xc8, 0x31, 0xf1, 0x90, 0xb8, 0x90, 0x70,
+-0x90, 0x38, 0xa4, 0x0a, 0xe0, 0x32, 0x14, 0xa4, 0x0a, 0xf0, 0x32, 0x16,
+-0x10, 0x10, 0xa4, 0x0a, 0xe8, 0x32, 0x15, 0x90, 0x70, 0x90, 0x38, 0xa4,
+-0x0a, 0x50, 0x32, 0x02, 0xa4, 0x0a, 0x60, 0x32, 0x04, 0x10, 0x10, 0xa4,
+-0x0a, 0x58, 0x32, 0x03, 0x10, 0x10, 0x92, 0x40, 0x91, 0x20, 0x90, 0x90,
+-0x90, 0x48, 0x80, 0xe3, 0xa0, 0x3c, 0xc0, 0x30, 0xfa, 0x80, 0xe3, 0xa0,
+-0x3c, 0x80, 0x30, 0xf8, 0x90, 0x48, 0x80, 0xe3, 0xa0, 0x3c, 0x40, 0x30,
+-0xf6, 0x80, 0xe3, 0xa0, 0x3c, 0x00, 0x30, 0xf4, 0x90, 0x90, 0x90, 0x48,
+-0x80, 0xe3, 0xa0, 0x3a, 0x40, 0x30, 0xe4, 0x80, 0xe3, 0xa0, 0x3a, 0x00,
+-0x30, 0xee, 0x90, 0x48, 0x80, 0xe3, 0xa0, 0x39, 0xc0, 0x30, 0xec, 0x80,
+-0xe3, 0xa0, 0x39, 0x80, 0x30, 0xea, 0x91, 0x20, 0x90, 0x90, 0x90, 0x48,
+-0x80, 0xe3, 0xa0, 0x37, 0x40, 0x30, 0xcc, 0x80, 0xe3, 0xa0, 0x37, 0x00,
+-0x30, 0xe2, 0x90, 0x48, 0x80, 0xe3, 0xa0, 0x36, 0xc0, 0x30, 0xe0, 0x80,
+-0xe3, 0xa0, 0x36, 0x80, 0x30, 0xde, 0x90, 0x90, 0x90, 0x48, 0x80, 0xe3,
+-0xa0, 0x34, 0xc0, 0x30, 0xce, 0x80, 0xe3, 0xa0, 0x34, 0x80, 0x30, 0xd8,
+-0x90, 0x48, 0x80, 0xe3, 0xa0, 0x34, 0x40, 0x30, 0xd6, 0x80, 0xe3, 0xa0,
+-0x34, 0x00, 0x30, 0xd4, 0xc3, 0xc0, 0x30, 0x42, 0x9d, 0x18, 0x07, 0xf0,
+-0x91, 0xc0, 0x90, 0xf0, 0x10, 0x10, 0x80, 0x88, 0x00, 0x80, 0x90, 0x50,
+-0x90, 0x28, 0x80, 0x37, 0x1c, 0x80, 0x37, 0x1d, 0x81, 0x37, 0x13, 0xd0,
+-0x41, 0x80, 0x24, 0x39, 0xb0, 0x24, 0x39, 0xb8, 0x10, 0x10, 0x80, 0x90,
+-0x58, 0x80, 0x90, 0x28, 0x24, 0x38, 0xb0, 0x24, 0x38, 0xb8, 0x90, 0x30,
+-0x80, 0x24, 0x38, 0x60, 0x80, 0x24, 0x38, 0x58, 0x92, 0x68, 0x91, 0x00,
+-0x80, 0x90, 0x90, 0x90, 0x30, 0x80, 0x24, 0x39, 0x20, 0x90, 0x38, 0xa4,
+-0x39, 0x18, 0x37, 0x2a, 0x80, 0x37, 0x29, 0x80, 0x90, 0x28, 0x80, 0x37,
+-0x33, 0xa4, 0x39, 0x00, 0x37, 0x32, 0x80, 0x90, 0xc0, 0x90, 0x60, 0x90,
+-0x28, 0x80, 0x37, 0x2d, 0xa4, 0x39, 0x10, 0x37, 0x2c, 0x90, 0x28, 0x80,
+-0x37, 0x28, 0xa4, 0x39, 0x08, 0x37, 0x27, 0x90, 0x50, 0x90, 0x28, 0x80,
+-0x37, 0x31, 0x80, 0x37, 0x30, 0x90, 0x28, 0x24, 0x39, 0xa8, 0x24, 0x39,
+-0xa0, 0x90, 0x58, 0x80, 0x10, 0x10, 0x80, 0x10, 0x10, 0x80, 0x37, 0x1f,
+-0x80, 0x90, 0x40, 0x10, 0x10, 0x80, 0x24, 0x38, 0x70, 0x80, 0x10, 0x10,
+-0x80, 0x37, 0x1e, 0x91, 0xb8, 0x91, 0x60, 0x90, 0xe0, 0x80, 0x90, 0x78,
+-0x90, 0x50, 0x90, 0x28, 0x80, 0x37, 0x1a, 0x80, 0x37, 0x1b, 0x81, 0x37,
+-0x12, 0x10, 0x10, 0x90, 0x28, 0x24, 0x38, 0x80, 0x24, 0x38, 0x78, 0x81,
+-0x90, 0x50, 0x90, 0x28, 0x80, 0x37, 0x18, 0x80, 0x37, 0x19, 0x81, 0x37,
+-0x11, 0x83, 0x90, 0x28, 0x24, 0x38, 0xa0, 0x24, 0x38, 0xa8, 0x90, 0xe8,
+-0x81, 0x90, 0x88, 0x90, 0x38, 0x10, 0x10, 0x80, 0x37, 0x2b, 0x90, 0x28,
+-0x80, 0x37, 0x26, 0x80, 0x37, 0x25, 0x80, 0x90, 0x28, 0x80, 0x37, 0x2f,
+-0x80, 0x37, 0x2e, 0x82, 0x10, 0x10, 0x80, 0x24, 0x38, 0x68, 0x97, 0x10,
+-0x9e, 0x10, 0x06, 0x98, 0x93, 0x00, 0x91, 0x80, 0x90, 0xc0, 0x90, 0x60,
+-0x90, 0x38, 0xa4, 0x04, 0x80, 0x30, 0x91, 0x24, 0x04, 0x78, 0x90, 0x38,
+-0xa4, 0x05, 0x10, 0x30, 0xa3, 0x24, 0x05, 0x08, 0x90, 0x60, 0x90, 0x38,
+-0xa4, 0x06, 0x30, 0x30, 0xc7, 0x24, 0x06, 0x28, 0x90, 0x38, 0xa4, 0x05,
+-0xa0, 0x30, 0xb5, 0x24, 0x05, 0x98, 0x90, 0xc0, 0x90, 0x60, 0x90, 0x38,
+-0xa4, 0x04, 0x70, 0x30, 0x8c, 0x24, 0x04, 0x68, 0x90, 0x38, 0xa4, 0x05,
+-0x00, 0x30, 0x9e, 0x24, 0x04, 0xf8, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x06,
+-0x20, 0x30, 0xc2, 0x24, 0x06, 0x18, 0x90, 0x38, 0xa4, 0x05, 0x90, 0x30,
+-0xb0, 0x24, 0x05, 0x88, 0x91, 0x80, 0x90, 0xc0, 0x90, 0x60, 0x90, 0x38,
+-0xa4, 0x04, 0x58, 0x30, 0x89, 0x24, 0x04, 0x50, 0x90, 0x38, 0xa4, 0x04,
+-0xe8, 0x30, 0x9b, 0x24, 0x04, 0xe0, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x06,
+-0x08, 0x30, 0xbf, 0x24, 0x06, 0x00, 0x90, 0x38, 0xa4, 0x05, 0x78, 0x30,
+-0xad, 0x24, 0x05, 0x70, 0x90, 0xc0, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x04,
+-0x40, 0x30, 0x86, 0x24, 0x04, 0x38, 0x90, 0x38, 0xa4, 0x04, 0xd0, 0x30,
+-0x98, 0x24, 0x04, 0xc8, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x05, 0xf0, 0x30,
+-0xbc, 0x24, 0x05, 0xe8, 0x90, 0x38, 0xa4, 0x05, 0x60, 0x30, 0xaa, 0x24,
+-0x05, 0x58, 0x10, 0x10, 0x80, 0x10, 0x10, 0x10, 0x10, 0x90, 0x38, 0xa4,
+-0x03, 0xf8, 0x30, 0x7d, 0x24, 0x03, 0xf0, 0xd7, 0x42, 0x00, 0xa4, 0x52,
+-0x70, 0x3a, 0x50, 0xa4, 0x52, 0x50, 0x3a, 0x4c, 0x9f, 0x20, 0x08, 0xd0,
+-0x93, 0x00, 0x91, 0x80, 0x90, 0xc0, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x04,
+-0x28, 0x30, 0x83, 0x24, 0x04, 0x20, 0x90, 0x38, 0xa4, 0x04, 0xb8, 0x30,
+-0x95, 0x24, 0x04, 0xb0, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x05, 0xd8, 0x30,
+-0xb9, 0x24, 0x05, 0xd0, 0x90, 0x38, 0xa4, 0x05, 0x48, 0x30, 0xa7, 0x24,
+-0x05, 0x40, 0x90, 0xc0, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x04, 0x10, 0x30,
+-0x80, 0x24, 0x04, 0x08, 0x90, 0x38, 0xa4, 0x04, 0xa0, 0x30, 0x92, 0x24,
+-0x04, 0x98, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x05, 0xc0, 0x30, 0xb6, 0x24,
+-0x05, 0xb8, 0x90, 0x38, 0xa4, 0x05, 0x30, 0x30, 0xa4, 0x24, 0x05, 0x28,
+-0x10, 0x10, 0x92, 0x00, 0x91, 0x00, 0x90, 0x80, 0x90, 0x40, 0xe3, 0xe0,
+-0x1a, 0x80, 0x30, 0x71, 0xe3, 0xe0, 0x1a, 0x40, 0x30, 0x6f, 0x90, 0x40,
+-0xe3, 0xe0, 0x1a, 0x00, 0x30, 0x6d, 0xe3, 0xe0, 0x19, 0xc0, 0x30, 0x6b,
+-0x90, 0x80, 0x90, 0x40, 0xe3, 0xe0, 0x18, 0x00, 0x30, 0x5b, 0xe3, 0xe0,
+-0x17, 0xc0, 0x30, 0x65, 0x90, 0x40, 0xe3, 0xe0, 0x17, 0x80, 0x30, 0x63,
+-0xe3, 0xe0, 0x17, 0x40, 0x30, 0x61, 0x91, 0x00, 0x90, 0x80, 0x90, 0x40,
+-0xe3, 0xe0, 0x15, 0x00, 0x30, 0x43, 0xe3, 0xe0, 0x14, 0xc0, 0x30, 0x59,
+-0x90, 0x40, 0xe3, 0xe0, 0x14, 0x80, 0x30, 0x57, 0xe3, 0xe0, 0x14, 0x40,
+-0x30, 0x55, 0x90, 0x80, 0x90, 0x40, 0xe3, 0xe0, 0x12, 0x80, 0x30, 0x45,
+-0xe3, 0xe0, 0x12, 0x40, 0x30, 0x4f, 0x90, 0x40, 0xe3, 0xe0, 0x12, 0x00,
+-0x30, 0x4d, 0xe3, 0xe0, 0x11, 0xc0, 0x30, 0x4b, 0x91, 0x48, 0x80, 0x90,
+-0xa0, 0x90, 0x50, 0x90, 0x28, 0x80, 0x30, 0x76, 0x24, 0x03, 0xa8, 0x90,
+-0x28, 0x80, 0x30, 0x78, 0x24, 0x03, 0xb8, 0x90, 0x50, 0x90, 0x28, 0x80,
+-0x30, 0x7c, 0x24, 0x03, 0xd8, 0x90, 0x28, 0x80, 0x30, 0x7a, 0x24, 0x03,
+-0xc8, 0x80, 0x10, 0x10, 0x10, 0x10, 0x90, 0x28, 0x80, 0x30, 0x73, 0x24,
+-0x03, 0xa0, 0xd7, 0x42, 0x00, 0xa4, 0x52, 0x78, 0x3a, 0x51, 0xa4, 0x52,
+-0x58, 0x3a, 0x4d, 0xa0, 0x14, 0x68, 0xa0, 0x10, 0x90, 0xa0, 0x0c, 0x60,
+-0x9e, 0x88, 0x09, 0xd0, 0x94, 0xf0, 0x90, 0xb0, 0x88, 0x00, 0x68, 0x84,
+-0x10, 0x10, 0xc9, 0xe2, 0x15, 0x00, 0x85, 0x38, 0x70, 0xcb, 0x62, 0x0d,
+-0xc0, 0x85, 0x38, 0x46, 0x9a, 0x00, 0x03, 0xf8, 0x91, 0x98, 0x80, 0x91,
+-0x10, 0x90, 0xa0, 0x90, 0x68, 0x90, 0x20, 0x3d, 0x98, 0xc9, 0xe3, 0x65,
+-0x80, 0x85, 0x38, 0x6e, 0xa4, 0x6c, 0xa0, 0x3d, 0x95, 0x90, 0x38, 0xa4,
+-0x6c, 0x68, 0x3d, 0x8e, 0xa4, 0x6c, 0x58, 0x3d, 0x8c, 0x90, 0x48, 0x10,
+-0x10, 0xa4, 0x6c, 0x20, 0x3d, 0x85, 0x10, 0x10, 0x80, 0x3d, 0x81, 0x81,
+-0x10, 0x10, 0x80, 0xa4, 0x6b, 0xf0, 0x3d, 0x7f, 0x91, 0xb0, 0x91, 0x60,
+-0x90, 0xe0, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x6c, 0x90, 0x3d, 0x93, 0xa4,
+-0x6c, 0x80, 0x3d, 0x91, 0x90, 0x38, 0xa4, 0x6c, 0x48, 0x3d, 0x8a, 0xa4,
+-0x6c, 0x38, 0x3d, 0x88, 0x90, 0x48, 0x10, 0x10, 0xa4, 0x6c, 0x10, 0x3d,
+-0x83, 0x10, 0x10, 0x80, 0x3d, 0x80, 0x90, 0x28, 0x80, 0x3d, 0x79, 0x80,
+-0x3d, 0x78, 0x81, 0x10, 0x10, 0x80, 0xa4, 0x6b, 0xe0, 0x3d, 0x7d, 0xcb,
+-0x62, 0x0d, 0x80, 0x85, 0x38, 0x45, 0x90, 0xd8, 0x88, 0x00, 0x90, 0x84,
+-0x90, 0x38, 0xc1, 0xc0, 0x85, 0x3d, 0x9b, 0xc9, 0xe2, 0x14, 0xc0, 0x85,
+-0x38, 0x6c, 0xcb, 0x62, 0x0d, 0x40, 0x85, 0x38, 0x44, 0x88, 0x00, 0x68,
+-0x84, 0x10, 0x10, 0xc9, 0xe2, 0x14, 0x80, 0x85, 0x38, 0x6a, 0xcb, 0x62,
+-0x0d, 0x00, 0x85, 0x38, 0x43, 0x91, 0xf8, 0x90, 0xb0, 0x88, 0x00, 0x68,
+-0x84, 0x10, 0x10, 0xc9, 0xe2, 0x14, 0x00, 0x85, 0x38, 0x66, 0xcb, 0x62,
+-0x0c, 0x80, 0x85, 0x38, 0x41, 0x88, 0x01, 0x00, 0x90, 0xa0, 0x81, 0x90,
+-0x70, 0x80, 0x90, 0x20, 0x3d, 0x8f, 0xc9, 0xe2, 0x13, 0xc0, 0x85, 0x38,
+-0x64, 0x81, 0x3d, 0x86, 0x81, 0x10, 0x10, 0x80, 0xa4, 0x6b, 0xd0, 0x3d,
+-0x7b, 0xcb, 0x62, 0x0c, 0x40, 0x85, 0x38, 0x40, 0x90, 0xb0, 0x88, 0x00,
+-0x68, 0x84, 0x10, 0x10, 0xc9, 0xe2, 0x13, 0x80, 0x85, 0x38, 0x62, 0xcb,
+-0x62, 0x0c, 0x00, 0x85, 0x38, 0x3f, 0x88, 0x00, 0x68, 0x84, 0x10, 0x10,
+-0xc9, 0xe2, 0x13, 0x40, 0x85, 0x38, 0x60, 0xcb, 0x62, 0x0b, 0xc0, 0x85,
+-0x38, 0x3e, 0x92, 0x38, 0x81, 0x91, 0x68, 0x91, 0x18, 0x90, 0x80, 0x90,
+-0x40, 0x80, 0xa4, 0x6d, 0x50, 0x3d, 0xab, 0x80, 0xa4, 0x6d, 0x48, 0x3d,
+-0xa8, 0x90, 0x28, 0x81, 0x3d, 0xa7, 0x90, 0x38, 0xa4, 0x6d, 0x28, 0x3d,
+-0xa6, 0xa4, 0x6d, 0x18, 0x3d, 0xa4, 0x90, 0x28, 0x80, 0x3d, 0xa2, 0x80,
+-0x3d, 0xa1, 0x80, 0x90, 0x40, 0x10, 0x10, 0x80, 0x24, 0x6d, 0x00, 0x10,
+-0x10, 0x90, 0x38, 0xa4, 0x6c, 0xf0, 0x3d, 0x9f, 0xa4, 0x6c, 0xe0, 0x3d,
+-0x9d, 0x90, 0x28, 0x80, 0x3d, 0x9a, 0x80, 0x3d, 0x99, 0x9a, 0xd0, 0x03,
+-0xe0, 0x91, 0x60, 0x90, 0xb0, 0x88, 0x00, 0x68, 0x84, 0x10, 0x10, 0xc9,
+-0xe2, 0x12, 0xc0, 0x85, 0x38, 0x5c, 0xcb, 0x62, 0x0b, 0x40, 0x85, 0x38,
+-0x3c, 0x88, 0x00, 0x68, 0x84, 0x10, 0x10, 0xc9, 0xe2, 0x12, 0x80, 0x85,
+-0x38, 0x5a, 0xcb, 0x62, 0x0b, 0x00, 0x85, 0x38, 0x3b, 0x90, 0xb0, 0x88,
+-0x00, 0x68, 0x84, 0x10, 0x10, 0xc9, 0xe2, 0x12, 0x40, 0x85, 0x38, 0x58,
+-0xcb, 0x62, 0x0a, 0xc0, 0x85, 0x38, 0x3a, 0x88, 0x00, 0x68, 0x84, 0x10,
+-0x10, 0xc9, 0xe2, 0x12, 0x00, 0x85, 0x38, 0x56, 0xcb, 0x62, 0x0a, 0x80,
+-0x85, 0x38, 0x39, 0x90, 0x90, 0x90, 0x48, 0xcb, 0xa2, 0x08, 0xc0, 0x85,
+-0x38, 0x28, 0xcb, 0xa2, 0x08, 0x80, 0x85, 0x38, 0x27, 0x90, 0x48, 0xcb,
+-0xa2, 0x08, 0x40, 0x85, 0x38, 0x26, 0xcb, 0xa2, 0x08, 0x00, 0x85, 0x38,
+-0x25, 0xcb, 0xa3, 0x5d, 0x80, 0x80, 0x3d, 0x77, 0x92, 0x40, 0x91, 0x20,
+-0x90, 0x90, 0x90, 0x48, 0x8c, 0x40, 0x78, 0x84, 0x24, 0x40, 0xf0, 0x8c,
+-0x40, 0x70, 0x84, 0x24, 0x40, 0xe8, 0x90, 0x48, 0x8c, 0x40, 0x68, 0x84,
+-0x24, 0x40, 0xe0, 0x8c, 0x40, 0x60, 0x84, 0x24, 0x40, 0xd8, 0x90, 0x90,
+-0x90, 0x48, 0x8c, 0x40, 0x50, 0x84, 0x24, 0x40, 0xc8, 0x8c, 0x40, 0x48,
+-0x84, 0x24, 0x40, 0xc0, 0x90, 0x48, 0x8c, 0x40, 0x40, 0x84, 0x24, 0x40,
+-0xb8, 0x8c, 0x40, 0x38, 0x84, 0x24, 0x40, 0xb0, 0x91, 0x20, 0x90, 0x90,
+-0x90, 0x48, 0x8c, 0x40, 0x28, 0x84, 0x24, 0x40, 0xa0, 0x8c, 0x40, 0x20,
+-0x84, 0x24, 0x40, 0x98, 0x90, 0x48, 0x8c, 0x40, 0x18, 0x84, 0x24, 0x40,
+-0x90, 0x8c, 0x40, 0x10, 0x84, 0x24, 0x40, 0x88, 0x90, 0x38, 0xa4, 0x3f,
+-0xf8, 0x38, 0x00, 0xa4, 0x3f, 0xe8, 0x37, 0xfe, 0xa0, 0x0f, 0x50, 0xa0,
+-0x09, 0x08, 0x9a, 0x30, 0x04, 0x40, 0x91, 0x90, 0x90, 0xc8, 0x98, 0x50,
+-0x00, 0x80, 0xe5, 0x23, 0x5b, 0x80, 0x3d, 0x66, 0xe5, 0x23, 0x53, 0x80,
+-0x3d, 0x62, 0xcb, 0x61, 0xfb, 0x00, 0x85, 0x37, 0xfb, 0x98, 0x50, 0x00,
+-0x80, 0xe5, 0x23, 0x4b, 0x80, 0x3d, 0x26, 0xe5, 0x23, 0x43, 0x80, 0x3d,
+-0x22, 0xcb, 0x61, 0xfa, 0xc0, 0x85, 0x37, 0xfa, 0x90, 0x48, 0xcb, 0xa1,
+-0xfa, 0x80, 0x85, 0x37, 0xf9, 0xcb, 0xa1, 0xfa, 0x40, 0x85, 0x37, 0xf8,
+-0x91, 0x90, 0x90, 0xc8, 0x98, 0x50, 0x00, 0x80, 0xe5, 0x23, 0x35, 0x80,
+-0x3c, 0xee, 0xe5, 0x23, 0x29, 0x80, 0x3c, 0xbe, 0xcb, 0x61, 0xf9, 0xc0,
+-0x85, 0x37, 0xf6, 0x98, 0x50, 0x00, 0x80, 0xe5, 0x23, 0x1d, 0x80, 0x3c,
+-0x8e, 0xe5, 0x23, 0x11, 0x80, 0x3c, 0x5e, 0xcb, 0x61, 0xf9, 0x80, 0x85,
+-0x37, 0xf5, 0x90, 0x48, 0xcb, 0xa1, 0xf9, 0x40, 0x85, 0x37, 0xf4, 0xcb,
+-0xa1, 0xf9, 0x00, 0x85, 0x37, 0xf3, 0x92, 0x20, 0x91, 0x30, 0x90, 0xb8,
+-0xd5, 0x03, 0x00, 0xc0, 0xc0, 0x81, 0x8c, 0x01, 0xa0, 0x84, 0x30, 0x3e,
+-0xc0, 0xc0, 0x81, 0x8c, 0x01, 0x80, 0x84, 0x30, 0x3c, 0xd5, 0x02, 0x00,
+-0xc0, 0xc0, 0x81, 0x30, 0x28, 0xc0, 0xc0, 0x81, 0x30, 0x24, 0x90, 0x78,
+-0xd5, 0x02, 0x00, 0xc0, 0xc0, 0x81, 0x30, 0x1c, 0xc0, 0xc0, 0x81, 0x30,
+-0x18, 0xd5, 0x02, 0x00, 0xc0, 0xc0, 0x81, 0x30, 0x10, 0xc0, 0xc0, 0x81,
+-0x30, 0x0c, 0x91, 0x70, 0x90, 0xd8, 0xd5, 0x03, 0x80, 0xc8, 0xe3, 0x09,
+-0x80, 0x81, 0x8c, 0x01, 0xc0, 0x84, 0x30, 0x40, 0xc8, 0xe3, 0x0b, 0x80,
+-0x81, 0x8c, 0x01, 0x90, 0x84, 0x30, 0x3d, 0xd5, 0x02, 0x80, 0xc8, 0xe3,
+-0x08, 0x80, 0x81, 0x30, 0x2c, 0xc8, 0xe3, 0x03, 0x00, 0x81, 0x30, 0x26,
+-0x90, 0x98, 0xd5, 0x02, 0x80, 0xc8, 0xe2, 0xf8, 0x00, 0x81, 0x30, 0x20,
+-0xc8, 0xe2, 0xfa, 0x00, 0x81, 0x30, 0x1a, 0xd5, 0x02, 0x80, 0xc8, 0xe2,
+-0xf7, 0x00, 0x81, 0x30, 0x14, 0xc8, 0xe2, 0xf1, 0x80, 0x81, 0x30, 0x0e,
+-0x9a, 0x30, 0x04, 0x40, 0x91, 0x90, 0x90, 0xc8, 0x98, 0x50, 0x00, 0x80,
+-0xe5, 0x23, 0x4f, 0x80, 0x3d, 0x36, 0xe5, 0x23, 0x51, 0x80, 0x3d, 0x5a,
+-0xcb, 0x61, 0xf8, 0x80, 0x85, 0x37, 0xf1, 0x98, 0x50, 0x00, 0x80, 0xe5,
+-0x23, 0x3f, 0x80, 0x3c, 0xf6, 0xe5, 0x23, 0x41, 0x80, 0x3d, 0x1a, 0xcb,
+-0x61, 0xf8, 0x40, 0x85, 0x37, 0xf0, 0x90, 0x48, 0xcb, 0xa1, 0xf8, 0x00,
+-0x85, 0x37, 0xef, 0xcb, 0xa1, 0xf7, 0xc0, 0x85, 0x37, 0xee, 0x91, 0x90,
+-0x90, 0xc8, 0x98, 0x50, 0x00, 0x80, 0xe5, 0x23, 0x31, 0x80, 0x3c, 0xde,
+-0xe5, 0x23, 0x25, 0x80, 0x3c, 0xae, 0xcb, 0x61, 0xf6, 0x00, 0x85, 0x37,
+-0xdd, 0x98, 0x50, 0x00, 0x80, 0xe5, 0x23, 0x19, 0x80, 0x3c, 0x7e, 0xe5,
+-0x23, 0x0d, 0x80, 0x3c, 0x4e, 0xcb, 0x61, 0xf5, 0xc0, 0x85, 0x37, 0xdc,
+-0x90, 0x48, 0xcb, 0xa1, 0xf5, 0x80, 0x85, 0x37, 0xdb, 0xcb, 0xa1, 0xf5,
+-0x40, 0x85, 0x37, 0xda, 0x91, 0x00, 0x90, 0x80, 0x90, 0x40, 0xe5, 0x20,
+-0x02, 0x40, 0x30, 0x0a, 0xe5, 0x20, 0x01, 0x80, 0x30, 0x07, 0x90, 0x40,
+-0xe5, 0x20, 0x00, 0xc0, 0x30, 0x04, 0xe5, 0x20, 0x00, 0x00, 0x30, 0x01,
+-0x90, 0x80, 0x90, 0x40, 0xe5, 0x22, 0xfe, 0x80, 0x3b, 0xf0, 0xe5, 0x23,
+-0x00, 0xc0, 0x3c, 0x18, 0x90, 0x40, 0xe5, 0x22, 0xed, 0x00, 0x3b, 0xaa,
+-0xe5, 0x22, 0xef, 0x40, 0x3b, 0xd2, 0x80, 0x99, 0x28, 0x02, 0xf0, 0x8c,
+-0x3e, 0x60, 0x90, 0x80, 0x90, 0x40, 0xe5, 0x23, 0x55, 0x80, 0x3d, 0x52,
+-0xe5, 0x23, 0x52, 0x80, 0x3d, 0x5e, 0x90, 0x40, 0xe5, 0x23, 0x45, 0x80,
+-0x3d, 0x12, 0xe5, 0x23, 0x42, 0x80, 0x3d, 0x1e, 0x91, 0x48, 0x90, 0xc8,
+-0x98, 0x50, 0x00, 0x80, 0xe5, 0x23, 0x33, 0x80, 0x3c, 0xe6, 0xe5, 0x23,
+-0x27, 0x80, 0x3c, 0xb6, 0xcb, 0x61, 0xf3, 0xc0, 0x85, 0x37, 0xd3, 0x90,
+-0x40, 0xe5, 0x23, 0x1b, 0x80, 0x3c, 0x86, 0xe5, 0x23, 0x0f, 0x80, 0x3c,
+-0x56, 0x90, 0x48, 0xcb, 0xa1, 0xf3, 0x40, 0x85, 0x37, 0xd1, 0xcb, 0xa1,
+-0xf3, 0x80, 0x85, 0x37, 0xd2, 0x10, 0x10, 0x90, 0x80, 0x90, 0x40, 0xe5,
+-0x23, 0x05, 0x00, 0x3c, 0x10, 0xe5, 0x23, 0x02, 0x00, 0x3c, 0x1e, 0x90,
+-0x40, 0xe5, 0x22, 0xf3, 0x80, 0x3b, 0xca, 0xe5, 0x22, 0xf0, 0x80, 0x3b,
+-0xd8,
++0xa1, 0x02, 0x78, 0xa0, 0x2f, 0x28, 0xa0, 0x2d, 0x10, 0xa0, 0x1c, 0x40,
++0x98, 0xb0, 0x02, 0x50, 0x90, 0x50, 0x90, 0x28, 0x24, 0x52, 0x40, 0x24,
++0x52, 0x38, 0x90, 0x28, 0x24, 0x52, 0x30, 0x24, 0x52, 0x28, 0x91, 0x60,
++0x90, 0x28, 0x24, 0x52, 0x18, 0x10, 0x10, 0x58, 0x41, 0x62, 0x90, 0x80,
++0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
++0x10, 0x10, 0x52, 0xc0, 0xc0, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
++0x10, 0x10, 0x10, 0x24, 0x3d, 0x90, 0x90, 0x28, 0x24, 0x52, 0x08, 0x24,
++0x52, 0x00, 0xa8, 0x0b, 0x88, 0x15, 0x60, 0x97, 0x60, 0x96, 0x08, 0x9a,
++0xf8, 0x05, 0x78, 0x91, 0x58, 0x90, 0xe0, 0x90, 0xa0, 0x80, 0x90, 0x20,
++0x37, 0xc9, 0x90, 0x20, 0x37, 0xc6, 0xcb, 0xa1, 0xf1, 0x00, 0xa4, 0x37,
++0xf8, 0x37, 0x00, 0x80, 0xa4, 0x4f, 0xb8, 0x39, 0xfc, 0x90, 0x50, 0x90,
++0x28, 0x80, 0x39, 0xf2, 0x80, 0x37, 0xaa, 0x81, 0x37, 0x03, 0x90, 0xe0,
++0x90, 0x70, 0x90, 0x38, 0xa4, 0x3d, 0x30, 0x37, 0xa7, 0xa4, 0x38, 0x10,
++0x37, 0xa4, 0x90, 0x38, 0xa4, 0x51, 0xb8, 0x3a, 0x3d, 0xa4, 0x51, 0x60,
++0x3a, 0x31, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x50, 0x38, 0x3a, 0x12, 0xa4,
++0x50, 0x10, 0x3a, 0x0d, 0x80, 0xa4, 0x3d, 0x10, 0x37, 0xa3, 0x92, 0x18,
++0x91, 0xc0, 0x80, 0x91, 0x80, 0x90, 0xf8, 0xdb, 0x84, 0x61, 0xc1, 0x80,
++0xc0, 0xc0, 0x80, 0xa4, 0x5b, 0x80, 0x8c, 0x5c, 0xe0, 0x84, 0x3b, 0xa6,
++0xc0, 0xc0, 0x80, 0xa4, 0x5b, 0x70, 0x8c, 0x5c, 0xc0, 0x84, 0x3b, 0xa4,
++0xd3, 0x82, 0x40, 0x50, 0xc0, 0xc0, 0x81, 0x3b, 0x58, 0x50, 0xc0, 0xc0,
++0x81, 0x3b, 0x56, 0xa4, 0x38, 0x20, 0x37, 0x05, 0x80, 0x90, 0x28, 0x80,
++0x37, 0x01, 0x80, 0x37, 0xac, 0x81, 0x90, 0x38, 0xa4, 0x3d, 0xa0, 0x37,
++0xaf, 0xa4, 0x3d, 0x68, 0x37, 0xa9, 0xc0, 0x40, 0x10, 0x10, 0x90, 0x38,
++0xa4, 0x37, 0xe8, 0x36, 0xfe, 0xa4, 0x37, 0xd8, 0x36, 0xfc, 0x18, 0x24,
++0x3e, 0x18, 0x83, 0x90, 0xa8, 0xd3, 0x82, 0xc0, 0xc0, 0xc0, 0x80, 0xa4,
++0x5b, 0x50, 0x3b, 0x90, 0xc0, 0xc0, 0x80, 0xa4, 0x5b, 0x40, 0x3b, 0x8c,
++0xd3, 0x82, 0x40, 0x50, 0xc0, 0xc0, 0x81, 0x3b, 0x52, 0x50, 0xc0, 0xc0,
++0x81, 0x3b, 0x50, 0x92, 0xb8, 0x99, 0x84, 0x3d, 0x88, 0x90, 0x78, 0x90,
++0x50, 0x10, 0x10, 0x80, 0xa4, 0x4f, 0xb0, 0x39, 0xfb, 0x82, 0x39, 0xf1,
++0x90, 0x80, 0x10, 0x10, 0x90, 0x38, 0xa4, 0x51, 0xb0, 0x3a, 0x3c, 0xa4,
++0x51, 0x58, 0x3a, 0x30, 0x80, 0x90, 0x38, 0xa4, 0x50, 0x30, 0x3a, 0x11,
++0xa4, 0x50, 0x08, 0x3a, 0x0c, 0x83, 0x90, 0xa8, 0xd3, 0x82, 0xc0, 0xc0,
++0xc0, 0x80, 0xa4, 0x5b, 0x20, 0x3b, 0x84, 0xc0, 0xc0, 0x80, 0xa4, 0x5b,
++0x10, 0x3b, 0x80, 0xd3, 0x82, 0x40, 0x50, 0xc0, 0xc0, 0x81, 0x3b, 0x4c,
++0x50, 0xc0, 0xc0, 0x81, 0x3b, 0x4a, 0x18, 0x24, 0x3d, 0x98, 0x83, 0x90,
++0xa8, 0xd3, 0x82, 0xc0, 0xc0, 0xc0, 0x80, 0xa4, 0x5a, 0xf0, 0x3b, 0x78,
++0xc0, 0xc0, 0x80, 0xa4, 0x5a, 0xe0, 0x3b, 0x74, 0xd3, 0x82, 0x40, 0x50,
++0xc0, 0xc0, 0x81, 0x3b, 0x46, 0x50, 0xc0, 0xc0, 0x81, 0x3b, 0x44, 0x94,
++0x50, 0x92, 0xf8, 0x99, 0x84, 0x38, 0x50, 0x90, 0x78, 0x90, 0x50, 0x10,
++0x10, 0x80, 0xa4, 0x4f, 0xa8, 0x39, 0xfa, 0x82, 0x39, 0xf0, 0x90, 0x80,
++0x10, 0x10, 0x90, 0x38, 0xa4, 0x51, 0xa8, 0x3a, 0x3b, 0xa4, 0x51, 0x50,
++0x3a, 0x2f, 0x80, 0x90, 0x38, 0xa4, 0x50, 0x28, 0x3a, 0x10, 0xa4, 0x50,
++0x00, 0x3a, 0x0b, 0x83, 0x90, 0xe8, 0xd3, 0x83, 0xc0, 0xc0, 0xc0, 0x80,
++0xa4, 0x5b, 0x90, 0x8c, 0x5d, 0x00, 0x84, 0x3b, 0xa8, 0xc0, 0xc0, 0x80,
++0xa4, 0x5b, 0x78, 0x8c, 0x5c, 0xd0, 0x84, 0x3b, 0xa5, 0xd3, 0x82, 0x40,
++0x50, 0xc0, 0xc0, 0x81, 0x3b, 0x5a, 0x50, 0xc0, 0xc0, 0x81, 0x3b, 0x57,
++0x18, 0x24, 0x38, 0x48, 0x83, 0x90, 0xa8, 0xd3, 0x82, 0xc0, 0xc0, 0xc0,
++0x80, 0xa4, 0x5b, 0x60, 0x3b, 0x94, 0xc0, 0xc0, 0x80, 0xa4, 0x5b, 0x48,
++0x3b, 0x8e, 0xd3, 0x82, 0x40, 0x50, 0xc0, 0xc0, 0x81, 0x3b, 0x54, 0x50,
++0xc0, 0xc0, 0x81, 0x3b, 0x51, 0x92, 0xb8, 0x99, 0x84, 0x38, 0x40, 0x90,
++0x78, 0x90, 0x50, 0x10, 0x10, 0x80, 0xa4, 0x4f, 0xa0, 0x39, 0xf9, 0x82,
++0x39, 0xef, 0x90, 0x80, 0x10, 0x10, 0x90, 0x38, 0xa4, 0x51, 0xa0, 0x3a,
++0x3a, 0xa4, 0x51, 0x48, 0x3a, 0x2e, 0x80, 0x90, 0x38, 0xa4, 0x50, 0x20,
++0x3a, 0x0f, 0xa4, 0x4f, 0xf8, 0x3a, 0x0a, 0x83, 0x90, 0xa8, 0xd3, 0x82,
++0xc0, 0xc0, 0xc0, 0x80, 0xa4, 0x5b, 0x30, 0x3b, 0x88, 0xc0, 0xc0, 0x80,
++0xa4, 0x5b, 0x18, 0x3b, 0x82, 0xd3, 0x82, 0x40, 0x50, 0xc0, 0xc0, 0x81,
++0x3b, 0x4e, 0x50, 0xc0, 0xc0, 0x81, 0x3b, 0x4b, 0x18, 0x20, 0x01, 0x48,
++0x83, 0x90, 0xa8, 0xd3, 0x82, 0xc0, 0xc0, 0xc0, 0x80, 0xa4, 0x5b, 0x00,
++0x3b, 0x7c, 0xc0, 0xc0, 0x80, 0xa4, 0x5a, 0xe8, 0x3b, 0x76, 0xd3, 0x82,
++0x40, 0x50, 0xc0, 0xc0, 0x81, 0x3b, 0x48, 0x50, 0xc0, 0xc0, 0x81, 0x3b,
++0x45, 0xda, 0x06, 0xe1, 0xc1, 0xc0, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x3e,
++0x08, 0x37, 0xbf, 0x80, 0x37, 0xbc, 0x90, 0x38, 0xa4, 0x3d, 0xb0, 0x37,
++0xba, 0x80, 0x37, 0xb7, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x3d, 0xf0, 0x37,
++0xc0, 0x80, 0x37, 0xbd, 0x90, 0x38, 0xa4, 0x3d, 0xc8, 0x37, 0xbb, 0x80,
++0x37, 0xb8, 0xc8, 0x40, 0x19, 0x00, 0x91, 0x58, 0x90, 0x60, 0x82, 0x90,
++0x20, 0x39, 0xee, 0xa4, 0x4f, 0x60, 0x39, 0xed, 0x90, 0xc0, 0x80, 0x90,
++0x90, 0x90, 0x48, 0xc9, 0xe2, 0x89, 0xc0, 0x85, 0x3a, 0x26, 0xc9, 0xe2,
++0x89, 0x00, 0x85, 0x3a, 0x23, 0x80, 0x3a, 0x22, 0x10, 0x10, 0x81, 0x39,
++0xfe, 0x90, 0xa8, 0x10, 0x10, 0x90, 0x28, 0x81, 0x3a, 0x1c, 0x90, 0x38,
++0xa4, 0x50, 0xb8, 0x3a, 0x18, 0xa4, 0x50, 0xa8, 0x3a, 0x16, 0x90, 0x70,
++0x10, 0x10, 0x90, 0x38, 0xa4, 0x50, 0xd0, 0x3a, 0x1b, 0x80, 0x3a, 0x19,
++0x90, 0x60, 0x90, 0x28, 0x24, 0x51, 0x08, 0xa4, 0x50, 0xf8, 0x3a, 0x20,
++0x80, 0xa4, 0x50, 0xe8, 0x3a, 0x1e, 0x80, 0x90, 0xf8, 0x90, 0x90, 0x90,
++0x50, 0x90, 0x28, 0x80, 0x3b, 0x3a, 0x80, 0x3b, 0x43, 0x80, 0xa4, 0x5a,
++0x08, 0x3b, 0x42, 0x90, 0x28, 0x81, 0x3b, 0x40, 0x80, 0xa4, 0x59, 0xf0,
++0x3b, 0x3f, 0x90, 0x28, 0x82, 0x3b, 0x3d, 0x81, 0xa4, 0x59, 0xd8, 0x3b,
++0x3c, 0x98, 0xe8, 0x01, 0xb0, 0x90, 0x88, 0x90, 0x60, 0xa4, 0x4f, 0x50,
++0x10, 0x10, 0x10, 0x10, 0x83, 0x36, 0xd5, 0x24, 0x4f, 0x48, 0x90, 0x28,
++0x24, 0x4f, 0x40, 0x24, 0x4f, 0x38, 0x90, 0x88, 0x90, 0x60, 0xa4, 0x4f,
++0x28, 0x10, 0x10, 0x10, 0x10, 0x83, 0x36, 0xd4, 0x24, 0x4f, 0x20, 0x90,
++0x28, 0x24, 0x4f, 0x18, 0x24, 0x4f, 0x10, 0xa8, 0x09, 0x10, 0x0e, 0x30,
++0x96, 0x58, 0x95, 0xf8, 0x93, 0x38, 0x91, 0xa0, 0x90, 0xd0, 0x90, 0x70,
++0x90, 0x38, 0xa4, 0x37, 0x58, 0x36, 0xec, 0xa4, 0x37, 0x48, 0x36, 0xea,
++0x90, 0x38, 0xa4, 0x37, 0x38, 0x36, 0xe8, 0x80, 0x36, 0xe6, 0x90, 0x60,
++0x90, 0x28, 0x24, 0x36, 0xf0, 0xa4, 0x36, 0xe0, 0x36, 0xdd, 0x90, 0x38,
++0xa4, 0x36, 0xd0, 0x36, 0xdb, 0xa4, 0x37, 0x20, 0x36, 0xe5, 0x90, 0xe0,
++0x90, 0x70, 0x90, 0x38, 0xa4, 0x37, 0x10, 0x36, 0xe3, 0xa4, 0x37, 0x00,
++0x36, 0xe1, 0x90, 0x38, 0xa4, 0x4e, 0xc8, 0x39, 0xdf, 0xa4, 0x4e, 0x68,
++0x39, 0xd3, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x4b, 0xa8, 0x39, 0x81, 0xa4,
++0x4b, 0x78, 0x39, 0x7b, 0x10, 0x10, 0xa4, 0x36, 0xc0, 0x36, 0xd9, 0x99,
++0x70, 0x02, 0x80, 0x90, 0xa0, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x37, 0x88,
++0x36, 0xdf, 0x80, 0x36, 0xf9, 0x80, 0xa4, 0x37, 0x90, 0x36, 0xf7, 0x90,
++0x50, 0x90, 0x28, 0x24, 0x37, 0x98, 0x80, 0x36, 0xfa, 0x90, 0x38, 0xa4,
++0x37, 0xa0, 0x36, 0xf8, 0xa4, 0x37, 0x68, 0x36, 0xee, 0x90, 0xe0, 0x90,
++0x70, 0x90, 0x38, 0xa4, 0x4e, 0x00, 0x39, 0xc8, 0xa4, 0x4d, 0x60, 0x39,
++0xb5, 0x90, 0x38, 0xa4, 0x4c, 0xf8, 0x39, 0xa6, 0xa4, 0x4c, 0x68, 0x39,
++0x95, 0x81, 0xa4, 0x37, 0x78, 0x36, 0xf0, 0xe4, 0xa2, 0xcd, 0x00, 0x3b,
++0x36, 0x18, 0x24, 0x36, 0xb8, 0xe4, 0xe2, 0xcb, 0x80, 0x3b, 0x30, 0x92,
++0x40, 0x91, 0x08, 0x10, 0x10, 0x90, 0x80, 0x10, 0x10, 0x90, 0x38, 0xa4,
++0x4e, 0xc0, 0x39, 0xde, 0xa4, 0x4e, 0x60, 0x39, 0xd2, 0x80, 0x90, 0x38,
++0xa4, 0x4b, 0xa0, 0x39, 0x80, 0xa4, 0x4b, 0x70, 0x39, 0x7a, 0x18, 0x20,
++0x00, 0xf8, 0x80, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x4d, 0xf0, 0x39, 0xc7,
++0xa4, 0x4d, 0x58, 0x39, 0xb3, 0x90, 0x38, 0xa4, 0x4c, 0xe8, 0x39, 0xa5,
++0xa4, 0x4c, 0x60, 0x39, 0x93, 0xe4, 0xa2, 0xca, 0x00, 0x3b, 0x2a, 0x18,
++0x24, 0x36, 0xb0, 0xe4, 0xe2, 0xc8, 0x80, 0x3b, 0x24, 0x92, 0x90, 0x92,
++0x40, 0x91, 0x08, 0x10, 0x10, 0x90, 0x80, 0x10, 0x10, 0x90, 0x38, 0xa4,
++0x4e, 0xb8, 0x39, 0xdd, 0xa4, 0x4e, 0x58, 0x39, 0xd1, 0x80, 0x90, 0x38,
++0xa4, 0x4b, 0x98, 0x39, 0x7f, 0xa4, 0x4b, 0x68, 0x39, 0x79, 0x18, 0x20,
++0x00, 0xf8, 0x80, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x4d, 0xe0, 0x39, 0xc6,
++0xa4, 0x4d, 0x50, 0x39, 0xb1, 0x90, 0x38, 0xa4, 0x4c, 0xd8, 0x39, 0xa4,
++0xa4, 0x4c, 0x58, 0x39, 0x91, 0xe4, 0xa2, 0xcd, 0x40, 0x3b, 0x38, 0x10,
++0x10, 0xe4, 0xe2, 0xcb, 0xc0, 0x3b, 0x32, 0x92, 0x50, 0x99, 0x1c, 0x37,
++0xa8, 0x10, 0x10, 0x90, 0x80, 0x10, 0x10, 0x90, 0x38, 0xa4, 0x4e, 0xb0,
++0x39, 0xdc, 0xa4, 0x4e, 0x50, 0x39, 0xd0, 0x80, 0x90, 0x38, 0xa4, 0x4b,
++0x90, 0x39, 0x7e, 0xa4, 0x4b, 0x60, 0x39, 0x78, 0x18, 0x20, 0x00, 0xf8,
++0x80, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x4d, 0xd0, 0x39, 0xc5, 0xa4, 0x4d,
++0x48, 0x39, 0xaf, 0x90, 0x38, 0xa4, 0x4c, 0xc8, 0x39, 0xa3, 0xa4, 0x4c,
++0x50, 0x39, 0x8f, 0xe4, 0xa2, 0xca, 0x40, 0x3b, 0x2c, 0x10, 0x10, 0xe4,
++0xe2, 0xc8, 0xc0, 0x3b, 0x26, 0xc0, 0x40, 0x80, 0x10, 0x10, 0x81, 0x90,
++0x90, 0x90, 0x48, 0xc9, 0xe2, 0x61, 0x40, 0x85, 0x39, 0x89, 0xc9, 0xe2,
++0x61, 0xc0, 0x85, 0x39, 0x86, 0x80, 0x39, 0x84, 0x80, 0xd8, 0x47, 0x80,
++0x0d, 0xc0, 0xc0, 0x80, 0x10, 0x10, 0x82, 0x90, 0x58, 0xd5, 0x81, 0x80,
++0x80, 0x3b, 0x20, 0x80, 0x3b, 0x1e, 0xd5, 0x81, 0x80, 0x80, 0x3b, 0x1c,
++0x80, 0x3b, 0x1a, 0xc0, 0x80, 0x10, 0x10, 0x82, 0x90, 0x58, 0xd5, 0x81,
++0x80, 0x80, 0x3b, 0x21, 0x80, 0x3b, 0x1f, 0xd5, 0x81, 0x80, 0x80, 0x3b,
++0x1d, 0x80, 0x3b, 0x1b, 0xc0, 0x80, 0x83, 0xa4, 0x58, 0xc0, 0x3b, 0x19,
++0xa0, 0x79, 0x20, 0xa0, 0x61, 0xa0, 0xa8, 0x3e, 0x70, 0x54, 0x48, 0xa0,
++0x21, 0x30, 0xa0, 0x14, 0xe0, 0xa0, 0x0a, 0xd8, 0x9d, 0x60, 0x0a, 0x90,
++0x92, 0xa0, 0x91, 0x50, 0x90, 0xb0, 0x90, 0x58, 0xa4, 0x20, 0x60, 0xe1,
++0xe1, 0xb3, 0x00, 0x36, 0xd3, 0xa4, 0x20, 0x80, 0xe1, 0xe1, 0xb2, 0xc0,
++0x36, 0xd1, 0x90, 0x48, 0x80, 0xe1, 0xe1, 0xb2, 0x80, 0x36, 0xcf, 0xa4,
++0x20, 0x70, 0xe1, 0xe1, 0xb2, 0x40, 0x36, 0xcd, 0x90, 0xb0, 0x90, 0x58,
++0xa4, 0x20, 0x00, 0xe1, 0xe1, 0x9a, 0x40, 0x36, 0x70, 0xa4, 0x20, 0x20,
++0xe1, 0xe1, 0x9a, 0x00, 0x36, 0x6e, 0x90, 0x48, 0x80, 0xe1, 0xe1, 0x99,
++0xc0, 0x36, 0x6c, 0xa4, 0x20, 0x10, 0xe1, 0xe1, 0x99, 0x80, 0x36, 0x6a,
++0x91, 0x50, 0x90, 0xb0, 0x90, 0x58, 0xa4, 0x1f, 0xa0, 0xe1, 0xe1, 0x81,
++0x80, 0x36, 0x0d, 0xa4, 0x1f, 0xc0, 0xe1, 0xe1, 0x81, 0x40, 0x36, 0x0b,
++0x90, 0x48, 0x80, 0xe1, 0xe1, 0x81, 0x00, 0x36, 0x09, 0xa4, 0x1f, 0xb0,
++0xe1, 0xe1, 0x80, 0xc0, 0x36, 0x07, 0x90, 0xc0, 0x90, 0x68, 0xa4, 0x1f,
++0x40, 0xe9, 0xe1, 0x68, 0xe1, 0x44, 0x00, 0x35, 0xaa, 0xa4, 0x1f, 0x60,
++0xe1, 0xe1, 0x68, 0x80, 0x35, 0xa8, 0x90, 0x48, 0x80, 0xe1, 0xe1, 0x68,
++0x40, 0x35, 0xa6, 0xa4, 0x1f, 0x50, 0xe1, 0xe1, 0x68, 0x00, 0x35, 0xa4,
++0x92, 0xa0, 0x91, 0x50, 0x90, 0xb0, 0x90, 0x58, 0xa4, 0x20, 0x30, 0xe1,
++0xe1, 0xb0, 0x80, 0x36, 0xbe, 0xa4, 0x20, 0x50, 0xe1, 0xe1, 0xb0, 0x40,
++0x36, 0xc7, 0x90, 0x48, 0x80, 0xe1, 0xe1, 0xb0, 0x00, 0x36, 0xc5, 0xa4,
++0x20, 0x40, 0xe1, 0xe1, 0xaf, 0xc0, 0x36, 0xc3, 0x90, 0xb0, 0x90, 0x58,
++0xa4, 0x1f, 0xd0, 0xe1, 0xe1, 0x97, 0xc0, 0x36, 0x5b, 0xa4, 0x1f, 0xf0,
++0xe1, 0xe1, 0x97, 0x80, 0x36, 0x64, 0x90, 0x48, 0x80, 0xe1, 0xe1, 0x97,
++0x40, 0x36, 0x62, 0xa4, 0x1f, 0xe0, 0xe1, 0xe1, 0x97, 0x00, 0x36, 0x60,
++0x91, 0x50, 0x90, 0xb0, 0x90, 0x58, 0xa4, 0x1f, 0x70, 0xe1, 0xe1, 0x7f,
++0x00, 0x35, 0xf8, 0xa4, 0x1f, 0x90, 0xe1, 0xe1, 0x7e, 0xc0, 0x36, 0x01,
++0x90, 0x48, 0x80, 0xe1, 0xe1, 0x7e, 0x80, 0x35, 0xff, 0xa4, 0x1f, 0x80,
++0xe1, 0xe1, 0x7e, 0x40, 0x35, 0xfd, 0x90, 0xb0, 0x90, 0x58, 0xa4, 0x1f,
++0x10, 0xe1, 0xe1, 0x66, 0x40, 0x35, 0x95, 0xa4, 0x1f, 0x30, 0xe1, 0xe1,
++0x66, 0x00, 0x35, 0x9e, 0x90, 0x48, 0x80, 0xe1, 0xe1, 0x65, 0xc0, 0x35,
++0x9c, 0xa4, 0x1f, 0x20, 0xe1, 0xe1, 0x65, 0x80, 0x35, 0x9a, 0xe4, 0xe2,
++0x54, 0x00, 0x39, 0x64, 0x9d, 0x50, 0x09, 0xc0, 0x92, 0xa0, 0x91, 0x50,
++0x90, 0xb0, 0x90, 0x58, 0xa4, 0x1e, 0xa8, 0xe1, 0xe1, 0xad, 0xc0, 0x36,
++0xb3, 0xa4, 0x1e, 0xa0, 0xe1, 0xe1, 0xad, 0x80, 0x36, 0xbc, 0x90, 0x48,
++0x80, 0xe1, 0xe1, 0xad, 0x40, 0x36, 0xba, 0xa4, 0x1e, 0x98, 0xe1, 0xe1,
++0xad, 0x00, 0x36, 0xb8, 0x90, 0xb0, 0x90, 0x58, 0xa4, 0x1e, 0x90, 0xe1,
++0xe1, 0x95, 0x00, 0x36, 0x50, 0xa4, 0x1e, 0x88, 0xe1, 0xe1, 0x94, 0xc0,
++0x36, 0x59, 0x90, 0x48, 0x80, 0xe1, 0xe1, 0x94, 0x80, 0x36, 0x57, 0xa4,
++0x1e, 0x80, 0xe1, 0xe1, 0x94, 0x40, 0x36, 0x55, 0x91, 0x50, 0x90, 0xb0,
++0x90, 0x58, 0xa4, 0x1e, 0x78, 0xe1, 0xe1, 0x7c, 0x40, 0x35, 0xed, 0xa4,
++0x1e, 0x70, 0xe1, 0xe1, 0x7c, 0x00, 0x35, 0xf6, 0x90, 0x48, 0x80, 0xe1,
++0xe1, 0x7b, 0xc0, 0x35, 0xf4, 0xa4, 0x1e, 0x68, 0xe1, 0xe1, 0x7b, 0x80,
++0x35, 0xf2, 0x90, 0xb0, 0x90, 0x58, 0xa4, 0x1e, 0x60, 0xe1, 0xe1, 0x63,
++0x80, 0x35, 0x8a, 0xa4, 0x1e, 0x58, 0xe1, 0xe1, 0x63, 0x40, 0x35, 0x93,
++0x90, 0x48, 0x80, 0xe1, 0xe1, 0x63, 0x00, 0x35, 0x91, 0xa4, 0x1e, 0x50,
++0xe1, 0xe1, 0x62, 0xc0, 0x35, 0x8f, 0x92, 0x40, 0x91, 0x20, 0x90, 0x90,
++0x90, 0x48, 0x80, 0xe1, 0xe1, 0xab, 0x00, 0x36, 0xa8, 0x80, 0xe1, 0xe1,
++0xaa, 0xc0, 0x36, 0xb1, 0x90, 0x48, 0x80, 0xe1, 0xe1, 0xaa, 0x80, 0x36,
++0xaf, 0x80, 0xe1, 0xe1, 0xaa, 0x40, 0x36, 0xad, 0x90, 0x90, 0x90, 0x48,
++0x80, 0xe1, 0xe1, 0x92, 0x40, 0x36, 0x45, 0x80, 0xe1, 0xe1, 0x92, 0x00,
++0x36, 0x4e, 0x90, 0x48, 0x80, 0xe1, 0xe1, 0x91, 0xc0, 0x36, 0x4c, 0x80,
++0xe1, 0xe1, 0x91, 0x80, 0x36, 0x4a, 0x91, 0x20, 0x90, 0x90, 0x90, 0x48,
++0x80, 0xe1, 0xe1, 0x79, 0x80, 0x35, 0xe2, 0x80, 0xe1, 0xe1, 0x79, 0x40,
++0x35, 0xeb, 0x90, 0x48, 0x80, 0xe1, 0xe1, 0x79, 0x00, 0x35, 0xe9, 0x80,
++0xe1, 0xe1, 0x78, 0xc0, 0x35, 0xe7, 0x90, 0x90, 0x90, 0x48, 0x80, 0xe1,
++0xe1, 0x60, 0xc0, 0x35, 0x7f, 0x80, 0xe1, 0xe1, 0x60, 0x80, 0x35, 0x88,
++0x90, 0x48, 0x80, 0xe1, 0xe1, 0x60, 0x40, 0x35, 0x86, 0x80, 0xe1, 0xe1,
++0x60, 0x00, 0x35, 0x84, 0xe4, 0xe2, 0x2f, 0x00, 0x38, 0xe4, 0xa0, 0x0a,
++0x08, 0x9c, 0xf0, 0x09, 0xc0, 0x92, 0x40, 0x91, 0x20, 0x90, 0x90, 0x90,
++0x48, 0x80, 0xe1, 0xe1, 0xa8, 0x40, 0x36, 0x9d, 0x80, 0xe1, 0xe1, 0xa8,
++0x00, 0x36, 0xa6, 0x90, 0x48, 0x80, 0xe1, 0xe1, 0xa7, 0xc0, 0x36, 0xa4,
++0x80, 0xe1, 0xe1, 0xa7, 0x80, 0x36, 0xa2, 0x90, 0x90, 0x90, 0x48, 0x80,
++0xe1, 0xe1, 0x8f, 0x80, 0x36, 0x3a, 0x80, 0xe1, 0xe1, 0x8f, 0x40, 0x36,
++0x43, 0x90, 0x48, 0x80, 0xe1, 0xe1, 0x8f, 0x00, 0x36, 0x41, 0x80, 0xe1,
++0xe1, 0x8e, 0xc0, 0x36, 0x3f, 0x91, 0x50, 0x90, 0xb0, 0x90, 0x58, 0xa4,
++0x1e, 0x38, 0xe1, 0xe1, 0x76, 0xc0, 0x35, 0xd7, 0xa4, 0x1e, 0x48, 0xe1,
++0xe1, 0x76, 0x80, 0x35, 0xe0, 0x90, 0x48, 0x80, 0xe1, 0xe1, 0x76, 0x40,
++0x35, 0xde, 0xa4, 0x1e, 0x40, 0xe1, 0xe1, 0x76, 0x00, 0x35, 0xdc, 0x90,
++0xb0, 0x90, 0x58, 0xa4, 0x1e, 0x08, 0xe1, 0xe1, 0x5e, 0x00, 0x35, 0x74,
++0xa4, 0x1e, 0x18, 0xe1, 0xe1, 0x5d, 0xc0, 0x35, 0x7d, 0x90, 0x48, 0x80,
++0xe1, 0xe1, 0x5d, 0x80, 0x35, 0x7b, 0xa4, 0x1e, 0x10, 0xe1, 0xe1, 0x5d,
++0x40, 0x35, 0x79, 0x92, 0x40, 0x91, 0x20, 0x90, 0x90, 0x90, 0x48, 0x80,
++0xe1, 0xe1, 0xa5, 0x80, 0x36, 0x92, 0x80, 0xe1, 0xe1, 0xa5, 0x40, 0x36,
++0x9b, 0x90, 0x48, 0x80, 0xe1, 0xe1, 0xa5, 0x00, 0x36, 0x99, 0x80, 0xe1,
++0xe1, 0xa4, 0xc0, 0x36, 0x97, 0x90, 0x90, 0x90, 0x48, 0x80, 0xe1, 0xe1,
++0x8c, 0xc0, 0x36, 0x2f, 0x80, 0xe1, 0xe1, 0x8c, 0x80, 0x36, 0x38, 0x90,
++0x48, 0x80, 0xe1, 0xe1, 0x8c, 0x40, 0x36, 0x36, 0x80, 0xe1, 0xe1, 0x8c,
++0x00, 0x36, 0x34, 0x91, 0x50, 0x90, 0xb0, 0x90, 0x58, 0xa4, 0x1e, 0x20,
++0xe1, 0xe1, 0x74, 0x00, 0x35, 0xcc, 0xa4, 0x1e, 0x30, 0xe1, 0xe1, 0x73,
++0xc0, 0x35, 0xd5, 0x90, 0x48, 0x80, 0xe1, 0xe1, 0x73, 0x80, 0x35, 0xd3,
++0xa4, 0x1e, 0x28, 0xe1, 0xe1, 0x73, 0x40, 0x35, 0xd1, 0x90, 0xb0, 0x90,
++0x58, 0xa4, 0x1d, 0xf0, 0xe1, 0xe1, 0x5b, 0x40, 0x35, 0x69, 0xa4, 0x1e,
++0x00, 0xe1, 0xe1, 0x5b, 0x00, 0x35, 0x72, 0x90, 0x48, 0x80, 0xe1, 0xe1,
++0x5a, 0xc0, 0x35, 0x70, 0xa4, 0x1d, 0xf8, 0xe1, 0xe1, 0x5a, 0x80, 0x35,
++0x6e, 0xe4, 0xe2, 0x53, 0x00, 0x39, 0x60, 0x99, 0x50, 0x02, 0x00, 0x10,
++0x10, 0x10, 0x10, 0x90, 0x90, 0x90, 0x48, 0x80, 0xe1, 0xe1, 0x58, 0x80,
++0x35, 0x5e, 0x80, 0xe1, 0xe1, 0x58, 0x40, 0x35, 0x67, 0x90, 0x48, 0x80,
++0xe1, 0xe1, 0x58, 0x00, 0x35, 0x65, 0x80, 0xe1, 0xe1, 0x57, 0xc0, 0x35,
++0x63, 0x90, 0x60, 0x90, 0x30, 0x60, 0xa0, 0xef, 0x40, 0x60, 0xa0, 0xef,
++0x00, 0x90, 0x30, 0x60, 0xa0, 0xee, 0xc0, 0x60, 0xa0, 0xee, 0x80, 0xe4,
++0xe2, 0x2d, 0x00, 0x38, 0xdc, 0xa0, 0x10, 0x98, 0xa0, 0x09, 0xa8, 0x9c,
++0xc0, 0x09, 0x60, 0x92, 0x70, 0x91, 0x50, 0x90, 0xb0, 0x90, 0x58, 0xa4,
++0x1e, 0xe0, 0xe1, 0xe1, 0xa2, 0xc0, 0x36, 0x7c, 0xa4, 0x1f, 0x00, 0xe1,
++0xe1, 0xa2, 0x80, 0x36, 0x90, 0x90, 0x48, 0x80, 0xe1, 0xe1, 0xa2, 0x40,
++0x36, 0x8e, 0xa4, 0x1e, 0xf0, 0xe1, 0xe1, 0xa2, 0x00, 0x36, 0x8c, 0x90,
++0x90, 0x90, 0x48, 0x80, 0xe1, 0xe1, 0x8a, 0x00, 0x36, 0x19, 0x80, 0xe1,
++0xe1, 0x89, 0xc0, 0x36, 0x2d, 0x90, 0x48, 0x80, 0xe1, 0xe1, 0x89, 0x80,
++0x36, 0x2b, 0x80, 0xe1, 0xe1, 0x89, 0x40, 0x36, 0x29, 0x91, 0x20, 0x90,
++0x90, 0x90, 0x48, 0x80, 0xe1, 0xe1, 0x71, 0x40, 0x35, 0xb6, 0x80, 0xe1,
++0xe1, 0x71, 0x00, 0x35, 0xca, 0x90, 0x48, 0x80, 0xe1, 0xe1, 0x70, 0xc0,
++0x35, 0xc8, 0x80, 0xe1, 0xe1, 0x70, 0x80, 0x35, 0xc6, 0x90, 0x90, 0x90,
++0x48, 0x80, 0xe1, 0xe1, 0x55, 0xc0, 0x35, 0x48, 0x80, 0xe1, 0xe1, 0x55,
++0x80, 0x35, 0x5c, 0x90, 0x48, 0x80, 0xe1, 0xe1, 0x55, 0x40, 0x35, 0x5a,
++0x80, 0xe1, 0xe1, 0x55, 0x00, 0x35, 0x58, 0x92, 0x70, 0x91, 0x50, 0x90,
++0xb0, 0x90, 0x58, 0xa4, 0x1e, 0xb0, 0xe1, 0xe1, 0x9d, 0x40, 0x36, 0x71,
++0xa4, 0x1e, 0xd0, 0xe1, 0xe1, 0x9d, 0x00, 0x36, 0x7a, 0x90, 0x48, 0x80,
++0xe1, 0xe1, 0x9c, 0xc0, 0x36, 0x78, 0xa4, 0x1e, 0xc0, 0xe1, 0xe1, 0x9c,
++0x80, 0x36, 0x76, 0x90, 0x90, 0x90, 0x48, 0x80, 0xe1, 0xe1, 0x84, 0x80,
++0x36, 0x0e, 0x80, 0xe1, 0xe1, 0x84, 0x40, 0x36, 0x17, 0x90, 0x48, 0x80,
++0xe1, 0xe1, 0x84, 0x00, 0x36, 0x15, 0x80, 0xe1, 0xe1, 0x83, 0xc0, 0x36,
++0x13, 0x91, 0x20, 0x90, 0x90, 0x90, 0x48, 0x80, 0xe1, 0xe1, 0x6b, 0xc0,
++0x35, 0xab, 0x80, 0xe1, 0xe1, 0x6b, 0x80, 0x35, 0xb4, 0x90, 0x48, 0x80,
++0xe1, 0xe1, 0x6b, 0x40, 0x35, 0xb2, 0x80, 0xe1, 0xe1, 0x6b, 0x00, 0x35,
++0xb0, 0x90, 0x90, 0x90, 0x48, 0x80, 0xe1, 0xe1, 0x50, 0x40, 0x35, 0x3d,
++0x80, 0xe1, 0xe1, 0x50, 0x00, 0x35, 0x46, 0x90, 0x48, 0x80, 0xe1, 0xe1,
++0x4f, 0xc0, 0x35, 0x44, 0x80, 0xe1, 0xe1, 0x4f, 0x80, 0x35, 0x42, 0xe4,
++0xe2, 0x52, 0x00, 0x39, 0x5c, 0x9d, 0x70, 0x06, 0xa8, 0x93, 0x20, 0x92,
++0x00, 0x91, 0x00, 0x90, 0x80, 0x90, 0x40, 0xe1, 0xe1, 0xa0, 0x40, 0x36,
++0x7d, 0xe1, 0xe1, 0x4b, 0x40, 0x35, 0x3b, 0x90, 0x40, 0xe1, 0xe1, 0xa0,
++0x00, 0x36, 0x86, 0xe1, 0xe1, 0x4a, 0xc0, 0x35, 0x37, 0x90, 0x80, 0x90,
++0x40, 0xe1, 0xe1, 0x9f, 0xc0, 0x36, 0x84, 0xe1, 0xe1, 0x4a, 0x40, 0x35,
++0x33, 0x90, 0x40, 0xe1, 0xe1, 0x9f, 0x80, 0x36, 0x82, 0xe1, 0xe1, 0x49,
++0xc0, 0x35, 0x2f, 0x90, 0x90, 0x90, 0x48, 0x80, 0xe1, 0xe1, 0x87, 0x80,
++0x36, 0x1a, 0x80, 0xe1, 0xe1, 0x87, 0x40, 0x36, 0x23, 0x90, 0x48, 0x80,
++0xe1, 0xe1, 0x87, 0x00, 0x36, 0x21, 0x80, 0xe1, 0xe1, 0x86, 0xc0, 0x36,
++0x1f, 0x91, 0x20, 0x90, 0x90, 0x90, 0x48, 0x80, 0xe1, 0xe1, 0x6e, 0xc0,
++0x35, 0xb7, 0x80, 0xe1, 0xe1, 0x6e, 0x80, 0x35, 0xc0, 0x90, 0x48, 0x80,
++0xe1, 0xe1, 0x6e, 0x40, 0x35, 0xbe, 0x80, 0xe1, 0xe1, 0x6e, 0x00, 0x35,
++0xbc, 0x90, 0x90, 0x90, 0x48, 0x80, 0xe1, 0xe1, 0x53, 0x40, 0x35, 0x49,
++0x80, 0xe1, 0xe1, 0x53, 0x00, 0x35, 0x52, 0x90, 0x48, 0x80, 0xe1, 0xe1,
++0x52, 0xc0, 0x35, 0x50, 0x80, 0xe1, 0xe1, 0x52, 0x80, 0x35, 0x4e, 0x81,
++0x90, 0xa0, 0x90, 0x50, 0x10, 0x10, 0xe1, 0xe1, 0x46, 0x40, 0x35, 0x11,
++0x10, 0x10, 0xe1, 0xe1, 0x45, 0xc0, 0x35, 0x23, 0x90, 0x50, 0x10, 0x10,
++0xe1, 0xe1, 0x45, 0x40, 0x35, 0x1f, 0x10, 0x10, 0xe1, 0xe1, 0x44, 0xc0,
++0x35, 0x1b, 0xe4, 0xe2, 0x2b, 0x00, 0x38, 0xd4, 0xa0, 0x0b, 0x08, 0x9d,
++0x70, 0x0a, 0xc0, 0x93, 0x20, 0x92, 0x00, 0x91, 0x00, 0x90, 0x80, 0x90,
++0x40, 0xe3, 0xa1, 0x26, 0x40, 0x34, 0xa0, 0xe3, 0xa1, 0x0b, 0x80, 0x34,
++0x3c, 0x90, 0x40, 0xe3, 0xa1, 0x26, 0x00, 0x34, 0x9e, 0xe3, 0xa1, 0x0b,
++0x00, 0x34, 0x38, 0x90, 0x80, 0x90, 0x40, 0xe3, 0xa1, 0x25, 0xc0, 0x34,
++0x9c, 0xe3, 0xa1, 0x0a, 0x80, 0x34, 0x34, 0x90, 0x40, 0xe3, 0xa1, 0x25,
++0x80, 0x34, 0x9a, 0xe3, 0xa1, 0x0a, 0x00, 0x34, 0x30, 0x90, 0x90, 0x90,
++0x48, 0x80, 0xe3, 0xa1, 0x20, 0xc0, 0x34, 0x8a, 0x80, 0xe3, 0xa1, 0x20,
++0x80, 0x34, 0x88, 0x90, 0x48, 0x80, 0xe3, 0xa1, 0x20, 0x40, 0x34, 0x86,
++0x80, 0xe3, 0xa1, 0x20, 0x00, 0x34, 0x84, 0x91, 0x20, 0x90, 0x90, 0x90,
++0x48, 0x80, 0xe3, 0xa1, 0x1b, 0x40, 0x34, 0x74, 0x80, 0xe3, 0xa1, 0x1b,
++0x00, 0x34, 0x72, 0x90, 0x48, 0x80, 0xe3, 0xa1, 0x1a, 0xc0, 0x34, 0x70,
++0x80, 0xe3, 0xa1, 0x1a, 0x80, 0x34, 0x6e, 0x90, 0x90, 0x90, 0x48, 0x80,
++0xe3, 0xa1, 0x15, 0xc0, 0x34, 0x5e, 0x80, 0xe3, 0xa1, 0x15, 0x80, 0x34,
++0x5c, 0x90, 0x48, 0x80, 0xe3, 0xa1, 0x15, 0x40, 0x34, 0x5a, 0x80, 0xe3,
++0xa1, 0x15, 0x00, 0x34, 0x58, 0x93, 0x20, 0x92, 0x00, 0x91, 0x00, 0x90,
++0x80, 0x90, 0x40, 0xe3, 0xa1, 0x23, 0xc0, 0x34, 0x8b, 0xe3, 0xa1, 0x06,
++0x80, 0x34, 0x12, 0x90, 0x40, 0xe3, 0xa1, 0x23, 0x80, 0x34, 0x94, 0xe3,
++0xa1, 0x06, 0x00, 0x34, 0x24, 0x90, 0x80, 0x90, 0x40, 0xe3, 0xa1, 0x23,
++0x40, 0x34, 0x92, 0xe3, 0xa1, 0x05, 0x80, 0x34, 0x20, 0x90, 0x40, 0xe3,
++0xa1, 0x23, 0x00, 0x34, 0x90, 0xe3, 0xa1, 0x05, 0x00, 0x34, 0x1c, 0x90,
++0x90, 0x90, 0x48, 0x80, 0xe3, 0xa1, 0x1e, 0x40, 0x34, 0x75, 0x80, 0xe3,
++0xa1, 0x1e, 0x00, 0x34, 0x7e, 0x90, 0x48, 0x80, 0xe3, 0xa1, 0x1d, 0xc0,
++0x34, 0x7c, 0x80, 0xe3, 0xa1, 0x1d, 0x80, 0x34, 0x7a, 0x91, 0x20, 0x90,
++0x90, 0x90, 0x48, 0x80, 0xe3, 0xa1, 0x18, 0xc0, 0x34, 0x5f, 0x80, 0xe3,
++0xa1, 0x18, 0x80, 0x34, 0x68, 0x90, 0x48, 0x80, 0xe3, 0xa1, 0x18, 0x40,
++0x34, 0x66, 0x80, 0xe3, 0xa1, 0x18, 0x00, 0x34, 0x64, 0x90, 0x90, 0x90,
++0x48, 0x80, 0xe3, 0xa1, 0x13, 0x40, 0x34, 0x49, 0x80, 0xe3, 0xa1, 0x13,
++0x00, 0x34, 0x52, 0x90, 0x48, 0x80, 0xe3, 0xa1, 0x12, 0xc0, 0x34, 0x50,
++0x80, 0xe3, 0xa1, 0x12, 0x80, 0x34, 0x4e, 0xe4, 0xe2, 0x51, 0x00, 0x39,
++0x58, 0x88, 0x01, 0x48, 0x10, 0x10, 0x10, 0x10, 0x90, 0x90, 0x90, 0x48,
++0x80, 0xe3, 0xa1, 0x10, 0x80, 0x34, 0x3e, 0x80, 0xe3, 0xa1, 0x10, 0x40,
++0x34, 0x47, 0x90, 0x48, 0x80, 0xe3, 0xa1, 0x10, 0x00, 0x34, 0x45, 0x80,
++0xe3, 0xa1, 0x0f, 0xc0, 0x34, 0x43, 0xe4, 0xe2, 0x29, 0x00, 0x38, 0xcc,
++0xa0, 0x0e, 0x80, 0xa0, 0x09, 0x08, 0x94, 0x80, 0x9a, 0x30, 0x04, 0x40,
++0x91, 0x10, 0x90, 0x88, 0x90, 0x50, 0x90, 0x28, 0x80, 0x35, 0x0f, 0x80,
++0x35, 0x0e, 0x10, 0x10, 0x80, 0x35, 0x0d, 0x90, 0x50, 0x90, 0x28, 0x80,
++0x34, 0xf4, 0x80, 0x34, 0xf3, 0x10, 0x10, 0x80, 0x34, 0xf2, 0x90, 0x88,
++0x90, 0x50, 0x90, 0x28, 0x80, 0x34, 0xd9, 0x80, 0x34, 0xd8, 0x10, 0x10,
++0x80, 0x34, 0xd7, 0x90, 0x50, 0x90, 0x28, 0x80, 0x34, 0xbe, 0x80, 0x34,
++0xbd, 0x10, 0x10, 0x80, 0x34, 0xbc, 0x91, 0x10, 0x90, 0x88, 0x90, 0x50,
++0x90, 0x28, 0x80, 0x35, 0x0a, 0x80, 0x35, 0x0c, 0x10, 0x10, 0x80, 0x35,
++0x0b, 0x90, 0x50, 0x90, 0x28, 0x80, 0x34, 0xef, 0x80, 0x34, 0xf1, 0x10,
++0x10, 0x80, 0x34, 0xf0, 0x90, 0x88, 0x90, 0x50, 0x90, 0x28, 0x80, 0x34,
++0xd4, 0x80, 0x34, 0xd6, 0x10, 0x10, 0x80, 0x34, 0xd5, 0x90, 0x50, 0x90,
++0x28, 0x80, 0x34, 0xb9, 0x80, 0x34, 0xbb, 0x10, 0x10, 0x80, 0x34, 0xba,
++0xe4, 0xe2, 0x43, 0x00, 0x39, 0x34, 0x9a, 0x30, 0x04, 0x40, 0x91, 0x10,
++0x90, 0x88, 0x90, 0x50, 0x90, 0x28, 0x80, 0x35, 0x07, 0x80, 0x35, 0x09,
++0x10, 0x10, 0x80, 0x35, 0x08, 0x90, 0x50, 0x90, 0x28, 0x80, 0x34, 0xec,
++0x80, 0x34, 0xee, 0x10, 0x10, 0x80, 0x34, 0xed, 0x90, 0x88, 0x90, 0x50,
++0x90, 0x28, 0x80, 0x34, 0xd1, 0x80, 0x34, 0xd3, 0x10, 0x10, 0x80, 0x34,
++0xd2, 0x90, 0x50, 0x90, 0x28, 0x80, 0x34, 0xb6, 0x80, 0x34, 0xb8, 0x10,
++0x10, 0x80, 0x34, 0xb7, 0x91, 0x10, 0x90, 0x88, 0x90, 0x50, 0x90, 0x28,
++0x80, 0x35, 0x04, 0x80, 0x35, 0x06, 0x10, 0x10, 0x80, 0x35, 0x05, 0x90,
++0x50, 0x90, 0x28, 0x80, 0x34, 0xe9, 0x80, 0x34, 0xeb, 0x10, 0x10, 0x80,
++0x34, 0xea, 0x90, 0x88, 0x90, 0x50, 0x90, 0x28, 0x80, 0x34, 0xce, 0x80,
++0x34, 0xd0, 0x10, 0x10, 0x80, 0x34, 0xcf, 0x90, 0x50, 0x90, 0x28, 0x80,
++0x34, 0xb3, 0x80, 0x34, 0xb5, 0x10, 0x10, 0x80, 0x34, 0xb4, 0xe4, 0xe2,
++0x22, 0x00, 0x38, 0x9c, 0x94, 0x80, 0x9a, 0x30, 0x04, 0x40, 0x91, 0x10,
++0x90, 0x88, 0x90, 0x50, 0x90, 0x28, 0x80, 0x35, 0x01, 0x80, 0x35, 0x03,
++0x10, 0x10, 0x80, 0x35, 0x02, 0x90, 0x50, 0x90, 0x28, 0x80, 0x34, 0xe6,
++0x80, 0x34, 0xe8, 0x10, 0x10, 0x80, 0x34, 0xe7, 0x90, 0x88, 0x90, 0x50,
++0x90, 0x28, 0x80, 0x34, 0xcb, 0x80, 0x34, 0xcd, 0x10, 0x10, 0x80, 0x34,
++0xcc, 0x90, 0x50, 0x90, 0x28, 0x80, 0x34, 0xb0, 0x80, 0x34, 0xb2, 0x10,
++0x10, 0x80, 0x34, 0xb1, 0x91, 0x10, 0x90, 0x88, 0x90, 0x50, 0x90, 0x28,
++0x80, 0x34, 0xfe, 0x80, 0x35, 0x00, 0x10, 0x10, 0x80, 0x34, 0xff, 0x90,
++0x50, 0x90, 0x28, 0x80, 0x34, 0xe3, 0x80, 0x34, 0xe5, 0x10, 0x10, 0x80,
++0x34, 0xe4, 0x90, 0x88, 0x90, 0x50, 0x90, 0x28, 0x80, 0x34, 0xc8, 0x80,
++0x34, 0xca, 0x10, 0x10, 0x80, 0x34, 0xc9, 0x90, 0x50, 0x90, 0x28, 0x80,
++0x34, 0xad, 0x80, 0x34, 0xaf, 0x10, 0x10, 0x80, 0x34, 0xae, 0xe4, 0xe2,
++0x41, 0x00, 0x39, 0x2c, 0x88, 0x00, 0xb0, 0x10, 0x10, 0x10, 0x10, 0x90,
++0x50, 0x90, 0x28, 0x80, 0x34, 0xaa, 0x80, 0x34, 0xac, 0x10, 0x10, 0x80,
++0x34, 0xab, 0xe4, 0xe2, 0x21, 0x00, 0x38, 0x98, 0x96, 0xe8, 0x94, 0x80,
++0x9a, 0x30, 0x04, 0x40, 0x91, 0x10, 0x90, 0x88, 0x90, 0x50, 0x90, 0x28,
++0x80, 0x34, 0xf8, 0x80, 0x34, 0xfd, 0x10, 0x10, 0x80, 0x34, 0xfc, 0x90,
++0x50, 0x90, 0x28, 0x80, 0x34, 0xdd, 0x80, 0x34, 0xe2, 0x10, 0x10, 0x80,
++0x34, 0xe1, 0x90, 0x88, 0x90, 0x50, 0x90, 0x28, 0x80, 0x34, 0xc2, 0x80,
++0x34, 0xc7, 0x10, 0x10, 0x80, 0x34, 0xc6, 0x90, 0x50, 0x90, 0x28, 0x80,
++0x34, 0xa4, 0x80, 0x34, 0xa9, 0x10, 0x10, 0x80, 0x34, 0xa8, 0x91, 0x10,
++0x90, 0x88, 0x90, 0x50, 0x90, 0x28, 0x80, 0x34, 0xf5, 0x80, 0x34, 0xf7,
++0x10, 0x10, 0x80, 0x34, 0xf6, 0x90, 0x50, 0x90, 0x28, 0x80, 0x34, 0xda,
++0x80, 0x34, 0xdc, 0x10, 0x10, 0x80, 0x34, 0xdb, 0x90, 0x88, 0x90, 0x50,
++0x90, 0x28, 0x80, 0x34, 0xbf, 0x80, 0x34, 0xc1, 0x10, 0x10, 0x80, 0x34,
++0xc0, 0x90, 0x50, 0x90, 0x28, 0x80, 0x34, 0xa1, 0x80, 0x34, 0xa3, 0x10,
++0x10, 0x80, 0x34, 0xa2, 0xe4, 0xe2, 0x3f, 0x00, 0x39, 0x24, 0x88, 0x02,
++0x28, 0x91, 0x10, 0x90, 0x88, 0x90, 0x50, 0x90, 0x28, 0x80, 0x34, 0xf9,
++0x80, 0x34, 0xfb, 0x10, 0x10, 0x80, 0x34, 0xfa, 0x90, 0x50, 0x90, 0x28,
++0x80, 0x34, 0xde, 0x80, 0x34, 0xe0, 0x10, 0x10, 0x80, 0x34, 0xdf, 0x90,
++0x88, 0x90, 0x50, 0x90, 0x28, 0x80, 0x34, 0xc3, 0x80, 0x34, 0xc5, 0x10,
++0x10, 0x80, 0x34, 0xc4, 0x90, 0x50, 0x90, 0x28, 0x80, 0x34, 0xa5, 0x80,
++0x34, 0xa7, 0x10, 0x10, 0x80, 0x34, 0xa6, 0xe4, 0xe2, 0x20, 0x00, 0x38,
++0x94, 0x90, 0x40, 0xe5, 0x22, 0x3d, 0x00, 0x39, 0x1c, 0xe5, 0x22, 0x1f,
++0x00, 0x38, 0x90, 0x9e, 0xb4, 0x3d, 0x08, 0x93, 0x70, 0x91, 0xd8, 0xd5,
++0x07, 0x80, 0xd0, 0xc4, 0x40, 0x90, 0x48, 0x80, 0x8c, 0x58, 0x50, 0x84,
++0x3b, 0x14, 0xa4, 0x56, 0x30, 0x3a, 0xde, 0x90, 0x28, 0x24, 0x55, 0x70,
++0xa4, 0x53, 0xf0, 0x3a, 0x96, 0xd0, 0xc4, 0x40, 0x90, 0x48, 0x80, 0x8c,
++0x58, 0x30, 0x84, 0x3b, 0x12, 0xa4, 0x56, 0x20, 0x3a, 0xdc, 0x90, 0x28,
++0x24, 0x55, 0x60, 0xa4, 0x53, 0xe0, 0x3a, 0x94, 0xd5, 0x06, 0x80, 0xd0,
++0xc3, 0x40, 0x90, 0x28, 0x80, 0x3a, 0xfe, 0xa4, 0x56, 0x00, 0x3a, 0xd8,
++0x90, 0x28, 0x24, 0x55, 0x40, 0xa4, 0x53, 0xc0, 0x3a, 0x90, 0xd0, 0xc3,
++0x40, 0x90, 0x28, 0x80, 0x3a, 0xfa, 0xa4, 0x55, 0xf0, 0x3a, 0xd6, 0x90,
++0x28, 0x24, 0x55, 0x30, 0xa4, 0x53, 0xb0, 0x3a, 0x8e, 0x91, 0x98, 0xd5,
++0x06, 0x80, 0xd0, 0xc3, 0x40, 0x90, 0x28, 0x80, 0x3a, 0xf2, 0xa4, 0x55,
++0xd0, 0x3a, 0xd2, 0x90, 0x28, 0x24, 0x55, 0x10, 0xa4, 0x53, 0x90, 0x3a,
++0x8a, 0xd0, 0xc3, 0x40, 0x90, 0x28, 0x80, 0x3a, 0xee, 0xa4, 0x55, 0xc0,
++0x3a, 0xd0, 0x90, 0x28, 0x24, 0x55, 0x00, 0xa4, 0x53, 0x80, 0x3a, 0x88,
++0xd5, 0x06, 0x80, 0xd0, 0xc3, 0x40, 0x90, 0x28, 0x80, 0x3a, 0xe6, 0xa4,
++0x55, 0xa0, 0x3a, 0xcc, 0x90, 0x28, 0x24, 0x54, 0xe0, 0xa4, 0x53, 0x60,
++0x3a, 0x84, 0xd0, 0xc3, 0x40, 0x90, 0x28, 0x80, 0x3a, 0xe2, 0xa4, 0x55,
++0x90, 0x3a, 0xca, 0x90, 0x28, 0x24, 0x54, 0xd0, 0xa4, 0x53, 0x50, 0x3a,
++0x82, 0x93, 0x70, 0x91, 0xd8, 0xd5, 0x07, 0x80, 0xd0, 0xc4, 0x40, 0x90,
++0x48, 0x80, 0x8c, 0x58, 0x70, 0x84, 0x3b, 0x16, 0xa4, 0x56, 0x40, 0x3a,
++0xe0, 0x90, 0x28, 0x24, 0x55, 0x80, 0xa4, 0x54, 0x00, 0x3a, 0x98, 0xd0,
++0xc4, 0x40, 0x90, 0x48, 0x80, 0x8c, 0x58, 0x40, 0x84, 0x3b, 0x13, 0xa4,
++0x56, 0x28, 0x3a, 0xdd, 0x90, 0x28, 0x24, 0x55, 0x68, 0xa4, 0x53, 0xe8,
++0x3a, 0x95, 0xd5, 0x06, 0x80, 0xd0, 0xc3, 0x40, 0x90, 0x28, 0x80, 0x3b,
++0x02, 0xa4, 0x56, 0x10, 0x3a, 0xda, 0x90, 0x28, 0x24, 0x55, 0x50, 0xa4,
++0x53, 0xd0, 0x3a, 0x92, 0xd0, 0xc3, 0x40, 0x90, 0x28, 0x80, 0x3a, 0xfc,
++0xa4, 0x55, 0xf8, 0x3a, 0xd7, 0x90, 0x28, 0x24, 0x55, 0x38, 0xa4, 0x53,
++0xb8, 0x3a, 0x8f, 0x91, 0x98, 0xd5, 0x06, 0x80, 0xd0, 0xc3, 0x40, 0x90,
++0x28, 0x80, 0x3a, 0xf6, 0xa4, 0x55, 0xe0, 0x3a, 0xd4, 0x90, 0x28, 0x24,
++0x55, 0x20, 0xa4, 0x53, 0xa0, 0x3a, 0x8c, 0xd0, 0xc3, 0x40, 0x90, 0x28,
++0x80, 0x3a, 0xf0, 0xa4, 0x55, 0xc8, 0x3a, 0xd1, 0x90, 0x28, 0x24, 0x55,
++0x08, 0xa4, 0x53, 0x88, 0x3a, 0x89, 0xd5, 0x06, 0x80, 0xd0, 0xc3, 0x40,
++0x90, 0x28, 0x80, 0x3a, 0xea, 0xa4, 0x55, 0xb0, 0x3a, 0xce, 0x90, 0x28,
++0x24, 0x54, 0xf0, 0xa4, 0x53, 0x70, 0x3a, 0x86, 0xd0, 0xc3, 0x40, 0x90,
++0x28, 0x80, 0x3a, 0xe4, 0xa4, 0x55, 0x98, 0x3a, 0xcb, 0x90, 0x28, 0x24,
++0x54, 0xd8, 0xa4, 0x53, 0x58, 0x3a, 0x83, 0x99, 0xd8, 0x03, 0x90, 0x81,
++0x90, 0xe0, 0x5b, 0x41, 0x40, 0x03, 0x40, 0x51, 0x40, 0xc0, 0xa4, 0x3c,
++0xa0, 0x37, 0x84, 0xd1, 0x42, 0x00, 0xa4, 0x3b, 0xa0, 0x37, 0x64, 0xa4,
++0x3a, 0xa0, 0x37, 0x44, 0x5b, 0x41, 0x40, 0x03, 0x40, 0x51, 0x40, 0xc0,
++0xa4, 0x3b, 0xc0, 0x37, 0x88, 0xd1, 0x42, 0x00, 0xa4, 0x3a, 0xc0, 0x37,
++0x68, 0xa4, 0x39, 0xc0, 0x37, 0x48, 0x81, 0x90, 0xe0, 0x5b, 0x41, 0x40,
++0x03, 0x40, 0x51, 0x40, 0xc0, 0xa4, 0x3c, 0x00, 0x37, 0x90, 0xd1, 0x42,
++0x00, 0xa4, 0x3b, 0x00, 0x37, 0x70, 0xa4, 0x3a, 0x00, 0x37, 0x50, 0x5b,
++0x41, 0x40, 0x03, 0x40, 0x51, 0x40, 0xc0, 0xa4, 0x3b, 0xe0, 0x37, 0x8c,
++0xd1, 0x42, 0x00, 0xa4, 0x3a, 0xe0, 0x37, 0x6c, 0xa4, 0x39, 0xe0, 0x37,
++0x4c, 0xa8, 0x0b, 0x18, 0x13, 0xa8, 0x96, 0x80, 0x93, 0x40, 0x99, 0x90,
++0x03, 0x00, 0x90, 0xc0, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x1d, 0xc0, 0x33,
++0xb9, 0x24, 0x1d, 0xb8, 0x90, 0x38, 0xa4, 0x1c, 0xe8, 0x33, 0x9e, 0x24,
++0x1c, 0xe0, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x1c, 0x10, 0x33, 0x83, 0x24,
++0x1c, 0x08, 0x90, 0x38, 0xa4, 0x1b, 0x38, 0x33, 0x68, 0x24, 0x1b, 0x30,
++0x90, 0xc0, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x1d, 0xb0, 0x33, 0xb4, 0x24,
++0x1d, 0xa8, 0x90, 0x38, 0xa4, 0x1c, 0xd8, 0x33, 0x99, 0x24, 0x1c, 0xd0,
++0x90, 0x60, 0x90, 0x38, 0xa4, 0x1c, 0x00, 0x33, 0x7e, 0x24, 0x1b, 0xf8,
++0x90, 0x38, 0xa4, 0x1b, 0x28, 0x33, 0x63, 0x24, 0x1b, 0x20, 0xe4, 0xe2,
++0x99, 0x00, 0x3a, 0x66, 0x99, 0x90, 0x03, 0x00, 0x90, 0xc0, 0x90, 0x60,
++0x90, 0x38, 0xa4, 0x1d, 0x98, 0x33, 0xb1, 0x24, 0x1d, 0x90, 0x90, 0x38,
++0xa4, 0x1c, 0xc0, 0x33, 0x96, 0x24, 0x1c, 0xb8, 0x90, 0x60, 0x90, 0x38,
++0xa4, 0x1b, 0xe8, 0x33, 0x7b, 0x24, 0x1b, 0xe0, 0x90, 0x38, 0xa4, 0x1b,
++0x10, 0x33, 0x60, 0x24, 0x1b, 0x08, 0x90, 0xc0, 0x90, 0x60, 0x90, 0x38,
++0xa4, 0x1d, 0x80, 0x33, 0xae, 0x24, 0x1d, 0x78, 0x90, 0x38, 0xa4, 0x1c,
++0xa8, 0x33, 0x93, 0x24, 0x1c, 0xa0, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x1b,
++0xd0, 0x33, 0x78, 0x24, 0x1b, 0xc8, 0x90, 0x38, 0xa4, 0x1a, 0xf8, 0x33,
++0x5d, 0x24, 0x1a, 0xf0, 0xe4, 0xe2, 0x97, 0x80, 0x3a, 0x60, 0x93, 0x78,
++0x99, 0x90, 0x03, 0x00, 0x90, 0xc0, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x1d,
++0x68, 0x33, 0xab, 0x24, 0x1d, 0x60, 0x90, 0x38, 0xa4, 0x1c, 0x90, 0x33,
++0x90, 0x24, 0x1c, 0x88, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x1b, 0xb8, 0x33,
++0x75, 0x24, 0x1b, 0xb0, 0x90, 0x38, 0xa4, 0x1a, 0xe0, 0x33, 0x5a, 0x24,
++0x1a, 0xd8, 0x90, 0xc0, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x1d, 0x50, 0x33,
++0xa8, 0x24, 0x1d, 0x48, 0x90, 0x38, 0xa4, 0x1c, 0x78, 0x33, 0x8d, 0x24,
++0x1c, 0x70, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x1b, 0xa0, 0x33, 0x72, 0x24,
++0x1b, 0x98, 0x90, 0x38, 0xa4, 0x1a, 0xc8, 0x33, 0x57, 0x24, 0x1a, 0xc0,
++0xec, 0xa1, 0xe7, 0x00, 0x02, 0x00, 0x37, 0x9e, 0xa4, 0x52, 0xc0, 0x3a,
++0x5a, 0x88, 0x00, 0x88, 0x10, 0x10, 0x10, 0x10, 0x90, 0x38, 0xa4, 0x1a,
++0xb0, 0x33, 0x54, 0x24, 0x1a, 0xa8, 0xe9, 0x61, 0xe6, 0x40, 0x02, 0x00,
++0x37, 0x9a, 0xe3, 0x62, 0x94, 0x80, 0x3a, 0x54, 0x95, 0x08, 0x93, 0x40,
++0x99, 0x90, 0x03, 0x00, 0x90, 0xc0, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x1d,
++0x38, 0x33, 0xa2, 0x24, 0x1d, 0x30, 0x90, 0x38, 0xa4, 0x1c, 0x60, 0x33,
++0x87, 0x24, 0x1c, 0x58, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x1b, 0x88, 0x33,
++0x6c, 0x24, 0x1b, 0x80, 0x90, 0x38, 0xa4, 0x1a, 0x98, 0x33, 0x4e, 0x24,
++0x1a, 0x90, 0x90, 0xc0, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x1d, 0x08, 0x33,
++0x9f, 0x24, 0x1d, 0x00, 0x90, 0x38, 0xa4, 0x1c, 0x30, 0x33, 0x84, 0x24,
++0x1c, 0x28, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x1b, 0x58, 0x33, 0x69, 0x24,
++0x1b, 0x50, 0x90, 0x38, 0xa4, 0x1a, 0x68, 0x33, 0x4b, 0x24, 0x1a, 0x60,
++0xe4, 0xe2, 0x99, 0x40, 0x3a, 0x68, 0x88, 0x01, 0x88, 0x90, 0xc0, 0x90,
++0x60, 0x90, 0x38, 0xa4, 0x1d, 0x28, 0x33, 0xa3, 0x24, 0x1d, 0x20, 0x90,
++0x38, 0xa4, 0x1c, 0x50, 0x33, 0x88, 0x24, 0x1c, 0x48, 0x90, 0x60, 0x90,
++0x38, 0xa4, 0x1b, 0x78, 0x33, 0x6d, 0x24, 0x1b, 0x70, 0x90, 0x38, 0xa4,
++0x1a, 0x88, 0x33, 0x4f, 0x24, 0x1a, 0x80, 0xe4, 0xe2, 0x97, 0xc0, 0x3a,
++0x62, 0x92, 0xd0, 0x99, 0x50, 0x02, 0x80, 0x90, 0xa0, 0x90, 0x50, 0x90,
++0x28, 0x80, 0x33, 0x4a, 0x24, 0x1a, 0x48, 0x90, 0x28, 0x80, 0x33, 0x46,
++0x24, 0x1a, 0x28, 0x90, 0x50, 0x90, 0x28, 0x80, 0x33, 0x42, 0x24, 0x1a,
++0x08, 0x90, 0x28, 0x80, 0x33, 0x3e, 0x24, 0x19, 0xe8, 0x90, 0xa0, 0x90,
++0x50, 0x90, 0x28, 0x80, 0x33, 0x47, 0x24, 0x1a, 0x40, 0x90, 0x28, 0x80,
++0x33, 0x43, 0x24, 0x1a, 0x20, 0x90, 0x50, 0x90, 0x28, 0x80, 0x33, 0x3f,
++0x24, 0x1a, 0x00, 0x90, 0x28, 0x80, 0x33, 0x3b, 0x24, 0x19, 0xe0, 0xec,
++0xe2, 0x96, 0x61, 0xe8, 0x00, 0x3a, 0x5c, 0x88, 0x00, 0x78, 0x10, 0x10,
++0x10, 0x10, 0x90, 0x28, 0x80, 0x33, 0x39, 0x24, 0x19, 0xd0, 0xec, 0xe2,
++0x94, 0xe1, 0xe6, 0x00, 0x3a, 0x56, 0xe5, 0xa2, 0x1e, 0x00, 0x38, 0x74,
++0xa0, 0x41, 0xe0, 0xa8, 0x2c, 0x30, 0x41, 0xa8, 0xa0, 0x16, 0x68, 0xa0,
++0x14, 0x50, 0xa0, 0x0a, 0x28, 0x95, 0x10, 0x92, 0x70, 0x91, 0x20, 0x90,
++0x90, 0x90, 0x48, 0x80, 0xe1, 0xe0, 0x9a, 0xc0, 0x32, 0x72, 0x80, 0xe1,
++0xe0, 0x9a, 0x80, 0x32, 0x70, 0x90, 0x48, 0x80, 0xe1, 0xe0, 0x9a, 0x40,
++0x32, 0x6e, 0x80, 0xe1, 0xe0, 0x9a, 0x00, 0x32, 0x6c, 0x90, 0xb0, 0x90,
++0x58, 0xa4, 0x0b, 0xf8, 0xe1, 0xe0, 0xab, 0x40, 0x32, 0xb4, 0xa4, 0x0b,
++0xf0, 0xe1, 0xe0, 0xab, 0x00, 0x32, 0xb2, 0x90, 0x48, 0x80, 0xe1, 0xe0,
++0xaa, 0xc0, 0x32, 0xb0, 0xa4, 0x0b, 0xe8, 0xe1, 0xe0, 0xaa, 0x80, 0x32,
++0xae, 0x91, 0x50, 0x90, 0xb0, 0x90, 0x58, 0xa4, 0x0d, 0x18, 0xe1, 0xe0,
++0xcc, 0x40, 0x33, 0x38, 0xa4, 0x0d, 0x10, 0xe1, 0xe0, 0xcc, 0x00, 0x33,
++0x36, 0x90, 0x48, 0x80, 0xe1, 0xe0, 0xcb, 0xc0, 0x33, 0x34, 0xa4, 0x0d,
++0x08, 0xe1, 0xe0, 0xcb, 0x80, 0x33, 0x32, 0x90, 0xb0, 0x90, 0x58, 0xa4,
++0x0c, 0x88, 0xe1, 0xe0, 0xbb, 0xc0, 0x32, 0xf6, 0xa4, 0x0c, 0x80, 0xe1,
++0xe0, 0xbb, 0x80, 0x32, 0xf4, 0x90, 0x48, 0x80, 0xe1, 0xe0, 0xbb, 0x40,
++0x32, 0xf2, 0xa4, 0x0c, 0x78, 0xe1, 0xe0, 0xbb, 0x00, 0x32, 0xf0, 0x92,
++0x70, 0x91, 0x20, 0x90, 0x90, 0x90, 0x48, 0x80, 0xe1, 0xe0, 0x98, 0x40,
++0x32, 0x5d, 0x80, 0xe1, 0xe0, 0x98, 0x00, 0x32, 0x66, 0x90, 0x48, 0x80,
++0xe1, 0xe0, 0x97, 0xc0, 0x32, 0x64, 0x80, 0xe1, 0xe0, 0x97, 0x80, 0x32,
++0x62, 0x90, 0xb0, 0x90, 0x58, 0xa4, 0x0b, 0xd0, 0xe1, 0xe0, 0xa8, 0xc0,
++0x32, 0x9f, 0xa4, 0x0b, 0xe0, 0xe1, 0xe0, 0xa8, 0x80, 0x32, 0xa8, 0x90,
++0x48, 0x80, 0xe1, 0xe0, 0xa8, 0x40, 0x32, 0xa6, 0xa4, 0x0b, 0xd8, 0xe1,
++0xe0, 0xa8, 0x00, 0x32, 0xa4, 0x91, 0x50, 0x90, 0xb0, 0x90, 0x58, 0xa4,
++0x0c, 0xf0, 0xe1, 0xe0, 0xc9, 0xc0, 0x33, 0x23, 0xa4, 0x0d, 0x00, 0xe1,
++0xe0, 0xc9, 0x80, 0x33, 0x2c, 0x90, 0x48, 0x80, 0xe1, 0xe0, 0xc9, 0x40,
++0x33, 0x2a, 0xa4, 0x0c, 0xf8, 0xe1, 0xe0, 0xc9, 0x00, 0x33, 0x28, 0x90,
++0xb0, 0x90, 0x58, 0xa4, 0x0c, 0x60, 0xe1, 0xe0, 0xb9, 0x40, 0x32, 0xe1,
++0xa4, 0x0c, 0x70, 0xe1, 0xe0, 0xb9, 0x00, 0x32, 0xea, 0x90, 0x48, 0x80,
++0xe1, 0xe0, 0xb8, 0xc0, 0x32, 0xe8, 0xa4, 0x0c, 0x68, 0xe1, 0xe0, 0xb8,
++0x80, 0x32, 0xe6, 0x95, 0x10, 0x92, 0x70, 0x91, 0x20, 0x90, 0x90, 0x90,
++0x48, 0x80, 0xe1, 0xe0, 0x95, 0x80, 0x32, 0x52, 0x80, 0xe1, 0xe0, 0x95,
++0x40, 0x32, 0x5b, 0x90, 0x48, 0x80, 0xe1, 0xe0, 0x95, 0x00, 0x32, 0x59,
++0x80, 0xe1, 0xe0, 0x94, 0xc0, 0x32, 0x57, 0x90, 0xb0, 0x90, 0x58, 0xa4,
++0x0b, 0xb8, 0xe1, 0xe0, 0xa6, 0x00, 0x32, 0x94, 0xa4, 0x0b, 0xc8, 0xe1,
++0xe0, 0xa5, 0xc0, 0x32, 0x9d, 0x90, 0x48, 0x80, 0xe1, 0xe0, 0xa5, 0x80,
++0x32, 0x9b, 0xa4, 0x0b, 0xc0, 0xe1, 0xe0, 0xa5, 0x40, 0x32, 0x99, 0x91,
++0x50, 0x90, 0xb0, 0x90, 0x58, 0xa4, 0x0c, 0xd8, 0xe1, 0xe0, 0xc7, 0x00,
++0x33, 0x18, 0xa4, 0x0c, 0xe8, 0xe1, 0xe0, 0xc6, 0xc0, 0x33, 0x21, 0x90,
++0x48, 0x80, 0xe1, 0xe0, 0xc6, 0x80, 0x33, 0x1f, 0xa4, 0x0c, 0xe0, 0xe1,
++0xe0, 0xc6, 0x40, 0x33, 0x1d, 0x90, 0xb0, 0x90, 0x58, 0xa4, 0x0c, 0x48,
++0xe1, 0xe0, 0xb6, 0x80, 0x32, 0xd6, 0xa4, 0x0c, 0x58, 0xe1, 0xe0, 0xb6,
++0x40, 0x32, 0xdf, 0x90, 0x48, 0x80, 0xe1, 0xe0, 0xb6, 0x00, 0x32, 0xdd,
++0xa4, 0x0c, 0x50, 0xe1, 0xe0, 0xb5, 0xc0, 0x32, 0xdb, 0x92, 0x70, 0x91,
++0x20, 0x90, 0x90, 0x90, 0x48, 0x80, 0xe1, 0xe0, 0x92, 0xc0, 0x32, 0x47,
++0x80, 0xe1, 0xe0, 0x92, 0x80, 0x32, 0x50, 0x90, 0x48, 0x80, 0xe1, 0xe0,
++0x92, 0x40, 0x32, 0x4e, 0x80, 0xe1, 0xe0, 0x92, 0x00, 0x32, 0x4c, 0x90,
++0xb0, 0x90, 0x58, 0xa4, 0x0b, 0xa0, 0xe1, 0xe0, 0xa3, 0x40, 0x32, 0x89,
++0xa4, 0x0b, 0xb0, 0xe1, 0xe0, 0xa3, 0x00, 0x32, 0x92, 0x90, 0x48, 0x80,
++0xe1, 0xe0, 0xa2, 0xc0, 0x32, 0x90, 0xa4, 0x0b, 0xa8, 0xe1, 0xe0, 0xa2,
++0x80, 0x32, 0x8e, 0x91, 0x50, 0x90, 0xb0, 0x90, 0x58, 0xa4, 0x0c, 0xc0,
++0xe1, 0xe0, 0xc4, 0x40, 0x33, 0x0d, 0xa4, 0x0c, 0xd0, 0xe1, 0xe0, 0xc4,
++0x00, 0x33, 0x16, 0x90, 0x48, 0x80, 0xe1, 0xe0, 0xc3, 0xc0, 0x33, 0x14,
++0xa4, 0x0c, 0xc8, 0xe1, 0xe0, 0xc3, 0x80, 0x33, 0x12, 0x90, 0xb0, 0x90,
++0x58, 0xa4, 0x0c, 0x30, 0xe1, 0xe0, 0xb3, 0xc0, 0x32, 0xcb, 0xa4, 0x0c,
++0x40, 0xe1, 0xe0, 0xb3, 0x80, 0x32, 0xd4, 0x90, 0x48, 0x80, 0xe1, 0xe0,
++0xb3, 0x40, 0x32, 0xd2, 0xa4, 0x0c, 0x38, 0xe1, 0xe0, 0xb3, 0x00, 0x32,
++0xd0, 0x10, 0x10, 0x91, 0x40, 0x10, 0x10, 0x10, 0x10, 0x90, 0x90, 0x90,
++0x48, 0x80, 0xe1, 0xe0, 0x8a, 0x80, 0x32, 0x26, 0x80, 0xe1, 0xe0, 0x8a,
++0x40, 0x32, 0x2f, 0x90, 0x48, 0x80, 0xe1, 0xe0, 0x8a, 0x00, 0x32, 0x2d,
++0x80, 0xe1, 0xe0, 0x89, 0xc0, 0x32, 0x2b, 0x90, 0x60, 0x90, 0x30, 0x60,
++0xa0, 0x32, 0xc0, 0x60, 0xa0, 0x32, 0x80, 0x90, 0x30, 0x60, 0xa0, 0x32,
++0x40, 0x60, 0xa0, 0x32, 0x00, 0xa0, 0x0f, 0xe0, 0xa0, 0x0a, 0x28, 0x95,
++0x10, 0x92, 0x70, 0x91, 0x20, 0x90, 0x90, 0x90, 0x48, 0x80, 0xe1, 0xe0,
++0x90, 0x00, 0x32, 0x3c, 0x80, 0xe1, 0xe0, 0x8f, 0xc0, 0x32, 0x45, 0x90,
++0x48, 0x80, 0xe1, 0xe0, 0x8f, 0x80, 0x32, 0x43, 0x80, 0xe1, 0xe0, 0x8f,
++0x40, 0x32, 0x41, 0x90, 0xb0, 0x90, 0x58, 0xa4, 0x0b, 0x88, 0xe1, 0xe0,
++0xa0, 0x80, 0x32, 0x7e, 0xa4, 0x0b, 0x98, 0xe1, 0xe0, 0xa0, 0x40, 0x32,
++0x87, 0x90, 0x48, 0x80, 0xe1, 0xe0, 0xa0, 0x00, 0x32, 0x85, 0xa4, 0x0b,
++0x90, 0xe1, 0xe0, 0x9f, 0xc0, 0x32, 0x83, 0x91, 0x50, 0x90, 0xb0, 0x90,
++0x58, 0xa4, 0x0c, 0xa8, 0xe1, 0xe0, 0xc1, 0x80, 0x33, 0x02, 0xa4, 0x0c,
++0xb8, 0xe1, 0xe0, 0xc1, 0x40, 0x33, 0x0b, 0x90, 0x48, 0x80, 0xe1, 0xe0,
++0xc1, 0x00, 0x33, 0x09, 0xa4, 0x0c, 0xb0, 0xe1, 0xe0, 0xc0, 0xc0, 0x33,
++0x07, 0x90, 0xb0, 0x90, 0x58, 0xa4, 0x0c, 0x18, 0xe1, 0xe0, 0xb1, 0x00,
++0x32, 0xc0, 0xa4, 0x0c, 0x28, 0xe1, 0xe0, 0xb0, 0xc0, 0x32, 0xc9, 0x90,
++0x48, 0x80, 0xe1, 0xe0, 0xb0, 0x80, 0x32, 0xc7, 0xa4, 0x0c, 0x20, 0xe1,
++0xe0, 0xb0, 0x40, 0x32, 0xc5, 0x92, 0x70, 0x91, 0x20, 0x90, 0x90, 0x90,
++0x48, 0x80, 0xe1, 0xe0, 0x8d, 0x40, 0x32, 0x31, 0x80, 0xe1, 0xe0, 0x8d,
++0x00, 0x32, 0x3a, 0x90, 0x48, 0x80, 0xe1, 0xe0, 0x8c, 0xc0, 0x32, 0x38,
++0x80, 0xe1, 0xe0, 0x8c, 0x80, 0x32, 0x36, 0x90, 0xb0, 0x90, 0x58, 0xa4,
++0x0b, 0x70, 0xe1, 0xe0, 0x9d, 0xc0, 0x32, 0x73, 0xa4, 0x0b, 0x80, 0xe1,
++0xe0, 0x9d, 0x80, 0x32, 0x7c, 0x90, 0x48, 0x80, 0xe1, 0xe0, 0x9d, 0x40,
++0x32, 0x7a, 0xa4, 0x0b, 0x78, 0xe1, 0xe0, 0x9d, 0x00, 0x32, 0x78, 0x91,
++0x50, 0x90, 0xb0, 0x90, 0x58, 0xa4, 0x0c, 0x90, 0xe1, 0xe0, 0xbe, 0xc0,
++0x32, 0xf7, 0xa4, 0x0c, 0xa0, 0xe1, 0xe0, 0xbe, 0x80, 0x33, 0x00, 0x90,
++0x48, 0x80, 0xe1, 0xe0, 0xbe, 0x40, 0x32, 0xfe, 0xa4, 0x0c, 0x98, 0xe1,
++0xe0, 0xbe, 0x00, 0x32, 0xfc, 0x90, 0xb0, 0x90, 0x58, 0xa4, 0x0c, 0x00,
++0xe1, 0xe0, 0xae, 0x40, 0x32, 0xb5, 0xa4, 0x0c, 0x10, 0xe1, 0xe0, 0xae,
++0x00, 0x32, 0xbe, 0x90, 0x48, 0x80, 0xe1, 0xe0, 0xad, 0xc0, 0x32, 0xbc,
++0xa4, 0x0c, 0x08, 0xe1, 0xe0, 0xad, 0x80, 0x32, 0xba, 0x10, 0x10, 0x93,
++0x60, 0x92, 0x40, 0x91, 0x20, 0x90, 0x90, 0x80, 0xd1, 0xc2, 0x40, 0xe1,
++0xa0, 0x4b, 0xc0, 0x31, 0x36, 0xe1, 0xa0, 0x40, 0x40, 0x30, 0xfc, 0x80,
++0xd1, 0xc2, 0x40, 0xe1, 0xa0, 0x4b, 0x80, 0x31, 0x34, 0xe1, 0xa0, 0x40,
++0x00, 0x31, 0x06, 0x90, 0x90, 0x80, 0xd1, 0xc2, 0x40, 0xe1, 0xa0, 0x4b,
++0x40, 0x31, 0x32, 0xe1, 0xa0, 0x3f, 0xc0, 0x31, 0x04, 0x80, 0xd1, 0xc2,
++0x40, 0xe1, 0xa0, 0x4b, 0x00, 0x31, 0x30, 0xe1, 0xa0, 0x3f, 0x80, 0x31,
++0x02, 0x90, 0x90, 0x90, 0x48, 0x80, 0xe3, 0xa0, 0x49, 0x40, 0x31, 0x20,
++0x80, 0xe3, 0xa0, 0x49, 0x00, 0x31, 0x2a, 0x90, 0x48, 0x80, 0xe3, 0xa0,
++0x48, 0xc0, 0x31, 0x28, 0x80, 0xe3, 0xa0, 0x48, 0x80, 0x31, 0x26, 0x91,
++0x20, 0x90, 0x90, 0x90, 0x48, 0x80, 0xe3, 0xa0, 0x46, 0x40, 0x31, 0x08,
++0x80, 0xe3, 0xa0, 0x46, 0x00, 0x31, 0x1e, 0x90, 0x48, 0x80, 0xe3, 0xa0,
++0x45, 0xc0, 0x31, 0x1c, 0x80, 0xe3, 0xa0, 0x45, 0x80, 0x31, 0x1a, 0x90,
++0x90, 0x90, 0x48, 0x80, 0xe3, 0xa0, 0x43, 0xc0, 0x31, 0x0a, 0x80, 0xe3,
++0xa0, 0x43, 0x80, 0x31, 0x14, 0x90, 0x48, 0x80, 0xe3, 0xa0, 0x43, 0x40,
++0x31, 0x12, 0x80, 0xe3, 0xa0, 0x43, 0x00, 0x31, 0x10, 0x94, 0x88, 0x80,
++0x92, 0x40, 0x91, 0x20, 0x90, 0x90, 0x90, 0x48, 0x80, 0xe3, 0xa0, 0x6c,
++0x80, 0x31, 0xb9, 0x80, 0xe3, 0xa0, 0x6c, 0x40, 0x31, 0xb7, 0x90, 0x48,
++0x80, 0xe3, 0xa0, 0x6c, 0x00, 0x31, 0xb5, 0x80, 0xe3, 0xa0, 0x6b, 0xc0,
++0x31, 0xb3, 0x90, 0x90, 0x90, 0x48, 0x80, 0xe3, 0xa0, 0x6f, 0x40, 0x31,
++0xc4, 0x80, 0xe3, 0xa0, 0x6f, 0x00, 0x31, 0xc2, 0x90, 0x48, 0x80, 0xe3,
++0xa0, 0x6e, 0xc0, 0x31, 0xc0, 0x80, 0xe3, 0xa0, 0x6e, 0x80, 0x31, 0xbe,
++0x91, 0x20, 0x90, 0x90, 0x90, 0x48, 0x80, 0xe3, 0xa0, 0x74, 0xc0, 0x31,
++0xda, 0x80, 0xe3, 0xa0, 0x74, 0x80, 0x31, 0xd8, 0x90, 0x48, 0x80, 0xe3,
++0xa0, 0x74, 0x40, 0x31, 0xd6, 0x80, 0xe3, 0xa0, 0x74, 0x00, 0x31, 0xd4,
++0x90, 0x90, 0x90, 0x48, 0x80, 0xe3, 0xa0, 0x72, 0x00, 0x31, 0xcf, 0x80,
++0xe3, 0xa0, 0x71, 0xc0, 0x31, 0xcd, 0x90, 0x48, 0x80, 0xe3, 0xa0, 0x71,
++0x80, 0x31, 0xcb, 0x80, 0xe3, 0xa0, 0x71, 0x40, 0x31, 0xc9, 0x80, 0x10,
++0x10, 0x10, 0x10, 0x90, 0x90, 0x90, 0x48, 0x80, 0xe3, 0xa0, 0x6a, 0x00,
++0x31, 0xa4, 0x80, 0xe3, 0xa0, 0x69, 0xc0, 0x31, 0xad, 0x90, 0x48, 0x80,
++0xe3, 0xa0, 0x69, 0x80, 0x31, 0xab, 0x80, 0xe3, 0xa0, 0x69, 0x40, 0x31,
++0xa9, 0xa0, 0x0b, 0x90, 0xa0, 0x0a, 0xc8, 0x95, 0x60, 0x92, 0xb0, 0x91,
++0x40, 0x90, 0x88, 0x90, 0x50, 0x90, 0x28, 0x80, 0x31, 0xef, 0x80, 0x31,
++0xee, 0x10, 0x10, 0x80, 0x31, 0xed, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x0a,
++0x48, 0x32, 0x01, 0xa4, 0x0a, 0x40, 0x32, 0x00, 0x10, 0x10, 0xa4, 0x0a,
++0x38, 0x31, 0xff, 0x90, 0xb8, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x0b, 0x68,
++0x32, 0x25, 0xa4, 0x0b, 0x60, 0x32, 0x24, 0x10, 0x10, 0xa4, 0x0b, 0x58,
++0x32, 0x23, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x0a, 0xd8, 0x32, 0x13, 0xa4,
++0x0a, 0xd0, 0x32, 0x12, 0x10, 0x10, 0xa4, 0x0a, 0xc8, 0x32, 0x11, 0x91,
++0x40, 0x90, 0x88, 0x90, 0x50, 0x90, 0x28, 0x80, 0x31, 0xea, 0x80, 0x31,
++0xec, 0x10, 0x10, 0x80, 0x31, 0xeb, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x0a,
++0x20, 0x31, 0xfc, 0xa4, 0x0a, 0x30, 0x31, 0xfe, 0x10, 0x10, 0xa4, 0x0a,
++0x28, 0x31, 0xfd, 0x90, 0xb8, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x0b, 0x40,
++0x32, 0x20, 0xa4, 0x0b, 0x50, 0x32, 0x22, 0x10, 0x10, 0xa4, 0x0b, 0x48,
++0x32, 0x21, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x0a, 0xb0, 0x32, 0x0e, 0xa4,
++0x0a, 0xc0, 0x32, 0x10, 0x10, 0x10, 0xa4, 0x0a, 0xb8, 0x32, 0x0f, 0x92,
++0xb0, 0x91, 0x40, 0x90, 0x88, 0x90, 0x50, 0x90, 0x28, 0x80, 0x31, 0xe7,
++0x80, 0x31, 0xe9, 0x10, 0x10, 0x80, 0x31, 0xe8, 0x90, 0x70, 0x90, 0x38,
++0xa4, 0x0a, 0x08, 0x31, 0xf9, 0xa4, 0x0a, 0x18, 0x31, 0xfb, 0x10, 0x10,
++0xa4, 0x0a, 0x10, 0x31, 0xfa, 0x90, 0xb8, 0x90, 0x70, 0x90, 0x38, 0xa4,
++0x0b, 0x28, 0x32, 0x1d, 0xa4, 0x0b, 0x38, 0x32, 0x1f, 0x10, 0x10, 0xa4,
++0x0b, 0x30, 0x32, 0x1e, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x0a, 0x98, 0x32,
++0x0b, 0xa4, 0x0a, 0xa8, 0x32, 0x0d, 0x10, 0x10, 0xa4, 0x0a, 0xa0, 0x32,
++0x0c, 0x91, 0x40, 0x90, 0x88, 0x90, 0x50, 0x90, 0x28, 0x80, 0x31, 0xe4,
++0x80, 0x31, 0xe6, 0x10, 0x10, 0x80, 0x31, 0xe5, 0x90, 0x70, 0x90, 0x38,
++0xa4, 0x09, 0xf0, 0x31, 0xf6, 0xa4, 0x0a, 0x00, 0x31, 0xf8, 0x10, 0x10,
++0xa4, 0x09, 0xf8, 0x31, 0xf7, 0x90, 0xb8, 0x90, 0x70, 0x90, 0x38, 0xa4,
++0x0b, 0x10, 0x32, 0x1a, 0xa4, 0x0b, 0x20, 0x32, 0x1c, 0x10, 0x10, 0xa4,
++0x0b, 0x18, 0x32, 0x1b, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x0a, 0x80, 0x32,
++0x08, 0xa4, 0x0a, 0x90, 0x32, 0x0a, 0x10, 0x10, 0xa4, 0x0a, 0x88, 0x32,
++0x09, 0x10, 0x10, 0x80, 0x10, 0x10, 0x10, 0x10, 0x90, 0x50, 0x90, 0x28,
++0x80, 0x31, 0xdb, 0x80, 0x31, 0xdd, 0x10, 0x10, 0x80, 0x31, 0xdc, 0x80,
++0x95, 0x60, 0x92, 0xb0, 0x91, 0x40, 0x90, 0x88, 0x90, 0x50, 0x90, 0x28,
++0x80, 0x31, 0xe1, 0x80, 0x31, 0xe3, 0x10, 0x10, 0x80, 0x31, 0xe2, 0x90,
++0x70, 0x90, 0x38, 0xa4, 0x09, 0xd8, 0x31, 0xf3, 0xa4, 0x09, 0xe8, 0x31,
++0xf5, 0x10, 0x10, 0xa4, 0x09, 0xe0, 0x31, 0xf4, 0x90, 0xb8, 0x90, 0x70,
++0x90, 0x38, 0xa4, 0x0a, 0xf8, 0x32, 0x17, 0xa4, 0x0b, 0x08, 0x32, 0x19,
++0x10, 0x10, 0xa4, 0x0b, 0x00, 0x32, 0x18, 0x90, 0x70, 0x90, 0x38, 0xa4,
++0x0a, 0x68, 0x32, 0x05, 0xa4, 0x0a, 0x78, 0x32, 0x07, 0x10, 0x10, 0xa4,
++0x0a, 0x70, 0x32, 0x06, 0x91, 0x40, 0x90, 0x88, 0x90, 0x50, 0x90, 0x28,
++0x80, 0x31, 0xde, 0x80, 0x31, 0xe0, 0x10, 0x10, 0x80, 0x31, 0xdf, 0x90,
++0x70, 0x90, 0x38, 0xa4, 0x09, 0xc0, 0x31, 0xf0, 0xa4, 0x09, 0xd0, 0x31,
++0xf2, 0x10, 0x10, 0xa4, 0x09, 0xc8, 0x31, 0xf1, 0x90, 0xb8, 0x90, 0x70,
++0x90, 0x38, 0xa4, 0x0a, 0xe0, 0x32, 0x14, 0xa4, 0x0a, 0xf0, 0x32, 0x16,
++0x10, 0x10, 0xa4, 0x0a, 0xe8, 0x32, 0x15, 0x90, 0x70, 0x90, 0x38, 0xa4,
++0x0a, 0x50, 0x32, 0x02, 0xa4, 0x0a, 0x60, 0x32, 0x04, 0x10, 0x10, 0xa4,
++0x0a, 0x58, 0x32, 0x03, 0x10, 0x10, 0x92, 0x40, 0x91, 0x20, 0x90, 0x90,
++0x90, 0x48, 0x80, 0xe3, 0xa0, 0x3c, 0xc0, 0x30, 0xfa, 0x80, 0xe3, 0xa0,
++0x3c, 0x80, 0x30, 0xf8, 0x90, 0x48, 0x80, 0xe3, 0xa0, 0x3c, 0x40, 0x30,
++0xf6, 0x80, 0xe3, 0xa0, 0x3c, 0x00, 0x30, 0xf4, 0x90, 0x90, 0x90, 0x48,
++0x80, 0xe3, 0xa0, 0x3a, 0x40, 0x30, 0xe4, 0x80, 0xe3, 0xa0, 0x3a, 0x00,
++0x30, 0xee, 0x90, 0x48, 0x80, 0xe3, 0xa0, 0x39, 0xc0, 0x30, 0xec, 0x80,
++0xe3, 0xa0, 0x39, 0x80, 0x30, 0xea, 0x91, 0x20, 0x90, 0x90, 0x90, 0x48,
++0x80, 0xe3, 0xa0, 0x37, 0x40, 0x30, 0xcc, 0x80, 0xe3, 0xa0, 0x37, 0x00,
++0x30, 0xe2, 0x90, 0x48, 0x80, 0xe3, 0xa0, 0x36, 0xc0, 0x30, 0xe0, 0x80,
++0xe3, 0xa0, 0x36, 0x80, 0x30, 0xde, 0x90, 0x90, 0x90, 0x48, 0x80, 0xe3,
++0xa0, 0x34, 0xc0, 0x30, 0xce, 0x80, 0xe3, 0xa0, 0x34, 0x80, 0x30, 0xd8,
++0x90, 0x48, 0x80, 0xe3, 0xa0, 0x34, 0x40, 0x30, 0xd6, 0x80, 0xe3, 0xa0,
++0x34, 0x00, 0x30, 0xd4, 0xc3, 0xc0, 0x30, 0x42, 0x9d, 0x18, 0x07, 0xf0,
++0x91, 0xc0, 0x90, 0xf0, 0x10, 0x10, 0x80, 0x88, 0x00, 0x80, 0x90, 0x50,
++0x90, 0x28, 0x80, 0x37, 0x1c, 0x80, 0x37, 0x1d, 0x81, 0x37, 0x13, 0xd0,
++0x41, 0x80, 0x24, 0x39, 0xb0, 0x24, 0x39, 0xb8, 0x10, 0x10, 0x80, 0x90,
++0x58, 0x80, 0x90, 0x28, 0x24, 0x38, 0xb0, 0x24, 0x38, 0xb8, 0x90, 0x30,
++0x80, 0x24, 0x38, 0x60, 0x80, 0x24, 0x38, 0x58, 0x92, 0x68, 0x91, 0x00,
++0x80, 0x90, 0x90, 0x90, 0x30, 0x80, 0x24, 0x39, 0x20, 0x90, 0x38, 0xa4,
++0x39, 0x18, 0x37, 0x2a, 0x80, 0x37, 0x29, 0x80, 0x90, 0x28, 0x80, 0x37,
++0x33, 0xa4, 0x39, 0x00, 0x37, 0x32, 0x80, 0x90, 0xc0, 0x90, 0x60, 0x90,
++0x28, 0x80, 0x37, 0x2d, 0xa4, 0x39, 0x10, 0x37, 0x2c, 0x90, 0x28, 0x80,
++0x37, 0x28, 0xa4, 0x39, 0x08, 0x37, 0x27, 0x90, 0x50, 0x90, 0x28, 0x80,
++0x37, 0x31, 0x80, 0x37, 0x30, 0x90, 0x28, 0x24, 0x39, 0xa8, 0x24, 0x39,
++0xa0, 0x90, 0x58, 0x80, 0x10, 0x10, 0x80, 0x10, 0x10, 0x80, 0x37, 0x1f,
++0x80, 0x90, 0x40, 0x10, 0x10, 0x80, 0x24, 0x38, 0x70, 0x80, 0x10, 0x10,
++0x80, 0x37, 0x1e, 0x91, 0xb8, 0x91, 0x60, 0x90, 0xe0, 0x80, 0x90, 0x78,
++0x90, 0x50, 0x90, 0x28, 0x80, 0x37, 0x1a, 0x80, 0x37, 0x1b, 0x81, 0x37,
++0x12, 0x10, 0x10, 0x90, 0x28, 0x24, 0x38, 0x80, 0x24, 0x38, 0x78, 0x81,
++0x90, 0x50, 0x90, 0x28, 0x80, 0x37, 0x18, 0x80, 0x37, 0x19, 0x81, 0x37,
++0x11, 0x83, 0x90, 0x28, 0x24, 0x38, 0xa0, 0x24, 0x38, 0xa8, 0x90, 0xe8,
++0x81, 0x90, 0x88, 0x90, 0x38, 0x10, 0x10, 0x80, 0x37, 0x2b, 0x90, 0x28,
++0x80, 0x37, 0x26, 0x80, 0x37, 0x25, 0x80, 0x90, 0x28, 0x80, 0x37, 0x2f,
++0x80, 0x37, 0x2e, 0x82, 0x10, 0x10, 0x80, 0x24, 0x38, 0x68, 0x97, 0x10,
++0x9e, 0x10, 0x06, 0x98, 0x93, 0x00, 0x91, 0x80, 0x90, 0xc0, 0x90, 0x60,
++0x90, 0x38, 0xa4, 0x04, 0x80, 0x30, 0x91, 0x24, 0x04, 0x78, 0x90, 0x38,
++0xa4, 0x05, 0x10, 0x30, 0xa3, 0x24, 0x05, 0x08, 0x90, 0x60, 0x90, 0x38,
++0xa4, 0x06, 0x30, 0x30, 0xc7, 0x24, 0x06, 0x28, 0x90, 0x38, 0xa4, 0x05,
++0xa0, 0x30, 0xb5, 0x24, 0x05, 0x98, 0x90, 0xc0, 0x90, 0x60, 0x90, 0x38,
++0xa4, 0x04, 0x70, 0x30, 0x8c, 0x24, 0x04, 0x68, 0x90, 0x38, 0xa4, 0x05,
++0x00, 0x30, 0x9e, 0x24, 0x04, 0xf8, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x06,
++0x20, 0x30, 0xc2, 0x24, 0x06, 0x18, 0x90, 0x38, 0xa4, 0x05, 0x90, 0x30,
++0xb0, 0x24, 0x05, 0x88, 0x91, 0x80, 0x90, 0xc0, 0x90, 0x60, 0x90, 0x38,
++0xa4, 0x04, 0x58, 0x30, 0x89, 0x24, 0x04, 0x50, 0x90, 0x38, 0xa4, 0x04,
++0xe8, 0x30, 0x9b, 0x24, 0x04, 0xe0, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x06,
++0x08, 0x30, 0xbf, 0x24, 0x06, 0x00, 0x90, 0x38, 0xa4, 0x05, 0x78, 0x30,
++0xad, 0x24, 0x05, 0x70, 0x90, 0xc0, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x04,
++0x40, 0x30, 0x86, 0x24, 0x04, 0x38, 0x90, 0x38, 0xa4, 0x04, 0xd0, 0x30,
++0x98, 0x24, 0x04, 0xc8, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x05, 0xf0, 0x30,
++0xbc, 0x24, 0x05, 0xe8, 0x90, 0x38, 0xa4, 0x05, 0x60, 0x30, 0xaa, 0x24,
++0x05, 0x58, 0x10, 0x10, 0x80, 0x10, 0x10, 0x10, 0x10, 0x90, 0x38, 0xa4,
++0x03, 0xf8, 0x30, 0x7d, 0x24, 0x03, 0xf0, 0xd7, 0x42, 0x00, 0xa4, 0x52,
++0x70, 0x3a, 0x50, 0xa4, 0x52, 0x50, 0x3a, 0x4c, 0x9f, 0x20, 0x08, 0xd0,
++0x93, 0x00, 0x91, 0x80, 0x90, 0xc0, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x04,
++0x28, 0x30, 0x83, 0x24, 0x04, 0x20, 0x90, 0x38, 0xa4, 0x04, 0xb8, 0x30,
++0x95, 0x24, 0x04, 0xb0, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x05, 0xd8, 0x30,
++0xb9, 0x24, 0x05, 0xd0, 0x90, 0x38, 0xa4, 0x05, 0x48, 0x30, 0xa7, 0x24,
++0x05, 0x40, 0x90, 0xc0, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x04, 0x10, 0x30,
++0x80, 0x24, 0x04, 0x08, 0x90, 0x38, 0xa4, 0x04, 0xa0, 0x30, 0x92, 0x24,
++0x04, 0x98, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x05, 0xc0, 0x30, 0xb6, 0x24,
++0x05, 0xb8, 0x90, 0x38, 0xa4, 0x05, 0x30, 0x30, 0xa4, 0x24, 0x05, 0x28,
++0x10, 0x10, 0x92, 0x00, 0x91, 0x00, 0x90, 0x80, 0x90, 0x40, 0xe3, 0xe0,
++0x1a, 0x80, 0x30, 0x71, 0xe3, 0xe0, 0x1a, 0x40, 0x30, 0x6f, 0x90, 0x40,
++0xe3, 0xe0, 0x1a, 0x00, 0x30, 0x6d, 0xe3, 0xe0, 0x19, 0xc0, 0x30, 0x6b,
++0x90, 0x80, 0x90, 0x40, 0xe3, 0xe0, 0x18, 0x00, 0x30, 0x5b, 0xe3, 0xe0,
++0x17, 0xc0, 0x30, 0x65, 0x90, 0x40, 0xe3, 0xe0, 0x17, 0x80, 0x30, 0x63,
++0xe3, 0xe0, 0x17, 0x40, 0x30, 0x61, 0x91, 0x00, 0x90, 0x80, 0x90, 0x40,
++0xe3, 0xe0, 0x15, 0x00, 0x30, 0x43, 0xe3, 0xe0, 0x14, 0xc0, 0x30, 0x59,
++0x90, 0x40, 0xe3, 0xe0, 0x14, 0x80, 0x30, 0x57, 0xe3, 0xe0, 0x14, 0x40,
++0x30, 0x55, 0x90, 0x80, 0x90, 0x40, 0xe3, 0xe0, 0x12, 0x80, 0x30, 0x45,
++0xe3, 0xe0, 0x12, 0x40, 0x30, 0x4f, 0x90, 0x40, 0xe3, 0xe0, 0x12, 0x00,
++0x30, 0x4d, 0xe3, 0xe0, 0x11, 0xc0, 0x30, 0x4b, 0x91, 0x48, 0x80, 0x90,
++0xa0, 0x90, 0x50, 0x90, 0x28, 0x80, 0x30, 0x76, 0x24, 0x03, 0xa8, 0x90,
++0x28, 0x80, 0x30, 0x78, 0x24, 0x03, 0xb8, 0x90, 0x50, 0x90, 0x28, 0x80,
++0x30, 0x7c, 0x24, 0x03, 0xd8, 0x90, 0x28, 0x80, 0x30, 0x7a, 0x24, 0x03,
++0xc8, 0x80, 0x10, 0x10, 0x10, 0x10, 0x90, 0x28, 0x80, 0x30, 0x73, 0x24,
++0x03, 0xa0, 0xd7, 0x42, 0x00, 0xa4, 0x52, 0x78, 0x3a, 0x51, 0xa4, 0x52,
++0x58, 0x3a, 0x4d, 0xa0, 0x14, 0x68, 0xa0, 0x10, 0x90, 0xa0, 0x0c, 0x60,
++0x9e, 0x88, 0x09, 0xd0, 0x94, 0xf0, 0x90, 0xb0, 0x88, 0x00, 0x68, 0x84,
++0x10, 0x10, 0xc9, 0xe2, 0x15, 0x00, 0x85, 0x38, 0x70, 0xcb, 0x62, 0x0d,
++0xc0, 0x85, 0x38, 0x46, 0x9a, 0x00, 0x03, 0xf8, 0x91, 0x98, 0x80, 0x91,
++0x10, 0x90, 0xa0, 0x90, 0x68, 0x90, 0x20, 0x3d, 0x98, 0xc9, 0xe3, 0x65,
++0x80, 0x85, 0x38, 0x6e, 0xa4, 0x6c, 0xa0, 0x3d, 0x95, 0x90, 0x38, 0xa4,
++0x6c, 0x68, 0x3d, 0x8e, 0xa4, 0x6c, 0x58, 0x3d, 0x8c, 0x90, 0x48, 0x10,
++0x10, 0xa4, 0x6c, 0x20, 0x3d, 0x85, 0x10, 0x10, 0x80, 0x3d, 0x81, 0x81,
++0x10, 0x10, 0x80, 0xa4, 0x6b, 0xf0, 0x3d, 0x7f, 0x91, 0xb0, 0x91, 0x60,
++0x90, 0xe0, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x6c, 0x90, 0x3d, 0x93, 0xa4,
++0x6c, 0x80, 0x3d, 0x91, 0x90, 0x38, 0xa4, 0x6c, 0x48, 0x3d, 0x8a, 0xa4,
++0x6c, 0x38, 0x3d, 0x88, 0x90, 0x48, 0x10, 0x10, 0xa4, 0x6c, 0x10, 0x3d,
++0x83, 0x10, 0x10, 0x80, 0x3d, 0x80, 0x90, 0x28, 0x80, 0x3d, 0x79, 0x80,
++0x3d, 0x78, 0x81, 0x10, 0x10, 0x80, 0xa4, 0x6b, 0xe0, 0x3d, 0x7d, 0xcb,
++0x62, 0x0d, 0x80, 0x85, 0x38, 0x45, 0x90, 0xd8, 0x88, 0x00, 0x90, 0x84,
++0x90, 0x38, 0xc1, 0xc0, 0x85, 0x3d, 0x9b, 0xc9, 0xe2, 0x14, 0xc0, 0x85,
++0x38, 0x6c, 0xcb, 0x62, 0x0d, 0x40, 0x85, 0x38, 0x44, 0x88, 0x00, 0x68,
++0x84, 0x10, 0x10, 0xc9, 0xe2, 0x14, 0x80, 0x85, 0x38, 0x6a, 0xcb, 0x62,
++0x0d, 0x00, 0x85, 0x38, 0x43, 0x91, 0xf8, 0x90, 0xb0, 0x88, 0x00, 0x68,
++0x84, 0x10, 0x10, 0xc9, 0xe2, 0x14, 0x00, 0x85, 0x38, 0x66, 0xcb, 0x62,
++0x0c, 0x80, 0x85, 0x38, 0x41, 0x88, 0x01, 0x00, 0x90, 0xa0, 0x81, 0x90,
++0x70, 0x80, 0x90, 0x20, 0x3d, 0x8f, 0xc9, 0xe2, 0x13, 0xc0, 0x85, 0x38,
++0x64, 0x81, 0x3d, 0x86, 0x81, 0x10, 0x10, 0x80, 0xa4, 0x6b, 0xd0, 0x3d,
++0x7b, 0xcb, 0x62, 0x0c, 0x40, 0x85, 0x38, 0x40, 0x90, 0xb0, 0x88, 0x00,
++0x68, 0x84, 0x10, 0x10, 0xc9, 0xe2, 0x13, 0x80, 0x85, 0x38, 0x62, 0xcb,
++0x62, 0x0c, 0x00, 0x85, 0x38, 0x3f, 0x88, 0x00, 0x68, 0x84, 0x10, 0x10,
++0xc9, 0xe2, 0x13, 0x40, 0x85, 0x38, 0x60, 0xcb, 0x62, 0x0b, 0xc0, 0x85,
++0x38, 0x3e, 0x92, 0x38, 0x81, 0x91, 0x68, 0x91, 0x18, 0x90, 0x80, 0x90,
++0x40, 0x80, 0xa4, 0x6d, 0x50, 0x3d, 0xab, 0x80, 0xa4, 0x6d, 0x48, 0x3d,
++0xa8, 0x90, 0x28, 0x81, 0x3d, 0xa7, 0x90, 0x38, 0xa4, 0x6d, 0x28, 0x3d,
++0xa6, 0xa4, 0x6d, 0x18, 0x3d, 0xa4, 0x90, 0x28, 0x80, 0x3d, 0xa2, 0x80,
++0x3d, 0xa1, 0x80, 0x90, 0x40, 0x10, 0x10, 0x80, 0x24, 0x6d, 0x00, 0x10,
++0x10, 0x90, 0x38, 0xa4, 0x6c, 0xf0, 0x3d, 0x9f, 0xa4, 0x6c, 0xe0, 0x3d,
++0x9d, 0x90, 0x28, 0x80, 0x3d, 0x9a, 0x80, 0x3d, 0x99, 0x9a, 0xd0, 0x03,
++0xe0, 0x91, 0x60, 0x90, 0xb0, 0x88, 0x00, 0x68, 0x84, 0x10, 0x10, 0xc9,
++0xe2, 0x12, 0xc0, 0x85, 0x38, 0x5c, 0xcb, 0x62, 0x0b, 0x40, 0x85, 0x38,
++0x3c, 0x88, 0x00, 0x68, 0x84, 0x10, 0x10, 0xc9, 0xe2, 0x12, 0x80, 0x85,
++0x38, 0x5a, 0xcb, 0x62, 0x0b, 0x00, 0x85, 0x38, 0x3b, 0x90, 0xb0, 0x88,
++0x00, 0x68, 0x84, 0x10, 0x10, 0xc9, 0xe2, 0x12, 0x40, 0x85, 0x38, 0x58,
++0xcb, 0x62, 0x0a, 0xc0, 0x85, 0x38, 0x3a, 0x88, 0x00, 0x68, 0x84, 0x10,
++0x10, 0xc9, 0xe2, 0x12, 0x00, 0x85, 0x38, 0x56, 0xcb, 0x62, 0x0a, 0x80,
++0x85, 0x38, 0x39, 0x90, 0x90, 0x90, 0x48, 0xcb, 0xa2, 0x08, 0xc0, 0x85,
++0x38, 0x28, 0xcb, 0xa2, 0x08, 0x80, 0x85, 0x38, 0x27, 0x90, 0x48, 0xcb,
++0xa2, 0x08, 0x40, 0x85, 0x38, 0x26, 0xcb, 0xa2, 0x08, 0x00, 0x85, 0x38,
++0x25, 0xcb, 0xa3, 0x5d, 0x80, 0x80, 0x3d, 0x77, 0x92, 0x40, 0x91, 0x20,
++0x90, 0x90, 0x90, 0x48, 0x8c, 0x40, 0x78, 0x84, 0x24, 0x40, 0xf0, 0x8c,
++0x40, 0x70, 0x84, 0x24, 0x40, 0xe8, 0x90, 0x48, 0x8c, 0x40, 0x68, 0x84,
++0x24, 0x40, 0xe0, 0x8c, 0x40, 0x60, 0x84, 0x24, 0x40, 0xd8, 0x90, 0x90,
++0x90, 0x48, 0x8c, 0x40, 0x50, 0x84, 0x24, 0x40, 0xc8, 0x8c, 0x40, 0x48,
++0x84, 0x24, 0x40, 0xc0, 0x90, 0x48, 0x8c, 0x40, 0x40, 0x84, 0x24, 0x40,
++0xb8, 0x8c, 0x40, 0x38, 0x84, 0x24, 0x40, 0xb0, 0x91, 0x20, 0x90, 0x90,
++0x90, 0x48, 0x8c, 0x40, 0x28, 0x84, 0x24, 0x40, 0xa0, 0x8c, 0x40, 0x20,
++0x84, 0x24, 0x40, 0x98, 0x90, 0x48, 0x8c, 0x40, 0x18, 0x84, 0x24, 0x40,
++0x90, 0x8c, 0x40, 0x10, 0x84, 0x24, 0x40, 0x88, 0x90, 0x38, 0xa4, 0x3f,
++0xf8, 0x38, 0x00, 0xa4, 0x3f, 0xe8, 0x37, 0xfe, 0xa0, 0x0f, 0x50, 0xa0,
++0x09, 0x08, 0x9a, 0x30, 0x04, 0x40, 0x91, 0x90, 0x90, 0xc8, 0x98, 0x50,
++0x00, 0x80, 0xe5, 0x23, 0x5b, 0x80, 0x3d, 0x66, 0xe5, 0x23, 0x53, 0x80,
++0x3d, 0x62, 0xcb, 0x61, 0xfb, 0x00, 0x85, 0x37, 0xfb, 0x98, 0x50, 0x00,
++0x80, 0xe5, 0x23, 0x4b, 0x80, 0x3d, 0x26, 0xe5, 0x23, 0x43, 0x80, 0x3d,
++0x22, 0xcb, 0x61, 0xfa, 0xc0, 0x85, 0x37, 0xfa, 0x90, 0x48, 0xcb, 0xa1,
++0xfa, 0x80, 0x85, 0x37, 0xf9, 0xcb, 0xa1, 0xfa, 0x40, 0x85, 0x37, 0xf8,
++0x91, 0x90, 0x90, 0xc8, 0x98, 0x50, 0x00, 0x80, 0xe5, 0x23, 0x35, 0x80,
++0x3c, 0xee, 0xe5, 0x23, 0x29, 0x80, 0x3c, 0xbe, 0xcb, 0x61, 0xf9, 0xc0,
++0x85, 0x37, 0xf6, 0x98, 0x50, 0x00, 0x80, 0xe5, 0x23, 0x1d, 0x80, 0x3c,
++0x8e, 0xe5, 0x23, 0x11, 0x80, 0x3c, 0x5e, 0xcb, 0x61, 0xf9, 0x80, 0x85,
++0x37, 0xf5, 0x90, 0x48, 0xcb, 0xa1, 0xf9, 0x40, 0x85, 0x37, 0xf4, 0xcb,
++0xa1, 0xf9, 0x00, 0x85, 0x37, 0xf3, 0x92, 0x20, 0x91, 0x30, 0x90, 0xb8,
++0xd5, 0x03, 0x00, 0xc0, 0xc0, 0x81, 0x8c, 0x01, 0xa0, 0x84, 0x30, 0x3e,
++0xc0, 0xc0, 0x81, 0x8c, 0x01, 0x80, 0x84, 0x30, 0x3c, 0xd5, 0x02, 0x00,
++0xc0, 0xc0, 0x81, 0x30, 0x28, 0xc0, 0xc0, 0x81, 0x30, 0x24, 0x90, 0x78,
++0xd5, 0x02, 0x00, 0xc0, 0xc0, 0x81, 0x30, 0x1c, 0xc0, 0xc0, 0x81, 0x30,
++0x18, 0xd5, 0x02, 0x00, 0xc0, 0xc0, 0x81, 0x30, 0x10, 0xc0, 0xc0, 0x81,
++0x30, 0x0c, 0x91, 0x70, 0x90, 0xd8, 0xd5, 0x03, 0x80, 0xc8, 0xe3, 0x09,
++0x80, 0x81, 0x8c, 0x01, 0xc0, 0x84, 0x30, 0x40, 0xc8, 0xe3, 0x0b, 0x80,
++0x81, 0x8c, 0x01, 0x90, 0x84, 0x30, 0x3d, 0xd5, 0x02, 0x80, 0xc8, 0xe3,
++0x08, 0x80, 0x81, 0x30, 0x2c, 0xc8, 0xe3, 0x03, 0x00, 0x81, 0x30, 0x26,
++0x90, 0x98, 0xd5, 0x02, 0x80, 0xc8, 0xe2, 0xf8, 0x00, 0x81, 0x30, 0x20,
++0xc8, 0xe2, 0xfa, 0x00, 0x81, 0x30, 0x1a, 0xd5, 0x02, 0x80, 0xc8, 0xe2,
++0xf7, 0x00, 0x81, 0x30, 0x14, 0xc8, 0xe2, 0xf1, 0x80, 0x81, 0x30, 0x0e,
++0x9a, 0x30, 0x04, 0x40, 0x91, 0x90, 0x90, 0xc8, 0x98, 0x50, 0x00, 0x80,
++0xe5, 0x23, 0x4f, 0x80, 0x3d, 0x36, 0xe5, 0x23, 0x51, 0x80, 0x3d, 0x5a,
++0xcb, 0x61, 0xf8, 0x80, 0x85, 0x37, 0xf1, 0x98, 0x50, 0x00, 0x80, 0xe5,
++0x23, 0x3f, 0x80, 0x3c, 0xf6, 0xe5, 0x23, 0x41, 0x80, 0x3d, 0x1a, 0xcb,
++0x61, 0xf8, 0x40, 0x85, 0x37, 0xf0, 0x90, 0x48, 0xcb, 0xa1, 0xf8, 0x00,
++0x85, 0x37, 0xef, 0xcb, 0xa1, 0xf7, 0xc0, 0x85, 0x37, 0xee, 0x91, 0x90,
++0x90, 0xc8, 0x98, 0x50, 0x00, 0x80, 0xe5, 0x23, 0x31, 0x80, 0x3c, 0xde,
++0xe5, 0x23, 0x25, 0x80, 0x3c, 0xae, 0xcb, 0x61, 0xf6, 0x00, 0x85, 0x37,
++0xdd, 0x98, 0x50, 0x00, 0x80, 0xe5, 0x23, 0x19, 0x80, 0x3c, 0x7e, 0xe5,
++0x23, 0x0d, 0x80, 0x3c, 0x4e, 0xcb, 0x61, 0xf5, 0xc0, 0x85, 0x37, 0xdc,
++0x90, 0x48, 0xcb, 0xa1, 0xf5, 0x80, 0x85, 0x37, 0xdb, 0xcb, 0xa1, 0xf5,
++0x40, 0x85, 0x37, 0xda, 0x91, 0x00, 0x90, 0x80, 0x90, 0x40, 0xe5, 0x20,
++0x02, 0x40, 0x30, 0x0a, 0xe5, 0x20, 0x01, 0x80, 0x30, 0x07, 0x90, 0x40,
++0xe5, 0x20, 0x00, 0xc0, 0x30, 0x04, 0xe5, 0x20, 0x00, 0x00, 0x30, 0x01,
++0x90, 0x80, 0x90, 0x40, 0xe5, 0x22, 0xfe, 0x80, 0x3b, 0xf0, 0xe5, 0x23,
++0x00, 0xc0, 0x3c, 0x18, 0x90, 0x40, 0xe5, 0x22, 0xed, 0x00, 0x3b, 0xaa,
++0xe5, 0x22, 0xef, 0x40, 0x3b, 0xd2, 0x80, 0x99, 0x28, 0x02, 0xf0, 0x8c,
++0x3e, 0x60, 0x90, 0x80, 0x90, 0x40, 0xe5, 0x23, 0x55, 0x80, 0x3d, 0x52,
++0xe5, 0x23, 0x52, 0x80, 0x3d, 0x5e, 0x90, 0x40, 0xe5, 0x23, 0x45, 0x80,
++0x3d, 0x12, 0xe5, 0x23, 0x42, 0x80, 0x3d, 0x1e, 0x91, 0x48, 0x90, 0xc8,
++0x98, 0x50, 0x00, 0x80, 0xe5, 0x23, 0x33, 0x80, 0x3c, 0xe6, 0xe5, 0x23,
++0x27, 0x80, 0x3c, 0xb6, 0xcb, 0x61, 0xf3, 0xc0, 0x85, 0x37, 0xd3, 0x90,
++0x40, 0xe5, 0x23, 0x1b, 0x80, 0x3c, 0x86, 0xe5, 0x23, 0x0f, 0x80, 0x3c,
++0x56, 0x90, 0x48, 0xcb, 0xa1, 0xf3, 0x40, 0x85, 0x37, 0xd1, 0xcb, 0xa1,
++0xf3, 0x80, 0x85, 0x37, 0xd2, 0x10, 0x10, 0x90, 0x80, 0x90, 0x40, 0xe5,
++0x23, 0x05, 0x00, 0x3c, 0x10, 0xe5, 0x23, 0x02, 0x00, 0x3c, 0x1e, 0x90,
++0x40, 0xe5, 0x22, 0xf3, 0x80, 0x3b, 0xca, 0xe5, 0x22, 0xf0, 0x80, 0x3b,
++0xd8,
+ };
+
+ static const struct ia64_dis_names ia64_dis_names[] = {
+--- a/opcodes/ia64-asmtab.h
++++ b/opcodes/ia64-asmtab.h
+@@ -31,7 +31,7 @@ struct ia64_main_table
+ opcode. */
+ unsigned short name_index;
+
+- /* The type of opcode; corresponds to the TYPE field in
++ /* The type of opcode; corresponds to the TYPE field in
+ struct ia64_opcode. */
+ unsigned char opcode_type;
+
+@@ -64,7 +64,7 @@ struct ia64_main_table
+ The completer entries modify certain bits in the instruction opcode.
+ Which bits are to be modified are marked by the BITS, MASK and
+ OFFSET fields. The completer entry may also note dependencies for the
+- opcode.
++ opcode.
+
+ These completers are arranged in a DAG; the pointers are indexes
+ into the completer_table array. The completer DAG is searched by
+@@ -81,7 +81,7 @@ struct ia64_main_table
+ not contain an empty entry.
+
+ Terminal completers (those completers that validly complete an
+- instruction) are marked by having the TERMINAL_COMPLETER flag set.
++ instruction) are marked by having the TERMINAL_COMPLETER flag set.
+
+ Only dependencies listed in the terminal completer for an opcode are
+ considered to apply to that opcode instance. */
+@@ -91,7 +91,7 @@ struct ia64_completer_table
+ /* The bit value that this completer sets. */
+ unsigned int bits;
+
+- /* And its mask. 1s are bits that are to be modified in the
++ /* And its mask. 1s are bits that are to be modified in the
+ instruction. */
+ unsigned int mask;
+
+@@ -118,11 +118,11 @@ struct ia64_completer_table
+
+ /* This contains sufficient information for the disassembler to resolve
+ the complete name of the original instruction. */
+-struct ia64_dis_names
++struct ia64_dis_names
+ {
+ /* COMPLETER_INDEX represents the tree of completers that make up
+ the instruction. The LSB represents the top of the tree for the
+- specified instruction.
++ specified instruction.
+
+ A 0 bit indicates to go to the next alternate completer via the
+ alternative field; a 1 bit indicates that the current completer
+--- a/opcodes/ia64-dis.c
++++ b/opcodes/ia64-dis.c
+@@ -303,7 +303,7 @@ print_insn_ia64 (bfd_vma memaddr, struct disassemble_info *info)
+ need_comma = 0;
+ }
+ }
+- if (slotnum + 1 == ia64_templ_desc[template_val].group_boundary
++ if (slotnum + 1 == ia64_templ_desc[template_val].group_boundary
+ || ((slotnum == 2) && s_bit))
+ (*info->fprintf_func) (info->stream, ";;");
+
+--- a/opcodes/ia64-gen.c
++++ b/opcodes/ia64-gen.c
+@@ -22,15 +22,15 @@
+
+ /* While the ia64-opc-* set of opcode tables are easy to maintain,
+ they waste a tremendous amount of space. ia64-gen rearranges the
+- instructions into a directed acyclic graph (DAG) of instruction opcodes and
+- their possible completers, as well as compacting the set of strings used.
++ instructions into a directed acyclic graph (DAG) of instruction opcodes and
++ their possible completers, as well as compacting the set of strings used.
+
+ The disassembler table consists of a state machine that does
+ branching based on the bits of the opcode being disassembled. The
+ state encodings have been chosen to minimize the amount of space
+- required.
++ required.
+
+- The resource table is constructed based on some text dependency tables,
++ The resource table is constructed based on some text dependency tables,
+ which are also easier to maintain than the final representation. */
+
+ #include "sysdep.h"
+@@ -172,7 +172,7 @@ struct bittree
+ alphabetical order. */
+
+ /* One entry in the string table. */
+-struct string_entry
++struct string_entry
+ {
+ /* The index in the ia64_strings[] array for this entry. */
+ int num;
+@@ -188,11 +188,11 @@ int strtabtotlen = 0;
+ struct rdep
+ {
+ char *name; /* Resource name. */
+- unsigned
++ unsigned
+ mode:2, /* RAW, WAW, or WAR. */
+ semantics:3; /* Dependency semantics. */
+ char *extra; /* Additional semantics info. */
+- int nchks;
++ int nchks;
+ int total_chks; /* Total #of terminal insns. */
+ int *chks; /* Insn classes which read (RAW), write
+ (WAW), or write (WAR) this rsrc. */
+@@ -211,12 +211,12 @@ static int rdepstotlen = 0;
+
+ /* Array of all instruction classes. */
+ struct iclass
+-{
++{
+ char *name; /* Instruction class name. */
+ int is_class; /* Is a class, not a terminal. */
+- int nsubs;
++ int nsubs;
+ int *subs; /* Other classes within this class. */
+- int nxsubs;
++ int nxsubs;
+ int xsubs[4]; /* Exclusions. */
+ char *comment; /* Optional comment. */
+ int note; /* Optional note. */
+@@ -301,7 +301,7 @@ static void
+ fail (const char *message, ...)
+ {
+ va_list args;
+-
++
+ va_start (args, message);
+ fprintf (stderr, _("%s: Error: "), program_name);
+ vfprintf (stderr, message, args);
+@@ -336,7 +336,7 @@ insert_resource (const char *name, enum ia64_dependency_mode type)
+ rdeps[rdepslen]->name = xstrdup (name);
+ rdeps[rdepslen]->mode = type;
+ rdeps[rdepslen]->waw_special = 0;
+-
++
+ return rdeps[rdepslen++];
+ }
+
+@@ -405,7 +405,7 @@ insert_deplist (int count, unsigned short *deps)
+
+ /* Add the given pair of dependency lists to the opcode dependency list. */
+ static short
+-insert_dependencies (int nchks, unsigned short *chks,
++insert_dependencies (int nchks, unsigned short *chks,
+ int nregs, unsigned short *regs)
+ {
+ struct opdep *pair;
+@@ -419,14 +419,14 @@ insert_dependencies (int nchks, unsigned short *chks,
+ chkind = insert_deplist (nchks, chks);
+
+ for (i = 0; i < opdeplen; i++)
+- if (opdeps[i]->chk == chkind
++ if (opdeps[i]->chk == chkind
+ && opdeps[i]->reg == regind)
+ return i;
+
+ pair = tmalloc (struct opdep);
+ pair->chk = chkind;
+ pair->reg = regind;
+-
++
+ if (opdeplen == opdeptotlen)
+ {
+ opdeptotlen += 20;
+@@ -438,7 +438,7 @@ insert_dependencies (int nchks, unsigned short *chks,
+ return opdeplen++;
+ }
+
+-static void
++static void
+ mark_used (struct iclass *ic, int clear_terminals)
+ {
+ int i;
+@@ -521,7 +521,7 @@ fetch_insn_class (const char *full_name, int create)
+ if (strcmp (name, ics[i]->name) == 0
+ && ((comment == NULL && ics[i]->comment == NULL)
+ || (comment != NULL && ics[i]->comment != NULL
+- && strncmp (ics[i]->comment, comment,
++ && strncmp (ics[i]->comment, comment,
+ strlen (ics[i]->comment)) == 0))
+ && note == ics[i]->note)
+ return i;
+@@ -623,10 +623,10 @@ load_insn_classes (void)
+ int iclass;
+ char *name;
+ char *tmp;
+-
++
+ if (fgets (buf, sizeof (buf), fp) == NULL)
+ break;
+-
++
+ while (ISSPACE (buf[strlen (buf) - 1]))
+ buf[strlen (buf) - 1] = '\0';
+
+@@ -670,9 +670,9 @@ load_insn_classes (void)
+ }
+ if (*tmp == ',')
+ *tmp++ = '\0';
+-
++
+ ics[iclass]->subs = (int *)
+- xrealloc ((void *)ics[iclass]->subs,
++ xrealloc ((void *)ics[iclass]->subs,
+ (ics[iclass]->nsubs + 1) * sizeof (int));
+
+ sub = fetch_insn_class (subname, 1);
+@@ -682,7 +682,7 @@ load_insn_classes (void)
+ }
+
+ /* Make sure classes come before terminals. */
+- qsort ((void *)ics[iclass]->subs,
++ qsort ((void *)ics[iclass]->subs,
+ ics[iclass]->nsubs, sizeof(int), sub_compare);
+ }
+ fclose (fp);
+@@ -712,7 +712,7 @@ parse_resource_users (const char *ref, int **usersp, int *nusersp,
+ int iclass;
+ int create = 0;
+ char *name;
+-
++
+ while (ISSPACE (*tmp))
+ ++tmp;
+ name = tmp;
+@@ -720,7 +720,7 @@ parse_resource_users (const char *ref, int **usersp, int *nusersp,
+ ++tmp;
+ c = *tmp;
+ *tmp++ = '\0';
+-
++
+ xsect = strchr (name, '\\');
+ if ((notestr = strstr (name, "+")) != NULL)
+ {
+@@ -738,7 +738,7 @@ parse_resource_users (const char *ref, int **usersp, int *nusersp,
+ if (!xsect)
+ *notestr = '\0';
+ }
+- else
++ else
+ note = 0;
+
+ /* All classes are created when the insn class table is parsed;
+@@ -748,7 +748,7 @@ parse_resource_users (const char *ref, int **usersp, int *nusersp,
+ table). */
+ if (! CONST_STRNEQ (name, "IC:") || xsect != NULL)
+ create = 1;
+-
++
+ iclass = fetch_insn_class (name, create);
+ if (iclass != -1)
+ {
+@@ -788,7 +788,7 @@ parse_semantics (char *sem)
+ return IA64_DVS_SPECIFIC;
+ else if (strcmp (sem, "stop") == 0)
+ return IA64_DVS_STOP;
+- else
++ else
+ return IA64_DVS_OTHER;
+ }
+
+@@ -835,7 +835,7 @@ load_depfile (const char *filename, enum ia64_dependency_mode mode)
+ while (*tmp != ';')
+ ++tmp;
+ *tmp++ = '\0';
+-
++
+ while (ISSPACE (*tmp))
+ ++tmp;
+ regp = tmp;
+@@ -883,7 +883,7 @@ load_dependencies (void)
+ }
+
+ /* Is the given operand an indirect register file operand? */
+-static int
++static int
+ irf_operand (int op, const char *field)
+ {
+ if (!field)
+@@ -910,7 +910,7 @@ irf_operand (int op, const char *field)
+ /* Handle mov_ar, mov_br, mov_cr, move_dahr, mov_indirect, mov_ip, mov_pr,
+ * mov_psr, and mov_um insn classes. */
+ static int
+-in_iclass_mov_x (struct ia64_opcode *idesc, struct iclass *ic,
++in_iclass_mov_x (struct ia64_opcode *idesc, struct iclass *ic,
+ const char *format, const char *field)
+ {
+ int plain_mov = strcmp (idesc->name, "mov") == 0;
+@@ -1031,7 +1031,7 @@ in_iclass_mov_x (struct ia64_opcode *idesc, struct iclass *ic,
+
+ /* Is the given opcode in the given insn class? */
+ static int
+-in_iclass (struct ia64_opcode *idesc, struct iclass *ic,
++in_iclass (struct ia64_opcode *idesc, struct iclass *ic,
+ const char *format, const char *field, int *notep)
+ {
+ int i;
+@@ -1049,7 +1049,7 @@ in_iclass (struct ia64_opcode *idesc, struct iclass *ic,
+ {
+ warn (_("most recent format '%s'\nappears more restrictive than '%s'\n"),
+ ic->comment, format);
+- format = ic->comment;
++ format = ic->comment;
+ }
+ }
+ else
+@@ -1074,7 +1074,7 @@ in_iclass (struct ia64_opcode *idesc, struct iclass *ic,
+ int len = strlen(ic->name);
+
+ resolved = ((strncmp (ic->name, idesc->name, len) == 0)
+- && (idesc->name[len] == '\0'
++ && (idesc->name[len] == '\0'
+ || idesc->name[len] == '.'));
+
+ /* All break, nop, and hint variations must match exactly. */
+@@ -1162,7 +1162,7 @@ in_iclass (struct ia64_opcode *idesc, struct iclass *ic,
+ resolved = 0;
+ }
+
+- /* Misc brl variations ('.cond' is optional);
++ /* Misc brl variations ('.cond' is optional);
+ plain brl matches brl.cond. */
+ if (!resolved
+ && (strcmp (idesc->name, "brl") == 0
+@@ -1173,7 +1173,7 @@ in_iclass (struct ia64_opcode *idesc, struct iclass *ic,
+ }
+
+ /* Misc br variations ('.cond' is optional). */
+- if (!resolved
++ if (!resolved
+ && (strcmp (idesc->name, "br") == 0
+ || CONST_STRNEQ (idesc->name, "br."))
+ && strcmp (ic->name, "br.cond") == 0)
+@@ -1190,8 +1190,8 @@ in_iclass (struct ia64_opcode *idesc, struct iclass *ic,
+ /* probe variations. */
+ if (!resolved && CONST_STRNEQ (idesc->name, "probe"))
+ {
+- resolved = strcmp (ic->name, "probe") == 0
+- && !((strstr (idesc->name, "fault") != NULL)
++ resolved = strcmp (ic->name, "probe") == 0
++ && !((strstr (idesc->name, "fault") != NULL)
+ ^ (format && strstr (format, "M40") != NULL));
+ }
+
+@@ -1226,7 +1226,7 @@ in_iclass (struct ia64_opcode *idesc, struct iclass *ic,
+ resolved = in_iclass_mov_x (idesc, ic, format, field);
+ }
+
+- /* Keep track of this so we can flag any insn classes which aren't
++ /* Keep track of this so we can flag any insn classes which aren't
+ mapped onto at least one real insn. */
+ if (resolved)
+ ic->terminal_resolved = 1;
+@@ -1248,7 +1248,7 @@ in_iclass (struct ia64_opcode *idesc, struct iclass *ic,
+ break;
+ }
+ }
+-
++
+ /* If it's in this IC, add the IC note (if any) to the insn. */
+ if (resolved)
+ {
+@@ -1483,7 +1483,7 @@ lookup_specifier (const char *name)
+ return IA64_RS_PMD;
+ if (strstr (name, "RR#") != NULL)
+ return IA64_RS_RR;
+-
++
+ warn (_("Don't know how to specify # dependency %s\n"),
+ name);
+ }
+@@ -1514,7 +1514,7 @@ print_dependency_table (void)
+ {
+ int i, j;
+
+- if (debug)
++ if (debug)
+ {
+ for (i=0;i < iclen;i++)
+ {
+@@ -1530,7 +1530,7 @@ print_dependency_table (void)
+ ics[i]->name);
+ }
+ }
+- else
++ else
+ {
+ if (!ics[i]->terminal_resolved && !ics[i]->orphan)
+ {
+@@ -1556,16 +1556,16 @@ print_dependency_table (void)
+
+ if (debug > 1)
+ for (i = 0; i < rdepslen; i++)
+- {
++ {
+ static const char *mode_str[] = { "RAW", "WAW", "WAR" };
+
+ if (rdeps[i]->total_chks == 0)
+ {
+ if (rdeps[i]->total_regs)
+- warn (_("Warning: rsrc %s (%s) has no chks\n"),
++ warn (_("Warning: rsrc %s (%s) has no chks\n"),
+ rdeps[i]->name, mode_str[rdeps[i]->mode]);
+ else
+- warn (_("Warning: rsrc %s (%s) has no chks or regs\n"),
++ warn (_("Warning: rsrc %s (%s) has no chks or regs\n"),
+ rdeps[i]->name, mode_str[rdeps[i]->mode]);
+ }
+ else if (rdeps[i]->total_regs == 0)
+@@ -1579,7 +1579,7 @@ print_dependency_table (void)
+ for (i = 0; i < rdepslen; i++)
+ {
+ /* '%', '#', AR[], CR[], or PSR. indicates we need to specify the actual
+- resource used. */
++ resource used. */
+ int specifier = lookup_specifier (rdeps[i]->name);
+ int regindex = lookup_regindex (rdeps[i]->name, specifier);
+
+@@ -1633,11 +1633,11 @@ print_dependency_table (void)
+ printf (" { ");
+ if (opdeps[i]->chk == -1)
+ printf ("0, NULL, ");
+- else
++ else
+ printf ("NELS(dep%d), dep%d, ", opdeps[i]->chk, opdeps[i]->chk);
+ if (opdeps[i]->reg == -1)
+ printf ("0, NULL, ");
+- else
++ else
+ printf ("NELS(dep%d), dep%d, ", opdeps[i]->reg, opdeps[i]->reg);
+ printf ("},\n");
+ }
+@@ -1656,7 +1656,7 @@ insert_string (char *str)
+ {
+ strtabtotlen += 20;
+ string_table = (struct string_entry **)
+- xrealloc (string_table,
++ xrealloc (string_table,
+ sizeof (struct string_entry **) * strtabtotlen);
+ }
+
+@@ -1729,7 +1729,7 @@ make_bittree_entry (void)
+ res->bits_to_skip = 0;
+ return res;
+ }
+-
++
+
+ static struct disent *
+ add_dis_table_ent (struct disent *which, int insn, int order,
+@@ -1794,7 +1794,7 @@ insert_bit_table_ent (struct bittree *curr_ent, int bit, ia64_insn opcode,
+
+ if (bit == -1)
+ {
+- struct disent *nent = add_dis_table_ent (curr_ent->disent,
++ struct disent *nent = add_dis_table_ent (curr_ent->disent,
+ opcodenum, order,
+ completer_index);
+ curr_ent->disent = nent;
+@@ -1833,8 +1833,8 @@ add_dis_entry (struct bittree *first, ia64_insn opcode, ia64_insn mask,
+
+ if (ent->is_terminal)
+ {
+- insert_bit_table_ent (bittree, 40, newopcode, mask,
+- opcodenum, opcode_count - ent->order - 1,
++ insert_bit_table_ent (bittree, 40, newopcode, mask,
++ opcodenum, opcode_count - ent->order - 1,
+ (completer_index << 1) | 1);
+ }
+ completer_index <<= 1;
+@@ -2013,7 +2013,7 @@ gen_dis_table (struct bittree *ent)
+ else
+ idest = ent->disent->ournum;
+
+- /* If the destination offset for the if (bit is 1) test is less
++ /* If the destination offset for the if (bit is 1) test is less
+ than 256 bytes away, we can store it as 8-bits instead of 16;
+ the instruction has bit 5 set for the 16-bit address, and bit
+ 4 for the 8-bit address. Since we've already allocated 16
+@@ -2108,7 +2108,7 @@ gen_dis_table (struct bittree *ent)
+ {
+ if (ent->skip_flag)
+ printf ("%d: skipping %d\n", our_offset, ent->bits_to_skip);
+-
++
+ if (ent->bits[0] != NULL)
+ printf ("%d: if (0:%d) goto %d\n", our_offset, zero_count + 1,
+ zero_dest);
+@@ -2164,7 +2164,7 @@ generate_disassembler (void)
+
+ if (ptr->opcode->type != IA64_TYPE_DYN)
+ add_dis_entry (bittree,
+- ptr->opcode->opcode, ptr->opcode->mask,
++ ptr->opcode->opcode, ptr->opcode->mask,
+ ptr->main_index,
+ ptr->completers, 1);
+ }
+@@ -2189,7 +2189,7 @@ print_string_table (void)
+ for (x = 0; x < strtablen; x++)
+ {
+ int len;
+-
++
+ if (strlen (string_table[x]->s) > 75)
+ abort ();
+
+@@ -2291,7 +2291,7 @@ insert_gclist (struct completer_entry *ent)
+ end = i - 1;
+ else if (c == 0)
+ {
+- while (i > 0
++ while (i > 0
+ && ent->name->num == glist[i - 1]->name->num)
+ i--;
+
+@@ -2368,7 +2368,7 @@ compute_completer_bits (struct main_entry *ment, struct completer_entry *ent)
+
+ while (p != NULL && ! p->is_terminal)
+ p = p->parent;
+-
++
+ if (p != NULL)
+ p_bits = p->bits;
+ else
+@@ -2421,7 +2421,7 @@ collapse_redundant_completers (void)
+
+ /* Attach two lists of dependencies to each opcode.
+ 1) all resources which, when already marked in use, conflict with this
+- opcode (chks)
++ opcode (chks)
+ 2) all resources which must be marked in use when this opcode is used
+ (regs). */
+ static int
+@@ -2432,7 +2432,7 @@ insert_opcode_dependencies (struct ia64_opcode *opc,
+ (79) and cmpxchng has the most regs (54) so 100 here should be enough. */
+ int i;
+ int nregs = 0;
+- unsigned short regs[256];
++ unsigned short regs[256];
+ int nchks = 0;
+ unsigned short chks[256];
+ /* Flag insns for which no class matched; there should be none. */
+@@ -2504,7 +2504,7 @@ insert_opcode_dependencies (struct ia64_opcode *opc,
+
+ if (no_class_found)
+ warn (_("opcode %s has no class (ops %d %d %d)\n"),
+- opc->name,
++ opc->name,
+ opc->operands[0], opc->operands[1], opc->operands[2]);
+
+ return insert_dependencies (nchks, chks, nregs, regs);
+@@ -2600,7 +2600,7 @@ print_completer_entry (struct completer_entry *ent)
+ if (bits & 0xffffffff00000000LL)
+ abort ();
+ }
+-
++
+ printf (" { 0x%x, 0x%x, %d, %d, %d, %d, %d, %d },\n",
+ (int)bits,
+ (int)mask,
+@@ -2629,7 +2629,7 @@ opcodes_eq (struct ia64_opcode *opc1, struct ia64_opcode *opc2)
+ int x;
+ int plen1, plen2;
+
+- if ((opc1->mask != opc2->mask) || (opc1->type != opc2->type)
++ if ((opc1->mask != opc2->mask) || (opc1->type != opc2->type)
+ || (opc1->num_outputs != opc2->num_outputs)
+ || (opc1->flags != opc2->flags))
+ return 0;
+@@ -2664,7 +2664,7 @@ add_opcode_entry (struct ia64_opcode *opc)
+ name = insert_string (prefix);
+
+ /* Walk the list of opcode table entries. If it's a new
+- instruction, allocate and fill in a new entry. Note
++ instruction, allocate and fill in a new entry. Note
+ the main table is alphabetical by opcode name. */
+
+ while (*place != NULL)
+@@ -2766,7 +2766,7 @@ shrink (struct ia64_opcode *table)
+ /* Program options. */
+ #define OPTION_SRCDIR 200
+
+-struct option long_options[] =
++struct option long_options[] =
+ {
+ {"srcdir", required_argument, NULL, OPTION_SRCDIR},
+ {"debug", no_argument, NULL, 'd'},
+@@ -2796,7 +2796,7 @@ main (int argc, char **argv)
+ extern int chdir (char *);
+ char *srcdir = NULL;
+ int c;
+-
++
+ program_name = *argv;
+ xmalloc_set_program_name (program_name);
+
+@@ -2824,7 +2824,7 @@ main (int argc, char **argv)
+ if (optind != argc)
+ usage (stdout, 1);
+
+- if (srcdir != NULL)
++ if (srcdir != NULL)
+ if (chdir (srcdir) != 0)
+ fail (_("unable to change directory to \"%s\", errno = %s\n"),
+ srcdir, strerror (errno));
+--- a/opcodes/ia64-opc-m.c
++++ b/opcodes/ia64-opc-m.c
+@@ -190,7 +190,7 @@ struct ia64_opcode ia64_opcodes_m[] =
+ {"ptc.e", M0, OpX3X6b (1, 0, 0x34), {R3}, PRIV, 0, NULL},
+
+ #if 0
+-// old pre-psn variant with 2-bit hints;
++// old pre-psn variant with 2-bit hints;
+ // saved for reference
+ /* integer load */
+ {"ld1", M, OpMXX6aHint (4, 0, 0, 0x00, 0), {R1, MR3}, EMPTY},
+@@ -893,7 +893,7 @@ struct ia64_opcode ia64_opcodes_m[] =
+ #undef LDINCREG
+
+ #if 0
+-// old pre-psn variant with 2-bit hints;
++// old pre-psn variant with 2-bit hints;
+ // saved for reference
+
+ {"st1", M, OpMXX6aHint (4, 0, 0, 0x30, 0), {MR3, R2}, EMPTY},
+@@ -1281,7 +1281,7 @@ struct ia64_opcode ia64_opcodes_m[] =
+ #undef STINCIMMED
+
+ #if 0
+-// old pre-psn variant with 2-bit hints;
++// old pre-psn variant with 2-bit hints;
+ // saved for reference
+ /* Floating-point load. */
+ {"ldfs", M, OpMXX6aHint (6, 0, 0, 0x02, 0), {F1, MR3}, EMPTY},
+@@ -1718,7 +1718,7 @@ struct ia64_opcode ia64_opcodes_m[] =
+ #undef FLDINCREG
+
+ #if 0
+-// old pre-psn variant with 2-bit hints;
++// old pre-psn variant with 2-bit hints;
+ // saved for reference
+ /* Floating-point store. */
+ {"stfs", M, OpMXX6aHint (6, 0, 0, 0x32, 0), {MR3, F2}, EMPTY},
+--- a/opcodes/ip2k-asm.c
++++ b/opcodes/ip2k-asm.c
+@@ -58,7 +58,7 @@ parse_fr (CGEN_CPU_DESC cd,
+ {
+ const char *errmsg;
+ const char *old_strp;
+- char *afteroffset;
++ char *afteroffset;
+ enum cgen_parse_operand_result result_type;
+ bfd_vma value;
+ extern CGEN_KEYWORD ip2k_cgen_opval_register_names;
+@@ -107,7 +107,7 @@ parse_fr (CGEN_CPU_DESC cd,
+ }
+ else
+ {
+- *strp += 4;
++ *strp += 4;
+ *valuep = 0;
+ errmsg = NULL;
+ return errmsg;
+@@ -241,7 +241,7 @@ parse_addr16 (CGEN_CPU_DESC cd,
+ errmsg = _("parse_addr16: invalid opindex.");
+ return errmsg;
+ }
+-
++
+ errmsg = cgen_parse_address (cd, strp, opindex, code,
+ & result_type, & value);
+ if (errmsg == NULL)
+@@ -255,7 +255,7 @@ parse_addr16 (CGEN_CPU_DESC cd,
+ else
+ /* code = BFD_RELOC_IP2K_LOW8DATA. */
+ value &= 0x00FF;
+- }
++ }
+ *valuep = value;
+ }
+
+@@ -272,7 +272,7 @@ parse_addr16_cjp (CGEN_CPU_DESC cd,
+ enum cgen_parse_operand_result result_type;
+ bfd_reloc_code_real_type code = BFD_RELOC_NONE;
+ bfd_vma value;
+-
++
+ if (opindex == (CGEN_OPERAND_TYPE) IP2K_OPERAND_ADDR16CJP)
+ code = BFD_RELOC_IP2K_ADDR16CJP;
+ else if (opindex == (CGEN_OPERAND_TYPE) IP2K_OPERAND_ADDR16P)
+@@ -300,10 +300,10 @@ parse_addr16_cjp (CGEN_CPU_DESC cd,
+ are labels. */
+ *valuep = value;
+ }
+- else
++ else
+ errmsg = _("cgen_parse_address returned a symbol. Literal required.");
+ }
+- return errmsg;
++ return errmsg;
+ }
+
+ static const char *
+@@ -352,7 +352,7 @@ parse_lit8 (CGEN_CPU_DESC cd,
+ /* Parse %op operand. */
+ if (code != BFD_RELOC_NONE)
+ {
+- errmsg = cgen_parse_address (cd, strp, opindex, code,
++ errmsg = cgen_parse_address (cd, strp, opindex, code,
+ & result_type, & value);
+ if ((errmsg == NULL) &&
+ (result_type != CGEN_PARSE_OPERAND_RESULT_QUEUED))
+@@ -412,7 +412,7 @@ parse_bit3 (CGEN_CPU_DESC cd,
+ errmsg = _("Attempt to find bit index of 0");
+ return errmsg;
+ }
+-
++
+ if (mode == 1)
+ {
+ count = 31;
+@@ -431,7 +431,7 @@ parse_bit3 (CGEN_CPU_DESC cd,
+ value >>= 1;
+ }
+ }
+-
++
+ *valuep = count;
+ }
+
+@@ -514,7 +514,7 @@ ip2k_cgen_parse_operand (CGEN_CPU_DESC cd,
+ return errmsg;
+ }
+
+-cgen_parse_fn * const ip2k_cgen_parse_handlers[] =
++cgen_parse_fn * const ip2k_cgen_parse_handlers[] =
+ {
+ parse_insn_normal,
+ };
+@@ -544,9 +544,9 @@ CGEN_ASM_INIT_HOOK
+
+ Returns NULL for success, an error message for failure. */
+
+-char *
++char *
+ ip2k_cgen_build_insn_regex (CGEN_INSN *insn)
+-{
++{
+ CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
+ const char *mnem = CGEN_INSN_MNEMONIC (insn);
+ char rxbuf[CGEN_MAX_RX_ELEMENTS];
+@@ -585,18 +585,18 @@ ip2k_cgen_build_insn_regex (CGEN_INSN *insn)
+ /* Copy any remaining literals from the syntax string into the rx. */
+ for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn)
+ {
+- if (CGEN_SYNTAX_CHAR_P (* syn))
++ if (CGEN_SYNTAX_CHAR_P (* syn))
+ {
+ char c = CGEN_SYNTAX_CHAR (* syn);
+
+- switch (c)
++ switch (c)
+ {
+ /* Escape any regex metacharacters in the syntax. */
+- case '.': case '[': case '\\':
+- case '*': case '^': case '$':
++ case '.': case '[': case '\\':
++ case '*': case '^': case '$':
+
+ #ifdef CGEN_ESCAPE_EXTENDED_REGEX
+- case '?': case '{': case '}':
++ case '?': case '{': case '}':
+ case '(': case ')': case '*':
+ case '|': case '+': case ']':
+ #endif
+@@ -626,20 +626,20 @@ ip2k_cgen_build_insn_regex (CGEN_INSN *insn)
+ }
+
+ /* Trailing whitespace ok. */
+- * rx++ = '[';
+- * rx++ = ' ';
+- * rx++ = '\t';
+- * rx++ = ']';
+- * rx++ = '*';
++ * rx++ = '[';
++ * rx++ = ' ';
++ * rx++ = '\t';
++ * rx++ = ']';
++ * rx++ = '*';
+
+ /* But anchor it after that. */
+- * rx++ = '$';
++ * rx++ = '$';
+ * rx = '\0';
+
+ CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t));
+ reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB);
+
+- if (reg_err == 0)
++ if (reg_err == 0)
+ return NULL;
+ else
+ {
+@@ -838,7 +838,7 @@ ip2k_cgen_assemble_insn (CGEN_CPU_DESC cd,
+ const CGEN_INSN *insn = ilist->insn;
+ recognized_mnemonic = 1;
+
+-#ifdef CGEN_VALIDATE_INSN_SUPPORTED
++#ifdef CGEN_VALIDATE_INSN_SUPPORTED
+ /* Not usually needed as unsupported opcodes
+ shouldn't be in the hash lists. */
+ /* Is this insn supported by the selected cpu? */
+@@ -898,7 +898,7 @@ ip2k_cgen_assemble_insn (CGEN_CPU_DESC cd,
+ if (strlen (start) > 50)
+ /* xgettext:c-format */
+ sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start);
+- else
++ else
+ /* xgettext:c-format */
+ sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start);
+ }
+@@ -907,11 +907,11 @@ ip2k_cgen_assemble_insn (CGEN_CPU_DESC cd,
+ if (strlen (start) > 50)
+ /* xgettext:c-format */
+ sprintf (errbuf, _("bad instruction `%.50s...'"), start);
+- else
++ else
+ /* xgettext:c-format */
+ sprintf (errbuf, _("bad instruction `%.50s'"), start);
+ }
+-
++
+ *errmsg = errbuf;
+ return NULL;
+ }
+--- a/opcodes/ip2k-desc.c
++++ b/opcodes/ip2k-desc.c
+@@ -332,55 +332,55 @@ const CGEN_OPERAND ip2k_cgen_operand_table[] =
+ {
+ /* pc: program counter */
+ { "pc", IP2K_OPERAND_PC, HW_H_PC, 0, 0,
+- { 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_NIL] } },
++ { 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_NIL] } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* addr16cjp: 13-bit address */
+ { "addr16cjp", IP2K_OPERAND_ADDR16CJP, HW_H_UINT, 12, 13,
+- { 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_ADDR16CJP] } },
++ { 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_ADDR16CJP] } },
+ { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
+ /* fr: register */
+ { "fr", IP2K_OPERAND_FR, HW_H_REGISTERS, 8, 9,
+- { 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_REG] } },
++ { 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_REG] } },
+ { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
+ /* lit8: 8-bit signed literal */
+ { "lit8", IP2K_OPERAND_LIT8, HW_H_SINT, 7, 8,
+- { 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_IMM8] } },
++ { 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_IMM8] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* bitno: bit number */
+ { "bitno", IP2K_OPERAND_BITNO, HW_H_UINT, 11, 3,
+- { 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_BITNO] } },
++ { 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_BITNO] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* addr16p: page number */
+ { "addr16p", IP2K_OPERAND_ADDR16P, HW_H_UINT, 2, 3,
+- { 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_PAGE3] } },
++ { 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_PAGE3] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* addr16h: high 8 bits of address */
+ { "addr16h", IP2K_OPERAND_ADDR16H, HW_H_UINT, 7, 8,
+- { 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_IMM8] } },
++ { 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_IMM8] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* addr16l: low 8 bits of address */
+ { "addr16l", IP2K_OPERAND_ADDR16L, HW_H_UINT, 7, 8,
+- { 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_IMM8] } },
++ { 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_IMM8] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* reti3: reti flags */
+ { "reti3", IP2K_OPERAND_RETI3, HW_H_UINT, 2, 3,
+- { 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_RETI3] } },
++ { 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_RETI3] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* pabits: page bits */
+ { "pabits", IP2K_OPERAND_PABITS, HW_H_PABITS, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* zbit: zero bit */
+ { "zbit", IP2K_OPERAND_ZBIT, HW_H_ZBIT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* cbit: carry bit */
+ { "cbit", IP2K_OPERAND_CBIT, HW_H_CBIT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* dcbit: digit carry bit */
+ { "dcbit", IP2K_OPERAND_DCBIT, HW_H_DCBIT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* sentinel */
+ { 0, 0, 0, 0, 0,
+@@ -1118,7 +1118,7 @@ ip2k_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
+
+ /* Default to not allowing signed overflow. */
+ cd->signed_overflow_ok_p = 0;
+-
++
+ return (CGEN_CPU_DESC) cd;
+ }
+
+@@ -1158,7 +1158,7 @@ ip2k_cgen_cpu_close (CGEN_CPU_DESC cd)
+ for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
+ if (CGEN_INSN_RX (insns))
+ regfree (CGEN_INSN_RX (insns));
+- }
++ }
+
+ if (cd->macro_insn_table.init_entries)
+ free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
+--- a/opcodes/ip2k-dis.c
++++ b/opcodes/ip2k-dis.c
+@@ -290,7 +290,7 @@ ip2k_cgen_print_operand (CGEN_CPU_DESC cd,
+ }
+ }
+
+-cgen_print_fn * const ip2k_cgen_print_handlers[] =
++cgen_print_fn * const ip2k_cgen_print_handlers[] =
+ {
+ print_insn_normal,
+ };
+@@ -480,7 +480,7 @@ print_insn (CGEN_CPU_DESC cd,
+ int length;
+ unsigned long insn_value_cropped;
+
+-#ifdef CGEN_VALIDATE_INSN_SUPPORTED
++#ifdef CGEN_VALIDATE_INSN_SUPPORTED
+ /* Not needed as insn shouldn't be in hash lists if not supported. */
+ /* Supported by this cpu? */
+ if (! ip2k_cgen_insn_supported (cd, insn))
+@@ -498,7 +498,7 @@ print_insn (CGEN_CPU_DESC cd,
+ relevant part from the buffer. */
+ if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
+ (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
+- insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
++ insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
+ info->endian == BFD_ENDIAN_BIG);
+ else
+ insn_value_cropped = insn_value;
+@@ -617,7 +617,7 @@ print_insn_ip2k (bfd_vma pc, disassemble_info *info)
+ arch = info->arch;
+ if (arch == bfd_arch_unknown)
+ arch = CGEN_BFD_ARCH;
+-
++
+ /* There's no standard way to compute the machine or isa number
+ so we leave it to the target. */
+ #ifdef CGEN_COMPUTE_MACH
+@@ -658,7 +658,7 @@ print_insn_ip2k (bfd_vma pc, disassemble_info *info)
+ break;
+ }
+ }
+- }
++ }
+
+ /* If we haven't initialized yet, initialize the opcode table. */
+ if (! cd)
+--- a/opcodes/ip2k-ibld.c
++++ b/opcodes/ip2k-ibld.c
+@@ -154,7 +154,7 @@ insert_normal (CGEN_CPU_DESC cd,
+ {
+ long minval = - (1L << (length - 1));
+ unsigned long maxval = mask;
+-
++
+ if ((value > 0 && (unsigned long) value > maxval)
+ || value < minval)
+ {
+@@ -192,7 +192,7 @@ insert_normal (CGEN_CPU_DESC cd,
+ {
+ long minval = - (1L << (length - 1));
+ long maxval = (1L << (length - 1)) - 1;
+-
++
+ if (value < minval || value > maxval)
+ {
+ sprintf
+@@ -683,12 +683,12 @@ ip2k_cgen_extract_operand (CGEN_CPU_DESC cd,
+ return length;
+ }
+
+-cgen_insert_fn * const ip2k_cgen_insert_handlers[] =
++cgen_insert_fn * const ip2k_cgen_insert_handlers[] =
+ {
+ insert_insn_normal,
+ };
+
+-cgen_extract_fn * const ip2k_cgen_extract_handlers[] =
++cgen_extract_fn * const ip2k_cgen_extract_handlers[] =
+ {
+ extract_insn_normal,
+ };
+--- a/opcodes/ip2k-opc.c
++++ b/opcodes/ip2k-opc.c
+@@ -60,7 +60,7 @@ ip2k_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn)
+ /* No mach attribute? Assume it's supported for all machs. */
+ if (machs == 0)
+ return 1;
+-
++
+ return (machs & cd->machs) != 0;
+ }
+
+--- a/opcodes/iq2000-asm.c
++++ b/opcodes/iq2000-asm.c
+@@ -70,16 +70,16 @@ iq2000_cgen_isa_register (const char **strp)
+ int len;
+ int ch1, ch2;
+
+- if (**strp == 'r' || **strp == 'R')
++ if (**strp == 'r' || **strp == 'R')
+ {
+ len = strlen (*strp);
+- if (len == 2)
++ if (len == 2)
+ {
+ ch1 = (*strp)[1];
+ if ('0' <= ch1 && ch1 <= '9')
+ return 1;
+- }
+- else if (len == 3)
++ }
++ else if (len == 3)
+ {
+ ch1 = (*strp)[1];
+ ch2 = (*strp)[2];
+@@ -112,7 +112,7 @@ parse_mimm (CGEN_CPU_DESC cd,
+ else
+ {
+ long value;
+-
++
+ errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value);
+ if (errmsg == NULL)
+ {
+@@ -462,7 +462,7 @@ iq2000_cgen_parse_operand (CGEN_CPU_DESC cd,
+ return errmsg;
+ }
+
+-cgen_parse_fn * const iq2000_cgen_parse_handlers[] =
++cgen_parse_fn * const iq2000_cgen_parse_handlers[] =
+ {
+ parse_insn_normal,
+ };
+@@ -492,9 +492,9 @@ CGEN_ASM_INIT_HOOK
+
+ Returns NULL for success, an error message for failure. */
+
+-char *
++char *
+ iq2000_cgen_build_insn_regex (CGEN_INSN *insn)
+-{
++{
+ CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
+ const char *mnem = CGEN_INSN_MNEMONIC (insn);
+ char rxbuf[CGEN_MAX_RX_ELEMENTS];
+@@ -533,18 +533,18 @@ iq2000_cgen_build_insn_regex (CGEN_INSN *insn)
+ /* Copy any remaining literals from the syntax string into the rx. */
+ for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn)
+ {
+- if (CGEN_SYNTAX_CHAR_P (* syn))
++ if (CGEN_SYNTAX_CHAR_P (* syn))
+ {
+ char c = CGEN_SYNTAX_CHAR (* syn);
+
+- switch (c)
++ switch (c)
+ {
+ /* Escape any regex metacharacters in the syntax. */
+- case '.': case '[': case '\\':
+- case '*': case '^': case '$':
++ case '.': case '[': case '\\':
++ case '*': case '^': case '$':
+
+ #ifdef CGEN_ESCAPE_EXTENDED_REGEX
+- case '?': case '{': case '}':
++ case '?': case '{': case '}':
+ case '(': case ')': case '*':
+ case '|': case '+': case ']':
+ #endif
+@@ -574,20 +574,20 @@ iq2000_cgen_build_insn_regex (CGEN_INSN *insn)
+ }
+
+ /* Trailing whitespace ok. */
+- * rx++ = '[';
+- * rx++ = ' ';
+- * rx++ = '\t';
+- * rx++ = ']';
+- * rx++ = '*';
++ * rx++ = '[';
++ * rx++ = ' ';
++ * rx++ = '\t';
++ * rx++ = ']';
++ * rx++ = '*';
+
+ /* But anchor it after that. */
+- * rx++ = '$';
++ * rx++ = '$';
+ * rx = '\0';
+
+ CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t));
+ reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB);
+
+- if (reg_err == 0)
++ if (reg_err == 0)
+ return NULL;
+ else
+ {
+@@ -786,7 +786,7 @@ iq2000_cgen_assemble_insn (CGEN_CPU_DESC cd,
+ const CGEN_INSN *insn = ilist->insn;
+ recognized_mnemonic = 1;
+
+-#ifdef CGEN_VALIDATE_INSN_SUPPORTED
++#ifdef CGEN_VALIDATE_INSN_SUPPORTED
+ /* Not usually needed as unsupported opcodes
+ shouldn't be in the hash lists. */
+ /* Is this insn supported by the selected cpu? */
+@@ -846,7 +846,7 @@ iq2000_cgen_assemble_insn (CGEN_CPU_DESC cd,
+ if (strlen (start) > 50)
+ /* xgettext:c-format */
+ sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start);
+- else
++ else
+ /* xgettext:c-format */
+ sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start);
+ }
+@@ -855,11 +855,11 @@ iq2000_cgen_assemble_insn (CGEN_CPU_DESC cd,
+ if (strlen (start) > 50)
+ /* xgettext:c-format */
+ sprintf (errbuf, _("bad instruction `%.50s...'"), start);
+- else
++ else
+ /* xgettext:c-format */
+ sprintf (errbuf, _("bad instruction `%.50s'"), start);
+ }
+-
++
+ *errmsg = errbuf;
+ return NULL;
+ }
+--- a/opcodes/iq2000-desc.c
++++ b/opcodes/iq2000-desc.c
+@@ -316,131 +316,131 @@ const CGEN_OPERAND iq2000_cgen_operand_table[] =
+ {
+ /* pc: program counter */
+ { "pc", IQ2000_OPERAND_PC, HW_H_PC, 0, 0,
+- { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_NIL] } },
++ { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_NIL] } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* rs: register Rs */
+ { "rs", IQ2000_OPERAND_RS, HW_H_GR, 25, 5,
+- { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RS] } },
++ { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RS] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* rt: register Rt */
+ { "rt", IQ2000_OPERAND_RT, HW_H_GR, 20, 5,
+- { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RT] } },
++ { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RT] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* rd: register Rd */
+ { "rd", IQ2000_OPERAND_RD, HW_H_GR, 15, 5,
+- { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RD] } },
++ { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RD] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* rd-rs: register Rd from Rs */
+ { "rd-rs", IQ2000_OPERAND_RD_RS, HW_H_GR, 15, 10,
+- { 2, { (const PTR) &IQ2000_F_RD_RS_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &IQ2000_F_RD_RS_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+ /* rd-rt: register Rd from Rt */
+ { "rd-rt", IQ2000_OPERAND_RD_RT, HW_H_GR, 15, 10,
+- { 2, { (const PTR) &IQ2000_F_RD_RT_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &IQ2000_F_RD_RT_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+ /* rt-rs: register Rt from Rs */
+ { "rt-rs", IQ2000_OPERAND_RT_RS, HW_H_GR, 20, 10,
+- { 2, { (const PTR) &IQ2000_F_RT_RS_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &IQ2000_F_RT_RS_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+ /* shamt: shift amount */
+ { "shamt", IQ2000_OPERAND_SHAMT, HW_H_UINT, 10, 5,
+- { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_SHAMT] } },
++ { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_SHAMT] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* imm: immediate */
+ { "imm", IQ2000_OPERAND_IMM, HW_H_UINT, 15, 16,
+- { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_IMM] } },
++ { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_IMM] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* offset: pc-relative offset */
+ { "offset", IQ2000_OPERAND_OFFSET, HW_H_IADDR, 15, 16,
+- { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_OFFSET] } },
++ { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_OFFSET] } },
+ { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
+ /* baseoff: base register offset */
+ { "baseoff", IQ2000_OPERAND_BASEOFF, HW_H_IADDR, 15, 16,
+- { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_IMM] } },
++ { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_IMM] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* jmptarg: jump target */
+ { "jmptarg", IQ2000_OPERAND_JMPTARG, HW_H_IADDR, 15, 16,
+- { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_JTARG] } },
++ { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_JTARG] } },
+ { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
+ /* mask: mask */
+ { "mask", IQ2000_OPERAND_MASK, HW_H_UINT, 9, 4,
+- { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_MASK] } },
++ { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_MASK] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* maskq10: iq10 mask */
+ { "maskq10", IQ2000_OPERAND_MASKQ10, HW_H_UINT, 10, 5,
+- { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_MASKQ10] } },
++ { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_MASKQ10] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* maskl: mask left */
+ { "maskl", IQ2000_OPERAND_MASKL, HW_H_UINT, 4, 5,
+- { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_MASKL] } },
++ { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_MASKL] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* count: count */
+ { "count", IQ2000_OPERAND_COUNT, HW_H_UINT, 15, 7,
+- { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_COUNT] } },
++ { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_COUNT] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* _index: index */
+ { "_index", IQ2000_OPERAND__INDEX, HW_H_UINT, 8, 9,
+- { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_INDEX] } },
++ { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_INDEX] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* execode: execcode */
+ { "execode", IQ2000_OPERAND_EXECODE, HW_H_UINT, 25, 20,
+- { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_EXCODE] } },
++ { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_EXCODE] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* bytecount: byte count */
+ { "bytecount", IQ2000_OPERAND_BYTECOUNT, HW_H_UINT, 7, 8,
+- { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_BYTECOUNT] } },
++ { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_BYTECOUNT] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* cam-y: cam global opn y */
+ { "cam-y", IQ2000_OPERAND_CAM_Y, HW_H_UINT, 2, 3,
+- { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CAM_Y] } },
++ { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CAM_Y] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* cam-z: cam global mask z */
+ { "cam-z", IQ2000_OPERAND_CAM_Z, HW_H_UINT, 5, 3,
+- { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CAM_Z] } },
++ { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CAM_Z] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* cm-3func: CM 3 bit fn field */
+ { "cm-3func", IQ2000_OPERAND_CM_3FUNC, HW_H_UINT, 5, 3,
+- { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CM_3FUNC] } },
++ { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CM_3FUNC] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* cm-4func: CM 4 bit fn field */
+ { "cm-4func", IQ2000_OPERAND_CM_4FUNC, HW_H_UINT, 5, 4,
+- { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CM_4FUNC] } },
++ { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CM_4FUNC] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* cm-3z: CM 3 bit Z field */
+ { "cm-3z", IQ2000_OPERAND_CM_3Z, HW_H_UINT, 1, 2,
+- { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CM_3Z] } },
++ { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CM_3Z] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* cm-4z: CM 4 bit Z field */
+ { "cm-4z", IQ2000_OPERAND_CM_4Z, HW_H_UINT, 2, 3,
+- { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CM_4Z] } },
++ { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CM_4Z] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* base: base register */
+ { "base", IQ2000_OPERAND_BASE, HW_H_GR, 25, 5,
+- { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RS] } },
++ { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RS] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* maskr: mask right */
+ { "maskr", IQ2000_OPERAND_MASKR, HW_H_UINT, 25, 5,
+- { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RS] } },
++ { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RS] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* bitnum: bit number */
+ { "bitnum", IQ2000_OPERAND_BITNUM, HW_H_UINT, 20, 5,
+- { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RT] } },
++ { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RT] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* hi16: high 16 bit immediate */
+ { "hi16", IQ2000_OPERAND_HI16, HW_H_UINT, 15, 16,
+- { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_IMM] } },
++ { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_IMM] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* lo16: 16 bit signed immediate, for low */
+ { "lo16", IQ2000_OPERAND_LO16, HW_H_UINT, 15, 16,
+- { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_IMM] } },
++ { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_IMM] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* mlo16: negated 16 bit signed immediate */
+ { "mlo16", IQ2000_OPERAND_MLO16, HW_H_UINT, 15, 16,
+- { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_IMM] } },
++ { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_IMM] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* jmptargq10: iq10 21-bit jump offset */
+ { "jmptargq10", IQ2000_OPERAND_JMPTARGQ10, HW_H_IADDR, 20, 21,
+- { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_JTARGQ10] } },
++ { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_JTARGQ10] } },
+ { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
+ /* sentinel */
+ { 0, 0, 0, 0, 0,
+@@ -2123,7 +2123,7 @@ iq2000_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
+
+ /* Default to not allowing signed overflow. */
+ cd->signed_overflow_ok_p = 0;
+-
++
+ return (CGEN_CPU_DESC) cd;
+ }
+
+@@ -2163,7 +2163,7 @@ iq2000_cgen_cpu_close (CGEN_CPU_DESC cd)
+ for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
+ if (CGEN_INSN_RX (insns))
+ regfree (CGEN_INSN_RX (insns));
+- }
++ }
+
+ if (cd->macro_insn_table.init_entries)
+ free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
+--- a/opcodes/iq2000-dis.c
++++ b/opcodes/iq2000-dis.c
+@@ -191,7 +191,7 @@ iq2000_cgen_print_operand (CGEN_CPU_DESC cd,
+ }
+ }
+
+-cgen_print_fn * const iq2000_cgen_print_handlers[] =
++cgen_print_fn * const iq2000_cgen_print_handlers[] =
+ {
+ print_insn_normal,
+ };
+@@ -381,7 +381,7 @@ print_insn (CGEN_CPU_DESC cd,
+ int length;
+ unsigned long insn_value_cropped;
+
+-#ifdef CGEN_VALIDATE_INSN_SUPPORTED
++#ifdef CGEN_VALIDATE_INSN_SUPPORTED
+ /* Not needed as insn shouldn't be in hash lists if not supported. */
+ /* Supported by this cpu? */
+ if (! iq2000_cgen_insn_supported (cd, insn))
+@@ -399,7 +399,7 @@ print_insn (CGEN_CPU_DESC cd,
+ relevant part from the buffer. */
+ if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
+ (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
+- insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
++ insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
+ info->endian == BFD_ENDIAN_BIG);
+ else
+ insn_value_cropped = insn_value;
+@@ -518,7 +518,7 @@ print_insn_iq2000 (bfd_vma pc, disassemble_info *info)
+ arch = info->arch;
+ if (arch == bfd_arch_unknown)
+ arch = CGEN_BFD_ARCH;
+-
++
+ /* There's no standard way to compute the machine or isa number
+ so we leave it to the target. */
+ #ifdef CGEN_COMPUTE_MACH
+@@ -559,7 +559,7 @@ print_insn_iq2000 (bfd_vma pc, disassemble_info *info)
+ break;
+ }
+ }
+- }
++ }
+
+ /* If we haven't initialized yet, initialize the opcode table. */
+ if (! cd)
+--- a/opcodes/iq2000-ibld.c
++++ b/opcodes/iq2000-ibld.c
+@@ -154,7 +154,7 @@ insert_normal (CGEN_CPU_DESC cd,
+ {
+ long minval = - (1L << (length - 1));
+ unsigned long maxval = mask;
+-
++
+ if ((value > 0 && (unsigned long) value > maxval)
+ || value < minval)
+ {
+@@ -192,7 +192,7 @@ insert_normal (CGEN_CPU_DESC cd,
+ {
+ long minval = - (1L << (length - 1));
+ long maxval = (1L << (length - 1)) - 1;
+-
++
+ if (value < minval || value > maxval)
+ {
+ sprintf
+@@ -889,12 +889,12 @@ iq2000_cgen_extract_operand (CGEN_CPU_DESC cd,
+ return length;
+ }
+
+-cgen_insert_fn * const iq2000_cgen_insert_handlers[] =
++cgen_insert_fn * const iq2000_cgen_insert_handlers[] =
+ {
+ insert_insn_normal,
+ };
+
+-cgen_extract_fn * const iq2000_cgen_extract_handlers[] =
++cgen_extract_fn * const iq2000_cgen_extract_handlers[] =
+ {
+ extract_insn_normal,
+ };
+--- a/opcodes/lm32-asm.c
++++ b/opcodes/lm32-asm.c
+@@ -352,7 +352,7 @@ lm32_cgen_parse_operand (CGEN_CPU_DESC cd,
+ return errmsg;
+ }
+
+-cgen_parse_fn * const lm32_cgen_parse_handlers[] =
++cgen_parse_fn * const lm32_cgen_parse_handlers[] =
+ {
+ parse_insn_normal,
+ };
+@@ -382,9 +382,9 @@ CGEN_ASM_INIT_HOOK
+
+ Returns NULL for success, an error message for failure. */
+
+-char *
++char *
+ lm32_cgen_build_insn_regex (CGEN_INSN *insn)
+-{
++{
+ CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
+ const char *mnem = CGEN_INSN_MNEMONIC (insn);
+ char rxbuf[CGEN_MAX_RX_ELEMENTS];
+@@ -423,18 +423,18 @@ lm32_cgen_build_insn_regex (CGEN_INSN *insn)
+ /* Copy any remaining literals from the syntax string into the rx. */
+ for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn)
+ {
+- if (CGEN_SYNTAX_CHAR_P (* syn))
++ if (CGEN_SYNTAX_CHAR_P (* syn))
+ {
+ char c = CGEN_SYNTAX_CHAR (* syn);
+
+- switch (c)
++ switch (c)
+ {
+ /* Escape any regex metacharacters in the syntax. */
+- case '.': case '[': case '\\':
+- case '*': case '^': case '$':
++ case '.': case '[': case '\\':
++ case '*': case '^': case '$':
+
+ #ifdef CGEN_ESCAPE_EXTENDED_REGEX
+- case '?': case '{': case '}':
++ case '?': case '{': case '}':
+ case '(': case ')': case '*':
+ case '|': case '+': case ']':
+ #endif
+@@ -464,20 +464,20 @@ lm32_cgen_build_insn_regex (CGEN_INSN *insn)
+ }
+
+ /* Trailing whitespace ok. */
+- * rx++ = '[';
+- * rx++ = ' ';
+- * rx++ = '\t';
+- * rx++ = ']';
+- * rx++ = '*';
++ * rx++ = '[';
++ * rx++ = ' ';
++ * rx++ = '\t';
++ * rx++ = ']';
++ * rx++ = '*';
+
+ /* But anchor it after that. */
+- * rx++ = '$';
++ * rx++ = '$';
+ * rx = '\0';
+
+ CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t));
+ reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB);
+
+- if (reg_err == 0)
++ if (reg_err == 0)
+ return NULL;
+ else
+ {
+@@ -676,7 +676,7 @@ lm32_cgen_assemble_insn (CGEN_CPU_DESC cd,
+ const CGEN_INSN *insn = ilist->insn;
+ recognized_mnemonic = 1;
+
+-#ifdef CGEN_VALIDATE_INSN_SUPPORTED
++#ifdef CGEN_VALIDATE_INSN_SUPPORTED
+ /* Not usually needed as unsupported opcodes
+ shouldn't be in the hash lists. */
+ /* Is this insn supported by the selected cpu? */
+@@ -736,7 +736,7 @@ lm32_cgen_assemble_insn (CGEN_CPU_DESC cd,
+ if (strlen (start) > 50)
+ /* xgettext:c-format */
+ sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start);
+- else
++ else
+ /* xgettext:c-format */
+ sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start);
+ }
+@@ -745,11 +745,11 @@ lm32_cgen_assemble_insn (CGEN_CPU_DESC cd,
+ if (strlen (start) > 50)
+ /* xgettext:c-format */
+ sprintf (errbuf, _("bad instruction `%.50s...'"), start);
+- else
++ else
+ /* xgettext:c-format */
+ sprintf (errbuf, _("bad instruction `%.50s'"), start);
+ }
+-
++
+ *errmsg = errbuf;
+ return NULL;
+ }
+--- a/opcodes/lm32-desc.c
++++ b/opcodes/lm32-desc.c
+@@ -274,75 +274,75 @@ const CGEN_OPERAND lm32_cgen_operand_table[] =
+ {
+ /* pc: program counter */
+ { "pc", LM32_OPERAND_PC, HW_H_PC, 0, 0,
+- { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_NIL] } },
++ { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_NIL] } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* r0: register 0 */
+ { "r0", LM32_OPERAND_R0, HW_H_GR, 25, 5,
+- { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_R0] } },
++ { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_R0] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* r1: register 1 */
+ { "r1", LM32_OPERAND_R1, HW_H_GR, 20, 5,
+- { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_R1] } },
++ { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_R1] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* r2: register 2 */
+ { "r2", LM32_OPERAND_R2, HW_H_GR, 15, 5,
+- { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_R2] } },
++ { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_R2] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* shift: shift amout */
+ { "shift", LM32_OPERAND_SHIFT, HW_H_UINT, 4, 5,
+- { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_SHIFT] } },
++ { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_SHIFT] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* imm: signed immediate */
+ { "imm", LM32_OPERAND_IMM, HW_H_SINT, 15, 16,
+- { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_IMM] } },
++ { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_IMM] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* uimm: unsigned immediate */
+ { "uimm", LM32_OPERAND_UIMM, HW_H_UINT, 15, 16,
+- { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_UIMM] } },
++ { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_UIMM] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* branch: branch offset */
+ { "branch", LM32_OPERAND_BRANCH, HW_H_IADDR, 15, 16,
+- { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_BRANCH] } },
++ { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_BRANCH] } },
+ { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
+ /* call: call offset */
+ { "call", LM32_OPERAND_CALL, HW_H_IADDR, 25, 26,
+- { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_CALL] } },
++ { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_CALL] } },
+ { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
+ /* csr: csr */
+ { "csr", LM32_OPERAND_CSR, HW_H_CSR, 25, 5,
+- { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_CSR] } },
++ { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_CSR] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* user: user */
+ { "user", LM32_OPERAND_USER, HW_H_UINT, 10, 11,
+- { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_USER] } },
++ { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_USER] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* exception: exception */
+ { "exception", LM32_OPERAND_EXCEPTION, HW_H_UINT, 25, 26,
+- { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_EXCEPTION] } },
++ { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_EXCEPTION] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* hi16: high 16-bit immediate */
+ { "hi16", LM32_OPERAND_HI16, HW_H_UINT, 15, 16,
+- { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_UIMM] } },
++ { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_UIMM] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* lo16: low 16-bit immediate */
+ { "lo16", LM32_OPERAND_LO16, HW_H_UINT, 15, 16,
+- { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_UIMM] } },
++ { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_UIMM] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* gp16: gp relative 16-bit immediate */
+ { "gp16", LM32_OPERAND_GP16, HW_H_SINT, 15, 16,
+- { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_IMM] } },
++ { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_IMM] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* got16: got 16-bit immediate */
+ { "got16", LM32_OPERAND_GOT16, HW_H_SINT, 15, 16,
+- { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_IMM] } },
++ { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_IMM] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* gotoffhi16: got offset high 16-bit immediate */
+ { "gotoffhi16", LM32_OPERAND_GOTOFFHI16, HW_H_SINT, 15, 16,
+- { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_IMM] } },
++ { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_IMM] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* gotofflo16: got offset low 16-bit immediate */
+ { "gotofflo16", LM32_OPERAND_GOTOFFLO16, HW_H_SINT, 15, 16,
+- { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_IMM] } },
++ { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_IMM] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* sentinel */
+ { 0, 0, 0, 0, 0,
+@@ -1105,7 +1105,7 @@ lm32_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
+
+ /* Default to not allowing signed overflow. */
+ cd->signed_overflow_ok_p = 0;
+-
++
+ return (CGEN_CPU_DESC) cd;
+ }
+
+@@ -1145,7 +1145,7 @@ lm32_cgen_cpu_close (CGEN_CPU_DESC cd)
+ for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
+ if (CGEN_INSN_RX (insns))
+ regfree (CGEN_INSN_RX (insns));
+- }
++ }
+
+ if (cd->macro_insn_table.init_entries)
+ free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
+--- a/opcodes/lm32-dis.c
++++ b/opcodes/lm32-dis.c
+@@ -149,7 +149,7 @@ lm32_cgen_print_operand (CGEN_CPU_DESC cd,
+ }
+ }
+
+-cgen_print_fn * const lm32_cgen_print_handlers[] =
++cgen_print_fn * const lm32_cgen_print_handlers[] =
+ {
+ print_insn_normal,
+ };
+@@ -339,7 +339,7 @@ print_insn (CGEN_CPU_DESC cd,
+ int length;
+ unsigned long insn_value_cropped;
+
+-#ifdef CGEN_VALIDATE_INSN_SUPPORTED
++#ifdef CGEN_VALIDATE_INSN_SUPPORTED
+ /* Not needed as insn shouldn't be in hash lists if not supported. */
+ /* Supported by this cpu? */
+ if (! lm32_cgen_insn_supported (cd, insn))
+@@ -357,7 +357,7 @@ print_insn (CGEN_CPU_DESC cd,
+ relevant part from the buffer. */
+ if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
+ (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
+- insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
++ insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
+ info->endian == BFD_ENDIAN_BIG);
+ else
+ insn_value_cropped = insn_value;
+@@ -476,7 +476,7 @@ print_insn_lm32 (bfd_vma pc, disassemble_info *info)
+ arch = info->arch;
+ if (arch == bfd_arch_unknown)
+ arch = CGEN_BFD_ARCH;
+-
++
+ /* There's no standard way to compute the machine or isa number
+ so we leave it to the target. */
+ #ifdef CGEN_COMPUTE_MACH
+@@ -517,7 +517,7 @@ print_insn_lm32 (bfd_vma pc, disassemble_info *info)
+ break;
+ }
+ }
+- }
++ }
+
+ /* If we haven't initialized yet, initialize the opcode table. */
+ if (! cd)
+--- a/opcodes/lm32-ibld.c
++++ b/opcodes/lm32-ibld.c
+@@ -154,7 +154,7 @@ insert_normal (CGEN_CPU_DESC cd,
+ {
+ long minval = - (1L << (length - 1));
+ unsigned long maxval = mask;
+-
++
+ if ((value > 0 && (unsigned long) value > maxval)
+ || value < minval)
+ {
+@@ -192,7 +192,7 @@ insert_normal (CGEN_CPU_DESC cd,
+ {
+ long minval = - (1L << (length - 1));
+ long maxval = (1L << (length - 1)) - 1;
+-
++
+ if (value < minval || value > maxval)
+ {
+ sprintf
+@@ -739,12 +739,12 @@ lm32_cgen_extract_operand (CGEN_CPU_DESC cd,
+ return length;
+ }
+
+-cgen_insert_fn * const lm32_cgen_insert_handlers[] =
++cgen_insert_fn * const lm32_cgen_insert_handlers[] =
+ {
+ insert_insn_normal,
+ };
+
+-cgen_extract_fn * const lm32_cgen_extract_handlers[] =
++cgen_extract_fn * const lm32_cgen_extract_handlers[] =
+ {
+ extract_insn_normal,
+ };
+--- a/opcodes/lm32-opc.h
++++ b/opcodes/lm32-opc.h
+@@ -31,7 +31,7 @@ This file is part of the GNU Binutils and/or GDB, the GNU debugger.
+ #define CGEN_VERBOSE_ASSEMBLER_ERRORS
+
+ #define CGEN_DIS_HASH_SIZE 64
+-#define CGEN_DIS_HASH(buf,value) ((value >> 26) & 0x3f)
++#define CGEN_DIS_HASH(buf,value) ((value >> 26) & 0x3f)
+
+ /* -- asm.c */
+ /* Enum declaration for lm32 instruction types. */
+--- a/opcodes/m10200-dis.c
++++ b/opcodes/m10200-dis.c
+@@ -20,7 +20,7 @@
+
+ #include "sysdep.h"
+ #include <stdio.h>
+-#include "opcode/mn10200.h"
++#include "opcode/mn10200.h"
+ #include "dis-asm.h"
+ #include "opintl.h"
+
+@@ -54,7 +54,7 @@ disassemble (bfd_vma memaddr,
+ mysize = 5;
+ else
+ abort ();
+-
++
+ if (op->format == FMT_2 || op->format == FMT_5)
+ extra_shift = 8;
+ else if (op->format == FMT_3
+@@ -70,7 +70,7 @@ disassemble (bfd_vma memaddr,
+ const unsigned char *opindex_ptr;
+ unsigned int nocomma;
+ int paren = 0;
+-
++
+ match = 1;
+ (*info->fprintf_func) (info->stream, "%s\t", op->name);
+
+@@ -104,7 +104,7 @@ disassemble (bfd_vma memaddr,
+ (*info->fprintf_func) (info->stream, ",");
+
+ nocomma = 0;
+-
++
+ if ((operand->flags & MN10200_OPERAND_DREG) != 0)
+ {
+ value = ((insn >> (operand->shift + extra_shift))
+@@ -144,7 +144,7 @@ disassemble (bfd_vma memaddr,
+ else if ((operand->flags & MN10200_OPERAND_MEMADDR) != 0)
+ (*info->print_address_func) (value, info);
+
+- else
++ else
+ (*info->fprintf_func) (info->stream, "%ld", value);
+ }
+ /* All done. */
+@@ -157,7 +157,7 @@ disassemble (bfd_vma memaddr,
+ (*info->fprintf_func) (info->stream, _("unknown\t0x%04lx"), insn);
+ }
+
+-int
++int
+ print_insn_mn10200 (bfd_vma memaddr, struct disassemble_info *info)
+ {
+ int status;
+--- a/opcodes/m10200-opc.c
++++ b/opcodes/m10200-opc.c
+@@ -24,7 +24,7 @@
+
+ const struct mn10200_operand mn10200_operands[] = {
+ #define UNUSED 0
+- {0, 0, 0},
++ {0, 0, 0},
+
+ /* dn register in the first register operand position. */
+ #define DN0 (UNUSED+1)
+@@ -130,7 +130,7 @@ const struct mn10200_operand mn10200_operands[] = {
+
+ /* Either an open paren or close paren. */
+ #define PAREN (SIMM16N+1)
+- {0, 0, MN10200_OPERAND_PAREN},
++ {0, 0, MN10200_OPERAND_PAREN},
+
+ /* dn register that appears in the first and second register positions. */
+ #define DN01 (PAREN+1)
+@@ -139,10 +139,10 @@ const struct mn10200_operand mn10200_operands[] = {
+ /* an register that appears in the first and second register positions. */
+ #define AN01 (DN01+1)
+ {2, 0, MN10200_OPERAND_AREG | MN10200_OPERAND_REPEATED},
+-} ;
++} ;
+
+-#define MEM(ADDR) PAREN, ADDR, PAREN
+-#define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN
++#define MEM(ADDR) PAREN, ADDR, PAREN
++#define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN
+
+ /* The opcode table.
+
+--- a/opcodes/m10300-opc.c
++++ b/opcodes/m10300-opc.c
+@@ -26,7 +26,7 @@
+
+ const struct mn10300_operand mn10300_operands[] = {
+ #define UNUSED 0
+- {0, 0, 0},
++ {0, 0, 0},
+
+ /* dn register in the first register operand position. */
+ #define DN0 (UNUSED+1)
+@@ -97,7 +97,7 @@ const struct mn10300_operand mn10300_operands[] = {
+ {16, 0, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR},
+
+ /* 32bit immediate, high 16 bits in the main instruction
+- word, 16bits in the extension word.
++ word, 16bits in the extension word.
+
+ The "bits" field indicates how many bits are in the
+ main instruction word for MN10300_OPERAND_SPLIT! */
+@@ -114,7 +114,7 @@ const struct mn10300_operand mn10300_operands[] = {
+
+ /* 32bit immediate, high 16 bits in the main instruction
+ word, 16bits in the extension word, low 16bits are left
+- shifted 8 places.
++ shifted 8 places.
+
+ The "bits" field indicates how many bits are in the
+ main instruction word for MN10300_OPERAND_SPLIT! */
+@@ -131,7 +131,7 @@ const struct mn10300_operand mn10300_operands[] = {
+
+ /* 32bit immediate, high 24 bits in the main instruction
+ word, 8 in the extension word, low 8 bits are left
+- shifted 16 places.
++ shifted 16 places.
+
+ The "bits" field indicates how many bits are in the
+ main instruction word for MN10300_OPERAND_SPLIT! */
+@@ -184,7 +184,7 @@ const struct mn10300_operand mn10300_operands[] = {
+
+ /* Either an open paren or close paren. */
+ #define PAREN (SIMM16+1)
+- {0, 0, MN10300_OPERAND_PAREN},
++ {0, 0, MN10300_OPERAND_PAREN},
+
+ /* dn register that appears in the first and second register positions. */
+ #define DN01 (PAREN+1)
+@@ -270,7 +270,7 @@ const struct mn10300_operand mn10300_operands[] = {
+
+ /* + for autoincrement */
+ #define PLUS (XRM2+1)
+- {0, 0, MN10300_OPERAND_PLUS},
++ {0, 0, MN10300_OPERAND_PLUS},
+
+ #define XRN02 (PLUS+1)
+ {4, 0, MN10300_OPERAND_XRREG | MN10300_OPERAND_REPEATED},
+@@ -420,12 +420,12 @@ const struct mn10300_operand mn10300_operands[] = {
+ #define FDN3 (FDN2+1)
+ {5, -12, MN10300_OPERAND_FDREG },
+
+-} ;
++} ;
+
+-#define MEM(ADDR) PAREN, ADDR, PAREN
+-#define MEMINC(ADDR) PAREN, ADDR, PLUS, PAREN
+-#define MEMINC2(ADDR,INC) PAREN, ADDR, PLUS, INC, PAREN
+-#define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN
++#define MEM(ADDR) PAREN, ADDR, PAREN
++#define MEMINC(ADDR) PAREN, ADDR, PLUS, PAREN
++#define MEMINC2(ADDR,INC) PAREN, ADDR, PLUS, INC, PAREN
++#define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN
+
+ /* The opcode table.
+
+@@ -1666,7 +1666,7 @@ const struct mn10300_opcode mn10300_opcodes[] = {
+ { "leq_mov", 0xf7e00008, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
+ { "lne_mov", 0xf7e00009, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
+ { "lra_mov", 0xf7e0000a, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
+-
++
+ { 0, 0, 0, 0, 0, 0, {0}},
+
+ } ;
+--- a/opcodes/m32c-asm.c
++++ b/opcodes/m32c-asm.c
+@@ -58,14 +58,14 @@ m32c_cgen_isa_register (const char **strp)
+ {
+ int u;
+ const char *s = *strp;
+- static char * m32c_register_names [] =
++ static char * m32c_register_names [] =
+ {
+ "r0", "r1", "r2", "r3", "r0l", "r0h", "r1l", "r1h",
+ "a0", "a1", "r2r0", "r3r1", "sp", "fb", "dct0", "dct1", "flg", "svf",
+ "drc0", "drc1", "dmd0", "dmd1", "intb", "svp", "vct", "isp", "dma0",
+ "dma1", "dra0", "dra1", "dsa0", "dsa1", 0
+ };
+-
++
+ for (u = 0; m32c_register_names[u]; u++)
+ {
+ int len = strlen (m32c_register_names[u]);
+@@ -148,7 +148,7 @@ parse_unsigned8 (CGEN_CPU_DESC cd, const char **strp,
+ return errmsg;
+ }
+
+- if (strncmp (*strp, "0x0", 3) == 0
++ if (strncmp (*strp, "0x0", 3) == 0
+ || (**strp == '0' && *(*strp + 1) != 'x'))
+ have_zero = 1;
+
+@@ -173,7 +173,7 @@ parse_signed4 (CGEN_CPU_DESC cd, const char **strp,
+ signed long value;
+ long have_zero = 0;
+
+- if (strncmp (*strp, "0x0", 3) == 0
++ if (strncmp (*strp, "0x0", 3) == 0
+ || (**strp == '0' && *(*strp + 1) != 'x'))
+ have_zero = 1;
+
+@@ -198,7 +198,7 @@ parse_signed4n (CGEN_CPU_DESC cd, const char **strp,
+ signed long value;
+ long have_zero = 0;
+
+- if (strncmp (*strp, "0x0", 3) == 0
++ if (strncmp (*strp, "0x0", 3) == 0
+ || (**strp == '0' && *(*strp + 1) != 'x'))
+ have_zero = 1;
+
+@@ -292,10 +292,10 @@ parse_unsigned16 (CGEN_CPU_DESC cd, const char **strp,
+ if (m32c_cgen_isa_register (strp))
+ return "Invalid literal"; /* Anything -- will not be seen. */
+
+- if (strncmp (*strp, "0x0", 3) == 0
++ if (strncmp (*strp, "0x0", 3) == 0
+ || (**strp == '0' && *(*strp + 1) != 'x'))
+ have_zero = 1;
+-
++
+ errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, & value);
+ if (errmsg)
+ return errmsg;
+@@ -381,7 +381,7 @@ parse_unsigned20 (CGEN_CPU_DESC cd, const char **strp,
+ {
+ const char *errmsg = 0;
+ unsigned long value;
+-
++
+ /* Don't successfully parse literals beginning with '['. */
+ if (**strp == '[')
+ return "Invalid literal"; /* Anything -- will not be seen. */
+@@ -407,7 +407,7 @@ parse_unsigned24 (CGEN_CPU_DESC cd, const char **strp,
+ {
+ const char *errmsg = 0;
+ unsigned long value;
+-
++
+ /* Don't successfully parse literals beginning with '['. */
+ if (**strp == '[')
+ return "Invalid literal"; /* Anything -- will not be seen. */
+@@ -453,7 +453,7 @@ parse_signed32 (CGEN_CPU_DESC cd, const char **strp,
+ {
+ const char *errmsg = 0;
+ signed long value;
+-
++
+ errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value);
+ if (errmsg)
+ return errmsg;
+@@ -486,7 +486,7 @@ parse_imm3_S (CGEN_CPU_DESC cd, const char **strp,
+ {
+ const char *errmsg = 0;
+ signed long value;
+-
++
+ errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value);
+ if (errmsg)
+ return errmsg;
+@@ -504,7 +504,7 @@ parse_bit3_S (CGEN_CPU_DESC cd, const char **strp,
+ {
+ const char *errmsg = 0;
+ signed long value;
+-
++
+ errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value);
+ if (errmsg)
+ return errmsg;
+@@ -591,7 +591,7 @@ parse_unsigned_bitbase (CGEN_CPU_DESC cd, const char **strp,
+
+ ++newp;
+
+- if (strncmp (newp, "0x0", 3) == 0
++ if (strncmp (newp, "0x0", 3) == 0
+ || (newp[0] == '0' && newp[1] != 'x'))
+ have_zero = 1;
+
+@@ -646,7 +646,7 @@ parse_signed_bitbase (CGEN_CPU_DESC cd, const char **strp,
+
+ ++newp;
+
+- if (strncmp (newp, "0x0", 3) == 0
++ if (strncmp (newp, "0x0", 3) == 0
+ || (newp[0] == '0' && newp[1] != 'x'))
+ have_zero = 1;
+
+@@ -731,7 +731,7 @@ static const char *
+ parse_suffix (const char **strp, char suffix)
+ {
+ const char *newp = *strp;
+-
++
+ if (**strp == ':' && TOLOWER (*(*strp + 1)) == suffix)
+ newp = *strp + 2;
+
+@@ -740,7 +740,7 @@ parse_suffix (const char **strp, char suffix)
+ *strp = newp;
+ return 0;
+ }
+-
++
+ return "Invalid suffix"; /* Anything -- will not be seen. */
+ }
+
+@@ -859,7 +859,7 @@ parse_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ {
+ const char *errmsg = 0;
+ int regno = 0;
+-
++
+ *valuep = 0;
+ while (**strp && **strp != ')')
+ {
+@@ -878,19 +878,19 @@ parse_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ errmsg = _("Register number is not valid");
+ regno = **strp - '0' + 4;
+ }
+-
++
+ else if (strncasecmp (*strp, "sb", 2) == 0 || strncasecmp (*strp, "SB", 2) == 0)
+ {
+ regno = 6;
+ ++*strp;
+ }
+-
++
+ else if (strncasecmp (*strp, "fb", 2) == 0 || strncasecmp (*strp, "FB", 2) == 0)
+ {
+ regno = 7;
+ ++*strp;
+ }
+-
++
+ if (push) /* Mask is reversed for push. */
+ *valuep |= 0x80 >> regno;
+ else
+@@ -1587,7 +1587,7 @@ m32c_cgen_parse_operand (CGEN_CPU_DESC cd,
+ return errmsg;
+ }
+
+-cgen_parse_fn * const m32c_cgen_parse_handlers[] =
++cgen_parse_fn * const m32c_cgen_parse_handlers[] =
+ {
+ parse_insn_normal,
+ };
+@@ -1617,9 +1617,9 @@ CGEN_ASM_INIT_HOOK
+
+ Returns NULL for success, an error message for failure. */
+
+-char *
++char *
+ m32c_cgen_build_insn_regex (CGEN_INSN *insn)
+-{
++{
+ CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
+ const char *mnem = CGEN_INSN_MNEMONIC (insn);
+ char rxbuf[CGEN_MAX_RX_ELEMENTS];
+@@ -1658,18 +1658,18 @@ m32c_cgen_build_insn_regex (CGEN_INSN *insn)
+ /* Copy any remaining literals from the syntax string into the rx. */
+ for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn)
+ {
+- if (CGEN_SYNTAX_CHAR_P (* syn))
++ if (CGEN_SYNTAX_CHAR_P (* syn))
+ {
+ char c = CGEN_SYNTAX_CHAR (* syn);
+
+- switch (c)
++ switch (c)
+ {
+ /* Escape any regex metacharacters in the syntax. */
+- case '.': case '[': case '\\':
+- case '*': case '^': case '$':
++ case '.': case '[': case '\\':
++ case '*': case '^': case '$':
+
+ #ifdef CGEN_ESCAPE_EXTENDED_REGEX
+- case '?': case '{': case '}':
++ case '?': case '{': case '}':
+ case '(': case ')': case '*':
+ case '|': case '+': case ']':
+ #endif
+@@ -1699,20 +1699,20 @@ m32c_cgen_build_insn_regex (CGEN_INSN *insn)
+ }
+
+ /* Trailing whitespace ok. */
+- * rx++ = '[';
+- * rx++ = ' ';
+- * rx++ = '\t';
+- * rx++ = ']';
+- * rx++ = '*';
++ * rx++ = '[';
++ * rx++ = ' ';
++ * rx++ = '\t';
++ * rx++ = ']';
++ * rx++ = '*';
+
+ /* But anchor it after that. */
+- * rx++ = '$';
++ * rx++ = '$';
+ * rx = '\0';
+
+ CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t));
+ reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB);
+
+- if (reg_err == 0)
++ if (reg_err == 0)
+ return NULL;
+ else
+ {
+@@ -1911,7 +1911,7 @@ m32c_cgen_assemble_insn (CGEN_CPU_DESC cd,
+ const CGEN_INSN *insn = ilist->insn;
+ recognized_mnemonic = 1;
+
+-#ifdef CGEN_VALIDATE_INSN_SUPPORTED
++#ifdef CGEN_VALIDATE_INSN_SUPPORTED
+ /* Not usually needed as unsupported opcodes
+ shouldn't be in the hash lists. */
+ /* Is this insn supported by the selected cpu? */
+@@ -1971,7 +1971,7 @@ m32c_cgen_assemble_insn (CGEN_CPU_DESC cd,
+ if (strlen (start) > 50)
+ /* xgettext:c-format */
+ sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start);
+- else
++ else
+ /* xgettext:c-format */
+ sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start);
+ }
+@@ -1980,11 +1980,11 @@ m32c_cgen_assemble_insn (CGEN_CPU_DESC cd,
+ if (strlen (start) > 50)
+ /* xgettext:c-format */
+ sprintf (errbuf, _("bad instruction `%.50s...'"), start);
+- else
++ else
+ /* xgettext:c-format */
+ sprintf (errbuf, _("bad instruction `%.50s'"), start);
+ }
+-
++
+ *errmsg = errbuf;
+ return NULL;
+ }
+--- a/opcodes/m32c-desc.c
++++ b/opcodes/m32c-desc.c
+@@ -1163,839 +1163,839 @@ const CGEN_OPERAND m32c_cgen_operand_table[] =
+ {
+ /* pc: program counter */
+ { "pc", M32C_OPERAND_PC, HW_H_PC, 0, 0,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_NIL] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_NIL] } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Src16RnQI: general register QI view */
+ { "Src16RnQI", M32C_OPERAND_SRC16RNQI, HW_H_GR_QI, 10, 2,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC16_RN] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC16_RN] } },
+ { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Src16RnHI: general register QH view */
+ { "Src16RnHI", M32C_OPERAND_SRC16RNHI, HW_H_GR_HI, 10, 2,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC16_RN] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC16_RN] } },
+ { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Src32RnUnprefixedQI: general register QI view */
+ { "Src32RnUnprefixedQI", M32C_OPERAND_SRC32RNUNPREFIXEDQI, HW_H_GR_QI, 10, 2,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_UNPREFIXED_QI] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_UNPREFIXED_QI] } },
+ { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Src32RnUnprefixedHI: general register HI view */
+ { "Src32RnUnprefixedHI", M32C_OPERAND_SRC32RNUNPREFIXEDHI, HW_H_GR_HI, 10, 2,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_UNPREFIXED_HI] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_UNPREFIXED_HI] } },
+ { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Src32RnUnprefixedSI: general register SI view */
+ { "Src32RnUnprefixedSI", M32C_OPERAND_SRC32RNUNPREFIXEDSI, HW_H_GR_SI, 10, 2,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_UNPREFIXED_SI] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_UNPREFIXED_SI] } },
+ { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Src32RnPrefixedQI: general register QI view */
+ { "Src32RnPrefixedQI", M32C_OPERAND_SRC32RNPREFIXEDQI, HW_H_GR_QI, 18, 2,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_PREFIXED_QI] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_PREFIXED_QI] } },
+ { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Src32RnPrefixedHI: general register HI view */
+ { "Src32RnPrefixedHI", M32C_OPERAND_SRC32RNPREFIXEDHI, HW_H_GR_HI, 18, 2,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_PREFIXED_HI] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_PREFIXED_HI] } },
+ { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Src32RnPrefixedSI: general register SI view */
+ { "Src32RnPrefixedSI", M32C_OPERAND_SRC32RNPREFIXEDSI, HW_H_GR_SI, 18, 2,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_PREFIXED_SI] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_PREFIXED_SI] } },
+ { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Src16An: address register */
+ { "Src16An", M32C_OPERAND_SRC16AN, HW_H_AR, 11, 1,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC16_AN] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC16_AN] } },
+ { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Src16AnQI: address register QI view */
+ { "Src16AnQI", M32C_OPERAND_SRC16ANQI, HW_H_AR_QI, 11, 1,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC16_AN] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC16_AN] } },
+ { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Src16AnHI: address register HI view */
+ { "Src16AnHI", M32C_OPERAND_SRC16ANHI, HW_H_AR_HI, 11, 1,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC16_AN] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC16_AN] } },
+ { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Src32AnUnprefixed: address register */
+ { "Src32AnUnprefixed", M32C_OPERAND_SRC32ANUNPREFIXED, HW_H_AR, 11, 1,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_UNPREFIXED] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_UNPREFIXED] } },
+ { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Src32AnUnprefixedQI: address register QI view */
+ { "Src32AnUnprefixedQI", M32C_OPERAND_SRC32ANUNPREFIXEDQI, HW_H_AR_QI, 11, 1,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_UNPREFIXED] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_UNPREFIXED] } },
+ { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Src32AnUnprefixedHI: address register HI view */
+ { "Src32AnUnprefixedHI", M32C_OPERAND_SRC32ANUNPREFIXEDHI, HW_H_AR_HI, 11, 1,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_UNPREFIXED] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_UNPREFIXED] } },
+ { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Src32AnUnprefixedSI: address register SI view */
+ { "Src32AnUnprefixedSI", M32C_OPERAND_SRC32ANUNPREFIXEDSI, HW_H_AR, 11, 1,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_UNPREFIXED] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_UNPREFIXED] } },
+ { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Src32AnPrefixed: address register */
+ { "Src32AnPrefixed", M32C_OPERAND_SRC32ANPREFIXED, HW_H_AR, 19, 1,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_PREFIXED] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_PREFIXED] } },
+ { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Src32AnPrefixedQI: address register QI view */
+ { "Src32AnPrefixedQI", M32C_OPERAND_SRC32ANPREFIXEDQI, HW_H_AR_QI, 19, 1,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_PREFIXED] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_PREFIXED] } },
+ { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Src32AnPrefixedHI: address register HI view */
+ { "Src32AnPrefixedHI", M32C_OPERAND_SRC32ANPREFIXEDHI, HW_H_AR_HI, 19, 1,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_PREFIXED] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_PREFIXED] } },
+ { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Src32AnPrefixedSI: address register SI view */
+ { "Src32AnPrefixedSI", M32C_OPERAND_SRC32ANPREFIXEDSI, HW_H_AR, 19, 1,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_PREFIXED] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_PREFIXED] } },
+ { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dst16RnQI: general register QI view */
+ { "Dst16RnQI", M32C_OPERAND_DST16RNQI, HW_H_GR_QI, 14, 2,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN] } },
+ { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dst16RnHI: general register HI view */
+ { "Dst16RnHI", M32C_OPERAND_DST16RNHI, HW_H_GR_HI, 14, 2,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN] } },
+ { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dst16RnSI: general register SI view */
+ { "Dst16RnSI", M32C_OPERAND_DST16RNSI, HW_H_GR_SI, 14, 2,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN] } },
+ { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dst16RnExtQI: general register QI/HI view for 'ext' insns */
+ { "Dst16RnExtQI", M32C_OPERAND_DST16RNEXTQI, HW_H_GR_EXT_QI, 14, 1,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN_EXT] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN_EXT] } },
+ { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dst32R0QI-S: general register QI view */
+ { "Dst32R0QI-S", M32C_OPERAND_DST32R0QI_S, HW_H_R0L, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dst32R0HI-S: general register HI view */
+ { "Dst32R0HI-S", M32C_OPERAND_DST32R0HI_S, HW_H_R0, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dst32RnUnprefixedQI: general register QI view */
+ { "Dst32RnUnprefixedQI", M32C_OPERAND_DST32RNUNPREFIXEDQI, HW_H_GR_QI, 8, 2,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_UNPREFIXED_QI] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_UNPREFIXED_QI] } },
+ { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dst32RnUnprefixedHI: general register HI view */
+ { "Dst32RnUnprefixedHI", M32C_OPERAND_DST32RNUNPREFIXEDHI, HW_H_GR_HI, 8, 2,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_UNPREFIXED_HI] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_UNPREFIXED_HI] } },
+ { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dst32RnUnprefixedSI: general register SI view */
+ { "Dst32RnUnprefixedSI", M32C_OPERAND_DST32RNUNPREFIXEDSI, HW_H_GR_SI, 8, 2,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_UNPREFIXED_SI] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_UNPREFIXED_SI] } },
+ { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dst32RnExtUnprefixedQI: general register QI view */
+ { "Dst32RnExtUnprefixedQI", M32C_OPERAND_DST32RNEXTUNPREFIXEDQI, HW_H_GR_EXT_QI, 9, 1,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_EXT_UNPREFIXED] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_EXT_UNPREFIXED] } },
+ { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dst32RnExtUnprefixedHI: general register HI view */
+ { "Dst32RnExtUnprefixedHI", M32C_OPERAND_DST32RNEXTUNPREFIXEDHI, HW_H_GR_EXT_HI, 9, 1,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_EXT_UNPREFIXED] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_EXT_UNPREFIXED] } },
+ { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dst32RnPrefixedQI: general register QI view */
+ { "Dst32RnPrefixedQI", M32C_OPERAND_DST32RNPREFIXEDQI, HW_H_GR_QI, 16, 2,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_PREFIXED_QI] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_PREFIXED_QI] } },
+ { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dst32RnPrefixedHI: general register HI view */
+ { "Dst32RnPrefixedHI", M32C_OPERAND_DST32RNPREFIXEDHI, HW_H_GR_HI, 16, 2,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_PREFIXED_HI] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_PREFIXED_HI] } },
+ { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dst32RnPrefixedSI: general register SI view */
+ { "Dst32RnPrefixedSI", M32C_OPERAND_DST32RNPREFIXEDSI, HW_H_GR_SI, 16, 2,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_PREFIXED_SI] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_PREFIXED_SI] } },
+ { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dst16RnQI-S: general register QI view */
+ { "Dst16RnQI-S", M32C_OPERAND_DST16RNQI_S, HW_H_R0L_R0H, 5, 1,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN_QI_S] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN_QI_S] } },
+ { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dst16AnQI-S: address register QI view */
+ { "Dst16AnQI-S", M32C_OPERAND_DST16ANQI_S, HW_H_AR_QI, 5, 1,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN_QI_S] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN_QI_S] } },
+ { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Bit16Rn: general register bit view */
+ { "Bit16Rn", M32C_OPERAND_BIT16RN, HW_H_GR_HI, 14, 2,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN] } },
+ { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Bit32RnPrefixed: general register bit view */
+ { "Bit32RnPrefixed", M32C_OPERAND_BIT32RNPREFIXED, HW_H_GR_QI, 16, 2,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_PREFIXED_QI] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_PREFIXED_QI] } },
+ { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Bit32RnUnprefixed: general register bit view */
+ { "Bit32RnUnprefixed", M32C_OPERAND_BIT32RNUNPREFIXED, HW_H_GR_QI, 8, 2,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_UNPREFIXED_QI] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_UNPREFIXED_QI] } },
+ { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* R0: r0 */
+ { "R0", M32C_OPERAND_R0, HW_H_R0, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* R1: r1 */
+ { "R1", M32C_OPERAND_R1, HW_H_R1, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* R2: r2 */
+ { "R2", M32C_OPERAND_R2, HW_H_R2, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* R3: r3 */
+ { "R3", M32C_OPERAND_R3, HW_H_R3, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* R0l: r0l */
+ { "R0l", M32C_OPERAND_R0L, HW_H_R0L, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* R0h: r0h */
+ { "R0h", M32C_OPERAND_R0H, HW_H_R0H, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* R2R0: r2r0 */
+ { "R2R0", M32C_OPERAND_R2R0, HW_H_R2R0, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* R3R1: r3r1 */
+ { "R3R1", M32C_OPERAND_R3R1, HW_H_R3R1, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* R1R2R0: r1r2r0 */
+ { "R1R2R0", M32C_OPERAND_R1R2R0, HW_H_R1R2R0, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dst16An: address register */
+ { "Dst16An", M32C_OPERAND_DST16AN, HW_H_AR, 15, 1,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN] } },
+ { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dst16AnQI: address register QI view */
+ { "Dst16AnQI", M32C_OPERAND_DST16ANQI, HW_H_AR_QI, 15, 1,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN] } },
+ { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dst16AnHI: address register HI view */
+ { "Dst16AnHI", M32C_OPERAND_DST16ANHI, HW_H_AR_HI, 15, 1,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN] } },
+ { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dst16AnSI: address register SI view */
+ { "Dst16AnSI", M32C_OPERAND_DST16ANSI, HW_H_AR_SI, 15, 1,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN] } },
+ { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dst16An-S: address register HI view */
+ { "Dst16An-S", M32C_OPERAND_DST16AN_S, HW_H_AR_HI, 4, 1,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN_S] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN_S] } },
+ { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dst32AnUnprefixed: address register */
+ { "Dst32AnUnprefixed", M32C_OPERAND_DST32ANUNPREFIXED, HW_H_AR, 9, 1,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } },
+ { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dst32AnUnprefixedQI: address register QI view */
+ { "Dst32AnUnprefixedQI", M32C_OPERAND_DST32ANUNPREFIXEDQI, HW_H_AR_QI, 9, 1,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } },
+ { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dst32AnUnprefixedHI: address register HI view */
+ { "Dst32AnUnprefixedHI", M32C_OPERAND_DST32ANUNPREFIXEDHI, HW_H_AR_HI, 9, 1,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } },
+ { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dst32AnUnprefixedSI: address register SI view */
+ { "Dst32AnUnprefixedSI", M32C_OPERAND_DST32ANUNPREFIXEDSI, HW_H_AR, 9, 1,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } },
+ { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dst32AnExtUnprefixed: address register */
+ { "Dst32AnExtUnprefixed", M32C_OPERAND_DST32ANEXTUNPREFIXED, HW_H_AR, 9, 1,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } },
+ { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dst32AnPrefixed: address register */
+ { "Dst32AnPrefixed", M32C_OPERAND_DST32ANPREFIXED, HW_H_AR, 17, 1,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_PREFIXED] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_PREFIXED] } },
+ { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dst32AnPrefixedQI: address register QI view */
+ { "Dst32AnPrefixedQI", M32C_OPERAND_DST32ANPREFIXEDQI, HW_H_AR_QI, 17, 1,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_PREFIXED] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_PREFIXED] } },
+ { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dst32AnPrefixedHI: address register HI view */
+ { "Dst32AnPrefixedHI", M32C_OPERAND_DST32ANPREFIXEDHI, HW_H_AR_HI, 17, 1,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_PREFIXED] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_PREFIXED] } },
+ { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dst32AnPrefixedSI: address register SI view */
+ { "Dst32AnPrefixedSI", M32C_OPERAND_DST32ANPREFIXEDSI, HW_H_AR, 17, 1,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_PREFIXED] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_PREFIXED] } },
+ { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Bit16An: address register bit view */
+ { "Bit16An", M32C_OPERAND_BIT16AN, HW_H_AR, 15, 1,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN] } },
+ { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Bit32AnPrefixed: address register bit */
+ { "Bit32AnPrefixed", M32C_OPERAND_BIT32ANPREFIXED, HW_H_AR, 17, 1,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_PREFIXED] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_PREFIXED] } },
+ { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Bit32AnUnprefixed: address register bit */
+ { "Bit32AnUnprefixed", M32C_OPERAND_BIT32ANUNPREFIXED, HW_H_AR, 9, 1,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } },
+ { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* A0: a0 */
+ { "A0", M32C_OPERAND_A0, HW_H_A0, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* A1: a1 */
+ { "A1", M32C_OPERAND_A1, HW_H_A1, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* sb: SB register */
+ { "sb", M32C_OPERAND_SB, HW_H_SB, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* fb: FB register */
+ { "fb", M32C_OPERAND_FB, HW_H_FB, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* sp: SP register */
+ { "sp", M32C_OPERAND_SP, HW_H_SP, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* SrcDst16-r0l-r0h-S-normal: r0l/r0h pair */
+ { "SrcDst16-r0l-r0h-S-normal", M32C_OPERAND_SRCDST16_R0L_R0H_S_NORMAL, HW_H_SINT, 5, 1,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_5_1] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_5_1] } },
+ { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Regsetpop: popm regset */
+ { "Regsetpop", M32C_OPERAND_REGSETPOP, HW_H_UINT, 8, 8,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_8_8] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_8_8] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Regsetpush: pushm regset */
+ { "Regsetpush", M32C_OPERAND_REGSETPUSH, HW_H_UINT, 8, 8,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_8_8] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_8_8] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Rn16-push-S: r0[lh] */
+ { "Rn16-push-S", M32C_OPERAND_RN16_PUSH_S, HW_H_GR_QI, 4, 1,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_4_1] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_4_1] } },
+ { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* An16-push-S: a[01] */
+ { "An16-push-S", M32C_OPERAND_AN16_PUSH_S, HW_H_AR_HI, 4, 1,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_4_1] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_4_1] } },
+ { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dsp-8-u6: unsigned 6 bit displacement at offset 8 bits */
+ { "Dsp-8-u6", M32C_OPERAND_DSP_8_U6, HW_H_UINT, 8, 6,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_U6] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_U6] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dsp-8-u8: unsigned 8 bit displacement at offset 8 bits */
+ { "Dsp-8-u8", M32C_OPERAND_DSP_8_U8, HW_H_UINT, 8, 8,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_U8] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_U8] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dsp-8-u16: unsigned 16 bit displacement at offset 8 bits */
+ { "Dsp-8-u16", M32C_OPERAND_DSP_8_U16, HW_H_UINT, 8, 16,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_U16] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_U16] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dsp-8-s8: signed 8 bit displacement at offset 8 bits */
+ { "Dsp-8-s8", M32C_OPERAND_DSP_8_S8, HW_H_SINT, 8, 8,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_S8] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_S8] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dsp-8-s24: signed 24 bit displacement at offset 8 bits */
+ { "Dsp-8-s24", M32C_OPERAND_DSP_8_S24, HW_H_SINT, 8, 24,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_S24] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_S24] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dsp-8-u24: unsigned 24 bit displacement at offset 8 bits */
+ { "Dsp-8-u24", M32C_OPERAND_DSP_8_U24, HW_H_UINT, 8, 24,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_U24] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_U24] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dsp-10-u6: unsigned 6 bit displacement at offset 10 bits */
+ { "Dsp-10-u6", M32C_OPERAND_DSP_10_U6, HW_H_UINT, 10, 6,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_10_U6] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_10_U6] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dsp-16-u8: unsigned 8 bit displacement at offset 16 bits */
+ { "Dsp-16-u8", M32C_OPERAND_DSP_16_U8, HW_H_UINT, 16, 8,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dsp-16-u16: unsigned 16 bit displacement at offset 16 bits */
+ { "Dsp-16-u16", M32C_OPERAND_DSP_16_U16, HW_H_UINT, 16, 16,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U16] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U16] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dsp-16-u20: unsigned 20 bit displacement at offset 16 bits */
+ { "Dsp-16-u20", M32C_OPERAND_DSP_16_U20, HW_H_UINT, 0, 24,
+- { 2, { (const PTR) &M32C_F_DSP_16_U24_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &M32C_F_DSP_16_U24_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dsp-16-u24: unsigned 24 bit displacement at offset 16 bits */
+ { "Dsp-16-u24", M32C_OPERAND_DSP_16_U24, HW_H_UINT, 0, 24,
+- { 2, { (const PTR) &M32C_F_DSP_16_U24_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &M32C_F_DSP_16_U24_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dsp-16-s8: signed 8 bit displacement at offset 16 bits */
+ { "Dsp-16-s8", M32C_OPERAND_DSP_16_S8, HW_H_SINT, 16, 8,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S8] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S8] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dsp-16-s16: signed 16 bit displacement at offset 16 bits */
+ { "Dsp-16-s16", M32C_OPERAND_DSP_16_S16, HW_H_SINT, 16, 16,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S16] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S16] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dsp-24-u8: unsigned 8 bit displacement at offset 24 bits */
+ { "Dsp-24-u8", M32C_OPERAND_DSP_24_U8, HW_H_UINT, 24, 8,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dsp-24-u16: unsigned 16 bit displacement at offset 24 bits */
+ { "Dsp-24-u16", M32C_OPERAND_DSP_24_U16, HW_H_UINT, 0, 16,
+- { 2, { (const PTR) &M32C_F_DSP_24_U16_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &M32C_F_DSP_24_U16_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dsp-24-u20: unsigned 20 bit displacement at offset 24 bits */
+ { "Dsp-24-u20", M32C_OPERAND_DSP_24_U20, HW_H_UINT, 0, 24,
+- { 2, { (const PTR) &M32C_F_DSP_24_U24_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &M32C_F_DSP_24_U24_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dsp-24-u24: unsigned 24 bit displacement at offset 24 bits */
+ { "Dsp-24-u24", M32C_OPERAND_DSP_24_U24, HW_H_UINT, 0, 24,
+- { 2, { (const PTR) &M32C_F_DSP_24_U24_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &M32C_F_DSP_24_U24_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dsp-24-s8: signed 8 bit displacement at offset 24 bits */
+ { "Dsp-24-s8", M32C_OPERAND_DSP_24_S8, HW_H_SINT, 24, 8,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_S8] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_S8] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dsp-24-s16: signed 16 bit displacement at offset 24 bits */
+ { "Dsp-24-s16", M32C_OPERAND_DSP_24_S16, HW_H_SINT, 0, 16,
+- { 2, { (const PTR) &M32C_F_DSP_24_S16_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &M32C_F_DSP_24_S16_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dsp-32-u8: unsigned 8 bit displacement at offset 32 bits */
+ { "Dsp-32-u8", M32C_OPERAND_DSP_32_U8, HW_H_UINT, 0, 8,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dsp-32-u16: unsigned 16 bit displacement at offset 32 bits */
+ { "Dsp-32-u16", M32C_OPERAND_DSP_32_U16, HW_H_UINT, 0, 16,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U16] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U16] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dsp-32-u24: unsigned 24 bit displacement at offset 32 bits */
+ { "Dsp-32-u24", M32C_OPERAND_DSP_32_U24, HW_H_UINT, 0, 24,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U24] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U24] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dsp-32-u20: unsigned 20 bit displacement at offset 32 bits */
+ { "Dsp-32-u20", M32C_OPERAND_DSP_32_U20, HW_H_UINT, 0, 24,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U24] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U24] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dsp-32-s8: signed 8 bit displacement at offset 32 bits */
+ { "Dsp-32-s8", M32C_OPERAND_DSP_32_S8, HW_H_SINT, 0, 8,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S8] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S8] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dsp-32-s16: signed 16 bit displacement at offset 32 bits */
+ { "Dsp-32-s16", M32C_OPERAND_DSP_32_S16, HW_H_SINT, 0, 16,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S16] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S16] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dsp-40-u8: unsigned 8 bit displacement at offset 40 bits */
+ { "Dsp-40-u8", M32C_OPERAND_DSP_40_U8, HW_H_UINT, 8, 8,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U8] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U8] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dsp-40-s8: signed 8 bit displacement at offset 40 bits */
+ { "Dsp-40-s8", M32C_OPERAND_DSP_40_S8, HW_H_SINT, 8, 8,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_S8] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_S8] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dsp-40-u16: unsigned 16 bit displacement at offset 40 bits */
+ { "Dsp-40-u16", M32C_OPERAND_DSP_40_U16, HW_H_UINT, 8, 16,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U16] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U16] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dsp-40-s16: signed 16 bit displacement at offset 40 bits */
+ { "Dsp-40-s16", M32C_OPERAND_DSP_40_S16, HW_H_SINT, 8, 16,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_S16] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_S16] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dsp-40-u20: unsigned 20 bit displacement at offset 40 bits */
+ { "Dsp-40-u20", M32C_OPERAND_DSP_40_U20, HW_H_UINT, 8, 20,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U20] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U20] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dsp-40-u24: unsigned 24 bit displacement at offset 40 bits */
+ { "Dsp-40-u24", M32C_OPERAND_DSP_40_U24, HW_H_UINT, 8, 24,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U24] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U24] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dsp-48-u8: unsigned 8 bit displacement at offset 48 bits */
+ { "Dsp-48-u8", M32C_OPERAND_DSP_48_U8, HW_H_UINT, 16, 8,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_U8] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_U8] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dsp-48-s8: signed 8 bit displacement at offset 48 bits */
+ { "Dsp-48-s8", M32C_OPERAND_DSP_48_S8, HW_H_SINT, 16, 8,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_S8] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_S8] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dsp-48-u16: unsigned 16 bit displacement at offset 48 bits */
+ { "Dsp-48-u16", M32C_OPERAND_DSP_48_U16, HW_H_UINT, 16, 16,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_U16] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_U16] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dsp-48-s16: signed 16 bit displacement at offset 48 bits */
+ { "Dsp-48-s16", M32C_OPERAND_DSP_48_S16, HW_H_SINT, 16, 16,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_S16] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_S16] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dsp-48-u20: unsigned 24 bit displacement at offset 40 bits */
+ { "Dsp-48-u20", M32C_OPERAND_DSP_48_U20, HW_H_UINT, 0, 24,
+- { 2, { (const PTR) &M32C_F_DSP_48_U20_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &M32C_F_DSP_48_U20_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Dsp-48-u24: unsigned 24 bit displacement at offset 48 bits */
+ { "Dsp-48-u24", M32C_OPERAND_DSP_48_U24, HW_H_UINT, 0, 24,
+- { 2, { (const PTR) &M32C_F_DSP_48_U24_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &M32C_F_DSP_48_U24_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Imm-8-s4: signed 4 bit immediate at offset 8 bits */
+ { "Imm-8-s4", M32C_OPERAND_IMM_8_S4, HW_H_SINT, 8, 4,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_8_S4] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_8_S4] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Imm-8-s4n: negated 4 bit immediate at offset 8 bits */
+ { "Imm-8-s4n", M32C_OPERAND_IMM_8_S4N, HW_H_SINT, 8, 4,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_8_S4] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_8_S4] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Imm-sh-8-s4: signed 4 bit shift immediate at offset 8 bits */
+ { "Imm-sh-8-s4", M32C_OPERAND_IMM_SH_8_S4, HW_H_SHIMM, 8, 4,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_8_S4] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_8_S4] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Imm-8-QI: signed 8 bit immediate at offset 8 bits */
+ { "Imm-8-QI", M32C_OPERAND_IMM_8_QI, HW_H_SINT, 8, 8,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_S8] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_S8] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Imm-8-HI: signed 16 bit immediate at offset 8 bits */
+ { "Imm-8-HI", M32C_OPERAND_IMM_8_HI, HW_H_SINT, 8, 16,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_S16] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_S16] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Imm-12-s4: signed 4 bit immediate at offset 12 bits */
+ { "Imm-12-s4", M32C_OPERAND_IMM_12_S4, HW_H_SINT, 12, 4,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_12_S4] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_12_S4] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Imm-12-s4n: negated 4 bit immediate at offset 12 bits */
+ { "Imm-12-s4n", M32C_OPERAND_IMM_12_S4N, HW_H_SINT, 12, 4,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_12_S4] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_12_S4] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Imm-sh-12-s4: signed 4 bit shift immediate at offset 12 bits */
+ { "Imm-sh-12-s4", M32C_OPERAND_IMM_SH_12_S4, HW_H_SHIMM, 12, 4,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_12_S4] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_12_S4] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Imm-13-u3: signed 3 bit immediate at offset 13 bits */
+ { "Imm-13-u3", M32C_OPERAND_IMM_13_U3, HW_H_SINT, 13, 3,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_13_U3] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_13_U3] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Imm-20-s4: signed 4 bit immediate at offset 20 bits */
+ { "Imm-20-s4", M32C_OPERAND_IMM_20_S4, HW_H_SINT, 20, 4,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_20_S4] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_20_S4] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Imm-sh-20-s4: signed 4 bit shift immediate at offset 12 bits */
+ { "Imm-sh-20-s4", M32C_OPERAND_IMM_SH_20_S4, HW_H_SHIMM, 20, 4,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_20_S4] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_20_S4] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Imm-16-QI: signed 8 bit immediate at offset 16 bits */
+ { "Imm-16-QI", M32C_OPERAND_IMM_16_QI, HW_H_SINT, 16, 8,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S8] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S8] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Imm-16-HI: signed 16 bit immediate at offset 16 bits */
+ { "Imm-16-HI", M32C_OPERAND_IMM_16_HI, HW_H_SINT, 16, 16,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S16] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S16] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Imm-16-SI: signed 32 bit immediate at offset 16 bits */
+ { "Imm-16-SI", M32C_OPERAND_IMM_16_SI, HW_H_SINT, 0, 32,
+- { 2, { (const PTR) &M32C_F_DSP_16_S32_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &M32C_F_DSP_16_S32_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Imm-24-QI: signed 8 bit immediate at offset 24 bits */
+ { "Imm-24-QI", M32C_OPERAND_IMM_24_QI, HW_H_SINT, 24, 8,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_S8] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_S8] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Imm-24-HI: signed 16 bit immediate at offset 24 bits */
+ { "Imm-24-HI", M32C_OPERAND_IMM_24_HI, HW_H_SINT, 0, 16,
+- { 2, { (const PTR) &M32C_F_DSP_24_S16_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &M32C_F_DSP_24_S16_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Imm-24-SI: signed 32 bit immediate at offset 24 bits */
+ { "Imm-24-SI", M32C_OPERAND_IMM_24_SI, HW_H_SINT, 0, 32,
+- { 2, { (const PTR) &M32C_F_DSP_24_S32_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &M32C_F_DSP_24_S32_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Imm-32-QI: signed 8 bit immediate at offset 32 bits */
+ { "Imm-32-QI", M32C_OPERAND_IMM_32_QI, HW_H_SINT, 0, 8,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S8] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S8] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Imm-32-SI: signed 32 bit immediate at offset 32 bits */
+ { "Imm-32-SI", M32C_OPERAND_IMM_32_SI, HW_H_SINT, 0, 32,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S32] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S32] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Imm-32-HI: signed 16 bit immediate at offset 32 bits */
+ { "Imm-32-HI", M32C_OPERAND_IMM_32_HI, HW_H_SINT, 0, 16,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S16] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S16] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Imm-40-QI: signed 8 bit immediate at offset 40 bits */
+ { "Imm-40-QI", M32C_OPERAND_IMM_40_QI, HW_H_SINT, 8, 8,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_S8] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_S8] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Imm-40-HI: signed 16 bit immediate at offset 40 bits */
+ { "Imm-40-HI", M32C_OPERAND_IMM_40_HI, HW_H_SINT, 8, 16,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_S16] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_S16] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Imm-40-SI: signed 32 bit immediate at offset 40 bits */
+ { "Imm-40-SI", M32C_OPERAND_IMM_40_SI, HW_H_SINT, 0, 32,
+- { 2, { (const PTR) &M32C_F_DSP_40_S32_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &M32C_F_DSP_40_S32_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Imm-48-QI: signed 8 bit immediate at offset 48 bits */
+ { "Imm-48-QI", M32C_OPERAND_IMM_48_QI, HW_H_SINT, 16, 8,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_S8] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_S8] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Imm-48-HI: signed 16 bit immediate at offset 48 bits */
+ { "Imm-48-HI", M32C_OPERAND_IMM_48_HI, HW_H_SINT, 16, 16,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_S16] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_S16] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Imm-48-SI: signed 32 bit immediate at offset 48 bits */
+ { "Imm-48-SI", M32C_OPERAND_IMM_48_SI, HW_H_SINT, 0, 32,
+- { 2, { (const PTR) &M32C_F_DSP_48_S32_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &M32C_F_DSP_48_S32_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Imm-56-QI: signed 8 bit immediate at offset 56 bits */
+ { "Imm-56-QI", M32C_OPERAND_IMM_56_QI, HW_H_SINT, 24, 8,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_56_S8] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_56_S8] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Imm-56-HI: signed 16 bit immediate at offset 56 bits */
+ { "Imm-56-HI", M32C_OPERAND_IMM_56_HI, HW_H_SINT, 0, 16,
+- { 2, { (const PTR) &M32C_F_DSP_56_S16_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &M32C_F_DSP_56_S16_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Imm-64-HI: signed 16 bit immediate at offset 64 bits */
+ { "Imm-64-HI", M32C_OPERAND_IMM_64_HI, HW_H_SINT, 0, 16,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_64_S16] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_64_S16] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Imm1-S: signed 1 bit immediate for short format binary insns */
+ { "Imm1-S", M32C_OPERAND_IMM1_S, HW_H_SINT, 2, 1,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM1_S] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM1_S] } },
+ { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Imm3-S: signed 3 bit immediate for short format binary insns */
+ { "Imm3-S", M32C_OPERAND_IMM3_S, HW_H_SINT, 2, 3,
+- { 2, { (const PTR) &M32C_F_IMM3_S_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &M32C_F_IMM3_S_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Bit3-S: 3 bit bit number */
+ { "Bit3-S", M32C_OPERAND_BIT3_S, HW_H_SINT, 2, 3,
+- { 2, { (const PTR) &M32C_F_IMM3_S_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &M32C_F_IMM3_S_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Bitno16R: bit number for indexing registers */
+ { "Bitno16R", M32C_OPERAND_BITNO16R, HW_H_UINT, 16, 8,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Bitno32Prefixed: bit number for indexing objects */
+ { "Bitno32Prefixed", M32C_OPERAND_BITNO32PREFIXED, HW_H_UINT, 21, 3,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_PREFIXED] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_PREFIXED] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Bitno32Unprefixed: bit number for indexing objects */
+ { "Bitno32Unprefixed", M32C_OPERAND_BITNO32UNPREFIXED, HW_H_UINT, 13, 3,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_UNPREFIXED] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_UNPREFIXED] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* BitBase16-16-u8: unsigned bit,base:8 at offset 16for m16c */
+ { "BitBase16-16-u8", M32C_OPERAND_BITBASE16_16_U8, HW_H_UINT, 16, 8,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* BitBase16-16-s8: signed bit,base:8 at offset 16for m16c */
+ { "BitBase16-16-s8", M32C_OPERAND_BITBASE16_16_S8, HW_H_SINT, 16, 8,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S8] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S8] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* BitBase16-16-u16: unsigned bit,base:16 at offset 16 for m16c */
+ { "BitBase16-16-u16", M32C_OPERAND_BITBASE16_16_U16, HW_H_UINT, 16, 16,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U16] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U16] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* BitBase16-8-u11-S: signed bit,base:11 at offset 16 for m16c */
+ { "BitBase16-8-u11-S", M32C_OPERAND_BITBASE16_8_U11_S, HW_H_UINT, 5, 11,
+- { 2, { (const PTR) &M32C_F_BITBASE16_U11_S_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &M32C_F_BITBASE16_U11_S_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* BitBase32-16-u11-Unprefixed: unsigned bit,base:11 at offset 16 for m32c */
+ { "BitBase32-16-u11-Unprefixed", M32C_OPERAND_BITBASE32_16_U11_UNPREFIXED, HW_H_UINT, 13, 11,
+- { 2, { (const PTR) &M32C_F_BITBASE32_16_U11_UNPREFIXED_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &M32C_F_BITBASE32_16_U11_UNPREFIXED_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* BitBase32-16-s11-Unprefixed: signed bit,base:11 at offset 16 for m32c */
+ { "BitBase32-16-s11-Unprefixed", M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED, HW_H_SINT, 13, 11,
+- { 2, { (const PTR) &M32C_F_BITBASE32_16_S11_UNPREFIXED_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &M32C_F_BITBASE32_16_S11_UNPREFIXED_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* BitBase32-16-u19-Unprefixed: unsigned bit,base:19 at offset 16 for m32c */
+ { "BitBase32-16-u19-Unprefixed", M32C_OPERAND_BITBASE32_16_U19_UNPREFIXED, HW_H_UINT, 13, 19,
+- { 2, { (const PTR) &M32C_F_BITBASE32_16_U19_UNPREFIXED_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &M32C_F_BITBASE32_16_U19_UNPREFIXED_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* BitBase32-16-s19-Unprefixed: signed bit,base:19 at offset 16 for m32c */
+ { "BitBase32-16-s19-Unprefixed", M32C_OPERAND_BITBASE32_16_S19_UNPREFIXED, HW_H_SINT, 13, 19,
+- { 2, { (const PTR) &M32C_F_BITBASE32_16_S19_UNPREFIXED_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &M32C_F_BITBASE32_16_S19_UNPREFIXED_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* BitBase32-16-u27-Unprefixed: unsigned bit,base:27 at offset 16 for m32c */
+ { "BitBase32-16-u27-Unprefixed", M32C_OPERAND_BITBASE32_16_U27_UNPREFIXED, HW_H_UINT, 0, 27,
+- { 3, { (const PTR) &M32C_F_BITBASE32_16_U27_UNPREFIXED_MULTI_IFIELD[0] } },
++ { 3, { (const PTR) &M32C_F_BITBASE32_16_U27_UNPREFIXED_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* BitBase32-24-u11-Prefixed: unsigned bit,base:11 at offset 24 for m32c */
+ { "BitBase32-24-u11-Prefixed", M32C_OPERAND_BITBASE32_24_U11_PREFIXED, HW_H_UINT, 21, 11,
+- { 2, { (const PTR) &M32C_F_BITBASE32_24_U11_PREFIXED_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &M32C_F_BITBASE32_24_U11_PREFIXED_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* BitBase32-24-s11-Prefixed: signed bit,base:11 at offset 24 for m32c */
+ { "BitBase32-24-s11-Prefixed", M32C_OPERAND_BITBASE32_24_S11_PREFIXED, HW_H_SINT, 21, 11,
+- { 2, { (const PTR) &M32C_F_BITBASE32_24_S11_PREFIXED_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &M32C_F_BITBASE32_24_S11_PREFIXED_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* BitBase32-24-u19-Prefixed: unsigned bit,base:19 at offset 24 for m32c */
+ { "BitBase32-24-u19-Prefixed", M32C_OPERAND_BITBASE32_24_U19_PREFIXED, HW_H_UINT, 0, 19,
+- { 3, { (const PTR) &M32C_F_BITBASE32_24_U19_PREFIXED_MULTI_IFIELD[0] } },
++ { 3, { (const PTR) &M32C_F_BITBASE32_24_U19_PREFIXED_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* BitBase32-24-s19-Prefixed: signed bit,base:19 at offset 24 for m32c */
+ { "BitBase32-24-s19-Prefixed", M32C_OPERAND_BITBASE32_24_S19_PREFIXED, HW_H_SINT, 0, 19,
+- { 3, { (const PTR) &M32C_F_BITBASE32_24_S19_PREFIXED_MULTI_IFIELD[0] } },
++ { 3, { (const PTR) &M32C_F_BITBASE32_24_S19_PREFIXED_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* BitBase32-24-u27-Prefixed: unsigned bit,base:27 at offset 24 for m32c */
+ { "BitBase32-24-u27-Prefixed", M32C_OPERAND_BITBASE32_24_U27_PREFIXED, HW_H_UINT, 0, 27,
+- { 3, { (const PTR) &M32C_F_BITBASE32_24_U27_PREFIXED_MULTI_IFIELD[0] } },
++ { 3, { (const PTR) &M32C_F_BITBASE32_24_U27_PREFIXED_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Lab-5-3: 3 bit label */
+ { "Lab-5-3", M32C_OPERAND_LAB_5_3, HW_H_IADDR, 5, 3,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_5_3] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_5_3] } },
+ { 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Lab32-jmp-s: 3 bit label */
+ { "Lab32-jmp-s", M32C_OPERAND_LAB32_JMP_S, HW_H_IADDR, 2, 3,
+- { 2, { (const PTR) &M32C_F_LAB32_JMP_S_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &M32C_F_LAB32_JMP_S_MULTI_IFIELD[0] } },
+ { 0|A(RELAX)|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Lab-8-8: 8 bit label */
+ { "Lab-8-8", M32C_OPERAND_LAB_8_8, HW_H_IADDR, 8, 8,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_8_8] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_8_8] } },
+ { 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Lab-8-16: 16 bit label */
+ { "Lab-8-16", M32C_OPERAND_LAB_8_16, HW_H_IADDR, 8, 16,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_8_16] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_8_16] } },
+ { 0|A(RELAX)|A(SIGN_OPT)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Lab-8-24: 24 bit label */
+ { "Lab-8-24", M32C_OPERAND_LAB_8_24, HW_H_IADDR, 8, 24,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_8_24] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_8_24] } },
+ { 0|A(RELAX)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Lab-16-8: 8 bit label */
+ { "Lab-16-8", M32C_OPERAND_LAB_16_8, HW_H_IADDR, 16, 8,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_16_8] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_16_8] } },
+ { 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Lab-24-8: 8 bit label */
+ { "Lab-24-8", M32C_OPERAND_LAB_24_8, HW_H_IADDR, 24, 8,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_24_8] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_24_8] } },
+ { 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Lab-32-8: 8 bit label */
+ { "Lab-32-8", M32C_OPERAND_LAB_32_8, HW_H_IADDR, 0, 8,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_32_8] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_32_8] } },
+ { 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Lab-40-8: 8 bit label */
+ { "Lab-40-8", M32C_OPERAND_LAB_40_8, HW_H_IADDR, 8, 8,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_40_8] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_40_8] } },
+ { 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* sbit: negative bit */
+ { "sbit", M32C_OPERAND_SBIT, HW_H_SBIT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* obit: overflow bit */
+ { "obit", M32C_OPERAND_OBIT, HW_H_OBIT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* zbit: zero bit */
+ { "zbit", M32C_OPERAND_ZBIT, HW_H_ZBIT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* cbit: carry bit */
+ { "cbit", M32C_OPERAND_CBIT, HW_H_CBIT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* ubit: stack ptr select bit */
+ { "ubit", M32C_OPERAND_UBIT, HW_H_UBIT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* ibit: interrupt enable bit */
+ { "ibit", M32C_OPERAND_IBIT, HW_H_IBIT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* bbit: reg bank select bit */
+ { "bbit", M32C_OPERAND_BBIT, HW_H_BBIT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* dbit: debug bit */
+ { "dbit", M32C_OPERAND_DBIT, HW_H_DBIT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* cond16-16: condition */
+ { "cond16-16", M32C_OPERAND_COND16_16, HW_H_COND16, 16, 8,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* cond16-24: condition */
+ { "cond16-24", M32C_OPERAND_COND16_24, HW_H_COND16, 24, 8,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* cond16-32: condition */
+ { "cond16-32", M32C_OPERAND_COND16_32, HW_H_COND16, 0, 8,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* cond32-16: condition */
+ { "cond32-16", M32C_OPERAND_COND32_16, HW_H_COND32, 16, 8,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* cond32-24: condition */
+ { "cond32-24", M32C_OPERAND_COND32_24, HW_H_COND32, 24, 8,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* cond32-32: condition */
+ { "cond32-32", M32C_OPERAND_COND32_32, HW_H_COND32, 0, 8,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* cond32-40: condition */
+ { "cond32-40", M32C_OPERAND_COND32_40, HW_H_COND32, 8, 8,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U8] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U8] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* cond16c: condition */
+ { "cond16c", M32C_OPERAND_COND16C, HW_H_COND16C, 12, 4,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_COND16] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_COND16] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* cond16j: condition */
+ { "cond16j", M32C_OPERAND_COND16J, HW_H_COND16J, 12, 4,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_COND16] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_COND16] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* cond16j5: condition */
+ { "cond16j5", M32C_OPERAND_COND16J5, HW_H_COND16J_5, 5, 3,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_COND16J_5] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_COND16J_5] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* cond32: condition */
+ { "cond32", M32C_OPERAND_COND32, HW_H_COND32, 9, 4,
+- { 2, { (const PTR) &M32C_F_COND32_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &M32C_F_COND32_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* cond32j: condition */
+ { "cond32j", M32C_OPERAND_COND32J, HW_H_COND32, 1, 4,
+- { 2, { (const PTR) &M32C_F_COND32J_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &M32C_F_COND32J_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* sccond32: scCND condition */
+ { "sccond32", M32C_OPERAND_SCCOND32, HW_H_COND32, 12, 4,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_COND16] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_COND16] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* flags16: flags */
+ { "flags16", M32C_OPERAND_FLAGS16, HW_H_FLAGS, 9, 3,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_9_3] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_9_3] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* flags32: flags */
+ { "flags32", M32C_OPERAND_FLAGS32, HW_H_FLAGS, 13, 3,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_13_3] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_13_3] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* cr16: control */
+ { "cr16", M32C_OPERAND_CR16, HW_H_CR_16, 9, 3,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_9_3] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_9_3] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* cr1-Unprefixed-32: control */
+ { "cr1-Unprefixed-32", M32C_OPERAND_CR1_UNPREFIXED_32, HW_H_CR1_32, 13, 3,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_13_3] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_13_3] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* cr1-Prefixed-32: control */
+ { "cr1-Prefixed-32", M32C_OPERAND_CR1_PREFIXED_32, HW_H_CR1_32, 21, 3,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_21_3] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_21_3] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* cr2-32: control */
+ { "cr2-32", M32C_OPERAND_CR2_32, HW_H_CR2_32, 13, 3,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_13_3] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_13_3] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* cr3-Unprefixed-32: control */
+ { "cr3-Unprefixed-32", M32C_OPERAND_CR3_UNPREFIXED_32, HW_H_CR3_32, 13, 3,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_13_3] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_13_3] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* cr3-Prefixed-32: control */
+ { "cr3-Prefixed-32", M32C_OPERAND_CR3_PREFIXED_32, HW_H_CR3_32, 21, 3,
+- { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_21_3] } },
++ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_21_3] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Z: Suffix for zero format insns */
+ { "Z", M32C_OPERAND_Z, HW_H_SINT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* S: Suffix for short format insns */
+ { "S", M32C_OPERAND_S, HW_H_SINT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* Q: Suffix for quick format insns */
+ { "Q", M32C_OPERAND_Q, HW_H_SINT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* G: Suffix for general format insns */
+ { "G", M32C_OPERAND_G, HW_H_SINT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* X: Empty suffix */
+ { "X", M32C_OPERAND_X, HW_H_SINT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* size: any size specifier */
+ { "size", M32C_OPERAND_SIZE, HW_H_SINT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* BitIndex: Bit Index for the next insn */
+ { "BitIndex", M32C_OPERAND_BITINDEX, HW_H_BIT_INDEX, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* SrcIndex: Source Index for the next insn */
+ { "SrcIndex", M32C_OPERAND_SRCINDEX, HW_H_SRC_INDEX, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* DstIndex: Destination Index for the next insn */
+ { "DstIndex", M32C_OPERAND_DSTINDEX, HW_H_DST_INDEX, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* NoRemainder: Place holder for when the remainder is not kept */
+ { "NoRemainder", M32C_OPERAND_NOREMAINDER, HW_H_NONE, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
+ /* src16-Rn-direct-QI: m16c Rn direct source QI */
+ /* src16-Rn-direct-HI: m16c Rn direct source HI */
+@@ -63136,7 +63136,7 @@ m32c_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
+
+ /* Default to not allowing signed overflow. */
+ cd->signed_overflow_ok_p = 0;
+-
++
+ return (CGEN_CPU_DESC) cd;
+ }
+
+@@ -63176,7 +63176,7 @@ m32c_cgen_cpu_close (CGEN_CPU_DESC cd)
+ for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
+ if (CGEN_INSN_RX (insns))
+ regfree (CGEN_INSN_RX (insns));
+- }
++ }
+
+ if (cd->macro_insn_table.init_entries)
+ free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
+--- a/opcodes/m32c-dis.c
++++ b/opcodes/m32c-dis.c
+@@ -203,7 +203,7 @@ print_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ int length ATTRIBUTE_UNUSED,
+ int push)
+ {
+- static char * m16c_register_names [] =
++ static char * m16c_register_names [] =
+ {
+ "r0", "r1", "r2", "r3", "a0", "a1", "sb", "fb"
+ };
+@@ -216,7 +216,7 @@ print_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ mask = 0x80;
+ else
+ mask = 1;
+-
++
+ if (value & mask)
+ {
+ (*info->fprintf_func) (info->stream, "%s", m16c_register_names [0]);
+@@ -893,7 +893,7 @@ m32c_cgen_print_operand (CGEN_CPU_DESC cd,
+ }
+ }
+
+-cgen_print_fn * const m32c_cgen_print_handlers[] =
++cgen_print_fn * const m32c_cgen_print_handlers[] =
+ {
+ print_insn_normal,
+ };
+@@ -1083,7 +1083,7 @@ print_insn (CGEN_CPU_DESC cd,
+ int length;
+ unsigned long insn_value_cropped;
+
+-#ifdef CGEN_VALIDATE_INSN_SUPPORTED
++#ifdef CGEN_VALIDATE_INSN_SUPPORTED
+ /* Not needed as insn shouldn't be in hash lists if not supported. */
+ /* Supported by this cpu? */
+ if (! m32c_cgen_insn_supported (cd, insn))
+@@ -1101,7 +1101,7 @@ print_insn (CGEN_CPU_DESC cd,
+ relevant part from the buffer. */
+ if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
+ (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
+- insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
++ insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
+ info->endian == BFD_ENDIAN_BIG);
+ else
+ insn_value_cropped = insn_value;
+@@ -1220,7 +1220,7 @@ print_insn_m32c (bfd_vma pc, disassemble_info *info)
+ arch = info->arch;
+ if (arch == bfd_arch_unknown)
+ arch = CGEN_BFD_ARCH;
+-
++
+ /* There's no standard way to compute the machine or isa number
+ so we leave it to the target. */
+ #ifdef CGEN_COMPUTE_MACH
+@@ -1261,7 +1261,7 @@ print_insn_m32c (bfd_vma pc, disassemble_info *info)
+ break;
+ }
+ }
+- }
++ }
+
+ /* If we haven't initialized yet, initialize the opcode table. */
+ if (! cd)
+--- a/opcodes/m32c-ibld.c
++++ b/opcodes/m32c-ibld.c
+@@ -154,7 +154,7 @@ insert_normal (CGEN_CPU_DESC cd,
+ {
+ long minval = - (1L << (length - 1));
+ unsigned long maxval = mask;
+-
++
+ if ((value > 0 && (unsigned long) value > maxval)
+ || value < minval)
+ {
+@@ -192,7 +192,7 @@ insert_normal (CGEN_CPU_DESC cd,
+ {
+ long minval = - (1L << (length - 1));
+ long maxval = (1L << (length - 1)) - 1;
+-
++
+ if (value < minval || value > maxval)
+ {
+ sprintf
+@@ -2893,12 +2893,12 @@ m32c_cgen_extract_operand (CGEN_CPU_DESC cd,
+ return length;
+ }
+
+-cgen_insert_fn * const m32c_cgen_insert_handlers[] =
++cgen_insert_fn * const m32c_cgen_insert_handlers[] =
+ {
+ insert_insn_normal,
+ };
+
+-cgen_extract_fn * const m32c_cgen_extract_handlers[] =
++cgen_extract_fn * const m32c_cgen_extract_handlers[] =
+ {
+ extract_insn_normal,
+ };
+--- a/opcodes/m32c-opc.c
++++ b/opcodes/m32c-opc.c
+@@ -35,19 +35,19 @@ static unsigned int
+ m32c_asm_hash (const char *mnem)
+ {
+ unsigned int h;
+-
++
+ /* The length of the mnemonic for the Jcnd insns is 1. Hash jsri. */
+ if (mnem[0] == 'j' && mnem[1] != 's')
+ return 'j';
+-
++
+ /* Don't hash scCND */
+ if (mnem[0] == 's' && mnem[1] == 'c')
+ return 's';
+-
++
+ /* Don't hash bmCND */
+ if (mnem[0] == 'b' && mnem[1] == 'm')
+ return 'b';
+-
++
+ for (h = 0; *mnem && *mnem != ' ' && *mnem != ':'; ++mnem)
+ h += *mnem;
+ return h % CGEN_ASM_HASH_SIZE;
+--- a/opcodes/m32r-asm.c
++++ b/opcodes/m32r-asm.c
+@@ -331,7 +331,7 @@ m32r_cgen_parse_operand (CGEN_CPU_DESC cd,
+ return errmsg;
+ }
+
+-cgen_parse_fn * const m32r_cgen_parse_handlers[] =
++cgen_parse_fn * const m32r_cgen_parse_handlers[] =
+ {
+ parse_insn_normal,
+ };
+@@ -361,9 +361,9 @@ CGEN_ASM_INIT_HOOK
+
+ Returns NULL for success, an error message for failure. */
+
+-char *
++char *
+ m32r_cgen_build_insn_regex (CGEN_INSN *insn)
+-{
++{
+ CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
+ const char *mnem = CGEN_INSN_MNEMONIC (insn);
+ char rxbuf[CGEN_MAX_RX_ELEMENTS];
+@@ -402,18 +402,18 @@ m32r_cgen_build_insn_regex (CGEN_INSN *insn)
+ /* Copy any remaining literals from the syntax string into the rx. */
+ for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn)
+ {
+- if (CGEN_SYNTAX_CHAR_P (* syn))
++ if (CGEN_SYNTAX_CHAR_P (* syn))
+ {
+ char c = CGEN_SYNTAX_CHAR (* syn);
+
+- switch (c)
++ switch (c)
+ {
+ /* Escape any regex metacharacters in the syntax. */
+- case '.': case '[': case '\\':
+- case '*': case '^': case '$':
++ case '.': case '[': case '\\':
++ case '*': case '^': case '$':
+
+ #ifdef CGEN_ESCAPE_EXTENDED_REGEX
+- case '?': case '{': case '}':
++ case '?': case '{': case '}':
+ case '(': case ')': case '*':
+ case '|': case '+': case ']':
+ #endif
+@@ -443,20 +443,20 @@ m32r_cgen_build_insn_regex (CGEN_INSN *insn)
+ }
+
+ /* Trailing whitespace ok. */
+- * rx++ = '[';
+- * rx++ = ' ';
+- * rx++ = '\t';
+- * rx++ = ']';
+- * rx++ = '*';
++ * rx++ = '[';
++ * rx++ = ' ';
++ * rx++ = '\t';
++ * rx++ = ']';
++ * rx++ = '*';
+
+ /* But anchor it after that. */
+- * rx++ = '$';
++ * rx++ = '$';
+ * rx = '\0';
+
+ CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t));
+ reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB);
+
+- if (reg_err == 0)
++ if (reg_err == 0)
+ return NULL;
+ else
+ {
+@@ -655,7 +655,7 @@ m32r_cgen_assemble_insn (CGEN_CPU_DESC cd,
+ const CGEN_INSN *insn = ilist->insn;
+ recognized_mnemonic = 1;
+
+-#ifdef CGEN_VALIDATE_INSN_SUPPORTED
++#ifdef CGEN_VALIDATE_INSN_SUPPORTED
+ /* Not usually needed as unsupported opcodes
+ shouldn't be in the hash lists. */
+ /* Is this insn supported by the selected cpu? */
+@@ -715,7 +715,7 @@ m32r_cgen_assemble_insn (CGEN_CPU_DESC cd,
+ if (strlen (start) > 50)
+ /* xgettext:c-format */
+ sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start);
+- else
++ else
+ /* xgettext:c-format */
+ sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start);
+ }
+@@ -724,11 +724,11 @@ m32r_cgen_assemble_insn (CGEN_CPU_DESC cd,
+ if (strlen (start) > 50)
+ /* xgettext:c-format */
+ sprintf (errbuf, _("bad instruction `%.50s...'"), start);
+- else
++ else
+ /* xgettext:c-format */
+ sprintf (errbuf, _("bad instruction `%.50s'"), start);
+ }
+-
++
+ *errmsg = errbuf;
+ return NULL;
+ }
+--- a/opcodes/m32r-desc.c
++++ b/opcodes/m32r-desc.c
+@@ -312,115 +312,115 @@ const CGEN_OPERAND m32r_cgen_operand_table[] =
+ {
+ /* pc: program counter */
+ { "pc", M32R_OPERAND_PC, HW_H_PC, 0, 0,
+- { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_NIL] } },
++ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_NIL] } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* sr: source register */
+ { "sr", M32R_OPERAND_SR, HW_H_GR, 12, 4,
+- { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R2] } },
++ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R2] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* dr: destination register */
+ { "dr", M32R_OPERAND_DR, HW_H_GR, 4, 4,
+- { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R1] } },
++ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R1] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* src1: source register 1 */
+ { "src1", M32R_OPERAND_SRC1, HW_H_GR, 4, 4,
+- { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R1] } },
++ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R1] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* src2: source register 2 */
+ { "src2", M32R_OPERAND_SRC2, HW_H_GR, 12, 4,
+- { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R2] } },
++ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R2] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* scr: source control register */
+ { "scr", M32R_OPERAND_SCR, HW_H_CR, 12, 4,
+- { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R2] } },
++ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R2] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* dcr: destination control register */
+ { "dcr", M32R_OPERAND_DCR, HW_H_CR, 4, 4,
+- { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R1] } },
++ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R1] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* simm8: 8 bit signed immediate */
+ { "simm8", M32R_OPERAND_SIMM8, HW_H_SINT, 8, 8,
+- { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM8] } },
++ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM8] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* simm16: 16 bit signed immediate */
+ { "simm16", M32R_OPERAND_SIMM16, HW_H_SINT, 16, 16,
+- { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM16] } },
++ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM16] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* uimm3: 3 bit unsigned number */
+ { "uimm3", M32R_OPERAND_UIMM3, HW_H_UINT, 5, 3,
+- { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM3] } },
++ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM3] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* uimm4: 4 bit trap number */
+ { "uimm4", M32R_OPERAND_UIMM4, HW_H_UINT, 12, 4,
+- { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM4] } },
++ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM4] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* uimm5: 5 bit shift count */
+ { "uimm5", M32R_OPERAND_UIMM5, HW_H_UINT, 11, 5,
+- { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM5] } },
++ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM5] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* uimm8: 8 bit unsigned immediate */
+ { "uimm8", M32R_OPERAND_UIMM8, HW_H_UINT, 8, 8,
+- { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM8] } },
++ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM8] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* uimm16: 16 bit unsigned immediate */
+ { "uimm16", M32R_OPERAND_UIMM16, HW_H_UINT, 16, 16,
+- { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM16] } },
++ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM16] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* imm1: 1 bit immediate */
+ { "imm1", M32R_OPERAND_IMM1, HW_H_UINT, 15, 1,
+- { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_IMM1] } },
++ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_IMM1] } },
+ { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } } },
+ /* accd: accumulator destination register */
+ { "accd", M32R_OPERAND_ACCD, HW_H_ACCUMS, 4, 2,
+- { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACCD] } },
++ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACCD] } },
+ { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } } },
+ /* accs: accumulator source register */
+ { "accs", M32R_OPERAND_ACCS, HW_H_ACCUMS, 12, 2,
+- { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACCS] } },
++ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACCS] } },
+ { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } } },
+ /* acc: accumulator reg (d) */
+ { "acc", M32R_OPERAND_ACC, HW_H_ACCUMS, 8, 1,
+- { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACC] } },
++ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACC] } },
+ { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } } },
+ /* hash: # prefix */
+ { "hash", M32R_OPERAND_HASH, HW_H_SINT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* hi16: high 16 bit immediate, sign optional */
+ { "hi16", M32R_OPERAND_HI16, HW_H_HI16, 16, 16,
+- { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_HI16] } },
++ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_HI16] } },
+ { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } },
+ /* slo16: 16 bit signed immediate, for low() */
+ { "slo16", M32R_OPERAND_SLO16, HW_H_SLO16, 16, 16,
+- { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM16] } },
++ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM16] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* ulo16: 16 bit unsigned immediate, for low() */
+ { "ulo16", M32R_OPERAND_ULO16, HW_H_ULO16, 16, 16,
+- { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM16] } },
++ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM16] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* uimm24: 24 bit address */
+ { "uimm24", M32R_OPERAND_UIMM24, HW_H_ADDR, 8, 24,
+- { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM24] } },
++ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM24] } },
+ { 0|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
+ /* disp8: 8 bit displacement */
+ { "disp8", M32R_OPERAND_DISP8, HW_H_IADDR, 8, 8,
+- { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_DISP8] } },
++ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_DISP8] } },
+ { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
+ /* disp16: 16 bit displacement */
+ { "disp16", M32R_OPERAND_DISP16, HW_H_IADDR, 16, 16,
+- { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_DISP16] } },
++ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_DISP16] } },
+ { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
+ /* disp24: 24 bit displacement */
+ { "disp24", M32R_OPERAND_DISP24, HW_H_IADDR, 8, 24,
+- { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_DISP24] } },
++ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_DISP24] } },
+ { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
+ /* condbit: condition bit */
+ { "condbit", M32R_OPERAND_CONDBIT, HW_H_COND, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* accum: accumulator */
+ { "accum", M32R_OPERAND_ACCUM, HW_H_ACCUM, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* sentinel */
+ { 0, 0, 0, 0, 0,
+@@ -1468,7 +1468,7 @@ m32r_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
+
+ /* Default to not allowing signed overflow. */
+ cd->signed_overflow_ok_p = 0;
+-
++
+ return (CGEN_CPU_DESC) cd;
+ }
+
+@@ -1508,7 +1508,7 @@ m32r_cgen_cpu_close (CGEN_CPU_DESC cd)
+ for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
+ if (CGEN_INSN_RX (insns))
+ regfree (CGEN_INSN_RX (insns));
+- }
++ }
+
+ if (cd->macro_insn_table.init_entries)
+ free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
+--- a/opcodes/m32r-dis.c
++++ b/opcodes/m32r-dis.c
+@@ -281,7 +281,7 @@ m32r_cgen_print_operand (CGEN_CPU_DESC cd,
+ }
+ }
+
+-cgen_print_fn * const m32r_cgen_print_handlers[] =
++cgen_print_fn * const m32r_cgen_print_handlers[] =
+ {
+ print_insn_normal,
+ };
+@@ -471,7 +471,7 @@ print_insn (CGEN_CPU_DESC cd,
+ int length;
+ unsigned long insn_value_cropped;
+
+-#ifdef CGEN_VALIDATE_INSN_SUPPORTED
++#ifdef CGEN_VALIDATE_INSN_SUPPORTED
+ /* Not needed as insn shouldn't be in hash lists if not supported. */
+ /* Supported by this cpu? */
+ if (! m32r_cgen_insn_supported (cd, insn))
+@@ -489,7 +489,7 @@ print_insn (CGEN_CPU_DESC cd,
+ relevant part from the buffer. */
+ if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
+ (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
+- insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
++ insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
+ info->endian == BFD_ENDIAN_BIG);
+ else
+ insn_value_cropped = insn_value;
+@@ -608,7 +608,7 @@ print_insn_m32r (bfd_vma pc, disassemble_info *info)
+ arch = info->arch;
+ if (arch == bfd_arch_unknown)
+ arch = CGEN_BFD_ARCH;
+-
++
+ /* There's no standard way to compute the machine or isa number
+ so we leave it to the target. */
+ #ifdef CGEN_COMPUTE_MACH
+@@ -649,7 +649,7 @@ print_insn_m32r (bfd_vma pc, disassemble_info *info)
+ break;
+ }
+ }
+- }
++ }
+
+ /* If we haven't initialized yet, initialize the opcode table. */
+ if (! cd)
+--- a/opcodes/m32r-ibld.c
++++ b/opcodes/m32r-ibld.c
+@@ -154,7 +154,7 @@ insert_normal (CGEN_CPU_DESC cd,
+ {
+ long minval = - (1L << (length - 1));
+ unsigned long maxval = mask;
+-
++
+ if ((value > 0 && (unsigned long) value > maxval)
+ || value < minval)
+ {
+@@ -192,7 +192,7 @@ insert_normal (CGEN_CPU_DESC cd,
+ {
+ long minval = - (1L << (length - 1));
+ long maxval = (1L << (length - 1)) - 1;
+-
++
+ if (value < minval || value > maxval)
+ {
+ sprintf
+@@ -803,12 +803,12 @@ m32r_cgen_extract_operand (CGEN_CPU_DESC cd,
+ return length;
+ }
+
+-cgen_insert_fn * const m32r_cgen_insert_handlers[] =
++cgen_insert_fn * const m32r_cgen_insert_handlers[] =
+ {
+ insert_insn_normal,
+ };
+
+-cgen_extract_fn * const m32r_cgen_extract_handlers[] =
++cgen_extract_fn * const m32r_cgen_extract_handlers[] =
+ {
+ extract_insn_normal,
+ };
+--- a/opcodes/m68hc11-dis.c
++++ b/opcodes/m68hc11-dis.c
+@@ -697,7 +697,7 @@ print_insn (bfd_vma memaddr, struct disassemble_info* info, int arch)
+ {
+ int cur_page;
+ bfd_vma vaddr;
+-
++
+ if (memaddr >= M68HC12_BANK_VIRT)
+ cur_page = ((memaddr - M68HC12_BANK_VIRT)
+ >> M68HC12_BANK_SHIFT);
+@@ -827,7 +827,7 @@ print_insn (bfd_vma memaddr, struct disassemble_info* info, int arch)
+ val = buffer[0] & 0x0ff;
+ (*info->fprintf_func) (info->stream, ", 0x%x", val);
+ }
+-
++
+ #ifdef DEBUG
+ /* Consistency check. 'format' must be 0, so that we have handled
+ all formats; and the computed size of the insn must match the
+--- a/opcodes/m68hc11-opc.c
++++ b/opcodes/m68hc11-opc.c
+@@ -328,7 +328,7 @@ const struct m68hc11_opcode m68hc11_opcodes[] = {
+ { "bgt", OP_JUMP_REL, 2, 0x2e, 1, 3, CHG_NONE, cpu6811 | cpu6812|cpu9s12x, 0 },
+ { "bhi", OP_JUMP_REL, 2, 0x22, 1, 3, CHG_NONE, cpu6811 | cpu6812|cpu9s12x, 0 },
+ { "bhs", OP_JUMP_REL, 2, 0x24, 1, 3, CHG_NONE, cpu6811 | cpu6812|cpu9s12x, 0 },
+-
++
+ { "bita", OP_IMM8, 2, 0x85, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "bita", OP_DIRECT, 2, 0x95, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "bita", OP_IND16, 3, 0xb5, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
+--- a/opcodes/m68k-dis.c
++++ b/opcodes/m68k-dis.c
+@@ -79,7 +79,7 @@ static char *const reg_half_names[] =
+ return ret_val; \
+ val = COERCE16 ((p[-2] << 8) + p[-1]); \
+ } \
+- while (0)
++ while (0)
+
+ /* Get a 4 byte signed integer. */
+ #define COERCE32(x) ((bfd_signed_vma) ((x) ^ 0x80000000) - 0x80000000)
+@@ -1336,7 +1336,7 @@ match_insn_m68k (bfd_vma memaddr,
+
+ if (*args == '.')
+ args++;
+-
++
+ /* Point at first word of argument data,
+ and at descriptor for first argument. */
+ p = buffer + 2;
+@@ -1583,7 +1583,7 @@ m68k_scan_mask (bfd_vma memaddr, disassemble_info *info,
+ }
+ }
+ return 0;
+-}
++}
+
+ /* Print the m68k instruction at address MEMADDR in debugged memory,
+ on INFO->STREAM. Returns length of the instruction, in bytes. */
+--- a/opcodes/m68k-opc.c
++++ b/opcodes/m68k-opc.c
+@@ -292,7 +292,7 @@ const struct m68k_opcode m68k_opcodes[] =
+ {"cmpl", 6, one(0006200), one(0177700), "#lDs", mcfisa_a },
+ {"cmpl", 2, one(0130610), one(0170770), "+s+d", m68000up },
+ {"cmpl", 2, one(0130200), one(0170700), "*lDd", m68000up | mcfisa_a },
+-
++
+ {"cp0bcbusy",2, one (0176300), one (01777770), "BW", mcfisa_a},
+ {"cp1bcbusy",2, one (0177300), one (01777770), "BW", mcfisa_a},
+ {"cp0nop", 4, two (0176000,0), two (01777477,0170777), "jE", mcfisa_a},
+@@ -316,7 +316,7 @@ const struct m68k_opcode m68k_opcodes[] =
+ {"cp1stl", 6, one (0177600), one (01777700), ".R1pwjEK3", mcfisa_a},
+ {"cp0st", 6, one (0176600), one (01777700), ".R1pwjEK3", mcfisa_a},
+ {"cp1st", 6, one (0177600), one (01777700), ".R1pwjEK3", mcfisa_a},
+-
++
+ {"dbcc", 2, one(0052310), one(0177770), "DsBw", m68000up },
+ {"dbcs", 2, one(0052710), one(0177770), "DsBw", m68000up },
+ {"dbeq", 2, one(0053710), one(0177770), "DsBw", m68000up },
+@@ -376,7 +376,7 @@ const struct m68k_opcode m68k_opcodes[] =
+ {"eor", 4, one(0005174), one(0177777), "#wSs", m68000up },
+ {"eor", 4, one(0005100), one(0177700), "#w$s", m68000up },
+ {"eor", 2, one(0130500), one(0170700), "Dd$s", m68000up },
+-
++
+ {"exg", 2, one(0140500), one(0170770), "DdDs", m68000up },
+ {"exg", 2, one(0140510), one(0170770), "AdAs", m68000up },
+ {"exg", 2, one(0140610), one(0170770), "DdAs", m68000up },
+@@ -2005,22 +2005,22 @@ const struct m68k_opcode m68k_opcodes[] =
+ {"roxrl", 2, one(0160260), one(0170770), "DdDs", m68000up },
+
+ {"rtd", 4, one(0047164), one(0177777), "#w", m68010up },
+-
++
+ {"rte", 2, one(0047163), one(0177777), "", m68000up | mcfisa_a },
+-
++
+ {"rtm", 2, one(0003300), one(0177760), "Rs", m68020 },
+-
++
+ {"rtr", 2, one(0047167), one(0177777), "", m68000up },
+-
++
+ {"rts", 2, one(0047165), one(0177777), "", m68000up | mcfisa_a },
+
+ {"satsl", 2, one(0046200), one(0177770), "Ds", mcfisa_b | mcfisa_c },
+
+ {"sbcd", 2, one(0100400), one(0170770), "DsDd", m68000up },
+ {"sbcd", 2, one(0100410), one(0170770), "-s-d", m68000up },
+-
++
+ {"stldsr", 6, two(0x40e7, 0x46fc), two(0xffff, 0xffff), "#w", mcfisa_aa | mcfisa_c },
+-
++
+ /* Traps have to come before conditional sets, as they have a more
+ specific opcode. */
+ {"trapcc", 2, one(0052374), one(0177777), "", m68020up | cpu32 | fido_a },
+--- a/opcodes/m88k-dis.c
++++ b/opcodes/m88k-dis.c
+@@ -522,7 +522,7 @@ HASHTAB *hashtable[HASHVAL] = {0};
+
+
+ /* Initialize the disassembler instruction table.
+-
++
+ Initialize the hash table and instruction table for the
+ disassembler. This should be called once before the first call to
+ disasm(). */
+@@ -549,14 +549,14 @@ init_disasm (void)
+ hashtable[hashvalue] = &hashentries[i];
+ }
+ }
+-
++
+ /* Decode an Operand of an instruction.
+-
++
+ This function formats and writes an operand of an instruction to
+ info based on the operand specification. When the `first' flag is
+ set this is the first operand of an instruction. Undefined operand
+ types cause a <dis error> message.
+-
++
+ Parameters:
+ disassemble_info where the operand may be printed
+ OPSPEC *opptr pointer to an operand specification
+@@ -564,7 +564,7 @@ init_disasm (void)
+ UINT pc pc of instruction; used for pc-relative disp.
+ int first flag which if nonzero indicates the first
+ operand of an instruction
+-
++
+ The operand specified is extracted from the instruction and is
+ written to buf in the format specified. The operand is preceded by
+ a comma if it is not the first operand of an instruction and it is
+@@ -654,7 +654,7 @@ printop (struct disassemble_info *info,
+ else
+ (*info->fprintf_func) (info->stream, "%x", extracted_field);
+ break;
+-
++
+ case PCREL:
+ (*info->print_address_func)
+ (pc + (4 * (SEXT (inst, opptr->offset, opptr->width))),
+@@ -683,7 +683,7 @@ printop (struct disassemble_info *info,
+ `pc' should be the address of this instruction, it will be used to
+ print the target address if this is a relative jump or call the
+ disassembled instruction is written to `info'.
+-
++
+ The function returns the length of this instruction in bytes. */
+
+ static int
+--- a/opcodes/makefile.vms
++++ b/opcodes/makefile.vms
+@@ -11,12 +11,12 @@
+ # it under the terms of the GNU General Public License as published by
+ # the Free Software Foundation; either version 3 of the License, or
+ # (at your option) any later version.
+-#
++#
+ # This program is distributed in the hope that it will be useful,
+ # but WITHOUT ANY WARRANTY; without even the implied warranty of
+ # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ # GNU General Public License for more details.
+-#
++#
+ # You should have received a copy of the GNU General Public License
+ # along with this program; see the file COPYING3. If not see
+ # <http://www.gnu.org/licenses/>.
+--- a/opcodes/mcore-opc.h
++++ b/opcodes/mcore-opc.h
+@@ -128,14 +128,14 @@ const mcore_opcode_info mcore_table[] =
+ { "cmpnei", OB, 0, 0x2A00 },
+ { "bmaski", OMa, 0, 0x2C00 },
+ { "divu", O1R1, 0, 0x2C10 },
+-/* SPACE: 0x2c20 - 0x2c7f */
++/* SPACE: 0x2c20 - 0x2c7f */
+ { "bmaski", OMb, 0, 0x2C80 },
+ { "bmaski", OMc, 0, 0x2D00 },
+ { "andi", OB, 0, 0x2E00 },
+ { "bclri", OB, 0, 0x3000 },
+ /* SPACE: 0x3200 - 0x320f */
+ { "divs", O1R1, 0, 0x3210 },
+-/* SPACE: 0x3220 - 0x326f */
++/* SPACE: 0x3220 - 0x326f */
+ { "bgeni", OBRa, 0, 0x3270 },
+ { "bgeni", OBRb, 0, 0x3280 },
+ { "bgeni", OBRc, 0, 0x3300 },
+--- a/opcodes/mep-asm.c
++++ b/opcodes/mep-asm.c
+@@ -488,7 +488,7 @@ parse_unsigned7 (CGEN_CPU_DESC cd, const char **strp,
+ break;
+ default:
+ /* Safe assumption? */
+- abort ();
++ abort ();
+ }
+ errmsg = cgen_parse_address (cd, strp, opindex, reloc,
+ NULL, &value);
+@@ -534,7 +534,7 @@ parse_cdisp10 (CGEN_CPU_DESC cd,
+ if ((MEP_CPU & EF_MEP_CPU_MASK) == EF_MEP_CPU_C5)
+ wide = 1;
+
+- if (strncmp (*strp, "0x0", 3) == 0
++ if (strncmp (*strp, "0x0", 3) == 0
+ || (**strp == '0' && *(*strp + 1) != 'x'))
+ have_zero = 1;
+
+@@ -601,7 +601,7 @@ mep_cgen_expand_macros_and_parse_operand
+
+ static char *
+ str_append (char *dest, const char *input, int len)
+-{
++{
+ char *new_dest;
+ int oldlen;
+
+@@ -637,8 +637,8 @@ expand_macro (arg *args, int narg, macro *mac)
+ /* printf("expanding macro %s with %d args\n", mac->name, narg + 1); */
+ while (*e)
+ {
+- if (*e == '`' &&
+- (*e+1) &&
++ if (*e == '`' &&
++ (*e+1) &&
+ ((*(e + 1) - '1') <= MAXARGS) &&
+ ((*(e + 1) - '1') <= narg))
+ {
+@@ -661,7 +661,7 @@ expand_macro (arg *args, int narg, macro *mac)
+ free (result);
+ return rescanned_result;
+ }
+- else
++ else
+ return result;
+ }
+
+@@ -686,8 +686,8 @@ expand_string (const char *in, int first_only)
+ switch (state)
+ {
+ case IN_TEXT:
+- if (*in == '%' && *(in + 1) && (!first_only || num_expansions == 0))
+- {
++ if (*in == '%' && *(in + 1) && (!first_only || num_expansions == 0))
++ {
+ pmacro = lookup_macro (in + 1);
+ if (pmacro)
+ {
+@@ -698,7 +698,7 @@ expand_string (const char *in, int first_only)
+ while (*in == ' ') ++in;
+ if (*in != '(')
+ {
+- state = IN_TEXT;
++ state = IN_TEXT;
+ pmacro = NULL;
+ }
+ else
+@@ -707,7 +707,7 @@ expand_string (const char *in, int first_only)
+ narg = 0;
+ args[narg].start = in + 1;
+ args[narg].len = 0;
+- mark = in + 1;
++ mark = in + 1;
+ }
+ }
+ }
+@@ -747,9 +747,9 @@ expand_string (const char *in, int first_only)
+ depth++;
+ default:
+ args[narg].len++;
+- break;
++ break;
+ }
+- }
++ }
+ else
+ {
+ if (*in == ')')
+@@ -757,14 +757,14 @@ expand_string (const char *in, int first_only)
+ if (narg > -1)
+ args[narg].len++;
+ }
+-
++
+ }
+ ++in;
+ }
+-
++
+ if (mark != in)
+ result = str_append (result, mark, in - mark);
+-
++
+ return result;
+ }
+
+@@ -803,10 +803,10 @@ mep_cgen_expand_macros_and_parse_operand (CGEN_CPU_DESC cd, int opindex,
+ {
+ if (strstr (*strp_in, str))
+ /* A macro-expansion was pulled off the front. */
+- *strp_in = strstr (*strp_in, str);
++ *strp_in = strstr (*strp_in, str);
+ else
+ /* A non-macro-expansion was pulled off the front. */
+- *strp_in += (str - hold);
++ *strp_in += (str - hold);
+ }
+
+ if (hold)
+@@ -815,7 +815,7 @@ mep_cgen_expand_macros_and_parse_operand (CGEN_CPU_DESC cd, int opindex,
+ return errmsg;
+ }
+
+-#define CGEN_ASM_INIT_HOOK (cd->parse_operand = mep_cgen_expand_macros_and_parse_operand);
++#define CGEN_ASM_INIT_HOOK (cd->parse_operand = mep_cgen_expand_macros_and_parse_operand);
+
+ /* -- dis.c */
+
+@@ -1289,7 +1289,7 @@ mep_cgen_parse_operand (CGEN_CPU_DESC cd,
+ return errmsg;
+ }
+
+-cgen_parse_fn * const mep_cgen_parse_handlers[] =
++cgen_parse_fn * const mep_cgen_parse_handlers[] =
+ {
+ parse_insn_normal,
+ };
+@@ -1319,9 +1319,9 @@ CGEN_ASM_INIT_HOOK
+
+ Returns NULL for success, an error message for failure. */
+
+-char *
++char *
+ mep_cgen_build_insn_regex (CGEN_INSN *insn)
+-{
++{
+ CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
+ const char *mnem = CGEN_INSN_MNEMONIC (insn);
+ char rxbuf[CGEN_MAX_RX_ELEMENTS];
+@@ -1360,18 +1360,18 @@ mep_cgen_build_insn_regex (CGEN_INSN *insn)
+ /* Copy any remaining literals from the syntax string into the rx. */
+ for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn)
+ {
+- if (CGEN_SYNTAX_CHAR_P (* syn))
++ if (CGEN_SYNTAX_CHAR_P (* syn))
+ {
+ char c = CGEN_SYNTAX_CHAR (* syn);
+
+- switch (c)
++ switch (c)
+ {
+ /* Escape any regex metacharacters in the syntax. */
+- case '.': case '[': case '\\':
+- case '*': case '^': case '$':
++ case '.': case '[': case '\\':
++ case '*': case '^': case '$':
+
+ #ifdef CGEN_ESCAPE_EXTENDED_REGEX
+- case '?': case '{': case '}':
++ case '?': case '{': case '}':
+ case '(': case ')': case '*':
+ case '|': case '+': case ']':
+ #endif
+@@ -1401,20 +1401,20 @@ mep_cgen_build_insn_regex (CGEN_INSN *insn)
+ }
+
+ /* Trailing whitespace ok. */
+- * rx++ = '[';
+- * rx++ = ' ';
+- * rx++ = '\t';
+- * rx++ = ']';
+- * rx++ = '*';
++ * rx++ = '[';
++ * rx++ = ' ';
++ * rx++ = '\t';
++ * rx++ = ']';
++ * rx++ = '*';
+
+ /* But anchor it after that. */
+- * rx++ = '$';
++ * rx++ = '$';
+ * rx = '\0';
+
+ CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t));
+ reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB);
+
+- if (reg_err == 0)
++ if (reg_err == 0)
+ return NULL;
+ else
+ {
+@@ -1613,7 +1613,7 @@ mep_cgen_assemble_insn (CGEN_CPU_DESC cd,
+ const CGEN_INSN *insn = ilist->insn;
+ recognized_mnemonic = 1;
+
+-#ifdef CGEN_VALIDATE_INSN_SUPPORTED
++#ifdef CGEN_VALIDATE_INSN_SUPPORTED
+ /* Not usually needed as unsupported opcodes
+ shouldn't be in the hash lists. */
+ /* Is this insn supported by the selected cpu? */
+@@ -1673,7 +1673,7 @@ mep_cgen_assemble_insn (CGEN_CPU_DESC cd,
+ if (strlen (start) > 50)
+ /* xgettext:c-format */
+ sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start);
+- else
++ else
+ /* xgettext:c-format */
+ sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start);
+ }
+@@ -1682,11 +1682,11 @@ mep_cgen_assemble_insn (CGEN_CPU_DESC cd,
+ if (strlen (start) > 50)
+ /* xgettext:c-format */
+ sprintf (errbuf, _("bad instruction `%.50s...'"), start);
+- else
++ else
+ /* xgettext:c-format */
+ sprintf (errbuf, _("bad instruction `%.50s'"), start);
+ }
+-
++
+ *errmsg = errbuf;
+ return NULL;
+ }
+--- a/opcodes/mep-desc.c
++++ b/opcodes/mep-desc.c
+@@ -103,13 +103,13 @@ static const CGEN_ATTR_ENTRY CRET_attr[] ATTRIBUTE_UNUSED =
+ { 0, 0 }
+ };
+
+-static const CGEN_ATTR_ENTRY ALIGN_attr [] ATTRIBUTE_UNUSED =
++static const CGEN_ATTR_ENTRY ALIGN_attr [] ATTRIBUTE_UNUSED =
+ {
+ {"integer", 1},
+ { 0, 0 }
+ };
+
+-static const CGEN_ATTR_ENTRY LATENCY_attr [] ATTRIBUTE_UNUSED =
++static const CGEN_ATTR_ENTRY LATENCY_attr [] ATTRIBUTE_UNUSED =
+ {
+ {"integer", 0},
+ { 0, 0 }
+@@ -880,583 +880,583 @@ const CGEN_OPERAND mep_cgen_operand_table[] =
+ {
+ /* pc: program counter */
+ { "pc", MEP_OPERAND_PC, HW_H_PC, 0, 0,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_NIL] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_NIL] } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* r0: register 0 */
+ { "r0", MEP_OPERAND_R0, HW_H_GPR, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* rn: register Rn */
+ { "rn", MEP_OPERAND_RN, HW_H_GPR, 4, 4,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* rm: register Rm */
+ { "rm", MEP_OPERAND_RM, HW_H_GPR, 8, 4,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RM] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RM] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* rl: register Rl */
+ { "rl", MEP_OPERAND_RL, HW_H_GPR, 12, 4,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RL] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RL] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* rn3: register 0-7 */
+ { "rn3", MEP_OPERAND_RN3, HW_H_GPR, 5, 3,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* rma: register Rm holding pointer */
+ { "rma", MEP_OPERAND_RMA, HW_H_GPR, 8, 4,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RM] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RM] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_POINTER, 0 } }, { { 1, 0 } } } } },
+ /* rnc: register Rn holding char */
+ { "rnc", MEP_OPERAND_RNC, HW_H_GPR, 4, 4,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* rnuc: register Rn holding unsigned char */
+ { "rnuc", MEP_OPERAND_RNUC, HW_H_GPR, 4, 4,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* rns: register Rn holding short */
+ { "rns", MEP_OPERAND_RNS, HW_H_GPR, 4, 4,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* rnus: register Rn holding unsigned short */
+ { "rnus", MEP_OPERAND_RNUS, HW_H_GPR, 4, 4,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* rnl: register Rn holding long */
+ { "rnl", MEP_OPERAND_RNL, HW_H_GPR, 4, 4,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* rnul: register Rn holding unsigned long */
+ { "rnul", MEP_OPERAND_RNUL, HW_H_GPR, 4, 4,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_ULONG, 0 } }, { { 1, 0 } } } } },
+ /* rn3c: register 0-7 holding unsigned char */
+ { "rn3c", MEP_OPERAND_RN3C, HW_H_GPR, 5, 3,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* rn3uc: register 0-7 holding byte */
+ { "rn3uc", MEP_OPERAND_RN3UC, HW_H_GPR, 5, 3,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* rn3s: register 0-7 holding unsigned short */
+ { "rn3s", MEP_OPERAND_RN3S, HW_H_GPR, 5, 3,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* rn3us: register 0-7 holding short */
+ { "rn3us", MEP_OPERAND_RN3US, HW_H_GPR, 5, 3,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* rn3l: register 0-7 holding unsigned long */
+ { "rn3l", MEP_OPERAND_RN3L, HW_H_GPR, 5, 3,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* rn3ul: register 0-7 holding long */
+ { "rn3ul", MEP_OPERAND_RN3UL, HW_H_GPR, 5, 3,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_ULONG, 0 } }, { { 1, 0 } } } } },
+ /* lp: link pointer */
+ { "lp", MEP_OPERAND_LP, HW_H_CSR, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* sar: shift amount register */
+ { "sar", MEP_OPERAND_SAR, HW_H_CSR, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* hi: high result */
+ { "hi", MEP_OPERAND_HI, HW_H_CSR, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* lo: low result */
+ { "lo", MEP_OPERAND_LO, HW_H_CSR, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* mb0: modulo begin register 0 */
+ { "mb0", MEP_OPERAND_MB0, HW_H_CSR, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* me0: modulo end register 0 */
+ { "me0", MEP_OPERAND_ME0, HW_H_CSR, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* mb1: modulo begin register 1 */
+ { "mb1", MEP_OPERAND_MB1, HW_H_CSR, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* me1: modulo end register 1 */
+ { "me1", MEP_OPERAND_ME1, HW_H_CSR, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* psw: program status word */
+ { "psw", MEP_OPERAND_PSW, HW_H_CSR, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* epc: exception prog counter */
+ { "epc", MEP_OPERAND_EPC, HW_H_CSR, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* exc: exception cause */
+ { "exc", MEP_OPERAND_EXC, HW_H_CSR, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* npc: nmi program counter */
+ { "npc", MEP_OPERAND_NPC, HW_H_CSR, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* dbg: debug register */
+ { "dbg", MEP_OPERAND_DBG, HW_H_CSR, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* depc: debug exception pc */
+ { "depc", MEP_OPERAND_DEPC, HW_H_CSR, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* opt: option register */
+ { "opt", MEP_OPERAND_OPT, HW_H_CSR, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* r1: register 1 */
+ { "r1", MEP_OPERAND_R1, HW_H_GPR, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* tp: tiny data area pointer */
+ { "tp", MEP_OPERAND_TP, HW_H_GPR, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* sp: stack pointer */
+ { "sp", MEP_OPERAND_SP, HW_H_GPR, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* tpr: comment */
+ { "tpr", MEP_OPERAND_TPR, HW_H_GPR, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* spr: comment */
+ { "spr", MEP_OPERAND_SPR, HW_H_GPR, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* csrn: control/special register */
+ { "csrn", MEP_OPERAND_CSRN, HW_H_CSR, 8, 5,
+- { 2, { (const PTR) &MEP_F_CSRN_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &MEP_F_CSRN_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_REGNUM, 0 } }, { { 1, 0 } } } } },
+ /* csrn-idx: control/special reg idx */
+ { "csrn-idx", MEP_OPERAND_CSRN_IDX, HW_H_UINT, 8, 5,
+- { 2, { (const PTR) &MEP_F_CSRN_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &MEP_F_CSRN_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* crn64: copro Rn (64-bit) */
+ { "crn64", MEP_OPERAND_CRN64, HW_H_CR64, 4, 4,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CRN] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CRN] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } } },
+ /* crn: copro Rn (32-bit) */
+ { "crn", MEP_OPERAND_CRN, HW_H_CR, 4, 4,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CRN] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CRN] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } } },
+ /* crnx64: copro Rn (0-31, 64-bit) */
+ { "crnx64", MEP_OPERAND_CRNX64, HW_H_CR64, 4, 5,
+- { 2, { (const PTR) &MEP_F_CRNX_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &MEP_F_CRNX_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } } },
+ /* crnx: copro Rn (0-31, 32-bit) */
+ { "crnx", MEP_OPERAND_CRNX, HW_H_CR, 4, 5,
+- { 2, { (const PTR) &MEP_F_CRNX_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &MEP_F_CRNX_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } } },
+ /* ccrn: copro control reg CCRn */
+ { "ccrn", MEP_OPERAND_CCRN, HW_H_CCR, 4, 6,
+- { 2, { (const PTR) &MEP_F_CCRN_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &MEP_F_CCRN_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_REGNUM, 0 } }, { { 1, 0 } } } } },
+ /* cccc: copro flags */
+ { "cccc", MEP_OPERAND_CCCC, HW_H_UINT, 8, 4,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RM] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RM] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* pcrel8a2: comment */
+ { "pcrel8a2", MEP_OPERAND_PCREL8A2, HW_H_SINT, 8, 7,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_8S8A2] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_8S8A2] } },
+ { 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } } },
+ /* pcrel12a2: comment */
+ { "pcrel12a2", MEP_OPERAND_PCREL12A2, HW_H_SINT, 4, 11,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_12S4A2] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_12S4A2] } },
+ { 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } } },
+ /* pcrel17a2: comment */
+ { "pcrel17a2", MEP_OPERAND_PCREL17A2, HW_H_SINT, 16, 16,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_17S16A2] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_17S16A2] } },
+ { 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } } },
+ /* pcrel24a2: comment */
+ { "pcrel24a2", MEP_OPERAND_PCREL24A2, HW_H_SINT, 5, 23,
+- { 2, { (const PTR) &MEP_F_24S5A2N_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &MEP_F_24S5A2N_MULTI_IFIELD[0] } },
+ { 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } } },
+ /* pcabs24a2: comment */
+ { "pcabs24a2", MEP_OPERAND_PCABS24A2, HW_H_UINT, 5, 23,
+- { 2, { (const PTR) &MEP_F_24U5A2N_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &MEP_F_24U5A2N_MULTI_IFIELD[0] } },
+ { 0|A(ABS_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } } },
+ /* sdisp16: comment */
+ { "sdisp16", MEP_OPERAND_SDISP16, HW_H_SINT, 16, 16,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_16S16] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_16S16] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* simm16: comment */
+ { "simm16", MEP_OPERAND_SIMM16, HW_H_SINT, 16, 16,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_16S16] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_16S16] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* uimm16: comment */
+ { "uimm16", MEP_OPERAND_UIMM16, HW_H_UINT, 16, 16,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_16U16] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_16U16] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* code16: uci/dsp code (16 bits) */
+ { "code16", MEP_OPERAND_CODE16, HW_H_UINT, 16, 16,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_16U16] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_16U16] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* udisp2: SSARB addend (2 bits) */
+ { "udisp2", MEP_OPERAND_UDISP2, HW_H_SINT, 6, 2,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_2U6] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_2U6] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* uimm2: interrupt (2 bits) */
+ { "uimm2", MEP_OPERAND_UIMM2, HW_H_UINT, 10, 2,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_2U10] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_2U10] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* simm6: add const (6 bits) */
+ { "simm6", MEP_OPERAND_SIMM6, HW_H_SINT, 8, 6,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_6S8] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_6S8] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* simm8: mov const (8 bits) */
+ { "simm8", MEP_OPERAND_SIMM8, HW_H_SINT, 8, 8,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_8S8] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_8S8] } },
+ { 0|A(RELOC_IMPLIES_OVERFLOW), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* addr24a4: comment */
+ { "addr24a4", MEP_OPERAND_ADDR24A4, HW_H_UINT, 8, 22,
+- { 2, { (const PTR) &MEP_F_24U8A4N_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &MEP_F_24U8A4N_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 4, 0 } } } } },
+ /* code24: coprocessor code */
+ { "code24", MEP_OPERAND_CODE24, HW_H_UINT, 4, 24,
+- { 2, { (const PTR) &MEP_F_24U4N_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &MEP_F_24U4N_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* callnum: system call number */
+ { "callnum", MEP_OPERAND_CALLNUM, HW_H_UINT, 5, 4,
+- { 4, { (const PTR) &MEP_F_CALLNUM_MULTI_IFIELD[0] } },
++ { 4, { (const PTR) &MEP_F_CALLNUM_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* uimm3: bit immediate (3 bits) */
+ { "uimm3", MEP_OPERAND_UIMM3, HW_H_UINT, 5, 3,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_3U5] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_3U5] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* uimm4: bCC const (4 bits) */
+ { "uimm4", MEP_OPERAND_UIMM4, HW_H_UINT, 8, 4,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_4U8] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_4U8] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* uimm5: bit/shift val (5 bits) */
+ { "uimm5", MEP_OPERAND_UIMM5, HW_H_UINT, 8, 5,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_5U8] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_5U8] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* udisp7: comment */
+ { "udisp7", MEP_OPERAND_UDISP7, HW_H_UINT, 9, 7,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7U9] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7U9] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* udisp7a2: comment */
+ { "udisp7a2", MEP_OPERAND_UDISP7A2, HW_H_UINT, 9, 6,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7U9A2] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7U9A2] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 2, 0 } } } } },
+ /* udisp7a4: comment */
+ { "udisp7a4", MEP_OPERAND_UDISP7A4, HW_H_UINT, 9, 5,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7U9A4] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7U9A4] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 4, 0 } } } } },
+ /* uimm7a4: comment */
+ { "uimm7a4", MEP_OPERAND_UIMM7A4, HW_H_UINT, 9, 5,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7U9A4] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7U9A4] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 4, 0 } } } } },
+ /* uimm24: immediate (24 bits) */
+ { "uimm24", MEP_OPERAND_UIMM24, HW_H_UINT, 8, 24,
+- { 2, { (const PTR) &MEP_F_24U8N_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &MEP_F_24U8N_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* cimm4: cache immed'te (4 bits) */
+ { "cimm4", MEP_OPERAND_CIMM4, HW_H_UINT, 4, 4,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* cimm5: clip immediate (5 bits) */
+ { "cimm5", MEP_OPERAND_CIMM5, HW_H_UINT, 24, 5,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_5U24] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_5U24] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* cdisp10: comment */
+ { "cdisp10", MEP_OPERAND_CDISP10, HW_H_SINT, 22, 10,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CDISP10] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CDISP10] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* cdisp10a2: comment */
+ { "cdisp10a2", MEP_OPERAND_CDISP10A2, HW_H_SINT, 22, 10,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CDISP10] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CDISP10] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* cdisp10a4: comment */
+ { "cdisp10a4", MEP_OPERAND_CDISP10A4, HW_H_SINT, 22, 10,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CDISP10] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CDISP10] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* cdisp10a8: comment */
+ { "cdisp10a8", MEP_OPERAND_CDISP10A8, HW_H_SINT, 22, 10,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CDISP10] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CDISP10] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* zero: Zero operand */
+ { "zero", MEP_OPERAND_ZERO, HW_H_SINT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* rl5: register Rl c5 */
+ { "rl5", MEP_OPERAND_RL5, HW_H_GPR, 20, 4,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RL5] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RL5] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* cdisp12: copro addend (12 bits) */
+ { "cdisp12", MEP_OPERAND_CDISP12, HW_H_SINT, 20, 12,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_12S20] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_12S20] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* c5rmuimm20: 20-bit immediate in rm and imm16 */
+ { "c5rmuimm20", MEP_OPERAND_C5RMUIMM20, HW_H_UINT, 8, 20,
+- { 2, { (const PTR) &MEP_F_C5_RMUIMM20_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &MEP_F_C5_RMUIMM20_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* c5rnmuimm24: 24-bit immediate in rn, rm, and imm16 */
+ { "c5rnmuimm24", MEP_OPERAND_C5RNMUIMM24, HW_H_UINT, 4, 24,
+- { 2, { (const PTR) &MEP_F_C5_RNMUIMM24_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &MEP_F_C5_RNMUIMM24_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* cp_flag: branch condition register */
+ { "cp_flag", MEP_OPERAND_CP_FLAG, HW_H_CCR, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* ivc2_csar0: ivc2_csar0 */
+ { "ivc2_csar0", MEP_OPERAND_IVC2_CSAR0, HW_H_CCR_IVC2, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* ivc2_cc: ivc2_cc */
+ { "ivc2_cc", MEP_OPERAND_IVC2_CC, HW_H_CCR_IVC2, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* ivc2_cofr0: ivc2_cofr0 */
+ { "ivc2_cofr0", MEP_OPERAND_IVC2_COFR0, HW_H_CCR_IVC2, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* ivc2_cofr1: ivc2_cofr1 */
+ { "ivc2_cofr1", MEP_OPERAND_IVC2_COFR1, HW_H_CCR_IVC2, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* ivc2_cofa0: ivc2_cofa0 */
+ { "ivc2_cofa0", MEP_OPERAND_IVC2_COFA0, HW_H_CCR_IVC2, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* ivc2_cofa1: ivc2_cofa1 */
+ { "ivc2_cofa1", MEP_OPERAND_IVC2_COFA1, HW_H_CCR_IVC2, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* ivc2_csar1: ivc2_csar1 */
+ { "ivc2_csar1", MEP_OPERAND_IVC2_CSAR1, HW_H_CCR_IVC2, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* ivc2_acc0_0: acc0_0 */
+ { "ivc2_acc0_0", MEP_OPERAND_IVC2_ACC0_0, HW_H_CCR_IVC2, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* ivc2_acc0_1: acc0_1 */
+ { "ivc2_acc0_1", MEP_OPERAND_IVC2_ACC0_1, HW_H_CCR_IVC2, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* ivc2_acc0_2: acc0_2 */
+ { "ivc2_acc0_2", MEP_OPERAND_IVC2_ACC0_2, HW_H_CCR_IVC2, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* ivc2_acc0_3: acc0_3 */
+ { "ivc2_acc0_3", MEP_OPERAND_IVC2_ACC0_3, HW_H_CCR_IVC2, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* ivc2_acc0_4: acc0_4 */
+ { "ivc2_acc0_4", MEP_OPERAND_IVC2_ACC0_4, HW_H_CCR_IVC2, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* ivc2_acc0_5: acc0_5 */
+ { "ivc2_acc0_5", MEP_OPERAND_IVC2_ACC0_5, HW_H_CCR_IVC2, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* ivc2_acc0_6: acc0_6 */
+ { "ivc2_acc0_6", MEP_OPERAND_IVC2_ACC0_6, HW_H_CCR_IVC2, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* ivc2_acc0_7: acc0_7 */
+ { "ivc2_acc0_7", MEP_OPERAND_IVC2_ACC0_7, HW_H_CCR_IVC2, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* ivc2_acc1_0: acc1_0 */
+ { "ivc2_acc1_0", MEP_OPERAND_IVC2_ACC1_0, HW_H_CCR_IVC2, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* ivc2_acc1_1: acc1_1 */
+ { "ivc2_acc1_1", MEP_OPERAND_IVC2_ACC1_1, HW_H_CCR_IVC2, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* ivc2_acc1_2: acc1_2 */
+ { "ivc2_acc1_2", MEP_OPERAND_IVC2_ACC1_2, HW_H_CCR_IVC2, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* ivc2_acc1_3: acc1_3 */
+ { "ivc2_acc1_3", MEP_OPERAND_IVC2_ACC1_3, HW_H_CCR_IVC2, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* ivc2_acc1_4: acc1_4 */
+ { "ivc2_acc1_4", MEP_OPERAND_IVC2_ACC1_4, HW_H_CCR_IVC2, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* ivc2_acc1_5: acc1_5 */
+ { "ivc2_acc1_5", MEP_OPERAND_IVC2_ACC1_5, HW_H_CCR_IVC2, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* ivc2_acc1_6: acc1_6 */
+ { "ivc2_acc1_6", MEP_OPERAND_IVC2_ACC1_6, HW_H_CCR_IVC2, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* ivc2_acc1_7: acc1_7 */
+ { "ivc2_acc1_7", MEP_OPERAND_IVC2_ACC1_7, HW_H_CCR_IVC2, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* croc: $CRo C3 */
+ { "croc", MEP_OPERAND_CROC, HW_H_CR64, 7, 5,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U7] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U7] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } } },
+ /* crqc: $CRq C3 */
+ { "crqc", MEP_OPERAND_CRQC, HW_H_CR64, 21, 5,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U21] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U21] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } } },
+ /* crpc: $CRp C3 */
+ { "crpc", MEP_OPERAND_CRPC, HW_H_CR64, 26, 5,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U26] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U26] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } } },
+ /* ivc-x-6-1: filler */
+ { "ivc-x-6-1", MEP_OPERAND_IVC_X_6_1, HW_H_UINT, 6, 1,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_1U6] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_1U6] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* ivc-x-6-2: filler */
+ { "ivc-x-6-2", MEP_OPERAND_IVC_X_6_2, HW_H_UINT, 6, 2,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_2U6] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_2U6] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* ivc-x-6-3: filler */
+ { "ivc-x-6-3", MEP_OPERAND_IVC_X_6_3, HW_H_UINT, 6, 3,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_3U6] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_3U6] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* imm3p4: Imm3p4 */
+ { "imm3p4", MEP_OPERAND_IMM3P4, HW_H_UINT, 4, 3,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_3U4] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_3U4] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* imm3p9: Imm3p9 */
+ { "imm3p9", MEP_OPERAND_IMM3P9, HW_H_UINT, 9, 3,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_3U9] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_3U9] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* imm4p8: Imm4p8 */
+ { "imm4p8", MEP_OPERAND_IMM4P8, HW_H_UINT, 8, 4,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_4U8] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_4U8] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* imm5p7: Imm5p7 */
+ { "imm5p7", MEP_OPERAND_IMM5P7, HW_H_UINT, 7, 5,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U7] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U7] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* imm6p6: Imm6p6 */
+ { "imm6p6", MEP_OPERAND_IMM6P6, HW_H_UINT, 6, 6,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_6U6] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_6U6] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* imm8p4: Imm8p4 */
+ { "imm8p4", MEP_OPERAND_IMM8P4, HW_H_UINT, 4, 8,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8U4] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8U4] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* simm8p4: sImm8p4 */
+ { "simm8p4", MEP_OPERAND_SIMM8P4, HW_H_SINT, 4, 8,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8S4] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8S4] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* imm3p5: Imm3p5 */
+ { "imm3p5", MEP_OPERAND_IMM3P5, HW_H_UINT, 5, 3,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_3U5] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_3U5] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* imm3p12: Imm3p12 */
+ { "imm3p12", MEP_OPERAND_IMM3P12, HW_H_UINT, 12, 3,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_3U12] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_3U12] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* imm4p4: Imm4p4 */
+ { "imm4p4", MEP_OPERAND_IMM4P4, HW_H_UINT, 4, 4,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_4U4] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_4U4] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* imm4p10: Imm4p10 */
+ { "imm4p10", MEP_OPERAND_IMM4P10, HW_H_UINT, 10, 4,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_4U10] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_4U10] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* imm5p8: Imm5p8 */
+ { "imm5p8", MEP_OPERAND_IMM5P8, HW_H_UINT, 8, 5,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U8] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U8] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* imm5p3: Imm5p3 */
+ { "imm5p3", MEP_OPERAND_IMM5P3, HW_H_UINT, 3, 5,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U3] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U3] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* imm6p2: Imm6p2 */
+ { "imm6p2", MEP_OPERAND_IMM6P2, HW_H_UINT, 2, 6,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_6U2] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_6U2] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* imm5p23: Imm5p23 */
+ { "imm5p23", MEP_OPERAND_IMM5P23, HW_H_UINT, 23, 5,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U23] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U23] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* imm3p25: Imm3p25 */
+ { "imm3p25", MEP_OPERAND_IMM3P25, HW_H_UINT, 25, 3,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_3U25] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_3U25] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* imm8p0: Imm8p0 */
+ { "imm8p0", MEP_OPERAND_IMM8P0, HW_H_UINT, 0, 8,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8U0] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8U0] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* simm8p0: sImm8p0 */
+ { "simm8p0", MEP_OPERAND_SIMM8P0, HW_H_SINT, 0, 8,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8S0] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8S0] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* simm8p20: sImm8p20 */
+ { "simm8p20", MEP_OPERAND_SIMM8P20, HW_H_SINT, 20, 8,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8S20] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8S20] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* imm8p20: Imm8p20 */
+ { "imm8p20", MEP_OPERAND_IMM8P20, HW_H_UINT, 20, 8,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8U20] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8U20] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* crop: $CRo Pn */
+ { "crop", MEP_OPERAND_CROP, HW_H_CR64, 23, 5,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U23] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U23] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } } },
+ /* crqp: $CRq Pn */
+ { "crqp", MEP_OPERAND_CRQP, HW_H_CR64, 13, 5,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U13] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U13] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } } },
+ /* crpp: $CRp Pn */
+ { "crpp", MEP_OPERAND_CRPP, HW_H_CR64, 18, 5,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U18] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U18] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } } },
+ /* ivc-x-0-2: filler */
+ { "ivc-x-0-2", MEP_OPERAND_IVC_X_0_2, HW_H_UINT, 0, 2,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_2U0] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_2U0] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* ivc-x-0-3: filler */
+ { "ivc-x-0-3", MEP_OPERAND_IVC_X_0_3, HW_H_UINT, 0, 3,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_3U0] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_3U0] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* ivc-x-0-4: filler */
+ { "ivc-x-0-4", MEP_OPERAND_IVC_X_0_4, HW_H_UINT, 0, 4,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_4U0] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_4U0] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* ivc-x-0-5: filler */
+ { "ivc-x-0-5", MEP_OPERAND_IVC_X_0_5, HW_H_UINT, 0, 5,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U0] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U0] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* imm16p0: comment */
+ { "imm16p0", MEP_OPERAND_IMM16P0, HW_H_UINT, 0, 16,
+- { 2, { (const PTR) &MEP_F_IVC2_IMM16P0_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &MEP_F_IVC2_IMM16P0_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* simm16p0: comment */
+ { "simm16p0", MEP_OPERAND_SIMM16P0, HW_H_SINT, 0, 16,
+- { 2, { (const PTR) &MEP_F_IVC2_SIMM16P0_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &MEP_F_IVC2_SIMM16P0_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* ivc2rm: reg Rm */
+ { "ivc2rm", MEP_OPERAND_IVC2RM, HW_H_GPR, 4, 4,
+- { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_CRM] } },
++ { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_CRM] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ /* ivc2crn: copro Rn (0-31, 64-bit */
+ { "ivc2crn", MEP_OPERAND_IVC2CRN, HW_H_CR64, 0, 5,
+- { 2, { (const PTR) &MEP_F_IVC2_CRNX_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &MEP_F_IVC2_CRNX_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } } },
+ /* ivc2ccrn: copro control reg CCRn */
+ { "ivc2ccrn", MEP_OPERAND_IVC2CCRN, HW_H_CCR_IVC2, 0, 6,
+- { 2, { (const PTR) &MEP_F_IVC2_CCRN_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &MEP_F_IVC2_CCRN_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_REGNUM, 0 } }, { { 1, 0 } } } } },
+ /* ivc2c3ccrn: copro control reg CCRn */
+ { "ivc2c3ccrn", MEP_OPERAND_IVC2C3CCRN, HW_H_CCR_IVC2, 4, 6,
+- { 2, { (const PTR) &MEP_F_IVC2_CCRN_C3_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &MEP_F_IVC2_CCRN_C3_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_REGNUM, 0 } }, { { 1, 0 } } } } },
+ /* sentinel */
+ { 0, 0, 0, 0, 0,
+@@ -6329,7 +6329,7 @@ mep_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
+
+ /* Default to not allowing signed overflow. */
+ cd->signed_overflow_ok_p = 0;
+-
++
+ return (CGEN_CPU_DESC) cd;
+ }
+
+@@ -6369,7 +6369,7 @@ mep_cgen_cpu_close (CGEN_CPU_DESC cd)
+ for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
+ if (CGEN_INSN_RX (insns))
+ regfree (CGEN_INSN_RX (insns));
+- }
++ }
+
+ if (cd->macro_insn_table.init_entries)
+ free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
+--- a/opcodes/mep-dis.c
++++ b/opcodes/mep-dis.c
+@@ -78,7 +78,7 @@ print_tpreg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, PTR dis_info,
+ }
+
+ static void
+-print_spreg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, PTR dis_info,
++print_spreg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, PTR dis_info,
+ CGEN_KEYWORD *table ATTRIBUTE_UNUSED, long val ATTRIBUTE_UNUSED,
+ unsigned int flags ATTRIBUTE_UNUSED)
+ {
+@@ -143,11 +143,11 @@ mep_print_vliw_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info,
+ if (corelength > 0)
+ {
+ int my_status = 0;
+-
++
+ for (i = 0; i < corelength; i++ )
+ insnbuf[i] = buf[i];
+ cd->isas = & MEP_CORE_ISA;
+-
++
+ my_status = print_insn (cd, pc, info, insnbuf, corelength);
+ if (my_status != corelength)
+ {
+@@ -159,7 +159,7 @@ mep_print_vliw_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info,
+ /* Print the + to indicate that the following copro insn is */
+ /* part of a vliw group. */
+ if (copro1length > 0)
+- (*info->fprintf_func) (info->stream, " + ");
++ (*info->fprintf_func) (info->stream, " + ");
+ }
+
+ /* Now all that is left to be processed is the coprocessor insns
+@@ -171,7 +171,7 @@ mep_print_vliw_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info,
+ if (copro1length > 0)
+ {
+ int my_status = 0;
+-
++
+ for (i = corelength; i < corelength + copro1length; i++ )
+ insnbuf[i - corelength] = buf[i];
+
+@@ -190,7 +190,7 @@ mep_print_vliw_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info,
+ break;
+ case 8:
+ cd->isas = & MEP_COP64_ISA;
+- break;
++ break;
+ default:
+ /* Shouldn't be anything but 16,32,48,64. */
+ break;
+@@ -223,7 +223,7 @@ mep_print_vliw_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info,
+
+ for (i = corelength + copro1length; i < 64; i++)
+ insnbuf[i - (corelength + copro1length)] = buf[i];
+-
++
+ switch (copro2length)
+ {
+ case 2:
+@@ -236,7 +236,7 @@ mep_print_vliw_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info,
+ cd->isas = 1 << ISA_EXT_COP1_48;
+ break;
+ case 8:
+- cd->isas = 1 << ISA_EXT_COP1_64;
++ cd->isas = 1 << ISA_EXT_COP1_64;
+ break;
+ default:
+ /* Shouldn't be anything but 16,32,48,64. */
+@@ -264,29 +264,29 @@ mep_print_vliw_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info,
+ return status;
+ }
+
+-/* The two functions mep_examine_vliw[32,64]_insns are used find out
+- which vliw combinaion (16 bit core with 48 bit copro, 32 bit core
+- with 32 bit copro, etc.) is present. Later on, when internally
+- parallel coprocessors are handled, only these functions should
+- need to be changed.
++/* The two functions mep_examine_vliw[32,64]_insns are used find out
++ which vliw combinaion (16 bit core with 48 bit copro, 32 bit core
++ with 32 bit copro, etc.) is present. Later on, when internally
++ parallel coprocessors are handled, only these functions should
++ need to be changed.
++
++ At this time only the following combinations are supported:
+
+- At this time only the following combinations are supported:
+-
+ VLIW32 Mode:
+ 16 bit core insn (core) and 16 bit coprocessor insn (cop1)
+ 32 bit core insn (core)
+ 32 bit coprocessor insn (cop1)
+ Note: As of this time, I do not believe we have enough information
+ to distinguish a 32 bit core insn from a 32 bit cop insn. Also,
+- no 16 bit coprocessor insns have been specified.
++ no 16 bit coprocessor insns have been specified.
+
+ VLIW64 Mode:
+ 16 bit core insn (core) and 48 bit coprocessor insn (cop1)
+ 32 bit core insn (core) and 32 bit coprocessor insn (cop1)
+ 64 bit coprocessor insn (cop1)
+-
++
+ The framework for an internally parallel coprocessor is also
+- present (2nd coprocessor insn is cop2), but at this time it
++ present (2nd coprocessor insn is cop2), but at this time it
+ is not used. This only appears to be valid in VLIW64 mode. */
+
+ static int
+@@ -297,9 +297,9 @@ mep_examine_vliw32_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
+ int corebuflength;
+ int cop1buflength;
+ int cop2buflength;
+- bfd_byte buf[CGEN_MAX_INSN_SIZE];
++ bfd_byte buf[CGEN_MAX_INSN_SIZE];
+ char indicator16[1];
+- char indicatorcop32[2];
++ char indicatorcop32[2];
+
+ /* At this time we're not supporting internally parallel coprocessors,
+ so cop2buflength will always be 0. */
+@@ -1189,7 +1189,7 @@ mep_cgen_print_operand (CGEN_CPU_DESC cd,
+ }
+ }
+
+-cgen_print_fn * const mep_cgen_print_handlers[] =
++cgen_print_fn * const mep_cgen_print_handlers[] =
+ {
+ print_insn_normal,
+ };
+@@ -1379,7 +1379,7 @@ print_insn (CGEN_CPU_DESC cd,
+ int length;
+ unsigned long insn_value_cropped;
+
+-#ifdef CGEN_VALIDATE_INSN_SUPPORTED
++#ifdef CGEN_VALIDATE_INSN_SUPPORTED
+ /* Not needed as insn shouldn't be in hash lists if not supported. */
+ /* Supported by this cpu? */
+ if (! mep_cgen_insn_supported (cd, insn))
+@@ -1397,7 +1397,7 @@ print_insn (CGEN_CPU_DESC cd,
+ relevant part from the buffer. */
+ if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
+ (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
+- insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
++ insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
+ info->endian == BFD_ENDIAN_BIG);
+ else
+ insn_value_cropped = insn_value;
+@@ -1516,7 +1516,7 @@ print_insn_mep (bfd_vma pc, disassemble_info *info)
+ arch = info->arch;
+ if (arch == bfd_arch_unknown)
+ arch = CGEN_BFD_ARCH;
+-
++
+ /* There's no standard way to compute the machine or isa number
+ so we leave it to the target. */
+ #ifdef CGEN_COMPUTE_MACH
+@@ -1557,7 +1557,7 @@ print_insn_mep (bfd_vma pc, disassemble_info *info)
+ break;
+ }
+ }
+- }
++ }
+
+ /* If we haven't initialized yet, initialize the opcode table. */
+ if (! cd)
+--- a/opcodes/mep-ibld.c
++++ b/opcodes/mep-ibld.c
+@@ -154,7 +154,7 @@ insert_normal (CGEN_CPU_DESC cd,
+ {
+ long minval = - (1L << (length - 1));
+ unsigned long maxval = mask;
+-
++
+ if ((value > 0 && (unsigned long) value > maxval)
+ || value < minval)
+ {
+@@ -192,7 +192,7 @@ insert_normal (CGEN_CPU_DESC cd,
+ {
+ long minval = - (1L << (length - 1));
+ long maxval = (1L << (length - 1)) - 1;
+-
++
+ if (value < minval || value > maxval)
+ {
+ sprintf
+@@ -1808,12 +1808,12 @@ mep_cgen_extract_operand (CGEN_CPU_DESC cd,
+ return length;
+ }
+
+-cgen_insert_fn * const mep_cgen_insert_handlers[] =
++cgen_insert_fn * const mep_cgen_insert_handlers[] =
+ {
+ insert_insn_normal,
+ };
+
+-cgen_extract_fn * const mep_cgen_extract_handlers[] =
++cgen_extract_fn * const mep_cgen_extract_handlers[] =
+ {
+ extract_insn_normal,
+ };
+--- a/opcodes/mep-opc.h
++++ b/opcodes/mep-opc.h
+@@ -87,7 +87,7 @@ extern CGEN_ATTR_VALUE_BITSET_TYPE mep_all_core_isas_mask;
+ )
+
+ /* A mask for all ISAs executed by a VLIW coprocessor. */
+-#define MEP_ALL_COP_ISAS_MASK mep_all_cop_isas_mask
++#define MEP_ALL_COP_ISAS_MASK mep_all_cop_isas_mask
+ extern CGEN_ATTR_VALUE_BITSET_TYPE mep_all_cop_isas_mask;
+
+ #define MEP_INSN_COP_P(insn) ( \
+#--- a/opcodes/microblaze-dis.h
+#+++ b/opcodes/microblaze-dis.h
+#@@ -26,12 +26,12 @@
+# extern "C" {
+# #endif
+#
+#-extern enum microblaze_instr microblaze_decode_insn (long, int *, int *,
+#+extern enum microblaze_instr microblaze_decode_insn (long, int *, int *,
+# int *, int *);
+# extern unsigned long microblaze_get_target_address (long, bfd_boolean, int,
+# long, long, long, bfd_boolean *, bfd_boolean *);
+#
+#-extern enum microblaze_instr get_insn_microblaze (long, bfd_boolean *,
+#+extern enum microblaze_instr get_insn_microblaze (long, bfd_boolean *,
+# enum microblaze_instr_type *,
+# short *);
+#
+#--- a/opcodes/microblaze-opc.h
+#+++ b/opcodes/microblaze-opc.h
+#@@ -1,5 +1,5 @@
+# /* microblaze-opc.h -- MicroBlaze Opcodes
+#-
+#+
+# Copyright (C) 2009-2015 Free Software Foundation, Inc.
+#
+# This file is part of the GNU opcodes library.
+#@@ -63,12 +63,12 @@
+#
+#
+#
+#-/* Instructions where the label address is resolved as a PC offset
+#+/* Instructions where the label address is resolved as a PC offset
+# (for branch label). */
+#-#define INST_PC_OFFSET 1
+#-/* Instructions where the label address is resolved as an absolute
+#+#define INST_PC_OFFSET 1
+#+/* Instructions where the label address is resolved as an absolute
+# value (for data mem or abs address). */
+#-#define INST_NO_OFFSET 0
+#+#define INST_NO_OFFSET 0
+#
+# #define IMMVAL_MASK_NON_SPECIAL 0x0000
+# #define IMMVAL_MASK_MTS 0x4000
+#@@ -81,14 +81,14 @@
+# #define OPCODE_MASK_H4 0xFC0007FF /* High 6 and low 11 bits. */
+# #define OPCODE_MASK_H13S 0xFFE0E7F0 /* High 11 16:18 21:27 bits, 19:20 bits
+# and last nibble of last byte for spr. */
+#-#define OPCODE_MASK_H23S 0xFC1FC000 /* High 6, 20-16 and 15:1 bits and last
+#+#define OPCODE_MASK_H23S 0xFC1FC000 /* High 6, 20-16 and 15:1 bits and last
+# nibble of last byte for spr. */
+# #define OPCODE_MASK_H34 0xFC00FFFF /* High 6 and low 16 bits. */
+# #define OPCODE_MASK_H14 0xFFE007FF /* High 11 and low 11 bits. */
+# #define OPCODE_MASK_H24 0xFC1F07FF /* High 6, bits 20-16 and low 11 bits. */
+# #define OPCODE_MASK_H124 0xFFFF07FF /* High 16, and low 11 bits. */
+# #define OPCODE_MASK_H1234 0xFFFFFFFF /* All 32 bits. */
+#-#define OPCODE_MASK_H3 0xFC000600 /* High 6 bits and bits 21, 22. */
+#+#define OPCODE_MASK_H3 0xFC000600 /* High 6 bits and bits 21, 22. */
+# #define OPCODE_MASK_H32 0xFC00FC00 /* High 6 bits and bit 16-21. */
+# #define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits. */
+# #define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26. */
+#@@ -110,15 +110,15 @@ struct op_code_struct
+# short inst_offset_type; /* Immediate vals offset from PC? (= 1 for branches). */
+# short delay_slots; /* Info about delay slots needed after this instr. */
+# short immval_mask;
+#- unsigned long bit_sequence; /* All the fixed bits for the op are set and
+#- all the variable bits (reg names, imm vals)
+#- are set to 0. */
+#+ unsigned long bit_sequence; /* All the fixed bits for the op are set and
+#+ all the variable bits (reg names, imm vals)
+#+ are set to 0. */
+# unsigned long opcode_mask; /* Which bits define the opcode. */
+# enum microblaze_instr instr;
+# enum microblaze_instr_type instr_type;
+# /* More info about output format here. */
+#-} opcodes[MAX_OPCODES] =
+#-{
+#+} opcodes[MAX_OPCODES] =
+#+{
+# {"add", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x00000000, OPCODE_MASK_H4, add, arithmetic_inst },
+# {"rsub", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H4, rsub, arithmetic_inst },
+# {"addc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x08000000, OPCODE_MASK_H4, addc, arithmetic_inst },
+#@@ -277,7 +277,7 @@ struct op_code_struct
+# {"tcput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00B000, OPCODE_MASK_H32, tcput, anyware_inst },
+# {"tnput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00D000, OPCODE_MASK_H32, tnput, anyware_inst },
+# {"tncput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00F000, OPCODE_MASK_H32, tncput, anyware_inst },
+#-
+#+
+# {"eget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C000400, OPCODE_MASK_H32, eget, anyware_inst },
+# {"ecget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C002400, OPCODE_MASK_H32, ecget, anyware_inst },
+# {"neget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C004400, OPCODE_MASK_H32, neget, anyware_inst },
+#@@ -286,7 +286,7 @@ struct op_code_struct
+# {"ecput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00A400, OPCODE_MASK_H32, ecput, anyware_inst },
+# {"neput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00C400, OPCODE_MASK_H32, neput, anyware_inst },
+# {"necput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E400, OPCODE_MASK_H32, necput, anyware_inst },
+#-
+#+
+# {"teget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C001400, OPCODE_MASK_H32, teget, anyware_inst },
+# {"tecget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C003400, OPCODE_MASK_H32, tecget, anyware_inst },
+# {"tneget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C005400, OPCODE_MASK_H32, tneget, anyware_inst },
+#@@ -295,7 +295,7 @@ struct op_code_struct
+# {"tecput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00B400, OPCODE_MASK_H32, tecput, anyware_inst },
+# {"tneput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00D400, OPCODE_MASK_H32, tneput, anyware_inst },
+# {"tnecput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00F400, OPCODE_MASK_H32, tnecput, anyware_inst },
+#-
+#+
+# {"aget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C000800, OPCODE_MASK_H32, aget, anyware_inst },
+# {"caget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C002800, OPCODE_MASK_H32, caget, anyware_inst },
+# {"naget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C004800, OPCODE_MASK_H32, naget, anyware_inst },
+#@@ -304,7 +304,7 @@ struct op_code_struct
+# {"caput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00A800, OPCODE_MASK_H32, caput, anyware_inst },
+# {"naput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00C800, OPCODE_MASK_H32, naput, anyware_inst },
+# {"ncaput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E800, OPCODE_MASK_H32, ncaput, anyware_inst },
+#-
+#+
+# {"taget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C001800, OPCODE_MASK_H32, taget, anyware_inst },
+# {"tcaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C003800, OPCODE_MASK_H32, tcaget, anyware_inst },
+# {"tnaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C005800, OPCODE_MASK_H32, tnaget, anyware_inst },
+#@@ -313,7 +313,7 @@ struct op_code_struct
+# {"tcaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00B800, OPCODE_MASK_H32, tcaput, anyware_inst },
+# {"tnaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00D800, OPCODE_MASK_H32, tnaput, anyware_inst },
+# {"tncaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00F800, OPCODE_MASK_H32, tncaput, anyware_inst },
+#-
+#+
+# {"eaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C000C00, OPCODE_MASK_H32, eget, anyware_inst },
+# {"ecaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C002C00, OPCODE_MASK_H32, ecget, anyware_inst },
+# {"neaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C004C00, OPCODE_MASK_H32, neget, anyware_inst },
+#@@ -322,7 +322,7 @@ struct op_code_struct
+# {"ecaput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00AC00, OPCODE_MASK_H32, ecput, anyware_inst },
+# {"neaput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00CC00, OPCODE_MASK_H32, neput, anyware_inst },
+# {"necaput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00EC00, OPCODE_MASK_H32, necput, anyware_inst },
+#-
+#+
+# {"teaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C001C00, OPCODE_MASK_H32, teaget, anyware_inst },
+# {"tecaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C003C00, OPCODE_MASK_H32, tecaget, anyware_inst },
+# {"tneaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C005C00, OPCODE_MASK_H32, tneaget, anyware_inst },
+#@@ -331,7 +331,7 @@ struct op_code_struct
+# {"tecaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00BC00, OPCODE_MASK_H32, tecaput, anyware_inst },
+# {"tneaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00DC00, OPCODE_MASK_H32, tneaput, anyware_inst },
+# {"tnecaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00FC00, OPCODE_MASK_H32, tnecaput, anyware_inst },
+#-
+#+
+# {"getd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000000, OPCODE_MASK_H34C, getd, anyware_inst },
+# {"tgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000080, OPCODE_MASK_H34C, tgetd, anyware_inst },
+# {"cgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000100, OPCODE_MASK_H34C, cgetd, anyware_inst },
+#@@ -348,7 +348,7 @@ struct op_code_struct
+# {"tnputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000680, OPCODE_MASK_H34C, tnputd, anyware_inst },
+# {"ncputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000700, OPCODE_MASK_H34C, ncputd, anyware_inst },
+# {"tncputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000780, OPCODE_MASK_H34C, tncputd, anyware_inst },
+#-
+#+
+# {"egetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000020, OPCODE_MASK_H34C, egetd, anyware_inst },
+# {"tegetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0000A0, OPCODE_MASK_H34C, tegetd, anyware_inst },
+# {"ecgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000120, OPCODE_MASK_H34C, ecgetd, anyware_inst },
+#@@ -365,7 +365,7 @@ struct op_code_struct
+# {"tneputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0006A0, OPCODE_MASK_H34C, tneputd, anyware_inst },
+# {"necputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000720, OPCODE_MASK_H34C, necputd, anyware_inst },
+# {"tnecputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0007A0, OPCODE_MASK_H34C, tnecputd, anyware_inst },
+#-
+#+
+# {"agetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000040, OPCODE_MASK_H34C, agetd, anyware_inst },
+# {"tagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0000C0, OPCODE_MASK_H34C, tagetd, anyware_inst },
+# {"cagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000140, OPCODE_MASK_H34C, cagetd, anyware_inst },
+#@@ -382,7 +382,7 @@ struct op_code_struct
+# {"tnaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0006C0, OPCODE_MASK_H34C, tnaputd, anyware_inst },
+# {"ncaputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000740, OPCODE_MASK_H34C, ncaputd, anyware_inst },
+# {"tncaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0007C0, OPCODE_MASK_H34C, tncaputd, anyware_inst },
+#-
+#+
+# {"eagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000060, OPCODE_MASK_H34C, eagetd, anyware_inst },
+# {"teagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0000E0, OPCODE_MASK_H34C, teagetd, anyware_inst },
+# {"ecagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000160, OPCODE_MASK_H34C, ecagetd, anyware_inst },
+#--- a/opcodes/microblaze-opcm.h
+#+++ b/opcodes/microblaze-opcm.h
+#@@ -18,7 +18,7 @@
+# along with this file; see the file COPYING. If not, write to the
+# Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA. */
+#-
+#+
+#
+# #ifndef MICROBLAZE_OPCM
+# #define MICROBLAZE_OPCM
+#@@ -26,23 +26,23 @@
+# enum microblaze_instr
+# {
+# add, rsub, addc, rsubc, addk, rsubk, addkc, rsubkc, clz, cmp, cmpu,
+#- addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul,
+#+ addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul,
+# mulh, mulhu, mulhsu,swapb,swaph,
+# idiv, idivu, bsll, bsra, bsrl, get, put, nget, nput, cget, cput,
+# ncget, ncput, muli, bslli, bsrai, bsrli, mului,
+# /* 'or/and/xor' are C++ keywords. */
+# microblaze_or, microblaze_and, microblaze_xor,
+#- andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
+#+ andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
+# wic, wdc, wdcclear, wdcflush, mts, mfs, mbar, br, brd,
+# brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
+# bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
+# imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
+# brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti,
+#- bgtid, bgei, bgeid, lbu, lbur, lhu, lhur, lw, lwr, lwx, sb, sbr, sh,
+#+ bgtid, bgei, bgeid, lbu, lbur, lhu, lhur, lw, lwr, lwx, sb, sbr, sh,
+# shr, sw, swr, swx, lbui, lhui, lwi,
+#- sbi, shi, swi, msrset, msrclr, tuqula, fadd, frsub, fmul, fdiv,
+#- fcmp_lt, fcmp_eq, fcmp_le, fcmp_gt, fcmp_ne, fcmp_ge, fcmp_un, flt,
+#- fint, fsqrt,
+#+ sbi, shi, swi, msrset, msrclr, tuqula, fadd, frsub, fmul, fdiv,
+#+ fcmp_lt, fcmp_eq, fcmp_le, fcmp_gt, fcmp_ne, fcmp_ge, fcmp_un, flt,
+#+ fint, fsqrt,
+# tget, tcget, tnget, tncget, tput, tcput, tnput, tncput,
+# eget, ecget, neget, necget, eput, ecput, neput, necput,
+# teget, tecget, tneget, tnecget, teput, tecput, tneput, tnecput,
+#@@ -123,7 +123,7 @@ enum microblaze_instr_type
+# /* Assembler Register - Used in Delay Slot Optimization. */
+# #define REG_AS 18
+# #define REG_ZERO 0
+#-
+#+
+# #define RD_LOW 21 /* Low bit for RD. */
+# #define RA_LOW 16 /* Low bit for RA. */
+# #define RB_LOW 11 /* Low bit for RB. */
+#--- a/opcodes/mips-dis.c
+#+++ b/opcodes/mips-dis.c
+#@@ -875,8 +875,8 @@ parse_mips_dis_option (const char *option, unsigned int len)
+# mips_ase |= ASE_XPA;
+# return;
+# }
+#-
+#-
+#+
+#+
+# /* Look for the = that delimits the end of the option name. */
+# for (i = 0; i < len; i++)
+# if (option[i] == '=')
+#@@ -1709,7 +1709,7 @@ print_insn_mips (bfd_vma memaddr,
+# {
+# for (; op < &mips_opcodes[NUMOPCODES]; op++)
+# {
+#- if (op->pinfo != INSN_MACRO
+#+ if (op->pinfo != INSN_MACRO
+# && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
+# && (word & op->mask) == op->match)
+# {
+#--- a/opcodes/mips-opc.c
+#+++ b/opcodes/mips-opc.c
+#@@ -404,7 +404,7 @@ decode_mips_operand (const char *p)
+#
+# Because of the lookup algorithm used, entries with the same opcode
+# name must be contiguous.
+#-
+#+
+# Many instructions are short hand for other instructions (i.e., The
+# jal <register> instruction is short for jalr <register>). */
+#
+#@@ -2062,8 +2062,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
+# {"zcb", "(b)", 0x7000071f, 0xfc1fffff, RD_1|SM, 0, IOCT2, 0, 0 },
+# {"zcbt", "(b)", 0x7000075f, 0xfc1fffff, RD_1|SM, 0, IOCT2, 0, 0 },
+#
+#-/* Coprocessor 0 move instructions cfc0 and ctc0 conflict with the
+#- mfhc0 and mthc0 XPA instructions, so they have been placed here
+#+/* Coprocessor 0 move instructions cfc0 and ctc0 conflict with the
+#+ mfhc0 and mthc0 XPA instructions, so they have been placed here
+# to allow the XPA instructions to take precedence. */
+# {"ctc0", "t,G", 0x40c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, IOCT|IOCTP|IOCT2 },
+# {"cfc0", "t,G", 0x40400000, 0xffe007ff, WR_1|RD_C0|LC, 0, I1, 0, IOCT|IOCTP|IOCT2 },
+#@@ -2110,7 +2110,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
+# {"qmtc2", "t,+6", 0x48a00000, 0xffe007ff, RD_1|WR_C2, 0, EE, 0, 0 },
+# {"qmtc2.i", "t,+6", 0x48a00001, 0xffe007ff, RD_1|WR_C2, 0, EE, 0, 0 },
+# {"qmtc2.ni", "t,+6", 0x48a00000, 0xffe007ff, RD_1|WR_C2, 0, EE, 0, 0 },
+#-/* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X
+#+/* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X
+# instructions, so they are here for the latters to take precedence. */
+# {"bc3f", "p", 0x4d000000, 0xffff0000, RD_CC|CBD, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 },
+# {"bc3fl", "p", 0x4d020000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, IOCT|IOCTP|IOCT2|EE|I37 },
+--- a/opcodes/moxie-dis.c
++++ b/opcodes/moxie-dis.c
+@@ -210,7 +210,7 @@ print_insn_moxie (bfd_vma addr, struct disassemble_info * info)
+ {
+ case MOXIE_F3_PCREL:
+ fpr (stream, "%s\t", opcode->name);
+- info->print_address_func ((bfd_vma) (addr + INST2OFFSET(iword) + 2),
++ info->print_address_func ((bfd_vma) (addr + INST2OFFSET(iword) + 2),
+ info);
+ break;
+ case MOXIE_BAD:
+#--- a/opcodes/msp430-decode.c
+#+++ b/opcodes/msp430-decode.c
+#@@ -375,7 +375,7 @@ msp430_decode_opcode (unsigned long pc,
+# ID (MSO_mov); SM (srcr, 0); DR (dstr);
+# msp430->size = 20;
+# msp430->ofs_430x = 1;
+#-
+#+
+# }
+# break;
+# case 0x10:
+#@@ -399,7 +399,7 @@ msp430_decode_opcode (unsigned long pc,
+# ID (MSO_mov); SI (srcr); DR (dstr);
+# msp430->size = 20;
+# msp430->ofs_430x = 1;
+#-
+#+
+# }
+# break;
+# case 0x20:
+#@@ -423,7 +423,7 @@ msp430_decode_opcode (unsigned long pc,
+# ID (MSO_mov); SA ((srcr << 16) + IMMU(2)); DR (dstr);
+# msp430->size = 20;
+# msp430->ofs_430x = 1;
+#-
+#+
+# }
+# break;
+# case 0x30:
+#@@ -447,7 +447,7 @@ msp430_decode_opcode (unsigned long pc,
+# ID (MSO_mov); SM (srcr, IMMS(2)); DR (dstr);
+# msp430->size = 20;
+# msp430->ofs_430x = 1;
+#-
+#+
+# }
+# break;
+# case 0x40:
+#@@ -477,7 +477,7 @@ msp430_decode_opcode (unsigned long pc,
+# msp430->size = w ? 16 : 20;
+# msp430->ofs_430x = 1;
+# F_0NZC;
+#-
+#+
+# }
+# break;
+# case 0x60:
+#@@ -501,7 +501,7 @@ msp430_decode_opcode (unsigned long pc,
+# ID (MSO_mov); SR (srcr); DA ((dstr << 16) + IMMU(2));
+# msp430->size = 20;
+# msp430->ofs_430x = 1;
+#-
+#+
+# }
+# break;
+# case 0x70:
+#@@ -525,7 +525,7 @@ msp430_decode_opcode (unsigned long pc,
+# ID (MSO_mov); SR (srcr); DM (dstr, IMMS(2));
+# msp430->size = 20;
+# msp430->ofs_430x = 1;
+#-
+#+
+# }
+# break;
+# case 0x80:
+#@@ -549,7 +549,7 @@ msp430_decode_opcode (unsigned long pc,
+# ID (MSO_mov); SC ((srcr << 16) + IMMU(2)); DR (dstr);
+# msp430->size = 20;
+# msp430->ofs_430x = 1;
+#-
+#+
+# }
+# break;
+# case 0x90:
+#@@ -574,7 +574,7 @@ msp430_decode_opcode (unsigned long pc,
+# msp430->size = 20;
+# msp430->ofs_430x = 1;
+# F_VNZC;
+#-
+#+
+# }
+# break;
+# case 0xa0:
+#@@ -599,7 +599,7 @@ msp430_decode_opcode (unsigned long pc,
+# msp430->size = 20;
+# msp430->ofs_430x = 1;
+# F_VNZC;
+#-
+#+
+# }
+# break;
+# case 0xb0:
+#@@ -624,7 +624,7 @@ msp430_decode_opcode (unsigned long pc,
+# msp430->size = 20;
+# msp430->ofs_430x = 1;
+# F_VNZC;
+#-
+#+
+# }
+# break;
+# case 0xc0:
+#@@ -648,7 +648,7 @@ msp430_decode_opcode (unsigned long pc,
+# ID (MSO_mov); SR (srcr); DR (dstr);
+# msp430->size = 20;
+# msp430->ofs_430x = 1;
+#-
+#+
+# }
+# break;
+# case 0xd0:
+#@@ -673,7 +673,7 @@ msp430_decode_opcode (unsigned long pc,
+# msp430->size = 20;
+# msp430->ofs_430x = 1;
+# F_VNZC;
+#-
+#+
+# }
+# break;
+# case 0xe0:
+#@@ -698,7 +698,7 @@ msp430_decode_opcode (unsigned long pc,
+# msp430->size = 20;
+# msp430->ofs_430x = 1;
+# F_VNZC;
+#-
+#+
+# }
+# break;
+# case 0xf0:
+#@@ -723,7 +723,7 @@ msp430_decode_opcode (unsigned long pc,
+# msp430->size = 20;
+# msp430->ofs_430x = 1;
+# F_VNZC;
+#-
+#+
+# }
+# break;
+# }
+#@@ -771,7 +771,7 @@ msp430_decode_opcode (unsigned long pc,
+# msp430->size = w ? 16 : 20;
+# msp430->ofs_430x = 1;
+# F_0NZC;
+#-
+#+
+# }
+# break;
+# case 0x60:
+#@@ -849,7 +849,7 @@ msp430_decode_opcode (unsigned long pc,
+# msp430->size = w ? 16 : 20;
+# msp430->ofs_430x = 1;
+# F_0NZC;
+#-
+#+
+# }
+# break;
+# case 0x60:
+#@@ -927,7 +927,7 @@ msp430_decode_opcode (unsigned long pc,
+# msp430->size = w ? 16 : 20;
+# msp430->ofs_430x = 1;
+# F_0NZC;
+#-
+#+
+# }
+# break;
+# case 0x60:
+#@@ -1617,20 +1617,20 @@ msp430_decode_opcode (unsigned long pc,
+# }
+# SYNTAX("%S%b %1");
+# #line 394 "msp430-decode.opc"
+#-
+#+
+# ID (sopc_to_id (so,c)); ASX (dreg, ad, srxt_bits); ABW (al_bit, b);
+#-
+#+
+# if (ad == 0)
+# REPZC (srxt_bits, dsxt_bits);
+#-
+#+
+# /* The helper functions encode for source, but it's
+# both source and dest, with a few documented exceptions. */
+# msp430->op[0] = msp430->op[1];
+#-
+#+
+# /* RETI ignores the operand. */
+# if (msp430->id == MSO_reti)
+# msp430->syntax = "%S";
+#-
+#+
+# switch (msp430->id)
+# {
+# case MSO_rrc: F_VNZC; break;
+#@@ -1642,7 +1642,7 @@ msp430_decode_opcode (unsigned long pc,
+# case MSO_reti: F_VNZC; break;
+# default: break;
+# }
+#-
+#+
+# /* 20xx 0010 0000 ---- ----
+# 3cxx 0011 1100 ---- ----
+# 001j mp-- ---- ----. */
+#@@ -1686,7 +1686,7 @@ msp430_decode_opcode (unsigned long pc,
+# ID (MSO_reti);
+# msp430->size = 20;
+# msp430->ofs_430x = 1;
+#-
+#+
+# }
+# break;
+# case 0x01:
+#@@ -1917,7 +1917,7 @@ msp430_decode_opcode (unsigned long pc,
+# ID (MSO_call); AS (dstr, as);
+# msp430->size = 20;
+# msp430->ofs_430x = 1;
+#-
+#+
+# }
+# break;
+# case 0x80:
+#@@ -1952,7 +1952,7 @@ msp430_decode_opcode (unsigned long pc,
+# ID (MSO_call); SA (IMMU(2) | (extb << 16));
+# msp430->size = 20;
+# msp430->ofs_430x = 1;
+#-
+#+
+# }
+# break;
+# case 0x90:
+#@@ -1990,7 +1990,7 @@ msp430_decode_opcode (unsigned long pc,
+# ID (MSO_call); SA (pc + raddr + msp430->n_bytes);
+# msp430->size = 20;
+# msp430->ofs_430x = 1;
+#-
+#+
+# }
+# break;
+# case 0xb0:
+#@@ -2025,7 +2025,7 @@ msp430_decode_opcode (unsigned long pc,
+# ID (MSO_call); SC (IMMU(2) | (extb << 16));
+# msp430->size = 20;
+# msp430->ofs_430x = 1;
+#-
+#+
+# }
+# break;
+# }
+#@@ -2059,7 +2059,7 @@ msp430_decode_opcode (unsigned long pc,
+# msp430->size = w ? 16 : 20;
+# msp430->repeats = bits;
+# msp430->ofs_430x = 1;
+#-
+#+
+# }
+# break;
+# }
+#@@ -2102,7 +2102,7 @@ msp430_decode_opcode (unsigned long pc,
+# msp430->size = w ? 16 : 20;
+# msp430->repeats = bits;
+# msp430->ofs_430x = 1;
+#-
+#+
+# }
+# break;
+# }
+#@@ -2144,25 +2144,25 @@ msp430_decode_opcode (unsigned long pc,
+# }
+# SYNTAX("430x");
+# #line 350 "msp430-decode.opc"
+#-
+#+
+# al_bit = l;
+# srxt_bits = srx * 2 + t;
+# dsxt_bits = dsxt;
+# op = op_buf + lds.op_ptr;
+# msp430->ofs_430x = 1;
+# goto post_extension_word;
+#-
+#+
+# /* double-op insns:
+# opcode:4 sreg:4 Ad:1 BW:1 As:2 Dreg:4
+#-
+#+
+# single-op insn:
+# opcode:9 BW:1 Ad:2 DSreg:4
+#-
+#+
+# jumps:
+# opcode:3 Cond:3 pcrel:10. */
+#-
+#+
+# /* Double-Operand "opcode" fields. */
+#-
+#+
+# }
+# break;
+# default: UNSUPPORTED(); break;
+#@@ -2263,7 +2263,7 @@ msp430_decode_opcode (unsigned long pc,
+# }
+# SYNTAX("%J %1");
+# #line 424 "msp430-decode.opc"
+#-
+#+
+# raddr = (aa << 9) | (addrlsbs << 1);
+# if (raddr & 0x400)
+# raddr = raddr - 0x800;
+#@@ -2273,9 +2273,9 @@ msp430_decode_opcode (unsigned long pc,
+# data at that address. */
+# ID (MSO_jmp); SC (pc + raddr + msp430->n_bytes);
+# msp430->cond = jmp;
+#-
+#+
+# /* Extended instructions. */
+#-
+#+
+# }
+# break;
+# }
+#@@ -2593,11 +2593,11 @@ msp430_decode_opcode (unsigned long pc,
+# }
+# SYNTAX("%D%b %1,%0");
+# #line 371 "msp430-decode.opc"
+#-
+#+
+# ID (dopc_to_id (dopc)); ASX (sreg, as, srxt_bits); ADX (dreg, a, dsxt_bits); ABW (al_bit, b);
+# if (a == 0 && as == 0)
+# REPZC (srxt_bits, dsxt_bits);
+#-
+#+
+# switch (msp430->id)
+# {
+# case MSO_mov: F_____; break;
+#@@ -2614,7 +2614,7 @@ msp430_decode_opcode (unsigned long pc,
+# case MSO_and: F_0NZC; break;
+# default: break;
+# }
+#-
+#+
+# }
+# break;
+# }
+#--- a/opcodes/msp430-dis.c
+#+++ b/opcodes/msp430-dis.c
+#@@ -2,7 +2,7 @@
+# Copyright (C) 2002-2015 Free Software Foundation, Inc.
+#
+# Contributed by Dmitry Diky <diwil@mail.ru>
+#-
+#+
+# This file is part of the GNU opcodes library.
+#
+# This library is free software; you can redistribute it and/or modify
+#@@ -397,7 +397,7 @@ msp430_doubleoperand (disassemble_info *info,
+# Rm Register,
+# x(Rm) Indexed,
+# 0xXXXX Relative,
+#- &0xXXXX Absolute
+#+ &0xXXXX Absolute
+# emulated_ins dst
+# basic_ins dst, dst. */
+#
+#@@ -936,7 +936,7 @@ print_insn_msp430 (bfd_vma addr, disassemble_info *info)
+# sprintf (comm1, "20-bit words");
+# bc =".a";
+# }
+#-
+#+
+# cycles = 2; /*FIXME*/
+# cmd_len = 2;
+# break;
+#@@ -984,7 +984,7 @@ print_insn_msp430 (bfd_vma addr, disassemble_info *info)
+# if (strcmp (opcode->name, "bra") != 0)
+# sprintf (op2, "r%d", reg);
+# break;
+#-
+#+
+# case 1: /* MOVA @Rsrc+, Rdst */
+# cmd_len = 2;
+# if (strcmp (opcode->name, "reta") != 0)
+#@@ -994,7 +994,7 @@ print_insn_msp430 (bfd_vma addr, disassemble_info *info)
+# sprintf (op2, "r%d", reg);
+# }
+# break;
+#-
+#+
+# case 2: /* MOVA &abs20, Rdst */
+# cmd_len = 4;
+# n <<= 16;
+#@@ -1005,7 +1005,7 @@ print_insn_msp430 (bfd_vma addr, disassemble_info *info)
+# if (strcmp (opcode->name, "bra") != 0)
+# sprintf (op2, "r%d", reg);
+# break;
+#-
+#+
+# case 3: /* MOVA x(Rsrc), Rdst */
+# cmd_len = 4;
+# if (strcmp (opcode->name, "bra") != 0)
+#@@ -1051,7 +1051,7 @@ print_insn_msp430 (bfd_vma addr, disassemble_info *info)
+# sprintf (comm2, "0x%05x", n);
+# }
+# break;
+#-
+#+
+# case 8: /* MOVA #imm20, Rdst */
+# cmd_len = 4;
+# n <<= 16;
+#@@ -1064,7 +1064,7 @@ print_insn_msp430 (bfd_vma addr, disassemble_info *info)
+# if (strcmp (opcode->name, "bra") != 0)
+# sprintf (op2, "r%d", reg);
+# break;
+#-
+#+
+# case 12: /* MOVA Rsrc, Rdst */
+# cmd_len = 2;
+# sprintf (op1, "r%d", n);
+#@@ -1110,7 +1110,7 @@ print_insn_msp430 (bfd_vma addr, disassemble_info *info)
+# sprintf (comm2, _("Reserved use of A/L and B/W bits detected"));
+# }
+# }
+#-
+#+
+# break;
+# case 1:
+# cmd_len +=
+--- a/opcodes/mt-asm.c
++++ b/opcodes/mt-asm.c
+@@ -52,7 +52,7 @@ static const char * parse_insn_normal
+ /* Range checking for signed numbers. Returns 0 if acceptable
+ and 1 if the value is out of bounds for a signed quantity. */
+
+-static int
++static int
+ signed_out_of_bounds (long val)
+ {
+ if ((val < -32768) || (val > 32767))
+@@ -72,7 +72,7 @@ parse_loopsize (CGEN_CPU_DESC cd,
+ enum cgen_parse_operand_result result_type;
+ bfd_vma value;
+
+- /* Is it a control transfer instructions? */
++ /* Is it a control transfer instructions? */
+ if (opindex == (CGEN_OPERAND_TYPE) MT_OPERAND_LOOPSIZE)
+ {
+ code = BFD_RELOC_MT_PCINSN8;
+@@ -97,7 +97,7 @@ parse_imm16 (CGEN_CPU_DESC cd,
+ bfd_reloc_code_real_type code = BFD_RELOC_NONE;
+ bfd_vma value;
+
+- /* Is it a control transfer instructions? */
++ /* Is it a control transfer instructions? */
+ if (opindex == (CGEN_OPERAND_TYPE) MT_OPERAND_IMM16O)
+ {
+ code = BFD_RELOC_16_PCREL;
+@@ -144,7 +144,7 @@ parse_imm16 (CGEN_CPU_DESC cd,
+ value = (value >> 16) & 0xFFFF;
+ else if (code == BFD_RELOC_LO16)
+ value = value & 0xFFFF;
+- else
++ else
+ errmsg = _("Biiiig Trouble in parse_imm16!");
+ break;
+
+@@ -173,27 +173,27 @@ parse_imm16 (CGEN_CPU_DESC cd,
+ if (parse_signed)
+ {
+ /* Parse as as signed integer. */
+-
++
+ errmsg = cgen_parse_signed_integer (cd, strp, opindex, valuep);
+
+- if (errmsg == NULL)
++ if (errmsg == NULL)
+ {
+ #if 0
+ /* Manual range checking is needed for the signed case. */
+ if (*valuep & 0x8000)
+ value = 0xffff0000 | *valuep;
+- else
++ else
+ value = *valuep;
+
+ if (signed_out_of_bounds (value))
+ errmsg = _("Operand out of range. Must be between -32768 and 32767.");
+ /* Truncate to 16 bits. This is necessary
+ because cgen will have sign extended *valuep. */
+- *valuep &= 0xFFFF;
++ *valuep &= 0xFFFF;
+ #endif
+ }
+ }
+- else
++ else
+ {
+ /* MT_OPERAND_IMM16Z. Parse as an unsigned integer. */
+ errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, (unsigned long *) valuep);
+@@ -598,7 +598,7 @@ mt_cgen_parse_operand (CGEN_CPU_DESC cd,
+ return errmsg;
+ }
+
+-cgen_parse_fn * const mt_cgen_parse_handlers[] =
++cgen_parse_fn * const mt_cgen_parse_handlers[] =
+ {
+ parse_insn_normal,
+ };
+@@ -628,9 +628,9 @@ CGEN_ASM_INIT_HOOK
+
+ Returns NULL for success, an error message for failure. */
+
+-char *
++char *
+ mt_cgen_build_insn_regex (CGEN_INSN *insn)
+-{
++{
+ CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
+ const char *mnem = CGEN_INSN_MNEMONIC (insn);
+ char rxbuf[CGEN_MAX_RX_ELEMENTS];
+@@ -669,18 +669,18 @@ mt_cgen_build_insn_regex (CGEN_INSN *insn)
+ /* Copy any remaining literals from the syntax string into the rx. */
+ for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn)
+ {
+- if (CGEN_SYNTAX_CHAR_P (* syn))
++ if (CGEN_SYNTAX_CHAR_P (* syn))
+ {
+ char c = CGEN_SYNTAX_CHAR (* syn);
+
+- switch (c)
++ switch (c)
+ {
+ /* Escape any regex metacharacters in the syntax. */
+- case '.': case '[': case '\\':
+- case '*': case '^': case '$':
++ case '.': case '[': case '\\':
++ case '*': case '^': case '$':
+
+ #ifdef CGEN_ESCAPE_EXTENDED_REGEX
+- case '?': case '{': case '}':
++ case '?': case '{': case '}':
+ case '(': case ')': case '*':
+ case '|': case '+': case ']':
+ #endif
+@@ -710,20 +710,20 @@ mt_cgen_build_insn_regex (CGEN_INSN *insn)
+ }
+
+ /* Trailing whitespace ok. */
+- * rx++ = '[';
+- * rx++ = ' ';
+- * rx++ = '\t';
+- * rx++ = ']';
+- * rx++ = '*';
++ * rx++ = '[';
++ * rx++ = ' ';
++ * rx++ = '\t';
++ * rx++ = ']';
++ * rx++ = '*';
+
+ /* But anchor it after that. */
+- * rx++ = '$';
++ * rx++ = '$';
+ * rx = '\0';
+
+ CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t));
+ reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB);
+
+- if (reg_err == 0)
++ if (reg_err == 0)
+ return NULL;
+ else
+ {
+@@ -922,7 +922,7 @@ mt_cgen_assemble_insn (CGEN_CPU_DESC cd,
+ const CGEN_INSN *insn = ilist->insn;
+ recognized_mnemonic = 1;
+
+-#ifdef CGEN_VALIDATE_INSN_SUPPORTED
++#ifdef CGEN_VALIDATE_INSN_SUPPORTED
+ /* Not usually needed as unsupported opcodes
+ shouldn't be in the hash lists. */
+ /* Is this insn supported by the selected cpu? */
+@@ -982,7 +982,7 @@ mt_cgen_assemble_insn (CGEN_CPU_DESC cd,
+ if (strlen (start) > 50)
+ /* xgettext:c-format */
+ sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start);
+- else
++ else
+ /* xgettext:c-format */
+ sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start);
+ }
+@@ -991,11 +991,11 @@ mt_cgen_assemble_insn (CGEN_CPU_DESC cd,
+ if (strlen (start) > 50)
+ /* xgettext:c-format */
+ sprintf (errbuf, _("bad instruction `%.50s...'"), start);
+- else
++ else
+ /* xgettext:c-format */
+ sprintf (errbuf, _("bad instruction `%.50s'"), start);
+ }
+-
++
+ *errmsg = errbuf;
+ return NULL;
+ }
+--- a/opcodes/mt-desc.c
++++ b/opcodes/mt-desc.c
+@@ -310,223 +310,223 @@ const CGEN_OPERAND mt_cgen_operand_table[] =
+ {
+ /* pc: program counter */
+ { "pc", MT_OPERAND_PC, HW_H_PC, 0, 0,
+- { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_NIL] } },
++ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_NIL] } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* frsr1: register */
+ { "frsr1", MT_OPERAND_FRSR1, HW_H_SPR, 23, 4,
+- { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_SR1] } },
++ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_SR1] } },
+ { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
+ /* frsr2: register */
+ { "frsr2", MT_OPERAND_FRSR2, HW_H_SPR, 19, 4,
+- { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_SR2] } },
++ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_SR2] } },
+ { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
+ /* frdr: register */
+ { "frdr", MT_OPERAND_FRDR, HW_H_SPR, 19, 4,
+- { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_DR] } },
++ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_DR] } },
+ { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
+ /* frdrrr: register */
+ { "frdrrr", MT_OPERAND_FRDRRR, HW_H_SPR, 15, 4,
+- { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_DRRR] } },
++ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_DRRR] } },
+ { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
+ /* imm16: immediate value - sign extd */
+ { "imm16", MT_OPERAND_IMM16, HW_H_SINT, 15, 16,
+- { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_IMM16S] } },
++ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_IMM16S] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* imm16z: immediate value - zero extd */
+ { "imm16z", MT_OPERAND_IMM16Z, HW_H_UINT, 15, 16,
+- { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_IMM16U] } },
++ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_IMM16U] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* imm16o: immediate value */
+ { "imm16o", MT_OPERAND_IMM16O, HW_H_UINT, 15, 16,
+- { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_IMM16S] } },
++ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_IMM16S] } },
+ { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
+ /* rc: rc */
+ { "rc", MT_OPERAND_RC, HW_H_UINT, 15, 1,
+- { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RC] } },
++ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RC] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* rcnum: rcnum */
+ { "rcnum", MT_OPERAND_RCNUM, HW_H_UINT, 14, 3,
+- { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RCNUM] } },
++ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RCNUM] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* contnum: context number */
+ { "contnum", MT_OPERAND_CONTNUM, HW_H_UINT, 8, 9,
+- { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CONTNUM] } },
++ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CONTNUM] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* rbbc: omega network configuration */
+ { "rbbc", MT_OPERAND_RBBC, HW_H_UINT, 25, 2,
+- { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RBBC] } },
++ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RBBC] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* colnum: column number */
+ { "colnum", MT_OPERAND_COLNUM, HW_H_UINT, 18, 3,
+- { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_COLNUM] } },
++ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_COLNUM] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* rownum: row number */
+ { "rownum", MT_OPERAND_ROWNUM, HW_H_UINT, 14, 3,
+- { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_ROWNUM] } },
++ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_ROWNUM] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* rownum1: row number */
+ { "rownum1", MT_OPERAND_ROWNUM1, HW_H_UINT, 12, 3,
+- { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_ROWNUM1] } },
++ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_ROWNUM1] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* rownum2: row number */
+ { "rownum2", MT_OPERAND_ROWNUM2, HW_H_UINT, 9, 3,
+- { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_ROWNUM2] } },
++ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_ROWNUM2] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* rc1: rc1 */
+ { "rc1", MT_OPERAND_RC1, HW_H_UINT, 11, 1,
+- { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RC1] } },
++ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RC1] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* rc2: rc2 */
+ { "rc2", MT_OPERAND_RC2, HW_H_UINT, 6, 1,
+- { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RC2] } },
++ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RC2] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* cbrb: data-bus orientation */
+ { "cbrb", MT_OPERAND_CBRB, HW_H_UINT, 10, 1,
+- { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CBRB] } },
++ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CBRB] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* cell: cell */
+ { "cell", MT_OPERAND_CELL, HW_H_UINT, 9, 3,
+- { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CELL] } },
++ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CELL] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* dup: dup */
+ { "dup", MT_OPERAND_DUP, HW_H_UINT, 6, 1,
+- { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_DUP] } },
++ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_DUP] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* ctxdisp: context displacement */
+ { "ctxdisp", MT_OPERAND_CTXDISP, HW_H_UINT, 5, 6,
+- { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CTXDISP] } },
++ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CTXDISP] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* fbdisp: frame buffer displacement */
+ { "fbdisp", MT_OPERAND_FBDISP, HW_H_UINT, 15, 6,
+- { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_FBDISP] } },
++ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_FBDISP] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* type: type */
+ { "type", MT_OPERAND_TYPE, HW_H_UINT, 21, 2,
+- { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_TYPE] } },
++ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_TYPE] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* mask: mask */
+ { "mask", MT_OPERAND_MASK, HW_H_UINT, 25, 16,
+- { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_MASK] } },
++ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_MASK] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* bankaddr: bank address */
+ { "bankaddr", MT_OPERAND_BANKADDR, HW_H_UINT, 25, 13,
+- { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BANKADDR] } },
++ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BANKADDR] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* incamt: increment amount */
+ { "incamt", MT_OPERAND_INCAMT, HW_H_UINT, 19, 8,
+- { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_INCAMT] } },
++ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_INCAMT] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* xmode: xmode */
+ { "xmode", MT_OPERAND_XMODE, HW_H_UINT, 23, 1,
+- { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_XMODE] } },
++ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_XMODE] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* mask1: mask1 */
+ { "mask1", MT_OPERAND_MASK1, HW_H_UINT, 22, 3,
+- { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_MASK1] } },
++ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_MASK1] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* ball: b_all */
+ { "ball", MT_OPERAND_BALL, HW_H_UINT, 19, 1,
+- { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BALL] } },
++ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BALL] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* brc: b_r_c */
+ { "brc", MT_OPERAND_BRC, HW_H_UINT, 18, 3,
+- { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BRC] } },
++ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BRC] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* rda: rd */
+ { "rda", MT_OPERAND_RDA, HW_H_UINT, 25, 1,
+- { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RDA] } },
++ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RDA] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* wr: wr */
+ { "wr", MT_OPERAND_WR, HW_H_UINT, 24, 1,
+- { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_WR] } },
++ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_WR] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* ball2: b_all2 */
+ { "ball2", MT_OPERAND_BALL2, HW_H_UINT, 15, 1,
+- { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BALL2] } },
++ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BALL2] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* brc2: b_r_c2 */
+ { "brc2", MT_OPERAND_BRC2, HW_H_UINT, 14, 3,
+- { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BRC2] } },
++ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BRC2] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* perm: perm */
+ { "perm", MT_OPERAND_PERM, HW_H_UINT, 25, 2,
+- { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_PERM] } },
++ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_PERM] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* a23: a23 */
+ { "a23", MT_OPERAND_A23, HW_H_UINT, 23, 1,
+- { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_A23] } },
++ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_A23] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* cr: c-r */
+ { "cr", MT_OPERAND_CR, HW_H_UINT, 22, 3,
+- { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CR] } },
++ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CR] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* cbs: cbs */
+ { "cbs", MT_OPERAND_CBS, HW_H_UINT, 19, 2,
+- { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CBS] } },
++ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CBS] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* incr: incr */
+ { "incr", MT_OPERAND_INCR, HW_H_UINT, 17, 6,
+- { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_INCR] } },
++ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_INCR] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* length: length */
+ { "length", MT_OPERAND_LENGTH, HW_H_UINT, 15, 3,
+- { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_LENGTH] } },
++ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_LENGTH] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* cbx: cbx */
+ { "cbx", MT_OPERAND_CBX, HW_H_UINT, 14, 3,
+- { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CBX] } },
++ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CBX] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* ccb: ccb */
+ { "ccb", MT_OPERAND_CCB, HW_H_UINT, 11, 1,
+- { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CCB] } },
++ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CCB] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* cdb: cdb */
+ { "cdb", MT_OPERAND_CDB, HW_H_UINT, 10, 1,
+- { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CDB] } },
++ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CDB] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* mode: mode */
+ { "mode", MT_OPERAND_MODE, HW_H_UINT, 25, 2,
+- { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_MODE] } },
++ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_MODE] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* id: i/d */
+ { "id", MT_OPERAND_ID, HW_H_UINT, 14, 1,
+- { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_ID] } },
++ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_ID] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* size: size */
+ { "size", MT_OPERAND_SIZE, HW_H_UINT, 13, 14,
+- { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_SIZE] } },
++ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_SIZE] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* fbincr: fb incr */
+ { "fbincr", MT_OPERAND_FBINCR, HW_H_UINT, 23, 4,
+- { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_FBINCR] } },
++ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_FBINCR] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* loopsize: immediate value */
+ { "loopsize", MT_OPERAND_LOOPSIZE, HW_H_UINT, 7, 8,
+- { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_LOOPO] } },
++ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_LOOPO] } },
+ { 0|A(PCREL_ADDR), { { { (1<<MACH_MS2), 0 } } } } },
+ /* imm16l: immediate value */
+ { "imm16l", MT_OPERAND_IMM16L, HW_H_UINT, 23, 16,
+- { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_IMM16L] } },
++ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_IMM16L] } },
+ { 0, { { { (1<<MACH_MS2), 0 } } } } },
+ /* rc3: rc3 */
+ { "rc3", MT_OPERAND_RC3, HW_H_UINT, 7, 1,
+- { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RC3] } },
++ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RC3] } },
+ { 0, { { { (1<<MACH_MS2), 0 } } } } },
+ /* cb1sel: cb1sel */
+ { "cb1sel", MT_OPERAND_CB1SEL, HW_H_UINT, 25, 3,
+- { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CB1SEL] } },
++ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CB1SEL] } },
+ { 0, { { { (1<<MACH_MS2), 0 } } } } },
+ /* cb2sel: cb2sel */
+ { "cb2sel", MT_OPERAND_CB2SEL, HW_H_UINT, 22, 3,
+- { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CB2SEL] } },
++ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CB2SEL] } },
+ { 0, { { { (1<<MACH_MS2), 0 } } } } },
+ /* cb1incr: cb1incr */
+ { "cb1incr", MT_OPERAND_CB1INCR, HW_H_SINT, 19, 6,
+- { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CB1INCR] } },
++ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CB1INCR] } },
+ { 0|A(SIGNED), { { { (1<<MACH_MS2), 0 } } } } },
+ /* cb2incr: cb2incr */
+ { "cb2incr", MT_OPERAND_CB2INCR, HW_H_SINT, 13, 6,
+- { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CB2INCR] } },
++ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CB2INCR] } },
+ { 0|A(SIGNED), { { { (1<<MACH_MS2), 0 } } } } },
+ /* sentinel */
+ { 0, 0, 0, 0, 0,
+@@ -1249,7 +1249,7 @@ mt_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
+
+ /* Default to not allowing signed overflow. */
+ cd->signed_overflow_ok_p = 0;
+-
++
+ return (CGEN_CPU_DESC) cd;
+ }
+
+@@ -1289,7 +1289,7 @@ mt_cgen_cpu_close (CGEN_CPU_DESC cd)
+ for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
+ if (CGEN_INSN_RX (insns))
+ regfree (CGEN_INSN_RX (insns));
+- }
++ }
+
+ if (cd->macro_insn_table.init_entries)
+ free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
+--- a/opcodes/mt-dis.c
++++ b/opcodes/mt-dis.c
+@@ -292,7 +292,7 @@ mt_cgen_print_operand (CGEN_CPU_DESC cd,
+ }
+ }
+
+-cgen_print_fn * const mt_cgen_print_handlers[] =
++cgen_print_fn * const mt_cgen_print_handlers[] =
+ {
+ print_insn_normal,
+ };
+@@ -482,7 +482,7 @@ print_insn (CGEN_CPU_DESC cd,
+ int length;
+ unsigned long insn_value_cropped;
+
+-#ifdef CGEN_VALIDATE_INSN_SUPPORTED
++#ifdef CGEN_VALIDATE_INSN_SUPPORTED
+ /* Not needed as insn shouldn't be in hash lists if not supported. */
+ /* Supported by this cpu? */
+ if (! mt_cgen_insn_supported (cd, insn))
+@@ -500,7 +500,7 @@ print_insn (CGEN_CPU_DESC cd,
+ relevant part from the buffer. */
+ if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
+ (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
+- insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
++ insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
+ info->endian == BFD_ENDIAN_BIG);
+ else
+ insn_value_cropped = insn_value;
+@@ -619,7 +619,7 @@ print_insn_mt (bfd_vma pc, disassemble_info *info)
+ arch = info->arch;
+ if (arch == bfd_arch_unknown)
+ arch = CGEN_BFD_ARCH;
+-
++
+ /* There's no standard way to compute the machine or isa number
+ so we leave it to the target. */
+ #ifdef CGEN_COMPUTE_MACH
+@@ -660,7 +660,7 @@ print_insn_mt (bfd_vma pc, disassemble_info *info)
+ break;
+ }
+ }
+- }
++ }
+
+ /* If we haven't initialized yet, initialize the opcode table. */
+ if (! cd)
+--- a/opcodes/mt-ibld.c
++++ b/opcodes/mt-ibld.c
+@@ -154,7 +154,7 @@ insert_normal (CGEN_CPU_DESC cd,
+ {
+ long minval = - (1L << (length - 1));
+ unsigned long maxval = mask;
+-
++
+ if ((value > 0 && (unsigned long) value > maxval)
+ || value < minval)
+ {
+@@ -192,7 +192,7 @@ insert_normal (CGEN_CPU_DESC cd,
+ {
+ long minval = - (1L << (length - 1));
+ long maxval = (1L << (length - 1)) - 1;
+-
++
+ if (value < minval || value > maxval)
+ {
+ sprintf
+@@ -970,12 +970,12 @@ mt_cgen_extract_operand (CGEN_CPU_DESC cd,
+ return length;
+ }
+
+-cgen_insert_fn * const mt_cgen_insert_handlers[] =
++cgen_insert_fn * const mt_cgen_insert_handlers[] =
+ {
+ insert_insn_normal,
+ };
+
+-cgen_extract_fn * const mt_cgen_extract_handlers[] =
++cgen_extract_fn * const mt_cgen_extract_handlers[] =
+ {
+ extract_insn_normal,
+ };
+--- a/opcodes/mt-opc.c
++++ b/opcodes/mt-opc.c
+@@ -43,7 +43,7 @@ mt_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn)
+ /* No mach attribute? Assume it's supported for all machs. */
+ if (machs == 0)
+ return 1;
+-
++
+ return ((machs & cd->machs) != 0);
+ }
+
+#--- a/opcodes/nios2-dis.c
+#+++ b/opcodes/nios2-dis.c
+#@@ -96,7 +96,7 @@ nios2_r2_disassembler_state = {
+# NULL,
+# 0
+# };
+#-
+#+
+# /* Function to initialize the opcode hash table. */
+# static void
+# nios2_init_opcode_hash (nios2_disassembler_state *state)
+#@@ -218,7 +218,7 @@ static struct nios2_reg *
+# nios2_coprocessor_regs (void)
+# {
+# static struct nios2_reg *cached = NULL;
+#-
+#+
+# if (!cached)
+# {
+# int i;
+#@@ -238,7 +238,7 @@ static struct nios2_reg *
+# nios2_control_regs (void)
+# {
+# static struct nios2_reg *cached = NULL;
+#-
+#+
+# if (!cached)
+# {
+# int i;
+#@@ -859,7 +859,7 @@ nios2_print_insn_arg (const char *argptr,
+# reglist = i << 2;
+# dir = GET_IW_F1X4L17_REGMASK (opcode) ? 1 : -1;
+# break;
+#-
+#+
+# case iw_L5I4X1_type:
+# /* Encoding for push.n/pop.n. */
+# reglist |= (1 << 31);
+#@@ -903,7 +903,7 @@ nios2_print_insn_arg (const char *argptr,
+# (*info->fprintf_func) (info->stream, "--");
+#
+# i = GET_IW_F1X4I12_A (opcode);
+#- (*info->fprintf_func) (info->stream, "(%s)",
+#+ (*info->fprintf_func) (info->stream, "(%s)",
+# nios2_builtin_regs[i].name);
+#
+# if (GET_IW_F1X4L17_ID (opcode))
+--- a/opcodes/ns32k-dis.c
++++ b/opcodes/ns32k-dis.c
+@@ -413,7 +413,7 @@ invalid_float (bfd_byte *p, int len)
+ #else
+ /* Assumes the bytes have been swapped to local order. */
+ typedef union
+-{
++{
+ double d;
+ float f;
+ struct { unsigned m:23, e:8, :1;} sf;
+@@ -618,7 +618,7 @@ print_insn_arg (int d,
+ int bit_index;
+ static const char *ind = "bwdq";
+ char *off;
+-
++
+ /* Scaled index basemode[R0 -- R7:B,W,D,Q]. */
+ bit_index = bit_extract (buffer, index_offset - 8, 3);
+ print_insn_arg (d, index_offset, aoffsetp, buffer, addr,
+@@ -794,7 +794,7 @@ print_insn_ns32k (bfd_vma memaddr, disassemble_info *info)
+
+ /* 0 for operand A, 1 for operand B, greater for other args. */
+ int whicharg = 0;
+-
++
+ (*dis_info->fprintf_func)(dis_info->stream, "\t");
+
+ maxarg = 0;
+--- a/opcodes/opintl.h
++++ b/opcodes/opintl.h
+@@ -23,7 +23,7 @@
+ #ifdef ENABLE_NLS
+ # include <libintl.h>
+ /* Note the use of dgetext() and PACKAGE here, rather than gettext().
+-
++
+ This is because the code in this directory is used to build a library which
+ will be linked with code in other directories to form programs. We want to
+ maintain a seperate translation file for this directory however, rather
+#--- a/opcodes/or1k-asm.c
+#+++ b/opcodes/or1k-asm.c
+#@@ -506,7 +506,7 @@ or1k_cgen_parse_operand (CGEN_CPU_DESC cd,
+# return errmsg;
+# }
+#
+#-cgen_parse_fn * const or1k_cgen_parse_handlers[] =
+#+cgen_parse_fn * const or1k_cgen_parse_handlers[] =
+# {
+# parse_insn_normal,
+# };
+#@@ -536,9 +536,9 @@ CGEN_ASM_INIT_HOOK
+#
+# Returns NULL for success, an error message for failure. */
+#
+#-char *
+#+char *
+# or1k_cgen_build_insn_regex (CGEN_INSN *insn)
+#-{
+#+{
+# CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
+# const char *mnem = CGEN_INSN_MNEMONIC (insn);
+# char rxbuf[CGEN_MAX_RX_ELEMENTS];
+#@@ -577,18 +577,18 @@ or1k_cgen_build_insn_regex (CGEN_INSN *insn)
+# /* Copy any remaining literals from the syntax string into the rx. */
+# for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn)
+# {
+#- if (CGEN_SYNTAX_CHAR_P (* syn))
+#+ if (CGEN_SYNTAX_CHAR_P (* syn))
+# {
+# char c = CGEN_SYNTAX_CHAR (* syn);
+#
+#- switch (c)
+#+ switch (c)
+# {
+# /* Escape any regex metacharacters in the syntax. */
+#- case '.': case '[': case '\\':
+#- case '*': case '^': case '$':
+#+ case '.': case '[': case '\\':
+#+ case '*': case '^': case '$':
+#
+# #ifdef CGEN_ESCAPE_EXTENDED_REGEX
+#- case '?': case '{': case '}':
+#+ case '?': case '{': case '}':
+# case '(': case ')': case '*':
+# case '|': case '+': case ']':
+# #endif
+#@@ -618,20 +618,20 @@ or1k_cgen_build_insn_regex (CGEN_INSN *insn)
+# }
+#
+# /* Trailing whitespace ok. */
+#- * rx++ = '[';
+#- * rx++ = ' ';
+#- * rx++ = '\t';
+#- * rx++ = ']';
+#- * rx++ = '*';
+#+ * rx++ = '[';
+#+ * rx++ = ' ';
+#+ * rx++ = '\t';
+#+ * rx++ = ']';
+#+ * rx++ = '*';
+#
+# /* But anchor it after that. */
+#- * rx++ = '$';
+#+ * rx++ = '$';
+# * rx = '\0';
+#
+# CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t));
+# reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB);
+#
+#- if (reg_err == 0)
+#+ if (reg_err == 0)
+# return NULL;
+# else
+# {
+#@@ -830,7 +830,7 @@ or1k_cgen_assemble_insn (CGEN_CPU_DESC cd,
+# const CGEN_INSN *insn = ilist->insn;
+# recognized_mnemonic = 1;
+#
+#-#ifdef CGEN_VALIDATE_INSN_SUPPORTED
+#+#ifdef CGEN_VALIDATE_INSN_SUPPORTED
+# /* Not usually needed as unsupported opcodes
+# shouldn't be in the hash lists. */
+# /* Is this insn supported by the selected cpu? */
+#@@ -890,7 +890,7 @@ or1k_cgen_assemble_insn (CGEN_CPU_DESC cd,
+# if (strlen (start) > 50)
+# /* xgettext:c-format */
+# sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start);
+#- else
+#+ else
+# /* xgettext:c-format */
+# sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start);
+# }
+#@@ -899,11 +899,11 @@ or1k_cgen_assemble_insn (CGEN_CPU_DESC cd,
+# if (strlen (start) > 50)
+# /* xgettext:c-format */
+# sprintf (errbuf, _("bad instruction `%.50s...'"), start);
+#- else
+#+ else
+# /* xgettext:c-format */
+# sprintf (errbuf, _("bad instruction `%.50s'"), start);
+# }
+#-
+#+
+# *errmsg = errbuf;
+# return NULL;
+# }
+#--- a/opcodes/or1k-desc.c
+#+++ b/opcodes/or1k-desc.c
+#@@ -1008,127 +1008,127 @@ const CGEN_OPERAND or1k_cgen_operand_table[] =
+# {
+# /* pc: program counter */
+# { "pc", OR1K_OPERAND_PC, HW_H_PC, 0, 0,
+#- { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_NIL] } },
+#+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_NIL] } },
+# { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+# /* sys-sr: supervision register */
+# { "sys-sr", OR1K_OPERAND_SYS_SR, HW_H_SYS_SR, 0, 0,
+#- { 0, { (const PTR) 0 } },
+#+ { 0, { (const PTR) 0 } },
+# { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
+# /* sys-esr0: exception supervision register 0 */
+# { "sys-esr0", OR1K_OPERAND_SYS_ESR0, HW_H_SYS_ESR0, 0, 0,
+#- { 0, { (const PTR) 0 } },
+#+ { 0, { (const PTR) 0 } },
+# { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
+# /* sys-epcr0: exception PC register 0 */
+# { "sys-epcr0", OR1K_OPERAND_SYS_EPCR0, HW_H_SYS_EPCR0, 0, 0,
+#- { 0, { (const PTR) 0 } },
+#+ { 0, { (const PTR) 0 } },
+# { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
+# /* sys-sr-lee: SR little endian enable bit */
+# { "sys-sr-lee", OR1K_OPERAND_SYS_SR_LEE, HW_H_SYS_SR_LEE, 0, 0,
+#- { 0, { (const PTR) 0 } },
+#+ { 0, { (const PTR) 0 } },
+# { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
+# /* sys-sr-f: SR flag bit */
+# { "sys-sr-f", OR1K_OPERAND_SYS_SR_F, HW_H_SYS_SR_F, 0, 0,
+#- { 0, { (const PTR) 0 } },
+#+ { 0, { (const PTR) 0 } },
+# { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
+# /* sys-sr-cy: SR carry bit */
+# { "sys-sr-cy", OR1K_OPERAND_SYS_SR_CY, HW_H_SYS_SR_CY, 0, 0,
+#- { 0, { (const PTR) 0 } },
+#+ { 0, { (const PTR) 0 } },
+# { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
+# /* sys-sr-ov: SR overflow bit */
+# { "sys-sr-ov", OR1K_OPERAND_SYS_SR_OV, HW_H_SYS_SR_OV, 0, 0,
+#- { 0, { (const PTR) 0 } },
+#+ { 0, { (const PTR) 0 } },
+# { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
+# /* sys-sr-ove: SR overflow exception enable bit */
+# { "sys-sr-ove", OR1K_OPERAND_SYS_SR_OVE, HW_H_SYS_SR_OVE, 0, 0,
+#- { 0, { (const PTR) 0 } },
+#+ { 0, { (const PTR) 0 } },
+# { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
+# /* sys-cpucfgr-ob64s: CPUCFGR ORBIS64 supported bit */
+# { "sys-cpucfgr-ob64s", OR1K_OPERAND_SYS_CPUCFGR_OB64S, HW_H_SYS_CPUCFGR_OB64S, 0, 0,
+#- { 0, { (const PTR) 0 } },
+#+ { 0, { (const PTR) 0 } },
+# { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
+# /* sys-cpucfgr-nd: CPUCFGR no delay bit */
+# { "sys-cpucfgr-nd", OR1K_OPERAND_SYS_CPUCFGR_ND, HW_H_SYS_CPUCFGR_ND, 0, 0,
+#- { 0, { (const PTR) 0 } },
+#+ { 0, { (const PTR) 0 } },
+# { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
+# /* sys-fpcsr-rm: floating point round mode */
+# { "sys-fpcsr-rm", OR1K_OPERAND_SYS_FPCSR_RM, HW_H_SYS_FPCSR_RM, 0, 0,
+#- { 0, { (const PTR) 0 } },
+#+ { 0, { (const PTR) 0 } },
+# { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
+# /* mac-machi: MAC HI result register */
+# { "mac-machi", OR1K_OPERAND_MAC_MACHI, HW_H_MAC_MACHI, 0, 0,
+#- { 0, { (const PTR) 0 } },
+#+ { 0, { (const PTR) 0 } },
+# { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
+# /* mac-maclo: MAC LO result register */
+# { "mac-maclo", OR1K_OPERAND_MAC_MACLO, HW_H_MAC_MACLO, 0, 0,
+#- { 0, { (const PTR) 0 } },
+#+ { 0, { (const PTR) 0 } },
+# { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
+# /* atomic-reserve: atomic reserve flag */
+# { "atomic-reserve", OR1K_OPERAND_ATOMIC_RESERVE, HW_H_ATOMIC_RESERVE, 0, 0,
+#- { 0, { (const PTR) 0 } },
+#+ { 0, { (const PTR) 0 } },
+# { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
+# /* atomic-address: atomic address */
+# { "atomic-address", OR1K_OPERAND_ATOMIC_ADDRESS, HW_H_ATOMIC_ADDRESS, 0, 0,
+#- { 0, { (const PTR) 0 } },
+#+ { 0, { (const PTR) 0 } },
+# { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
+# /* uimm6: uimm6 */
+# { "uimm6", OR1K_OPERAND_UIMM6, HW_H_UIMM6, 5, 6,
+#- { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_UIMM6] } },
+#+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_UIMM6] } },
+# { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
+# /* rD: destination register */
+# { "rD", OR1K_OPERAND_RD, HW_H_GPR, 25, 5,
+#- { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R1] } },
+#+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R1] } },
+# { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
+# /* rA: source register A */
+# { "rA", OR1K_OPERAND_RA, HW_H_GPR, 20, 5,
+#- { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R2] } },
+#+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R2] } },
+# { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
+# /* rB: source register B */
+# { "rB", OR1K_OPERAND_RB, HW_H_GPR, 15, 5,
+#- { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R3] } },
+#+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R3] } },
+# { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
+# /* disp26: pc-rel 26 bit */
+# { "disp26", OR1K_OPERAND_DISP26, HW_H_IADDR, 25, 26,
+#- { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_DISP26] } },
+#+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_DISP26] } },
+# { 0|A(PCREL_ADDR), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
+# /* simm16: 16-bit signed immediate */
+# { "simm16", OR1K_OPERAND_SIMM16, HW_H_SIMM16, 15, 16,
+#- { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_SIMM16] } },
+#+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_SIMM16] } },
+# { 0|A(SIGN_OPT), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
+# /* uimm16: 16-bit unsigned immediate */
+# { "uimm16", OR1K_OPERAND_UIMM16, HW_H_UIMM16, 15, 16,
+#- { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_UIMM16] } },
+#+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_UIMM16] } },
+# { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
+# /* simm16-split: split 16-bit signed immediate */
+# { "simm16-split", OR1K_OPERAND_SIMM16_SPLIT, HW_H_SIMM16, 10, 16,
+#- { 2, { (const PTR) &OR1K_F_SIMM16_SPLIT_MULTI_IFIELD[0] } },
+#+ { 2, { (const PTR) &OR1K_F_SIMM16_SPLIT_MULTI_IFIELD[0] } },
+# { 0|A(SIGN_OPT)|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
+# /* uimm16-split: split 16-bit unsigned immediate */
+# { "uimm16-split", OR1K_OPERAND_UIMM16_SPLIT, HW_H_UIMM16, 10, 16,
+#- { 2, { (const PTR) &OR1K_F_UIMM16_SPLIT_MULTI_IFIELD[0] } },
+#+ { 2, { (const PTR) &OR1K_F_UIMM16_SPLIT_MULTI_IFIELD[0] } },
+# { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
+# /* rDSF: destination register (single floating point mode) */
+# { "rDSF", OR1K_OPERAND_RDSF, HW_H_FSR, 25, 5,
+#- { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R1] } },
+#+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R1] } },
+# { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
+# /* rASF: source register A (single floating point mode) */
+# { "rASF", OR1K_OPERAND_RASF, HW_H_FSR, 20, 5,
+#- { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R2] } },
+#+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R2] } },
+# { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
+# /* rBSF: source register B (single floating point mode) */
+# { "rBSF", OR1K_OPERAND_RBSF, HW_H_FSR, 15, 5,
+#- { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R3] } },
+#+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R3] } },
+# { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
+# /* rDDF: destination register (double floating point mode) */
+# { "rDDF", OR1K_OPERAND_RDDF, HW_H_FDR, 25, 5,
+#- { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R1] } },
+#+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R1] } },
+# { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
+# /* rADF: source register A (double floating point mode) */
+# { "rADF", OR1K_OPERAND_RADF, HW_H_FDR, 25, 5,
+#- { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R1] } },
+#+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R1] } },
+# { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
+# /* rBDF: source register B (double floating point mode) */
+# { "rBDF", OR1K_OPERAND_RBDF, HW_H_FDR, 25, 5,
+#- { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R1] } },
+#+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R1] } },
+# { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
+# /* sentinel */
+# { 0, 0, 0, 0, 0,
+#@@ -2051,7 +2051,7 @@ or1k_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
+#
+# /* Default to not allowing signed overflow. */
+# cd->signed_overflow_ok_p = 0;
+#-
+#+
+# return (CGEN_CPU_DESC) cd;
+# }
+#
+#@@ -2091,7 +2091,7 @@ or1k_cgen_cpu_close (CGEN_CPU_DESC cd)
+# for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
+# if (CGEN_INSN_RX (insns))
+# regfree (CGEN_INSN_RX (insns));
+#- }
+#+ }
+#
+# if (cd->macro_insn_table.init_entries)
+# free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
+#--- a/opcodes/or1k-dis.c
+#+++ b/opcodes/or1k-dis.c
+#@@ -143,7 +143,7 @@ or1k_cgen_print_operand (CGEN_CPU_DESC cd,
+# }
+# }
+#
+#-cgen_print_fn * const or1k_cgen_print_handlers[] =
+#+cgen_print_fn * const or1k_cgen_print_handlers[] =
+# {
+# print_insn_normal,
+# };
+#@@ -333,7 +333,7 @@ print_insn (CGEN_CPU_DESC cd,
+# int length;
+# unsigned long insn_value_cropped;
+#
+#-#ifdef CGEN_VALIDATE_INSN_SUPPORTED
+#+#ifdef CGEN_VALIDATE_INSN_SUPPORTED
+# /* Not needed as insn shouldn't be in hash lists if not supported. */
+# /* Supported by this cpu? */
+# if (! or1k_cgen_insn_supported (cd, insn))
+#@@ -351,7 +351,7 @@ print_insn (CGEN_CPU_DESC cd,
+# relevant part from the buffer. */
+# if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
+# (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
+#- insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
+#+ insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
+# info->endian == BFD_ENDIAN_BIG);
+# else
+# insn_value_cropped = insn_value;
+#@@ -470,7 +470,7 @@ print_insn_or1k (bfd_vma pc, disassemble_info *info)
+# arch = info->arch;
+# if (arch == bfd_arch_unknown)
+# arch = CGEN_BFD_ARCH;
+#-
+#+
+# /* There's no standard way to compute the machine or isa number
+# so we leave it to the target. */
+# #ifdef CGEN_COMPUTE_MACH
+#@@ -511,7 +511,7 @@ print_insn_or1k (bfd_vma pc, disassemble_info *info)
+# break;
+# }
+# }
+#- }
+#+ }
+#
+# /* If we haven't initialized yet, initialize the opcode table. */
+# if (! cd)
+#--- a/opcodes/or1k-ibld.c
+#+++ b/opcodes/or1k-ibld.c
+#@@ -154,7 +154,7 @@ insert_normal (CGEN_CPU_DESC cd,
+# {
+# long minval = - (1L << (length - 1));
+# unsigned long maxval = mask;
+#-
+#+
+# if ((value > 0 && (unsigned long) value > maxval)
+# || value < minval)
+# {
+#@@ -192,7 +192,7 @@ insert_normal (CGEN_CPU_DESC cd,
+# {
+# long minval = - (1L << (length - 1));
+# long maxval = (1L << (length - 1)) - 1;
+#-
+#+
+# if (value < minval || value > maxval)
+# {
+# sprintf
+#@@ -752,12 +752,12 @@ or1k_cgen_extract_operand (CGEN_CPU_DESC cd,
+# return length;
+# }
+#
+#-cgen_insert_fn * const or1k_cgen_insert_handlers[] =
+#+cgen_insert_fn * const or1k_cgen_insert_handlers[] =
+# {
+# insert_insn_normal,
+# };
+#
+#-cgen_extract_fn * const or1k_cgen_extract_handlers[] =
+#+cgen_extract_fn * const or1k_cgen_extract_handlers[] =
+# {
+# extract_insn_normal,
+# };
+--- a/opcodes/ppc-dis.c
++++ b/opcodes/ppc-dis.c
+@@ -687,7 +687,7 @@ print_insn_powerpc (bfd_vma memaddr,
+ (*info->print_address_func) (memaddr + value, info);
+ else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
+ (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
+- else if ((operand->flags & PPC_OPERAND_FSL) != 0)
++ else if ((operand->flags & PPC_OPERAND_FSL) != 0)
+ (*info->fprintf_func) (info->stream, "fsl%ld", value);
+ else if ((operand->flags & PPC_OPERAND_FCR) != 0)
+ (*info->fprintf_func) (info->stream, "fcr%ld", value);
+--- a/opcodes/ppc-opc.c
++++ b/opcodes/ppc-opc.c
+@@ -797,12 +797,12 @@ const struct powerpc_operand powerpc_operands[] =
+ #define FCRT_MASK (0x1f << 21)
+ { 0x1f, 21, 0, 0, PPC_OPERAND_FCR },
+
+- /* Xilinx FSL related masks and macros */
++ /* Xilinx FSL related masks and macros */
+ #define FSL FCRT + 1
+ #define FSL_MASK (0x1f << 11)
+- { 0x1f, 11, 0, 0, PPC_OPERAND_FSL },
++ { 0x1f, 11, 0, 0, PPC_OPERAND_FSL },
+
+- /* Xilinx UDI related masks and macros */
++ /* Xilinx UDI related masks and macros */
+ #define URT FSL + 1
+ { 0x1f, 21, 0, 0, PPC_OPERAND_UDI },
+
+@@ -904,7 +904,7 @@ static long
+ extract_arx (unsigned long insn,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid ATTRIBUTE_UNUSED)
+-{
++{
+ return (insn & 0xf) + 8;
+ }
+
+@@ -1149,11 +1149,11 @@ valid_bo_pre_v2 (long value)
+ {
+ /* Certain encodings have bits that are required to be zero.
+ These are (z must be zero, y may be anything):
+- 0000y
+- 0001y
++ 0000y
++ 0001y
+ 001zy
+- 0100y
+- 0101y
++ 0100y
++ 0101y
+ 011zy
+ 1z00y
+ 1z01y
+@@ -2329,7 +2329,7 @@ extract_vleil (unsigned long insn,
+ #define SCI8BF_MASK SCI8BF(0x3f, 7, 0x1f)
+
+ /* An SD4 form instruction. This is a 16-bit instruction. */
+-#define SD4(op) ((((unsigned long)(op)) & 0xf) << 12)
++#define SD4(op) ((((unsigned long)(op)) & 0xf) << 12)
+ #define SD4_MASK SD4(0xf)
+
+ /* An SE_IM5 form instruction. This is a 16-bit instruction. */
+@@ -2777,7 +2777,7 @@ extract_vleil (unsigned long insn,
+ #define PPCRFMCI PPC_OPCODE_RFMCI
+ #define E500MC PPC_OPCODE_E500MC
+ #define PPCA2 PPC_OPCODE_A2
+-#define TITAN PPC_OPCODE_TITAN
++#define TITAN PPC_OPCODE_TITAN
+ #define MULHW PPC_OPCODE_405 | PPC_OPCODE_440 | TITAN | PPC_OPCODE_VLE
+ #define E500 PPC_OPCODE_E500
+ #define E6500 PPC_OPCODE_E6500
+@@ -3301,7 +3301,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"vandc", VX (4,1092), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+ {"vcmpequh.", VXR(4, 70,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+ {"udi1fcm.", APU(4, 547,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
+-{"udi1fcm", APU(4, 547,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
++{"udi1fcm", APU(4, 547,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
+ {"evmwhssf", VX (4,1095), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+ {"vpmsumh", VX (4,1096), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+ {"evmwlumi", VX (4,1096), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+@@ -3338,7 +3338,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"vpmsumw", VX (4,1160), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+ {"vcmpequw.", VXR(4, 134,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+ {"udi2fcm.", APU(4, 579,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
+-{"udi2fcm", APU(4, 579,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
++{"udi2fcm", APU(4, 579,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
+ {"machhwsuo", XO (4, 76,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+ {"machhwsuo.", XO (4, 76,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+ {"ps_merge10", XOPS(4,592,0), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
+@@ -3354,7 +3354,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"vcmpeqfp.", VXR(4, 198,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+ {"udi3fcm.", APU(4, 611,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
+ {"vcmpequd.", VXR(4, 199,1), VXR_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+-{"udi3fcm", APU(4, 611,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
++{"udi3fcm", APU(4, 611,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
+ {"evdivwu", VX (4,1223), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+ {"vpmsumd", VX (4,1224), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+ {"evaddumiaaw", VX (4,1224), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
+@@ -4404,10 +4404,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"subfc.", XO(31,8,0,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
+ {"sf.", XO(31,8,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
+ {"subc.", XO(31,8,0,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RB, RA}},
+-
++
+ {"mulhdu", XO(31,9,0,0), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
+ {"mulhdu.", XO(31,9,0,1), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
+-
++
+ {"addc", XO(31,10,0,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
+ {"a", XO(31,10,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
+ {"addc.", XO(31,10,0,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
+@@ -4430,11 +4430,11 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM|PPCVLE, PPCNONE, {RT, FXM}},
+
+ {"lwarx", X(31,20), XEH_MASK, PPC|PPCVLE, PPCNONE, {RT, RA0, RB, EH}},
+-
++
+ {"ldx", X(31,21), X_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA0, RB}},
+-
++
+ {"icbt", X(31,22), X_MASK, BOOKE|PPCE300|PPCA2|PPC476|PPCVLE, PPCNONE, {CT, RA0, RB}},
+-
++
+ {"lwzx", X(31,23), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA0, RB}},
+ {"lx", X(31,23), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
+
+@@ -4499,9 +4499,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"lbarx", X(31,52), XEH_MASK, POWER8|PPCVLE, PPCNONE, {RT, RA0, RB, EH}},
+
+ {"ldux", X(31,53), X_MASK, PPC64|PPCVLE, PPCNONE, {RT, RAL, RB}},
+-
++
+ {"dcbst", X(31,54), XRT_MASK, PPC|PPCVLE, PPCNONE, {RA0, RB}},
+-
++
+ {"lwzux", X(31,55), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RAL, RB}},
+ {"lux", X(31,55), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
+
+@@ -4514,7 +4514,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"waitrsv", X(31,62)|(1<<21), 0xffffffff, E500MC|PPCA2, PPCNONE, {0}},
+ {"waitimpl", X(31,62)|(2<<21), 0xffffffff, E500MC|PPCA2, PPCNONE, {0}},
+ {"wait", X(31,62), XWC_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {WC}},
+-
++
+ {"dcbstep", XRT(31,63,0), XRT_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RA0, RB}},
+
+ {"tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
+@@ -4537,7 +4537,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"lwfcmx", APU(31,71,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
+ {"mulhd", XO(31,73,0,0), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
+ {"mulhd.", XO(31,73,0,1), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
+-
++
+ {"mulhw", XO(31,75,0,0), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
+ {"mulhw.", XO(31,75,0,1), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
+
+@@ -4547,14 +4547,14 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, PPCNONE, {SR, RS}},
+
+ {"mfmsr", X(31,83), XRARB_MASK, COM|PPCVLE, PPCNONE, {RT}},
+-
++
+ {"ldarx", X(31,84), XEH_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA0, RB, EH}},
+
+ {"dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, PPC476, {RA0, RB}},
+ {"dcbf", X(31,86), XLRT_MASK, PPC|PPCVLE, PPCNONE, {RA0, RB, L}},
+
+ {"lbzx", X(31,87), X_MASK, COM|PPCVLE, PPCNONE, {RT, RA0, RB}},
+-
++
+ {"lbepx", X(31,95), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA0, RB}},
+
+ {"dni", XRC(31,97,1), XRB_MASK, E6500, PPCNONE, {DUI, DCTL}},
+@@ -4581,7 +4581,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"clf", X(31,118), XTO_MASK, POWER, PPCNONE, {RA, RB}},
+
+ {"lbzux", X(31,119), X_MASK, COM|PPCVLE, PPCNONE, {RT, RAL, RB}},
+-
++
+ {"popcntb", X(31,122), XRB_MASK, POWER5|PPCVLE, PPCNONE, {RA, RS}},
+
+ {"not", XRC(31,124,0), X_MASK, COM, PPCNONE, {RA, RS, RBS}},
+@@ -4590,9 +4590,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"nor.", XRC(31,124,1), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
+
+ {"dcbfep", XRT(31,127,0), XRT_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RA0, RB}},
+-
++
+ {"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {RS}},
+-
++
+ {"dcbtstls", X(31,134), X_MASK, PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA0, RB}},
+
+ {"stvebx", X(31,135), X_MASK, PPCVEC, PPCNONE, {VS, RA0, RB}},
+@@ -4625,9 +4625,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"eratsx.", XRC(31,147,1), X_MASK, PPCA2, PPCNONE, {RT, RA0, RB}},
+
+ {"stdx", X(31,149), X_MASK, PPC64|PPCVLE, PPCNONE, {RS, RA0, RB}},
+-
++
+ {"stwcx.", XRC(31,150,1), X_MASK, PPC|PPCVLE, PPCNONE, {RS, RA0, RB}},
+-
++
+ {"stwx", X(31,151), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RS, RA0, RB}},
+ {"stx", X(31,151), X_MASK, PWRCOM, PPCNONE, {RS, RA, RB}},
+
+@@ -4640,11 +4640,11 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"prtyw", X(31,154), XRB_MASK, POWER6|PPCA2|PPC476, PPCNONE, {RA, RS}},
+
+ {"stdepx", X(31,157), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RS, RA0, RB}},
+-
++
+ {"stwepx", X(31,159), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RS, RA0, RB}},
+-
++
+ {"wrteei", X(31,163), XE_MASK, PPC403|BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {E}},
+-
++
+ {"dcbtls", X(31,166), X_MASK, PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA0, RB}},
+
+ {"stvehx", X(31,167), X_MASK, PPCVEC, PPCNONE, {VS, RA0, RB}},
+@@ -4700,7 +4700,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"ldawx.", XRC(31,212,1), X_MASK, PPCA2, PPCNONE, {RT, RA0, RB}},
+
+ {"stdcx.", XRC(31,214,1), X_MASK, PPC64|PPCVLE, PPCNONE, {RS, RA0, RB}},
+-
++
+ {"stbx", X(31,215), X_MASK, COM|PPCVLE, PPCNONE, {RS, RA0, RB}},
+
+ {"sllq", XRC(31,216,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
+@@ -4710,7 +4710,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"sleq.", XRC(31,217,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
+
+ {"stbepx", X(31,223), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RS, RA0, RB}},
+-
++
+ {"icblc", X(31,230), X_MASK, PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA0, RB}},
+
+ {"stvx", X(31,231), X_MASK, PPCVEC|PPCVLE, PPCNONE, {VS, RA0, RB}},
+@@ -4723,7 +4723,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+
+ {"mulld", XO(31,233,0,0), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
+ {"mulld.", XO(31,233,0,1), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
+-
++
+ {"addme", XO(31,234,0,0), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}},
+ {"ame", XO(31,234,0,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
+ {"addme.", XO(31,234,0,1), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}},
+@@ -5070,7 +5070,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, PPCNONE, {RT}},
+ {"mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, PPCNONE, {RT}},
+ {"mfspr", X(31,339), X_MASK, COM|PPCVLE, PPCNONE, {RT, SPR}},
+-
++
+ {"lwax", X(31,341), X_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA0, RB}},
+
+ {"dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, PPCNONE, {RA, RB, STRM}},
+@@ -5202,7 +5202,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+
+ {"dccci", X(31,454), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, PPCNONE, {RAOPT, RBOPT}},
+ {"dci", X(31,454), XRARB_MASK, PPCA2|PPC476|PPCVLE, PPCNONE, {CT}},
+-
++
+ {"divdu", XO(31,457,0,0), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
+ {"divdu.", XO(31,457,0,1), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
+
+@@ -5375,7 +5375,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, PPCNONE, {RS}},
+ {"mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, PPCNONE, {RS}},
+ {"mtspr", X(31,467), X_MASK, COM|PPCVLE, PPCNONE, {SPR, RS}},
+-
++
+ {"dcbi", X(31,470), XRT_MASK, PPC|PPCVLE, PPCNONE, {RA0, RB}},
+
+ {"nand", XRC(31,476,0), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
+@@ -5424,7 +5424,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"subfco.", XO(31,8,1,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
+ {"sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
+ {"subco.", XO(31,8,1,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RB, RA}},
+-
++
+ {"addco", XO(31,10,1,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
+ {"ao", XO(31,10,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
+ {"addco.", XO(31,10,1,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
+@@ -5818,10 +5818,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+
+ {"iccci", X(31,966), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, PPCNONE, {RAOPT, RBOPT}},
+ {"ici", X(31,966), XRARB_MASK, PPCA2|PPC476|PPCVLE, PPCNONE, {CT}},
+-
++
+ {"divduo", XO(31,457,1,0), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
+ {"divduo.", XO(31,457,1,1), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
+-
++
+ {"divwuo", XO(31,459,1,0), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
+ {"divwuo.", XO(31,459,1,1), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
+
+@@ -5855,7 +5855,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+
+ {"divdo", XO(31,489,1,0), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
+ {"divdo.", XO(31,489,1,1), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
+-
++
+ {"divwo", XO(31,491,1,0), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
+ {"divwo.", XO(31,491,1,1), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
+
+@@ -6027,8 +6027,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"dctfix", XRC(59,290,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
+ {"dctfix.", XRC(59,290,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
+
+-{"ddedpd", XRC(59,322,0), X_MASK, POWER6, PPCNONE, {SP, FRT, FRB}},
+-{"ddedpd.", XRC(59,322,1), X_MASK, POWER6, PPCNONE, {SP, FRT, FRB}},
++{"ddedpd", XRC(59,322,0), X_MASK, POWER6, PPCNONE, {SP, FRT, FRB}},
++{"ddedpd.", XRC(59,322,1), X_MASK, POWER6, PPCNONE, {SP, FRT, FRB}},
+
+ {"dxex", XRC(59,354,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
+ {"dxex.", XRC(59,354,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
+@@ -6501,7 +6501,7 @@ const struct powerpc_opcode vle_opcodes[] = {
+ {"se_cmpl", SE_RR(3,1), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}},
+ {"se_cmph", SE_RR(3,2), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}},
+ {"se_cmphl", SE_RR(3,3), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}},
+-
++
+ {"e_cmpi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, PPCNONE, {CRD32, RA, SCLSCI8}},
+ {"e_cmpli", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, PPCNONE, {CRD32, RA, SCLSCI8}},
+ {"e_addi", SCI8(6,16), SCI8_MASK, PPCVLE, PPCNONE, {RT, RA, SCLSCI8}},
+@@ -6541,7 +6541,7 @@ const struct powerpc_opcode vle_opcodes[] = {
+ {"se_cmpi", SE_IM5(10,1), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, UI5}},
+ {"se_bmaski", SE_IM5(11,0), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, UI5}},
+ {"se_andi", SE_IM5(11,1), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, UI5}},
+-
++
+ {"e_lbz", OP(12), OP_MASK, PPCVLE, PPCNONE, {RT, D, RA0}},
+ {"e_stb", OP(13), OP_MASK, PPCVLE, PPCNONE, {RT, D, RA0}},
+ {"e_lha", OP(14), OP_MASK, PPCVLE, PPCNONE, {RT, D, RA0}},
+@@ -6555,7 +6555,7 @@ const struct powerpc_opcode vle_opcodes[] = {
+ {"se_and", SE_RR(17,2), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}},
+ {"se_and.", SE_RR(17,3), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}},
+ {"se_li", IM7(9), IM7_MASK, PPCVLE, PPCNONE, {RX, UI7}},
+-
++
+ {"e_lwz", OP(20), OP_MASK, PPCVLE, PPCNONE, {RT, D, RA0}},
+ {"e_stw", OP(21), OP_MASK, PPCVLE, PPCNONE, {RT, D, RA0}},
+ {"e_lhz", OP(22), OP_MASK, PPCVLE, PPCNONE, {RT, D, RA0}},
+@@ -6625,7 +6625,7 @@ const struct powerpc_opcode vle_opcodes[] = {
+ {"e_bfl", EBD15(30,8,BO32F,1), EBD15_MASK, PPCVLE, PPCNONE, {BI32,B15}},
+ {"e_bt", EBD15(30,8,BO32T,0), EBD15_MASK, PPCVLE, PPCNONE, {BI32,B15}},
+ {"e_btl", EBD15(30,8,BO32T,1), EBD15_MASK, PPCVLE, PPCNONE, {BI32,B15}},
+-
++
+ {"e_cmph", X(31,14), X_MASK, PPCVLE, PPCNONE, {CRD, RA, RB}},
+ {"e_cmphl", X(31,46), X_MASK, PPCVLE, PPCNONE, {CRD, RA, RB}},
+ {"e_crandc", XL(31,129), XL_MASK, PPCVLE, PPCNONE, {BT, BA, BB}},
+@@ -6637,18 +6637,18 @@ const struct powerpc_opcode vle_opcodes[] = {
+ {"e_mcrf", XL(31,16), XL_MASK, PPCVLE, PPCNONE, {CRD, CR}},
+ {"e_slwi", EX(31,112), EX_MASK, PPCVLE, PPCNONE, {RA, RS, SH}},
+ {"e_slwi.", EX(31,113), EX_MASK, PPCVLE, PPCNONE, {RA, RS, SH}},
+-
++
+ {"e_crand", XL(31,257), XL_MASK, PPCVLE, PPCNONE, {BT, BA, BB}},
+-
++
+ {"e_rlw", EX(31,560), EX_MASK, PPCVLE, PPCNONE, {RA, RS, RB}},
+ {"e_rlw.", EX(31,561), EX_MASK, PPCVLE, PPCNONE, {RA, RS, RB}},
+-
++
+ {"e_crset", XL(31,289), XL_MASK, PPCVLE, PPCNONE, {BT, BAT, BBA}},
+ {"e_creqv", XL(31,289), XL_MASK, PPCVLE, PPCNONE, {BT, BA, BB}},
+-
++
+ {"e_rlwi", EX(31,624), EX_MASK, PPCVLE, PPCNONE, {RA, RS, SH}},
+ {"e_rlwi.", EX(31,625), EX_MASK, PPCVLE, PPCNONE, {RA, RS, SH}},
+-
++
+ {"e_crorc", XL(31,417), XL_MASK, PPCVLE, PPCNONE, {BT, BA, BB}},
+
+ {"e_crmove", XL(31,449), XL_MASK, PPCVLE, PPCNONE, {BT, BA, BBA}},
+@@ -6658,19 +6658,19 @@ const struct powerpc_opcode vle_opcodes[] = {
+
+ {"e_srwi", EX(31,1136), EX_MASK, PPCVLE, PPCNONE, {RA, RS, SH}},
+ {"e_srwi.", EX(31,1137), EX_MASK, PPCVLE, PPCNONE, {RA, RS, SH}},
+-
++
+ {"se_lbz", SD4(8), SD4_MASK, PPCVLE, PPCNONE, {RZ, SE_SD, RX}},
+-
++
+ {"se_stb", SD4(9), SD4_MASK, PPCVLE, PPCNONE, {RZ, SE_SD, RX}},
+-
++
+ {"se_lhz", SD4(10), SD4_MASK, PPCVLE, PPCNONE, {RZ, SE_SDH, RX}},
+-
++
+ {"se_sth", SD4(11), SD4_MASK, PPCVLE, PPCNONE, {RZ, SE_SDH, RX}},
+-
++
+ {"se_lwz", SD4(12), SD4_MASK, PPCVLE, PPCNONE, {RZ, SE_SDW, RX}},
+-
++
+ {"se_stw", SD4(13), SD4_MASK, PPCVLE, PPCNONE, {RZ, SE_SDW, RX}},
+-
++
+ {"se_bge", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}},
+ {"se_bnl", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}},
+ {"se_ble", EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}},
+#--- a/opcodes/rl78-decode.c
+#+++ b/opcodes/rl78-decode.c
+#@@ -203,9 +203,9 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("nop");
+# #line 912 "rl78-decode.opc"
+# ID(nop);
+#-
+#+
+# /*----------------------------------------------------------------------*/
+#-
+#+
+# }
+# break;
+# case 0x01:
+#@@ -226,7 +226,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("addw %0, %1");
+# #line 274 "rl78-decode.opc"
+# ID(add); W(); DR(AX); SRW(rw); Fzac;
+#-
+#+
+# }
+# break;
+# case 0x02:
+#@@ -241,7 +241,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("addw %0, %e!1");
+# #line 265 "rl78-decode.opc"
+# ID(add); W(); DR(AX); SM(None, IMMU(2)); Fzac;
+#-
+#+
+# }
+# break;
+# case 0x04:
+#@@ -256,7 +256,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("addw %0, #%1");
+# #line 271 "rl78-decode.opc"
+# ID(add); W(); DR(AX); SC(IMMU(2)); Fzac;
+#-
+#+
+# }
+# break;
+# case 0x06:
+#@@ -271,7 +271,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("addw %0, %1");
+# #line 277 "rl78-decode.opc"
+# ID(add); W(); DR(AX); SM(None, SADDR); Fzac;
+#-
+#+
+# }
+# break;
+# case 0x08:
+#@@ -286,9 +286,9 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("xch a, x");
+# #line 1235 "rl78-decode.opc"
+# ID(xch); DR(A); SR(X);
+#-
+#+
+# /*----------------------------------------------------------------------*/
+#-
+#+
+# }
+# break;
+# case 0x09:
+#@@ -303,7 +303,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("mov %0, %e1");
+# #line 678 "rl78-decode.opc"
+# ID(mov); DR(A); SM(B, IMMU(2));
+#-
+#+
+# }
+# break;
+# case 0x0a:
+#@@ -318,9 +318,9 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("add %0, #%1");
+# #line 228 "rl78-decode.opc"
+# ID(add); DM(None, SADDR); SC(IMMU(1)); Fzac;
+#-
+#+
+# /*----------------------------------------------------------------------*/
+#-
+#+
+# }
+# break;
+# case 0x0b:
+#@@ -335,7 +335,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("add %0, %1");
+# #line 222 "rl78-decode.opc"
+# ID(add); DR(A); SM(None, SADDR); Fzac;
+#-
+#+
+# }
+# break;
+# case 0x0c:
+#@@ -350,7 +350,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("add %0, #%1");
+# #line 216 "rl78-decode.opc"
+# ID(add); DR(A); SC(IMMU(1)); Fzac;
+#-
+#+
+# }
+# break;
+# case 0x0d:
+#@@ -365,7 +365,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("add %0, %e1");
+# #line 204 "rl78-decode.opc"
+# ID(add); DR(A); SM(HL, 0); Fzac;
+#-
+#+
+# }
+# break;
+# case 0x0e:
+#@@ -380,7 +380,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("add %0, %ea1");
+# #line 210 "rl78-decode.opc"
+# ID(add); DR(A); SM(HL, IMMU(1)); Fzac;
+#-
+#+
+# }
+# break;
+# case 0x0f:
+#@@ -395,7 +395,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("add %0, %e!1");
+# #line 201 "rl78-decode.opc"
+# ID(add); DR(A); SM(None, IMMU(2)); Fzac;
+#-
+#+
+# }
+# break;
+# case 0x10:
+#@@ -410,9 +410,9 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("addw %0, #%1");
+# #line 280 "rl78-decode.opc"
+# ID(add); W(); DR(SP); SC(IMMU(1)); Fzac;
+#-
+#+
+# /*----------------------------------------------------------------------*/
+#-
+#+
+# }
+# break;
+# case 0x11:
+#@@ -430,9 +430,9 @@ rl78_decode_opcode (unsigned long pc AU,
+# op ++;
+# pc ++;
+# goto start_again;
+#-
+#+
+# /*----------------------------------------------------------------------*/
+#-
+#+
+# }
+# break;
+# case 0x12:
+#@@ -452,7 +452,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("movw %0, %1");
+# #line 859 "rl78-decode.opc"
+# ID(mov); W(); DRW(ra); SR(AX);
+#-
+#+
+# }
+# break;
+# case 0x13:
+#@@ -472,7 +472,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("movw %0, %1");
+# #line 856 "rl78-decode.opc"
+# ID(mov); W(); DR(AX); SRW(ra);
+#-
+#+
+# }
+# break;
+# case 0x18:
+#@@ -486,8 +486,8 @@ rl78_decode_opcode (unsigned long pc AU,
+# }
+# SYNTAX("mov %e0, %1");
+# #line 729 "rl78-decode.opc"
+#- ID(mov); DM(B, IMMU(2)); SR(A);
+#-
+#+ ID(mov); DM(B, IMMU(2)); SR(A);
+#+
+# }
+# break;
+# case 0x19:
+#@@ -501,8 +501,8 @@ rl78_decode_opcode (unsigned long pc AU,
+# }
+# SYNTAX("mov %e0, #%1");
+# #line 726 "rl78-decode.opc"
+#- ID(mov); DM(B, IMMU(2)); SC(IMMU(1));
+#-
+#+ ID(mov); DM(B, IMMU(2)); SC(IMMU(1));
+#+
+# }
+# break;
+# case 0x1a:
+#@@ -517,9 +517,9 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("addc %0, #%1");
+# #line 260 "rl78-decode.opc"
+# ID(addc); DM(None, SADDR); SC(IMMU(1)); Fzac;
+#-
+#+
+# /*----------------------------------------------------------------------*/
+#-
+#+
+# }
+# break;
+# case 0x1b:
+#@@ -534,7 +534,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("addc %0, %1");
+# #line 257 "rl78-decode.opc"
+# ID(addc); DR(A); SM(None, SADDR); Fzac;
+#-
+#+
+# }
+# break;
+# case 0x1c:
+#@@ -549,7 +549,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("addc %0, #%1");
+# #line 248 "rl78-decode.opc"
+# ID(addc); DR(A); SC(IMMU(1)); Fzac;
+#-
+#+
+# }
+# break;
+# case 0x1d:
+#@@ -564,7 +564,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("addc %0, %e1");
+# #line 236 "rl78-decode.opc"
+# ID(addc); DR(A); SM(HL, 0); Fzac;
+#-
+#+
+# }
+# break;
+# case 0x1e:
+#@@ -579,7 +579,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("addc %0, %ea1");
+# #line 245 "rl78-decode.opc"
+# ID(addc); DR(A); SM(HL, IMMU(1)); Fzac;
+#-
+#+
+# }
+# break;
+# case 0x1f:
+#@@ -594,7 +594,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("addc %0, %e!1");
+# #line 233 "rl78-decode.opc"
+# ID(addc); DR(A); SM(None, IMMU(2)); Fzac;
+#-
+#+
+# }
+# break;
+# case 0x20:
+#@@ -609,9 +609,9 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("subw %0, #%1");
+# #line 1199 "rl78-decode.opc"
+# ID(sub); W(); DR(SP); SC(IMMU(1)); Fzac;
+#-
+#+
+# /*----------------------------------------------------------------------*/
+#-
+#+
+# }
+# break;
+# case 0x21:
+#@@ -632,7 +632,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("subw %0, %1");
+# #line 1193 "rl78-decode.opc"
+# ID(sub); W(); DR(AX); SRW(rw); Fzac;
+#-
+#+
+# }
+# break;
+# case 0x22:
+#@@ -647,7 +647,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("subw %0, %e!1");
+# #line 1184 "rl78-decode.opc"
+# ID(sub); W(); DR(AX); SM(None, IMMU(2)); Fzac;
+#-
+#+
+# }
+# break;
+# case 0x24:
+#@@ -662,7 +662,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("subw %0, #%1");
+# #line 1190 "rl78-decode.opc"
+# ID(sub); W(); DR(AX); SC(IMMU(2)); Fzac;
+#-
+#+
+# }
+# break;
+# case 0x26:
+#@@ -677,7 +677,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("subw %0, %1");
+# #line 1196 "rl78-decode.opc"
+# ID(sub); W(); DR(AX); SM(None, SADDR); Fzac;
+#-
+#+
+# }
+# break;
+# case 0x28:
+#@@ -692,7 +692,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("mov %e0, %1");
+# #line 741 "rl78-decode.opc"
+# ID(mov); DM(C, IMMU(2)); SR(A);
+#-
+#+
+# }
+# break;
+# case 0x29:
+#@@ -707,7 +707,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("mov %0, %e1");
+# #line 684 "rl78-decode.opc"
+# ID(mov); DR(A); SM(C, IMMU(2));
+#-
+#+
+# }
+# break;
+# case 0x2a:
+#@@ -722,9 +722,9 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("sub %0, #%1");
+# #line 1147 "rl78-decode.opc"
+# ID(sub); DM(None, SADDR); SC(IMMU(1)); Fzac;
+#-
+#+
+# /*----------------------------------------------------------------------*/
+#-
+#+
+# }
+# break;
+# case 0x2b:
+#@@ -739,7 +739,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("sub %0, %1");
+# #line 1141 "rl78-decode.opc"
+# ID(sub); DR(A); SM(None, SADDR); Fzac;
+#-
+#+
+# }
+# break;
+# case 0x2c:
+#@@ -754,7 +754,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("sub %0, #%1");
+# #line 1135 "rl78-decode.opc"
+# ID(sub); DR(A); SC(IMMU(1)); Fzac;
+#-
+#+
+# }
+# break;
+# case 0x2d:
+#@@ -769,7 +769,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("sub %0, %e1");
+# #line 1123 "rl78-decode.opc"
+# ID(sub); DR(A); SM(HL, 0); Fzac;
+#-
+#+
+# }
+# break;
+# case 0x2e:
+#@@ -784,7 +784,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("sub %0, %ea1");
+# #line 1129 "rl78-decode.opc"
+# ID(sub); DR(A); SM(HL, IMMU(1)); Fzac;
+#-
+#+
+# }
+# break;
+# case 0x2f:
+#@@ -799,7 +799,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("sub %0, %e!1");
+# #line 1120 "rl78-decode.opc"
+# ID(sub); DR(A); SM(None, IMMU(2)); Fzac;
+#-
+#+
+# }
+# break;
+# case 0x30:
+#@@ -820,7 +820,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("movw %0, #%1");
+# #line 853 "rl78-decode.opc"
+# ID(mov); W(); DRW(rg); SC(IMMU(2));
+#-
+#+
+# }
+# break;
+# case 0x31:
+#@@ -842,9 +842,9 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("btclr %s1, $%a0");
+# #line 416 "rl78-decode.opc"
+# ID(branch_cond_clear); SM(None, SADDR); SB(bit); DC(pc+IMMS(1)+4); COND(T);
+#-
+#+
+# /*----------------------------------------------------------------------*/
+#-
+#+
+# }
+# break;
+# case 0x01:
+#@@ -862,7 +862,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("btclr %1, $%a0");
+# #line 410 "rl78-decode.opc"
+# ID(branch_cond_clear); DC(pc+IMMS(1)+3); SR(A); SB(bit); COND(T);
+#-
+#+
+# }
+# break;
+# case 0x02:
+#@@ -880,9 +880,9 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("bt %s1, $%a0");
+# #line 402 "rl78-decode.opc"
+# ID(branch_cond); SM(None, SADDR); SB(bit); DC(pc+IMMS(1)+4); COND(T);
+#-
+#+
+# /*----------------------------------------------------------------------*/
+#-
+#+
+# }
+# break;
+# case 0x03:
+#@@ -900,7 +900,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("bt %1, $%a0");
+# #line 396 "rl78-decode.opc"
+# ID(branch_cond); DC(pc+IMMS(1)+3); SR(A); SB(bit); COND(T);
+#-
+#+
+# }
+# break;
+# case 0x04:
+#@@ -918,9 +918,9 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("bf %s1, $%a0");
+# #line 363 "rl78-decode.opc"
+# ID(branch_cond); SM(None, SADDR); SB(bit); DC(pc+IMMS(1)+4); COND(F);
+#-
+#+
+# /*----------------------------------------------------------------------*/
+#-
+#+
+# }
+# break;
+# case 0x05:
+#@@ -938,7 +938,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("bf %1, $%a0");
+# #line 357 "rl78-decode.opc"
+# ID(branch_cond); DC(pc+IMMS(1)+3); SR(A); SB(bit); COND(F);
+#-
+#+
+# }
+# break;
+# case 0x07:
+#@@ -956,7 +956,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("shl %0, %1");
+# #line 1076 "rl78-decode.opc"
+# ID(shl); DR(C); SC(cnt);
+#-
+#+
+# }
+# break;
+# case 0x08:
+#@@ -974,7 +974,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("shl %0, %1");
+# #line 1073 "rl78-decode.opc"
+# ID(shl); DR(B); SC(cnt);
+#-
+#+
+# }
+# break;
+# case 0x09:
+#@@ -992,7 +992,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("shl %0, %1");
+# #line 1070 "rl78-decode.opc"
+# ID(shl); DR(A); SC(cnt);
+#-
+#+
+# }
+# break;
+# case 0x0a:
+#@@ -1010,7 +1010,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("shr %0, %1");
+# #line 1087 "rl78-decode.opc"
+# ID(shr); DR(A); SC(cnt);
+#-
+#+
+# }
+# break;
+# case 0x0b:
+#@@ -1028,7 +1028,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("sar %0, %1");
+# #line 1034 "rl78-decode.opc"
+# ID(sar); DR(A); SC(cnt);
+#-
+#+
+# }
+# break;
+# case 0x0c:
+#@@ -1047,9 +1047,9 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("shlw %0, %1");
+# #line 1082 "rl78-decode.opc"
+# ID(shl); W(); DR(BC); SC(wcnt);
+#-
+#+
+# /*----------------------------------------------------------------------*/
+#-
+#+
+# }
+# break;
+# case 0x0d:
+#@@ -1068,7 +1068,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("shlw %0, %1");
+# #line 1079 "rl78-decode.opc"
+# ID(shl); W(); DR(AX); SC(wcnt);
+#-
+#+
+# }
+# break;
+# case 0x0e:
+#@@ -1087,9 +1087,9 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("shrw %0, %1");
+# #line 1090 "rl78-decode.opc"
+# ID(shr); W(); DR(AX); SC(wcnt);
+#-
+#+
+# /*----------------------------------------------------------------------*/
+#-
+#+
+# }
+# break;
+# case 0x0f:
+#@@ -1108,9 +1108,9 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("sarw %0, %1");
+# #line 1037 "rl78-decode.opc"
+# ID(sar); W(); DR(AX); SC(wcnt);
+#-
+#+
+# /*----------------------------------------------------------------------*/
+#-
+#+
+# }
+# break;
+# case 0x80:
+#@@ -1128,7 +1128,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("btclr %s1, $%a0");
+# #line 413 "rl78-decode.opc"
+# ID(branch_cond_clear); SM(None, SFR); SB(bit); DC(pc+IMMS(1)+4); COND(T);
+#-
+#+
+# }
+# break;
+# case 0x81:
+#@@ -1146,7 +1146,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("btclr %e1, $%a0");
+# #line 407 "rl78-decode.opc"
+# ID(branch_cond_clear); DC(pc+IMMS(1)+3); SM(HL,0); SB(bit); COND(T);
+#-
+#+
+# }
+# break;
+# case 0x82:
+#@@ -1164,7 +1164,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("bt %s1, $%a0");
+# #line 399 "rl78-decode.opc"
+# ID(branch_cond); SM(None, SFR); SB(bit); DC(pc+IMMS(1)+4); COND(T);
+#-
+#+
+# }
+# break;
+# case 0x83:
+#@@ -1182,7 +1182,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("bt %e1, $%a0");
+# #line 393 "rl78-decode.opc"
+# ID(branch_cond); DC(pc+IMMS(1)+3); SM(HL,0); SB(bit); COND(T);
+#-
+#+
+# }
+# break;
+# case 0x84:
+#@@ -1200,7 +1200,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("bf %s1, $%a0");
+# #line 360 "rl78-decode.opc"
+# ID(branch_cond); SM(None, SFR); SB(bit); DC(pc+IMMS(1)+4); COND(F);
+#-
+#+
+# }
+# break;
+# case 0x85:
+#@@ -1218,7 +1218,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("bf %e1, $%a0");
+# #line 354 "rl78-decode.opc"
+# ID(branch_cond); DC(pc+IMMS(1)+3); SM(HL,0); SB(bit); COND(F);
+#-
+#+
+# }
+# break;
+# default: UNSUPPORTED(); break;
+#@@ -1241,9 +1241,9 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("xchw %0, %1");
+# #line 1240 "rl78-decode.opc"
+# ID(xch); W(); DR(AX); SRW(ra);
+#-
+#+
+# /*----------------------------------------------------------------------*/
+#-
+#+
+# }
+# break;
+# case 0x38:
+#@@ -1257,8 +1257,8 @@ rl78_decode_opcode (unsigned long pc AU,
+# }
+# SYNTAX("mov %e0, #%1");
+# #line 738 "rl78-decode.opc"
+#- ID(mov); DM(C, IMMU(2)); SC(IMMU(1));
+#-
+#+ ID(mov); DM(C, IMMU(2)); SC(IMMU(1));
+#+
+# }
+# break;
+# case 0x39:
+#@@ -1272,8 +1272,8 @@ rl78_decode_opcode (unsigned long pc AU,
+# }
+# SYNTAX("mov %e0, #%1");
+# #line 732 "rl78-decode.opc"
+#- ID(mov); DM(BC, IMMU(2)); SC(IMMU(1));
+#-
+#+ ID(mov); DM(BC, IMMU(2)); SC(IMMU(1));
+#+
+# }
+# break;
+# case 0x3a:
+#@@ -1288,9 +1288,9 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("subc %0, #%1");
+# #line 1179 "rl78-decode.opc"
+# ID(subc); DM(None, SADDR); SC(IMMU(1)); Fzac;
+#-
+#+
+# /*----------------------------------------------------------------------*/
+#-
+#+
+# }
+# break;
+# case 0x3b:
+#@@ -1305,7 +1305,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("subc %0, %1");
+# #line 1176 "rl78-decode.opc"
+# ID(subc); DR(A); SM(None, SADDR); Fzac;
+#-
+#+
+# }
+# break;
+# case 0x3c:
+#@@ -1320,7 +1320,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("subc %0, #%1");
+# #line 1167 "rl78-decode.opc"
+# ID(subc); DR(A); SC(IMMU(1)); Fzac;
+#-
+#+
+# }
+# break;
+# case 0x3d:
+#@@ -1335,7 +1335,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("subc %0, %e1");
+# #line 1155 "rl78-decode.opc"
+# ID(subc); DR(A); SM(HL, 0); Fzac;
+#-
+#+
+# }
+# break;
+# case 0x3e:
+#@@ -1350,7 +1350,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("subc %0, %ea1");
+# #line 1164 "rl78-decode.opc"
+# ID(subc); DR(A); SM(HL, IMMU(1)); Fzac;
+#-
+#+
+# }
+# break;
+# case 0x3f:
+#@@ -1365,7 +1365,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("subc %0, %e!1");
+# #line 1152 "rl78-decode.opc"
+# ID(subc); DR(A); SM(None, IMMU(2)); Fzac;
+#-
+#+
+# }
+# break;
+# case 0x40:
+#@@ -1380,7 +1380,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("cmp %e!0, #%1");
+# #line 480 "rl78-decode.opc"
+# ID(cmp); DM(None, IMMU(2)); SC(IMMU(1)); Fzac;
+#-
+#+
+# }
+# break;
+# case 0x41:
+#@@ -1394,8 +1394,8 @@ rl78_decode_opcode (unsigned long pc AU,
+# }
+# SYNTAX("mov %0, #%1");
+# #line 717 "rl78-decode.opc"
+#- ID(mov); DR(ES); SC(IMMU(1));
+#-
+#+ ID(mov); DR(ES); SC(IMMU(1));
+#+
+# }
+# break;
+# case 0x42:
+#@@ -1410,7 +1410,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("cmpw %0, %e!1");
+# #line 531 "rl78-decode.opc"
+# ID(cmp); W(); DR(AX); SM(None, IMMU(2)); Fzac;
+#-
+#+
+# }
+# break;
+# case 0x43:
+#@@ -1430,7 +1430,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("cmpw %0, %1");
+# #line 540 "rl78-decode.opc"
+# ID(cmp); W(); DR(AX); SRW(ra); Fzac;
+#-
+#+
+# }
+# break;
+# case 0x44:
+#@@ -1445,7 +1445,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("cmpw %0, #%1");
+# #line 537 "rl78-decode.opc"
+# ID(cmp); W(); DR(AX); SC(IMMU(2)); Fzac;
+#-
+#+
+# }
+# break;
+# case 0x46:
+#@@ -1460,9 +1460,9 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("cmpw %0, %1");
+# #line 543 "rl78-decode.opc"
+# ID(cmp); W(); DR(AX); SM(None, SADDR); Fzac;
+#-
+#+
+# /*----------------------------------------------------------------------*/
+#-
+#+
+# }
+# break;
+# case 0x48:
+#@@ -1476,8 +1476,8 @@ rl78_decode_opcode (unsigned long pc AU,
+# }
+# SYNTAX("mov %e0, %1");
+# #line 735 "rl78-decode.opc"
+#- ID(mov); DM(BC, IMMU(2)); SR(A);
+#-
+#+ ID(mov); DM(BC, IMMU(2)); SR(A);
+#+
+# }
+# break;
+# case 0x49:
+#@@ -1492,7 +1492,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("mov %0, %e1");
+# #line 681 "rl78-decode.opc"
+# ID(mov); DR(A); SM(BC, IMMU(2));
+#-
+#+
+# }
+# break;
+# case 0x4a:
+#@@ -1507,7 +1507,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("cmp %0, #%1");
+# #line 483 "rl78-decode.opc"
+# ID(cmp); DM(None, SADDR); SC(IMMU(1)); Fzac;
+#-
+#+
+# }
+# break;
+# case 0x4b:
+#@@ -1522,9 +1522,9 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("cmp %0, %1");
+# #line 510 "rl78-decode.opc"
+# ID(cmp); DR(A); SM(None, SADDR); Fzac;
+#-
+#+
+# /*----------------------------------------------------------------------*/
+#-
+#+
+# }
+# break;
+# case 0x4c:
+#@@ -1539,7 +1539,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("cmp %0, #%1");
+# #line 501 "rl78-decode.opc"
+# ID(cmp); DR(A); SC(IMMU(1)); Fzac;
+#-
+#+
+# }
+# break;
+# case 0x4d:
+#@@ -1554,7 +1554,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("cmp %0, %e1");
+# #line 489 "rl78-decode.opc"
+# ID(cmp); DR(A); SM(HL, 0); Fzac;
+#-
+#+
+# }
+# break;
+# case 0x4e:
+#@@ -1569,7 +1569,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("cmp %0, %ea1");
+# #line 498 "rl78-decode.opc"
+# ID(cmp); DR(A); SM(HL, IMMU(1)); Fzac;
+#-
+#+
+# }
+# break;
+# case 0x4f:
+#@@ -1584,7 +1584,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("cmp %0, %e!1");
+# #line 486 "rl78-decode.opc"
+# ID(cmp); DR(A); SM(None, IMMU(2)); Fzac;
+#-
+#+
+# }
+# break;
+# case 0x50:
+#@@ -1609,7 +1609,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("mov %0, #%1");
+# #line 669 "rl78-decode.opc"
+# ID(mov); DRB(reg); SC(IMMU(1));
+#-
+#+
+# }
+# break;
+# case 0x58:
+#@@ -1624,7 +1624,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("movw %e0, %1");
+# #line 871 "rl78-decode.opc"
+# ID(mov); W(); DM(B, IMMU(2)); SR(AX);
+#-
+#+
+# }
+# break;
+# case 0x59:
+#@@ -1639,7 +1639,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("movw %0, %e1");
+# #line 862 "rl78-decode.opc"
+# ID(mov); W(); DR(AX); SM(B, IMMU(2));
+#-
+#+
+# }
+# break;
+# case 0x5a:
+#@@ -1654,9 +1654,9 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("and %0, #%1");
+# #line 312 "rl78-decode.opc"
+# ID(and); DM(None, SADDR); SC(IMMU(1)); Fz;
+#-
+#+
+# /*----------------------------------------------------------------------*/
+#-
+#+
+# }
+# break;
+# case 0x5b:
+#@@ -1671,7 +1671,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("and %0, %1");
+# #line 309 "rl78-decode.opc"
+# ID(and); DR(A); SM(None, SADDR); Fz;
+#-
+#+
+# }
+# break;
+# case 0x5c:
+#@@ -1686,7 +1686,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("and %0, #%1");
+# #line 300 "rl78-decode.opc"
+# ID(and); DR(A); SC(IMMU(1)); Fz;
+#-
+#+
+# }
+# break;
+# case 0x5d:
+#@@ -1701,7 +1701,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("and %0, %e1");
+# #line 288 "rl78-decode.opc"
+# ID(and); DR(A); SM(HL, 0); Fz;
+#-
+#+
+# }
+# break;
+# case 0x5e:
+#@@ -1716,7 +1716,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("and %0, %ea1");
+# #line 294 "rl78-decode.opc"
+# ID(and); DR(A); SM(HL, IMMU(1)); Fz;
+#-
+#+
+# }
+# break;
+# case 0x5f:
+#@@ -1731,7 +1731,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("and %0, %e!1");
+# #line 285 "rl78-decode.opc"
+# ID(and); DR(A); SM(None, IMMU(2)); Fz;
+#-
+#+
+# }
+# break;
+# case 0x60:
+#@@ -1755,7 +1755,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("mov %0, %1");
+# #line 672 "rl78-decode.opc"
+# ID(mov); DR(A); SRB(rba);
+#-
+#+
+# }
+# break;
+# case 0x61:
+#@@ -1784,7 +1784,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("add %0, %1");
+# #line 225 "rl78-decode.opc"
+# ID(add); DRB(reg); SR(A); Fzac;
+#-
+#+
+# }
+# break;
+# case 0x08:
+#@@ -1808,7 +1808,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("add %0, %1");
+# #line 219 "rl78-decode.opc"
+# ID(add); DR(A); SRB(rba); Fzac;
+#-
+#+
+# }
+# break;
+# case 0x09:
+#@@ -1823,7 +1823,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("addw %0, %ea1");
+# #line 268 "rl78-decode.opc"
+# ID(add); W(); DR(AX); SM(HL, IMMU(1)); Fzac;
+#-
+#+
+# }
+# break;
+# case 0x10:
+#@@ -1848,7 +1848,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("addc %0, %1");
+# #line 254 "rl78-decode.opc"
+# ID(addc); DRB(reg); SR(A); Fzac;
+#-
+#+
+# }
+# break;
+# case 0x18:
+#@@ -1872,7 +1872,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("addc %0, %1");
+# #line 251 "rl78-decode.opc"
+# ID(addc); DR(A); SRB(rba); Fzac;
+#-
+#+
+# }
+# break;
+# case 0x20:
+#@@ -1897,7 +1897,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("sub %0, %1");
+# #line 1144 "rl78-decode.opc"
+# ID(sub); DRB(reg); SR(A); Fzac;
+#-
+#+
+# }
+# break;
+# case 0x28:
+#@@ -1921,7 +1921,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("sub %0, %1");
+# #line 1138 "rl78-decode.opc"
+# ID(sub); DR(A); SRB(rba); Fzac;
+#-
+#+
+# }
+# break;
+# case 0x29:
+#@@ -1936,7 +1936,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("subw %0, %ea1");
+# #line 1187 "rl78-decode.opc"
+# ID(sub); W(); DR(AX); SM(HL, IMMU(1)); Fzac;
+#-
+#+
+# }
+# break;
+# case 0x30:
+#@@ -1961,7 +1961,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("subc %0, %1");
+# #line 1173 "rl78-decode.opc"
+# ID(subc); DRB(reg); SR(A); Fzac;
+#-
+#+
+# }
+# break;
+# case 0x38:
+#@@ -1985,7 +1985,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("subc %0, %1");
+# #line 1170 "rl78-decode.opc"
+# ID(subc); DR(A); SRB(rba); Fzac;
+#-
+#+
+# }
+# break;
+# case 0x40:
+#@@ -2010,7 +2010,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("cmp %0, %1");
+# #line 507 "rl78-decode.opc"
+# ID(cmp); DRB(reg); SR(A); Fzac;
+#-
+#+
+# }
+# break;
+# case 0x48:
+#@@ -2034,7 +2034,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("cmp %0, %1");
+# #line 504 "rl78-decode.opc"
+# ID(cmp); DR(A); SRB(rba); Fzac;
+#-
+#+
+# }
+# break;
+# case 0x49:
+#@@ -2049,7 +2049,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("cmpw %0, %ea1");
+# #line 534 "rl78-decode.opc"
+# ID(cmp); W(); DR(AX); SM(HL, IMMU(1)); Fzac;
+#-
+#+
+# }
+# break;
+# case 0x50:
+#@@ -2074,7 +2074,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("and %0, %1");
+# #line 306 "rl78-decode.opc"
+# ID(and); DRB(reg); SR(A); Fz;
+#-
+#+
+# }
+# break;
+# case 0x58:
+#@@ -2098,7 +2098,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("and %0, %1");
+# #line 303 "rl78-decode.opc"
+# ID(and); DR(A); SRB(rba); Fz;
+#-
+#+
+# }
+# break;
+# case 0x59:
+#@@ -2113,7 +2113,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("inc %ea0");
+# #line 584 "rl78-decode.opc"
+# ID(add); DM(HL, IMMU(1)); SC(1); Fza;
+#-
+#+
+# }
+# break;
+# case 0x60:
+#@@ -2138,7 +2138,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("or %0, %1");
+# #line 962 "rl78-decode.opc"
+# ID(or); DRB(reg); SR(A); Fz;
+#-
+#+
+# }
+# break;
+# case 0x68:
+#@@ -2162,7 +2162,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("or %0, %1");
+# #line 959 "rl78-decode.opc"
+# ID(or); DR(A); SRB(rba); Fz;
+#-
+#+
+# }
+# break;
+# case 0x69:
+#@@ -2177,7 +2177,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("dec %ea0");
+# #line 551 "rl78-decode.opc"
+# ID(sub); DM(HL, IMMU(1)); SC(1); Fza;
+#-
+#+
+# }
+# break;
+# case 0x70:
+#@@ -2202,7 +2202,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("xor %0, %1");
+# #line 1266 "rl78-decode.opc"
+# ID(xor); DRB(reg); SR(A); Fz;
+#-
+#+
+# }
+# break;
+# case 0x78:
+#@@ -2226,7 +2226,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("xor %0, %1");
+# #line 1263 "rl78-decode.opc"
+# ID(xor); DR(A); SRB(rba); Fz;
+#-
+#+
+# }
+# break;
+# case 0x79:
+#@@ -2241,7 +2241,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("incw %ea0");
+# #line 598 "rl78-decode.opc"
+# ID(add); W(); DM(HL, IMMU(1)); SC(1);
+#-
+#+
+# }
+# break;
+# case 0x80:
+#@@ -2257,7 +2257,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("add %0, %e1");
+# #line 207 "rl78-decode.opc"
+# ID(add); DR(A); SM2(HL, B, 0); Fzac;
+#-
+#+
+# }
+# break;
+# case 0x82:
+#@@ -2272,7 +2272,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("add %0, %e1");
+# #line 213 "rl78-decode.opc"
+# ID(add); DR(A); SM2(HL, C, 0); Fzac;
+#-
+#+
+# }
+# break;
+# case 0x84:
+#@@ -2324,9 +2324,9 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("callt [%x0]");
+# #line 433 "rl78-decode.opc"
+# ID(call); DM(None, 0x80 + mm*16 + nnn*2);
+#-
+#+
+# /*----------------------------------------------------------------------*/
+#-
+#+
+# }
+# break;
+# case 0x88:
+#@@ -2351,7 +2351,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# #line 1225 "rl78-decode.opc"
+# /* Note: DECW uses reg == X, so this must follow DECW */
+# ID(xch); DR(A); SRB(reg);
+#-
+#+
+# }
+# break;
+# case 0x89:
+#@@ -2366,7 +2366,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("decw %ea0");
+# #line 565 "rl78-decode.opc"
+# ID(sub); W(); DM(HL, IMMU(1)); SC(1);
+#-
+#+
+# }
+# break;
+# case 0x90:
+#@@ -2381,7 +2381,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("addc %0, %e1");
+# #line 239 "rl78-decode.opc"
+# ID(addc); DR(A); SM2(HL, B, 0); Fzac;
+#-
+#+
+# }
+# break;
+# case 0x92:
+#@@ -2396,7 +2396,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("addc %0, %e1");
+# #line 242 "rl78-decode.opc"
+# ID(addc); DR(A); SM2(HL, C, 0); Fzac;
+#-
+#+
+# }
+# break;
+# case 0xa0:
+#@@ -2412,7 +2412,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("sub %0, %e1");
+# #line 1126 "rl78-decode.opc"
+# ID(sub); DR(A); SM2(HL, B, 0); Fzac;
+#-
+#+
+# }
+# break;
+# case 0xa2:
+#@@ -2427,7 +2427,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("sub %0, %e1");
+# #line 1132 "rl78-decode.opc"
+# ID(sub); DR(A); SM2(HL, C, 0); Fzac;
+#-
+#+
+# }
+# break;
+# case 0xa8:
+#@@ -2442,7 +2442,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("xch %0, %1");
+# #line 1229 "rl78-decode.opc"
+# ID(xch); DR(A); SM(None, SADDR);
+#-
+#+
+# }
+# break;
+# case 0xa9:
+#@@ -2457,7 +2457,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("xch %0, %e1");
+# #line 1222 "rl78-decode.opc"
+# ID(xch); DR(A); SM2(HL, C, 0);
+#-
+#+
+# }
+# break;
+# case 0xaa:
+#@@ -2472,7 +2472,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("xch %0, %e!1");
+# #line 1204 "rl78-decode.opc"
+# ID(xch); DR(A); SM(None, IMMU(2));
+#-
+#+
+# }
+# break;
+# case 0xab:
+#@@ -2487,7 +2487,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("xch %0, %1");
+# #line 1232 "rl78-decode.opc"
+# ID(xch); DR(A); SM(None, SFR);
+#-
+#+
+# }
+# break;
+# case 0xac:
+#@@ -2502,7 +2502,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("xch %0, %e1");
+# #line 1213 "rl78-decode.opc"
+# ID(xch); DR(A); SM(HL, 0);
+#-
+#+
+# }
+# break;
+# case 0xad:
+#@@ -2517,7 +2517,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("xch %0, %ea1");
+# #line 1219 "rl78-decode.opc"
+# ID(xch); DR(A); SM(HL, IMMU(1));
+#-
+#+
+# }
+# break;
+# case 0xae:
+#@@ -2532,7 +2532,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("xch %0, %e1");
+# #line 1207 "rl78-decode.opc"
+# ID(xch); DR(A); SM(DE, 0);
+#-
+#+
+# }
+# break;
+# case 0xaf:
+#@@ -2547,7 +2547,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("xch %0, %e1");
+# #line 1210 "rl78-decode.opc"
+# ID(xch); DR(A); SM(DE, IMMU(1));
+#-
+#+
+# }
+# break;
+# case 0xb0:
+#@@ -2562,7 +2562,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("subc %0, %e1");
+# #line 1158 "rl78-decode.opc"
+# ID(subc); DR(A); SM2(HL, B, 0); Fzac;
+#-
+#+
+# }
+# break;
+# case 0xb2:
+#@@ -2577,7 +2577,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("subc %0, %e1");
+# #line 1161 "rl78-decode.opc"
+# ID(subc); DR(A); SM2(HL, C, 0); Fzac;
+#-
+#+
+# }
+# break;
+# case 0xb8:
+#@@ -2591,8 +2591,8 @@ rl78_decode_opcode (unsigned long pc AU,
+# }
+# SYNTAX("mov %0, %1");
+# #line 723 "rl78-decode.opc"
+#- ID(mov); DR(ES); SM(None, SADDR);
+#-
+#+ ID(mov); DR(ES); SM(None, SADDR);
+#+
+# }
+# break;
+# case 0xb9:
+#@@ -2607,7 +2607,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("xch %0, %e1");
+# #line 1216 "rl78-decode.opc"
+# ID(xch); DR(A); SM2(HL, B, 0);
+#-
+#+
+# }
+# break;
+# case 0xc0:
+#@@ -2622,7 +2622,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("cmp %0, %e1");
+# #line 492 "rl78-decode.opc"
+# ID(cmp); DR(A); SM2(HL, B, 0); Fzac;
+#-
+#+
+# }
+# break;
+# case 0xc2:
+#@@ -2637,7 +2637,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("cmp %0, %e1");
+# #line 495 "rl78-decode.opc"
+# ID(cmp); DR(A); SM2(HL, C, 0); Fzac;
+#-
+#+
+# }
+# break;
+# case 0xc3:
+#@@ -2652,7 +2652,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("bh $%a0");
+# #line 340 "rl78-decode.opc"
+# ID(branch_cond); DC(pc+IMMS(1)+3); SR(None); COND(H);
+#-
+#+
+# }
+# break;
+# case 0xc8:
+#@@ -2667,7 +2667,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("sk%c1");
+# #line 1095 "rl78-decode.opc"
+# ID(skip); COND(C);
+#-
+#+
+# }
+# break;
+# case 0xc9:
+#@@ -2682,7 +2682,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("mov %0, %e1");
+# #line 660 "rl78-decode.opc"
+# ID(mov); DR(A); SM2(HL, B, 0);
+#-
+#+
+# }
+# break;
+# case 0xca:
+#@@ -2703,7 +2703,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("call %0");
+# #line 430 "rl78-decode.opc"
+# ID(call); DRW(rg);
+#-
+#+
+# }
+# break;
+# case 0xcb:
+#@@ -2718,9 +2718,9 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("br ax");
+# #line 380 "rl78-decode.opc"
+# ID(branch); DR(AX);
+#-
+#+
+# /*----------------------------------------------------------------------*/
+#-
+#+
+# }
+# break;
+# case 0xcc:
+#@@ -2735,9 +2735,9 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("brk");
+# #line 388 "rl78-decode.opc"
+# ID(break);
+#-
+#+
+# /*----------------------------------------------------------------------*/
+#-
+#+
+# }
+# break;
+# case 0xcd:
+#@@ -2752,9 +2752,9 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("pop %s0");
+# #line 990 "rl78-decode.opc"
+# ID(mov); W(); DR(PSW); SPOP();
+#-
+#+
+# /*----------------------------------------------------------------------*/
+#-
+#+
+# }
+# break;
+# case 0xce:
+#@@ -2769,9 +2769,9 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("movs %ea0, %1");
+# #line 811 "rl78-decode.opc"
+# ID(mov); DM(HL, IMMU(1)); SR(X); Fzc;
+#-
+#+
+# /*----------------------------------------------------------------------*/
+#-
+#+
+# }
+# break;
+# case 0xcf:
+#@@ -2792,9 +2792,9 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("sel rb%1");
+# #line 1042 "rl78-decode.opc"
+# ID(sel); SC(rb);
+#-
+#+
+# /*----------------------------------------------------------------------*/
+#-
+#+
+# }
+# break;
+# case 0xd0:
+#@@ -2809,7 +2809,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("and %0, %e1");
+# #line 291 "rl78-decode.opc"
+# ID(and); DR(A); SM2(HL, B, 0); Fz;
+#-
+#+
+# }
+# break;
+# case 0xd2:
+#@@ -2824,7 +2824,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("and %0, %e1");
+# #line 297 "rl78-decode.opc"
+# ID(and); DR(A); SM2(HL, C, 0); Fz;
+#-
+#+
+# }
+# break;
+# case 0xd3:
+#@@ -2839,7 +2839,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("bnh $%a0");
+# #line 343 "rl78-decode.opc"
+# ID(branch_cond); DC(pc+IMMS(1)+3); SR(None); COND(NH);
+#-
+#+
+# }
+# break;
+# case 0xd8:
+#@@ -2854,7 +2854,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("sk%c1");
+# #line 1101 "rl78-decode.opc"
+# ID(skip); COND(NC);
+#-
+#+
+# }
+# break;
+# case 0xd9:
+#@@ -2869,7 +2869,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("mov %e0, %1");
+# #line 627 "rl78-decode.opc"
+# ID(mov); DM2(HL, B, 0); SR(A);
+#-
+#+
+# }
+# break;
+# case 0xdb:
+#@@ -2884,7 +2884,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("ror %0, %1");
+# #line 1023 "rl78-decode.opc"
+# ID(ror); DR(A); SC(1);
+#-
+#+
+# }
+# break;
+# case 0xdc:
+#@@ -2899,7 +2899,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("rolc %0, %1");
+# #line 1017 "rl78-decode.opc"
+# ID(rolc); DR(A); SC(1);
+#-
+#+
+# }
+# break;
+# case 0xdd:
+#@@ -2914,9 +2914,9 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("push %s1");
+# #line 998 "rl78-decode.opc"
+# ID(mov); W(); DPUSH(); SR(PSW);
+#-
+#+
+# /*----------------------------------------------------------------------*/
+#-
+#+
+# }
+# break;
+# case 0xde:
+#@@ -2931,9 +2931,9 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("cmps %0, %ea1");
+# #line 526 "rl78-decode.opc"
+# ID(cmp); DR(X); SM(HL, IMMU(1)); Fzac;
+#-
+#+
+# /*----------------------------------------------------------------------*/
+#-
+#+
+# }
+# break;
+# case 0xe0:
+#@@ -2948,7 +2948,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("or %0, %e1");
+# #line 947 "rl78-decode.opc"
+# ID(or); DR(A); SM2(HL, B, 0); Fz;
+#-
+#+
+# }
+# break;
+# case 0xe2:
+#@@ -2963,7 +2963,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("or %0, %e1");
+# #line 953 "rl78-decode.opc"
+# ID(or); DR(A); SM2(HL, C, 0); Fz;
+#-
+#+
+# }
+# break;
+# case 0xe3:
+#@@ -2978,7 +2978,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("sk%c1");
+# #line 1098 "rl78-decode.opc"
+# ID(skip); COND(H);
+#-
+#+
+# }
+# break;
+# case 0xe8:
+#@@ -2993,9 +2993,9 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("sk%c1");
+# #line 1110 "rl78-decode.opc"
+# ID(skip); COND(Z);
+#-
+#+
+# /*----------------------------------------------------------------------*/
+#-
+#+
+# }
+# break;
+# case 0xe9:
+#@@ -3010,7 +3010,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("mov %0, %e1");
+# #line 663 "rl78-decode.opc"
+# ID(mov); DR(A); SM2(HL, C, 0);
+#-
+#+
+# }
+# break;
+# case 0xeb:
+#@@ -3025,7 +3025,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("rol %0, %1");
+# #line 1014 "rl78-decode.opc"
+# ID(rol); DR(A); SC(1);
+#-
+#+
+# }
+# break;
+# case 0xec:
+#@@ -3040,9 +3040,9 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("retb");
+# #line 1009 "rl78-decode.opc"
+# ID(reti);
+#-
+#+
+# /*----------------------------------------------------------------------*/
+#-
+#+
+# }
+# break;
+# case 0xed:
+#@@ -3057,9 +3057,9 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("halt");
+# #line 576 "rl78-decode.opc"
+# ID(halt);
+#-
+#+
+# /*----------------------------------------------------------------------*/
+#-
+#+
+# }
+# break;
+# case 0xee:
+#@@ -3078,7 +3078,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("rolwc %0, %1");
+# #line 1020 "rl78-decode.opc"
+# ID(rolc); W(); DRW(r); SC(1);
+#-
+#+
+# }
+# break;
+# case 0xf0:
+#@@ -3093,7 +3093,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("xor %0, %e1");
+# #line 1251 "rl78-decode.opc"
+# ID(xor); DR(A); SM2(HL, B, 0); Fz;
+#-
+#+
+# }
+# break;
+# case 0xf2:
+#@@ -3108,7 +3108,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("xor %0, %e1");
+# #line 1257 "rl78-decode.opc"
+# ID(xor); DR(A); SM2(HL, C, 0); Fz;
+#-
+#+
+# }
+# break;
+# case 0xf3:
+#@@ -3123,7 +3123,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("sk%c1");
+# #line 1104 "rl78-decode.opc"
+# ID(skip); COND(NH);
+#-
+#+
+# }
+# break;
+# case 0xf8:
+#@@ -3138,7 +3138,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("sk%c1");
+# #line 1107 "rl78-decode.opc"
+# ID(skip); COND(NZ);
+#-
+#+
+# }
+# break;
+# case 0xf9:
+#@@ -3153,7 +3153,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("mov %e0, %1");
+# #line 636 "rl78-decode.opc"
+# ID(mov); DM2(HL, C, 0); SR(A);
+#-
+#+
+# }
+# break;
+# case 0xfb:
+#@@ -3168,12 +3168,12 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("rorc %0, %1");
+# #line 1026 "rl78-decode.opc"
+# ID(rorc); DR(A); SC(1);
+#-
+#+
+# /*----------------------------------------------------------------------*/
+#-
+#+
+# /* Note that the branch insns need to be listed before the shift
+# ones, as "shift count of zero" means "branch insn" */
+#-
+#+
+# }
+# break;
+# case 0xfc:
+#@@ -3188,7 +3188,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("reti");
+# #line 1006 "rl78-decode.opc"
+# ID(reti);
+#-
+#+
+# }
+# break;
+# case 0xfd:
+#@@ -3203,9 +3203,9 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("stop");
+# #line 1115 "rl78-decode.opc"
+# ID(stop);
+#-
+#+
+# /*----------------------------------------------------------------------*/
+#-
+#+
+# }
+# break;
+# default: UNSUPPORTED(); break;
+#@@ -3223,7 +3223,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("movw %e0, %1");
+# #line 874 "rl78-decode.opc"
+# ID(mov); W(); DM(C, IMMU(2)); SR(AX);
+#-
+#+
+# }
+# break;
+# case 0x69:
+#@@ -3238,7 +3238,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("movw %0, %e1");
+# #line 865 "rl78-decode.opc"
+# ID(mov); W(); DR(AX); SM(C, IMMU(2));
+#-
+#+
+# }
+# break;
+# case 0x6a:
+#@@ -3253,9 +3253,9 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("or %0, #%1");
+# #line 968 "rl78-decode.opc"
+# ID(or); DM(None, SADDR); SC(IMMU(1)); Fz;
+#-
+#+
+# /*----------------------------------------------------------------------*/
+#-
+#+
+# }
+# break;
+# case 0x6b:
+#@@ -3270,7 +3270,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("or %0, %1");
+# #line 965 "rl78-decode.opc"
+# ID(or); DR(A); SM(None, SADDR); Fz;
+#-
+#+
+# }
+# break;
+# case 0x6c:
+#@@ -3285,7 +3285,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("or %0, #%1");
+# #line 956 "rl78-decode.opc"
+# ID(or); DR(A); SC(IMMU(1)); Fz;
+#-
+#+
+# }
+# break;
+# case 0x6d:
+#@@ -3300,7 +3300,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("or %0, %e1");
+# #line 944 "rl78-decode.opc"
+# ID(or); DR(A); SM(HL, 0); Fz;
+#-
+#+
+# }
+# break;
+# case 0x6e:
+#@@ -3315,7 +3315,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("or %0, %ea1");
+# #line 950 "rl78-decode.opc"
+# ID(or); DR(A); SM(HL, IMMU(1)); Fz;
+#-
+#+
+# }
+# break;
+# case 0x6f:
+#@@ -3330,7 +3330,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("or %0, %e!1");
+# #line 941 "rl78-decode.opc"
+# ID(or); DR(A); SM(None, IMMU(2)); Fz;
+#-
+#+
+# }
+# break;
+# case 0x70:
+#@@ -3354,7 +3354,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("mov %0, %1");
+# #line 696 "rl78-decode.opc"
+# ID(mov); DRB(rba); SR(A);
+#-
+#+
+# }
+# break;
+# case 0x71:
+#@@ -3383,7 +3383,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("set1 %e!0");
+# #line 1047 "rl78-decode.opc"
+# ID(mov); DM(None, IMMU(2)); DB(bit); SC(1);
+#-
+#+
+# }
+# break;
+# case 0x01:
+#@@ -3408,7 +3408,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("mov1 %0, cy");
+# #line 803 "rl78-decode.opc"
+# ID(mov); DM(None, SADDR); DB(bit); SCY();
+#-
+#+
+# }
+# break;
+# case 0x02:
+#@@ -3433,9 +3433,9 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("set1 %0");
+# #line 1065 "rl78-decode.opc"
+# ID(mov); DM(None, SADDR); DB(bit); SC(1);
+#-
+#+
+# /*----------------------------------------------------------------------*/
+#-
+#+
+# }
+# break;
+# case 0x03:
+#@@ -3460,9 +3460,9 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("clr1 %0");
+# #line 456 "rl78-decode.opc"
+# ID(mov); DM(None, SADDR); DB(bit); SC(0);
+#-
+#+
+# /*----------------------------------------------------------------------*/
+#-
+#+
+# }
+# break;
+# case 0x04:
+#@@ -3487,7 +3487,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("mov1 cy, %1");
+# #line 797 "rl78-decode.opc"
+# ID(mov); DCY(); SM(None, SADDR); SB(bit);
+#-
+#+
+# }
+# break;
+# case 0x05:
+#@@ -3512,12 +3512,12 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("and1 cy, %s1");
+# #line 326 "rl78-decode.opc"
+# ID(and); DCY(); SM(None, SADDR); SB(bit);
+#-
+#+
+# /*----------------------------------------------------------------------*/
+#-
+#+
+# /* Note that the branch insns need to be listed before the shift
+# ones, as "shift count of zero" means "branch insn" */
+#-
+#+
+# }
+# break;
+# case 0x06:
+#@@ -3542,9 +3542,9 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("or1 cy, %s1");
+# #line 982 "rl78-decode.opc"
+# ID(or); DCY(); SM(None, SADDR); SB(bit);
+#-
+#+
+# /*----------------------------------------------------------------------*/
+#-
+#+
+# }
+# break;
+# case 0x07:
+#@@ -3569,9 +3569,9 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("xor1 cy, %s1");
+# #line 1286 "rl78-decode.opc"
+# ID(xor); DCY(); SM(None, SADDR); SB(bit);
+#-
+#+
+# /*----------------------------------------------------------------------*/
+#-
+#+
+# }
+# break;
+# case 0x08:
+#@@ -3596,7 +3596,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("clr1 %e!0");
+# #line 438 "rl78-decode.opc"
+# ID(mov); DM(None, IMMU(2)); DB(bit); SC(0);
+#-
+#+
+# }
+# break;
+# case 0x09:
+#@@ -3621,9 +3621,9 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("mov1 %s0, cy");
+# #line 806 "rl78-decode.opc"
+# ID(mov); DM(None, SFR); DB(bit); SCY();
+#-
+#+
+# /*----------------------------------------------------------------------*/
+#-
+#+
+# }
+# break;
+# case 0x0a:
+#@@ -3651,7 +3651,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# ID(mov); DM(None, op0); DB(bit); SC(1);
+# if (op0 == RL78_SFR_PSW && bit == 7)
+# rl78->syntax = "ei";
+#-
+#+
+# }
+# break;
+# case 0x0b:
+#@@ -3679,7 +3679,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# ID(mov); DM(None, op0); DB(bit); SC(0);
+# if (op0 == RL78_SFR_PSW && bit == 7)
+# rl78->syntax = "di";
+#-
+#+
+# }
+# break;
+# case 0x0c:
+#@@ -3704,7 +3704,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("mov1 cy, %s1");
+# #line 800 "rl78-decode.opc"
+# ID(mov); DCY(); SM(None, SFR); SB(bit);
+#-
+#+
+# }
+# break;
+# case 0x0d:
+#@@ -3729,7 +3729,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("and1 cy, %s1");
+# #line 323 "rl78-decode.opc"
+# ID(and); DCY(); SM(None, SFR); SB(bit);
+#-
+#+
+# }
+# break;
+# case 0x0e:
+#@@ -3754,7 +3754,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("or1 cy, %s1");
+# #line 979 "rl78-decode.opc"
+# ID(or); DCY(); SM(None, SFR); SB(bit);
+#-
+#+
+# }
+# break;
+# case 0x0f:
+#@@ -3779,7 +3779,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("xor1 cy, %s1");
+# #line 1283 "rl78-decode.opc"
+# ID(xor); DCY(); SM(None, SFR); SB(bit);
+#-
+#+
+# }
+# break;
+# case 0x80:
+#@@ -3794,7 +3794,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("set1 cy");
+# #line 1056 "rl78-decode.opc"
+# ID(mov); DCY(); SC(1);
+#-
+#+
+# }
+# break;
+# case 0x81:
+#@@ -3819,7 +3819,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("mov1 %e0, cy");
+# #line 785 "rl78-decode.opc"
+# ID(mov); DM(HL, 0); DB(bit); SCY();
+#-
+#+
+# }
+# break;
+# case 0x82:
+#@@ -3844,7 +3844,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("set1 %e0");
+# #line 1050 "rl78-decode.opc"
+# ID(mov); DM(HL, 0); DB(bit); SC(1);
+#-
+#+
+# }
+# break;
+# case 0x83:
+#@@ -3869,7 +3869,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("clr1 %e0");
+# #line 441 "rl78-decode.opc"
+# ID(mov); DM(HL, 0); DB(bit); SC(0);
+#-
+#+
+# }
+# break;
+# case 0x84:
+#@@ -3894,7 +3894,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("mov1 cy, %e1");
+# #line 791 "rl78-decode.opc"
+# ID(mov); DCY(); SM(HL, 0); SB(bit);
+#-
+#+
+# }
+# break;
+# case 0x85:
+#@@ -3919,7 +3919,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("and1 cy, %e1");
+# #line 317 "rl78-decode.opc"
+# ID(and); DCY(); SM(HL, 0); SB(bit);
+#-
+#+
+# }
+# break;
+# case 0x86:
+#@@ -3944,7 +3944,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("or1 cy, %e1");
+# #line 973 "rl78-decode.opc"
+# ID(or); DCY(); SM(HL, 0); SB(bit);
+#-
+#+
+# }
+# break;
+# case 0x87:
+#@@ -3969,7 +3969,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("xor1 cy, %e1");
+# #line 1277 "rl78-decode.opc"
+# ID(xor); DCY(); SM(HL, 0); SB(bit);
+#-
+#+
+# }
+# break;
+# case 0x88:
+#@@ -3984,7 +3984,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("clr1 cy");
+# #line 447 "rl78-decode.opc"
+# ID(mov); DCY(); SC(0);
+#-
+#+
+# }
+# break;
+# case 0x89:
+#@@ -4009,7 +4009,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("mov1 %e0, cy");
+# #line 788 "rl78-decode.opc"
+# ID(mov); DR(A); DB(bit); SCY();
+#-
+#+
+# }
+# break;
+# case 0x8a:
+#@@ -4034,7 +4034,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("set1 %0");
+# #line 1053 "rl78-decode.opc"
+# ID(mov); DR(A); DB(bit); SC(1);
+#-
+#+
+# }
+# break;
+# case 0x8b:
+#@@ -4059,7 +4059,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("clr1 %0");
+# #line 444 "rl78-decode.opc"
+# ID(mov); DR(A); DB(bit); SC(0);
+#-
+#+
+# }
+# break;
+# case 0x8c:
+#@@ -4084,7 +4084,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("mov1 cy, %e1");
+# #line 794 "rl78-decode.opc"
+# ID(mov); DCY(); SR(A); SB(bit);
+#-
+#+
+# }
+# break;
+# case 0x8d:
+#@@ -4109,7 +4109,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("and1 cy, %1");
+# #line 320 "rl78-decode.opc"
+# ID(and); DCY(); SR(A); SB(bit);
+#-
+#+
+# }
+# break;
+# case 0x8e:
+#@@ -4134,7 +4134,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("or1 cy, %1");
+# #line 976 "rl78-decode.opc"
+# ID(or); DCY(); SR(A); SB(bit);
+#-
+#+
+# }
+# break;
+# case 0x8f:
+#@@ -4159,7 +4159,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("xor1 cy, %1");
+# #line 1280 "rl78-decode.opc"
+# ID(xor); DCY(); SR(A); SB(bit);
+#-
+#+
+# }
+# break;
+# case 0xc0:
+#@@ -4174,9 +4174,9 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("not1 cy");
+# #line 917 "rl78-decode.opc"
+# ID(xor); DCY(); SC(1);
+#-
+#+
+# /*----------------------------------------------------------------------*/
+#-
+#+
+# }
+# break;
+# default: UNSUPPORTED(); break;
+#@@ -4194,7 +4194,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("movw %e0, %1");
+# #line 877 "rl78-decode.opc"
+# ID(mov); W(); DM(BC, IMMU(2)); SR(AX);
+#-
+#+
+# }
+# break;
+# case 0x79:
+#@@ -4209,7 +4209,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("movw %0, %e1");
+# #line 868 "rl78-decode.opc"
+# ID(mov); W(); DR(AX); SM(BC, IMMU(2));
+#-
+#+
+# }
+# break;
+# case 0x7a:
+#@@ -4224,9 +4224,9 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("xor %0, #%1");
+# #line 1272 "rl78-decode.opc"
+# ID(xor); DM(None, SADDR); SC(IMMU(1)); Fz;
+#-
+#+
+# /*----------------------------------------------------------------------*/
+#-
+#+
+# }
+# break;
+# case 0x7b:
+#@@ -4241,7 +4241,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("xor %0, %1");
+# #line 1269 "rl78-decode.opc"
+# ID(xor); DR(A); SM(None, SADDR); Fz;
+#-
+#+
+# }
+# break;
+# case 0x7c:
+#@@ -4256,7 +4256,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("xor %0, #%1");
+# #line 1260 "rl78-decode.opc"
+# ID(xor); DR(A); SC(IMMU(1)); Fz;
+#-
+#+
+# }
+# break;
+# case 0x7d:
+#@@ -4271,7 +4271,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("xor %0, %e1");
+# #line 1248 "rl78-decode.opc"
+# ID(xor); DR(A); SM(HL, 0); Fz;
+#-
+#+
+# }
+# break;
+# case 0x7e:
+#@@ -4286,7 +4286,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("xor %0, %ea1");
+# #line 1254 "rl78-decode.opc"
+# ID(xor); DR(A); SM(HL, IMMU(1)); Fz;
+#-
+#+
+# }
+# break;
+# case 0x7f:
+#@@ -4301,7 +4301,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("xor %0, %e!1");
+# #line 1245 "rl78-decode.opc"
+# ID(xor); DR(A); SM(None, IMMU(2)); Fz;
+#-
+#+
+# }
+# break;
+# case 0x80:
+#@@ -4326,7 +4326,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("inc %0");
+# #line 587 "rl78-decode.opc"
+# ID(add); DRB(reg); SC(1); Fza;
+#-
+#+
+# }
+# break;
+# case 0x88:
+#@@ -4341,7 +4341,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("mov %0, %e1");
+# #line 666 "rl78-decode.opc"
+# ID(mov); DR(A); SM(SP, IMMU(1));
+#-
+#+
+# }
+# break;
+# case 0x89:
+#@@ -4356,7 +4356,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("mov %0, %e1");
+# #line 648 "rl78-decode.opc"
+# ID(mov); DR(A); SM(DE, 0);
+#-
+#+
+# }
+# break;
+# case 0x8a:
+#@@ -4371,7 +4371,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("mov %0, %e1");
+# #line 651 "rl78-decode.opc"
+# ID(mov); DR(A); SM(DE, IMMU(1));
+#-
+#+
+# }
+# break;
+# case 0x8b:
+#@@ -4386,7 +4386,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("mov %0, %e1");
+# #line 654 "rl78-decode.opc"
+# ID(mov); DR(A); SM(HL, 0);
+#-
+#+
+# }
+# break;
+# case 0x8c:
+#@@ -4401,7 +4401,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("mov %0, %ea1");
+# #line 657 "rl78-decode.opc"
+# ID(mov); DR(A); SM(HL, IMMU(1));
+#-
+#+
+# }
+# break;
+# case 0x8d:
+#@@ -4416,7 +4416,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("mov %0, %1");
+# #line 690 "rl78-decode.opc"
+# ID(mov); DR(A); SM(None, SADDR);
+#-
+#+
+# }
+# break;
+# case 0x8e:
+#@@ -4431,7 +4431,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("mov %0, %s1");
+# #line 687 "rl78-decode.opc"
+# ID(mov); DR(A); SM(None, SFR);
+#-
+#+
+# }
+# break;
+# case 0x8f:
+#@@ -4446,7 +4446,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("mov %0, %e!1");
+# #line 645 "rl78-decode.opc"
+# ID(mov); DR(A); SM(None, IMMU(2));
+#-
+#+
+# }
+# break;
+# case 0x90:
+#@@ -4471,7 +4471,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("dec %0");
+# #line 554 "rl78-decode.opc"
+# ID(sub); DRB(reg); SC(1); Fza;
+#-
+#+
+# }
+# break;
+# case 0x98:
+#@@ -4486,7 +4486,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("mov %0, %1");
+# #line 642 "rl78-decode.opc"
+# ID(mov); DM(SP, IMMU(1)); SR(A);
+#-
+#+
+# }
+# break;
+# case 0x99:
+#@@ -4501,7 +4501,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("mov %e0, %1");
+# #line 615 "rl78-decode.opc"
+# ID(mov); DM(DE, 0); SR(A);
+#-
+#+
+# }
+# break;
+# case 0x9a:
+#@@ -4516,7 +4516,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("mov %e0, %1");
+# #line 621 "rl78-decode.opc"
+# ID(mov); DM(DE, IMMU(1)); SR(A);
+#-
+#+
+# }
+# break;
+# case 0x9b:
+#@@ -4531,7 +4531,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("mov %e0, %1");
+# #line 624 "rl78-decode.opc"
+# ID(mov); DM(HL, 0); SR(A);
+#-
+#+
+# }
+# break;
+# case 0x9c:
+#@@ -4546,7 +4546,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("mov %ea0, %1");
+# #line 633 "rl78-decode.opc"
+# ID(mov); DM(HL, IMMU(1)); SR(A);
+#-
+#+
+# }
+# break;
+# case 0x9d:
+#@@ -4561,7 +4561,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("mov %0, %1");
+# #line 747 "rl78-decode.opc"
+# ID(mov); DM(None, SADDR); SR(A);
+#-
+#+
+# }
+# break;
+# case 0x9e:
+#@@ -4576,9 +4576,9 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("mov %0, %1");
+# #line 780 "rl78-decode.opc"
+# ID(mov); DM(None, SFR); SR(A);
+#-
+#+
+# /*----------------------------------------------------------------------*/
+#-
+#+
+# }
+# break;
+# case 0x9f:
+#@@ -4593,7 +4593,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("mov %e!0, %1");
+# #line 612 "rl78-decode.opc"
+# ID(mov); DM(None, IMMU(2)); SR(A);
+#-
+#+
+# }
+# break;
+# case 0xa0:
+#@@ -4608,7 +4608,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("inc %e!0");
+# #line 581 "rl78-decode.opc"
+# ID(add); DM(None, IMMU(2)); SC(1); Fza;
+#-
+#+
+# }
+# break;
+# case 0xa1:
+#@@ -4629,7 +4629,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("incw %0");
+# #line 601 "rl78-decode.opc"
+# ID(add); W(); DRW(rg); SC(1);
+#-
+#+
+# }
+# break;
+# case 0xa2:
+#@@ -4644,7 +4644,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("incw %e!0");
+# #line 595 "rl78-decode.opc"
+# ID(add); W(); DM(None, IMMU(2)); SC(1);
+#-
+#+
+# }
+# break;
+# case 0xa4:
+#@@ -4659,9 +4659,9 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("inc %0");
+# #line 590 "rl78-decode.opc"
+# ID(add); DM(None, SADDR); SC(1); Fza;
+#-
+#+
+# /*----------------------------------------------------------------------*/
+#-
+#+
+# }
+# break;
+# case 0xa6:
+#@@ -4676,9 +4676,9 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("incw %0");
+# #line 604 "rl78-decode.opc"
+# ID(add); W(); DM(None, SADDR); SC(1);
+#-
+#+
+# /*----------------------------------------------------------------------*/
+#-
+#+
+# }
+# break;
+# case 0xa8:
+#@@ -4693,7 +4693,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("movw %0, %1");
+# #line 850 "rl78-decode.opc"
+# ID(mov); W(); DR(AX); SM(SP, IMMU(1));
+#-
+#+
+# }
+# break;
+# case 0xa9:
+#@@ -4708,7 +4708,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("movw %0, %e1");
+# #line 838 "rl78-decode.opc"
+# ID(mov); W(); DR(AX); SM(DE, 0);
+#-
+#+
+# }
+# break;
+# case 0xaa:
+#@@ -4723,7 +4723,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("movw %0, %e1");
+# #line 841 "rl78-decode.opc"
+# ID(mov); W(); DR(AX); SM(DE, IMMU(1));
+#-
+#+
+# }
+# break;
+# case 0xab:
+#@@ -4738,7 +4738,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("movw %0, %e1");
+# #line 844 "rl78-decode.opc"
+# ID(mov); W(); DR(AX); SM(HL, 0);
+#-
+#+
+# }
+# break;
+# case 0xac:
+#@@ -4753,7 +4753,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("movw %0, %ea1");
+# #line 847 "rl78-decode.opc"
+# ID(mov); W(); DR(AX); SM(HL, IMMU(1));
+#-
+#+
+# }
+# break;
+# case 0xad:
+#@@ -4768,7 +4768,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("movw %0, %1");
+# #line 880 "rl78-decode.opc"
+# ID(mov); W(); DR(AX); SM(None, SADDR);
+#-
+#+
+# }
+# break;
+# case 0xae:
+#@@ -4783,7 +4783,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("movw %0, %s1");
+# #line 883 "rl78-decode.opc"
+# ID(mov); W(); DR(AX); SM(None, SFR);
+#-
+#+
+# }
+# break;
+# case 0xaf:
+#@@ -4798,8 +4798,8 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("movw %0, %e!1");
+# #line 834 "rl78-decode.opc"
+# ID(mov); W(); DR(AX); SM(None, IMMU(2));
+#-
+#-
+#+
+#+
+# }
+# break;
+# case 0xb0:
+#@@ -4814,7 +4814,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("dec %e!0");
+# #line 548 "rl78-decode.opc"
+# ID(sub); DM(None, IMMU(2)); SC(1); Fza;
+#-
+#+
+# }
+# break;
+# case 0xb1:
+#@@ -4835,7 +4835,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("decw %0");
+# #line 568 "rl78-decode.opc"
+# ID(sub); W(); DRW(rg); SC(1);
+#-
+#+
+# }
+# break;
+# case 0xb2:
+#@@ -4850,7 +4850,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("decw %e!0");
+# #line 562 "rl78-decode.opc"
+# ID(sub); W(); DM(None, IMMU(2)); SC(1);
+#-
+#+
+# }
+# break;
+# case 0xb4:
+#@@ -4865,9 +4865,9 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("dec %0");
+# #line 557 "rl78-decode.opc"
+# ID(sub); DM(None, SADDR); SC(1); Fza;
+#-
+#+
+# /*----------------------------------------------------------------------*/
+#-
+#+
+# }
+# break;
+# case 0xb6:
+#@@ -4882,9 +4882,9 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("decw %0");
+# #line 571 "rl78-decode.opc"
+# ID(sub); W(); DM(None, SADDR); SC(1);
+#-
+#+
+# /*----------------------------------------------------------------------*/
+#-
+#+
+# }
+# break;
+# case 0xb8:
+#@@ -4899,7 +4899,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("movw %0, %1");
+# #line 831 "rl78-decode.opc"
+# ID(mov); W(); DM(SP, IMMU(1)); SR(AX);
+#-
+#+
+# }
+# break;
+# case 0xb9:
+#@@ -4914,7 +4914,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("movw %e0, %1");
+# #line 819 "rl78-decode.opc"
+# ID(mov); W(); DM(DE, 0); SR(AX);
+#-
+#+
+# }
+# break;
+# case 0xba:
+#@@ -4929,7 +4929,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("movw %e0, %1");
+# #line 822 "rl78-decode.opc"
+# ID(mov); W(); DM(DE, IMMU(1)); SR(AX);
+#-
+#+
+# }
+# break;
+# case 0xbb:
+#@@ -4944,7 +4944,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("movw %e0, %1");
+# #line 825 "rl78-decode.opc"
+# ID(mov); W(); DM(HL, 0); SR(AX);
+#-
+#+
+# }
+# break;
+# case 0xbc:
+#@@ -4959,7 +4959,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("movw %ea0, %1");
+# #line 828 "rl78-decode.opc"
+# ID(mov); W(); DM(HL, IMMU(1)); SR(AX);
+#-
+#+
+# }
+# break;
+# case 0xbd:
+#@@ -4974,7 +4974,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("movw %0, %1");
+# #line 895 "rl78-decode.opc"
+# ID(mov); W(); DM(None, SADDR); SR(AX);
+#-
+#+
+# }
+# break;
+# case 0xbe:
+#@@ -4989,9 +4989,9 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("movw %0, %1");
+# #line 901 "rl78-decode.opc"
+# ID(mov); W(); DM(None, SFR); SR(AX);
+#-
+#+
+# /*----------------------------------------------------------------------*/
+#-
+#+
+# }
+# break;
+# case 0xbf:
+#@@ -5006,7 +5006,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("movw %e!0, %1");
+# #line 816 "rl78-decode.opc"
+# ID(mov); W(); DM(None, IMMU(2)); SR(AX);
+#-
+#+
+# }
+# break;
+# case 0xc0:
+#@@ -5027,7 +5027,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("pop %0");
+# #line 987 "rl78-decode.opc"
+# ID(mov); W(); DRW(rg); SPOP();
+#-
+#+
+# }
+# break;
+# case 0xc1:
+#@@ -5048,7 +5048,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("push %1");
+# #line 995 "rl78-decode.opc"
+# ID(mov); W(); DPUSH(); SRW(rg);
+#-
+#+
+# }
+# break;
+# case 0xc8:
+#@@ -5063,7 +5063,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("mov %0, #%1");
+# #line 639 "rl78-decode.opc"
+# ID(mov); DM(SP, IMMU(1)); SC(IMMU(1));
+#-
+#+
+# }
+# break;
+# case 0xc9:
+#@@ -5078,7 +5078,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("movw %0, #%1");
+# #line 892 "rl78-decode.opc"
+# ID(mov); W(); DM(None, SADDR); SC(IMMU(2));
+#-
+#+
+# }
+# break;
+# case 0xca:
+#@@ -5093,7 +5093,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("mov %e0, #%1");
+# #line 618 "rl78-decode.opc"
+# ID(mov); DM(DE, IMMU(1)); SC(IMMU(1));
+#-
+#+
+# }
+# break;
+# case 0xcb:
+#@@ -5108,7 +5108,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("movw %0, #%1");
+# #line 898 "rl78-decode.opc"
+# ID(mov); W(); DM(None, SFR); SC(IMMU(2));
+#-
+#+
+# }
+# break;
+# case 0xcc:
+#@@ -5123,7 +5123,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("mov %ea0, #%1");
+# #line 630 "rl78-decode.opc"
+# ID(mov); DM(HL, IMMU(1)); SC(IMMU(1));
+#-
+#+
+# }
+# break;
+# case 0xcd:
+#@@ -5138,7 +5138,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("mov %0, #%1");
+# #line 744 "rl78-decode.opc"
+# ID(mov); DM(None, SADDR); SC(IMMU(1));
+#-
+#+
+# }
+# break;
+# case 0xce:
+#@@ -5180,7 +5180,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# rl78->syntax = "divwu"; ID(divwu);
+# break;
+# }
+#-
+#+
+# }
+# break;
+# case 0xcf:
+#@@ -5195,7 +5195,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("mov %e!0, #%1");
+# #line 609 "rl78-decode.opc"
+# ID(mov); DM(None, IMMU(2)); SC(IMMU(1));
+#-
+#+
+# }
+# break;
+# case 0xd0:
+#@@ -5216,7 +5216,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("cmp0 %0");
+# #line 518 "rl78-decode.opc"
+# ID(cmp); DRB(rg); SC(0); Fzac;
+#-
+#+
+# }
+# break;
+# case 0xd4:
+#@@ -5231,9 +5231,9 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("cmp0 %0");
+# #line 521 "rl78-decode.opc"
+# ID(cmp); DM(None, SADDR); SC(0); Fzac;
+#-
+#+
+# /*----------------------------------------------------------------------*/
+#-
+#+
+# }
+# break;
+# case 0xd5:
+#@@ -5248,7 +5248,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("cmp0 %e!0");
+# #line 515 "rl78-decode.opc"
+# ID(cmp); DM(None, IMMU(2)); SC(0); Fzac;
+#-
+#+
+# }
+# break;
+# case 0xd6:
+#@@ -5264,9 +5264,9 @@ rl78_decode_opcode (unsigned long pc AU,
+# #line 906 "rl78-decode.opc"
+# if (isa == RL78_ISA_G14)
+# ID(mulu);
+#-
+#+
+# /*----------------------------------------------------------------------*/
+#-
+#+
+# }
+# break;
+# case 0xd7:
+#@@ -5281,7 +5281,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("ret");
+# #line 1003 "rl78-decode.opc"
+# ID(ret);
+#-
+#+
+# }
+# break;
+# case 0xd8:
+#@@ -5296,7 +5296,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("mov %0, %1");
+# #line 711 "rl78-decode.opc"
+# ID(mov); DR(X); SM(None, SADDR);
+#-
+#+
+# }
+# break;
+# case 0xd9:
+#@@ -5311,7 +5311,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("mov %0, %e!1");
+# #line 708 "rl78-decode.opc"
+# ID(mov); DR(X); SM(None, IMMU(2));
+#-
+#+
+# }
+# break;
+# case 0xda:
+#@@ -5331,7 +5331,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("movw %0, %1");
+# #line 889 "rl78-decode.opc"
+# ID(mov); W(); DRW(ra); SM(None, SADDR);
+#-
+#+
+# }
+# break;
+# case 0xdb:
+#@@ -5351,7 +5351,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("movw %0, %e!1");
+# #line 886 "rl78-decode.opc"
+# ID(mov); W(); DRW(ra); SM(None, IMMU(2));
+#-
+#+
+# }
+# break;
+# case 0xdc:
+#@@ -5366,7 +5366,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("bc $%a0");
+# #line 334 "rl78-decode.opc"
+# ID(branch_cond); DC(pc+IMMS(1)+2); SR(None); COND(C);
+#-
+#+
+# }
+# break;
+# case 0xdd:
+#@@ -5381,7 +5381,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("bz $%a0");
+# #line 346 "rl78-decode.opc"
+# ID(branch_cond); DC(pc+IMMS(1)+2); SR(None); COND(Z);
+#-
+#+
+# }
+# break;
+# case 0xde:
+#@@ -5396,7 +5396,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("bnc $%a0");
+# #line 337 "rl78-decode.opc"
+# ID(branch_cond); DC(pc+IMMS(1)+2); SR(None); COND(NC);
+#-
+#+
+# }
+# break;
+# case 0xdf:
+#@@ -5411,9 +5411,9 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("bnz $%a0");
+# #line 349 "rl78-decode.opc"
+# ID(branch_cond); DC(pc+IMMS(1)+2); SR(None); COND(NZ);
+#-
+#+
+# /*----------------------------------------------------------------------*/
+#-
+#+
+# }
+# break;
+# case 0xe0:
+#@@ -5434,7 +5434,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("oneb %0");
+# #line 925 "rl78-decode.opc"
+# ID(mov); DRB(rg); SC(1);
+#-
+#+
+# }
+# break;
+# case 0xe4:
+#@@ -5449,9 +5449,9 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("oneb %0");
+# #line 928 "rl78-decode.opc"
+# ID(mov); DM(None, SADDR); SC(1);
+#-
+#+
+# /*----------------------------------------------------------------------*/
+#-
+#+
+# }
+# break;
+# case 0xe5:
+#@@ -5466,7 +5466,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("oneb %e!0");
+# #line 922 "rl78-decode.opc"
+# ID(mov); DM(None, IMMU(2)); SC(1);
+#-
+#+
+# }
+# break;
+# case 0xe6:
+#@@ -5481,7 +5481,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("onew %0");
+# #line 933 "rl78-decode.opc"
+# ID(mov); DR(AX); SC(1);
+#-
+#+
+# }
+# break;
+# case 0xe7:
+#@@ -5496,9 +5496,9 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("onew %0");
+# #line 936 "rl78-decode.opc"
+# ID(mov); DR(BC); SC(1);
+#-
+#+
+# /*----------------------------------------------------------------------*/
+#-
+#+
+# }
+# break;
+# case 0xe8:
+#@@ -5513,7 +5513,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("mov %0, %1");
+# #line 699 "rl78-decode.opc"
+# ID(mov); DR(B); SM(None, SADDR);
+#-
+#+
+# }
+# break;
+# case 0xe9:
+#@@ -5528,7 +5528,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("mov %0, %e!1");
+# #line 693 "rl78-decode.opc"
+# ID(mov); DR(B); SM(None, IMMU(2));
+#-
+#+
+# }
+# break;
+# case 0xec:
+#@@ -5543,7 +5543,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("br !%!a0");
+# #line 368 "rl78-decode.opc"
+# ID(branch); DC(IMMU(3));
+#-
+#+
+# }
+# break;
+# case 0xed:
+#@@ -5558,7 +5558,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("br %!a0");
+# #line 371 "rl78-decode.opc"
+# ID(branch); DC(IMMU(2));
+#-
+#+
+# }
+# break;
+# case 0xee:
+#@@ -5573,7 +5573,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("br $%!a0");
+# #line 374 "rl78-decode.opc"
+# ID(branch); DC(pc+IMMS(2)+3);
+#-
+#+
+# }
+# break;
+# case 0xef:
+#@@ -5588,7 +5588,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("br $%a0");
+# #line 377 "rl78-decode.opc"
+# ID(branch); DC(pc+IMMS(1)+2);
+#-
+#+
+# }
+# break;
+# case 0xf0:
+#@@ -5609,7 +5609,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("clrb %0");
+# #line 464 "rl78-decode.opc"
+# ID(mov); DRB(rg); SC(0);
+#-
+#+
+# }
+# break;
+# case 0xf4:
+#@@ -5624,9 +5624,9 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("clrb %0");
+# #line 467 "rl78-decode.opc"
+# ID(mov); DM(None, SADDR); SC(0);
+#-
+#+
+# /*----------------------------------------------------------------------*/
+#-
+#+
+# }
+# break;
+# case 0xf5:
+#@@ -5641,7 +5641,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("clrb %e!0");
+# #line 461 "rl78-decode.opc"
+# ID(mov); DM(None, IMMU(2)); SC(0);
+#-
+#+
+# }
+# break;
+# case 0xf6:
+#@@ -5656,7 +5656,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("clrw %0");
+# #line 472 "rl78-decode.opc"
+# ID(mov); DR(AX); SC(0);
+#-
+#+
+# }
+# break;
+# case 0xf7:
+#@@ -5671,9 +5671,9 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("clrw %0");
+# #line 475 "rl78-decode.opc"
+# ID(mov); DR(BC); SC(0);
+#-
+#+
+# /*----------------------------------------------------------------------*/
+#-
+#+
+# }
+# break;
+# case 0xf8:
+#@@ -5688,7 +5688,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("mov %0, %1");
+# #line 705 "rl78-decode.opc"
+# ID(mov); DR(C); SM(None, SADDR);
+#-
+#+
+# }
+# break;
+# case 0xf9:
+#@@ -5703,7 +5703,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("mov %0, %e!1");
+# #line 702 "rl78-decode.opc"
+# ID(mov); DR(C); SM(None, IMMU(2));
+#-
+#+
+# }
+# break;
+# case 0xfc:
+#@@ -5718,7 +5718,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("call !%!a0");
+# #line 421 "rl78-decode.opc"
+# ID(call); DC(IMMU(3));
+#-
+#+
+# }
+# break;
+# case 0xfd:
+#@@ -5733,7 +5733,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("call %!a0");
+# #line 424 "rl78-decode.opc"
+# ID(call); DC(IMMU(2));
+#-
+#+
+# }
+# break;
+# case 0xfe:
+#@@ -5748,7 +5748,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("call $%!a0");
+# #line 427 "rl78-decode.opc"
+# ID(call); DC(pc+IMMS(2)+3);
+#-
+#+
+# }
+# break;
+# case 0xff:
+#@@ -5763,7 +5763,7 @@ rl78_decode_opcode (unsigned long pc AU,
+# SYNTAX("brk1");
+# #line 385 "rl78-decode.opc"
+# ID(break);
+#-
+#+
+# }
+# break;
+# }
+#--- a/opcodes/rl78-decode.opc
+#+++ b/opcodes/rl78-decode.opc
+#@@ -208,7 +208,7 @@ rl78_decode_opcode (unsigned long pc AU,
+#
+# /** 0000 1110 add %0, %ea1 */
+# ID(add); DR(A); SM(HL, IMMU(1)); Fzac;
+#-
+#+
+# /** 0110 0001 1000 0010 add %0, %e1 */
+# ID(add); DR(A); SM2(HL, C, 0); Fzac;
+#
+#@@ -714,28 +714,28 @@ rl78_decode_opcode (unsigned long pc AU,
+# ID(mov); DR(CS); SR(A);
+#
+# /** 0100 0001 mov %0, #%1 */
+#- ID(mov); DR(ES); SC(IMMU(1));
+#+ ID(mov); DR(ES); SC(IMMU(1));
+#
+# /** 1001 1110 1111 1101 mov %0, %1 */
+#- ID(mov); DR(ES); SR(A);
+#+ ID(mov); DR(ES); SR(A);
+#
+# /** 0110 0001 1011 1000 mov %0, %1 */
+#- ID(mov); DR(ES); SM(None, SADDR);
+#+ ID(mov); DR(ES); SM(None, SADDR);
+#
+# /** 0001 1001 mov %e0, #%1 */
+#- ID(mov); DM(B, IMMU(2)); SC(IMMU(1));
+#+ ID(mov); DM(B, IMMU(2)); SC(IMMU(1));
+#
+# /** 0001 1000 mov %e0, %1 */
+#- ID(mov); DM(B, IMMU(2)); SR(A);
+#+ ID(mov); DM(B, IMMU(2)); SR(A);
+#
+# /** 0011 1001 mov %e0, #%1 */
+#- ID(mov); DM(BC, IMMU(2)); SC(IMMU(1));
+#+ ID(mov); DM(BC, IMMU(2)); SC(IMMU(1));
+#
+# /** 0100 1000 mov %e0, %1 */
+#- ID(mov); DM(BC, IMMU(2)); SR(A);
+#+ ID(mov); DM(BC, IMMU(2)); SR(A);
+#
+# /** 0011 1000 mov %e0, #%1 */
+#- ID(mov); DM(C, IMMU(2)); SC(IMMU(1));
+#+ ID(mov); DM(C, IMMU(2)); SC(IMMU(1));
+#
+# /** 0010 1000 mov %e0, %1 */
+# ID(mov); DM(C, IMMU(2)); SR(A);
+--- a/opcodes/rl78-dis.c
++++ b/opcodes/rl78-dis.c
+@@ -204,7 +204,7 @@ print_insn_rl78_common (bfd_vma addr, disassemble_info * dis, RL78_Dis_Isa isa)
+ {
+ char *comma = "";
+ PR (PS, " \033[35m");
+-
++
+ if (opcode.flags & RL78_PSW_Z)
+ { PR (PS, "Z"); comma = ","; }
+ if (opcode.flags & RL78_PSW_AC)
+@@ -290,7 +290,7 @@ print_insn_rl78_common (bfd_vma addr, disassemble_info * dis, RL78_Dis_Isa isa)
+ PR (PS, "+%d", oper->addend);
+ PC (']');
+ break;
+-
++
+ }
+ if (oper->type == RL78_Operand_BitIndirect)
+ PR (PS, ".%d", oper->bit_number);
+#--- a/opcodes/rx-decode.c
+#+++ b/opcodes/rx-decode.c
+#@@ -66,7 +66,7 @@ static int ubwl[] =
+# RX_UByte,
+# RX_UWord,
+# RX_Long,
+#- 0 /* Bogus instructions can have a size field set to 3. */
+#+ 0 /* Bogus instructions can have a size field set to 3. */
+# };
+#
+# static int memex[] =
+#@@ -250,7 +250,7 @@ rx_disp (int n, int type, int reg, int size, LocalData * ld)
+# #define xZ 2
+# #define xC 1
+#
+#-#define F_____
+#+#define F_____
+# #define F___ZC rx->flags_0 = rx->flags_s = xZ|xC;
+# #define F__SZ_ rx->flags_0 = rx->flags_s = xS|xZ;
+# #define F__SZC rx->flags_0 = rx->flags_s = xS|xZ|xC;
+#@@ -296,7 +296,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("brk");
+# #line 987 "rx-decode.opc"
+# ID(brk);
+#-
+#+
+# }
+# break;
+# case 0x01:
+#@@ -311,7 +311,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("dbt");
+# #line 990 "rx-decode.opc"
+# ID(dbt);
+#-
+#+
+# }
+# break;
+# case 0x02:
+#@@ -326,10 +326,10 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("rts");
+# #line 768 "rx-decode.opc"
+# ID(rts);
+#-
+#+
+# /*----------------------------------------------------------------------*/
+# /* NOP */
+#-
+#+
+# }
+# break;
+# case 0x03:
+#@@ -344,10 +344,10 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("nop");
+# #line 774 "rx-decode.opc"
+# ID(nop);
+#-
+#+
+# /*----------------------------------------------------------------------*/
+# /* STRING FUNCTIONS */
+#-
+#+
+# }
+# break;
+# case 0x04:
+#@@ -362,7 +362,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("bra.a %a0");
+# #line 746 "rx-decode.opc"
+# ID(branch); DC(pc + IMMex(3));
+#-
+#+
+# }
+# break;
+# case 0x05:
+#@@ -377,7 +377,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("bsr.a %a0");
+# #line 762 "rx-decode.opc"
+# ID(jsr); DC(pc + IMMex(3));
+#-
+#+
+# }
+# break;
+# case 0x06:
+#@@ -413,7 +413,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("sub %2%S2, %1");
+# #line 542 "rx-decode.opc"
+# ID(sub); S2Pm(ss, rsrc, mx); SR(rdst); DR(rdst); F_OSZC;
+#-
+#+
+# }
+# break;
+# }
+#@@ -474,10 +474,10 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("cmp %2%S2, %1");
+# #line 530 "rx-decode.opc"
+# ID(sub); S2Pm(ss, rsrc, mx); SR(rdst); F_OSZC;
+#-
+#+
+# /*----------------------------------------------------------------------*/
+# /* SUB */
+#-
+#+
+# }
+# break;
+# }
+#@@ -538,7 +538,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("add %1%S1, %0");
+# #line 506 "rx-decode.opc"
+# ID(add); SPm(ss, rsrc, mx); DR(rdst); F_OSZC;
+#-
+#+
+# }
+# break;
+# }
+#@@ -599,7 +599,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("mul %1%S1, %0");
+# #line 611 "rx-decode.opc"
+# ID(mul); SPm(ss, rsrc, mx); DR(rdst); F_____;
+#-
+#+
+# }
+# break;
+# }
+#@@ -660,7 +660,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("and %1%S1, %0");
+# #line 419 "rx-decode.opc"
+# ID(and); SPm(ss, rsrc, mx); DR(rdst); F__SZ_;
+#-
+#+
+# }
+# break;
+# }
+#@@ -721,7 +721,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("or %1%S1, %0");
+# #line 437 "rx-decode.opc"
+# ID(or); SPm(ss, rsrc, mx); DR(rdst); F__SZ_;
+#-
+#+
+# }
+# break;
+# }
+#@@ -786,10 +786,10 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("sbb %1%S1, %0");
+# #line 555 "rx-decode.opc"
+# ID(sbb); SPm(sp, rsrc, mx); DR(rdst); F_OSZC;
+#-
+#+
+# /*----------------------------------------------------------------------*/
+# /* ABS */
+#-
+#+
+# }
+# break;
+# }
+#@@ -823,10 +823,10 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("max %1%S1, %0");
+# #line 584 "rx-decode.opc"
+# ID(max); SPm(ss, rsrc, mx); DR(rdst);
+#-
+#+
+# /*----------------------------------------------------------------------*/
+# /* MIN */
+#-
+#+
+# }
+# break;
+# }
+#@@ -860,10 +860,10 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("min %1%S1, %0");
+# #line 596 "rx-decode.opc"
+# ID(min); SPm(ss, rsrc, mx); DR(rdst);
+#-
+#+
+# /*----------------------------------------------------------------------*/
+# /* MUL */
+#-
+#+
+# }
+# break;
+# }
+#@@ -897,10 +897,10 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("emul %1%S1, %0");
+# #line 626 "rx-decode.opc"
+# ID(emul); SPm(ss, rsrc, mx); DR(rdst);
+#-
+#+
+# /*----------------------------------------------------------------------*/
+# /* EMULU */
+#-
+#+
+# }
+# break;
+# }
+#@@ -934,10 +934,10 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("emulu %1%S1, %0");
+# #line 638 "rx-decode.opc"
+# ID(emulu); SPm(ss, rsrc, mx); DR(rdst);
+#-
+#+
+# /*----------------------------------------------------------------------*/
+# /* DIV */
+#-
+#+
+# }
+# break;
+# }
+#@@ -971,10 +971,10 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("div %1%S1, %0");
+# #line 650 "rx-decode.opc"
+# ID(div); SPm(ss, rsrc, mx); DR(rdst); F_O___;
+#-
+#+
+# /*----------------------------------------------------------------------*/
+# /* DIVU */
+#-
+#+
+# }
+# break;
+# }
+#@@ -1008,10 +1008,10 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("divu %1%S1, %0");
+# #line 662 "rx-decode.opc"
+# ID(divu); SPm(ss, rsrc, mx); DR(rdst); F_O___;
+#-
+#+
+# /*----------------------------------------------------------------------*/
+# /* SHIFT */
+#-
+#+
+# }
+# break;
+# }
+#@@ -1045,10 +1045,10 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("tst %1%S1, %2");
+# #line 473 "rx-decode.opc"
+# ID(and); SPm(ss, rsrc, mx); S2R(rdst); F__SZ_;
+#-
+#+
+# /*----------------------------------------------------------------------*/
+# /* NEG */
+#-
+#+
+# }
+# break;
+# }
+#@@ -1082,10 +1082,10 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("xor %1%S1, %0");
+# #line 452 "rx-decode.opc"
+# ID(xor); SPm(ss, rsrc, mx); DR(rdst); F__SZ_;
+#-
+#+
+# /*----------------------------------------------------------------------*/
+# /* NOT */
+#-
+#+
+# }
+# break;
+# }
+#@@ -1119,10 +1119,10 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("xchg %1%S1, %0");
+# #line 386 "rx-decode.opc"
+# ID(xchg); DR(rdst); SPm(ss, rsrc, mx);
+#-
+#+
+# /*----------------------------------------------------------------------*/
+# /* STZ/STNZ */
+#-
+#+
+# }
+# break;
+# }
+#@@ -1156,10 +1156,10 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("itof %1%S1, %0");
+# #line 891 "rx-decode.opc"
+# ID(itof); DR (rdst); SPm(sd, rsrc, mx); F__SZ_;
+#-
+#+
+# /*----------------------------------------------------------------------*/
+# /* BIT OPS */
+#-
+#+
+# }
+# break;
+# }
+#@@ -2380,10 +2380,10 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("adc %1%S1, %0");
+# #line 494 "rx-decode.opc"
+# ID(adc); SPm(ss, rsrc, 2); DR(rdst); F_OSZC;
+#-
+#+
+# /*----------------------------------------------------------------------*/
+# /* ADD */
+#-
+#+
+# }
+# break;
+# }
+#@@ -3491,7 +3491,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("bra.s %a0");
+# #line 737 "rx-decode.opc"
+# ID(branch); DC(pc + dsp3map[dsp]);
+#-
+#+
+# }
+# break;
+# case 0x10:
+#@@ -3527,7 +3527,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("b%1.s %a0");
+# #line 727 "rx-decode.opc"
+# ID(branch); Scc(n); DC(pc + dsp3map[dsp]);
+#-
+#+
+# }
+# break;
+# case 0x20:
+#@@ -3559,7 +3559,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("b%1.b %a0");
+# #line 730 "rx-decode.opc"
+# ID(branch); Scc(cond); DC(pc + IMMex (1));
+#-
+#+
+# }
+# break;
+# case 0x2e:
+#@@ -3574,7 +3574,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("bra.b %a0");
+# #line 740 "rx-decode.opc"
+# ID(branch); DC(pc + IMMex(1));
+#-
+#+
+# }
+# break;
+# case 0x38:
+#@@ -3589,7 +3589,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("bra.w %a0");
+# #line 743 "rx-decode.opc"
+# ID(branch); DC(pc + IMMex(2));
+#-
+#+
+# }
+# break;
+# case 0x39:
+#@@ -3604,7 +3604,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("bsr.w %a0");
+# #line 759 "rx-decode.opc"
+# ID(jsr); DC(pc + IMMex(2));
+#-
+#+
+# }
+# break;
+# case 0x3a:
+#@@ -3623,8 +3623,8 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("b%1.w %a0");
+# #line 733 "rx-decode.opc"
+# ID(branch); Scc(c); DC(pc + IMMex (2));
+#-
+#-
+#+
+#+
+# }
+# break;
+# case 0x3c:
+#@@ -3656,7 +3656,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("mov%s #%1, %0");
+# #line 307 "rx-decode.opc"
+# ID(mov); sBWL (sz); DIs(dst, d*16+sppp, sz); SC(IMM(1)); F_____;
+#-
+#+
+# }
+# break;
+# }
+#@@ -3701,10 +3701,10 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("rtsd #%1, %2-%0");
+# #line 404 "rx-decode.opc"
+# ID(rtsd); SC(IMM(1) * 4); S2R(rega); DR(regb);
+#-
+#+
+# /*----------------------------------------------------------------------*/
+# /* AND */
+#-
+#+
+# }
+# break;
+# }
+#@@ -3735,7 +3735,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("sub %2%S2, %1");
+# #line 539 "rx-decode.opc"
+# ID(sub); S2P(ss, rsrc); SR(rdst); DR(rdst); F_OSZC;
+#-
+#+
+# }
+# break;
+# }
+#@@ -3793,7 +3793,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("cmp %2%S2, %1");
+# #line 527 "rx-decode.opc"
+# ID(sub); S2P(ss, rsrc); SR(rdst); F_OSZC;
+#-
+#+
+# }
+# break;
+# }
+#@@ -3851,7 +3851,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("add %1%S1, %0");
+# #line 503 "rx-decode.opc"
+# ID(add); SP(ss, rsrc); DR(rdst); F_OSZC;
+#-
+#+
+# }
+# break;
+# }
+#@@ -3909,7 +3909,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("mul %1%S1, %0");
+# #line 608 "rx-decode.opc"
+# ID(mul); SP(ss, rsrc); DR(rdst); F_____;
+#-
+#+
+# }
+# break;
+# }
+#@@ -3967,7 +3967,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("and %1%S1, %0");
+# #line 416 "rx-decode.opc"
+# ID(and); SP(ss, rsrc); DR(rdst); F__SZ_;
+#-
+#+
+# }
+# break;
+# }
+#@@ -4025,7 +4025,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("or %1%S1, %0");
+# #line 434 "rx-decode.opc"
+# ID(or); SP(ss, rsrc); DR(rdst); F__SZ_;
+#-
+#+
+# }
+# break;
+# }
+#@@ -4086,7 +4086,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("movu%s %1, %0");
+# #line 355 "rx-decode.opc"
+# ID(mov); uBWL(s); SD(ss, rsrc, s); DR(rdst); F_____;
+#-
+#+
+# }
+# break;
+# }
+#@@ -4176,7 +4176,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("sub #%2, %0");
+# #line 536 "rx-decode.opc"
+# ID(sub); S2C(immm); SR(rdst); DR(rdst); F_OSZC;
+#-
+#+
+# }
+# break;
+# }
+#@@ -4203,7 +4203,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("cmp #%2, %1");
+# #line 518 "rx-decode.opc"
+# ID(sub); S2C(immm); SR(rdst); F_OSZC;
+#-
+#+
+# }
+# break;
+# }
+#@@ -4230,7 +4230,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("add #%1, %0");
+# #line 500 "rx-decode.opc"
+# ID(add); SC(immm); DR(rdst); F_OSZC;
+#-
+#+
+# }
+# break;
+# }
+#@@ -4257,7 +4257,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("mul #%1, %0");
+# #line 602 "rx-decode.opc"
+# ID(mul); DR(rdst); SC(immm); F_____;
+#-
+#+
+# }
+# break;
+# }
+#@@ -4284,7 +4284,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("and #%1, %0");
+# #line 410 "rx-decode.opc"
+# ID(and); SC(immm); DR(rdst); F__SZ_;
+#-
+#+
+# }
+# break;
+# }
+#@@ -4311,7 +4311,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("or #%1, %0");
+# #line 428 "rx-decode.opc"
+# ID(or); SC(immm); DR(rdst); F__SZ_;
+#-
+#+
+# }
+# break;
+# }
+#@@ -4338,7 +4338,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("mov%s #%1, %0");
+# #line 304 "rx-decode.opc"
+# ID(mov); DR(rdst); SC(immm); F_____;
+#-
+#+
+# }
+# break;
+# }
+#@@ -4355,7 +4355,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("rtsd #%1");
+# #line 401 "rx-decode.opc"
+# ID(rtsd); SC(IMM(1) * 4);
+#-
+#+
+# }
+# break;
+# case 0x68:
+#@@ -4384,7 +4384,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("shlr #%2, %0");
+# #line 688 "rx-decode.opc"
+# ID(shlr); S2C(i*16+mmmm); SR(rdst); DR(rdst); F__SZC;
+#-
+#+
+# }
+# break;
+# }
+#@@ -4424,7 +4424,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("shar #%2, %0");
+# #line 678 "rx-decode.opc"
+# ID(shar); S2C(i*16+mmmm); SR(rdst); DR(rdst); F_0SZC;
+#-
+#+
+# }
+# break;
+# }
+#@@ -4464,7 +4464,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("shll #%2, %0");
+# #line 668 "rx-decode.opc"
+# ID(shll); S2C(i*16+mmmm); SR(rdst); DR(rdst); F_OSZC;
+#-
+#+
+# }
+# break;
+# }
+#@@ -4500,7 +4500,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("pushm %1-%2");
+# #line 368 "rx-decode.opc"
+# ID(pushm); SR(dsta); S2R(dstb); F_____;
+#-
+#+
+# }
+# break;
+# }
+#@@ -4527,7 +4527,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("popm %1-%2");
+# #line 365 "rx-decode.opc"
+# ID(popm); SR(dsta); S2R(dstb); F_____;
+#-
+#+
+# }
+# break;
+# }
+#@@ -4558,7 +4558,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("add #%1, %2, %0");
+# #line 509 "rx-decode.opc"
+# ID(add); SC(IMMex(im)); S2R(rsrc); DR(rdst); F_OSZC;
+#-
+#+
+# }
+# break;
+# }
+#@@ -4613,7 +4613,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("cmp #%2, %1%S1");
+# #line 521 "rx-decode.opc"
+# ID(sub); SR(rsrc); S2C(IMMex(im)); F_OSZC;
+#-
+#+
+# }
+# break;
+# case 0x10:
+#@@ -4635,7 +4635,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("mul #%1, %0");
+# #line 605 "rx-decode.opc"
+# ID(mul); DR(rdst); SC(IMMex(im)); F_____;
+#-
+#+
+# }
+# break;
+# case 0x20:
+#@@ -4657,7 +4657,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("and #%1, %0");
+# #line 413 "rx-decode.opc"
+# ID(and); SC(IMMex(im)); DR(rdst); F__SZ_;
+#-
+#+
+# }
+# break;
+# case 0x30:
+#@@ -4679,7 +4679,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("or #%1, %0");
+# #line 431 "rx-decode.opc"
+# ID(or); SC(IMMex(im)); DR(rdst); F__SZ_;
+#-
+#+
+# }
+# break;
+# default: UNSUPPORTED(); break;
+#@@ -4791,7 +4791,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("mov%s #%1, %0");
+# #line 285 "rx-decode.opc"
+# ID(mov); DR(rdst); SC(IMM (1)); F_____;
+#-
+#+
+# }
+# break;
+# case 0x50:
+#@@ -4824,7 +4824,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("cmp #%2, %1");
+# #line 524 "rx-decode.opc"
+# ID(sub); SR(rsrc); S2C(IMM(1)); F_OSZC;
+#-
+#+
+# }
+# break;
+# case 0x60:
+#@@ -4839,7 +4839,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("int #%1");
+# #line 993 "rx-decode.opc"
+# ID(int); SC(IMM(1));
+#-
+#+
+# }
+# break;
+# case 0x70:
+#@@ -4861,7 +4861,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("mvtipl #%1");
+# #line 960 "rx-decode.opc"
+# ID(mvtipl); SC(immm);
+#-
+#+
+# }
+# break;
+# default: UNSUPPORTED(); break;
+#@@ -4934,8 +4934,8 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("bset #%1, %0");
+# #line 905 "rx-decode.opc"
+# ID(bset); BWL(LSIZE); SC(b*16+ittt); DR(rdst); F_____;
+#-
+#-
+#+
+#+
+# }
+# break;
+# }
+#@@ -4975,8 +4975,8 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("bclr #%1, %0");
+# #line 917 "rx-decode.opc"
+# ID(bclr); BWL(LSIZE); SC(b*16+ittt); DR(rdst); F_____;
+#-
+#-
+#+
+#+
+# }
+# break;
+# }
+#@@ -5016,8 +5016,8 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("btst #%2, %1");
+# #line 929 "rx-decode.opc"
+# ID(btst); BWL(LSIZE); S2C(b*16+ittt); SR(rdst); F___ZC;
+#-
+#-
+#+
+#+
+# }
+# break;
+# }
+#@@ -5050,7 +5050,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("not %0");
+# #line 458 "rx-decode.opc"
+# ID(xor); DR(rdst); SR(rdst); S2C(~0); F__SZ_;
+#-
+#+
+# }
+# break;
+# case 0x10:
+#@@ -5068,7 +5068,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("neg %0");
+# #line 479 "rx-decode.opc"
+# ID(sub); DR(rdst); SC(0); S2R(rdst); F_OSZC;
+#-
+#+
+# }
+# break;
+# case 0x20:
+#@@ -5086,7 +5086,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("abs %0");
+# #line 561 "rx-decode.opc"
+# ID(abs); DR(rdst); SR(rdst); F_OSZ_;
+#-
+#+
+# }
+# break;
+# case 0x30:
+#@@ -5104,7 +5104,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("sat %0");
+# #line 843 "rx-decode.opc"
+# ID(sat); DR (rdst);
+#-
+#+
+# }
+# break;
+# case 0x40:
+#@@ -5122,7 +5122,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("rorc %0");
+# #line 703 "rx-decode.opc"
+# ID(rorc); DR(rdst); F__SZC;
+#-
+#+
+# }
+# break;
+# case 0x50:
+#@@ -5140,7 +5140,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("rolc %0");
+# #line 700 "rx-decode.opc"
+# ID(rolc); DR(rdst); F__SZC;
+#-
+#+
+# }
+# break;
+# case 0x80:
+#@@ -5163,7 +5163,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("push%s %1");
+# #line 374 "rx-decode.opc"
+# ID(mov); BWL(sz); OP(0, RX_Operand_Predec, 0, 0); SR(rsrc); F_____;
+#-
+#+
+# }
+# break;
+# case 0xb0:
+#@@ -5181,7 +5181,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("pop %0");
+# #line 371 "rx-decode.opc"
+# ID(mov); OP(1, RX_Operand_Postinc, 0, 0); DR(rdst); F_____;
+#-
+#+
+# }
+# break;
+# case 0xc0:
+#@@ -5200,7 +5200,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("pushc %1");
+# #line 966 "rx-decode.opc"
+# ID(mov); OP(0, RX_Operand_Predec, 0, 0); SR(crsrc + 16);
+#-
+#+
+# }
+# break;
+# case 0xe0:
+#@@ -5219,7 +5219,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("popc %0");
+# #line 963 "rx-decode.opc"
+# ID(mov); OP(1, RX_Operand_Postinc, 0, 0); DR(crdst + 16);
+#-
+#+
+# }
+# break;
+# default: UNSUPPORTED(); break;
+#@@ -5259,7 +5259,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("jmp %0");
+# #line 753 "rx-decode.opc"
+# ID(branch); DR(rsrc);
+#-
+#+
+# }
+# break;
+# case 0x10:
+#@@ -5292,7 +5292,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("jsr %0");
+# #line 756 "rx-decode.opc"
+# ID(jsr); DR(rsrc);
+#-
+#+
+# }
+# break;
+# case 0x40:
+#@@ -5325,8 +5325,8 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("bra.l %0");
+# #line 749 "rx-decode.opc"
+# ID(branchrel); DR(rsrc);
+#-
+#-
+#+
+#+
+# }
+# break;
+# case 0x50:
+#@@ -5359,7 +5359,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("bsr.l %0");
+# #line 765 "rx-decode.opc"
+# ID(jsrrel); DR(rsrc);
+#-
+#+
+# }
+# break;
+# case 0x80:
+#@@ -5379,7 +5379,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("suntil%s");
+# #line 789 "rx-decode.opc"
+# ID(suntil); BWL(sz); F___ZC;
+#-
+#+
+# }
+# break;
+# case 0x83:
+#@@ -5394,7 +5394,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("scmpu");
+# #line 780 "rx-decode.opc"
+# ID(scmpu); F___ZC;
+#-
+#+
+# }
+# break;
+# case 0x84:
+#@@ -5414,7 +5414,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("swhile%s");
+# #line 792 "rx-decode.opc"
+# ID(swhile); BWL(sz); F___ZC;
+#-
+#+
+# }
+# break;
+# case 0x87:
+#@@ -5429,7 +5429,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("smovu");
+# #line 783 "rx-decode.opc"
+# ID(smovu);
+#-
+#+
+# }
+# break;
+# case 0x88:
+#@@ -5449,10 +5449,10 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("sstr%s");
+# #line 798 "rx-decode.opc"
+# ID(sstr); BWL(sz);
+#-
+#+
+# /*----------------------------------------------------------------------*/
+# /* RMPA */
+#-
+#+
+# }
+# break;
+# case 0x8b:
+#@@ -5467,7 +5467,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("smovb");
+# #line 786 "rx-decode.opc"
+# ID(smovb);
+#-
+#+
+# }
+# break;
+# case 0x8c:
+#@@ -5487,10 +5487,10 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("rmpa%s");
+# #line 804 "rx-decode.opc"
+# ID(rmpa); BWL(sz); F_OS__;
+#-
+#+
+# /*----------------------------------------------------------------------*/
+# /* HI/LO stuff */
+#-
+#+
+# }
+# break;
+# case 0x8f:
+#@@ -5505,7 +5505,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("smovf");
+# #line 795 "rx-decode.opc"
+# ID(smovf);
+#-
+#+
+# }
+# break;
+# case 0x93:
+#@@ -5520,10 +5520,10 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("satr");
+# #line 846 "rx-decode.opc"
+# ID(satr);
+#-
+#+
+# /*----------------------------------------------------------------------*/
+# /* FLOAT */
+#-
+#+
+# }
+# break;
+# case 0x94:
+#@@ -5538,7 +5538,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("rtfi");
+# #line 981 "rx-decode.opc"
+# ID(rtfi);
+#-
+#+
+# }
+# break;
+# case 0x95:
+#@@ -5553,7 +5553,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("rte");
+# #line 984 "rx-decode.opc"
+# ID(rte);
+#-
+#+
+# }
+# break;
+# case 0x96:
+#@@ -5568,10 +5568,10 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("wait");
+# #line 996 "rx-decode.opc"
+# ID(wait);
+#-
+#+
+# /*----------------------------------------------------------------------*/
+# /* SCcnd */
+#-
+#+
+# }
+# break;
+# case 0xa0:
+#@@ -5604,7 +5604,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("setpsw %0");
+# #line 957 "rx-decode.opc"
+# ID(setpsw); DF(rdst);
+#-
+#+
+# }
+# break;
+# case 0xb0:
+#@@ -5637,7 +5637,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("clrpsw %0");
+# #line 954 "rx-decode.opc"
+# ID(clrpsw); DF(rdst);
+#-
+#+
+# }
+# break;
+# default: UNSUPPORTED(); break;
+#@@ -5678,7 +5678,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("mov%s %1, %0");
+# #line 332 "rx-decode.opc"
+# ID(mov); sBWL(sz); DIs(dst, dsp*4+a*2+b, sz); SR(src); F_____;
+#-
+#+
+# }
+# break;
+# }
+#@@ -5781,7 +5781,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("mov%s %1, %0");
+# #line 329 "rx-decode.opc"
+# ID(mov); sBWL(sz); DR(dst); SIs(src, dsp*4+a*2+b, sz); F_____;
+#-
+#+
+# }
+# break;
+# }
+#@@ -6172,7 +6172,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("movu%s %1, %0");
+# #line 352 "rx-decode.opc"
+# ID(mov); uBWL(w); DR(dst); SIs(src, dsp*4+a*2+b, w); F_____;
+#-
+#+
+# }
+# break;
+# }
+#@@ -6360,7 +6360,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SD(ss, rsrc, sz); DD(sd, rdst, sz);
+# }
+# }
+#-
+#+
+# }
+# break;
+# }
+#@@ -6814,7 +6814,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("bset #%1, %0%S0");
+# #line 897 "rx-decode.opc"
+# ID(bset); BWL(BSIZE); SC(bit); DD(sd, rdst, BSIZE); F_____;
+#-
+#+
+# }
+# break;
+# case 0x08:
+#@@ -6839,7 +6839,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("bclr #%1, %0%S0");
+# #line 909 "rx-decode.opc"
+# ID(bclr); BWL(BSIZE); SC(bit); DD(sd, rdst, BSIZE); F_____;
+#-
+#+
+# }
+# break;
+# }
+#@@ -6907,7 +6907,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("btst #%2, %1%S1");
+# #line 921 "rx-decode.opc"
+# ID(btst); BWL(BSIZE); S2C(bit); SD(sd, rdst, BSIZE); F___ZC;
+#-
+#+
+# }
+# break;
+# case 0x08:
+#@@ -6932,10 +6932,10 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("push%s %1");
+# #line 377 "rx-decode.opc"
+# ID(mov); BWL(sz); OP(0, RX_Operand_Predec, 0, 0); SD(ss, rsrc, sz); F_____;
+#-
+#+
+# /*----------------------------------------------------------------------*/
+# /* XCHG */
+#-
+#+
+# }
+# break;
+# default: UNSUPPORTED(); break;
+#@@ -7025,7 +7025,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SC(IMMex(im));
+# }
+# F_____;
+#-
+#+
+# }
+# break;
+# }
+#@@ -7083,7 +7083,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("sbb %1, %0");
+# #line 551 "rx-decode.opc"
+# ID(sbb); SR (rsrc); DR(rdst); F_OSZC;
+#-
+#+
+# /* FIXME: only supports .L */
+# }
+# break;
+#@@ -7111,10 +7111,10 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("neg %2, %0");
+# #line 482 "rx-decode.opc"
+# ID(sub); DR(rdst); SC(0); S2R(rsrc); F_OSZC;
+#-
+#+
+# /*----------------------------------------------------------------------*/
+# /* ADC */
+#-
+#+
+# }
+# break;
+# }
+#@@ -7141,7 +7141,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("adc %1, %0");
+# #line 491 "rx-decode.opc"
+# ID(adc); SR(rsrc); DR(rdst); F_OSZC;
+#-
+#+
+# }
+# break;
+# }
+#@@ -7168,10 +7168,10 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("abs %1, %0");
+# #line 564 "rx-decode.opc"
+# ID(abs); DR(rdst); SR(rsrc); F_OSZ_;
+#-
+#+
+# /*----------------------------------------------------------------------*/
+# /* MAX */
+#-
+#+
+# }
+# break;
+# }
+#@@ -7210,7 +7210,7 @@ rx_decode_opcode (unsigned long pc AU,
+# {
+# ID(max); SP(ss, rsrc); DR(rdst);
+# }
+#-
+#+
+# }
+# break;
+# }
+#@@ -7268,7 +7268,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("min %1%S1, %0");
+# #line 593 "rx-decode.opc"
+# ID(min); SP(ss, rsrc); DR(rdst);
+#-
+#+
+# }
+# break;
+# }
+#@@ -7326,7 +7326,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("emul %1%S1, %0");
+# #line 623 "rx-decode.opc"
+# ID(emul); SP(ss, rsrc); DR(rdst);
+#-
+#+
+# }
+# break;
+# }
+#@@ -7384,7 +7384,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("emulu %1%S1, %0");
+# #line 635 "rx-decode.opc"
+# ID(emulu); SP(ss, rsrc); DR(rdst);
+#-
+#+
+# }
+# break;
+# }
+#@@ -7442,7 +7442,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("div %1%S1, %0");
+# #line 647 "rx-decode.opc"
+# ID(div); SP(ss, rsrc); DR(rdst); F_O___;
+#-
+#+
+# }
+# break;
+# }
+#@@ -7500,7 +7500,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("divu %1%S1, %0");
+# #line 659 "rx-decode.opc"
+# ID(divu); SP(ss, rsrc); DR(rdst); F_O___;
+#-
+#+
+# }
+# break;
+# }
+#@@ -7558,7 +7558,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("tst %1%S1, %2");
+# #line 470 "rx-decode.opc"
+# ID(and); SP(ss, rsrc); S2R(rdst); F__SZ_;
+#-
+#+
+# }
+# break;
+# }
+#@@ -7616,7 +7616,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("xor %1%S1, %0");
+# #line 449 "rx-decode.opc"
+# ID(xor); SP(ss, rsrc); DR(rdst); F__SZ_;
+#-
+#+
+# }
+# break;
+# }
+#@@ -7670,10 +7670,10 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("not %1, %0");
+# #line 461 "rx-decode.opc"
+# ID(xor); DR(rdst); SR(rsrc); S2C(~0); F__SZ_;
+#-
+#+
+# /*----------------------------------------------------------------------*/
+# /* TST */
+#-
+#+
+# }
+# break;
+# }
+#@@ -7704,7 +7704,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("xchg %1%S1, %0");
+# #line 383 "rx-decode.opc"
+# ID(xchg); DR(rdst); SP(ss, rsrc);
+#-
+#+
+# }
+# break;
+# }
+#@@ -7762,7 +7762,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("itof %1%S1, %0");
+# #line 888 "rx-decode.opc"
+# ID(itof); DR (rdst); SP(sd, rsrc); F__SZ_;
+#-
+#+
+# }
+# break;
+# }
+#@@ -7822,7 +7822,7 @@ rx_decode_opcode (unsigned long pc AU,
+# ID(bset); BWL(BSIZE); SR(rsrc); DD(sd, rdst, BSIZE); F_____;
+# if (sd == 3) /* bset reg,reg */
+# BWL(LSIZE);
+#-
+#+
+# }
+# break;
+# }
+#@@ -7882,7 +7882,7 @@ rx_decode_opcode (unsigned long pc AU,
+# ID(bclr); BWL(BSIZE); SR(rsrc); DD(sd, rdst, BSIZE); F_____;
+# if (sd == 3) /* bset reg,reg */
+# BWL(LSIZE);
+#-
+#+
+# }
+# break;
+# }
+#@@ -7942,7 +7942,7 @@ rx_decode_opcode (unsigned long pc AU,
+# ID(btst); BWL(BSIZE); S2R(rsrc); SD(sd, rdst, BSIZE); F___ZC;
+# if (sd == 3) /* bset reg,reg */
+# BWL(LSIZE);
+#-
+#+
+# }
+# break;
+# }
+#@@ -8002,7 +8002,7 @@ rx_decode_opcode (unsigned long pc AU,
+# ID(bnot); BWL(BSIZE); SR(rsrc); DD(sd, rdst, BSIZE);
+# if (sd == 3) /* bset reg,reg */
+# BWL(LSIZE);
+#-
+#+
+# }
+# break;
+# }
+#@@ -8060,7 +8060,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("fsub %1%S1, %0");
+# #line 867 "rx-decode.opc"
+# ID(fsub); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_;
+#-
+#+
+# }
+# break;
+# }
+#@@ -8118,7 +8118,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("fcmp %1%S1, %0");
+# #line 861 "rx-decode.opc"
+# ID(fcmp); DR(rdst); SD(sd, rsrc, LSIZE); F_OSZ_;
+#-
+#+
+# }
+# break;
+# }
+#@@ -8176,7 +8176,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("fadd %1%S1, %0");
+# #line 855 "rx-decode.opc"
+# ID(fadd); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_;
+#-
+#+
+# }
+# break;
+# }
+#@@ -8234,7 +8234,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("fmul %1%S1, %0");
+# #line 876 "rx-decode.opc"
+# ID(fmul); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_;
+#-
+#+
+# }
+# break;
+# }
+#@@ -8292,7 +8292,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("fdiv %1%S1, %0");
+# #line 882 "rx-decode.opc"
+# ID(fdiv); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_;
+#-
+#+
+# }
+# break;
+# }
+#@@ -8350,7 +8350,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("ftoi %1%S1, %0");
+# #line 870 "rx-decode.opc"
+# ID(ftoi); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_;
+#-
+#+
+# }
+# break;
+# }
+#@@ -8408,7 +8408,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("round %1%S1, %0");
+# #line 885 "rx-decode.opc"
+# ID(round); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_;
+#-
+#+
+# }
+# break;
+# }
+#@@ -8469,7 +8469,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("sc%1%s %0");
+# #line 1002 "rx-decode.opc"
+# ID(sccnd); BWL(sz); DD (sd, rdst, sz); Scc(cond);
+#-
+#+
+# }
+# break;
+# }
+#@@ -8616,7 +8616,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("bm%2 #%1, %0%S0");
+# #line 945 "rx-decode.opc"
+# ID(bmcc); BWL(BSIZE); S2cc(cond); SC(bit); DD(sd, rdst, BSIZE);
+#-
+#+
+# }
+# break;
+# case 0x0f:
+#@@ -8641,7 +8641,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("bnot #%1, %0%S0");
+# #line 933 "rx-decode.opc"
+# ID(bnot); BWL(BSIZE); SC(bit); DD(sd, rdst, BSIZE);
+#-
+#+
+# }
+# break;
+# }
+#@@ -9481,7 +9481,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("mulhi %1, %2");
+# #line 810 "rx-decode.opc"
+# ID(mulhi); SR(srca); S2R(srcb); F_____;
+#-
+#+
+# }
+# break;
+# }
+#@@ -9508,7 +9508,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("mullo %1, %2");
+# #line 813 "rx-decode.opc"
+# ID(mullo); SR(srca); S2R(srcb); F_____;
+#-
+#+
+# }
+# break;
+# }
+#@@ -9535,7 +9535,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("machi %1, %2");
+# #line 816 "rx-decode.opc"
+# ID(machi); SR(srca); S2R(srcb); F_____;
+#-
+#+
+# }
+# break;
+# }
+#@@ -9562,7 +9562,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("maclo %1, %2");
+# #line 819 "rx-decode.opc"
+# ID(maclo); SR(srca); S2R(srcb); F_____;
+#-
+#+
+# }
+# break;
+# }
+#@@ -9586,7 +9586,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("mvtachi %1");
+# #line 822 "rx-decode.opc"
+# ID(mvtachi); SR(rsrc); F_____;
+#-
+#+
+# }
+# break;
+# case 0x10:
+#@@ -9604,7 +9604,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("mvtaclo %1");
+# #line 825 "rx-decode.opc"
+# ID(mvtaclo); SR(rsrc); F_____;
+#-
+#+
+# }
+# break;
+# default: UNSUPPORTED(); break;
+#@@ -9629,10 +9629,10 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("racw #%1");
+# #line 837 "rx-decode.opc"
+# ID(racw); SC(i+1); F_____;
+#-
+#+
+# /*----------------------------------------------------------------------*/
+# /* SAT */
+#-
+#+
+# }
+# break;
+# default: UNSUPPORTED(); break;
+#@@ -9657,7 +9657,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("mvfachi %0");
+# #line 828 "rx-decode.opc"
+# ID(mvfachi); DR(rdst); F_____;
+#-
+#+
+# }
+# break;
+# case 0x10:
+#@@ -9675,7 +9675,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("mvfaclo %0");
+# #line 834 "rx-decode.opc"
+# ID(mvfaclo); DR(rdst); F_____;
+#-
+#+
+# }
+# break;
+# case 0x20:
+#@@ -9693,7 +9693,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("mvfacmi %0");
+# #line 831 "rx-decode.opc"
+# ID(mvfacmi); DR(rdst); F_____;
+#-
+#+
+# }
+# break;
+# default: UNSUPPORTED(); break;
+#@@ -9729,7 +9729,7 @@ rx_decode_opcode (unsigned long pc AU,
+# #line 344 "rx-decode.opc"
+# ID(mov); sBWL (sz); SR(rsrc); F_____;
+# OP(0, p ? RX_Operand_Predec : RX_Operand_Postinc, rdst, 0);
+#-
+#+
+# }
+# break;
+# }
+#@@ -9809,7 +9809,7 @@ rx_decode_opcode (unsigned long pc AU,
+# #line 348 "rx-decode.opc"
+# ID(mov); sBWL (sz); DR(rdst); F_____;
+# OP(1, p ? RX_Operand_Predec : RX_Operand_Postinc, rsrc, 0);
+#-
+#+
+# }
+# break;
+# }
+#@@ -9889,10 +9889,10 @@ rx_decode_opcode (unsigned long pc AU,
+# #line 358 "rx-decode.opc"
+# ID(mov); uBWL (sz); DR(rdst); F_____;
+# OP(1, p ? RX_Operand_Predec : RX_Operand_Postinc, rsrc, 0);
+#-
+#+
+# /*----------------------------------------------------------------------*/
+# /* PUSH/POP */
+#-
+#+
+# }
+# break;
+# }
+#@@ -9964,7 +9964,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("shlr %2, %0");
+# #line 691 "rx-decode.opc"
+# ID(shlr); S2R(rsrc); SR(rdst); DR(rdst); F__SZC;
+#-
+#+
+# }
+# break;
+# }
+#@@ -9991,7 +9991,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("shar %2, %0");
+# #line 681 "rx-decode.opc"
+# ID(shar); S2R(rsrc); SR(rdst); DR(rdst); F_0SZC;
+#-
+#+
+# }
+# break;
+# }
+#@@ -10018,7 +10018,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("shll %2, %0");
+# #line 671 "rx-decode.opc"
+# ID(shll); S2R(rsrc); SR(rdst); DR(rdst); F_OSZC;
+#-
+#+
+# }
+# break;
+# }
+#@@ -10045,7 +10045,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("rotr %1, %0");
+# #line 715 "rx-decode.opc"
+# ID(rotr); SR(rsrc); DR(rdst); F__SZC;
+#-
+#+
+# }
+# break;
+# }
+#@@ -10072,7 +10072,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("revw %1, %0");
+# #line 718 "rx-decode.opc"
+# ID(revw); SR(rsrc); DR(rdst);
+#-
+#+
+# }
+# break;
+# }
+#@@ -10099,7 +10099,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("rotl %1, %0");
+# #line 709 "rx-decode.opc"
+# ID(rotl); SR(rsrc); DR(rdst); F__SZC;
+#-
+#+
+# }
+# break;
+# }
+#@@ -10126,10 +10126,10 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("revl %1, %0");
+# #line 721 "rx-decode.opc"
+# ID(revl); SR(rsrc); DR(rdst);
+#-
+#+
+# /*----------------------------------------------------------------------*/
+# /* BRANCH */
+#-
+#+
+# }
+# break;
+# }
+#@@ -10160,7 +10160,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("mvtc %1, %0");
+# #line 972 "rx-decode.opc"
+# ID(mov); SR(rsrc); DR(c*16+rdst + 16);
+#-
+#+
+# }
+# break;
+# }
+#@@ -10200,10 +10200,10 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("mvfc %1, %0");
+# #line 975 "rx-decode.opc"
+# ID(mov); SR((s*16+rsrc) + 16); DR(rdst);
+#-
+#+
+# /*----------------------------------------------------------------------*/
+# /* INTERRUPTS */
+#-
+#+
+# }
+# break;
+# }
+#@@ -10243,7 +10243,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("rotr #%1, %0");
+# #line 712 "rx-decode.opc"
+# ID(rotr); SC(i*16+mmmm); DR(rdst); F__SZC;
+#-
+#+
+# }
+# break;
+# }
+#@@ -10283,7 +10283,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("rotl #%1, %0");
+# #line 706 "rx-decode.opc"
+# ID(rotl); SC(i*16+mmmm); DR(rdst); F__SZC;
+#-
+#+
+# }
+# break;
+# }
+#@@ -10320,7 +10320,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("adc #%1, %0");
+# #line 488 "rx-decode.opc"
+# ID(adc); SC(IMMex(im)); DR(rdst); F_OSZC;
+#-
+#+
+# }
+# break;
+# case 0x40:
+#@@ -10342,7 +10342,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("max #%1, %0");
+# #line 570 "rx-decode.opc"
+# ID(max); DR(rdst); SC(IMMex(im));
+#-
+#+
+# }
+# break;
+# case 0x50:
+#@@ -10364,7 +10364,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("min #%1, %0");
+# #line 590 "rx-decode.opc"
+# ID(min); DR(rdst); SC(IMMex(im));
+#-
+#+
+# }
+# break;
+# case 0x60:
+#@@ -10386,7 +10386,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("emul #%1, %0");
+# #line 620 "rx-decode.opc"
+# ID(emul); DR(rdst); SC(IMMex(im));
+#-
+#+
+# }
+# break;
+# case 0x70:
+#@@ -10408,7 +10408,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("emulu #%1, %0");
+# #line 632 "rx-decode.opc"
+# ID(emulu); DR(rdst); SC(IMMex(im));
+#-
+#+
+# }
+# break;
+# case 0x80:
+#@@ -10430,7 +10430,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("div #%1, %0");
+# #line 644 "rx-decode.opc"
+# ID(div); DR(rdst); SC(IMMex(im)); F_O___;
+#-
+#+
+# }
+# break;
+# case 0x90:
+#@@ -10452,7 +10452,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("divu #%1, %0");
+# #line 656 "rx-decode.opc"
+# ID(divu); DR(rdst); SC(IMMex(im)); F_O___;
+#-
+#+
+# }
+# break;
+# case 0xc0:
+#@@ -10474,7 +10474,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("tst #%1, %2");
+# #line 467 "rx-decode.opc"
+# ID(and); SC(IMMex(im)); S2R(rdst); F__SZ_;
+#-
+#+
+# }
+# break;
+# case 0xd0:
+#@@ -10496,7 +10496,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("xor #%1, %0");
+# #line 446 "rx-decode.opc"
+# ID(xor); SC(IMMex(im)); DR(rdst); F__SZ_;
+#-
+#+
+# }
+# break;
+# case 0xe0:
+#@@ -10518,7 +10518,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("stz #%1, %0");
+# #line 392 "rx-decode.opc"
+# ID(stcc); SC(IMMex(im)); DR(rdst); S2cc(RXC_z);
+#-
+#+
+# }
+# break;
+# case 0xf0:
+#@@ -10540,10 +10540,10 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("stnz #%1, %0");
+# #line 395 "rx-decode.opc"
+# ID(stcc); SC(IMMex(im)); DR(rdst); S2cc(RXC_nz);
+#-
+#+
+# /*----------------------------------------------------------------------*/
+# /* RTSD */
+#-
+#+
+# }
+# break;
+# default: UNSUPPORTED(); break;
+#@@ -10568,7 +10568,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("fsub #%1, %0");
+# #line 864 "rx-decode.opc"
+# ID(fsub); DR(rdst); SC(IMM(0)); F__SZ_;
+#-
+#+
+# }
+# break;
+# case 0x10:
+#@@ -10586,7 +10586,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("fcmp #%1, %0");
+# #line 858 "rx-decode.opc"
+# ID(fcmp); DR(rdst); SC(IMM(0)); F_OSZ_;
+#-
+#+
+# }
+# break;
+# case 0x20:
+#@@ -10604,7 +10604,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("fadd #%1, %0");
+# #line 852 "rx-decode.opc"
+# ID(fadd); DR(rdst); SC(IMM(0)); F__SZ_;
+#-
+#+
+# }
+# break;
+# case 0x30:
+#@@ -10622,7 +10622,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("fmul #%1, %0");
+# #line 873 "rx-decode.opc"
+# ID(fmul); DR(rdst); SC(IMM(0)); F__SZ_;
+#-
+#+
+# }
+# break;
+# case 0x40:
+#@@ -10640,7 +10640,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("fdiv #%1, %0");
+# #line 879 "rx-decode.opc"
+# ID(fdiv); DR(rdst); SC(IMM(0)); F__SZ_;
+#-
+#+
+# }
+# break;
+# default: UNSUPPORTED(); break;
+#@@ -10669,7 +10669,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("mvtc #%1, %0");
+# #line 969 "rx-decode.opc"
+# ID(mov); SC(IMMex(im)); DR(crdst + 16);
+#-
+#+
+# }
+# break;
+# default: UNSUPPORTED(); break;
+#@@ -10851,10 +10851,10 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("shlr #%2, %1, %0");
+# #line 694 "rx-decode.opc"
+# ID(shlr); S2C(immmm); SR(rsrc); DR(rdst); F__SZC;
+#-
+#+
+# /*----------------------------------------------------------------------*/
+# /* ROTATE */
+#-
+#+
+# }
+# break;
+# }
+#@@ -11164,8 +11164,8 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("shar #%2, %1, %0");
+# #line 684 "rx-decode.opc"
+# ID(shar); S2C(immmm); SR(rsrc); DR(rdst); F_0SZC;
+#-
+#-
+#+
+#+
+# }
+# break;
+# }
+#@@ -11475,8 +11475,8 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("shll #%2, %1, %0");
+# #line 674 "rx-decode.opc"
+# ID(shll); S2C(immmm); SR(rsrc); DR(rdst); F_OSZC;
+#-
+#-
+#+
+#+
+# }
+# break;
+# }
+#@@ -11800,10 +11800,10 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("bm%2 #%1, %0%S0");
+# #line 948 "rx-decode.opc"
+# ID(bmcc); BWL(LSIZE); S2cc(cond); SC(bittt); DR(rdst);
+#-
+#+
+# /*----------------------------------------------------------------------*/
+# /* CONTROL REGISTERS */
+#-
+#+
+# }
+# break;
+# case 0xf0:
+#@@ -11825,8 +11825,8 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("bnot #%1, %0");
+# #line 941 "rx-decode.opc"
+# ID(bnot); BWL(LSIZE); SC(bittt); DR(rdst);
+#-
+#-
+#+
+#+
+# }
+# break;
+# }
+#@@ -12673,7 +12673,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("mov%s %0, [%1, %2]");
+# #line 338 "rx-decode.opc"
+# ID(movbir); sBWL(sz); DR(rdst); SRR(isrc); S2R(bsrc); F_____;
+#-
+#+
+# }
+# break;
+# }
+#@@ -13130,7 +13130,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("mov%s [%1, %2], %0");
+# #line 335 "rx-decode.opc"
+# ID(movbi); sBWL(sz); DR(rdst); SRR(isrc); S2R(bsrc); F_____;
+#-
+#+
+# }
+# break;
+# }
+#@@ -13587,7 +13587,7 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("movu%s [%1, %2], %0");
+# #line 341 "rx-decode.opc"
+# ID(movbi); uBWL(sz); DR(rdst); SRR(isrc); S2R(bsrc); F_____;
+#-
+#+
+# }
+# break;
+# }
+#@@ -14048,10 +14048,10 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("sub %2, %1, %0");
+# #line 545 "rx-decode.opc"
+# ID(sub); DR(rdst); SR(srcb); S2R(srca); F_OSZC;
+#-
+#+
+# /*----------------------------------------------------------------------*/
+# /* SBB */
+#-
+#+
+# }
+# break;
+# }
+#@@ -14217,10 +14217,10 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("add %2, %1, %0");
+# #line 512 "rx-decode.opc"
+# ID(add); DR(rdst); SR(srcb); S2R(srca); F_OSZC;
+#-
+#+
+# /*----------------------------------------------------------------------*/
+# /* CMP */
+#-
+#+
+# }
+# break;
+# }
+#@@ -14386,10 +14386,10 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("mul %2, %1, %0");
+# #line 614 "rx-decode.opc"
+# ID(mul); DR(rdst); SR(srcb); S2R(srca); F_____;
+#-
+#+
+# /*----------------------------------------------------------------------*/
+# /* EMUL */
+#-
+#+
+# }
+# break;
+# }
+#@@ -14555,10 +14555,10 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("and %2, %1, %0");
+# #line 422 "rx-decode.opc"
+# ID(and); DR(rdst); SR(srcb); S2R(srca); F__SZ_;
+#-
+#+
+# /*----------------------------------------------------------------------*/
+# /* OR */
+#-
+#+
+# }
+# break;
+# }
+#@@ -14724,10 +14724,10 @@ rx_decode_opcode (unsigned long pc AU,
+# SYNTAX("or %2, %1, %0");
+# #line 440 "rx-decode.opc"
+# ID(or); DR(rdst); SR(srcb); S2R(srca); F__SZ_;
+#-
+#+
+# /*----------------------------------------------------------------------*/
+# /* XOR */
+#-
+#+
+# }
+# break;
+# }
+#--- a/opcodes/rx-decode.opc
+#+++ b/opcodes/rx-decode.opc
+#@@ -65,7 +65,7 @@ static int ubwl[] =
+# RX_UByte,
+# RX_UWord,
+# RX_Long,
+#- 0 /* Bogus instructions can have a size field set to 3. */
+#+ 0 /* Bogus instructions can have a size field set to 3. */
+# };
+#
+# static int memex[] =
+#@@ -249,7 +249,7 @@ rx_disp (int n, int type, int reg, int size, LocalData * ld)
+# #define xZ 2
+# #define xC 1
+#
+#-#define F_____
+#+#define F_____
+# #define F___ZC rx->flags_0 = rx->flags_s = xZ|xC;
+# #define F__SZ_ rx->flags_0 = rx->flags_s = xS|xZ;
+# #define F__SZC rx->flags_0 = rx->flags_s = xS|xZ|xC;
+#@@ -366,10 +366,10 @@ rx_decode_opcode (unsigned long pc AU,
+#
+# /** 0110 1110 dsta dstb pushm %1-%2 */
+# ID(pushm); SR(dsta); S2R(dstb); F_____;
+#-
+#+
+# /** 0111 1110 1011 rdst pop %0 */
+# ID(mov); OP(1, RX_Operand_Postinc, 0, 0); DR(rdst); F_____;
+#-
+#+
+# /** 0111 1110 10sz rsrc push%s %1 */
+# ID(mov); BWL(sz); OP(0, RX_Operand_Predec, 0, 0); SR(rsrc); F_____;
+#
+--- a/opcodes/score-dis.c
++++ b/opcodes/score-dis.c
+@@ -35,7 +35,7 @@
+
+ #ifdef BFD64
+ /* s3_s7: opcodes and export prototypes. */
+-extern int
++extern int
+ s7_print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little);
+
+ struct score_opcode
+@@ -52,7 +52,7 @@ static struct score_opcode score_opcodes[] =
+ {
+ /* Score Instructions. */
+ {0x3800000a, 0x3e007fff, "abs\t\t%20-24r, %15-19r"},
+- {0x3800004b, 0x3e007fff, "abs.s\t\t%20-24r, %15-19r"},
++ {0x3800004b, 0x3e007fff, "abs.s\t\t%20-24r, %15-19r"},
+ {0x00000010, 0x3e0003ff, "add\t\t%20-24r, %15-19r, %10-14r"},
+ {0x00000011, 0x3e0003ff, "add.c\t\t%20-24r, %15-19r, %10-14r"},
+ {0x38000048, 0x3e0003ff, "add.s\t\t%20-24r, %15-19r, %10-14r"},
+@@ -190,36 +190,36 @@ static struct score_opcode score_opcodes[] =
+ {0x31e00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
+ {0x31f00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
+ {0x38000000, 0x3ff003ff, "mad\t\t%15-19r, %10-14r"},
+- {0x38000020, 0x3ff003ff, "madu\t\t%15-19r, %10-14r"},
++ {0x38000020, 0x3ff003ff, "madu\t\t%15-19r, %10-14r"},
+ {0x38000080, 0x3ff003ff, "mad.f\t\t%15-19r, %10-14r"},
+- {0x38000001, 0x3ff003ff, "msb\t\t%15-19r, %10-14r"},
++ {0x38000001, 0x3ff003ff, "msb\t\t%15-19r, %10-14r"},
+ {0x38000021, 0x3ff003ff, "msbu\t\t%15-19r, %10-14r"},
+ {0x38000081, 0x3ff003ff, "msb.f\t\t%15-19r, %10-14r"},
+- {0x38000102, 0x3ff003ff, "mazl\t\t%15-19r, %10-14r"},
+- {0x38000182, 0x3ff003ff, "mazl.f\t\t%15-19r, %10-14r"},
+- {0x38000002, 0x3ff003ff, "madl\t\t%15-19r, %10-14r"},
+- {0x380000c2, 0x3ff003ff, "madl.fs\t\t%15-19r, %10-14r"},
+- {0x38000303, 0x3ff003ff, "mazh\t\t%15-19r, %10-14r"},
+- {0x38000383, 0x3ff003ff, "mazh.f\t\t%15-19r, %10-14r"},
+- {0x38000203, 0x3ff003ff, "madh\t\t%15-19r, %10-14r"},
+- {0x380002c3, 0x3ff003ff, "madh.fs\t\t%15-19r, %10-14r"},
+- {0x38000007, 0x3e0003ff, "max\t\t%20-24r, %15-19r, %10-14r"},
+-
+- {0x00000064, 0x3e00007e, "mbitclr\t\t[%15-19r, %m], %10-14d"},
+- {0x0000006c, 0x3e00007e, "mbitset\t\t[%15-19r, %m], %10-14d"},
++ {0x38000102, 0x3ff003ff, "mazl\t\t%15-19r, %10-14r"},
++ {0x38000182, 0x3ff003ff, "mazl.f\t\t%15-19r, %10-14r"},
++ {0x38000002, 0x3ff003ff, "madl\t\t%15-19r, %10-14r"},
++ {0x380000c2, 0x3ff003ff, "madl.fs\t\t%15-19r, %10-14r"},
++ {0x38000303, 0x3ff003ff, "mazh\t\t%15-19r, %10-14r"},
++ {0x38000383, 0x3ff003ff, "mazh.f\t\t%15-19r, %10-14r"},
++ {0x38000203, 0x3ff003ff, "madh\t\t%15-19r, %10-14r"},
++ {0x380002c3, 0x3ff003ff, "madh.fs\t\t%15-19r, %10-14r"},
++ {0x38000007, 0x3e0003ff, "max\t\t%20-24r, %15-19r, %10-14r"},
++
++ {0x00000064, 0x3e00007e, "mbitclr\t\t[%15-19r, %m], %10-14d"},
++ {0x0000006c, 0x3e00007e, "mbitset\t\t[%15-19r, %m], %10-14d"},
+
+ {0x38000006, 0x3e0003ff, "min\t\t%20-24r, %15-19r, %10-14r"},
+- {0x38000104, 0x3ff003ff, "mszl\t\t%15-19r, %10-14r"},
+- {0x38000184, 0x3ff003ff, "mszl.f\t\t%15-19r, %10-14r"},
+- {0x38000004, 0x3ff003ff, "msbl\t\t%15-19r, %10-14r"},
++ {0x38000104, 0x3ff003ff, "mszl\t\t%15-19r, %10-14r"},
++ {0x38000184, 0x3ff003ff, "mszl.f\t\t%15-19r, %10-14r"},
++ {0x38000004, 0x3ff003ff, "msbl\t\t%15-19r, %10-14r"},
+ {0x380000c4, 0x3ff003ff, "msbl.fs\t\t%15-19r, %10-14r"},
+- {0x38000305, 0x3ff003ff, "mszh\t\t%15-19r, %10-14r"},
+- {0x38000385, 0x3ff003ff, "mszh.f\t\t%15-19r, %10-14r"},
+- {0x38000205, 0x3ff003ff, "msbh\t\t%15-19r, %10-14r"},
+- {0x380002c5, 0x3ff003ff, "msbh.fs\t\t%15-19r, %10-14r"},
+- {0x3800004e, 0x3e0003ff, "sll.s\t\t%20-24r, %15-19r, %10-14r"},
+- {0x38000049, 0x3e0003ff, "sub.s\t\t%20-24r, %15-19r, %10-14r"},
+- {0x0000001c, 0x3e007fff, "clz\t\t%20-24r, %15-19r"},
++ {0x38000305, 0x3ff003ff, "mszh\t\t%15-19r, %10-14r"},
++ {0x38000385, 0x3ff003ff, "mszh.f\t\t%15-19r, %10-14r"},
++ {0x38000205, 0x3ff003ff, "msbh\t\t%15-19r, %10-14r"},
++ {0x380002c5, 0x3ff003ff, "msbh.fs\t\t%15-19r, %10-14r"},
++ {0x3800004e, 0x3e0003ff, "sll.s\t\t%20-24r, %15-19r, %10-14r"},
++ {0x38000049, 0x3e0003ff, "sub.s\t\t%20-24r, %15-19r, %10-14r"},
++ {0x0000001c, 0x3e007fff, "clz\t\t%20-24r, %15-19r"},
+ {0x38000000, 0x3e000000, "ceinst\t\t%20-24d, %15-19r, %10-14r, %5-9d, %0-4d"},
+ {0x00000019, 0x3ff003ff, "cmpteq.c\t\t%15-19r, %10-14r"},
+ {0x00100019, 0x3ff003ff, "cmptmi.c\t\t%15-19r, %10-14r"},
+@@ -285,15 +285,15 @@ static struct score_opcode score_opcodes[] =
+ {0x0e000000, 0x3e000007, "lw\t\t%20-24r, [%15-19r]+, %3-14i"},
+ {0x00001000, 0x00007000, "lw!\t\t%8-11r, [%5-7r,%0-4d2]"},
+ {0x000000000002LL, 0x1c000000001fLL, "lw48\t\t%37-41r,[0x%7-36w]"},
+- {0x00007a00, 0x00007f00, "madl.fs!\t\t%4-7r, %0-3r"},
+- {0x00007500, 0x00007f00, "madu!\t\t%4-7r, %0-3r"},
++ {0x00007a00, 0x00007f00, "madl.fs!\t\t%4-7r, %0-3r"},
++ {0x00007500, 0x00007f00, "madu!\t\t%4-7r, %0-3r"},
+ {0x00007400, 0x00007f00, "mad.f!\t\t%4-7r, %0-3r"},
+- {0x00007900, 0x00007f00, "mazh.f!\t\t%4-7r, %0-3r"},
++ {0x00007900, 0x00007f00, "mazh.f!\t\t%4-7r, %0-3r"},
+ {0x00007800, 0x00007f00, "mazl.f!\t\t%4-7r, %0-3r"},
+ {0x00000448, 0x3e007fff, "mfcel\t\t%20-24r"},
+ {0x00007100, 0x00007ff0, "mfcel!\t\t%0-3r"},
+- {0x00000848, 0x3e007fff, "mfceh\t\t%20-24r"},
+- {0x00007110, 0x00007ff0, "mfceh!\t\t%0-3r"},
++ {0x00000848, 0x3e007fff, "mfceh\t\t%20-24r"},
++ {0x00007110, 0x00007ff0, "mfceh!\t\t%0-3r"},
+ {0x00000c48, 0x3e007fff, "mfcehl\t\t%20-24r, %15-19r"},
+ {0x00000048, 0x3e0003ff, "mfce\t\t%20-24r, er%10-14d"},
+ {0x00000050, 0x3e0003ff, "mfsr\t\t%20-24r, sr%10-14d"},
+@@ -311,7 +311,7 @@ static struct score_opcode score_opcodes[] =
+ {0x00006c00, 0x00007c00, "rpush!\t\t%5-9r, %0-4d"},
+ {0x00007600, 0x00007f00, "msb.f!\t\t%4-7r, %0-3r"},
+ {0x00007f00, 0x00007f00, "msbh.fs!\t\t%4-7r, %0-3r"},
+- {0x00007e00, 0x00007f00, "msbl.fs!\t\t%4-7r, %0-3r"},
++ {0x00007e00, 0x00007f00, "msbl.fs!\t\t%4-7r, %0-3r"},
+ {0x00007700, 0x00007f00, "msbu!\t\t%4-7r, %0-3r"},
+ {0x00007d00, 0x00007f00, "mszh.f!\t\t%4-7r, %0-3r"},
+ {0x00007c00, 0x00007f00, "mszl.f!\t\t%4-7r, %0-3r"},
+@@ -338,14 +338,14 @@ static struct score_opcode score_opcodes[] =
+ {0x00000341, 0x3e0003ff, "mulr.f\t\t%20-24r,%15-19r, %10-14r"},
+ {0x00000040, 0x3e0003ff, "maz\t\t%15-19r, %10-14r"},
+ {0x00000041, 0x3e0003ff, "mul.f\t\t%15-19r, %10-14r"},
+- {0x00000041, 0x3e0003ff, "maz.f\t\t%15-19r, %10-14r"},
++ {0x00000041, 0x3e0003ff, "maz.f\t\t%15-19r, %10-14r"},
+ {0x00007200, 0x00007f00, "mul.f!\t\t%4-7r, %0-3r"},
+ {0x00000042, 0x3e0003ff, "mulu\t\t%15-19r, %10-14r"},
+ {0x00000142, 0x3e0003ff, "mulur.l\t\t%20-24r,%15-19r, %10-14r"},
+ {0x00000242, 0x3e0003ff, "mulur.h\t\t%20-24r,%15-19r, %10-14r"},
+ {0x00000342, 0x3e0003ff, "mulur\t\t%20-24r,%15-19r, %10-14r"},
+ {0x00000042, 0x3e0003ff, "mazu\t\t%15-19r, %10-14r"},
+- {0x00007300, 0x00007f00, "mulu!\t\t%4-7r, %0-3r"},
++ {0x00007300, 0x00007f00, "mulu!\t\t%4-7r, %0-3r"},
+ {0x00000056, 0x3e007fff, "mvcs\t\t%20-24r, %15-19r"},
+ {0x00000456, 0x3e007fff, "mvcc\t\t%20-24r, %15-19r"},
+ {0x00000856, 0x3e007fff, "mvgtu\t\t%20-24r, %15-19r"},
+@@ -370,8 +370,8 @@ static struct score_opcode score_opcodes[] =
+ {0x00000000, 0x00007fff, "nop!"},
+ {0x00000022, 0x3e0003ff, "or\t\t%20-24r, %15-19r, %10-14r"},
+ {0x00000023, 0x3e0003ff, "or.c\t\t%20-24r, %15-19r, %10-14r"},
+- {0x020a0000, 0x3e0e0001, "ori\t\t%20-24r, 0x%1-16x"},
+- {0x020a0001, 0x3e0e0001, "ori.c\t\t%20-24r, 0x%1-16x"},
++ {0x020a0000, 0x3e0e0001, "ori\t\t%20-24r, 0x%1-16x"},
++ {0x020a0001, 0x3e0e0001, "ori.c\t\t%20-24r, 0x%1-16x"},
+ {0x0a0a0000, 0x3e0e0001, "oris\t\t%20-24r, 0x%1-16x"},
+ {0x0a0a0001, 0x3e0e0001, "oris.c\t\t%20-24r, 0x%1-16x"},
+ {0x1a000000, 0x3e000001, "orri\t\t%20-24r, %15-19r, 0x%1-14x"},
+@@ -589,7 +589,7 @@ print_insn_score48 (struct disassemble_info *info, bfd_vma given)
+ reg &= (2 << (bitend - bitstart)) - 1;
+ reg = ((reg ^ (1 << (bitend - bitstart))) -
+ (1 << (bitend - bitstart)));
+- /* Fix bug: s3_testsuite 64-bit.
++ /* Fix bug: s3_testsuite 64-bit.
+ Remove high 32 bits. */
+ reg = (int) reg;
+
+@@ -610,7 +610,7 @@ print_insn_score48 (struct disassemble_info *info, bfd_vma given)
+
+ reg = given >> bitstart;
+ reg &= (2 << (bitend - bitstart)) - 1;
+- /* Fix bug: s3_testsuite 64-bit.
++ /* Fix bug: s3_testsuite 64-bit.
+ Remove high 32 bits. */
+ reg = (int) reg;
+
+@@ -626,7 +626,7 @@ print_insn_score48 (struct disassemble_info *info, bfd_vma given)
+ func (stream, "%lx", reg);
+ }
+ break;
+-
++
+ default:
+ abort ();
+ }
+@@ -662,7 +662,7 @@ print_insn_score48 (struct disassemble_info *info, bfd_vma given)
+ func (stream, _("<illegal instruction>"));
+ return 6;
+ #endif
+-
++
+ abort ();
+ }
+
+@@ -682,7 +682,7 @@ print_insn_score32 (bfd_vma pc, struct disassemble_info *info, long given)
+ {
+ /* check for bcmpeq / bcmpeqz / bcmpne / bcmpnez */
+ /* given &0x7c00 is for to test if rb is zero ,
+- rb_equal_zero =1 : index to bcmpeqz
++ rb_equal_zero =1 : index to bcmpeqz
+ rb_equal_zero =0 , index to bcmpeq
+ this checking rule only for branch compare ( insn->mask ==0x3e00007e*/
+ if (((given & 0x7c00) !=0)&&(rb_equal_zero ==1)&&(insn->mask == 0x3e00007e)
+@@ -691,7 +691,7 @@ print_insn_score32 (bfd_vma pc, struct disassemble_info *info, long given)
+ rb_equal_zero =0;
+ continue;
+ }
+-
++
+ char *c;
+
+ for (c = insn->assembler; *c; c++)
+@@ -743,9 +743,9 @@ print_insn_score32 (bfd_vma pc, struct disassemble_info *info, long given)
+ int target = (pc + SEXT10 (disp));
+ func (stream, "%s ,", score_regnames[reg] );
+ (*info->print_address_func) (target, info);
+-
++
+ }
+-
++
+ }
+ break;
+ case 'm':
+@@ -1030,7 +1030,7 @@ print_insn_score16 (bfd_vma pc, struct disassemble_info *info, long given)
+ func (stream, _("<illegal instruction>"));
+ return 2;
+ #endif
+-
++
+ /* No match. */
+ abort ();
+ }
+@@ -1077,7 +1077,7 @@ s3_print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
+ if ((given & 0x8000)==0)
+ return print_insn_score16 (pc, info, given);
+
+- else
++ else
+ {
+ if (little)
+ {
+@@ -1120,7 +1120,7 @@ s3_print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
+ given_l = ((bfd_vma)b[5]) | ((bfd_vma)b[4] << 8) | ((bfd_vma)b[3] << 16) | ((bfd_vma)b[2] << 24) ;
+ given_h = ((bfd_vma)b[1] )|((bfd_vma)b[0] <<8);
+ given = ((bfd_vma)given_h<<32) | (bfd_vma)given_l ;
+-
++
+ }
+
+ /* Set given_48. */
+@@ -1205,4 +1205,4 @@ print_insn_little_score (bfd_vma pc ATTRIBUTE_UNUSED,
+ {
+ abort ();
+ }
+-#endif
++#endif
+#--- a/opcodes/score-opc.h
+#+++ b/opcodes/score-opc.h
+#@@ -1,5 +1,5 @@
+# /* Copyright (C) 2006-2015 Free Software Foundation, Inc.
+#-
+#+
+# This file is part of the GNU opcodes library.
+#
+# This library is free software; you can redistribute it and/or modify
+#@@ -31,7 +31,7 @@ static struct score_opcode score_opcodes[] =
+# {
+# /* Score Instructions. */
+# {0x3800000a, 0x3e007fff, "abs\t\t%20-24r, %15-19r"},
+#- {0x3800004b, 0x3e007fff, "abs.s\t\t%20-24r, %15-19r"},
+#+ {0x3800004b, 0x3e007fff, "abs.s\t\t%20-24r, %15-19r"},
+# {0x00000010, 0x3e0003ff, "add\t\t%20-24r, %15-19r, %10-14r"},
+# {0x00000011, 0x3e0003ff, "add.c\t\t%20-24r, %15-19r, %10-14r"},
+# {0x38000048, 0x3e0003ff, "add.s\t\t%20-24r, %15-19r, %10-14r"},
+#@@ -169,36 +169,36 @@ static struct score_opcode score_opcodes[] =
+# {0x31e00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
+# {0x31f00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
+# {0x38000000, 0x3ff003ff, "mad\t\t%15-19r, %10-14r"},
+#- {0x38000020, 0x3ff003ff, "madu\t\t%15-19r, %10-14r"},
+#+ {0x38000020, 0x3ff003ff, "madu\t\t%15-19r, %10-14r"},
+# {0x38000080, 0x3ff003ff, "mad.f\t\t%15-19r, %10-14r"},
+#- {0x38000001, 0x3ff003ff, "msb\t\t%15-19r, %10-14r"},
+#+ {0x38000001, 0x3ff003ff, "msb\t\t%15-19r, %10-14r"},
+# {0x38000021, 0x3ff003ff, "msbu\t\t%15-19r, %10-14r"},
+# {0x38000081, 0x3ff003ff, "msb.f\t\t%15-19r, %10-14r"},
+#- {0x38000102, 0x3ff003ff, "mazl\t\t%15-19r, %10-14r"},
+#- {0x38000182, 0x3ff003ff, "mazl.f\t\t%15-19r, %10-14r"},
+#- {0x38000002, 0x3ff003ff, "madl\t\t%15-19r, %10-14r"},
+#- {0x380000c2, 0x3ff003ff, "madl.fs\t\t%15-19r, %10-14r"},
+#- {0x38000303, 0x3ff003ff, "mazh\t\t%15-19r, %10-14r"},
+#- {0x38000383, 0x3ff003ff, "mazh.f\t\t%15-19r, %10-14r"},
+#- {0x38000203, 0x3ff003ff, "madh\t\t%15-19r, %10-14r"},
+#- {0x380002c3, 0x3ff003ff, "madh.fs\t\t%15-19r, %10-14r"},
+#- {0x38000007, 0x3e0003ff, "max\t\t%20-24r, %15-19r, %10-14r"},
+#+ {0x38000102, 0x3ff003ff, "mazl\t\t%15-19r, %10-14r"},
+#+ {0x38000182, 0x3ff003ff, "mazl.f\t\t%15-19r, %10-14r"},
+#+ {0x38000002, 0x3ff003ff, "madl\t\t%15-19r, %10-14r"},
+#+ {0x380000c2, 0x3ff003ff, "madl.fs\t\t%15-19r, %10-14r"},
+#+ {0x38000303, 0x3ff003ff, "mazh\t\t%15-19r, %10-14r"},
+#+ {0x38000383, 0x3ff003ff, "mazh.f\t\t%15-19r, %10-14r"},
+#+ {0x38000203, 0x3ff003ff, "madh\t\t%15-19r, %10-14r"},
+#+ {0x380002c3, 0x3ff003ff, "madh.fs\t\t%15-19r, %10-14r"},
+#+ {0x38000007, 0x3e0003ff, "max\t\t%20-24r, %15-19r, %10-14r"},
+#
+#- {0x00000064, 0x3e00007e, "mbitclr\t\t[%15-19r, %m], %10-14d"},
+#- {0x0000006c, 0x3e00007e, "mbitset\t\t[%20-24r, %m], %10-14d"},
+#+ {0x00000064, 0x3e00007e, "mbitclr\t\t[%15-19r, %m], %10-14d"},
+#+ {0x0000006c, 0x3e00007e, "mbitset\t\t[%20-24r, %m], %10-14d"},
+#
+# {0x38000006, 0x3e0003ff, "min\t\t%20-24r, %15-19r, %10-14r"},
+#- {0x38000104, 0x3ff003ff, "mszl\t\t%15-19r, %10-14r"},
+#- {0x38000184, 0x3ff003ff, "mszl.f\t\t%15-19r, %10-14r"},
+#- {0x38000004, 0x3ff003ff, "msbl\t\t%15-19r, %10-14r"},
+#+ {0x38000104, 0x3ff003ff, "mszl\t\t%15-19r, %10-14r"},
+#+ {0x38000184, 0x3ff003ff, "mszl.f\t\t%15-19r, %10-14r"},
+#+ {0x38000004, 0x3ff003ff, "msbl\t\t%15-19r, %10-14r"},
+# {0x380000c4, 0x3ff003ff, "msbl.fs\t\t%15-19r, %10-14r"},
+#- {0x38000305, 0x3ff003ff, "mszh\t\t%15-19r, %10-14r"},
+#- {0x38000385, 0x3ff003ff, "mszh.f\t\t%15-19r, %10-14r"},
+#- {0x38000205, 0x3ff003ff, "msbh\t\t%15-19r, %10-14r"},
+#- {0x380002c5, 0x3ff003ff, "msbh.fs\t\t%15-19r, %10-14r"},
+#- {0x3800004e, 0x3e0003ff, "sll.s\t\t%20-24r, %15-19r, %10-14r"},
+#- {0x38000049, 0x3e0003ff, "sub.s\t\t%20-24r, %15-19r, %10-14r"},
+#- {0x0000001c, 0x3e007fff, "clz\t\t%20-24r, %15-19r"},
+#+ {0x38000305, 0x3ff003ff, "mszh\t\t%15-19r, %10-14r"},
+#+ {0x38000385, 0x3ff003ff, "mszh.f\t\t%15-19r, %10-14r"},
+#+ {0x38000205, 0x3ff003ff, "msbh\t\t%15-19r, %10-14r"},
+#+ {0x380002c5, 0x3ff003ff, "msbh.fs\t\t%15-19r, %10-14r"},
+#+ {0x3800004e, 0x3e0003ff, "sll.s\t\t%20-24r, %15-19r, %10-14r"},
+#+ {0x38000049, 0x3e0003ff, "sub.s\t\t%20-24r, %15-19r, %10-14r"},
+#+ {0x0000001c, 0x3e007fff, "clz\t\t%20-24r, %15-19r"},
+# {0x38000000, 0x3e000000, "ceinst\t\t%20-24d, %15-19r, %10-14r, %5-9d, %0-4d"},
+# {0x00000019, 0x3ff003ff, "cmpteq.c\t\t%15-19r, %10-14r"},
+# {0x00100019, 0x3ff003ff, "cmptmi.c\t\t%15-19r, %10-14r"},
+#@@ -264,16 +264,16 @@ static struct score_opcode score_opcodes[] =
+# {0x0e000000, 0x3e000007, "lw\t\t%20-24r, [%15-19r]+, %3-14i"},
+# {0x00001000, 0x00007000, "lw!\t\t%8-11r, [%5-7r,%0-4d2]"},
+# {0x000000000002LL, 0x1c000000001fLL, "lw48\t\t%37-41r,[0x%7-36w]"},
+#- {0x00007b00, 0x00007f00, "madh.fs!\t\t%8-11r, %4-7r"},
+#- {0x00007a00, 0x00007f00, "madl.fs!\t\t%8-11r, %4-7r"},
+#- {0x00007500, 0x00007f00, "madu!\t\t%8-11r, %4-7r"},
+#+ {0x00007b00, 0x00007f00, "madh.fs!\t\t%8-11r, %4-7r"},
+#+ {0x00007a00, 0x00007f00, "madl.fs!\t\t%8-11r, %4-7r"},
+#+ {0x00007500, 0x00007f00, "madu!\t\t%8-11r, %4-7r"},
+# {0x00007400, 0x00007f00, "mad.f!\t\t%8-11r, %4-7r"},
+#- {0x00007900, 0x00007f00, "mazh.f!\t\t%8-11r, %4-7r"},
+#+ {0x00007900, 0x00007f00, "mazh.f!\t\t%8-11r, %4-7r"},
+# {0x00007800, 0x00007f00, "mazl.f!\t\t%8-11r, %4-7r"},
+# {0x00000448, 0x3e007fff, "mfcel\t\t%20-24r"},
+# {0x00007100, 0x00007ff0, "mfcel!\t\t%4-7r"},
+#- {0x00000848, 0x3e007fff, "mfceh\t\t%20-24r"},
+#- {0x00007110, 0x00007ff0, "mfceh!\t\t%4-7r"},
+#+ {0x00000848, 0x3e007fff, "mfceh\t\t%20-24r"},
+#+ {0x00007110, 0x00007ff0, "mfceh!\t\t%4-7r"},
+# {0x00000c48, 0x3e007fff, "mfcehl\t\t%20-24r, %15-19r"},
+# {0x00000048, 0x3e0003ff, "mfce\t\t%20-24r, er%10-14d"},
+# {0x00000050, 0x3e0003ff, "mfsr\t\t%20-24r, sr%10-14d"},
+#@@ -291,7 +291,7 @@ static struct score_opcode score_opcodes[] =
+# {0x00006c00, 0x00007c00, "rpush!\t\t%5-9r, %0-4d"},
+# {0x00007600, 0x00007f00, "msb.f!\t\t%8-11r, %4-7r"},
+# {0x00007f00, 0x00007f00, "msbh.fs!\t\t%8-11r, %4-7r"},
+#- {0x00007e00, 0x00007f00, "msbl.fs!\t\t%8-11r, %4-7r"},
+#+ {0x00007e00, 0x00007f00, "msbl.fs!\t\t%8-11r, %4-7r"},
+# {0x00007700, 0x00007f00, "msbu!\t\t%8-11r, %4-7r"},
+# {0x00007d00, 0x00007f00, "mszh.f!\t\t%8-11r, %4-7r"},
+# {0x00007c00, 0x00007f00, "mszl.f!\t\t%8-11r, %4-7r"},
+#@@ -318,14 +318,14 @@ static struct score_opcode score_opcodes[] =
+# {0x00000241, 0x3e0003ff, "mulr.hf\t\t%20-24r,%15-19r, %10-14r"},
+# {0x00000341, 0x3e0003ff, "mulr.f\t\t%20-24r,%15-19r, %10-14r"},
+# {0x00000040, 0x3e0003ff, "maz\t\t%15-19r, %10-14r"},
+#- {0x00000041, 0x3e0003ff, "maz.f\t\t%15-19r, %10-14r"},
+#+ {0x00000041, 0x3e0003ff, "maz.f\t\t%15-19r, %10-14r"},
+# {0x00007200, 0x00007f00, "mul.f!\t\t%8-11r, %4-7r"},
+# {0x00000042, 0x3e0003ff, "mulu\t\t%15-19r, %10-14r"},
+# {0x00000142, 0x3e0003ff, "mulur.l\t\t%20-24r,%15-19r, %10-14r"},
+# {0x00000242, 0x3e0003ff, "mulur.h\t\t%20-24r,%15-19r, %10-14r"},
+# {0x00000342, 0x3e0003ff, "mulur\t\t%20-24r,%15-19r, %10-14r"},
+# {0x00000042, 0x3e0003ff, "mazu\t\t%15-19r, %10-14r"},
+#- {0x00007300, 0x00007f00, "mulu!\t\t%8-11r, %4-7r"},
+#+ {0x00007300, 0x00007f00, "mulu!\t\t%8-11r, %4-7r"},
+# {0x00000056, 0x3e007fff, "mvcs\t\t%20-24r, %15-19r"},
+# {0x00000456, 0x3e007fff, "mvcc\t\t%20-24r, %15-19r"},
+# {0x00000856, 0x3e007fff, "mvgtu\t\t%20-24r, %15-19r"},
+#@@ -350,8 +350,8 @@ static struct score_opcode score_opcodes[] =
+# {0x00000000, 0x00007fff, "nop!"},
+# {0x00000022, 0x3e0003ff, "or\t\t%20-24r, %15-19r, %10-14r"},
+# {0x00000023, 0x3e0003ff, "or.c\t\t%20-24r, %15-19r, %10-14r"},
+#- {0x020a0000, 0x3e0e0001, "ori\t\t%20-24r, 0x%1-16x"},
+#- {0x020a0001, 0x3e0e0001, "ori.c\t\t%20-24r, 0x%1-16x"},
+#+ {0x020a0000, 0x3e0e0001, "ori\t\t%20-24r, 0x%1-16x"},
+#+ {0x020a0001, 0x3e0e0001, "ori.c\t\t%20-24r, 0x%1-16x"},
+# {0x0a0a0000, 0x3e0e0001, "oris\t\t%20-24r, 0x%1-16x"},
+# {0x0a0a0001, 0x3e0e0001, "oris.c\t\t%20-24r, 0x%1-16x"},
+# {0x1a000000, 0x3e000001, "orri\t\t%20-24r, %15-19r, 0x%1-14x"},
+#@@ -381,7 +381,7 @@ static struct score_opcode score_opcodes[] =
+# {0x0000006a, 0x3e0003ff, "scw\t\t%20-24r, [%15-19r]+"},
+# {0x0000006e, 0x3e0003ff, "sce\t\t[%15-19r]+"},
+# {0x00000006, 0x3e0003ff, "sdbbp\t\t%15-19d"},
+#- {0x00000020, 0x00007fe0, "sdbbp!\t\t%0-4d"},
+#+ {0x00000020, 0x00007fe0, "sdbbp!\t\t%0-4d"},
+# {0x000000000000LL, 0x1c000000001fLL, "sdbbp48\t\t%5-9d"},
+# {0x2a000000, 0x3e000000, "sh\t\t%20-24r, [%15-19r, %0-14i]"},
+# {0x06000005, 0x3e000007, "sh\t\t%20-24r, [%15-19r, %3-14i]+"},
+--- a/opcodes/score7-dis.c
++++ b/opcodes/score7-dis.c
+@@ -59,7 +59,7 @@ static struct score_opcode score_opcodes[] =
+ {
+ /* Score Instructions. */
+ {0x3800000a, 0x3e007fff, "abs\t\t%20-24r, %15-19r"},
+- {0x3800004b, 0x3e007fff, "abs.s\t\t%20-24r, %15-19r"},
++ {0x3800004b, 0x3e007fff, "abs.s\t\t%20-24r, %15-19r"},
+ {0x00000010, 0x3e0003ff, "add\t\t%20-24r, %15-19r, %10-14r"},
+ {0x00000011, 0x3e0003ff, "add.c\t\t%20-24r, %15-19r, %10-14r"},
+ {0x38000048, 0x3e0003ff, "add.s\t\t%20-24r, %15-19r, %10-14r"},
+@@ -226,32 +226,32 @@ static struct score_opcode score_opcodes[] =
+ {0x31e00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
+ {0x31f00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
+ {0x38000000, 0x3ff003ff, "mad\t\t%15-19r, %10-14r"},
+- {0x38000020, 0x3ff003ff, "madu\t\t%15-19r, %10-14r"},
++ {0x38000020, 0x3ff003ff, "madu\t\t%15-19r, %10-14r"},
+ {0x38000080, 0x3ff003ff, "mad.f\t\t%15-19r, %10-14r"},
+- {0x38000001, 0x3ff003ff, "msb\t\t%15-19r, %10-14r"},
++ {0x38000001, 0x3ff003ff, "msb\t\t%15-19r, %10-14r"},
+ {0x38000021, 0x3ff003ff, "msbu\t\t%15-19r, %10-14r"},
+ {0x38000081, 0x3ff003ff, "msb.f\t\t%15-19r, %10-14r"},
+- {0x38000102, 0x3ff003ff, "mazl\t\t%15-19r, %10-14r"},
+- {0x38000182, 0x3ff003ff, "mazl.f\t\t%15-19r, %10-14r"},
+- {0x38000002, 0x3ff003ff, "madl\t\t%15-19r, %10-14r"},
+- {0x380000c2, 0x3ff003ff, "madl.fs\t\t%15-19r, %10-14r"},
+- {0x38000303, 0x3ff003ff, "mazh\t\t%15-19r, %10-14r"},
+- {0x38000383, 0x3ff003ff, "mazh.f\t\t%15-19r, %10-14r"},
+- {0x38000203, 0x3ff003ff, "madh\t\t%15-19r, %10-14r"},
+- {0x380002c3, 0x3ff003ff, "madh.fs\t\t%15-19r, %10-14r"},
+- {0x38000007, 0x3e0003ff, "max\t\t%20-24r, %15-19r, %10-14r"},
++ {0x38000102, 0x3ff003ff, "mazl\t\t%15-19r, %10-14r"},
++ {0x38000182, 0x3ff003ff, "mazl.f\t\t%15-19r, %10-14r"},
++ {0x38000002, 0x3ff003ff, "madl\t\t%15-19r, %10-14r"},
++ {0x380000c2, 0x3ff003ff, "madl.fs\t\t%15-19r, %10-14r"},
++ {0x38000303, 0x3ff003ff, "mazh\t\t%15-19r, %10-14r"},
++ {0x38000383, 0x3ff003ff, "mazh.f\t\t%15-19r, %10-14r"},
++ {0x38000203, 0x3ff003ff, "madh\t\t%15-19r, %10-14r"},
++ {0x380002c3, 0x3ff003ff, "madh.fs\t\t%15-19r, %10-14r"},
++ {0x38000007, 0x3e0003ff, "max\t\t%20-24r, %15-19r, %10-14r"},
+ {0x38000006, 0x3e0003ff, "min\t\t%20-24r, %15-19r, %10-14r"},
+- {0x38000104, 0x3ff003ff, "mszl\t\t%15-19r, %10-14r"},
+- {0x38000184, 0x3ff003ff, "mszl.f\t\t%15-19r, %10-14r"},
+- {0x38000004, 0x3ff003ff, "msbl\t\t%15-19r, %10-14r"},
++ {0x38000104, 0x3ff003ff, "mszl\t\t%15-19r, %10-14r"},
++ {0x38000184, 0x3ff003ff, "mszl.f\t\t%15-19r, %10-14r"},
++ {0x38000004, 0x3ff003ff, "msbl\t\t%15-19r, %10-14r"},
+ {0x380000c4, 0x3ff003ff, "msbl.fs\t\t%15-19r, %10-14r"},
+- {0x38000305, 0x3ff003ff, "mszh\t\t%15-19r, %10-14r"},
+- {0x38000385, 0x3ff003ff, "mszh.f\t\t%15-19r, %10-14r"},
+- {0x38000205, 0x3ff003ff, "msbh\t\t%15-19r, %10-14r"},
+- {0x380002c5, 0x3ff003ff, "msbh.fs\t\t%15-19r, %10-14r"},
+- {0x3800004e, 0x3e0003ff, "sll.s\t\t%20-24r, %15-19r, %10-14r"},
+- {0x38000049, 0x3e0003ff, "sub.s\t\t%20-24r, %15-19r, %10-14r"},
+- {0x3800000d, 0x3e007fff, "clz\t\t%20-24r, %15-19r"},
++ {0x38000305, 0x3ff003ff, "mszh\t\t%15-19r, %10-14r"},
++ {0x38000385, 0x3ff003ff, "mszh.f\t\t%15-19r, %10-14r"},
++ {0x38000205, 0x3ff003ff, "msbh\t\t%15-19r, %10-14r"},
++ {0x380002c5, 0x3ff003ff, "msbh.fs\t\t%15-19r, %10-14r"},
++ {0x3800004e, 0x3e0003ff, "sll.s\t\t%20-24r, %15-19r, %10-14r"},
++ {0x38000049, 0x3e0003ff, "sub.s\t\t%20-24r, %15-19r, %10-14r"},
++ {0x3800000d, 0x3e007fff, "clz\t\t%20-24r, %15-19r"},
+ {0x38000000, 0x3e000000, "ceinst\t\t%20-24d, %15-19r, %10-14r, %5-9d, %0-4d"},
+ {0x00000019, 0x3ff003ff, "cmpteq.c\t\t%15-19r, %10-14r"},
+ {0x00100019, 0x3ff003ff, "cmptmi.c\t\t%15-19r, %10-14r"},
+@@ -310,16 +310,16 @@ static struct score_opcode score_opcodes[] =
+ {0x0e000000, 0x3e000007, "lw\t\t%20-24r, [%15-19r]+, %3-14i"},
+ {0x00002008, 0x0000700f, "lw!\t\t%8-11r, [%4-7r]"},
+ {0x00007000, 0x00007007, "lwp!\t\t%8-11r, %3-7d2"},
+- {0x0000100b, 0x0000700f, "madh.fs!\t\t%8-11r, %4-7r"},
+- {0x0000100a, 0x0000700f, "madl.fs!\t\t%8-11r, %4-7r"},
+- {0x00001005, 0x0000700f, "madu!\t\t%8-11r, %4-7r"},
++ {0x0000100b, 0x0000700f, "madh.fs!\t\t%8-11r, %4-7r"},
++ {0x0000100a, 0x0000700f, "madl.fs!\t\t%8-11r, %4-7r"},
++ {0x00001005, 0x0000700f, "madu!\t\t%8-11r, %4-7r"},
+ {0x00001004, 0x0000700f, "mad.f!\t\t%8-11r, %4-7r"},
+- {0x00001009, 0x0000700f, "mazh.f!\t\t%8-11r, %4-7r"},
++ {0x00001009, 0x0000700f, "mazh.f!\t\t%8-11r, %4-7r"},
+ {0x00001008, 0x0000700f, "mazl.f!\t\t%8-11r, %4-7r"},
+ {0x00000448, 0x3e007fff, "mfcel\t\t%20-24r"},
+ {0x00001001, 0x00007f0f, "mfcel!\t\t%4-7r"},
+- {0x00000848, 0x3e007fff, "mfceh\t\t%20-24r"},
+- {0x00001101, 0x00007f0f, "mfceh!\t\t%4-7r"},
++ {0x00000848, 0x3e007fff, "mfceh\t\t%20-24r"},
++ {0x00001101, 0x00007f0f, "mfceh!\t\t%4-7r"},
+ {0x00000c48, 0x3e007fff, "mfcehl\t\t%20-24r, %15-19r"},
+ {0x00000048, 0x3e0003ff, "mfce\t\t%20-24r, er%10-14d"},
+ {0x00000050, 0x3e0003ff, "mfsr\t\t%20-24r, sr%10-14d"},
+@@ -331,10 +331,10 @@ static struct score_opcode score_opcodes[] =
+ {0x0c000017, 0x3e00001f, "mfcc2\t\t%20-24r, c%15-19r"},
+ {0x0c00001f, 0x3e00001f, "mfcc3\t\t%20-24r, c%15-19r"},
+ {0x00000002, 0x0000700f, "mhfl!\t\t%8-11R, %4-7r"},
+- {0x00000001, 0x0000700f, "mlfh!\t\t%8-11r, %4-7R"},
++ {0x00000001, 0x0000700f, "mlfh!\t\t%8-11r, %4-7R"},
+ {0x00001006, 0x0000700f, "msb.f!\t\t%8-11r, %4-7r"},
+ {0x0000100f, 0x0000700f, "msbh.fs!\t\t%8-11r, %4-7r"},
+- {0x0000100e, 0x0000700f, "msbl.fs!\t\t%8-11r, %4-7r"},
++ {0x0000100e, 0x0000700f, "msbl.fs!\t\t%8-11r, %4-7r"},
+ {0x00001007, 0x0000700f, "msbu!\t\t%8-11r, %4-7r"},
+ {0x0000100d, 0x0000700f, "mszh.f!\t\t%8-11r, %4-7r"},
+ {0x0000100c, 0x0000700f, "mszl.f!\t\t%8-11r, %4-7r"},
+@@ -355,11 +355,11 @@ static struct score_opcode score_opcodes[] =
+ {0x00000040, 0x3e0003ff, "mul\t\t%15-19r, %10-14r"},
+ {0x00000040, 0x3e0003ff, "maz\t\t%15-19r, %10-14r"},
+ {0x00000041, 0x3e0003ff, "mul.f\t\t%15-19r, %10-14r"},
+- {0x00000041, 0x3e0003ff, "maz.f\t\t%15-19r, %10-14r"},
++ {0x00000041, 0x3e0003ff, "maz.f\t\t%15-19r, %10-14r"},
+ {0x00001002, 0x0000700f, "mul.f!\t\t%8-11r, %4-7r"},
+ {0x00000042, 0x3e0003ff, "mulu\t\t%15-19r, %10-14r"},
+ {0x00000042, 0x3e0003ff, "mazu\t\t%15-19r, %10-14r"},
+- {0x00001003, 0x0000700f, "mulu!\t\t%8-11r, %4-7r"},
++ {0x00001003, 0x0000700f, "mulu!\t\t%8-11r, %4-7r"},
+ {0x00000056, 0x3e007fff, "mvcs\t\t%20-24r, %15-19r"},
+ {0x00000456, 0x3e007fff, "mvcc\t\t%20-24r, %15-19r"},
+ {0x00000856, 0x3e007fff, "mvgtu\t\t%20-24r, %15-19r"},
+@@ -386,8 +386,8 @@ static struct score_opcode score_opcodes[] =
+ {0x00002006, 0x0000700f, "not!\t\t%8-11r, %4-7r"},
+ {0x00000022, 0x3e0003ff, "or\t\t%20-24r, %15-19r, %10-14r"},
+ {0x00000023, 0x3e0003ff, "or.c\t\t%20-24r, %15-19r, %10-14r"},
+- {0x020a0000, 0x3e0e0001, "ori\t\t%20-24r, 0x%1-16x"},
+- {0x020a0001, 0x3e0e0001, "ori.c\t\t%20-24r, 0x%1-16x"},
++ {0x020a0000, 0x3e0e0001, "ori\t\t%20-24r, 0x%1-16x"},
++ {0x020a0001, 0x3e0e0001, "ori.c\t\t%20-24r, 0x%1-16x"},
+ {0x0a0a0000, 0x3e0e0001, "oris\t\t%20-24r, 0x%1-16x"},
+ {0x0a0a0001, 0x3e0e0001, "oris.c\t\t%20-24r, 0x%1-16x"},
+ {0x1a000000, 0x3e000001, "orri\t\t%20-24r, %15-19r, 0x%1-14x"},
+@@ -537,7 +537,7 @@ static unsigned int regname_selected = 0;
+ #define score_regnames regnames[regname_selected].reg_names
+
+ /* s3_s7: opcodes and export prototypes. */
+-int
++int
+ s7_print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little);
+
+ /* Print one instruction from PC on INFO->STREAM.
+--- a/opcodes/sh-dis.c
++++ b/opcodes/sh-dis.c
+@@ -152,7 +152,7 @@ print_insn_ddt (int insn, struct disassemble_info *info)
+ while (op->nibbles[2] != (unsigned) ((insn >> 4) & 3)
+ || op->nibbles[3] != (unsigned) (insn & 0xf))
+ op++;
+-
++
+ print_movxy (op,
+ (4 * ((insn & (is_movy ? 0x200 : 0x100)) == 0)
+ + 2 * is_movy
+--- a/opcodes/sh-opc.h
++++ b/opcodes/sh-opc.h
+@@ -285,7 +285,7 @@ bfd_boolean sh_merge_bfd_arch (bfd *ibfd, bfd *obfd);
+
+ /* Below are the 'architecture sets'.
+ They describe the following inheritance graph:
+-
++
+ SH1
+ |
+ SH2
+@@ -529,7 +529,7 @@ const sh_opcode_info sh_table[] =
+ /* 0100nnnn10111010 lds <REG_N>,Y1 */{"lds",{A_REG_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up},
+
+ /* 0100nnnn01011010 lds <REG_N>,FPUL */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up},
+-
++
+ /* 0100nnnn01101010 lds <REG_M>,FPSCR */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up},
+
+ /* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up},
+@@ -551,7 +551,7 @@ const sh_opcode_info sh_table[] =
+ /* 0100nnnn10110110 lds.l @<REG_N>+,Y1 */{"lds.l",{A_INC_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_6}, arch_sh_dsp_up},
+
+ /* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up},
+-
++
+ /* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up},
+
+ /* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up},
+@@ -804,7 +804,7 @@ const sh_opcode_info sh_table[] =
+ /* 0000nnnn10111010 sts Y1,<REG_N> */{"sts",{A_Y1,A_REG_N},{HEX_0,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up},
+
+ /* 0000nnnn01011010 sts FPUL,<REG_N> */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up},
+-
++
+ /* 0000nnnn01101010 sts FPSCR,<REG_N> */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up},
+
+ /* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up},
+@@ -826,7 +826,7 @@ const sh_opcode_info sh_table[] =
+ /* 0100nnnn10110110 sts.l Y1,@-<REG_N> */{"sts.l",{A_Y1,A_DEC_N},{HEX_4,REG_N,HEX_B,HEX_2}, arch_sh_dsp_up},
+
+ /* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up},
+-
++
+ /* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up},
+
+ /* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up},
+@@ -1194,7 +1194,7 @@ const sh_opcode_info sh_table[] =
+ /* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */
+ {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32},
+
+-{ 0, {0}, {0}, 0 }
++{ 0, {0}, {0}, 0 }
+ };
+
+ #endif
+--- a/opcodes/sh64-opc.c
++++ b/opcodes/sh64-opc.c
+@@ -33,7 +33,7 @@ const shmedia_opcode_info shmedia_table[] = {
+ { "add.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x00080000
+ },
+ /* 110100mmmmmmssssssssssdddddd0000 addi <A_GREG_M>,<A_IMMS10>,<A_GREG_D> */
+- { "addi", {A_GREG_M,A_IMMS10BY1,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4},
++ { "addi", {A_GREG_M,A_IMMS10BY1,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4},
+ SHMEDIA_ADDI_OPC
+ },
+ /* 110101mmmmmmssssssssssdddddd0000 addi.l <A_GREG_M>,<A_IMMS10>,<A_GREG_D> */
+#--- a/opcodes/sparc-dis.c
+#+++ b/opcodes/sparc-dis.c
+#@@ -94,7 +94,7 @@ static char *v9_priv_reg_names[] =
+# static char *v9_hpriv_reg_names[] =
+# {
+# "hpstate", "htstate", "resv2", "hintp", "resv4", "htba", "hver",
+#- "resv7", "resv8", "resv9", "resv10", "resv11", "resv12", "resv13",
+#+ "resv7", "resv8", "resv9", "resv10", "resv11", "resv12", "resv13",
+# "resv14", "resv15", "resv16", "resv17", "resv18", "resv19", "resv20",
+# "resv21", "resv22", "resv23", "resv24", "resv25", "resv26", "resv27",
+# "hstick_offset", "hstick_enable", "resv30", "hstick_cmpr"
+--- a/opcodes/spu-opc.c
++++ b/opcodes/spu-opc.c
+@@ -26,9 +26,9 @@
+
+ /*
+ Example contents of spu-insn.h
+- id_tag mode mode type opcode mnemonic asmtype dependency FPU L/S? branch? instruction
+- QUAD WORD (0,RC,RB,RA,RT) latency
+- APUOP(M_LQD, 1, 0, RI9, 0x1f8, "lqd", ASM_RI9IDX, 00012, FXU, 1, 0) Load Quadword d-form
++ id_tag mode mode type opcode mnemonic asmtype dependency FPU L/S? branch? instruction
++ QUAD WORD (0,RC,RB,RA,RT) latency
++ APUOP(M_LQD, 1, 0, RI9, 0x1f8, "lqd", ASM_RI9IDX, 00012, FXU, 1, 0) Load Quadword d-form
+ */
+
+ const struct spu_opcode spu_opcodes[] = {
+--- a/opcodes/tic80-opc.c
++++ b/opcodes/tic80-opc.c
+@@ -256,7 +256,7 @@ tic80_symbol_to_value (name, symbol_class)
+ {
+ low = middle + 1;
+ }
+- else
++ else
+ {
+ pdsp = &tic80_predefined_symbols[middle];
+ if ((symbol_class == 0) || (symbol_class & PDS_VALUE (pdsp)))
+--- a/opcodes/v850-opc.c
++++ b/opcodes/v850-opc.c
+@@ -1385,15 +1385,15 @@ const struct v850_opcode v850_opcodes[] =
+ { "bgt", two (0x07ef, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
+ { "ble", two (0x07e7, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
+ { "blt", two (0x07e6, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
+-/* Unsigned integer. */
++/* Unsigned integer. */
+ { "bh", two (0x07eb, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
+ { "bl", two (0x07e1, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
+ { "bnh", two (0x07e3, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
+ { "bnl", two (0x07e9, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
+-/* Common. */
++/* Common. */
+ { "be", two (0x07e2, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
+ { "bne", two (0x07ea, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
+-/* Others. */
++/* Others. */
+ { "bc", two (0x07e1, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
+ { "bf", two (0x07ea, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
+ { "bn", two (0x07e4, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
+@@ -1522,7 +1522,7 @@ const struct v850_opcode v850_opcodes[] =
+
+ { "hvcall", two (0xd7e0, 0x4160), two (0xffe0, 0x41ff), {VECTOR8}, 0, PROCESSOR_V850E3V5_UP },
+ { "hvtrap", two (0x07e0, 0x0110), two (0xffe0, 0xffff), {VECTOR5}, 0, PROCESSOR_V850E3V5_UP },
+-
++
+ { "jarl", two (0xc7e0, 0x0160), two (0xffe0, 0x07ff), {R1, R3_NOTR0}, 1, PROCESSOR_V850E3V5_UP},
+ { "jarl", two (0x0780, 0x0000), two (0x07c0, 0x0001), {D22, R2_NOTR0}, 0, PROCESSOR_ALL},
+ { "jarl", one (0x02e0), one (0xffe0), {D32_31_PCREL, R1_NOTR0}, 0, PROCESSOR_V850E2_UP },
+--- a/opcodes/vax-dis.c
++++ b/opcodes/vax-dis.c
+@@ -131,14 +131,14 @@ parse_disassembler_options (char * options)
+ /* A guesstimate of the number of entries we will have to create. */
+ entry_addr_total_slots +=
+ strlen (options) / (strlen (entry_switch) + 5);
+-
++
+ entry_addr = realloc (entry_addr, sizeof (bfd_vma)
+ * entry_addr_total_slots);
+ }
+
+ if (entry_addr == NULL)
+ return FALSE;
+-
++
+ entry_addr[entry_addr_occupied_slots] = bfd_scan_vma (options, NULL, 0);
+ entry_addr_occupied_slots ++;
+ }
+#--- a/opcodes/w65-opc.h
+#+++ b/opcodes/w65-opc.h
+#@@ -1,4 +1,4 @@
+#-/* Instruction opcode header for WDC 65816
+#+/* Instruction opcode header for WDC 65816
+# (generated by the program sim/w65/gencode -a)
+#
+# Copyright (C) 2001-2015 Free Software Foundation, Inc.
+--- a/opcodes/xc16x-asm.c
++++ b/opcodes/xc16x-asm.c
+@@ -94,7 +94,7 @@ parse_pof (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ *strp += 4;
+ return NULL;
+ }
+- return _("Missing 'pof:' prefix");
++ return _("Missing 'pof:' prefix");
+ }
+
+ /* Handle 'pag:' prefixes (i.e. skip over them). */
+@@ -379,7 +379,7 @@ xc16x_cgen_parse_operand (CGEN_CPU_DESC cd,
+ return errmsg;
+ }
+
+-cgen_parse_fn * const xc16x_cgen_parse_handlers[] =
++cgen_parse_fn * const xc16x_cgen_parse_handlers[] =
+ {
+ parse_insn_normal,
+ };
+@@ -409,9 +409,9 @@ CGEN_ASM_INIT_HOOK
+
+ Returns NULL for success, an error message for failure. */
+
+-char *
++char *
+ xc16x_cgen_build_insn_regex (CGEN_INSN *insn)
+-{
++{
+ CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
+ const char *mnem = CGEN_INSN_MNEMONIC (insn);
+ char rxbuf[CGEN_MAX_RX_ELEMENTS];
+@@ -450,18 +450,18 @@ xc16x_cgen_build_insn_regex (CGEN_INSN *insn)
+ /* Copy any remaining literals from the syntax string into the rx. */
+ for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn)
+ {
+- if (CGEN_SYNTAX_CHAR_P (* syn))
++ if (CGEN_SYNTAX_CHAR_P (* syn))
+ {
+ char c = CGEN_SYNTAX_CHAR (* syn);
+
+- switch (c)
++ switch (c)
+ {
+ /* Escape any regex metacharacters in the syntax. */
+- case '.': case '[': case '\\':
+- case '*': case '^': case '$':
++ case '.': case '[': case '\\':
++ case '*': case '^': case '$':
+
+ #ifdef CGEN_ESCAPE_EXTENDED_REGEX
+- case '?': case '{': case '}':
++ case '?': case '{': case '}':
+ case '(': case ')': case '*':
+ case '|': case '+': case ']':
+ #endif
+@@ -491,20 +491,20 @@ xc16x_cgen_build_insn_regex (CGEN_INSN *insn)
+ }
+
+ /* Trailing whitespace ok. */
+- * rx++ = '[';
+- * rx++ = ' ';
+- * rx++ = '\t';
+- * rx++ = ']';
+- * rx++ = '*';
++ * rx++ = '[';
++ * rx++ = ' ';
++ * rx++ = '\t';
++ * rx++ = ']';
++ * rx++ = '*';
+
+ /* But anchor it after that. */
+- * rx++ = '$';
++ * rx++ = '$';
+ * rx = '\0';
+
+ CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t));
+ reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB);
+
+- if (reg_err == 0)
++ if (reg_err == 0)
+ return NULL;
+ else
+ {
+@@ -703,7 +703,7 @@ xc16x_cgen_assemble_insn (CGEN_CPU_DESC cd,
+ const CGEN_INSN *insn = ilist->insn;
+ recognized_mnemonic = 1;
+
+-#ifdef CGEN_VALIDATE_INSN_SUPPORTED
++#ifdef CGEN_VALIDATE_INSN_SUPPORTED
+ /* Not usually needed as unsupported opcodes
+ shouldn't be in the hash lists. */
+ /* Is this insn supported by the selected cpu? */
+@@ -763,7 +763,7 @@ xc16x_cgen_assemble_insn (CGEN_CPU_DESC cd,
+ if (strlen (start) > 50)
+ /* xgettext:c-format */
+ sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start);
+- else
++ else
+ /* xgettext:c-format */
+ sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start);
+ }
+@@ -772,11 +772,11 @@ xc16x_cgen_assemble_insn (CGEN_CPU_DESC cd,
+ if (strlen (start) > 50)
+ /* xgettext:c-format */
+ sprintf (errbuf, _("bad instruction `%.50s...'"), start);
+- else
++ else
+ /* xgettext:c-format */
+ sprintf (errbuf, _("bad instruction `%.50s'"), start);
+ }
+-
++
+ *errmsg = errbuf;
+ return NULL;
+ }
+--- a/opcodes/xc16x-desc.c
++++ b/opcodes/xc16x-desc.c
+@@ -738,263 +738,263 @@ const CGEN_OPERAND xc16x_cgen_operand_table[] =
+ {
+ /* pc: program counter */
+ { "pc", XC16X_OPERAND_PC, HW_H_PC, 0, 0,
+- { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_NIL] } },
++ { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_NIL] } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* sr: source register */
+ { "sr", XC16X_OPERAND_SR, HW_H_GR, 11, 4,
+- { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R2] } },
++ { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R2] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* dr: destination register */
+ { "dr", XC16X_OPERAND_DR, HW_H_GR, 15, 4,
+- { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R1] } },
++ { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R1] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* dri: destination register */
+ { "dri", XC16X_OPERAND_DRI, HW_H_GR, 11, 4,
+- { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R4] } },
++ { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R4] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* srb: source register */
+ { "srb", XC16X_OPERAND_SRB, HW_H_GRB, 11, 4,
+- { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R2] } },
++ { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R2] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* drb: destination register */
+ { "drb", XC16X_OPERAND_DRB, HW_H_GRB, 15, 4,
+- { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R1] } },
++ { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R1] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* sr2: 2 bit source register */
+ { "sr2", XC16X_OPERAND_SR2, HW_H_GR, 9, 2,
+- { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R0] } },
++ { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R0] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* src1: source register 1 */
+ { "src1", XC16X_OPERAND_SRC1, HW_H_GR, 15, 4,
+- { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R1] } },
++ { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R1] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* src2: source register 2 */
+ { "src2", XC16X_OPERAND_SRC2, HW_H_GR, 11, 4,
+- { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R2] } },
++ { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R2] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* srdiv: source register 2 */
+ { "srdiv", XC16X_OPERAND_SRDIV, HW_H_REGDIV8, 15, 8,
+- { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REG8] } },
++ { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REG8] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* RegNam: PSW bits */
+ { "RegNam", XC16X_OPERAND_REGNAM, HW_H_PSW, 15, 8,
+- { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REG8] } },
++ { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REG8] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* uimm2: 2 bit unsigned number */
+ { "uimm2", XC16X_OPERAND_UIMM2, HW_H_EXT, 13, 2,
+- { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM2] } },
++ { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM2] } },
+ { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
+ /* uimm3: 3 bit unsigned number */
+ { "uimm3", XC16X_OPERAND_UIMM3, HW_H_R01, 10, 3,
+- { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM3] } },
++ { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM3] } },
+ { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
+ /* uimm4: 4 bit unsigned number */
+ { "uimm4", XC16X_OPERAND_UIMM4, HW_H_UINT, 15, 4,
+- { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM4] } },
++ { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM4] } },
+ { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
+ /* uimm7: 7 bit trap number */
+ { "uimm7", XC16X_OPERAND_UIMM7, HW_H_UINT, 15, 7,
+- { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM7] } },
++ { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM7] } },
+ { 0|A(HASH_PREFIX)|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
+ /* uimm8: 8 bit unsigned immediate */
+ { "uimm8", XC16X_OPERAND_UIMM8, HW_H_UINT, 23, 8,
+- { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM8] } },
++ { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM8] } },
+ { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
+ /* uimm16: 16 bit unsigned immediate */
+ { "uimm16", XC16X_OPERAND_UIMM16, HW_H_UINT, 31, 16,
+- { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM16] } },
++ { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM16] } },
+ { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
+ /* upof16: 16 bit unsigned immediate */
+ { "upof16", XC16X_OPERAND_UPOF16, HW_H_ADDR, 31, 16,
+- { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_MEMORY] } },
++ { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_MEMORY] } },
+ { 0|A(POF_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
+ /* reg8: 8 bit word register number */
+ { "reg8", XC16X_OPERAND_REG8, HW_H_R8, 15, 8,
+- { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REG8] } },
++ { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REG8] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* regmem8: 8 bit word register number */
+ { "regmem8", XC16X_OPERAND_REGMEM8, HW_H_REGMEM8, 15, 8,
+- { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGMEM8] } },
++ { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGMEM8] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* regbmem8: 8 bit byte register number */
+ { "regbmem8", XC16X_OPERAND_REGBMEM8, HW_H_REGBMEM8, 15, 8,
+- { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGMEM8] } },
++ { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGMEM8] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* regoff8: 8 bit word register number */
+ { "regoff8", XC16X_OPERAND_REGOFF8, HW_H_R8, 15, 8,
+- { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGOFF8] } },
++ { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGOFF8] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* reghi8: 8 bit word register number */
+ { "reghi8", XC16X_OPERAND_REGHI8, HW_H_R8, 23, 8,
+- { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGHI8] } },
++ { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGHI8] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* regb8: 8 bit byte register number */
+ { "regb8", XC16X_OPERAND_REGB8, HW_H_GRB8, 15, 8,
+- { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGB8] } },
++ { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGB8] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* genreg: 8 bit word register number */
+ { "genreg", XC16X_OPERAND_GENREG, HW_H_R8, 15, 8,
+- { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGB8] } },
++ { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGB8] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* seg: 8 bit segment number */
+ { "seg", XC16X_OPERAND_SEG, HW_H_UINT, 15, 8,
+- { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_SEG8] } },
++ { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_SEG8] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* seghi8: 8 bit hi segment number */
+ { "seghi8", XC16X_OPERAND_SEGHI8, HW_H_UINT, 23, 8,
+- { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_SEGNUM8] } },
++ { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_SEGNUM8] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* caddr: 16 bit address offset */
+ { "caddr", XC16X_OPERAND_CADDR, HW_H_ADDR, 31, 16,
+- { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OFFSET16] } },
++ { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OFFSET16] } },
+ { 0|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
+ /* rel: 8 bit signed relative offset */
+ { "rel", XC16X_OPERAND_REL, HW_H_SINT, 15, 8,
+- { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REL8] } },
++ { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REL8] } },
+ { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
+ /* relhi: hi 8 bit signed relative offset */
+ { "relhi", XC16X_OPERAND_RELHI, HW_H_SINT, 23, 8,
+- { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_RELHI8] } },
++ { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_RELHI8] } },
+ { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
+ /* condbit: condition bit */
+ { "condbit", XC16X_OPERAND_CONDBIT, HW_H_COND, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* bit1: gap of 1 bit */
+ { "bit1", XC16X_OPERAND_BIT1, HW_H_UINT, 11, 1,
+- { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_BIT1] } },
++ { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_BIT1] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* bit2: gap of 2 bits */
+ { "bit2", XC16X_OPERAND_BIT2, HW_H_UINT, 11, 2,
+- { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_BIT2] } },
++ { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_BIT2] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* bit4: gap of 4 bits */
+ { "bit4", XC16X_OPERAND_BIT4, HW_H_UINT, 11, 4,
+- { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_BIT4] } },
++ { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_BIT4] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* lbit4: gap of 4 bits */
+ { "lbit4", XC16X_OPERAND_LBIT4, HW_H_UINT, 15, 4,
+- { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_LBIT4] } },
++ { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_LBIT4] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* lbit2: gap of 2 bits */
+ { "lbit2", XC16X_OPERAND_LBIT2, HW_H_UINT, 15, 2,
+- { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_LBIT2] } },
++ { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_LBIT2] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* bit8: gap of 8 bits */
+ { "bit8", XC16X_OPERAND_BIT8, HW_H_UINT, 31, 8,
+- { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_BIT8] } },
++ { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_BIT8] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* u4: gap of 4 bits */
+ { "u4", XC16X_OPERAND_U4, HW_H_R0, 15, 4,
+- { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM4] } },
++ { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM4] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* bitone: field of 1 bit */
+ { "bitone", XC16X_OPERAND_BITONE, HW_H_UINT, 9, 1,
+- { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_ONEBIT] } },
++ { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_ONEBIT] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* bit01: field of 1 bit */
+ { "bit01", XC16X_OPERAND_BIT01, HW_H_UINT, 8, 1,
+- { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_1BIT] } },
++ { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_1BIT] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* cond: condition code */
+ { "cond", XC16X_OPERAND_COND, HW_H_CC, 7, 4,
+- { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_CONDCODE] } },
++ { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_CONDCODE] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* icond: indirect condition code */
+ { "icond", XC16X_OPERAND_ICOND, HW_H_CC, 15, 4,
+- { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_ICONDCODE] } },
++ { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_ICONDCODE] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* extcond: extended condition code */
+ { "extcond", XC16X_OPERAND_EXTCOND, HW_H_ECC, 15, 5,
+- { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_EXTCCODE] } },
++ { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_EXTCCODE] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* memory: 16 bit memory */
+ { "memory", XC16X_OPERAND_MEMORY, HW_H_ADDR, 31, 16,
+- { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_MEMORY] } },
++ { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_MEMORY] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* memgr8: 16 bit memory */
+ { "memgr8", XC16X_OPERAND_MEMGR8, HW_H_MEMGR8, 31, 16,
+- { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_MEMGR8] } },
++ { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_MEMGR8] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* cbit: carry bit */
+ { "cbit", XC16X_OPERAND_CBIT, HW_H_CBIT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* qbit: bit addr */
+ { "qbit", XC16X_OPERAND_QBIT, HW_H_UINT, 7, 4,
+- { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_QBIT] } },
++ { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_QBIT] } },
+ { 0|A(DOT_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
+ /* qlobit: bit addr */
+ { "qlobit", XC16X_OPERAND_QLOBIT, HW_H_UINT, 31, 4,
+- { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_QLOBIT] } },
++ { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_QLOBIT] } },
+ { 0|A(DOT_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
+ /* qhibit: bit addr */
+ { "qhibit", XC16X_OPERAND_QHIBIT, HW_H_UINT, 27, 4,
+- { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_QHIBIT] } },
++ { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_QHIBIT] } },
+ { 0|A(DOT_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
+ /* mask8: 8 bit mask */
+ { "mask8", XC16X_OPERAND_MASK8, HW_H_UINT, 23, 8,
+- { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_MASK8] } },
++ { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_MASK8] } },
+ { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
+ /* masklo8: 8 bit mask */
+ { "masklo8", XC16X_OPERAND_MASKLO8, HW_H_UINT, 31, 8,
+- { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_DATAHI8] } },
++ { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_DATAHI8] } },
+ { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
+ /* pagenum: 10 bit page number */
+ { "pagenum", XC16X_OPERAND_PAGENUM, HW_H_UINT, 25, 10,
+- { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_PAGENUM] } },
++ { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_PAGENUM] } },
+ { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
+ /* data8: 8 bit data */
+ { "data8", XC16X_OPERAND_DATA8, HW_H_UINT, 23, 8,
+- { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_DATA8] } },
++ { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_DATA8] } },
+ { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
+ /* datahi8: 8 bit data */
+ { "datahi8", XC16X_OPERAND_DATAHI8, HW_H_UINT, 31, 8,
+- { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_DATAHI8] } },
++ { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_DATAHI8] } },
+ { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
+ /* sgtdisbit: segmentation enable bit */
+ { "sgtdisbit", XC16X_OPERAND_SGTDISBIT, HW_H_SGTDIS, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* upag16: 16 bit unsigned immediate */
+ { "upag16", XC16X_OPERAND_UPAG16, HW_H_UINT, 31, 16,
+- { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM16] } },
++ { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM16] } },
+ { 0|A(PAG_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
+ /* useg8: 8 bit segment */
+ { "useg8", XC16X_OPERAND_USEG8, HW_H_UINT, 15, 8,
+- { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_SEG8] } },
++ { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_SEG8] } },
+ { 0|A(SEG_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
+ /* useg16: 16 bit address offset */
+ { "useg16", XC16X_OPERAND_USEG16, HW_H_UINT, 31, 16,
+- { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OFFSET16] } },
++ { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OFFSET16] } },
+ { 0|A(SEG_PREFIX)|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
+ /* usof16: 16 bit address offset */
+ { "usof16", XC16X_OPERAND_USOF16, HW_H_UINT, 31, 16,
+- { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OFFSET16] } },
++ { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OFFSET16] } },
+ { 0|A(SOF_PREFIX)|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
+ /* hash: # prefix */
+ { "hash", XC16X_OPERAND_HASH, HW_H_SINT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* dot: . prefix */
+ { "dot", XC16X_OPERAND_DOT, HW_H_SINT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* pof: pof: prefix */
+ { "pof", XC16X_OPERAND_POF, HW_H_SINT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* pag: pag: prefix */
+ { "pag", XC16X_OPERAND_PAG, HW_H_SINT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* sof: sof: prefix */
+ { "sof", XC16X_OPERAND_SOF, HW_H_SINT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* segm: seg: prefix */
+ { "segm", XC16X_OPERAND_SEGM, HW_H_SINT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* sentinel */
+ { 0, 0, 0, 0, 0,
+@@ -3452,7 +3452,7 @@ xc16x_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
+
+ /* Default to not allowing signed overflow. */
+ cd->signed_overflow_ok_p = 0;
+-
++
+ return (CGEN_CPU_DESC) cd;
+ }
+
+@@ -3492,7 +3492,7 @@ xc16x_cgen_cpu_close (CGEN_CPU_DESC cd)
+ for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
+ if (CGEN_INSN_RX (insns))
+ regfree (CGEN_INSN_RX (insns));
+- }
++ }
+
+ if (cd->macro_insn_table.init_entries)
+ free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
+--- a/opcodes/xc16x-dis.c
++++ b/opcodes/xc16x-dis.c
+@@ -422,7 +422,7 @@ xc16x_cgen_print_operand (CGEN_CPU_DESC cd,
+ }
+ }
+
+-cgen_print_fn * const xc16x_cgen_print_handlers[] =
++cgen_print_fn * const xc16x_cgen_print_handlers[] =
+ {
+ print_insn_normal,
+ };
+@@ -612,7 +612,7 @@ print_insn (CGEN_CPU_DESC cd,
+ int length;
+ unsigned long insn_value_cropped;
+
+-#ifdef CGEN_VALIDATE_INSN_SUPPORTED
++#ifdef CGEN_VALIDATE_INSN_SUPPORTED
+ /* Not needed as insn shouldn't be in hash lists if not supported. */
+ /* Supported by this cpu? */
+ if (! xc16x_cgen_insn_supported (cd, insn))
+@@ -630,7 +630,7 @@ print_insn (CGEN_CPU_DESC cd,
+ relevant part from the buffer. */
+ if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
+ (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
+- insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
++ insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
+ info->endian == BFD_ENDIAN_BIG);
+ else
+ insn_value_cropped = insn_value;
+@@ -749,7 +749,7 @@ print_insn_xc16x (bfd_vma pc, disassemble_info *info)
+ arch = info->arch;
+ if (arch == bfd_arch_unknown)
+ arch = CGEN_BFD_ARCH;
+-
++
+ /* There's no standard way to compute the machine or isa number
+ so we leave it to the target. */
+ #ifdef CGEN_COMPUTE_MACH
+@@ -790,7 +790,7 @@ print_insn_xc16x (bfd_vma pc, disassemble_info *info)
+ break;
+ }
+ }
+- }
++ }
+
+ /* If we haven't initialized yet, initialize the opcode table. */
+ if (! cd)
+--- a/opcodes/xc16x-ibld.c
++++ b/opcodes/xc16x-ibld.c
+@@ -154,7 +154,7 @@ insert_normal (CGEN_CPU_DESC cd,
+ {
+ long minval = - (1L << (length - 1));
+ unsigned long maxval = mask;
+-
++
+ if ((value > 0 && (unsigned long) value > maxval)
+ || value < minval)
+ {
+@@ -192,7 +192,7 @@ insert_normal (CGEN_CPU_DESC cd,
+ {
+ long minval = - (1L << (length - 1));
+ long maxval = (1L << (length - 1)) - 1;
+-
++
+ if (value < minval || value > maxval)
+ {
+ sprintf
+@@ -973,12 +973,12 @@ xc16x_cgen_extract_operand (CGEN_CPU_DESC cd,
+ return length;
+ }
+
+-cgen_insert_fn * const xc16x_cgen_insert_handlers[] =
++cgen_insert_fn * const xc16x_cgen_insert_handlers[] =
+ {
+ insert_insn_normal,
+ };
+
+-cgen_extract_fn * const xc16x_cgen_extract_handlers[] =
++cgen_extract_fn * const xc16x_cgen_extract_handlers[] =
+ {
+ extract_insn_normal,
+ };
+--- a/opcodes/xc16x-opc.c
++++ b/opcodes/xc16x-opc.c
+@@ -31,7 +31,7 @@ This file is part of the GNU Binutils and/or GDB, the GNU debugger.
+ #include "libiberty.h"
+
+ /* -- opc.c */
+-
++
+ /* -- */
+ /* The hash functions are recorded here to help keep assembler code out of
+ the disassembler and vice versa. */
+--- a/opcodes/xstormy16-asm.c
++++ b/opcodes/xstormy16-asm.c
+@@ -65,7 +65,7 @@ parse_mem8 (CGEN_CPU_DESC cd,
+ if (**strp == '(')
+ {
+ const char *s = *strp;
+-
++
+ if (s[1] == '-' && s[2] == '-')
+ return _("Bad register in preincrement");
+
+@@ -76,7 +76,7 @@ parse_mem8 (CGEN_CPU_DESC cd,
+ if (s[0] == ',' || s[0] == ')')
+ return _("Bad register name");
+ }
+- else if (cgen_parse_keyword (cd, strp, & xstormy16_cgen_opval_gr_names,
++ else if (cgen_parse_keyword (cd, strp, & xstormy16_cgen_opval_gr_names,
+ (long *) valuep) == NULL)
+ return _("Label conflicts with register name");
+ else if (strncasecmp (*strp, "rx,", 3) == 0
+@@ -85,7 +85,7 @@ parse_mem8 (CGEN_CPU_DESC cd,
+ return _("Label conflicts with `Rx'");
+ else if (**strp == '#')
+ return _("Bad immediate expression");
+-
++
+ return cgen_parse_unsigned_integer (cd, strp, opindex, valuep);
+ }
+
+@@ -93,7 +93,7 @@ parse_mem8 (CGEN_CPU_DESC cd,
+ one for small operands and one for large ones. We want to use
+ the small one when possible, but we do not want to generate relocs
+ of the small size. This is somewhat tricky. */
+-
++
+ static const char *
+ parse_small_immediate (CGEN_CPU_DESC cd,
+ const char **strp,
+@@ -110,7 +110,7 @@ parse_small_immediate (CGEN_CPU_DESC cd,
+ errmsg = (* cd->parse_operand_fn)
+ (cd, CGEN_PARSE_OPERAND_INTEGER, strp, opindex, BFD_RELOC_NONE,
+ & result, & value);
+-
++
+ if (errmsg)
+ return errmsg;
+
+@@ -122,7 +122,7 @@ parse_small_immediate (CGEN_CPU_DESC cd,
+ }
+
+ /* Literal scan be either a normal literal, a @hi() or @lo relocation. */
+-
++
+ static const char *
+ parse_immediate16 (CGEN_CPU_DESC cd,
+ const char **strp,
+@@ -157,7 +157,7 @@ parse_immediate16 (CGEN_CPU_DESC cd,
+
+ *valuep = value;
+ if ((code == BFD_RELOC_HI16 || code == BFD_RELOC_LO16)
+- && **strp == ')')
++ && **strp == ')')
+ *strp += 1;
+ else
+ {
+@@ -279,7 +279,7 @@ xstormy16_cgen_parse_operand (CGEN_CPU_DESC cd,
+ return errmsg;
+ }
+
+-cgen_parse_fn * const xstormy16_cgen_parse_handlers[] =
++cgen_parse_fn * const xstormy16_cgen_parse_handlers[] =
+ {
+ parse_insn_normal,
+ };
+@@ -309,9 +309,9 @@ CGEN_ASM_INIT_HOOK
+
+ Returns NULL for success, an error message for failure. */
+
+-char *
++char *
+ xstormy16_cgen_build_insn_regex (CGEN_INSN *insn)
+-{
++{
+ CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
+ const char *mnem = CGEN_INSN_MNEMONIC (insn);
+ char rxbuf[CGEN_MAX_RX_ELEMENTS];
+@@ -350,18 +350,18 @@ xstormy16_cgen_build_insn_regex (CGEN_INSN *insn)
+ /* Copy any remaining literals from the syntax string into the rx. */
+ for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn)
+ {
+- if (CGEN_SYNTAX_CHAR_P (* syn))
++ if (CGEN_SYNTAX_CHAR_P (* syn))
+ {
+ char c = CGEN_SYNTAX_CHAR (* syn);
+
+- switch (c)
++ switch (c)
+ {
+ /* Escape any regex metacharacters in the syntax. */
+- case '.': case '[': case '\\':
+- case '*': case '^': case '$':
++ case '.': case '[': case '\\':
++ case '*': case '^': case '$':
+
+ #ifdef CGEN_ESCAPE_EXTENDED_REGEX
+- case '?': case '{': case '}':
++ case '?': case '{': case '}':
+ case '(': case ')': case '*':
+ case '|': case '+': case ']':
+ #endif
+@@ -391,20 +391,20 @@ xstormy16_cgen_build_insn_regex (CGEN_INSN *insn)
+ }
+
+ /* Trailing whitespace ok. */
+- * rx++ = '[';
+- * rx++ = ' ';
+- * rx++ = '\t';
+- * rx++ = ']';
+- * rx++ = '*';
++ * rx++ = '[';
++ * rx++ = ' ';
++ * rx++ = '\t';
++ * rx++ = ']';
++ * rx++ = '*';
+
+ /* But anchor it after that. */
+- * rx++ = '$';
++ * rx++ = '$';
+ * rx = '\0';
+
+ CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t));
+ reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB);
+
+- if (reg_err == 0)
++ if (reg_err == 0)
+ return NULL;
+ else
+ {
+@@ -603,7 +603,7 @@ xstormy16_cgen_assemble_insn (CGEN_CPU_DESC cd,
+ const CGEN_INSN *insn = ilist->insn;
+ recognized_mnemonic = 1;
+
+-#ifdef CGEN_VALIDATE_INSN_SUPPORTED
++#ifdef CGEN_VALIDATE_INSN_SUPPORTED
+ /* Not usually needed as unsupported opcodes
+ shouldn't be in the hash lists. */
+ /* Is this insn supported by the selected cpu? */
+@@ -663,7 +663,7 @@ xstormy16_cgen_assemble_insn (CGEN_CPU_DESC cd,
+ if (strlen (start) > 50)
+ /* xgettext:c-format */
+ sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start);
+- else
++ else
+ /* xgettext:c-format */
+ sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start);
+ }
+@@ -672,11 +672,11 @@ xstormy16_cgen_assemble_insn (CGEN_CPU_DESC cd,
+ if (strlen (start) > 50)
+ /* xgettext:c-format */
+ sprintf (errbuf, _("bad instruction `%.50s...'"), start);
+- else
++ else
+ /* xgettext:c-format */
+ sprintf (errbuf, _("bad instruction `%.50s'"), start);
+ }
+-
++
+ *errmsg = errbuf;
+ return NULL;
+ }
+--- a/opcodes/xstormy16-desc.c
++++ b/opcodes/xstormy16-desc.c
+@@ -320,159 +320,159 @@ const CGEN_OPERAND xstormy16_cgen_operand_table[] =
+ {
+ /* pc: program counter */
+ { "pc", XSTORMY16_OPERAND_PC, HW_H_PC, 0, 0,
+- { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_NIL] } },
++ { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_NIL] } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* psw-z8: */
+ { "psw-z8", XSTORMY16_OPERAND_PSW_Z8, HW_H_Z8, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* psw-z16: */
+ { "psw-z16", XSTORMY16_OPERAND_PSW_Z16, HW_H_Z16, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* psw-cy: */
+ { "psw-cy", XSTORMY16_OPERAND_PSW_CY, HW_H_CY, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* psw-hc: */
+ { "psw-hc", XSTORMY16_OPERAND_PSW_HC, HW_H_HC, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* psw-ov: */
+ { "psw-ov", XSTORMY16_OPERAND_PSW_OV, HW_H_OV, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* psw-pt: */
+ { "psw-pt", XSTORMY16_OPERAND_PSW_PT, HW_H_PT, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* psw-s: */
+ { "psw-s", XSTORMY16_OPERAND_PSW_S, HW_H_S, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* Rd: general register destination */
+ { "Rd", XSTORMY16_OPERAND_RD, HW_H_GR, 12, 4,
+- { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RD] } },
++ { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RD] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* Rdm: general register destination */
+ { "Rdm", XSTORMY16_OPERAND_RDM, HW_H_GR, 13, 3,
+- { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RDM] } },
++ { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RDM] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* Rm: general register for memory */
+ { "Rm", XSTORMY16_OPERAND_RM, HW_H_GR, 4, 3,
+- { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RM] } },
++ { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RM] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* Rs: general register source */
+ { "Rs", XSTORMY16_OPERAND_RS, HW_H_GR, 8, 4,
+- { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RS] } },
++ { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RS] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* Rb: base register */
+ { "Rb", XSTORMY16_OPERAND_RB, HW_H_RB, 17, 3,
+- { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RB] } },
++ { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RB] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* Rbj: base register for jump */
+ { "Rbj", XSTORMY16_OPERAND_RBJ, HW_H_RBJ, 11, 1,
+- { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RBJ] } },
++ { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RBJ] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* bcond2: branch condition opcode */
+ { "bcond2", XSTORMY16_OPERAND_BCOND2, HW_H_BRANCHCOND, 4, 4,
+- { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_OP2] } },
++ { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_OP2] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* ws2: word size opcode */
+ { "ws2", XSTORMY16_OPERAND_WS2, HW_H_WORDSIZE, 7, 1,
+- { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_OP2M] } },
++ { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_OP2M] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* bcond5: branch condition opcode */
+ { "bcond5", XSTORMY16_OPERAND_BCOND5, HW_H_BRANCHCOND, 16, 4,
+- { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_OP5] } },
++ { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_OP5] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* imm2: 2 bit unsigned immediate */
+ { "imm2", XSTORMY16_OPERAND_IMM2, HW_H_UINT, 10, 2,
+- { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM2] } },
++ { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM2] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* imm3: 3 bit unsigned immediate */
+ { "imm3", XSTORMY16_OPERAND_IMM3, HW_H_UINT, 4, 3,
+- { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM3] } },
++ { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM3] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* imm3b: 3 bit unsigned immediate for bit tests */
+ { "imm3b", XSTORMY16_OPERAND_IMM3B, HW_H_UINT, 17, 3,
+- { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM3B] } },
++ { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM3B] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* imm4: 4 bit unsigned immediate */
+ { "imm4", XSTORMY16_OPERAND_IMM4, HW_H_UINT, 8, 4,
+- { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM4] } },
++ { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM4] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* imm8: 8 bit unsigned immediate */
+ { "imm8", XSTORMY16_OPERAND_IMM8, HW_H_UINT, 8, 8,
+- { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM8] } },
++ { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM8] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* imm8small: 8 bit unsigned immediate */
+ { "imm8small", XSTORMY16_OPERAND_IMM8SMALL, HW_H_UINT, 8, 8,
+- { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM8] } },
++ { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM8] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* imm12: 12 bit signed immediate */
+ { "imm12", XSTORMY16_OPERAND_IMM12, HW_H_SINT, 20, 12,
+- { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM12] } },
++ { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM12] } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ /* imm16: 16 bit immediate */
+ { "imm16", XSTORMY16_OPERAND_IMM16, HW_H_UINT, 16, 16,
+- { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM16] } },
++ { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM16] } },
+ { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } },
+ /* lmem8: 8 bit unsigned immediate low memory */
+ { "lmem8", XSTORMY16_OPERAND_LMEM8, HW_H_UINT, 8, 8,
+- { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_LMEM8] } },
++ { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_LMEM8] } },
+ { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
+ /* hmem8: 8 bit unsigned immediate high memory */
+ { "hmem8", XSTORMY16_OPERAND_HMEM8, HW_H_UINT, 8, 8,
+- { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_HMEM8] } },
++ { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_HMEM8] } },
+ { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
+ /* rel8-2: 8 bit relative address */
+ { "rel8-2", XSTORMY16_OPERAND_REL8_2, HW_H_UINT, 8, 8,
+- { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_REL8_2] } },
++ { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_REL8_2] } },
+ { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
+ /* rel8-4: 8 bit relative address */
+ { "rel8-4", XSTORMY16_OPERAND_REL8_4, HW_H_UINT, 8, 8,
+- { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_REL8_4] } },
++ { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_REL8_4] } },
+ { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
+ /* rel12: 12 bit relative address */
+ { "rel12", XSTORMY16_OPERAND_REL12, HW_H_UINT, 20, 12,
+- { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_REL12] } },
++ { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_REL12] } },
+ { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
+ /* rel12a: 12 bit relative address */
+ { "rel12a", XSTORMY16_OPERAND_REL12A, HW_H_UINT, 4, 11,
+- { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_REL12A] } },
++ { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_REL12A] } },
+ { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
+ /* abs24: 24 bit absolute address */
+ { "abs24", XSTORMY16_OPERAND_ABS24, HW_H_UINT, 8, 24,
+- { 2, { (const PTR) &XSTORMY16_F_ABS24_MULTI_IFIELD[0] } },
++ { 2, { (const PTR) &XSTORMY16_F_ABS24_MULTI_IFIELD[0] } },
+ { 0|A(ABS_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+ /* psw: program status word */
+ { "psw", XSTORMY16_OPERAND_PSW, HW_H_GR, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* Rpsw: N0-N3 of the program status word */
+ { "Rpsw", XSTORMY16_OPERAND_RPSW, HW_H_RPSW, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* sp: stack pointer */
+ { "sp", XSTORMY16_OPERAND_SP, HW_H_GR, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* R0: R0 */
+ { "R0", XSTORMY16_OPERAND_R0, HW_H_GR, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* R1: R1 */
+ { "R1", XSTORMY16_OPERAND_R1, HW_H_GR, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* R2: R2 */
+ { "R2", XSTORMY16_OPERAND_R2, HW_H_GR, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* R8: R8 */
+ { "R8", XSTORMY16_OPERAND_R8, HW_H_GR, 0, 0,
+- { 0, { (const PTR) 0 } },
++ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
+ /* sentinel */
+ { 0, 0, 0, 0, 0,
+@@ -1420,7 +1420,7 @@ xstormy16_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
+
+ /* Default to not allowing signed overflow. */
+ cd->signed_overflow_ok_p = 0;
+-
++
+ return (CGEN_CPU_DESC) cd;
+ }
+
+@@ -1460,7 +1460,7 @@ xstormy16_cgen_cpu_close (CGEN_CPU_DESC cd)
+ for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
+ if (CGEN_INSN_RX (insns))
+ regfree (CGEN_INSN_RX (insns));
+- }
++ }
+
+ if (cd->macro_insn_table.init_entries)
+ free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
+--- a/opcodes/xstormy16-dis.c
++++ b/opcodes/xstormy16-dis.c
+@@ -170,7 +170,7 @@ xstormy16_cgen_print_operand (CGEN_CPU_DESC cd,
+ }
+ }
+
+-cgen_print_fn * const xstormy16_cgen_print_handlers[] =
++cgen_print_fn * const xstormy16_cgen_print_handlers[] =
+ {
+ print_insn_normal,
+ };
+@@ -360,7 +360,7 @@ print_insn (CGEN_CPU_DESC cd,
+ int length;
+ unsigned long insn_value_cropped;
+
+-#ifdef CGEN_VALIDATE_INSN_SUPPORTED
++#ifdef CGEN_VALIDATE_INSN_SUPPORTED
+ /* Not needed as insn shouldn't be in hash lists if not supported. */
+ /* Supported by this cpu? */
+ if (! xstormy16_cgen_insn_supported (cd, insn))
+@@ -378,7 +378,7 @@ print_insn (CGEN_CPU_DESC cd,
+ relevant part from the buffer. */
+ if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
+ (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
+- insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
++ insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
+ info->endian == BFD_ENDIAN_BIG);
+ else
+ insn_value_cropped = insn_value;
+@@ -497,7 +497,7 @@ print_insn_xstormy16 (bfd_vma pc, disassemble_info *info)
+ arch = info->arch;
+ if (arch == bfd_arch_unknown)
+ arch = CGEN_BFD_ARCH;
+-
++
+ /* There's no standard way to compute the machine or isa number
+ so we leave it to the target. */
+ #ifdef CGEN_COMPUTE_MACH
+@@ -538,7 +538,7 @@ print_insn_xstormy16 (bfd_vma pc, disassemble_info *info)
+ break;
+ }
+ }
+- }
++ }
+
+ /* If we haven't initialized yet, initialize the opcode table. */
+ if (! cd)
+--- a/opcodes/xstormy16-ibld.c
++++ b/opcodes/xstormy16-ibld.c
+@@ -154,7 +154,7 @@ insert_normal (CGEN_CPU_DESC cd,
+ {
+ long minval = - (1L << (length - 1));
+ unsigned long maxval = mask;
+-
++
+ if ((value > 0 && (unsigned long) value > maxval)
+ || value < minval)
+ {
+@@ -192,7 +192,7 @@ insert_normal (CGEN_CPU_DESC cd,
+ {
+ long minval = - (1L << (length - 1));
+ long maxval = (1L << (length - 1)) - 1;
+-
++
+ if (value < minval || value > maxval)
+ {
+ sprintf
+@@ -825,12 +825,12 @@ xstormy16_cgen_extract_operand (CGEN_CPU_DESC cd,
+ return length;
+ }
+
+-cgen_insert_fn * const xstormy16_cgen_insert_handlers[] =
++cgen_insert_fn * const xstormy16_cgen_insert_handlers[] =
+ {
+ insert_insn_normal,
+ };
+
+-cgen_extract_fn * const xstormy16_cgen_extract_handlers[] =
++cgen_extract_fn * const xstormy16_cgen_extract_handlers[] =
+ {
+ extract_insn_normal,
+ };
+--- a/opcodes/xtensa-dis.c
++++ b/opcodes/xtensa-dis.c
+@@ -80,7 +80,7 @@ print_xtensa_operand (bfd_vma memaddr,
+ {
+ xtensa_isa isa = xtensa_default_isa;
+ int signed_operand_val;
+-
++
+ if (show_raw_fields)
+ {
+ if (operand_val < 0xa)
+@@ -124,7 +124,7 @@ print_xtensa_operand (bfd_vma memaddr,
+ xtensa_regfile_shortname (isa, opnd_rf),
+ operand_val);
+ i++;
+- }
++ }
+ }
+ }
+
+--- a/opcodes/z80-dis.c
++++ b/opcodes/z80-dis.c
+@@ -130,7 +130,7 @@ prt_rr_nn (struct buffer *buf, disassemble_info * info, char *txt)
+ char mytxt[TXTSIZ];
+ int rr;
+
+- rr = (buf->data[buf->n_fetch - 1] >> 4) & 3;
++ rr = (buf->data[buf->n_fetch - 1] >> 4) & 3;
+ snprintf (mytxt, TXTSIZ, txt, rr_str[rr]);
+ return prt_nn (buf, info, mytxt);
+ }
+@@ -314,7 +314,7 @@ struct tab_elt opc_ed[] =
+ };
+
+ static int
+-pref_ed (struct buffer * buf, disassemble_info * info,
++pref_ed (struct buffer * buf, disassemble_info * info,
+ char* txt ATTRIBUTE_UNUSED)
+ {
+ struct tab_elt *p;
diff --git a/SOURCES/gdb-rhbz1320945-power9-23of38.patch b/SOURCES/gdb-rhbz1320945-power9-23of38.patch
new file mode 100644
index 0000000..876c905
--- /dev/null
+++ b/SOURCES/gdb-rhbz1320945-power9-23of38.patch
@@ -0,0 +1,53 @@
+commit 6dca4fd141fd0b9fe0ea662295833b8ed43cb4e8
+Author: Anton Blanchard <anton@samba.org>
+Date: Tue Sep 22 15:39:24 2015 +1000
+
+ opcodes/ppc-opc.c: Add dscr and ctrl SPR mnemonics
+
+ opcodes/
+ * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
+
+### a/opcodes/ChangeLog
+### b/opcodes/ChangeLog
+## -1,3 +1,7 @@
++2015-09-22 Anton Blanchard <anton@samba.org>
++
++ * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
++
+ 2015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * sparc-dis.c (print_insn_sparc): Handle the privileged register
+--- a/opcodes/ppc-opc.c
++++ b/opcodes/ppc-opc.c
+@@ -4878,6 +4878,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"mfdec", XSPR(31,339, 6), XSPR_MASK, MFDEC1, PPCNONE, {RT}},
+ {"mflr", XSPR(31,339, 8), XSPR_MASK, COM|PPCVLE, PPCNONE, {RT}},
+ {"mfctr", XSPR(31,339, 9), XSPR_MASK, COM|PPCVLE, PPCNONE, {RT}},
++{"mfdscr", XSPR(31,339, 17), XSPR_MASK, POWER6, PPCNONE, {RT}},
+ {"mftid", XSPR(31,339, 17), XSPR_MASK, POWER, PPCNONE, {RT}},
+ {"mfdsisr", XSPR(31,339, 18), XSPR_MASK, COM, TITAN, {RT}},
+ {"mfdar", XSPR(31,339, 19), XSPR_MASK, COM, TITAN, {RT}},
+@@ -4893,6 +4894,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"mfdear", XSPR(31,339, 61), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+ {"mfesr", XSPR(31,339, 62), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+ {"mfivpr", XSPR(31,339, 63), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
++{"mfctrl", XSPR(31,339,136), XSPR_MASK, POWER4, PPCNONE, {RT}},
+ {"mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, PPCNONE, {RT}},
+ {"mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, PPCNONE, {RT}},
+ {"mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, PPCNONE, {RT}},
+@@ -5216,6 +5218,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"mtxer", XSPR(31,467, 1), XSPR_MASK, COM|PPCVLE, PPCNONE, {RS}},
+ {"mtlr", XSPR(31,467, 8), XSPR_MASK, COM|PPCVLE, PPCNONE, {RS}},
+ {"mtctr", XSPR(31,467, 9), XSPR_MASK, COM|PPCVLE, PPCNONE, {RS}},
++{"mtdscr", XSPR(31,467, 17), XSPR_MASK, POWER6, PPCNONE, {RS}},
+ {"mttid", XSPR(31,467, 17), XSPR_MASK, POWER, PPCNONE, {RS}},
+ {"mtdsisr", XSPR(31,467, 18), XSPR_MASK, COM, TITAN, {RS}},
+ {"mtdar", XSPR(31,467, 19), XSPR_MASK, COM, TITAN, {RS}},
+@@ -5242,6 +5245,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"mtder", XSPR(31,467,149), XSPR_MASK, PPC860, PPCNONE, {RS}},
+ {"mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, PPCNONE, {RS}},
+ {"mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, PPCNONE, {RS}},
++{"mtctrl", XSPR(31,467,152), XSPR_MASK, POWER4, PPCNONE, {RS}},
+ {"mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, PPCNONE, {RS}},
+ {"mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, PPCNONE, {RS}},
+ {"mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, PPCNONE, {RS}},
diff --git a/SOURCES/gdb-rhbz1320945-power9-24of38.patch b/SOURCES/gdb-rhbz1320945-power9-24of38.patch
new file mode 100644
index 0000000..3b48ee1
--- /dev/null
+++ b/SOURCES/gdb-rhbz1320945-power9-24of38.patch
@@ -0,0 +1,2408 @@
+commit a680de9a980e9d268846e8605af14ba1e7f3a39b
+Author: Peter Bergner <bergner@vnet.ibm.com>
+Date: Wed Nov 11 19:52:52 2015 -0600
+
+ Add assembler, disassembler and linker support for power9.
+
+ include/opcode/
+ * ppc.h (PPC_OPCODE_POWER9): New define.
+ (PPC_OPCODE_VSX3): Likewise.
+
+ opcodes/
+ * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
+ Add PPC_OPCODE_VSX3 to the vsx entry.
+ (powerpc_init_dialect): Set default dialect to power9.
+ * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
+ insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
+ extract_l1 insert_xtq6, extract_xtq6): New static functions.
+ (insert_esync): Test for illegal L operand value.
+ (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
+ XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
+ XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
+ XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
+ PPCVSX3): New defines.
+ (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
+ fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
+ <mcrxr>: Use XBFRARB_MASK.
+ <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
+ bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
+ cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
+ cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
+ lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
+ lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
+ modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
+ rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
+ stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
+ subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
+ vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
+ vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
+ vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
+ vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
+ vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
+ vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
+ vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
+ xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
+ xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
+ xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
+ xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
+ xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
+ xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
+ xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
+ xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
+ xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
+ xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
+ xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
+ xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
+ xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
+ <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
+ <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
+
+ include/elf/
+ * ppc.h (R_PPC_REL16DX_HA): New reloction.
+ * ppc64.h (R_PPC64_REL16DX_HA): Likewise.
+
+ bfd/
+ * elf32-ppc.c (ppc_elf_howto_raw): Add R_PPC_REL16DX_HA.
+ (ppc_elf_reloc_type_lookup): Handle R_PPC_REL16DX_HA.
+ (ppc_elf_addr16_ha_reloc): Likewise.
+ (ppc_elf_check_relocs): Likewise.
+ (ppc_elf_relocate_section): Likewise.
+ (is_insn_dq_form): Handle lxv and stxv instructions.
+ * elf64-ppc.c (ppc64_elf_howto_raw): Add R_PPC64_REL16DX_HA.
+ (ppc64_elf_reloc_type_lookup): Handle R_PPC64_REL16DX_HA.
+ (ppc64_elf_ha_reloc): Likewise.
+ (ppc64_elf_check_relocs): Likewise.
+ (ppc64_elf_relocate_section): Likewise.
+ * bfd-in2.h: Regenerate.
+ * libbfd.h: Likewise.
+ * reloc.c (BFD_RELOC_PPC_REL16DX_HA): New.
+
+ elfcpp/
+ * powerpc.h (R_POWERPC_REL16DX_HA): Define.
+
+ gas/
+ * doc/as.texinfo (Target PowerPC): Document -mpower9 and -mpwr9.
+ * doc/c-ppc.texi (PowerPC-Opts): Likewise.
+ * config/tc-ppc.c (md_show_usage): Likewise.
+ (md_assemble): Handle BFD_RELOC_PPC_REL16DX_HA.
+ (md_apply_fix): Likewise.
+ (ppc_handle_align): Handle power9's group ending nop.
+
+ gas/testsuite/
+ * gas/ppc/altivec3.s: New test.
+ * gas/ppc/altivec3.d: Likewise.
+ * gas/ppc/vsx3.s: Likewise.
+ * gas/ppc/vsx3.d: Likewise.
+ * gas/ppc/power9.s: Likewise.
+ * gas/ppc/power9.d: Likewise.
+ * gas/ppc/ppc.exp: Run them.
+ * gas/ppc/power8.s <lxvx, lxvd2x, stxvx, stxvd2x>: Add new tests.
+ * gas/ppc/power8.d: Likewise.
+ * gas/ppc/vsx.s: <lxvx, stxvx>: Rename invalid mnemonics ...
+ <lxvd2x, stxvd2x>: ...to this.
+ * gas/ppc/vsx.d: Likewise.
+
+ gold/
+ * gold/powerpc.cc (Powerpc_relocate_functions::addr16_dq): New function.
+ (Powerpc_relocate_functions::addr16dx_ha): Likewise.
+ (Target_powerpc::Scan::local): Handle R_POWERPC_REL16DX_HA.
+ (Target_powerpc::Scan::global): Likewise.
+ (Target_powerpc::Relocate::relocate): Likewise.
+
+ ld/testsuite/
+ * ld-powerpc/addpcis.d: New test.
+ * ld-powerpc/addpcis.s: New test.
+ * ld-powerpc/powerpc.exp: Run it.
+
+### a/bfd/ChangeLog
+### b/bfd/ChangeLog
+## -1,3 +1,21 @@
++2015-11-11 Alan Modra <amodra@gmail.com>
++ Peter Bergner <bergner@vnet.ibm.com>
++
++ * elf32-ppc.c (ppc_elf_howto_raw): Add R_PPC_REL16DX_HA.
++ (ppc_elf_reloc_type_lookup): Handle R_PPC_REL16DX_HA.
++ (ppc_elf_addr16_ha_reloc): Likewise.
++ (ppc_elf_check_relocs): Likewise.
++ (ppc_elf_relocate_section): Likewise.
++ (is_insn_dq_form): Handle lxv and stxv instructions.
++ * elf64-ppc.c (ppc64_elf_howto_raw): Add R_PPC64_REL16DX_HA.
++ (ppc64_elf_reloc_type_lookup): Handle R_PPC64_REL16DX_HA.
++ (ppc64_elf_ha_reloc): Likewise.
++ (ppc64_elf_check_relocs): Likewise.
++ (ppc64_elf_relocate_section): Likewise.
++ * bfd-in2.h: Regenerate.
++ * libbfd.h: Likewise.
++ * reloc.c (BFD_RELOC_PPC_REL16DX_HA): New.
++
+ 2015-11-10 H.J. Lu <hongjiu.lu@intel.com>
+
+ * elf32-i386.c (elf_i386_relocate_section): Handle VTINHERIT
+--- a/bfd/bfd-in2.h
++++ b/bfd/bfd-in2.h
+@@ -3303,6 +3303,7 @@ instruction. */
+ BFD_RELOC_PPC_VLE_SDAREL_HI16D,
+ BFD_RELOC_PPC_VLE_SDAREL_HA16A,
+ BFD_RELOC_PPC_VLE_SDAREL_HA16D,
++ BFD_RELOC_PPC_REL16DX_HA,
+ BFD_RELOC_PPC64_HIGHER,
+ BFD_RELOC_PPC64_HIGHER_S,
+ BFD_RELOC_PPC64_HIGHEST,
+--- a/bfd/elf32-ppc.c
++++ b/bfd/elf32-ppc.c
+@@ -1731,6 +1731,21 @@ static reloc_howto_type ppc_elf_howto_raw[] = {
+ 0xffff, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
++ /* Like R_PPC_REL16_HA but for split field in addpcis. */
++ HOWTO (R_PPC_REL16DX_HA, /* type */
++ 16, /* rightshift */
++ 2, /* size (0 = byte, 1 = short, 2 = long) */
++ 16, /* bitsize */
++ TRUE, /* pc_relative */
++ 0, /* bitpos */
++ complain_overflow_signed, /* complain_on_overflow */
++ ppc_elf_addr16_ha_reloc, /* special_function */
++ "R_PPC_REL16DX_HA", /* name */
++ FALSE, /* partial_inplace */
++ 0, /* src_mask */
++ 0x1fffc1, /* dst_mask */
++ TRUE), /* pcrel_offset */
++
+ /* GNU extension to record C++ vtable hierarchy. */
+ HOWTO (R_PPC_GNU_VTINHERIT, /* type */
+ 0, /* rightshift */
+@@ -1989,6 +2004,7 @@ ppc_elf_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
+ case BFD_RELOC_LO16_PCREL: r = R_PPC_REL16_LO; break;
+ case BFD_RELOC_HI16_PCREL: r = R_PPC_REL16_HI; break;
+ case BFD_RELOC_HI16_S_PCREL: r = R_PPC_REL16_HA; break;
++ case BFD_RELOC_PPC_REL16DX_HA: r = R_PPC_REL16DX_HA; break;
+ case BFD_RELOC_VTABLE_INHERIT: r = R_PPC_GNU_VTINHERIT; break;
+ case BFD_RELOC_VTABLE_ENTRY: r = R_PPC_GNU_VTENTRY; break;
+ }
+@@ -2058,7 +2074,10 @@ ppc_elf_addr16_ha_reloc (bfd *abfd ATTRIBUTE_UNUSED,
+ bfd *output_bfd,
+ char **error_message ATTRIBUTE_UNUSED)
+ {
+- bfd_vma relocation;
++ enum elf_ppc_reloc_type r_type;
++ long insn;
++ bfd_size_type octets;
++ bfd_vma value;
+
+ if (output_bfd != NULL)
+ {
+@@ -2066,20 +2085,28 @@ ppc_elf_addr16_ha_reloc (bfd *abfd ATTRIBUTE_UNUSED,
+ return bfd_reloc_ok;
+ }
+
+- if (bfd_is_com_section (symbol->section))
+- relocation = 0;
+- else
+- relocation = symbol->value;
+-
+- relocation += symbol->section->output_section->vma;
+- relocation += symbol->section->output_offset;
+- relocation += reloc_entry->addend;
+- if (reloc_entry->howto->pc_relative)
+- relocation -= reloc_entry->address;
+-
+- reloc_entry->addend += (relocation & 0x8000) << 1;
+-
+- return bfd_reloc_continue;
++ reloc_entry->addend += 0x8000;
++ r_type = reloc_entry->howto->type;
++ if (r_type != R_PPC_REL16DX_HA)
++ return bfd_reloc_continue;
++
++ value = 0;
++ if (!bfd_is_com_section (symbol->section))
++ value = symbol->value;
++ value += (reloc_entry->addend
++ + symbol->section->output_offset
++ + symbol->section->output_section->vma);
++ value -= (reloc_entry->address
++ + input_section->output_offset
++ + input_section->output_section->vma);
++ value >>= 16;
++
++ octets = reloc_entry->address * bfd_octets_per_byte (abfd);
++ insn = bfd_get_32 (abfd, (bfd_byte *) data + octets);
++ insn &= ~0x1fffc1;
++ insn |= (value & 0xffc1) | ((value & 0x3e) << 15);
++ bfd_put_32 (abfd, insn, (bfd_byte *) data + octets);
++ return bfd_reloc_ok;
+ }
+
+ static bfd_reloc_status_type
+@@ -4247,6 +4274,7 @@ ppc_elf_check_relocs (bfd *abfd,
+ case R_PPC_REL16_LO:
+ case R_PPC_REL16_HI:
+ case R_PPC_REL16_HA:
++ case R_PPC_REL16DX_HA:
+ ppc_elf_tdata (abfd)->has_rel16 = 1;
+ break;
+
+@@ -7604,7 +7632,9 @@ is_insn_ds_form (unsigned int insn)
+ static bfd_boolean
+ is_insn_dq_form (unsigned int insn)
+ {
+- return (insn & (0x3f << 26)) == 56u << 26; /* lq */
++ return ((insn & (0x3f << 26)) == 56u << 26 /* lq */
++ || ((insn & (0x3f << 26)) == (61u << 26) /* lxv, stxv */
++ && (insn & 3) == 1));
+ }
+
+ /* The RELOCATE_SECTION function is called by the ELF backend linker
+@@ -8605,6 +8635,7 @@ ppc_elf_relocate_section (bfd *output_bfd,
+ case R_PPC_REL16_LO:
+ case R_PPC_REL16_HI:
+ case R_PPC_REL16_HA:
++ case R_PPC_REL16DX_HA:
+ break;
+
+ case R_PPC_REL32:
+@@ -9311,6 +9342,7 @@ ppc_elf_relocate_section (bfd *output_bfd,
+
+ case R_PPC_ADDR16_HA:
+ case R_PPC_REL16_HA:
++ case R_PPC_REL16DX_HA:
+ case R_PPC_SECTOFF_HA:
+ case R_PPC_TPREL16_HA:
+ case R_PPC_DTPREL16_HA:
+@@ -9369,10 +9401,12 @@ ppc_elf_relocate_section (bfd *output_bfd,
+ mask = 15;
+ else
+ break;
+- lobit = mask & (relocation + addend);
++ relocation += addend;
++ addend = insn & mask;
++ lobit = mask & relocation;
+ if (lobit != 0)
+ {
+- addend -= lobit;
++ relocation ^= lobit;
+ info->callbacks->einfo
+ (_("%P: %H: error: %s against `%s' not a multiple of %u\n"),
+ input_bfd, input_section, rel->r_offset,
+@@ -9380,7 +9414,6 @@ ppc_elf_relocate_section (bfd *output_bfd,
+ bfd_set_error (bfd_error_bad_value);
+ ret = FALSE;
+ }
+- addend += insn & mask;
+ }
+ break;
+ }
+@@ -9439,8 +9472,30 @@ ppc_elf_relocate_section (bfd *output_bfd,
+ }
+ }
+
+- r = _bfd_final_link_relocate (howto, input_bfd, input_section, contents,
+- rel->r_offset, relocation, addend);
++ if (r_type == R_PPC_REL16DX_HA)
++ {
++ /* Split field reloc isn't handled by _bfd_final_link_relocate. */
++ if (rel->r_offset + 4 > input_section->size)
++ r = bfd_reloc_outofrange;
++ else
++ {
++ unsigned int insn;
++
++ relocation += addend;
++ relocation -= (rel->r_offset
++ + input_section->output_offset
++ + input_section->output_section->vma);
++ relocation >>= 16;
++ insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
++ insn &= ~0x1fffc1;
++ insn |= (relocation & 0xffc1) | ((relocation & 0x3e) << 15);
++ bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
++ r = bfd_reloc_ok;
++ }
++ }
++ else
++ r = _bfd_final_link_relocate (howto, input_bfd, input_section, contents,
++ rel->r_offset, relocation, addend);
+
+ if (r != bfd_reloc_ok)
+ {
+--- a/bfd/elf64-ppc.c
++++ b/bfd/elf64-ppc.c
+@@ -2022,6 +2022,21 @@ static reloc_howto_type ppc64_elf_howto_raw[] = {
+ 0xffff, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
++ /* Like R_PPC64_REL16_HA but for split field in addpcis. */
++ HOWTO (R_PPC64_REL16DX_HA, /* type */
++ 16, /* rightshift */
++ 2, /* size (0 = byte, 1 = short, 2 = long) */
++ 16, /* bitsize */
++ TRUE, /* pc_relative */
++ 0, /* bitpos */
++ complain_overflow_signed, /* complain_on_overflow */
++ ppc64_elf_ha_reloc, /* special_function */
++ "R_PPC64_REL16DX_HA", /* name */
++ FALSE, /* partial_inplace */
++ 0, /* src_mask */
++ 0x1fffc1, /* dst_mask */
++ TRUE), /* pcrel_offset */
++
+ /* Like R_PPC64_ADDR16_HI, but no overflow. */
+ HOWTO (R_PPC64_ADDR16_HIGH, /* type */
+ 16, /* rightshift */
+@@ -2412,6 +2427,8 @@ ppc64_elf_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
+ break;
+ case BFD_RELOC_HI16_S_PCREL: r = R_PPC64_REL16_HA;
+ break;
++ case BFD_RELOC_PPC_REL16DX_HA: r = R_PPC64_REL16DX_HA;
++ break;
+ case BFD_RELOC_PPC64_ADDR64_LOCAL: r = R_PPC64_ADDR64_LOCAL;
+ break;
+ case BFD_RELOC_VTABLE_INHERIT: r = R_PPC64_GNU_VTINHERIT;
+@@ -2466,6 +2483,11 @@ ppc64_elf_ha_reloc (bfd *abfd, arelent *reloc_entry, asymbol *symbol,
+ void *data, asection *input_section,
+ bfd *output_bfd, char **error_message)
+ {
++ enum elf_ppc64_reloc_type r_type;
++ long insn;
++ bfd_size_type octets;
++ bfd_vma value;
++
+ /* If this is a relocatable link (output_bfd test tells us), just
+ call the generic function. Any adjustment will be done at final
+ link time. */
+@@ -2477,7 +2499,29 @@ ppc64_elf_ha_reloc (bfd *abfd, arelent *reloc_entry, asymbol *symbol,
+ We won't actually be using the low 16 bits, so trashing them
+ doesn't matter. */
+ reloc_entry->addend += 0x8000;
+- return bfd_reloc_continue;
++ r_type = reloc_entry->howto->type;
++ if (r_type != R_PPC64_REL16DX_HA)
++ return bfd_reloc_continue;
++
++ value = 0;
++ if (!bfd_is_com_section (symbol->section))
++ value = symbol->value;
++ value += (reloc_entry->addend
++ + symbol->section->output_offset
++ + symbol->section->output_section->vma);
++ value -= (reloc_entry->address
++ + input_section->output_offset
++ + input_section->output_section->vma);
++ value = (bfd_signed_vma) value >> 16;
++
++ octets = reloc_entry->address * bfd_octets_per_byte (abfd);
++ insn = bfd_get_32 (abfd, (bfd_byte *) data + octets);
++ insn &= ~0x1fffc1;
++ insn |= (value & 0xffc1) | ((value & 0x3e) << 15);
++ bfd_put_32 (abfd, insn, (bfd_byte *) data + octets);
++ if (value + 0x8000 > 0xffff)
++ return bfd_reloc_overflow;
++ return bfd_reloc_ok;
+ }
+
+ static bfd_reloc_status_type
+@@ -5502,6 +5546,7 @@ ppc64_elf_check_relocs (bfd *abfd, struct bfd_link_info *info,
+ case R_PPC64_REL16_LO:
+ case R_PPC64_REL16_HI:
+ case R_PPC64_REL16_HA:
++ case R_PPC64_REL16DX_HA:
+ break;
+
+ /* Not supported as a dynamic relocation. */
+@@ -14430,6 +14475,7 @@ ppc64_elf_relocate_section (bfd *output_bfd,
+ case R_PPC64_REL16_LO:
+ case R_PPC64_REL16_HI:
+ case R_PPC64_REL16_HA:
++ case R_PPC64_REL16DX_HA:
+ break;
+
+ case R_PPC64_REL14:
+@@ -14842,6 +14888,7 @@ ppc64_elf_relocate_section (bfd *output_bfd,
+ break;
+
+ case R_PPC64_REL16_HA:
++ case R_PPC64_REL16DX_HA:
+ case R_PPC64_ADDR16_HA:
+ case R_PPC64_ADDR16_HIGHA:
+ case R_PPC64_ADDR16_HIGHERA:
+@@ -14897,16 +14944,20 @@ ppc64_elf_relocate_section (bfd *output_bfd,
+ case R_PPC64_DTPREL16_LO_DS:
+ insn = bfd_get_32 (input_bfd, contents + (rel->r_offset & ~3));
+ mask = 3;
+- /* If this reloc is against an lq insn, then the value must be
+- a multiple of 16. This is somewhat of a hack, but the
+- "correct" way to do this by defining _DQ forms of all the
+- _DS relocs bloats all reloc switches in this file. It
+- doesn't seem to make much sense to use any of these relocs
+- in data, so testing the insn should be safe. */
+- if ((insn & (0x3f << 26)) == (56u << 26))
++ /* If this reloc is against an lq, lxv, or stxv insn, then
++ the value must be a multiple of 16. This is somewhat of
++ a hack, but the "correct" way to do this by defining _DQ
++ forms of all the _DS relocs bloats all reloc switches in
++ this file. It doesn't make much sense to use these
++ relocs in data, so testing the insn should be safe. */
++ if ((insn & (0x3f << 26)) == (56u << 26)
++ || ((insn & (0x3f << 26)) == (61u << 26) && (insn & 3) == 1))
+ mask = 15;
+- if (((relocation + addend) & mask) != 0)
++ relocation += addend;
++ addend = insn & (mask ^ 3);
++ if ((relocation & mask) != 0)
+ {
++ relocation ^= relocation & mask;
+ info->callbacks->einfo
+ (_("%P: %H: error: %s not a multiple of %u\n"),
+ input_bfd, input_section, rel->r_offset,
+@@ -14964,8 +15015,30 @@ ppc64_elf_relocate_section (bfd *output_bfd,
+ }
+ }
+
+- r = _bfd_final_link_relocate (howto, input_bfd, input_section, contents,
+- rel->r_offset, relocation, addend);
++ if (r_type == R_PPC64_REL16DX_HA)
++ {
++ /* Split field reloc isn't handled by _bfd_final_link_relocate. */
++ if (rel->r_offset + 4 > input_section->size)
++ r = bfd_reloc_outofrange;
++ else
++ {
++ relocation += addend;
++ relocation -= (rel->r_offset
++ + input_section->output_offset
++ + input_section->output_section->vma);
++ relocation = (bfd_signed_vma) relocation >> 16;
++ insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
++ insn &= ~0x1fffc1;
++ insn |= (relocation & 0xffc1) | ((relocation & 0x3e) << 15);
++ bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
++ r = bfd_reloc_ok;
++ if (relocation + 0x8000 > 0xffff)
++ r = bfd_reloc_overflow;
++ }
++ }
++ else
++ r = _bfd_final_link_relocate (howto, input_bfd, input_section, contents,
++ rel->r_offset, relocation, addend);
+
+ if (r != bfd_reloc_ok)
+ {
+--- a/bfd/libbfd.h
++++ b/bfd/libbfd.h
+@@ -1391,6 +1391,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
+ "BFD_RELOC_PPC_VLE_SDAREL_HI16D",
+ "BFD_RELOC_PPC_VLE_SDAREL_HA16A",
+ "BFD_RELOC_PPC_VLE_SDAREL_HA16D",
++ "BFD_RELOC_PPC_REL16DX_HA",
+ "BFD_RELOC_PPC64_HIGHER",
+ "BFD_RELOC_PPC64_HIGHER_S",
+ "BFD_RELOC_PPC64_HIGHEST",
+--- a/bfd/reloc.c
++++ b/bfd/reloc.c
+@@ -2890,6 +2890,8 @@ ENUMX
+ ENUMX
+ BFD_RELOC_PPC_VLE_SDAREL_HA16D
+ ENUMX
++ BFD_RELOC_PPC_REL16DX_HA
++ENUMX
+ BFD_RELOC_PPC64_HIGHER
+ ENUMX
+ BFD_RELOC_PPC64_HIGHER_S
+### a/include/elf/ChangeLog
+### b/include/elf/ChangeLog
+## -1,3 +1,9 @@
++2015-11-11 Alan Modra <amodra@gmail.com>
++ Peter Bergner <bergner@vnet.ibm.com>
++
++ * ppc.h (R_PPC_REL16DX_HA): New reloction.
++ * ppc64.h (R_PPC64_REL16DX_HA): Likewise.
++
+ 2015-10-28 Cupertino Miranda <cmiranda@synopsys.com>
+
+ * arc-reloc.def (ARC_32_PCREL): New definition.
+--- a/include/elf/ppc.h
++++ b/include/elf/ppc.h
+@@ -149,6 +149,9 @@ START_RELOC_NUMBERS (elf_ppc_reloc_type)
+ RELOC_NUMBER (R_PPC_VLE_SDAREL_HA16A, 231)
+ RELOC_NUMBER (R_PPC_VLE_SDAREL_HA16D, 232)
+
++/* Power9 split rel16 for addpcis. */
++ RELOC_NUMBER (R_PPC_REL16DX_HA, 246)
++
+ /* Support STT_GNU_IFUNC plt calls. */
+ RELOC_NUMBER (R_PPC_IRELATIVE, 248)
+
+--- a/include/elf/ppc64.h
++++ b/include/elf/ppc64.h
+@@ -157,6 +157,10 @@ START_RELOC_NUMBERS (elf_ppc64_reloc_type)
+ /* Fake relocation only used internally by ld. */
+ RELOC_NUMBER (R_PPC64_LO_DS_OPT, 128)
+ #endif
++
++/* Power9 split rel16 for addpcis. */
++ RELOC_NUMBER (R_PPC64_REL16DX_HA, 246)
++
+ /* Support STT_GNU_IFUNC plt calls. */
+ RELOC_NUMBER (R_PPC64_JMP_IREL, 247)
+ RELOC_NUMBER (R_PPC64_IRELATIVE, 248)
+### a/include/opcode/ChangeLog
+### b/include/opcode/ChangeLog
+## -1,3 +1,9 @@
++2015-11-11 Alan Modra <amodra@gmail.com>
++ Peter Bergner <bergner@vnet.ibm.com>
++
++ * ppc.h (PPC_OPCODE_POWER9): New define.
++ (PPC_OPCODE_VSX3): Likewise.
++
+ 2015-11-02 Nick Clifton <nickc@redhat.com>
+
+ * rx.h (enum RX_Opcode_ID): Add more NOP opcodes.
+--- a/include/opcode/ppc.h
++++ b/include/opcode/ppc.h
+@@ -204,6 +204,12 @@ extern const int vle_num_opcodes;
+ /* Opcode is supported by ppc821/850/860. */
+ #define PPC_OPCODE_860 0x10000000000ull
+
++/* Opcode is only supported by Power9 architecture. */
++#define PPC_OPCODE_POWER9 0x20000000000ull
++
++/* Opcode is supported by Vector-Scalar (VSX) Unit from ISA 2.08. */
++#define PPC_OPCODE_VSX3 0x40000000000ull
++
+ /* A macro to extract the major opcode from an instruction. */
+ #define PPC_OP(i) (((i) >> 26) & 0x3f)
+
+### a/opcodes/ChangeLog
+### b/opcodes/ChangeLog
+## -1,3 +1,54 @@
++2015-11-11 Alan Modra <amodra@gmail.com>
++ Peter Bergner <bergner@vnet.ibm.com>
++
++ * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
++ Add PPC_OPCODE_VSX3 to the vsx entry.
++ (powerpc_init_dialect): Set default dialect to power9.
++ * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
++ insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
++ extract_l1 insert_xtq6, extract_xtq6): New static functions.
++ (insert_esync): Test for illegal L operand value.
++ (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
++ XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
++ XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
++ XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
++ PPCVSX3): New defines.
++ (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
++ fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
++ <mcrxr>: Use XBFRARB_MASK.
++ <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
++ bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
++ cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
++ cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
++ lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
++ lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
++ modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
++ rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
++ stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
++ subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
++ vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
++ vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
++ vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
++ vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
++ vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
++ vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
++ vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
++ xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
++ xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
++ xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
++ xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
++ xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
++ xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
++ xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
++ xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
++ xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
++ xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
++ xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
++ xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
++ xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
++ <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
++ <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
++
+ 2015-11-02 Nick Clifton <nickc@redhat.com>
+
+ * rx-decode.opc (rx_decode_opcode): Decode extra NOP
+--- a/opcodes/ppc-dis.c
++++ b/opcodes/ppc-dis.c
+@@ -157,6 +157,12 @@ struct ppc_mopt ppc_opts[] = {
+ | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_HTM
+ | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_VSX),
+ 0 },
++ { "power9", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
++ | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
++ | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
++ | PPC_OPCODE_HTM | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2
++ | PPC_OPCODE_VSX | PPC_OPCODE_VSX3 ),
++ 0 },
+ { "ppc", (PPC_OPCODE_PPC),
+ 0 },
+ { "ppc32", (PPC_OPCODE_PPC),
+@@ -191,6 +197,12 @@ struct ppc_mopt ppc_opts[] = {
+ | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_HTM
+ | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_VSX),
+ 0 },
++ { "pwr9", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
++ | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
++ | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
++ | PPC_OPCODE_HTM | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2
++ | PPC_OPCODE_VSX | PPC_OPCODE_VSX3 ),
++ 0 },
+ { "pwrx", (PPC_OPCODE_POWER | PPC_OPCODE_POWER2),
+ 0 },
+ { "spe", (PPC_OPCODE_PPC | PPC_OPCODE_EFS),
+@@ -201,7 +213,7 @@ struct ppc_mopt ppc_opts[] = {
+ { "vle", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_VLE),
+ PPC_OPCODE_VLE },
+ { "vsx", (PPC_OPCODE_PPC),
+- PPC_OPCODE_VSX },
++ PPC_OPCODE_VSX | PPC_OPCODE_VSX3 },
+ { "htm", (PPC_OPCODE_PPC),
+ PPC_OPCODE_HTM },
+ };
+@@ -303,7 +315,7 @@ powerpc_init_dialect (struct disassemble_info *info)
+ dialect = ppc_parse_cpu (dialect, &sticky, "vle");
+ break;
+ default:
+- dialect = ppc_parse_cpu (dialect, &sticky, "power8") | PPC_OPCODE_ANY;
++ dialect = ppc_parse_cpu (dialect, &sticky, "power9") | PPC_OPCODE_ANY;
+ }
+
+ arg = info->disassembler_options;
+--- a/opcodes/ppc-opc.c
++++ b/opcodes/ppc-opc.c
+@@ -54,8 +54,18 @@ static long extract_bo (unsigned long, ppc_cpu_t, int *);
+ static unsigned long insert_boe (unsigned long, long, ppc_cpu_t, const char **);
+ static long extract_boe (unsigned long, ppc_cpu_t, int *);
+ static unsigned long insert_esync (unsigned long, long, ppc_cpu_t, const char **);
++static unsigned long insert_dcmxs (unsigned long, long, ppc_cpu_t, const char **);
++static long extract_dcmxs (unsigned long, ppc_cpu_t, int *);
++static unsigned long insert_dxd (unsigned long, long, ppc_cpu_t, const char **);
++static long extract_dxd (unsigned long, ppc_cpu_t, int *);
++static unsigned long insert_dxdn (unsigned long, long, ppc_cpu_t, const char **);
++static long extract_dxdn (unsigned long, ppc_cpu_t, int *);
+ static unsigned long insert_fxm (unsigned long, long, ppc_cpu_t, const char **);
+ static long extract_fxm (unsigned long, ppc_cpu_t, int *);
++static unsigned long insert_l0 (unsigned long, long, ppc_cpu_t, const char **);
++static long extract_l0 (unsigned long, ppc_cpu_t, int *);
++static unsigned long insert_l1 (unsigned long, long, ppc_cpu_t, const char **);
++static long extract_l1 (unsigned long, ppc_cpu_t, int *);
+ static unsigned long insert_li20 (unsigned long, long, ppc_cpu_t, const char **);
+ static long extract_li20 (unsigned long, ppc_cpu_t, int *);
+ static unsigned long insert_ls (unsigned long, long, ppc_cpu_t, const char **);
+@@ -98,6 +108,8 @@ static unsigned long insert_tbr (unsigned long, long, ppc_cpu_t, const char **);
+ static long extract_tbr (unsigned long, ppc_cpu_t, int *);
+ static unsigned long insert_xt6 (unsigned long, long, ppc_cpu_t, const char **);
+ static long extract_xt6 (unsigned long, ppc_cpu_t, int *);
++static unsigned long insert_xtq6 (unsigned long, long, ppc_cpu_t, const char **);
++static long extract_xtq6 (unsigned long, ppc_cpu_t, int *);
+ static unsigned long insert_xa6 (unsigned long, long, ppc_cpu_t, const char **);
+ static long extract_xa6 (unsigned long, ppc_cpu_t, int *);
+ static unsigned long insert_xb6 (unsigned long, long, ppc_cpu_t, const char **);
+@@ -302,9 +314,17 @@ const struct powerpc_operand powerpc_operands[] =
+ #define D8 D + 1
+ { 0xff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
+
++ /* The DCMX field in an X form instruction. */
++#define DCMX D8 + 1
++ { 0x7f, 16, NULL, NULL, 0 },
++
++ /* The split DCMX field in an X form instruction. */
++#define DCMXS DCMX + 1
++ { 0x7f, PPC_OPSHIFT_INV, insert_dcmxs, extract_dcmxs, 0 },
++
+ /* The DQ field in a DQ form instruction. This is like D, but the
+ lower four bits are forced to zero. */
+-#define DQ D8 + 1
++#define DQ DCMXS + 1
+ { 0xfff0, 0, NULL, NULL,
+ PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
+
+@@ -320,10 +340,21 @@ const struct powerpc_operand powerpc_operands[] =
+ #define BHRBE DUIS
+ { 0x3ff, 11, NULL, NULL, 0 },
+
++ /* The split D field in a DX form instruction. */
++#define DXD DUIS + 1
++ { 0xffff, PPC_OPSHIFT_INV, insert_dxd, extract_dxd,
++ PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT},
++
++ /* The split ND field in a DX form instruction.
++ This is the same as the DX field, only negated. */
++#define NDXD DXD + 1
++ { 0xffff, PPC_OPSHIFT_INV, insert_dxdn, extract_dxdn,
++ PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT},
++
+ /* The E field in a wrteei instruction. */
+ /* And the W bit in the pair singles instructions. */
+ /* And the ST field in a VX form instruction. */
+-#define E DUIS + 1
++#define E NDXD + 1
+ #define PSW E
+ #define ST E
+ { 0x1, 15, NULL, NULL, 0 },
+@@ -397,8 +428,16 @@ const struct powerpc_operand powerpc_operands[] =
+ #define HTM_R L
+ { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
+
++ /* The L field in an X form instruction which must be zero. */
++#define L0 L + 1
++ { 0x1, 21, insert_l0, extract_l0, PPC_OPERAND_OPTIONAL },
++
++ /* The L field in an X form instruction which must be one. */
++#define L1 L0 + 1
++ { 0x1, 21, insert_l1, extract_l1, 0 },
++
+ /* The LEV field in a POWER SVC form instruction. */
+-#define SVC_LEV L + 1
++#define SVC_LEV L1 + 1
+ { 0x7f, 5, NULL, NULL, 0 },
+
+ /* The LEV field in an SC form instruction. */
+@@ -513,10 +552,14 @@ const struct powerpc_operand powerpc_operands[] =
+ #define RBOPT RBX + 1
+ { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
+
++ /* The RC register field in an maddld, maddhd or maddhdu instruction. */
++#define RC RBOPT + 1
++ { 0x1f, 6, NULL, NULL, PPC_OPERAND_GPR },
++
+ /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
+ instruction or the RT field in a D, DS, X, XFX or XO form
+ instruction. */
+-#define RS RBOPT + 1
++#define RS RC + 1
+ #define RT RS
+ #define RT_MASK (0x1f << 21)
+ #define RD RS
+@@ -577,6 +620,8 @@ const struct powerpc_operand powerpc_operands[] =
+ #define SH_MASK (0x1f << 11)
+ /* The other UIMM field in a EVX form instruction. */
+ #define EVUIMM SH
++ /* The FC field in an atomic X form instruction. */
++#define FC SH
+ { 0x1f, 11, NULL, NULL, 0 },
+
+ /* The SI field in a HTM X form instruction. */
+@@ -705,8 +750,12 @@ const struct powerpc_operand powerpc_operands[] =
+ #define UIMM3 UIMM + 1
+ { 0x7, 16, NULL, NULL, 0 },
+
++ /* The 6-bit UIM field in a X form instruction. */
++#define UIM6 UIMM3 + 1
++ { 0x3f, 16, NULL, NULL, 0 },
++
+ /* The SIX field in a VX form instruction. */
+-#define SIX UIMM3 + 1
++#define SIX UIM6 + 1
+ { 0xf, 11, NULL, NULL, 0 },
+
+ /* The PS field in a VX form instruction. */
+@@ -752,9 +801,10 @@ const struct powerpc_operand powerpc_operands[] =
+ #define PSD PSQM + 1
+ { 0xfff, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
+
+- /* The L field in an mtmsrd or A form instruction or W in an X form. */
++ /* The L field in an mtmsrd or A form instruction or R or W in an X form. */
+ #define A_L PSD + 1
+ #define W A_L
++#define X_R A_L
+ { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
+
+ #define RMC A_L + 1
+@@ -763,7 +813,13 @@ const struct powerpc_operand powerpc_operands[] =
+ #define R RMC + 1
+ { 0x1, 16, NULL, NULL, 0 },
+
+-#define SP R + 1
++#define RIC R + 1
++ { 0x3, 18, NULL, NULL, PPC_OPERAND_OPTIONAL },
++
++#define PRS RIC + 1
++ { 0x1, 17, NULL, NULL, PPC_OPERAND_OPTIONAL },
++
++#define SP PRS + 1
+ { 0x3, 19, NULL, NULL, 0 },
+
+ #define S SP + 1
+@@ -838,8 +894,13 @@ const struct powerpc_operand powerpc_operands[] =
+ #define XT6 XS6
+ { 0x3f, PPC_OPSHIFT_INV, insert_xt6, extract_xt6, PPC_OPERAND_VSR },
+
++ /* The XT and XS fields in an DQ form VSX instruction. This is split. */
++#define XSQ6 XT6 + 1
++#define XTQ6 XSQ6
++ { 0x3f, PPC_OPSHIFT_INV, insert_xtq6, extract_xtq6, PPC_OPERAND_VSR },
++
+ /* The XA field in an XX3 form instruction. This is split. */
+-#define XA6 XT6 + 1
++#define XA6 XTQ6 + 1
+ { 0x3f, PPC_OPSHIFT_INV, insert_xa6, extract_xa6, PPC_OPERAND_VSR },
+
+ /* The XB field in an XX2 or XX3 form instruction. This is split. */
+@@ -869,6 +930,8 @@ const struct powerpc_operand powerpc_operands[] =
+ #define UIM DMEX + 1
+ /* The 2-bit UIMM field in a VX form instruction. */
+ #define UIMM2 UIM
++ /* The 2-bit L field in a darn instruction. */
++#define LRAND UIM
+ { 0x3, 16, NULL, NULL, 0 },
+
+ #define ERAT_T UIM + 1
+@@ -876,6 +939,10 @@ const struct powerpc_operand powerpc_operands[] =
+
+ #define IH ERAT_T + 1
+ { 0x7, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
++
++ /* The 8-bit IMM8 field in a XX1 form instruction. */
++#define IMM8 IH + 1
++ { 0xff, 11, NULL, NULL, 0 },
+ };
+
+ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
+@@ -1272,6 +1339,64 @@ extract_boe (unsigned long insn,
+ return value & 0x1e;
+ }
+
++/* The DCMX field in a X form instruction when the field is split
++ into separate DC, DM and DX fields. */
++
++static unsigned long
++insert_dcmxs (unsigned long insn,
++ long value,
++ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
++ const char **errmsg ATTRIBUTE_UNUSED)
++{
++ return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3) | (value & 0x40);
++}
++
++static long
++extract_dcmxs (unsigned long insn,
++ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
++ int *invalid ATTRIBUTE_UNUSED)
++{
++ return (insn & 0x40) | ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f);
++}
++
++/* The D field in a DX form instruction when the field is split
++ into separate D0, D1 and D2 fields. */
++
++static unsigned long
++insert_dxd (unsigned long insn,
++ long value,
++ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
++ const char **errmsg ATTRIBUTE_UNUSED)
++{
++ return insn | (value & 0xffc1) | ((value & 0x3e) << 15);
++}
++
++static long
++extract_dxd (unsigned long insn,
++ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
++ int *invalid ATTRIBUTE_UNUSED)
++{
++ unsigned long dxd = (insn & 0xffc1) | ((insn >> 15) & 0x3e);
++ return (dxd ^ 0x8000) - 0x8000;
++}
++
++static unsigned long
++insert_dxdn (unsigned long insn,
++ long value,
++ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
++ const char **errmsg ATTRIBUTE_UNUSED)
++{
++ return insert_dxd (insn, -value, dialect, errmsg);
++}
++
++static long
++extract_dxdn (unsigned long insn,
++ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
++ int *invalid ATTRIBUTE_UNUSED)
++{
++ return -extract_dxd (insn, dialect, invalid);
++}
++
+ /* FXM mask in mfcr and mtcrf instructions. */
+
+ static unsigned long
+@@ -1343,6 +1468,58 @@ extract_fxm (unsigned long insn,
+ return mask;
+ }
+
++/* The L field in an X form instruction which must have the value zero. */
++
++static unsigned long
++insert_l0 (unsigned long insn,
++ long value,
++ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
++ const char **errmsg)
++{
++ if (value != 0)
++ *errmsg = _("invalid operand constant");
++ return insn & ~(0x1 << 21);
++}
++
++static long
++extract_l0 (unsigned long insn,
++ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
++ int *invalid)
++{
++ long value;
++
++ value = (insn >> 21) & 0x1;
++ if (value != 0)
++ *invalid = 1;
++ return value;
++}
++
++/* The L field in an X form instruction which must have the value one. */
++
++static unsigned long
++insert_l1 (unsigned long insn,
++ long value,
++ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
++ const char **errmsg)
++{
++ if (value != 1)
++ *errmsg = _("invalid operand constant");
++ return insn | (0x1 << 21);
++}
++
++static long
++extract_l1 (unsigned long insn,
++ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
++ int *invalid)
++{
++ long value;
++
++ value = (insn >> 21) & 0x1;
++ if (value != 1)
++ *invalid = 1;
++ return value;
++}
++
+ static unsigned long
+ insert_li20 (unsigned long insn,
+ long value,
+@@ -1398,16 +1575,16 @@ insert_ls (unsigned long insn,
+ static unsigned long
+ insert_esync (unsigned long insn,
+ long value,
+- ppc_cpu_t dialect ATTRIBUTE_UNUSED,
++ ppc_cpu_t dialect,
+ const char **errmsg)
+ {
+- unsigned long ls;
++ unsigned long ls = (insn >> 21) & 0x03;
+
+- ls = (insn >> 21) & 0x03;
+ if (value == 0)
+ {
+- if (ls > 1)
+- *errmsg = _("illegal L operand value");
++ if (((dialect & PPC_OPCODE_E6500) != 0 && ls > 1)
++ || ((dialect & PPC_OPCODE_POWER9) != 0 && ls > 2))
++ *errmsg = _("illegal L operand value");
+ return insn;
+ }
+
+@@ -1945,6 +2122,24 @@ extract_xt6 (unsigned long insn,
+ return ((insn << 5) & 0x20) | ((insn >> 21) & 0x1f);
+ }
+
++/* The XT and XS fields in an DQ form VSX instruction. This is split. */
++static unsigned long
++insert_xtq6 (unsigned long insn,
++ long value,
++ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
++ const char **errmsg ATTRIBUTE_UNUSED)
++{
++ return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 2);
++}
++
++static long
++extract_xtq6 (unsigned long insn,
++ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
++ int *invalid ATTRIBUTE_UNUSED)
++{
++ return ((insn << 2) & 0x20) | ((insn >> 21) & 0x1f);
++}
++
+ /* The XA field in an XX3 form instruction. This is split. */
+
+ static unsigned long
+@@ -2258,10 +2453,18 @@ extract_vleil (unsigned long insn,
+ /* The main opcode mask with the RA field clear. */
+ #define DRA_MASK (OP_MASK | RA_MASK)
+
++/* A DQ form VSX instruction. */
++#define DQX(op, xop) (OP (op) | ((xop) & 0x7))
++#define DQX_MASK DQX (0x3f, 7)
++
+ /* A DS form instruction. */
+ #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
+ #define DS_MASK DSO (0x3f, 3)
+
++/* An DX form instruction. */
++#define DX(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
++#define DX_MASK DX (0x3f, 0x1f)
++
+ /* An EVSEL form instruction. */
+ #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
+ #define EVSEL_MASK EVSEL(0x3f, 0xff)
+@@ -2374,6 +2577,9 @@ extract_vleil (unsigned long insn,
+ /* A VX_MASK with a PS field. */
+ #define VXPS_MASK (VX_MASK & ~(0x1 << 9))
+
++/* A VX_MASK with the VA field fixed with a PS field. */
++#define VXVAPS_MASK ((VX_MASK | (0x1f << 16)) & ~(0x1 << 9))
++
+ /* A VA form instruction. */
+ #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
+
+@@ -2389,9 +2595,15 @@ extract_vleil (unsigned long insn,
+ /* The mask for a VXR form instruction. */
+ #define VXR_MASK VXR(0x3f, 0x3ff, 1)
+
++/* A VX form instruction with a VA tertiary opcode. */
++#define VXVA(op, xop, vaop) (VX(op,xop) | (((vaop) & 0x1f) << 16))
++
+ /* An X form instruction. */
+ #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
+
++/* A X form instruction for Quad-Precision FP Instructions. */
++#define XVA(op, xop, vaop) (X(op,xop) | (((vaop) & 0x1f) << 16))
++
+ /* An EX form instruction. */
+ #define EX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
+
+@@ -2401,6 +2613,9 @@ extract_vleil (unsigned long insn,
+ /* An XX2 form instruction. */
+ #define XX2(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2))
+
++/* A XX2 form instruction with the VA bits specified. */
++#define XX2VA(op, xop, vaop) (XX2(op,xop) | (((vaop) & 0x1f) << 16))
++
+ /* An XX3 form instruction. */
+ #define XX3(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0xff) << 3))
+
+@@ -2416,12 +2631,18 @@ extract_vleil (unsigned long insn,
+ /* An X form instruction with the RC bit specified. */
+ #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
+
++/* A X form instruction for Quad-Precision FP Instructions with RC bit. */
++#define XVARC(op, xop, vaop, rc) (XVA ((op), (xop), (vaop)) | ((rc) & 1))
++
+ /* A Z form instruction with the RC bit specified. */
+ #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
+
+ /* The mask for an X form instruction. */
+ #define X_MASK XRC (0x3f, 0x3ff, 1)
+
++/* The mask for an X form instruction with the BF bits specified. */
++#define XBF_MASK (X_MASK | (3 << 21))
++
+ /* An X form wait instruction with everything filled in except the WC field. */
+ #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
+
+@@ -2437,9 +2658,18 @@ extract_vleil (unsigned long insn,
+ /* The mask for an XX2 form instruction with the UIM bits specified. */
+ #define XX2UIM_MASK (XX2 (0x3f, 0x1ff) | (7 << 18))
+
++/* The mask for an XX2 form instruction with the 4 UIM bits specified. */
++#define XX2UIM4_MASK (XX2 (0x3f, 0x1ff) | (1 << 20))
++
+ /* The mask for an XX2 form instruction with the BF bits specified. */
+ #define XX2BF_MASK (XX2_MASK | (3 << 21) | (1))
+
++/* The mask for an XX2 form instruction with the BF and DCMX bits specified. */
++#define XX2BFD_MASK (XX2 (0x3f, 0x1ff) | 1)
++
++/* The mask for an XX2 form instruction with a split DCMX bits specified. */
++#define XX2DCMXS_MASK XX2 (0x3f, 0x1ee)
++
+ /* The mask for an XX3 form instruction. */
+ #define XX3_MASK XX3 (0x3f, 0xff)
+
+@@ -2460,11 +2690,13 @@ extract_vleil (unsigned long insn,
+ #define Z_MASK ZRC (0x3f, 0x1ff, 1)
+ #define Z2_MASK ZRC (0x3f, 0xff, 1)
+
+-/* An X_MASK with the RA field fixed. */
++/* An X_MASK with the RA/VA field fixed. */
+ #define XRA_MASK (X_MASK | RA_MASK)
++#define XVA_MASK XRA_MASK
+
+-/* An XRA_MASK with the W field clear. */
++/* An XRA_MASK with the A_L/W field clear. */
+ #define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16))
++#define XRLA_MASK XWRA_MASK
+
+ /* An X_MASK with the RB field fixed. */
+ #define XRB_MASK (X_MASK | RB_MASK)
+@@ -2478,9 +2710,15 @@ extract_vleil (unsigned long insn,
+ /* An X_MASK with the RA and RB fields fixed. */
+ #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
+
++/* An XBF_MASK with the RA and RB fields fixed. */
++#define XBFRARB_MASK (XBF_MASK | RA_MASK | RB_MASK)
++
+ /* An XRARB_MASK, but with the L bit clear. */
+ #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
+
++/* An XRARB_MASK, but with the L bits in a darn instruction clear. */
++#define XLRAND_MASK (XRARB_MASK & ~((unsigned long) 3 << 16))
++
+ /* An X_MASK with the RT and RA fields fixed. */
+ #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
+
+@@ -2738,6 +2976,7 @@ extract_vleil (unsigned long insn,
+ #define POWER6 PPC_OPCODE_POWER6
+ #define POWER7 PPC_OPCODE_POWER7
+ #define POWER8 PPC_OPCODE_POWER8
++#define POWER9 PPC_OPCODE_POWER9
+ #define CELL PPC_OPCODE_CELL
+ #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_64_BRIDGE
+ #define NON32 (PPC_OPCODE_64 | PPC_OPCODE_POWER4 \
+@@ -2753,8 +2992,10 @@ extract_vleil (unsigned long insn,
+ #define PPCPS PPC_OPCODE_PPCPS
+ #define PPCVEC PPC_OPCODE_ALTIVEC
+ #define PPCVEC2 PPC_OPCODE_ALTIVEC2
++#define PPCVEC3 PPC_OPCODE_ALTIVEC2
+ #define PPCVSX PPC_OPCODE_VSX
+ #define PPCVSX2 PPC_OPCODE_VSX
++#define PPCVSX3 PPC_OPCODE_VSX3
+ #define POWER PPC_OPCODE_POWER
+ #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
+ #define PWR2COM PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
+@@ -2864,11 +3105,13 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"twi", OP(3), OP_MASK, PPCCOM, PPCNONE, {TO, RA, SI}},
+ {"ti", OP(3), OP_MASK, PWRCOM, PPCNONE, {TO, RA, SI}},
+
+-{"ps_cmpu0", X (4, 0), X_MASK|(3<<21), PPCPS, PPCNONE, {BF, FRA, FRB}},
++{"ps_cmpu0", X (4, 0), XBF_MASK, PPCPS, PPCNONE, {BF, FRA, FRB}},
+ {"vaddubm", VX (4, 0), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
++{"vmul10cuq", VX (4, 1), VXVB_MASK, PPCVEC3, PPCNONE, {VD, VA}},
+ {"vmaxub", VX (4, 2), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+ {"vrlb", VX (4, 4), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+ {"vcmpequb", VXR(4, 6,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
++{"vcmpneb", VXR(4, 7,0), VXR_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}},
+ {"vmuloub", VX (4, 8), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+ {"vaddfp", VX (4, 10), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+ {"psq_lx", XW (4, 6,0), XW_MASK, PPCPS, PPCNONE, {FRT,RA,RB,PSWM,PSQM}},
+@@ -2914,6 +3157,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VC, VB}},
+ {"ps_sel.", A (4, 23,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
+ {"vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VC, VB}},
++{"maddhd", VXA(4, 48), VXA_MASK, POWER9, PPCNONE, {RT, RA, RB, RC}},
++{"maddhdu", VXA(4, 49), VXA_MASK, POWER9, PPCNONE, {RT, RA, RB, RC}},
++{"maddld", VXA(4, 51), VXA_MASK, POWER9, PPCNONE, {RT, RA, RB, RC}},
+ {"ps_res", A (4, 24,0), AFRAFRC_MASK, PPCPS, PPCNONE, {FRT, FRB}},
+ {"ps_res.", A (4, 24,1), AFRAFRC_MASK, PPCPS, PPCNONE, {FRT, FRB}},
+ {"ps_mul", A (4, 25,0), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}},
+@@ -2928,15 +3174,18 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"ps_nmsub.", A (4, 30,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
+ {"ps_nmadd", A (4, 31,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
+ {"ps_nmadd.", A (4, 31,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
+-{"ps_cmpo0", X (4, 32), X_MASK|(3<<21), PPCPS, PPCNONE, {BF, FRA, FRB}},
++{"ps_cmpo0", X (4, 32), XBF_MASK, PPCPS, PPCNONE, {BF, FRA, FRB}},
++{"vpermr", VXA(4, 59), VXA_MASK, PPCVEC3, PPCNONE, {VD, VA, VB, VC}},
+ {"vaddeuqm", VXA(4, 60), VXA_MASK, PPCVEC2, PPCNONE, {VD, VA, VB, VC}},
+ {"vaddecuq", VXA(4, 61), VXA_MASK, PPCVEC2, PPCNONE, {VD, VA, VB, VC}},
+ {"vsubeuqm", VXA(4, 62), VXA_MASK, PPCVEC2, PPCNONE, {VD, VA, VB, VC}},
+ {"vsubecuq", VXA(4, 63), VXA_MASK, PPCVEC2, PPCNONE, {VD, VA, VB, VC}},
+ {"vadduhm", VX (4, 64), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
++{"vmul10ecuq", VX (4, 65), VX_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}},
+ {"vmaxuh", VX (4, 66), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+ {"vrlh", VX (4, 68), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+ {"vcmpequh", VXR(4, 70,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
++{"vcmpneh", VXR(4, 71,0), VXR_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}},
+ {"vmulouh", VX (4, 72), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+ {"vsubfp", VX (4, 74), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+ {"psq_lux", XW (4, 38,0), XW_MASK, PPCPS, PPCNONE, {FRT,RA,RB,PSWM,PSQM}},
+@@ -2951,11 +3200,13 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"machhw.", XO (4, 44,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+ {"nmachhw", XO (4, 46,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+ {"nmachhw.", XO (4, 46,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"ps_cmpu1", X (4, 64), X_MASK|(3<<21), PPCPS, PPCNONE, {BF, FRA, FRB}},
++{"ps_cmpu1", X (4, 64), XBF_MASK, PPCPS, PPCNONE, {BF, FRA, FRB}},
+ {"vadduwm", VX (4, 128), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+ {"vmaxuw", VX (4, 130), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+ {"vrlw", VX (4, 132), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
++{"vrlwmi", VX (4, 133), VX_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}},
+ {"vcmpequw", VXR(4, 134,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
++{"vcmpnew", VXR(4, 135,0), VXR_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}},
+ {"vmulouw", VX (4, 136), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+ {"vmuluwm", VX (4, 137), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+ {"vmrghw", VX (4, 140), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+@@ -2964,10 +3215,11 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"ps_mr.", XRC(4, 72,1), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}},
+ {"machhwsu", XO (4, 76,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+ {"machhwsu.", XO (4, 76,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"ps_cmpo1", X (4, 96), X_MASK|(3<<21), PPCPS, PPCNONE, {BF, FRA, FRB}},
++{"ps_cmpo1", X (4, 96), XBF_MASK, PPCPS, PPCNONE, {BF, FRA, FRB}},
+ {"vaddudm", VX (4, 192), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+ {"vmaxud", VX (4, 194), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+ {"vrld", VX (4, 196), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
++{"vrldmi", VX (4, 197), VX_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}},
+ {"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+ {"vcmpequd", VXR(4, 199,0), VXR_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+ {"vpkuwus", VX (4, 206), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+@@ -2977,6 +3229,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"nmachhws.", XO (4, 110,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+ {"vadduqm", VX (4, 256), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+ {"vmaxsb", VX (4, 258), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
++{"vcmpnezb", VXR(4, 263,0), VXR_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}},
+ {"vslb", VX (4, 260), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+ {"vmulosb", VX (4, 264), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+ {"vrefp", VX (4, 266), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}},
+@@ -2991,6 +3244,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"vaddcuq", VX (4, 320), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+ {"vmaxsh", VX (4, 322), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+ {"vslh", VX (4, 324), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
++{"vcmpnezh", VXR(4, 327,0), VXR_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}},
+ {"vmulosh", VX (4, 328), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+ {"vrsqrtefp", VX (4, 330), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}},
+ {"vmrglh", VX (4, 332), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+@@ -3004,6 +3258,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"vaddcuw", VX (4, 384), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+ {"vmaxsw", VX (4, 386), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+ {"vslw", VX (4, 388), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
++{"vrlwnm", VX (4, 389), VX_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}},
++{"vcmpnezw", VXR(4, 391,0), VXR_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}},
+ {"vmulosw", VX (4, 392), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+ {"vexptefp", VX (4, 394), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}},
+ {"vmrglw", VX (4, 396), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+@@ -3012,6 +3268,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"macchwsu.", XO (4, 204,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+ {"vmaxsd", VX (4, 450), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+ {"vsl", VX (4, 452), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
++{"vrldnm", VX (4, 453), VX_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}},
+ {"vcmpgefp", VXR(4, 454,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+ {"vlogefp", VX (4, 458), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}},
+ {"vpkswss", VX (4, 462), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+@@ -3021,6 +3278,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"nmacchws.", XO (4, 238,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+ {"evaddw", VX (4, 512), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+ {"vaddubs", VX (4, 512), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
++{"vmul10uq", VX (4, 513), VXVB_MASK, PPCVEC3, PPCNONE, {VD, VA}},
+ {"evaddiw", VX (4, 514), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RB, UIMM}},
+ {"vminub", VX (4, 514), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+ {"evsubfw", VX (4, 516), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+@@ -3037,6 +3295,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"evextsh", VX (4, 523), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
+ {"evrndw", VX (4, 524), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
+ {"vspltb", VX (4, 524), VXUIMM4_MASK,PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM4}},
++{"vextractub", VX (4, 525), VXUIMM4_MASK,PPCVEC3, PPCNONE, {VD, VB, UIMM4}},
+ {"evcntlzw", VX (4, 525), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
+ {"evcntlsw", VX (4, 526), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
+ {"vupkhsb", VX (4, 526), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}},
+@@ -3075,12 +3334,14 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"evcmpeq", VX (4, 564), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {CRFD, RA, RB}},
+ {"cget", APU(4, 284,0), APU_RA_MASK, PPC405, PPCNONE, {RT, FSL}},
+ {"vadduhs", VX (4, 576), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
++{"vmul10euq", VX (4, 577), VX_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}},
+ {"vminuh", VX (4, 578), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+ {"vsrh", VX (4, 580), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+ {"vcmpgtuh", VXR(4, 582,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+ {"vmuleuh", VX (4, 584), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+ {"vrfiz", VX (4, 586), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}},
+ {"vsplth", VX (4, 588), VXUIMM3_MASK,PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM3}},
++{"vextractuh", VX (4, 589), VXUIMM4_MASK,PPCVEC3, PPCNONE, {VD, VB, UIMM4}},
+ {"vupkhsh", VX (4, 590), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}},
+ {"nget", APU(4, 300,0), APU_RA_MASK, PPC405, PPCNONE, {RT, FSL}},
+ {"evsel", EVSEL(4,79), EVSEL_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB, CRFS}},
+@@ -3100,6 +3361,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"vrfip", VX (4, 650), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}},
+ {"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {CRFD, RA, RB}},
+ {"vspltw", VX (4, 652), VXUIMM2_MASK,PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM2}},
++{"vextractuw", VX (4, 653), VXUIMM4_MASK,PPCVEC3, PPCNONE, {VD, VB, UIMM4}},
+ {"evfscmplt", VX (4, 653), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {CRFD, RA, RB}},
+ {"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {CRFD, RA, RB}},
+ {"vupklsb", VX (4, 654), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}},
+@@ -3131,6 +3393,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"efsdiv", VX (4, 713), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA, RB}},
+ {"vrfim", VX (4, 714), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}},
+ {"efscmpgt", VX (4, 716), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {CRFD, RA, RB}},
++{"vextractd", VX (4, 717), VXUIMM4_MASK,PPCVEC3, PPCNONE, {VD, VB, UIMM4}},
+ {"efscmplt", VX (4, 717), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {CRFD, RA, RB}},
+ {"efscmpeq", VX (4, 718), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {CRFD, RA, RB}},
+ {"vupklsh", VX (4, 718), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}},
+@@ -3195,6 +3458,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"vcuxwfp", VX (4, 778), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}},
+ {"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+ {"vspltisb", VX (4, 780), VXVB_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, SIMM}},
++{"vinsertb", VX (4, 781), VXUIMM4_MASK,PPCVEC3, PPCNONE, {VD, VB, UIMM4}},
+ {"evlhhousplat",VX (4, 781), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_2, RA}},
+ {"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+ {"vpkpx", VX (4, 782), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+@@ -3228,6 +3492,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"evstwwox", VX (4, 828), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+ {"evstwwo", VX (4, 829), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_4, RA}},
+ {"vaddshs", VX (4, 832), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
++{"bcdcpsgn.", VX (4, 833), VX_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}},
+ {"vminsh", VX (4, 834), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+ {"vsrah", VX (4, 836), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+ {"vcmpgtsh", VXR(4, 838,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+@@ -3235,6 +3500,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"vcfsx", VX (4, 842), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}},
+ {"vcsxwfp", VX (4, 842), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}},
+ {"vspltish", VX (4, 844), VXVB_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, SIMM}},
++{"vinserth", VX (4, 845), VXUIMM4_MASK,PPCVEC3, PPCNONE, {VD, VB, UIMM4}},
+ {"vupkhpx", VX (4, 846), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}},
+ {"mullhw", XRC(4, 424,0), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+ {"mullhw.", XRC(4, 424,1), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+@@ -3250,6 +3516,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"vctuxs", VX (4, 906), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}},
+ {"vcfpuxws", VX (4, 906), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}},
+ {"vspltisw", VX (4, 908), VXVB_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, SIMM}},
++{"vinsertw", VX (4, 909), VXUIMM4_MASK,PPCVEC3, PPCNONE, {VD, VB, UIMM4}},
+ {"maclhwsu", XO (4, 460,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+ {"maclhwsu.", XO (4, 460,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+ {"vminsd", VX (4, 962), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+@@ -3258,6 +3525,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"vcmpgtsd", VXR(4, 967,0), VXR_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+ {"vctsxs", VX (4, 970), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}},
+ {"vcfpsxws", VX (4, 970), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}},
++{"vinsertd", VX (4, 973), VXUIMM4_MASK,PPCVEC3, PPCNONE, {VD, VB, UIMM4}},
+ {"vupklpx", VX (4, 974), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}},
+ {"maclhws", XO (4, 492,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+ {"maclhws.", XO (4, 492,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+@@ -3270,6 +3538,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"evmhessf", VX (4,1027), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+ {"vand", VX (4,1028), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+ {"vcmpequb.", VXR(4, 6,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
++{"vcmpneb.", VXR(4, 7,1), VXR_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}},
+ {"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
+ {"udi0fcm", APU(4, 515,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
+ {"evmhossf", VX (4,1031), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+@@ -3302,6 +3571,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"vcmpequh.", VXR(4, 70,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+ {"udi1fcm.", APU(4, 547,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
+ {"udi1fcm", APU(4, 547,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
++{"vcmpneh.", VXR(4, 71,1), VXR_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}},
+ {"evmwhssf", VX (4,1095), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+ {"vpmsumh", VX (4,1096), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+ {"evmwlumi", VX (4,1096), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+@@ -3331,10 +3601,12 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"evmwsmia", VX (4,1145), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+ {"evmwsmfa", VX (4,1147), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+ {"vsubuwm", VX (4,1152), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
++{"bcdus.", VX (4,1153), VX_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}},
+ {"vavguw", VX (4,1154), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+ {"vabsduw", VX (4,1155), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+ {"vmr", VX (4,1156), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VBA}},
+ {"vor", VX (4,1156), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
++{"vcmpnew.", VXR(4, 135,1), VXR_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}},
+ {"vpmsumw", VX (4,1160), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+ {"vcmpequw.", VXR(4, 134,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+ {"udi2fcm.", APU(4, 579,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
+@@ -3345,6 +3617,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"ps_merge10.", XOPS(4,592,1), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
+ {"vsubudm", VX (4,1216), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+ {"evaddusiaaw", VX (4,1216), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
++{"bcds.", VX (4,1217), VXPS_MASK, PPCVEC3, PPCNONE, {VD, VA, VB, PS}},
+ {"evaddssiaaw", VX (4,1217), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
+ {"evsubfusiaaw",VX (4,1218), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
+ {"evsubfssiaaw",VX (4,1219), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
+@@ -3370,6 +3643,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"ps_merge11.", XOPS(4,624,1), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
+ {"vsubuqm", VX (4,1280), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+ {"evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
++{"bcdtrunc.", VX (4,1281), VXPS_MASK, PPCVEC3, PPCNONE, {VD, VA, VB, PS}},
+ {"evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+ {"vavgsb", VX (4,1282), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+ {"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+@@ -3379,6 +3653,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+ {"udi4fcm.", APU(4, 643,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
+ {"udi4fcm", APU(4, 643,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
++{"vcmpnezb.", VXR(4, 263,1), VXR_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}},
+ {"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+ {"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+ {"vcipher", VX (4,1288), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+@@ -3399,11 +3674,13 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+ {"vsubcuq", VX (4,1344), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+ {"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
++{"bcdutrunc.", VX (4,1345), VX_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}},
+ {"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+ {"vavgsh", VX (4,1346), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+ {"vorc", VX (4,1348), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+ {"udi5fcm.", APU(4, 675,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
+ {"udi5fcm", APU(4, 675,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
++{"vcmpnezh.", VXR(4, 327,1), VXR_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}},
+ {"vncipher", VX (4,1352), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+ {"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+ {"vncipherlast",VX (4,1353), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+@@ -3421,6 +3698,13 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"evmheusianw", VX (4,1408), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+ {"vsubcuw", VX (4,1408), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+ {"evmhessianw", VX (4,1409), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
++{"bcdctsq.", VXVA(4,1409,0), VXVA_MASK, PPCVEC3, PPCNONE, {VD, VB}},
++{"bcdcfsq.", VXVA(4,1409,2), VXVAPS_MASK, PPCVEC3, PPCNONE, {VD, VB, PS}},
++{"bcdctz.", VXVA(4,1409,4), VXVAPS_MASK, PPCVEC3, PPCNONE, {VD, VB, PS}},
++{"bcdctn.", VXVA(4,1409,5), VXVA_MASK, PPCVEC3, PPCNONE, {VD, VB}},
++{"bcdcfz.", VXVA(4,1409,6), VXVAPS_MASK, PPCVEC3, PPCNONE, {VD, VB, PS}},
++{"bcdcfn.", VXVA(4,1409,7), VXVAPS_MASK, PPCVEC3, PPCNONE, {VD, VB, PS}},
++{"bcdsetsgn.", VXVA(4,1409,31),VXVAPS_MASK, PPCVEC3, PPCNONE, {VD, VB, PS}},
+ {"vavgsw", VX (4,1410), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+ {"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+ {"vnand", VX (4,1412), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+@@ -3428,6 +3712,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"evmhossianw", VX (4,1413), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+ {"udi6fcm.", APU(4, 707,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
+ {"udi6fcm", APU(4, 707,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
++{"vcmpnezw.", VXR(4, 391,1), VXR_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}},
+ {"evmhossfanw", VX (4,1415), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+ {"evmheumianw", VX (4,1416), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+ {"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+@@ -3444,6 +3729,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"evmhogsmian", VX (4,1453), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+ {"evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+ {"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
++{"bcdsr.", VX (4,1473), VXPS_MASK, PPCVEC3, PPCNONE, {VD, VA, VB, PS}},
+ {"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+ {"vsld", VX (4,1476), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+ {"vcmpgefp.", VXR(4, 454,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+@@ -3452,6 +3738,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"vsbox", VX (4,1480), VXVB_MASK, PPCVEC2, PPCNONE, {VD, VA}},
+ {"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+ {"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
++{"vbpermd", VX (4,1484), VX_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}},
+ {"vpksdss", VX (4,1486), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+ {"evmwssfan", VX (4,1491), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+ {"macchwso", XO (4, 236,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+@@ -3462,17 +3749,35 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"nmacchwso", XO (4, 238,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+ {"nmacchwso.", XO (4, 238,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+ {"vsububs", VX (4,1536), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
++{"vclzlsbb", VXVA(4,1538,0), VXVA_MASK, PPCVEC3, PPCNONE, {RT, VB}},
++{"vctzlsbb", VXVA(4,1538,1), VXVA_MASK, PPCVEC3, PPCNONE, {RT, VB}},
++{"vnegw", VXVA(4,1538,6), VXVA_MASK, PPCVEC3, PPCNONE, {VD, VB}},
++{"vnegd", VXVA(4,1538,7), VXVA_MASK, PPCVEC3, PPCNONE, {VD, VB}},
++{"vprtybw", VXVA(4,1538,8), VXVA_MASK, PPCVEC3, PPCNONE, {VD, VB}},
++{"vprtybd", VXVA(4,1538,9), VXVA_MASK, PPCVEC3, PPCNONE, {VD, VB}},
++{"vprtybq", VXVA(4,1538,10),VXVA_MASK, PPCVEC3, PPCNONE, {VD, VB}},
++{"vextsb2w", VXVA(4,1538,16),VXVA_MASK, PPCVEC3, PPCNONE, {VD, VB}},
++{"vextsh2w", VXVA(4,1538,17),VXVA_MASK, PPCVEC3, PPCNONE, {VD, VB}},
++{"vextsb2d", VXVA(4,1538,24),VXVA_MASK, PPCVEC3, PPCNONE, {VD, VB}},
++{"vextsh2d", VXVA(4,1538,25),VXVA_MASK, PPCVEC3, PPCNONE, {VD, VB}},
++{"vextsw2d", VXVA(4,1538,26),VXVA_MASK, PPCVEC3, PPCNONE, {VD, VB}},
++{"vctzb", VXVA(4,1538,28),VXVA_MASK, PPCVEC3, PPCNONE, {VD, VB}},
++{"vctzh", VXVA(4,1538,29),VXVA_MASK, PPCVEC3, PPCNONE, {VD, VB}},
++{"vctzw", VXVA(4,1538,30),VXVA_MASK, PPCVEC3, PPCNONE, {VD, VB}},
++{"vctzd", VXVA(4,1538,31),VXVA_MASK, PPCVEC3, PPCNONE, {VD, VB}},
+ {"mfvscr", VX (4,1540), VXVAVB_MASK, PPCVEC|PPCVLE, PPCNONE, {VD}},
+ {"vcmpgtub.", VXR(4, 518,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+ {"udi8fcm.", APU(4, 771,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
+ {"udi8fcm", APU(4, 771,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
+ {"vsum4ubs", VX (4,1544), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
++{"vextublx", VX (4,1549), VX_MASK, PPCVEC3, PPCNONE, {RT, RA, VB}},
+ {"vsubuhs", VX (4,1600), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+ {"mtvscr", VX (4,1604), VXVDVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VB}},
+ {"vcmpgtuh.", VXR(4, 582,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+ {"vsum4shs", VX (4,1608), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+ {"udi9fcm.", APU(4, 804,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
+ {"udi9fcm", APU(4, 804,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
++{"vextuhlx", VX (4,1613), VX_MASK, PPCVEC3, PPCNONE, {RT, RA, VB}},
+ {"vupkhsw", VX (4,1614), VXVA_MASK, PPCVEC2, PPCNONE, {VD, VB}},
+ {"vsubuws", VX (4,1664), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+ {"vshasigmaw", VX (4,1666), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, ST, SIX}},
+@@ -3482,6 +3787,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"udi10fcm", APU(4, 835,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
+ {"vsum2sws", VX (4,1672), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+ {"vmrgow", VX (4,1676), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
++{"vextuwlx", VX (4,1677), VX_MASK, PPCVEC3, PPCNONE, {RT, RA, VB}},
+ {"vshasigmad", VX (4,1730), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, ST, SIX}},
+ {"vsrd", VX (4,1732), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+ {"vcmpgtfp.", VXR(4, 710,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+@@ -3492,16 +3798,20 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"vsubsbs", VX (4,1792), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+ {"vclzb", VX (4,1794), VXVA_MASK, PPCVEC2, PPCNONE, {VD, VB}},
+ {"vpopcntb", VX (4,1795), VXVA_MASK, PPCVEC2, PPCNONE, {VD, VB}},
++{"vsrv", VX (4,1796), VX_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}},
+ {"vcmpgtsb.", VXR(4, 774,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+ {"udi12fcm.", APU(4, 899,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
+ {"udi12fcm", APU(4, 899,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
+ {"vsum4sbs", VX (4,1800), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
++{"vextubrx", VX (4,1805), VX_MASK, PPCVEC3, PPCNONE, {RT, RA, VB}},
+ {"maclhwuo", XO (4, 396,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+ {"maclhwuo.", XO (4, 396,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+ {"vsubshs", VX (4,1856), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+ {"vclzh", VX (4,1858), VXVA_MASK, PPCVEC2, PPCNONE, {VD, VB}},
+ {"vpopcnth", VX (4,1859), VXVA_MASK, PPCVEC2, PPCNONE, {VD, VB}},
++{"vslv", VX (4,1860), VX_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}},
+ {"vcmpgtsh.", VXR(4, 838,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
++{"vextuhrx", VX (4,1869), VX_MASK, PPCVEC3, PPCNONE, {RT, RA, VB}},
+ {"udi13fcm.", APU(4, 931,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
+ {"udi13fcm", APU(4, 931,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
+ {"maclhwo", XO (4, 428,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+@@ -3516,6 +3826,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"udi14fcm", APU(4, 963,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
+ {"vsumsws", VX (4,1928), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+ {"vmrgew", VX (4,1932), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
++{"vextuwrx", VX (4,1933), VX_MASK, PPCVEC3, PPCNONE, {RT, RA, VB}},
+ {"maclhwsuo", XO (4, 460,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+ {"maclhwsuo.", XO (4, 460,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+ {"vclzd", VX (4,1986), VXVA_MASK, PPCVEC2, PPCNONE, {VD, VB}},
+@@ -3854,6 +4165,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+
+ {"mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, PPCNONE, {BF, BFA}},
+
++{"addpcis", DX(19,2), DX_MASK, POWER9, PPCNONE, {RT, DXD}},
++{"subpcis", DX(19,2), DX_MASK, POWER9, PPCNONE, {RT, NDXD}},
++
+ {"bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}},
+ {"bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2, {0}},
+ {"bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}},
+@@ -4113,17 +4427,20 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"crset", XL(19,289), XL_MASK, PPCCOM, PPCNONE, {BT, BAT, BBA}},
+ {"creqv", XL(19,289), XL_MASK, COM, PPCNONE, {BT, BA, BB}},
+
+-{"doze", XL(19,402), 0xffffffff, POWER6, PPCNONE, {0}},
++{"urfid", XL(19,306), 0xffffffff, POWER9, PPCNONE, {0}},
++{"stop", XL(19,370), 0xffffffff, POWER9, PPCNONE, {0}},
++
++{"doze", XL(19,402), 0xffffffff, POWER6, POWER9, {0}},
+
+ {"crorc", XL(19,417), XL_MASK, COM, PPCNONE, {BT, BA, BB}},
+
+-{"nap", XL(19,434), 0xffffffff, POWER6, PPCNONE, {0}},
++{"nap", XL(19,434), 0xffffffff, POWER6, POWER9, {0}},
+
+ {"crmove", XL(19,449), XL_MASK, PPCCOM, PPCNONE, {BT, BA, BBA}},
+ {"cror", XL(19,449), XL_MASK, COM, PPCNONE, {BT, BA, BB}},
+
+-{"sleep", XL(19,466), 0xffffffff, POWER6, PPCNONE, {0}},
+-{"rvwinkle", XL(19,498), 0xffffffff, POWER6, PPCNONE, {0}},
++{"sleep", XL(19,466), 0xffffffff, POWER6, POWER9, {0}},
++{"rvwinkle", XL(19,498), 0xffffffff, POWER6, POWER9, {0}},
+
+ {"bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, PPCNONE, {0}},
+ {"bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, PPCNONE, {0}},
+@@ -4459,7 +4776,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+
+ {"ldepx", X(31,29), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA0, RB}},
+
+-{"waitasec", X(31,30), XRTRARB_MASK,POWER8, PPCNONE, {0}},
++{"waitasec", X(31,30), XRTRARB_MASK,POWER8, POWER9, {0}},
++{"wait", X(31,30), XWC_MASK, POWER9, PPCNONE, {WC}},
+
+ {"lwepx", X(31,31), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA0, RB}},
+
+@@ -4591,6 +4909,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+
+ {"dcbfep", XRT(31,127,0), XRT_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RA0, RB}},
+
++{"setb", X(31,128), XRB_MASK|(3<<16), POWER9, PPCNONE, {RT, BFA}},
++
+ {"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {RS}},
+
+ {"dcbtstls", X(31,134), X_MASK, PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA0, RB}},
+@@ -4673,6 +4993,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+
+ {"prtyd", X(31,186), XRB_MASK, POWER6|PPCA2, PPCNONE, {RA, RS}},
+
++{"cmprb", X(31,192), XCMP_MASK, POWER9, PPCNONE, {BF, L, RA, RB}},
++
+ {"icblq.", XRC(31,198,1), X_MASK, E6500, PPCNONE, {CT, RA0, RB}},
+
+ {"stvewx", X(31,199), X_MASK, PPCVEC, PPCNONE, {VS, RA0, RB}},
+@@ -4711,6 +5033,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+
+ {"stbepx", X(31,223), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RS, RA0, RB}},
+
++{"cmpeqb", X(31,224), XCMPL_MASK, POWER9, PPCNONE, {BF, RA, RB}},
++
+ {"icblc", X(31,230), X_MASK, PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA0, RB}},
+
+ {"stvx", X(31,231), X_MASK, PPCVEC|PPCVLE, PPCNONE, {VS, RA0, RB}},
+@@ -4770,14 +5094,22 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"doz", XO(31,264,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
+ {"doz.", XO(31,264,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
+
++{"modud", X(31,265), X_MASK, POWER9, PPCNONE, {RT, RA, RB}},
++
+ {"add", XO(31,266,0,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
+ {"cax", XO(31,266,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
+ {"add.", XO(31,266,0,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
+ {"cax.", XO(31,266,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
+
++{"moduw", X(31,267), X_MASK, POWER9, PPCNONE, {RT, RA, RB}},
++
++{"lxvx", X(31,268), XX1_MASK|1<<6, PPCVSX3, PPCNONE, {XT6, RA0, RB}},
++{"lxvl", X(31,269), XX1_MASK, PPCVSX3, PPCNONE, {XT6, RA0, RB}},
++
+ {"ehpriv", X(31,270), 0xffffffff, E500MC|PPCA2|PPCVLE, PPCNONE, {0}},
+
+-{"tlbiel", X(31,274), XRTLRA_MASK, POWER4, PPC476, {RB, L}},
++{"tlbiel", X(31,274), X_MASK|1<<20,POWER9, PPC476, {RB, RSO, RIC, PRS, X_R}},
++{"tlbiel", X(31,274), XRTLRA_MASK, POWER4, POWER9|PPC476, {RB, L}},
+
+ {"mfapidi", X(31,275), X_MASK, BOOKE, E500|TITAN, {RT, RA}},
+
+@@ -4805,12 +5137,19 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"lvexhx", X(31,293), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
+ {"lvepx", X(31,295), X_MASK, PPCVEC2|PPCVLE, PPCNONE, {VD, RA0, RB}},
+
++{"lxvll", X(31,301), XX1_MASK, PPCVSX3, PPCNONE, {XT6, RA0, RB}},
++
+ {"mfbhrbe", X(31,302), X_MASK, POWER8, PPCNONE, {RT, BHRBE}},
+
+-{"tlbie", X(31,306), XRA_MASK, POWER7, TITAN, {RB, RS}},
++{"tlbie", X(31,306), X_MASK|1<<20,POWER9, TITAN, {RB, RS, RIC, PRS, X_R}},
++{"tlbie", X(31,306), XRA_MASK, POWER7, POWER9|TITAN, {RB, RS}},
+ {"tlbie", X(31,306), XRTLRA_MASK, PPC, E500|POWER7|TITAN, {RB, L}},
+ {"tlbi", X(31,306), XRT_MASK, POWER, PPCNONE, {RA0, RB}},
+
++{"mfvsrld", X(31,307), XX1RB_MASK, PPCVSX3, PPCNONE, {RA, XS6}},
++
++{"ldmx", X(31,309), X_MASK, POWER9, PPCNONE, {RT, RA0, RB}},
++
+ {"eciwx", X(31,310), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
+
+ {"lhzux", X(31,311), X_MASK, COM|PPCVLE, PPCNONE, {RT, RAL, RB}},
+@@ -4871,6 +5210,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300|PPCVLE, PPCNONE, {RT, PMR}},
+ {"mftmr", X(31,366), X_MASK, PPCTMR|E6500, PPCNONE, {RT, TMR}},
+
++{"slbsync", X(31,338), 0xffffffff, POWER9, PPCNONE, {0}},
++
+ {"mfmq", XSPR(31,339, 0), XSPR_MASK, M601, PPCNONE, {RT}},
+ {"mfxer", XSPR(31,339, 1), XSPR_MASK, COM|PPCVLE, PPCNONE, {RT}},
+ {"mfrtcu", XSPR(31,339, 4), XSPR_MASK, COM, TITAN, {RT}},
+@@ -5087,6 +5428,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"divs", XO(31,363,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
+ {"divs.", XO(31,363,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
+
++{"lxvwsx", X(31,364), XX1_MASK, PPCVSX3, PPCNONE, {XT6, RA0, RB}},
++
+ {"tlbia", X(31,370), 0xffffffff, PPC, E500|TITAN, {0}},
+
+ {"mftbu", XSPR(31,371,269), XSPR_MASK, PPC, NO371|POWER4, {RT}},
+@@ -5114,10 +5457,15 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"divweu", XO(31,395,0,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
+ {"divweu.", XO(31,395,0,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
+
++{"stxvx", X(31,396), XX1_MASK, PPCVSX3, PPCNONE, {XS6, RA0, RB}},
++{"stxvl", X(31,397), XX1_MASK, PPCVSX3, PPCNONE, {XS6, RA0, RB}},
++
+ {"dcblce", X(31,398), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},
+
+ {"slbmte", X(31,402), XRA_MASK, PPC64, PPCNONE, {RS, RB}},
+
++{"mtvsrws", X(31,403), XX1RB_MASK, PPCVSX3, PPCNONE, {XT6, RA}},
++
+ {"pbt.", XRC(31,404,1), X_MASK, POWER8, PPCNONE, {RS, RA0, RB}},
+
+ {"icswx", XRC(31,406,0), X_MASK, POWER7|PPCA2, PPCNONE, {RS, RA, RB}},
+@@ -5141,10 +5489,14 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"divwe", XO(31,427,0,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
+ {"divwe.", XO(31,427,0,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
+
++{"stxvll", X(31,429), XX1_MASK, PPCVSX3, PPCNONE, {XS6, RA0, RB}},
++
+ {"clrbhrb", X(31,430), 0xffffffff, POWER8, PPCNONE, {0}},
+
+ {"slbie", X(31,434), XRTRA_MASK, PPC64, PPCNONE, {RB}},
+
++{"mtvsrdd", X(31,435), XX1_MASK, PPCVSX3, PPCNONE, {XT6, RA0, RB}},
++
+ {"ecowx", X(31,438), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
+
+ {"sthux", X(31,439), X_MASK, COM|PPCVLE, PPCNONE, {RS, RAS, RB}},
+@@ -5214,6 +5566,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300|PPCVLE, PPCNONE, {PMR, RS}},
+ {"mttmr", X(31,494), X_MASK, PPCTMR|E6500, PPCNONE, {TMR, RS}},
+
++{"slbieg", X(31,466), XRA_MASK, POWER9, PPCNONE, {RS, RB}},
++
+ {"mtmq", XSPR(31,467, 0), XSPR_MASK, M601, PPCNONE, {RS}},
+ {"mtxer", XSPR(31,467, 1), XSPR_MASK, COM|PPCVLE, PPCNONE, {RS}},
+ {"mtlr", XSPR(31,467, 8), XSPR_MASK, COM|PPCVLE, PPCNONE, {RS}},
+@@ -5413,7 +5767,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+
+ {"cmpb", X(31,508), X_MASK, POWER6|PPCA2|PPC476, PPCNONE, {RA, RS, RB}},
+
+-{"mcrxr", X(31,512), XRARB_MASK|(3<<21), COM|PPCVLE, POWER7, {BF}},
++{"mcrxr", X(31,512), XBFRARB_MASK, COM|PPCVLE, POWER7, {BF}},
+
+ {"lbdx", X(31,515), X_MASK, E500MC|PPCVLE, PPCNONE, {RT, RA, RB}},
+
+@@ -5456,6 +5810,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"rrib", XRC(31,537,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
+ {"rrib.", XRC(31,537,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
+
++{"cnttzw", XRC(31,538,0), XRB_MASK, POWER9, PPCNONE, {RA, RS}},
++{"cnttzw.", XRC(31,538,1), XRB_MASK, POWER9, PPCNONE, {RA, RS}},
++
+ {"srd", XRC(31,539,0), X_MASK, PPC64, PPCNONE, {RA, RS, RB}},
+ {"srd.", XRC(31,539,1), X_MASK, PPC64, PPCNONE, {RA, RS, RB}},
+
+@@ -5480,10 +5837,17 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+
+ {"lfsux", X(31,567), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},
+
++{"cnttzd", XRC(31,570,0), XRB_MASK, POWER9, PPCNONE, {RA, RS}},
++{"cnttzd.", XRC(31,570,1), XRB_MASK, POWER9, PPCNONE, {RA, RS}},
++
++{"mcrxrx", X(31,576), XBFRARB_MASK, POWER9, PPCNONE, {BF}},
++
+ {"lwdx", X(31,579), X_MASK, E500MC|PPCVLE, PPCNONE, {RT, RA, RB}},
+
+ {"lvtlx", X(31,581), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
+
++{"lwat", X(31,582), X_MASK, POWER9, PPCNONE, {RT, RA0, FC}},
++
+ {"lwfcmux", APU(31,583,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
+
+ {"lxsdx", X(31,588), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA0, RB}},
+@@ -5496,8 +5860,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"hwsync", XSYNC(31,598,0), 0xffffffff, POWER4, BOOKE|PPC476, {0}},
+ {"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, E500, {0}},
+ {"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, PPCNONE, {0}},
+-{"sync", X(31,598), XSYNCLE_MASK,E6500, PPCNONE, {LS, ESYNC}},
+-{"sync", X(31,598), XSYNC_MASK, PPCCOM|PPCVLE, BOOKE|PPC476, {LS}},
++{"sync", X(31,598), XSYNCLE_MASK,POWER9|E6500, PPCNONE, {LS, ESYNC}},
++{"sync", X(31,598), XSYNC_MASK, PPCCOM|PPCVLE, BOOKE|PPC476|POWER9, {LS}},
+ {"msync", X(31,598), 0xffffffff, BOOKE|PPCA2|PPC476, PPCNONE, {0}},
+ {"sync", X(31,598), 0xffffffff, BOOKE|PPC476, E6500, {0}},
+ {"lwsync", X(31,598), 0xffffffff, E500, PPCNONE, {0}},
+@@ -5512,6 +5876,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+
+ {"lvswx", X(31,613), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
+
++{"ldat", X(31,614), X_MASK, POWER9, PPCNONE, {RT, RA0, FC}},
++
+ {"lqfcmux", APU(31,615,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
+
+ {"nego", XO(31,104,1,0), XORB_MASK, COM|PPCVLE, PPCNONE, {RT, RA}},
+@@ -5584,6 +5950,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+
+ {"stvflx", X(31,709), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
+
++{"stwat", X(31,710), X_MASK, POWER9, PPCNONE, {RS, RA0, FC}},
++
+ {"stwfcmux", APU(31,711,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
+
+ {"stxsdx", X(31,716), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA0, RB}},
+@@ -5620,6 +5988,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+
+ {"stvswx", X(31,741), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
+
++{"stdat", X(31,742), X_MASK, POWER9, PPCNONE, {RS, RA0, FC}},
++
+ {"stqfcmux", APU(31,743,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
+
+ {"subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
+@@ -5644,6 +6014,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"tresume.", XRCL(31,750,1,1), XRTRARB_MASK,PPCHTM, PPCNONE, {0}},
+ {"tsr.", XRC(31,750,1), XRTLRARB_MASK,PPCHTM, PPCNONE, {L}},
+
++{"darn", X(31,755), XLRAND_MASK, POWER9, PPCNONE, {RT, LRAND}},
++
+ {"dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {RA0, RB}},
+ {"dcbal", XOPL(31,758,1), XRT_MASK, E500MC, PPCNONE, {RA0, RB}},
+
+@@ -5653,6 +6025,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"srliq.", XRC(31,760,1), X_MASK, M601, PPCNONE, {RA, RS, SH}},
+
+ {"lvsm", X(31,773), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
++
++{"copy_first", XOPL(31,774,1), XRT_MASK, POWER9, PPCNONE, {RA0, RB}},
++{"copy", X(31,774), XLRT_MASK, POWER9, PPCNONE, {RA0, RB, L}},
++
+ {"stvepxl", X(31,775), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
+ {"lvlxl", X(31,775), X_MASK, CELL, PPCNONE, {VD, RA0, RB}},
+ {"ldfcmux", APU(31,775,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
+@@ -5665,7 +6041,11 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"addo.", XO(31,266,1,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
+ {"caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
+
++{"modsd", X(31,777), X_MASK, POWER9, PPCNONE, {RT, RA, RB}},
++{"modsw", X(31,779), X_MASK, POWER9, PPCNONE, {RT, RA, RB}},
++
+ {"lxvw4x", X(31,780), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA0, RB}},
++{"lxsibzx", X(31,781), XX1_MASK, PPCVSX3, PPCNONE, {XT6, RA0, RB}},
+
+ {"tabortwc.", XRC(31,782,1), X_MASK, PPCHTM, PPCNONE, {TO, RA, RB}},
+
+@@ -5692,6 +6072,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"stvepx", X(31,807), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
+ {"lvrxl", X(31,807), X_MASK, CELL, PPCNONE, {VD, RA0, RB}},
+
++{"lxvh8x", X(31,812), XX1_MASK, PPCVSX3, PPCNONE, {XT6, RA0, RB}},
++{"lxsihzx", X(31,813), XX1_MASK, PPCVSX3, PPCNONE, {XT6, RA0, RB}},
++
+ {"tabortdc.", XRC(31,814,1), X_MASK, PPCHTM, PPCNONE, {TO, RA, RB}},
+
+ {"rac", X(31,818), X_MASK, M601, PPCNONE, {RT, RA, RB}},
+@@ -5714,17 +6097,20 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+
+ {"lvtlxl", X(31,837), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
+
++{"cp_abort", X(31,838), XRTRARB_MASK,POWER9, PPCNONE, {0}},
++
+ {"divo", XO(31,331,1,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
+ {"divo.", XO(31,331,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
+
+ {"lxvd2x", X(31,844), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA0, RB}},
+-{"lxvx", X(31,844), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA0, RB}},
++{"lxvx", X(31,844), XX1_MASK, POWER8, POWER9|PPCVSX3, {XT6, RA0, RB}},
+
+ {"tabortwci.", XRC(31,846,1), X_MASK, PPCHTM, PPCNONE, {TO, RA, HTM_SI}},
+
+ {"tlbsrx.", XRC(31,850,1), XRT_MASK, PPCA2, PPCNONE, {RA0, RB}},
+
+-{"slbmfev", X(31,851), XRA_MASK, PPC64, PPCNONE, {RT, RB}},
++{"slbmfev", X(31,851), XRLA_MASK, POWER9, PPCNONE, {RT, RB, A_L}},
++{"slbmfev", X(31,851), XRA_MASK, PPC64, POWER9, {RT, RB}},
+
+ {"lbzcix", X(31,853), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}},
+
+@@ -5743,12 +6129,25 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"divso", XO(31,363,1,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
+ {"divso.", XO(31,363,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
+
++{"lxvb16x", X(31,876), XX1_MASK, PPCVSX3, PPCNONE, {XT6, RA0, RB}},
++
+ {"tabortdci.", XRC(31,878,1), X_MASK, PPCHTM, PPCNONE, {TO, RA, HTM_SI}},
+
++{"rmieg", X(31,882), XRTRA_MASK, POWER9, PPCNONE, {RB}},
++
+ {"ldcix", X(31,885), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}},
+
++{"msgsync", X(31,886), 0xffffffff, POWER9, PPCNONE, {0}},
++
+ {"lfiwzx", X(31,887), X_MASK, POWER7|PPCA2, PPCNONE, {FRT, RA0, RB}},
+
++{"extswsli", XS(31,445,0), XS_MASK, POWER9, PPCNONE, {RA, RS, SH6}},
++{"extswsli.", XS(31,445,1), XS_MASK, POWER9, PPCNONE, {RA, RS, SH6}},
++
++{"paste", XRC(31,902,0), XLRT_MASK, POWER9, PPCNONE, {RA0, RB, L0}},
++{"paste_last", XRCL(31,902,1,1),XRT_MASK, POWER9, PPCNONE, {RA0, RB}},
++{"paste.", XRC(31,902,1), XLRT_MASK, POWER9, PPCNONE, {RA0, RB, L1}},
++
+ {"stvlxl", X(31,903), X_MASK, CELL, PPCNONE, {VS, RA0, RB}},
+ {"stdfcmux", APU(31,903,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
+
+@@ -5758,13 +6157,15 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"divweuo.", XO(31,395,1,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
+
+ {"stxvw4x", X(31,908), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA0, RB}},
++{"stxsibx", X(31,909), XX1_MASK, PPCVSX3, PPCNONE, {XS6, RA0, RB}},
+
+ {"tabort.", XRC(31,910,1), XRTRB_MASK, PPCHTM, PPCNONE, {RA}},
+
+ {"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RTO, RA0, RB}},
+ {"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RTO, RA0, RB}},
+
+-{"slbmfee", X(31,915), XRA_MASK, PPC64, PPCNONE, {RT, RB}},
++{"slbmfee", X(31,915), XRLA_MASK, POWER9, PPCNONE, {RT, RB, A_L}},
++{"slbmfee", X(31,915), XRA_MASK, PPC64, POWER9, {RT, RB}},
+
+ {"stwcix", X(31,917), X_MASK, POWER6, PPCNONE, {RS, RA0, RB}},
+
+@@ -5799,6 +6200,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"divweo", XO(31,427,1,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
+ {"divweo.", XO(31,427,1,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
+
++{"stxvh8x", X(31,940), XX1_MASK, PPCVSX3, PPCNONE, {XS6, RA0, RB}},
++{"stxsihx", X(31,941), XX1_MASK, PPCVSX3, PPCNONE, {XS6, RA0, RB}},
++
+ {"treclaim.", XRC(31,942,1), XRTRB_MASK, PPCHTM, PPCNONE, {RA}},
+
+ {"tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, PPCA2, {RT, RA}},
+@@ -5830,7 +6234,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"divwuo.", XO(31,459,1,1), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
+
+ {"stxvd2x", X(31,972), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA0, RB}},
+-{"stxvx", X(31,972), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA0, RB}},
++{"stxvx", X(31,972), XX1_MASK, POWER8, POWER9|PPCVSX3, {XS6, RA0, RB}},
+
+ {"tlbld", X(31,978), XRTRA_MASK, PPC, PPC403|BOOKE|PPCA2|PPC476, {RB}},
+ {"tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, PPCNONE, {RT, RA}},
+@@ -5863,6 +6267,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"divwo", XO(31,491,1,0), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
+ {"divwo.", XO(31,491,1,1), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
+
++{"stxvb16x", X(31,1004), XX1_MASK, PPCVSX3, PPCNONE, {XS6, RA0, RB}},
++
+ {"trechkpt.", XRC(31,1006,1), XRTRARB_MASK,PPCHTM, PPCNONE, {0}},
+
+ {"tlbli", X(31,1010), XRTRA_MASK, PPC, TITAN, {RB}},
+@@ -5947,6 +6353,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"psq_l", OP(56), OP_MASK, PPCPS, PPCNONE, {FRT,PSD,RA,PSW,PSQ}},
+ {"lfq", OP(56), OP_MASK, POWER2, PPCNONE, {FRT, D, RA0}},
+
++{"lxsd", DSO(57,2), DS_MASK, PPCVSX3, PPCNONE, {VD, DS, RA0}},
++{"lxssp", DSO(57,3), DS_MASK, PPCVSX3, PPCNONE, {VD, DS, RA0}},
+ {"lfdp", OP(57), OP_MASK, POWER6, POWER7, {FRTp, DS, RA0}},
+ {"psq_lu", OP(57), OP_MASK, PPCPS, PPCNONE, {FRT,PSD,RA,PSW,PSQ}},
+ {"lfqu", OP(57), OP_MASK, POWER2, PPCNONE, {FRT, D, RA0}},
+@@ -6046,6 +6454,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"dcmpu", X(59,642), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}},
+
+ {"dtstsf", X(59,674), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}},
++{"dtstsfi", X(59,675), X_MASK|1<<22,POWER9, PPCNONE, {BF, UIM6, FRB}},
+
+ {"drsp", XRC(59,770,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
+ {"drsp.", XRC(59,770,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
+@@ -6068,6 +6477,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"xsaddsp", XX3(60,0), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}},
+ {"xsmaddasp", XX3(60,1), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}},
+ {"xxsldwi", XX3(60,2), XX3SHW_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6, SHW}},
++{"xscmpeqdp", XX3(60,3), XX3_MASK, PPCVSX3, PPCNONE, {XT6, XA6, XB6}},
++{"xsrsqrtesp", XX2(60,10), XX2_MASK, PPCVSX2, PPCNONE, {XT6, XB6}},
++{"xssqrtsp", XX2(60,11), XX2_MASK, PPCVSX2, PPCNONE, {XT6, XB6}},
+ {"xxsel", XX4(60,3), XX4_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6, XC6}},
+ {"xssubsp", XX3(60,8), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}},
+ {"xsmaddmsp", XX3(60,9), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}},
+@@ -6076,163 +6488,203 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"xxswapd", XX3(60,10)|(2<<8), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6S}},
+ {"xxmrgld", XX3(60,10)|(3<<8), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+ {"xxpermdi", XX3(60,10), XX3DM_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6, DM}},
+-{"xsrsqrtesp", XX2(60,10), XX2_MASK, PPCVSX2, PPCNONE, {XT6, XB6}},
+-{"xssqrtsp", XX2(60,11), XX2_MASK, PPCVSX2, PPCNONE, {XT6, XB6}},
++{"xscmpgtdp", XX3(60,11), XX3_MASK, PPCVSX3, PPCNONE, {XT6, XA6, XB6}},
++{"xsresp", XX2(60,26), XX2_MASK, PPCVSX2, PPCNONE, {XT6, XB6}},
+ {"xsmulsp", XX3(60,16), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}},
+ {"xsmsubasp", XX3(60,17), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}},
+ {"xxmrghw", XX3(60,18), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
++{"xscmpgedp", XX3(60,19), XX3_MASK, PPCVSX3, PPCNONE, {XT6, XA6, XB6}},
+ {"xsdivsp", XX3(60,24), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}},
+ {"xsmsubmsp", XX3(60,25), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}},
+-{"xsresp", XX2(60,26), XX2_MASK, PPCVSX2, PPCNONE, {XT6, XB6}},
++{"xxperm", XX3(60,26), XX3_MASK, PPCVSX3, PPCNONE, {XT6, XA6, XB6}},
++{"xscmpnedp", XX3(60,27), XX3_MASK, PPCVSX3, PPCNONE, {XT6, XA6, XB6}},
+ {"xsadddp", XX3(60,32), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+ {"xsmaddadp", XX3(60,33), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+ {"xscmpudp", XX3(60,35), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}},
++{"xscvdpuxws", XX2(60,72), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
++{"xsrdpi", XX2(60,73), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
++{"xsrsqrtedp", XX2(60,74), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
++{"xssqrtdp", XX2(60,75), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+ {"xssubdp", XX3(60,40), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+ {"xsmaddmdp", XX3(60,41), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+ {"xscmpodp", XX3(60,43), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}},
++{"xscvdpsxws", XX2(60,88), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
++{"xsrdpiz", XX2(60,89), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
++{"xsredp", XX2(60,90), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+ {"xsmuldp", XX3(60,48), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+ {"xsmsubadp", XX3(60,49), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+ {"xxmrglw", XX3(60,50), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
++{"xsrdpip", XX2(60,105), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
++{"xstsqrtdp", XX2(60,106), XX2BF_MASK, PPCVSX, PPCNONE, {BF, XB6}},
++{"xsrdpic", XX2(60,107), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+ {"xsdivdp", XX3(60,56), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+ {"xsmsubmdp", XX3(60,57), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
++{"xxpermr", XX3(60,58), XX3_MASK, PPCVSX3, PPCNONE, {XT6, XA6, XB6}},
++{"xscmpexpdp", XX3(60,59), XX3BF_MASK, PPCVSX3, PPCNONE, {BF, XA6, XB6}},
++{"xsrdpim", XX2(60,121), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+ {"xstdivdp", XX3(60,61), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}},
+ {"xvaddsp", XX3(60,64), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+ {"xvmaddasp", XX3(60,65), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+ {"xvcmpeqsp", XX3RC(60,67,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+ {"xvcmpeqsp.", XX3RC(60,67,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
++{"xvcvspuxws", XX2(60,136), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
++{"xvrspi", XX2(60,137), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
++{"xvrsqrtesp", XX2(60,138), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
++{"xvsqrtsp", XX2(60,139), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+ {"xvsubsp", XX3(60,72), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xscvdpuxws", XX2(60,72), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+ {"xvmaddmsp", XX3(60,73), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xsrdpi", XX2(60,73), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xsrsqrtedp", XX2(60,74), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xssqrtdp", XX2(60,75), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+ {"xvcmpgtsp", XX3RC(60,75,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+ {"xvcmpgtsp.", XX3RC(60,75,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
++{"xvcvspsxws", XX2(60,152), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
++{"xvrspiz", XX2(60,153), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
++{"xvresp", XX2(60,154), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+ {"xvmulsp", XX3(60,80), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+ {"xvmsubasp", XX3(60,81), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
++{"xxspltw", XX2(60,164), XX2UIM_MASK, PPCVSX, PPCNONE, {XT6, XB6, UIM}},
++{"xxextractuw", XX2(60,165), XX2UIM4_MASK,PPCVSX3, PPCNONE, {XT6, XB6, UIMM4}},
+ {"xvcmpgesp", XX3RC(60,83,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+ {"xvcmpgesp.", XX3RC(60,83,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
++{"xvcvuxwsp", XX2(60,168), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
++{"xvrspip", XX2(60,169), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
++{"xvtsqrtsp", XX2(60,170), XX2BF_MASK, PPCVSX, PPCNONE, {BF, XB6}},
++{"xvrspic", XX2(60,171), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+ {"xvdivsp", XX3(60,88), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xscvdpsxws", XX2(60,88), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+ {"xvmsubmsp", XX3(60,89), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xsrdpiz", XX2(60,89), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xsredp", XX2(60,90), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
++{"xxspltib", X(60,360), XX1_MASK|3<<19, PPCVSX3,PPCNONE, {XT6, IMM8}},
++{"xxinsertw", XX2(60,181), XX2UIM4_MASK,PPCVSX3, PPCNONE, {XT6, XB6, UIMM4}},
++{"xvcmpnesp", XX3RC(60,91,0), XX3_MASK, PPCVSX3, PPCNONE, {XT6, XA6, XB6}},
++{"xvcmpnesp.", XX3RC(60,91,1), XX3_MASK, PPCVSX3, PPCNONE, {XT6, XA6, XB6}},
++{"xvcvsxwsp", XX2(60,184), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
++{"xvrspim", XX2(60,185), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+ {"xvtdivsp", XX3(60,93), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}},
+ {"xvadddp", XX3(60,96), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+ {"xvmaddadp", XX3(60,97), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+ {"xvcmpeqdp", XX3RC(60,99,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+ {"xvcmpeqdp.", XX3RC(60,99,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
++{"xvcvdpuxws", XX2(60,200), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
++{"xvrdpi", XX2(60,201), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
++{"xvrsqrtedp", XX2(60,202), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
++{"xvsqrtdp", XX2(60,203), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+ {"xvsubdp", XX3(60,104), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+ {"xvmaddmdp", XX3(60,105), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xsrdpip", XX2(60,105), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xstsqrtdp", XX2(60,106), XX2BF_MASK, PPCVSX, PPCNONE, {BF, XB6}},
+-{"xsrdpic", XX2(60,107), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+ {"xvcmpgtdp", XX3RC(60,107,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+ {"xvcmpgtdp.", XX3RC(60,107,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
++{"xvcvdpsxws", XX2(60,216), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
++{"xvrdpiz", XX2(60,217), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
++{"xvredp", XX2(60,218), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+ {"xvmuldp", XX3(60,112), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+ {"xvmsubadp", XX3(60,113), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+ {"xvcmpgedp", XX3RC(60,115,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+ {"xvcmpgedp.", XX3RC(60,115,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
++{"xvcvuxwdp", XX2(60,232), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
++{"xvrdpip", XX2(60,233), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
++{"xvtsqrtdp", XX2(60,234), XX2BF_MASK, PPCVSX, PPCNONE, {BF, XB6}},
++{"xvrdpic", XX2(60,235), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+ {"xvdivdp", XX3(60,120), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+ {"xvmsubmdp", XX3(60,121), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xsrdpim", XX2(60,121), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
++{"xvcmpnedp", XX3RC(60,123,0), XX3_MASK, PPCVSX3, PPCNONE, {XT6, XA6, XB6}},
++{"xvcmpnedp.", XX3RC(60,123,1), XX3_MASK, PPCVSX3, PPCNONE, {XT6, XA6, XB6}},
++{"xvcvsxwdp", XX2(60,248), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
++{"xvrdpim", XX2(60,249), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+ {"xvtdivdp", XX3(60,125), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}},
++{"xsmaxcdp", XX3(60,128), XX3_MASK, PPCVSX3, PPCNONE, {XT6, XA6, XB6}},
+ {"xsnmaddasp", XX3(60,129), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}},
+ {"xxland", XX3(60,130), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvcvspuxws", XX2(60,136), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
++{"xscvdpsp", XX2(60,265), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
++{"xscvdpspn", XX2(60,267), XX2_MASK, PPCVSX2, PPCNONE, {XT6, XB6}},
++{"xsmincdp", XX3(60,136), XX3_MASK, PPCVSX3, PPCNONE, {XT6, XA6, XB6}},
+ {"xsnmaddmsp", XX3(60,137), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}},
+-{"xvrspi", XX2(60,137), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+ {"xxlandc", XX3(60,138), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvrsqrtesp", XX2(60,138), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xvsqrtsp", XX2(60,139), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
++{"xsrsp", XX2(60,281), XX2_MASK, PPCVSX2, PPCNONE, {XT6, XB6}},
++{"xsmaxjdp", XX3(60,144), XX3_MASK, PPCVSX3, PPCNONE, {XT6, XA6, XB6}},
+ {"xsnmsubasp", XX3(60,145), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}},
+ {"xxlor", XX3(60,146), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvcvspsxws", XX2(60,152), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
++{"xscvuxdsp", XX2(60,296), XX2_MASK, PPCVSX2, PPCNONE, {XT6, XB6}},
++{"xststdcsp", XX2(60,298), XX2BFD_MASK, PPCVSX3, PPCNONE, {BF, XB6, DCMX}},
++{"xsminjdp", XX3(60,152), XX3_MASK, PPCVSX3, PPCNONE, {XT6, XA6, XB6}},
+ {"xsnmsubmsp", XX3(60,153), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}},
+-{"xvrspiz", XX2(60,153), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+ {"xxlxor", XX3(60,154), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvresp", XX2(60,154), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
++{"xscvsxdsp", XX2(60,312), XX2_MASK, PPCVSX2, PPCNONE, {XT6, XB6}},
+ {"xsmaxdp", XX3(60,160), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+ {"xsnmaddadp", XX3(60,161), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+ {"xxlnor", XX3(60,162), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xxspltw", XX2(60,164), XX2UIM_MASK, PPCVSX, PPCNONE, {XT6, XB6, UIM}},
++{"xscvdpuxds", XX2(60,328), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
++{"xscvspdp", XX2(60,329), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
++{"xscvspdpn", XX2(60,331), XX2_MASK, PPCVSX2, PPCNONE, {XT6, XB6}},
+ {"xsmindp", XX3(60,168), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvcvuxwsp", XX2(60,168), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+ {"xsnmaddmdp", XX3(60,169), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvrspip", XX2(60,169), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xvtsqrtsp", XX2(60,170), XX2BF_MASK, PPCVSX, PPCNONE, {BF, XB6}},
+ {"xxlorc", XX3(60,170), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}},
+-{"xvrspic", XX2(60,171), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
++{"xscvdpsxds", XX2(60,344), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
++{"xsabsdp", XX2(60,345), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
++{"xsxexpdp", XX2VA(60,347,0),XX2_MASK|1, PPCVSX3, PPCNONE, {RT, XB6}},
++{"xsxsigdp", XX2VA(60,347,1),XX2_MASK|1, PPCVSX3, PPCNONE, {RT, XB6}},
++{"xscvhpdp", XX2VA(60,347,16),XX2_MASK, PPCVSX3, PPCNONE, {XT6, XB6}},
++{"xscvdphp", XX2VA(60,347,17),XX2_MASK, PPCVSX3, PPCNONE, {XT6, XB6}},
+ {"xscpsgndp", XX3(60,176), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+ {"xsnmsubadp", XX3(60,177), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+ {"xxlnand", XX3(60,178), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}},
+-{"xvcvsxwsp", XX2(60,184), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
++{"xscvuxddp", XX2(60,360), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
++{"xsnabsdp", XX2(60,361), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
++{"xststdcdp", XX2(60,362), XX2BFD_MASK, PPCVSX3, PPCNONE, {BF, XB6, DCMX}},
+ {"xsnmsubmdp", XX3(60,185), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvrspim", XX2(60,185), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+ {"xxleqv", XX3(60,186), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}},
++{"xscvsxddp", XX2(60,376), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
++{"xsnegdp", XX2(60,377), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+ {"xvmaxsp", XX3(60,192), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+ {"xvnmaddasp", XX3(60,193), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
++{"xvcvspuxds", XX2(60,392), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
++{"xvcvdpsp", XX2(60,393), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+ {"xvminsp", XX3(60,200), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvcvdpuxws", XX2(60,200), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+ {"xvnmaddmsp", XX3(60,201), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvrdpi", XX2(60,201), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xvrsqrtedp", XX2(60,202), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xvsqrtdp", XX2(60,203), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
++{"xvcvspsxds", XX2(60,408), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
++{"xvabssp", XX2(60,409), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+ {"xvmovsp", XX3(60,208), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6S}},
+ {"xvcpsgnsp", XX3(60,208), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+ {"xvnmsubasp", XX3(60,209), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvcvdpsxws", XX2(60,216), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xvnmsubmsp", XX3(60,217), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvrdpiz", XX2(60,217), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xvredp", XX2(60,218), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xvmaxdp", XX3(60,224), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvnmaddadp", XX3(60,225), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvmindp", XX3(60,232), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvnmaddmdp", XX3(60,233), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvcvuxwdp", XX2(60,232), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xvrdpip", XX2(60,233), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xvtsqrtdp", XX2(60,234), XX2BF_MASK, PPCVSX, PPCNONE, {BF, XB6}},
+-{"xvrdpic", XX2(60,235), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xvmovdp", XX3(60,240), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6S}},
+-{"xvcpsgndp", XX3(60,240), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvnmsubadp", XX3(60,241), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvcvsxwdp", XX2(60,248), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xvnmsubmdp", XX3(60,249), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvrdpim", XX2(60,249), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xscvdpsp", XX2(60,265), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xscvdpspn", XX2(60,267), XX2_MASK, PPCVSX2, PPCNONE, {XT6, XB6}},
+-{"xsrsp", XX2(60,281), XX2_MASK, PPCVSX2, PPCNONE, {XT6, XB6}},
+-{"xscvuxdsp", XX2(60,296), XX2_MASK, PPCVSX2, PPCNONE, {XT6, XB6}},
+-{"xscvsxdsp", XX2(60,312), XX2_MASK, PPCVSX2, PPCNONE, {XT6, XB6}},
+-{"xscvdpuxds", XX2(60,328), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xscvspdp", XX2(60,329), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xscvspdpn", XX2(60,331), XX2_MASK, PPCVSX2, PPCNONE, {XT6, XB6}},
+-{"xscvdpsxds", XX2(60,344), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xsabsdp", XX2(60,345), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xscvuxddp", XX2(60,360), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xsnabsdp", XX2(60,361), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xscvsxddp", XX2(60,376), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xsnegdp", XX2(60,377), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xvcvspuxds", XX2(60,392), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xvcvdpsp", XX2(60,393), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xvcvspsxds", XX2(60,408), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xvabssp", XX2(60,409), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+ {"xvcvuxdsp", XX2(60,424), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+ {"xvnabssp", XX2(60,425), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
++{"xvtstdcsp", XX2(60,426), XX2DCMXS_MASK,PPCVSX3, PPCNONE, {XT6, XB6, DCMXS}},
++{"xviexpsp", XX3(60,216), XX3_MASK, PPCVSX3, PPCNONE, {XT6, XA6, XB6}},
++{"xvnmsubmsp", XX3(60,217), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+ {"xvcvsxdsp", XX2(60,440), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+ {"xvnegsp", XX2(60,441), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
++{"xvmaxdp", XX3(60,224), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
++{"xvnmaddadp", XX3(60,225), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+ {"xvcvdpuxds", XX2(60,456), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+ {"xvcvspdp", XX2(60,457), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
++{"xsiexpdp", X(60,918), XX1_MASK, PPCVSX3, PPCNONE, {XT6, RA, RB}},
++{"xvmindp", XX3(60,232), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
++{"xvnmaddmdp", XX3(60,233), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+ {"xvcvdpsxds", XX2(60,472), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+ {"xvabsdp", XX2(60,473), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
++{"xvxexpdp", XX2VA(60,475,0),XX2_MASK, PPCVSX3, PPCNONE, {XT6, XB6}},
++{"xvxsigdp", XX2VA(60,475,1),XX2_MASK, PPCVSX3, PPCNONE, {XT6, XB6}},
++{"xxbrh", XX2VA(60,475,7),XX2_MASK, PPCVSX3, PPCNONE, {XT6, XB6}},
++{"xvxexpsp", XX2VA(60,475,8),XX2_MASK, PPCVSX3, PPCNONE, {XT6, XB6}},
++{"xvxsigsp", XX2VA(60,475,9),XX2_MASK, PPCVSX3, PPCNONE, {XT6, XB6}},
++{"xxbrw", XX2VA(60,475,15),XX2_MASK, PPCVSX3, PPCNONE, {XT6, XB6}},
++{"xxbrd", XX2VA(60,475,23),XX2_MASK, PPCVSX3, PPCNONE, {XT6, XB6}},
++{"xvcvhpsp", XX2VA(60,475,24),XX2_MASK, PPCVSX3, PPCNONE, {XT6, XB6}},
++{"xvcvsphp", XX2VA(60,475,25),XX2_MASK, PPCVSX3, PPCNONE, {XT6, XB6}},
++{"xxbrq", XX2VA(60,475,31),XX2_MASK, PPCVSX3, PPCNONE, {XT6, XB6}},
++{"xvmovdp", XX3(60,240), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6S}},
++{"xvcpsgndp", XX3(60,240), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
++{"xvnmsubadp", XX3(60,241), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+ {"xvcvuxddp", XX2(60,488), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+ {"xvnabsdp", XX2(60,489), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
++{"xvtstdcdp", XX2(60,490), XX2DCMXS_MASK,PPCVSX3, PPCNONE, {XT6, XB6, DCMXS}},
++{"xviexpdp", XX3(60,248), XX3_MASK, PPCVSX3, PPCNONE, {XT6, XA6, XB6}},
++{"xvnmsubmdp", XX3(60,249), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+ {"xvcvsxddp", XX2(60,504), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+ {"xvnegdp", XX2(60,505), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+
+ {"psq_st", OP(60), OP_MASK, PPCPS, PPCNONE, {FRS,PSD,RA,PSW,PSQ}},
+ {"stfq", OP(60), OP_MASK, POWER2, PPCNONE, {FRS, D, RA}},
+
++{"lxv", DQX(61,1), DQX_MASK, PPCVSX3, PPCNONE, {XTQ6, DQ, RA0}},
++{"stxv", DQX(61,5), DQX_MASK, PPCVSX3, PPCNONE, {XSQ6, DQ, RA0}},
++{"stxsd", DSO(61,2), DS_MASK, PPCVSX3, PPCNONE, {VS, DS, RA0}},
++{"stxssp", DSO(61,3), DS_MASK, PPCVSX3, PPCNONE, {VS, DS, RA0}},
+ {"stfdp", OP(61), OP_MASK, POWER6, POWER7, {FRSp, DS, RA0}},
+ {"psq_stu", OP(61), OP_MASK, PPCPS, PPCNONE, {FRS,PSD,RA,PSW,PSQ}},
+ {"stfqu", OP(61), OP_MASK, POWER2, PPCNONE, {FRS, D, RA}},
+@@ -6241,7 +6693,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"stdu", DSO(62,1), DS_MASK, PPC64, PPCNONE, {RS, DS, RAS}},
+ {"stq", DSO(62,2), DS_MASK, POWER4, PPC476, {RSQ, DS, RA0}},
+
+-{"fcmpu", X(63,0), X_MASK|(3<<21), COM, PPCEFS, {BF, FRA, FRB}},
++{"fcmpu", X(63,0), XBF_MASK, COM, PPCEFS, {BF, FRA, FRB}},
+
+ {"daddq", XRC(63,2,0), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}},
+ {"daddq.", XRC(63,2,1), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}},
+@@ -6249,6 +6701,12 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"dquaq", ZRC(63,3,0), Z2_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp, RMC}},
+ {"dquaq.", ZRC(63,3,1), Z2_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp, RMC}},
+
++{"xsaddqp", XRC(63,4,0), X_MASK, PPCVSX3, PPCNONE, {VD, VA, VB}},
++{"xsaddqpo", XRC(63,4,1), X_MASK, PPCVSX3, PPCNONE, {VD, VA, VB}},
++
++{"xsrqpi", ZRC(63,5,0), Z2_MASK, PPCVSX3, PPCNONE, {R, VD, VB, RMC}},
++{"xsrqpix", ZRC(63,5,1), Z2_MASK, PPCVSX3, PPCNONE, {R, VD, VB, RMC}},
++
+ {"fcpsgn", XRC(63,8,0), X_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FRT, FRA, FRB}},
+ {"fcpsgn.", XRC(63,8,1), X_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FRT, FRA, FRB}},
+
+@@ -6321,7 +6779,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"fnmadd.", A(63,31,1), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}},
+ {"fnma.", A(63,31,1), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
+
+-{"fcmpo", X(63,32), X_MASK|(3<<21), COM, PPCEFS, {BF, FRA, FRB}},
++{"fcmpo", X(63,32), XBF_MASK, COM, PPCEFS, {BF, FRA, FRB}},
+
+ {"dmulq", XRC(63,34,0), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}},
+ {"dmulq.", XRC(63,34,1), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}},
+@@ -6329,6 +6787,11 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"drrndq", ZRC(63,35,0), Z2_MASK, POWER6, PPCNONE, {FRTp, FRA, FRBp, RMC}},
+ {"drrndq.", ZRC(63,35,1), Z2_MASK, POWER6, PPCNONE, {FRTp, FRA, FRBp, RMC}},
+
++{"xsmulqp", XRC(63,36,0), X_MASK, PPCVSX3, PPCNONE, {VD, VA, VB}},
++{"xsmulqpo", XRC(63,36,1), X_MASK, PPCVSX3, PPCNONE, {VD, VA, VB}},
++
++{"xsrqpxp", Z(63,37), Z2_MASK, PPCVSX3, PPCNONE, {R, VD, VB, RMC}},
++
+ {"mtfsb1", XRC(63,38,0), XRARB_MASK, COM, PPCNONE, {BT}},
+ {"mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, PPCNONE, {BT}},
+
+@@ -6355,10 +6818,14 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"drintxq", ZRC(63,99,0), Z2_MASK, POWER6, PPCNONE, {R, FRTp, FRBp, RMC}},
+ {"drintxq.", ZRC(63,99,1), Z2_MASK, POWER6, PPCNONE, {R, FRTp, FRBp, RMC}},
+
+-{"ftdiv", X(63,128), X_MASK|(3<<21), POWER7, PPCNONE, {BF, FRA, FRB}},
++{"xscpsgnqp", X(63,100), X_MASK, PPCVSX3, PPCNONE, {VD, VA, VB}},
++
++{"ftdiv", X(63,128), XBF_MASK, POWER7, PPCNONE, {BF, FRA, FRB}},
+
+ {"dcmpoq", X(63,130), X_MASK, POWER6, PPCNONE, {BF, FRAp, FRBp}},
+
++{"xscmpoqp", X(63,132), XBF_MASK, PPCVSX3, PPCNONE, {BF, VA, VB}},
++
+ {"mtfsfi", XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCNONE, {BFF, U, W}},
+ {"mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476, {BFF, U}},
+ {"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCNONE, {BFF, U, W}},
+@@ -6372,9 +6839,12 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"fctiwuz", XRC(63,143,0), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
+ {"fctiwuz.", XRC(63,143,1), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
+
+-{"ftsqrt", X(63,160), X_MASK|(3<<21|FRA_MASK), POWER7, PPCNONE, {BF, FRB}},
++{"ftsqrt", X(63,160), XBF_MASK|FRA_MASK, POWER7, PPCNONE, {BF, FRB}},
+
+ {"dtstexq", X(63,162), X_MASK, POWER6, PPCNONE, {BF, FRAp, FRBp}},
++
++{"xscmpexpqp", X(63,164), XBF_MASK, PPCVSX3, PPCNONE, {BF, VA, VB}},
++
+ {"dtstdcq", Z(63,194), Z_MASK, POWER6, PPCNONE, {BF, FRAp, DCM}},
+ {"dtstdgq", Z(63,226), Z_MASK, POWER6, PPCNONE, {BF, FRAp, DGM}},
+
+@@ -6396,27 +6866,53 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"dxexq", XRC(63,354,0), X_MASK, POWER6, PPCNONE, {FRT, FRBp}},
+ {"dxexq.", XRC(63,354,1), X_MASK, POWER6, PPCNONE, {FRT, FRBp}},
+
++{"xsmaddqp", XRC(63,388,0), X_MASK, PPCVSX3, PPCNONE, {VD, VA, VB}},
++{"xsmaddqpo", XRC(63,388,1), X_MASK, PPCVSX3, PPCNONE, {VD, VA, VB}},
++
+ {"frin", XRC(63,392,0), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}},
+ {"frin.", XRC(63,392,1), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}},
++
++{"xsmsubqp", XRC(63,420,0), X_MASK, PPCVSX3, PPCNONE, {VD, VA, VB}},
++{"xsmsubqpo", XRC(63,420,1), X_MASK, PPCVSX3, PPCNONE, {VD, VA, VB}},
++
+ {"friz", XRC(63,424,0), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}},
+ {"friz.", XRC(63,424,1), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}},
++
++{"xsnmaddqp", XRC(63,452,0), X_MASK, PPCVSX3, PPCNONE, {VD, VA, VB}},
++{"xsnmaddqpo", XRC(63,452,1), X_MASK, PPCVSX3, PPCNONE, {VD, VA, VB}},
++
+ {"frip", XRC(63,456,0), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}},
+ {"frip.", XRC(63,456,1), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}},
++
++{"xsnmsubqp", XRC(63,484,0), X_MASK, PPCVSX3, PPCNONE, {VD, VA, VB}},
++{"xsnmsubqpo", XRC(63,484,1), X_MASK, PPCVSX3, PPCNONE, {VD, VA, VB}},
++
+ {"frim", XRC(63,488,0), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}},
+ {"frim.", XRC(63,488,1), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}},
+
+ {"dsubq", XRC(63,514,0), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}},
+ {"dsubq.", XRC(63,514,1), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}},
+
++{"xssubqp", XRC(63,516,0), X_MASK, PPCVSX3, PPCNONE, {VD, VA, VB}},
++{"xssubqpo", XRC(63,516,1), X_MASK, PPCVSX3, PPCNONE, {VD, VA, VB}},
++
+ {"ddivq", XRC(63,546,0), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}},
+ {"ddivq.", XRC(63,546,1), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}},
+
++{"xsdivqp", XRC(63,548,0), X_MASK, PPCVSX3, PPCNONE, {VD, VA, VB}},
++{"xsdivqpo", XRC(63,548,1), X_MASK, PPCVSX3, PPCNONE, {VD, VA, VB}},
++
+ {"mffs", XRC(63,583,0), XRARB_MASK, COM, PPCEFS, {FRT}},
+ {"mffs.", XRC(63,583,1), XRARB_MASK, COM, PPCEFS, {FRT}},
+
+ {"dcmpuq", X(63,642), X_MASK, POWER6, PPCNONE, {BF, FRAp, FRBp}},
+
++{"xscmpuqp", X(63,644), XBF_MASK, PPCVSX3, PPCNONE, {BF, VA, VB}},
++
+ {"dtstsfq", X(63,674), X_MASK, POWER6, PPCNONE, {BF, FRA, FRBp}},
++{"dtstsfiq", X(63,675), X_MASK|1<<22,POWER9, PPCNONE, {BF, UIM6, FRBp}},
++
++{"xststdcqp", X(63,708), X_MASK, PPCVSX3, PPCNONE, {BF, VB, DCMX}},
+
+ {"mtfsf", XFL(63,711,0), XFL_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FLM, FRB, XFL_L, W}},
+ {"mtfsf", XFL(63,711,0), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS, {FLM, FRB}},
+@@ -6429,6 +6925,14 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"dcffixq", XRC(63,802,0), X_MASK, POWER6, PPCNONE, {FRTp, FRB}},
+ {"dcffixq.", XRC(63,802,1), X_MASK, POWER6, PPCNONE, {FRTp, FRB}},
+
++{"xsabsqp", XVA(63,804,0), XVA_MASK, PPCVSX3, PPCNONE, {VD, VB}},
++{"xsxexpqp", XVA(63,804,2), XVA_MASK, PPCVSX3, PPCNONE, {VD, VB}},
++{"xsnabsqp", XVA(63,804,8), XVA_MASK, PPCVSX3, PPCNONE, {VD, VB}},
++{"xsnegqp", XVA(63,804,16), XVA_MASK, PPCVSX3, PPCNONE, {VD, VB}},
++{"xsxsigqp", XVA(63,804,18), XVA_MASK, PPCVSX3, PPCNONE, {VD, VB}},
++{"xssqrtqp", XVARC(63,804,27,0), XVA_MASK, PPCVSX3, PPCNONE, {VD, VB}},
++{"xssqrtqpo", XVARC(63,804,27,1), XVA_MASK, PPCVSX3, PPCNONE, {VD, VB}},
++
+ {"fctid", XRC(63,814,0), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}},
+ {"fctid", XRC(63,814,0), XRA_MASK, PPC476, PPCNONE, {FRT, FRB}},
+ {"fctid.", XRC(63,814,1), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}},
+@@ -6442,6 +6946,16 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"denbcdq", XRC(63,834,0), X_MASK, POWER6, PPCNONE, {S, FRTp, FRBp}},
+ {"denbcdq.", XRC(63,834,1), X_MASK, POWER6, PPCNONE, {S, FRTp, FRBp}},
+
++{"xscvqpuwz", XVA(63,836,1), XVA_MASK, PPCVSX3, PPCNONE, {VD, VB}},
++{"xscvudqp", XVA(63,836,2), XVA_MASK, PPCVSX3, PPCNONE, {VD, VB}},
++{"xscvqpswz", XVA(63,836,9), XVA_MASK, PPCVSX3, PPCNONE, {VD, VB}},
++{"xscvsdqp", XVA(63,836,10), XVA_MASK, PPCVSX3, PPCNONE, {VD, VB}},
++{"xscvqpudz", XVA(63,836,17), XVA_MASK, PPCVSX3, PPCNONE, {VD, VB}},
++{"xscvqpdp", XVARC(63,836,20,0), XVA_MASK, PPCVSX3, PPCNONE, {VD, VB}},
++{"xscvqpdpo", XVARC(63,836,20,1), XVA_MASK, PPCVSX3, PPCNONE, {VD, VB}},
++{"xscvdpqp", XVA(63,836,22), XVA_MASK, PPCVSX3, PPCNONE, {VD, VB}},
++{"xscvqpsdz", XVA(63,836,25), XVA_MASK, PPCVSX3, PPCNONE, {VD, VB}},
++
+ {"fmrgow", X(63,838), X_MASK, PPCVSX2, PPCNONE, {FRT, FRA, FRB}},
+
+ {"fcfid", XRC(63,846,0), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}},
+@@ -6452,6 +6966,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"diexq", XRC(63,866,0), X_MASK, POWER6, PPCNONE, {FRTp, FRA, FRBp}},
+ {"diexq.", XRC(63,866,1), X_MASK, POWER6, PPCNONE, {FRTp, FRA, FRBp}},
+
++{"xsiexpqp", X(63,868), X_MASK, PPCVSX3, PPCNONE, {VD, VA, VB}},
++
+ {"fctidu", XRC(63,942,0), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
+ {"fctidu.", XRC(63,942,1), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
+
diff --git a/SOURCES/gdb-rhbz1320945-power9-25of38.patch b/SOURCES/gdb-rhbz1320945-power9-25of38.patch
new file mode 100644
index 0000000..04901ba
--- /dev/null
+++ b/SOURCES/gdb-rhbz1320945-power9-25of38.patch
@@ -0,0 +1,80 @@
+commit dd2887fc3de48f6261d34208a0132122f05d7ef4
+Author: Alan Modra <amodra@gmail.com>
+Date: Mon Dec 7 13:14:05 2015 +1030
+
+ Reorder some power9 insns
+
+ The idea being to put instructions that have the same encoding adjacent
+ to each other.
+
+ * opcodes/ppc-opc.c (powerpc_opcodes): Sort power9 insns by
+ major opcode/xop.
+
+### a/opcodes/ChangeLog
+### b/opcodes/ChangeLog
+## -1,3 +1,8 @@
++2015-12-07 Alan Modra <amodra@gmail.com>
++
++ * opcodes/ppc-opc.c (powerpc_opcodes): Sort power9 insns by
++ major opcode/xop.
++
+ 2015-12-04 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc-dis.c (special_flag_p): Match full mnemonic.
+--- a/opcodes/ppc-opc.c
++++ b/opcodes/ppc-opc.c
+@@ -3152,34 +3152,34 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"ps_add.", A (4, 21,1), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
+ {"vperm", VXA(4, 43), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}},
+ {"vsldoi", VXA(4, 44), VXASHB_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, SHB}},
+-{"ps_sel", A (4, 23,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
+ {"vpermxor", VXA(4, 45), VXA_MASK, PPCVEC2, PPCNONE, {VD, VA, VB, VC}},
++{"ps_sel", A (4, 23,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
+ {"vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VC, VB}},
+ {"ps_sel.", A (4, 23,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
+ {"vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VC, VB}},
+-{"maddhd", VXA(4, 48), VXA_MASK, POWER9, PPCNONE, {RT, RA, RB, RC}},
+-{"maddhdu", VXA(4, 49), VXA_MASK, POWER9, PPCNONE, {RT, RA, RB, RC}},
+-{"maddld", VXA(4, 51), VXA_MASK, POWER9, PPCNONE, {RT, RA, RB, RC}},
+ {"ps_res", A (4, 24,0), AFRAFRC_MASK, PPCPS, PPCNONE, {FRT, FRB}},
++{"maddhd", VXA(4, 48), VXA_MASK, POWER9, PPCNONE, {RT, RA, RB, RC}},
+ {"ps_res.", A (4, 24,1), AFRAFRC_MASK, PPCPS, PPCNONE, {FRT, FRB}},
+-{"ps_mul", A (4, 25,0), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}},
++{"maddhdu", VXA(4, 49), VXA_MASK, POWER9, PPCNONE, {RT, RA, RB, RC}},
++{"ps_mul", A (4, 25,0), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}},
+ {"ps_mul.", A (4, 25,1), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}},
++{"maddld", VXA(4, 51), VXA_MASK, POWER9, PPCNONE, {RT, RA, RB, RC}},
+ {"ps_rsqrte", A (4, 26,0), AFRAFRC_MASK, PPCPS, PPCNONE, {FRT, FRB}},
+ {"ps_rsqrte.", A (4, 26,1), AFRAFRC_MASK, PPCPS, PPCNONE, {FRT, FRB}},
+ {"ps_msub", A (4, 28,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
+ {"ps_msub.", A (4, 28,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
+ {"ps_madd", A (4, 29,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
+ {"ps_madd.", A (4, 29,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
+-{"ps_nmsub", A (4, 30,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
+-{"ps_nmsub.", A (4, 30,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
+-{"ps_nmadd", A (4, 31,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
+-{"ps_nmadd.", A (4, 31,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
+-{"ps_cmpo0", X (4, 32), XBF_MASK, PPCPS, PPCNONE, {BF, FRA, FRB}},
+ {"vpermr", VXA(4, 59), VXA_MASK, PPCVEC3, PPCNONE, {VD, VA, VB, VC}},
++{"ps_nmsub", A (4, 30,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
+ {"vaddeuqm", VXA(4, 60), VXA_MASK, PPCVEC2, PPCNONE, {VD, VA, VB, VC}},
++{"ps_nmsub.", A (4, 30,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
+ {"vaddecuq", VXA(4, 61), VXA_MASK, PPCVEC2, PPCNONE, {VD, VA, VB, VC}},
++{"ps_nmadd", A (4, 31,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
+ {"vsubeuqm", VXA(4, 62), VXA_MASK, PPCVEC2, PPCNONE, {VD, VA, VB, VC}},
++{"ps_nmadd.", A (4, 31,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
+ {"vsubecuq", VXA(4, 63), VXA_MASK, PPCVEC2, PPCNONE, {VD, VA, VB, VC}},
++{"ps_cmpo0", X (4, 32), XBF_MASK, PPCPS, PPCNONE, {BF, FRA, FRB}},
+ {"vadduhm", VX (4, 64), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+ {"vmul10ecuq", VX (4, 65), VX_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}},
+ {"vmaxuh", VX (4, 66), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+@@ -3229,8 +3229,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"nmachhws.", XO (4, 110,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+ {"vadduqm", VX (4, 256), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+ {"vmaxsb", VX (4, 258), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vcmpnezb", VXR(4, 263,0), VXR_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}},
+ {"vslb", VX (4, 260), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
++{"vcmpnezb", VXR(4, 263,0), VXR_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}},
+ {"vmulosb", VX (4, 264), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+ {"vrefp", VX (4, 266), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}},
+ {"vmrglb", VX (4, 268), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
diff --git a/SOURCES/gdb-rhbz1320945-power9-26of38.patch b/SOURCES/gdb-rhbz1320945-power9-26of38.patch
new file mode 100644
index 0000000..bc240ce
--- /dev/null
+++ b/SOURCES/gdb-rhbz1320945-power9-26of38.patch
@@ -0,0 +1,45 @@
+commit b817670b52b7414d592cbfd96fd77cf725a33413
+Author: Alan Modra <amodra@gmail.com>
+Date: Sat Dec 12 17:26:33 2015 +1030
+
+ Enable 2 operand form of powerpc mfcr with -many
+
+ This is a workaround for a gcc bug.
+
+ PR 19359
+ * ppc-opc.c (insert_fxm): Remove "ignored" from error message.
+ (powerpc_opcodes): Remove single-operand mfcr.
+
+### a/opcodes/ChangeLog
+### b/opcodes/ChangeLog
+## -1,3 +1,9 @@
++2015-12-12 Alan Modra <amodra@gmail.com>
++
++ PR 19359
++ * ppc-opc.c (insert_fxm): Remove "ignored" from error message.
++ (powerpc_opcodes): Remove single-operand mfcr.
++
+ 2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64-asm.c (aarch64_ins_hint): New.
+--- a/opcodes/ppc-opc.c
++++ b/opcodes/ppc-opc.c
+@@ -1434,7 +1434,7 @@ insert_fxm (unsigned long insn,
+ /* A value of -1 means we used the one operand form of
+ mfcr which is valid. */
+ if (value != -1)
+- *errmsg = _("ignoring invalid mfcr mask");
++ *errmsg = _("invalid mfcr mask");
+ value = 0;
+ }
+
+@@ -4742,8 +4742,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"tlbilxva", XTO(31,18,3), XTO_MASK, E500MC|PPCA2, PPCNONE, {RA0, RB}},
+ {"tlbilx", X(31,18), X_MASK, E500MC|PPCA2, PPCNONE, {T, RA0, RB}},
+
+-{"mfcr", XFXM(31,19,0,0), XFXFXM_MASK, POWER4, PPCNONE, {RT, FXM4}},
+-{"mfcr", XFXM(31,19,0,0), XRARB_MASK, COM|PPCVLE, POWER4, {RT}},
++{"mfcr", XFXM(31,19,0,0), XFXFXM_MASK, COM|PPCVLE, PPCNONE, {RT, FXM4}},
+ {"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM|PPCVLE, PPCNONE, {RT, FXM}},
+
+ {"lwarx", X(31,20), XEH_MASK, PPC|PPCVLE, PPCNONE, {RT, RA0, RB, EH}},
diff --git a/SOURCES/gdb-rhbz1320945-power9-27of38.patch b/SOURCES/gdb-rhbz1320945-power9-27of38.patch
new file mode 100644
index 0000000..5d540f6
--- /dev/null
+++ b/SOURCES/gdb-rhbz1320945-power9-27of38.patch
@@ -0,0 +1,62 @@
+commit afa8d4054b8e0b1384f2d07f1c15163c0699d660
+Author: Peter Bergner <bergner@vnet.ibm.com>
+Date: Mon Jan 11 11:54:58 2016 -0600
+
+ Delete opcodes that have been removed from ISA 3.0.
+
+ opcodes/
+ * ppc-opc.c <xscmpnedp>: Delete.
+ <xvcmpnedp>: Likewise.
+ <xvcmpnedp.>: Likewise.
+ <xvcmpnesp>: Likewise.
+ <xvcmpnesp.>: Likewise.
+
+ gas/
+ * testsuite/gas/ppc/power9.d <xscmpnedp, xvcmpnedp, xvcmpnedp.,
+ xvcmpnesp, xvcmpnesp.>: Delete tests.
+ * testsuite/gas/ppc/power9.s: Likewise.
+ * testsuite/gas/ppc/vsx3.d: Likewise.
+ * testsuite/gas/ppc/vsx3.s: Likewise.
+
+### a/opcodes/ChangeLog
+### b/opcodes/ChangeLog
+## -1,3 +1,11 @@
++2016-01-11 Peter Bergner <bergner@vnet.ibm.com>
++
++ * ppc-opc.c <xscmpnedp>: Delete.
++ <xvcmpnedp>: Likewise.
++ <xvcmpnedp.>: Likewise.
++ <xvcmpnesp>: Likewise.
++ <xvcmpnesp.>: Likewise.
++
+ 2016-01-08 Andreas Schwab <schwab@linux-m68k.org>
+
+ PR gas/13050
+--- a/opcodes/ppc-opc.c
++++ b/opcodes/ppc-opc.c
+@@ -6496,7 +6496,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"xsdivsp", XX3(60,24), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}},
+ {"xsmsubmsp", XX3(60,25), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}},
+ {"xxperm", XX3(60,26), XX3_MASK, PPCVSX3, PPCNONE, {XT6, XA6, XB6}},
+-{"xscmpnedp", XX3(60,27), XX3_MASK, PPCVSX3, PPCNONE, {XT6, XA6, XB6}},
+ {"xsadddp", XX3(60,32), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+ {"xsmaddadp", XX3(60,33), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+ {"xscmpudp", XX3(60,35), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}},
+@@ -6551,8 +6550,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"xvmsubmsp", XX3(60,89), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+ {"xxspltib", X(60,360), XX1_MASK|3<<19, PPCVSX3,PPCNONE, {XT6, IMM8}},
+ {"xxinsertw", XX2(60,181), XX2UIM4_MASK,PPCVSX3, PPCNONE, {XT6, XB6, UIMM4}},
+-{"xvcmpnesp", XX3RC(60,91,0), XX3_MASK, PPCVSX3, PPCNONE, {XT6, XA6, XB6}},
+-{"xvcmpnesp.", XX3RC(60,91,1), XX3_MASK, PPCVSX3, PPCNONE, {XT6, XA6, XB6}},
+ {"xvcvsxwsp", XX2(60,184), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+ {"xvrspim", XX2(60,185), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+ {"xvtdivsp", XX3(60,93), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}},
+@@ -6581,8 +6578,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"xvrdpic", XX2(60,235), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+ {"xvdivdp", XX3(60,120), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+ {"xvmsubmdp", XX3(60,121), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvcmpnedp", XX3RC(60,123,0), XX3_MASK, PPCVSX3, PPCNONE, {XT6, XA6, XB6}},
+-{"xvcmpnedp.", XX3RC(60,123,1), XX3_MASK, PPCVSX3, PPCNONE, {XT6, XA6, XB6}},
+ {"xvcvsxwdp", XX2(60,248), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+ {"xvrdpim", XX2(60,249), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+ {"xvtdivdp", XX3(60,125), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}},
diff --git a/SOURCES/gdb-rhbz1320945-power9-28of38.patch b/SOURCES/gdb-rhbz1320945-power9-28of38.patch
new file mode 100644
index 0000000..998f66e
--- /dev/null
+++ b/SOURCES/gdb-rhbz1320945-power9-28of38.patch
@@ -0,0 +1,126 @@
+commit e43de63c8fd11a15d7c6c852747c81664c0beb2a
+Author: Alan Modra <amodra@gmail.com>
+Date: Thu May 19 00:10:35 2016 +0930
+
+ Fix powerpc subis range
+
+ * ppc-opc.c: Formatting.
+ (NSISIGNOPT): Define.
+ (powerpc_opcodes <subis>): Use NSISIGNOPT.
+
+### a/opcodes/ChangeLog
+### b/opcodes/ChangeLog
+## -1,3 +1,9 @@
++2016-05-19 Alan Modra <amodra@gmail.com>
++
++ * ppc-opc.c: Formatting.
++ (NSISIGNOPT): Define.
++ (powerpc_opcodes <subis>): Use NSISIGNOPT.
++
+ 2016-05-18 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
+--- a/opcodes/ppc-opc.c
++++ b/opcodes/ppc-opc.c
+@@ -186,25 +186,25 @@ const struct powerpc_operand powerpc_operands[] =
+ This sets the y bit of the BO field appropriately. */
+ #define BDM BDA + 1
+ { 0xfffc, 0, insert_bdm, extract_bdm,
+- PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
++ PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
+
+ /* The BD field in a B form instruction when the - modifier is used
+ and absolute address is used. */
+ #define BDMA BDM + 1
+ { 0xfffc, 0, insert_bdm, extract_bdm,
+- PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
++ PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
+
+ /* The BD field in a B form instruction when the + modifier is used.
+ This sets the y bit of the BO field appropriately. */
+ #define BDP BDMA + 1
+ { 0xfffc, 0, insert_bdp, extract_bdp,
+- PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
++ PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
+
+ /* The BD field in a B form instruction when the + modifier is used
+ and absolute addressing is used. */
+ #define BDPA BDP + 1
+ { 0xfffc, 0, insert_bdp, extract_bdp,
+- PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
++ PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
+
+ /* The BF field in an X or XL form instruction. */
+ #define BF BDPA + 1
+@@ -414,7 +414,8 @@ const struct powerpc_operand powerpc_operands[] =
+
+ /* Power4 version for mfcr. */
+ #define FXM4 FXM + 1
+- { 0xff, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE},
++ { 0xff, 12, insert_fxm, extract_fxm,
++ PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE},
+ /* If the FXM4 operand is ommitted, use the sentinel value -1. */
+ { -1, -1, NULL, NULL, 0},
+
+@@ -493,10 +494,16 @@ const struct powerpc_operand powerpc_operands[] =
+ SI field, only negated. */
+ #define NSI NBI + 1
+ { 0xffff, 0, insert_nsi, extract_nsi,
+- PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
++ PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
++
++ /* The NSI field in a D form instruction when we accept a wide range
++ of positive values. */
++#define NSISIGNOPT NSI + 1
++ { 0xffff, 0, NULL, NULL,
++ PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
+
+ /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
+-#define RA NSI + 1
++#define RA NSISIGNOPT + 1
+ #define RA_MASK (0x1f << 16)
+ { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR },
+
+@@ -601,7 +608,7 @@ const struct powerpc_operand powerpc_operands[] =
+ SCLSCI8 field, only negated. */
+ #define SCLSCI8N SCLSCI8 + 1
+ { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8n, extract_sci8n,
+- PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
++ PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
+
+ /* The SD field of the SD4 form instruction. */
+ #define SE_SD SCLSCI8N + 1
+@@ -690,7 +697,8 @@ const struct powerpc_operand powerpc_operands[] =
+ /* The TBR field in an XFX form instruction. This is like the SPR
+ field, but it is optional. */
+ #define TBR SV + 1
+- { 0x3ff, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE},
++ { 0x3ff, 11, insert_tbr, extract_tbr,
++ PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE},
+ /* If the TBR operand is ommitted, use the value 268. */
+ { -1, 268, NULL, NULL, 0},
+
+@@ -874,12 +882,12 @@ const struct powerpc_operand powerpc_operands[] =
+ /* The VLESIMM field in a D form instruction. */
+ #define VLESIMM URC + 1
+ { 0xffff, PPC_OPSHIFT_INV, insert_vlesi, extract_vlesi,
+- PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
++ PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
+
+ /* The VLENSIMM field in a D form instruction. */
+ #define VLENSIMM VLESIMM + 1
+ { 0xffff, PPC_OPSHIFT_INV, insert_vlensi, extract_vlensi,
+- PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
++ PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
+
+ /* The VLEUIMM field in a D form instruction. */
+ #define VLEUIMM VLENSIMM + 1
+@@ -3878,7 +3886,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"liu", OP(15), DRA_MASK, PWRCOM, PPCNONE, {RT, SISIGNOPT}},
+ {"addis", OP(15), OP_MASK, PPCCOM, PPCNONE, {RT, RA0, SISIGNOPT}},
+ {"cau", OP(15), OP_MASK, PWRCOM, PPCNONE, {RT, RA0, SISIGNOPT}},
+-{"subis", OP(15), OP_MASK, PPCCOM, PPCNONE, {RT, RA0, NSI}},
++{"subis", OP(15), OP_MASK, PPCCOM, PPCNONE, {RT, RA0, NSISIGNOPT}},
+
+ {"bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDM}},
+ {"bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDP}},
diff --git a/SOURCES/gdb-rhbz1320945-power9-29of38.patch b/SOURCES/gdb-rhbz1320945-power9-29of38.patch
new file mode 100644
index 0000000..ed01a8b
--- /dev/null
+++ b/SOURCES/gdb-rhbz1320945-power9-29of38.patch
@@ -0,0 +1,67 @@
+commit 19dfcc89e8d94526f011242041b700ede8834996
+Author: Peter Bergner <bergner@vnet.ibm.com>
+Date: Thu May 26 19:06:51 2016 -0500
+
+ Add support for new POWER ISA 3.0 instructions.
+
+ opcodes/
+
+ * ppc-opc.c (CY): New define. Document it.
+ (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
+
+ gas/
+ * testsuite/gas/ppc/altivec3.d <vmsumudm>: Add test.
+ * testsuite/gas/ppc/altivec3.s: Likewise.
+ * testsuite/gas/ppc/power9.d <addex[.], lwzmx, vmsumudm>: Add tests.
+ * testsuite/gas/ppc/power9.s: Likewise.
+
+### a/opcodes/ChangeLog
+### b/opcodes/ChangeLog
+## -1,3 +1,8 @@
++2016-05-26 Peter Bergner <bergner@vnet.ibm.com>
++
++ * ppc-opc.c (CY): New define. Document it.
++ (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
++
+ 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
+--- a/opcodes/ppc-opc.c
++++ b/opcodes/ppc-opc.c
+@@ -815,7 +815,9 @@ const struct powerpc_operand powerpc_operands[] =
+ #define X_R A_L
+ { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
+
++ /* The RMC or CY field in a Z23 form instruction. */
+ #define RMC A_L + 1
++#define CY RMC
+ { 0x3, 9, NULL, NULL, 0 },
+
+ #define R RMC + 1
+@@ -3145,6 +3147,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}},
+ {"vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}},
+ {"vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}},
++{"vmsumudm", VXA(4, 35), VXA_MASK, PPCVEC3, PPCNONE, {VD, VA, VB, VC}},
+ {"ps_div", A (4, 18,0), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
+ {"vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}},
+ {"ps_div.", A (4, 18,1), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
+@@ -4977,6 +4980,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"stvehx", X(31,167), X_MASK, PPCVEC, PPCNONE, {VS, RA0, RB}},
+ {"sthfcmx", APU(31,167,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
+
++{"addex", ZRC(31,170,0), Z2_MASK, POWER9, PPCNONE, {RT, RA, RB, CY}},
++{"addex.", ZRC(31,170,1), Z2_MASK, POWER9, PPCNONE, {RT, RA, RB, CY}},
++
+ {"msgclrp", XRTRA(31,174,0,0), XRTRA_MASK, POWER8, PPCNONE, {RB}},
+ {"dcbtlse", X(31,174), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}},
+
+@@ -5504,6 +5510,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+
+ {"mtvsrdd", X(31,435), XX1_MASK, PPCVSX3, PPCNONE, {XT6, RA0, RB}},
+
++{"lwzmx", X(31,437), X_MASK, POWER9, PPCNONE, {RT, RA0, RB}},
++
+ {"ecowx", X(31,438), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
+
+ {"sthux", X(31,439), X_MASK, COM|PPCVLE, PPCNONE, {RS, RAS, RB}},
diff --git a/SOURCES/gdb-rhbz1320945-power9-30of38.patch b/SOURCES/gdb-rhbz1320945-power9-30of38.patch
new file mode 100644
index 0000000..0084e98
--- /dev/null
+++ b/SOURCES/gdb-rhbz1320945-power9-30of38.patch
@@ -0,0 +1,72 @@
+commit 026122a670440bc51266f8e013e5c5877c19b54e
+Author: Peter Bergner <bergner@vnet.ibm.com>
+Date: Fri Jun 3 18:38:02 2016 -0500
+
+ Re-add support for lbarx, lharx, stbcx. and sthcx. insns back to the E6500 cpu.
+
+ opcodes/
+ PR binutils/20196
+ * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
+ opcodes for E6500.
+
+ gas/
+ PR binutils/20196
+ * gas/testsuite/gas/ppc/e6500.s <lbarx, lharx, lwarx, ldarx,
+ stbcx., sthcx., stwcx., stdcx.>: Add tests.
+ * gas/testsuite/gas/ppc/e6500.d: Likewise.
+ * gas/testsuite/gas/ppc/power8.s: Likewise.
+ * gas/testsuite/gas/ppc/power8.d: Likewise.
+ * gas/testsuite/gas/ppc/power4.s <lwarx, ldarx, stwcx.,
+ stdcx.>: Add tests.
+ * gas/testsuite/gas/ppc/power4.d: Likewise.
+
+### a/opcodes/ChangeLog
+### b/opcodes/ChangeLog
+## -1,3 +1,9 @@
++2016-06-03 Peter Bergner <bergner@vnet.ibm.com>
++
++ PR binutils/20196
++ * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
++ opcodes for E6500.
++
+ 2016-06-03 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutis/18386
+--- a/opcodes/ppc-opc.c
++++ b/opcodes/ppc-opc.c
+@@ -4824,7 +4824,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"mfvrd", X(31,51)|1, XX1RB_MASK|1, PPCVSX2, PPCNONE, {RA, VS}},
+ {"eratilx", X(31,51), X_MASK, PPCA2, PPCNONE, {ERAT_T, RA, RB}},
+
+-{"lbarx", X(31,52), XEH_MASK, POWER8|PPCVLE, PPCNONE, {RT, RA0, RB, EH}},
++{"lbarx", X(31,52), XEH_MASK, POWER8|E6500|PPCVLE, PPCNONE, {RT, RA0, RB, EH}},
+
+ {"ldux", X(31,53), X_MASK, PPC64|PPCVLE, PPCNONE, {RT, RAL, RB}},
+
+@@ -4904,7 +4904,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"mfvrwz", X(31,115)|1, XX1RB_MASK|1, PPCVSX2, PPCNONE, {RA, VS}},
+ {"mfvsrwz", X(31,115), XX1RB_MASK, PPCVSX2, PPCNONE, {RA, XS6}},
+
+-{"lharx", X(31,116), XEH_MASK, POWER8|PPCVLE, PPCNONE, {RT, RA0, RB, EH}},
++{"lharx", X(31,116), XEH_MASK, POWER8|E6500|PPCVLE, PPCNONE, {RT, RA0, RB, EH}},
+
+ {"clf", X(31,118), XTO_MASK, POWER, PPCNONE, {RA, RB}},
+
+@@ -5954,7 +5954,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"tendall.", XRC(31,686,1)|(1<<25), XRTRARB_MASK, PPCHTM, PPCNONE, {0}},
+ {"tend.", XRC(31,686,1), XRTARARB_MASK, PPCHTM, PPCNONE, {HTM_A}},
+
+-{"stbcx.", XRC(31,694,1), X_MASK, POWER8, PPCNONE, {RS, RA0, RB}},
++{"stbcx.", XRC(31,694,1), X_MASK, POWER8|E6500, PPCNONE, {RS, RA0, RB}},
+
+ {"stfsux", X(31,695), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},
+
+@@ -5986,7 +5986,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"stswi", X(31,725), X_MASK, PPCCOM|PPCVLE, E500|E500MC, {RS, RA0, NB}},
+ {"stsi", X(31,725), X_MASK, PWRCOM, PPCNONE, {RS, RA0, NB}},
+
+-{"sthcx.", XRC(31,726,1), X_MASK, POWER8, PPCNONE, {RS, RA0, RB}},
++{"sthcx.", XRC(31,726,1), X_MASK, POWER8|E6500, PPCNONE, {RS, RA0, RB}},
+
+ {"stfdx", X(31,727), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
+
diff --git a/SOURCES/gdb-rhbz1320945-power9-31of38.patch b/SOURCES/gdb-rhbz1320945-power9-31of38.patch
new file mode 100644
index 0000000..714093c
--- /dev/null
+++ b/SOURCES/gdb-rhbz1320945-power9-31of38.patch
@@ -0,0 +1,8358 @@
+commit 14b57c7c6a53c747a8819fed3da858eae4195a0e
+Author: Alan Modra <amodra@gmail.com>
+Date: Tue Jun 7 22:04:38 2016 +0930
+
+ PowerPC VLE
+
+ VLE is an encoding, not a particular processor architecture, so it
+ isn't really proper to select insns based on PPC_OPCODE_VLE. For
+ example
+ {"evaddw", VX (4, 512), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+ {"vaddubs", VX (4, 512), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+ shows two insns that have the same encoding, both available with VLE.
+ Enabling both with VLE means we can't disassemble the second variant
+ even if -Maltivec is given rather than -Mspe. Also, we don't check
+ user assembly against the processor type as well as we could.
+
+ Another problem is that when using the VLE encoding, insns from the
+ main ppc opcode table are not available, except those using opcode 4
+ and 31. Correcting this revealed two errors in the ld testsuite,
+ use of "nop" and "rfmci" when -mvle.
+
+ This patch fixes those problems in the opcode table, and removes
+ PPCNONE. I find a plain 0 distracts less from other values.
+
+ In addition, I've implemented code to recognize some machine values
+ from the apuinfo note present in ppc32 objects. It's not a complete
+ disambiguation since we're lacking info to detect newer chips, but
+ what we have should help with disassembly.
+
+ include/
+ * elf/ppc.h (APUINFO_SECTION_NAME, APUINFO_LABEL, PPC_APUINFO_ISEL,
+ PPC_APUINFO_PMR, PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK,
+ PPC_APUINFO_SPE, PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK,
+ PPC_APUINFO_VLE: Define.
+ opcodes/
+ * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
+ cpu for "vle" to e500.
+ * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
+ (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
+ (PPCNONE): Delete, substitute throughout.
+ (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
+ except for major opcode 4 and 31.
+ (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
+ bfd/
+ * cpu-powerpc.c (powerpc_compatible): Allow bfd_mach_ppc_vle entry
+ to match other 32-bit archs.
+ * elf32-ppc.c (_bfd_elf_ppc_set_arch): New function.
+ (ppc_elf_object_p): Call it.
+ (ppc_elf_special_sections): Use APUINFO_SECTION_NAME. Fix
+ overlong line.
+ (APUINFO_SECTION_NAME, APUINFO_LABEL): Don't define here.
+ * elf64-ppc.c (ppc64_elf_object_p): Call _bfd_elf_ppc_set_arch.
+ * bfd-in.h (_bfd_elf_ppc_at_tls_transform,
+ _bfd_elf_ppc_at_tprel_transform): Move to..
+ * elf-bfd.h: ..here.
+ (_bfd_elf_ppc_set_arch): Declare.
+ * bfd-in2.h: Regenerate.
+ gas/
+ * config/tc-ppc.c (PPC_APUINFO_ISEL, PPC_APUINFO_PMR,
+ PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK, PPC_APUINFO_SPE,
+ PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK, PPC_APUINFO_VLE): Don't define.
+ (ppc_setup_opcodes): Check vle disables powerpc_opcodes overridden
+ by vle_opcodes, and that vle flag doesn't enable opcodes. Don't
+ add vle_opcodes twice.
+ (ppc_cleanup): Use APUINFO_SECTION_NAME and APUINFO_LABEL.
+ ld/
+ * testsuite/ld-powerpc/apuinfo1.s: Delete nop.
+ * testsuite/ld-powerpc/apuinfo-vle2.s: New.
+ * testsuite/ld-powerpc/powerpc.exp: Use apuinfo-vle2.s.
+
+### a/bfd/ChangeLog
+### b/bfd/ChangeLog
+## -1,3 +1,19 @@
++2016-06-07 Alan Modra <amodra@gmail.com>
++
++ * cpu-powerpc.c (powerpc_compatible): Allow bfd_mach_ppc_vle entry
++ to match other 32-bit archs.
++ * elf32-ppc.c (_bfd_elf_ppc_set_arch): New function.
++ (ppc_elf_object_p): Call it.
++ (ppc_elf_special_sections): Use APUINFO_SECTION_NAME. Fix
++ overlong line.
++ (APUINFO_SECTION_NAME, APUINFO_LABEL): Don't define here.
++ * elf64-ppc.c (ppc64_elf_object_p): Call _bfd_elf_ppc_set_arch.
++ * bfd-in.h (_bfd_elf_ppc_at_tls_transform,
++ _bfd_elf_ppc_at_tprel_transform): Move to..
++ * elf-bfd.h: ..here.
++ (_bfd_elf_ppc_set_arch): Declare.
++ * bfd-in2.h: Regenerate.
++
+ 2016-06-06 H.J. Lu <hongjiu.lu@intel.com>
+
+ * elf64-x86-64.c (elf_x86_64_link_hash_entry): Add tls_get_addr.
+--- a/bfd/bfd-in.h
++++ b/bfd/bfd-in.h
+@@ -951,13 +951,6 @@ extern bfd_boolean elf32_arm_fix_exidx_coverage
+ extern bfd_boolean elf32_tic6x_fix_exidx_coverage
+ (struct bfd_section **, unsigned int, struct bfd_link_info *, bfd_boolean);
+
+-/* PowerPC @tls opcode transform/validate. */
+-extern unsigned int _bfd_elf_ppc_at_tls_transform
+- (unsigned int, unsigned int);
+-/* PowerPC @tprel opcode transform/validate. */
+-extern unsigned int _bfd_elf_ppc_at_tprel_transform
+- (unsigned int, unsigned int);
+-
+ extern void bfd_elf64_aarch64_init_maps
+ (bfd *);
+
+--- a/bfd/bfd-in2.h
++++ b/bfd/bfd-in2.h
+@@ -958,13 +958,6 @@ extern bfd_boolean elf32_arm_fix_exidx_coverage
+ extern bfd_boolean elf32_tic6x_fix_exidx_coverage
+ (struct bfd_section **, unsigned int, struct bfd_link_info *, bfd_boolean);
+
+-/* PowerPC @tls opcode transform/validate. */
+-extern unsigned int _bfd_elf_ppc_at_tls_transform
+- (unsigned int, unsigned int);
+-/* PowerPC @tprel opcode transform/validate. */
+-extern unsigned int _bfd_elf_ppc_at_tprel_transform
+- (unsigned int, unsigned int);
+-
+ extern void bfd_elf64_aarch64_init_maps
+ (bfd *);
+
+--- a/bfd/cpu-powerpc.c
++++ b/bfd/cpu-powerpc.c
+@@ -35,6 +35,10 @@ powerpc_compatible (const bfd_arch_info_type *a,
+ default:
+ return NULL;
+ case bfd_arch_powerpc:
++ if (a->mach == bfd_mach_ppc_vle && b->bits_per_word == 32)
++ return a;
++ if (b->mach == bfd_mach_ppc_vle && a->bits_per_word == 32)
++ return b;
+ return bfd_default_compatible (a, b);
+ case bfd_arch_rs6000:
+ if (b->mach == bfd_mach_rs6k)
+--- a/bfd/elf-bfd.h
++++ b/bfd/elf-bfd.h
+@@ -2368,6 +2368,15 @@ extern bfd_boolean bfd_elf_lookup_section_flags
+ extern Elf_Internal_Phdr * _bfd_elf_find_segment_containing_section
+ (bfd * abfd, asection * section);
+
++/* PowerPC @tls opcode transform/validate. */
++extern unsigned int _bfd_elf_ppc_at_tls_transform
++ (unsigned int, unsigned int);
++/* PowerPC @tprel opcode transform/validate. */
++extern unsigned int _bfd_elf_ppc_at_tprel_transform
++ (unsigned int, unsigned int);
++/* PowerPC elf_object_p tweak. */
++extern bfd_boolean _bfd_elf_ppc_set_arch (bfd *);
++
+ /* Exported interface for writing elf corefile notes. */
+ extern char *elfcore_write_note
+ (bfd *, char *, int *, const char *, int, const void *, int);
+--- a/bfd/elf32-ppc.c
++++ b/bfd/elf32-ppc.c
+@@ -2196,13 +2196,93 @@ ppc_elf_mkobject (bfd *abfd)
+ PPC32_ELF_DATA);
+ }
+
++/* When defaulting arch/mach, decode apuinfo to find a better match. */
++
++bfd_boolean
++_bfd_elf_ppc_set_arch (bfd *abfd)
++{
++ unsigned long mach = 0;
++ asection *s;
++ unsigned char *contents;
++
++ if (abfd->arch_info->bits_per_word == 32
++ && bfd_big_endian (abfd))
++ {
++
++ for (s = abfd->sections; s != NULL; s = s->next)
++ if ((elf_section_data (s)->this_hdr.sh_flags & SHF_PPC_VLE) != 0)
++ break;
++ if (s != NULL)
++ mach = bfd_mach_ppc_vle;
++ }
++
++ if (mach == 0)
++ {
++ s = bfd_get_section_by_name (abfd, APUINFO_SECTION_NAME);
++ if (s != NULL && bfd_malloc_and_get_section (abfd, s, &contents))
++ {
++ unsigned int apuinfo_size = bfd_get_32 (abfd, contents + 4);
++ unsigned int i;
++
++ for (i = 20; i < apuinfo_size + 20 && i + 4 <= s->size; i += 4)
++ {
++ unsigned int val = bfd_get_32 (abfd, contents + i);
++ switch (val >> 16)
++ {
++ case PPC_APUINFO_PMR:
++ case PPC_APUINFO_RFMCI:
++ if (mach == 0)
++ mach = bfd_mach_ppc_titan;
++ break;
++
++ case PPC_APUINFO_ISEL:
++ case PPC_APUINFO_CACHELCK:
++ if (mach == bfd_mach_ppc_titan)
++ mach = bfd_mach_ppc_e500mc;
++ break;
++
++ case PPC_APUINFO_SPE:
++ case PPC_APUINFO_EFS:
++ case PPC_APUINFO_BRLOCK:
++ if (mach != bfd_mach_ppc_vle)
++ mach = bfd_mach_ppc_e500;
++
++ case PPC_APUINFO_VLE:
++ mach = bfd_mach_ppc_vle;
++ break;
++
++ default:
++ mach = -1ul;
++ }
++ }
++ free (contents);
++ }
++ }
++
++ if (mach != 0 && mach != -1ul)
++ {
++ const bfd_arch_info_type *arch;
++
++ for (arch = abfd->arch_info->next; arch; arch = arch->next)
++ if (arch->mach == mach)
++ {
++ abfd->arch_info = arch;
++ break;
++ }
++ }
++ return TRUE;
++}
++
+ /* Fix bad default arch selected for a 32 bit input bfd when the
+- default is 64 bit. */
++ default is 64 bit. Also select arch based on apuinfo. */
+
+ static bfd_boolean
+ ppc_elf_object_p (bfd *abfd)
+ {
+- if (abfd->arch_info->the_default && abfd->arch_info->bits_per_word == 64)
++ if (!abfd->arch_info->the_default)
++ return TRUE;
++
++ if (abfd->arch_info->bits_per_word == 64)
+ {
+ Elf_Internal_Ehdr *i_ehdr = elf_elfheader (abfd);
+
+@@ -2213,7 +2293,7 @@ ppc_elf_object_p (bfd *abfd)
+ BFD_ASSERT (abfd->arch_info->bits_per_word == 32);
+ }
+ }
+- return TRUE;
++ return _bfd_elf_ppc_set_arch (abfd);
+ }
+
+ /* Function to set whether a module needs the -mrelocatable bit set. */
+@@ -2519,16 +2599,16 @@ ppc_elf_modify_segment_map (bfd *abfd,
+
+ static const struct bfd_elf_special_section ppc_elf_special_sections[] =
+ {
+- { STRING_COMMA_LEN (".plt"), 0, SHT_NOBITS, SHF_ALLOC + SHF_EXECINSTR },
+- { STRING_COMMA_LEN (".sbss"), -2, SHT_NOBITS, SHF_ALLOC + SHF_WRITE },
+- { STRING_COMMA_LEN (".sbss2"), -2, SHT_PROGBITS, SHF_ALLOC },
+- { STRING_COMMA_LEN (".sdata"), -2, SHT_PROGBITS, SHF_ALLOC + SHF_WRITE },
+- { STRING_COMMA_LEN (".sdata2"), -2, SHT_PROGBITS, SHF_ALLOC },
+- { STRING_COMMA_LEN (".tags"), 0, SHT_ORDERED, SHF_ALLOC },
+- { STRING_COMMA_LEN (".PPC.EMB.apuinfo"), 0, SHT_NOTE, 0 },
+- { STRING_COMMA_LEN (".PPC.EMB.sbss0"), 0, SHT_PROGBITS, SHF_ALLOC },
+- { STRING_COMMA_LEN (".PPC.EMB.sdata0"), 0, SHT_PROGBITS, SHF_ALLOC },
+- { NULL, 0, 0, 0, 0 }
++ { STRING_COMMA_LEN (".plt"), 0, SHT_NOBITS, SHF_ALLOC + SHF_EXECINSTR },
++ { STRING_COMMA_LEN (".sbss"), -2, SHT_NOBITS, SHF_ALLOC + SHF_WRITE },
++ { STRING_COMMA_LEN (".sbss2"), -2, SHT_PROGBITS, SHF_ALLOC },
++ { STRING_COMMA_LEN (".sdata"), -2, SHT_PROGBITS, SHF_ALLOC + SHF_WRITE },
++ { STRING_COMMA_LEN (".sdata2"), -2, SHT_PROGBITS, SHF_ALLOC },
++ { STRING_COMMA_LEN (".tags"), 0, SHT_ORDERED, SHF_ALLOC },
++ { STRING_COMMA_LEN (APUINFO_SECTION_NAME), 0, SHT_NOTE, 0 },
++ { STRING_COMMA_LEN (".PPC.EMB.sbss0"), 0, SHT_PROGBITS, SHF_ALLOC },
++ { STRING_COMMA_LEN (".PPC.EMB.sdata0"), 0, SHT_PROGBITS, SHF_ALLOC },
++ { NULL, 0, 0, 0, 0 }
+ };
+
+ /* This is what we want for new plt/got. */
+@@ -2637,9 +2717,6 @@ apuinfo_list_finish (void)
+ head = NULL;
+ }
+
+-#define APUINFO_SECTION_NAME ".PPC.EMB.apuinfo"
+-#define APUINFO_LABEL "APUinfo"
+-
+ /* Scan the input BFDs and create a linked list of
+ the APUinfo values that will need to be emitted. */
+
+--- a/bfd/elf64-ppc.c
++++ b/bfd/elf64-ppc.c
+@@ -2888,12 +2888,15 @@ ppc64_elf_mkobject (bfd *abfd)
+ }
+
+ /* Fix bad default arch selected for a 64 bit input bfd when the
+- default is 32 bit. */
++ default is 32 bit. Also select arch based on apuinfo. */
+
+ static bfd_boolean
+ ppc64_elf_object_p (bfd *abfd)
+ {
+- if (abfd->arch_info->the_default && abfd->arch_info->bits_per_word == 32)
++ if (!abfd->arch_info->the_default)
++ return TRUE;
++
++ if (abfd->arch_info->bits_per_word == 32)
+ {
+ Elf_Internal_Ehdr *i_ehdr = elf_elfheader (abfd);
+
+@@ -2904,7 +2907,7 @@ ppc64_elf_object_p (bfd *abfd)
+ BFD_ASSERT (abfd->arch_info->bits_per_word == 64);
+ }
+ }
+- return TRUE;
++ return _bfd_elf_ppc_set_arch (abfd);
+ }
+
+ /* Support for core dump NOTE sections. */
+--- a/include/elf/ppc.h
++++ b/include/elf/ppc.h
+@@ -202,6 +202,19 @@ END_RELOC_NUMBERS (R_PPC_max)
+ specified in the associated \
+ symbol table entry. */
+
++/* APUinfo note section. */
++#define APUINFO_SECTION_NAME ".PPC.EMB.apuinfo"
++#define APUINFO_LABEL "APUinfo"
++
++#define PPC_APUINFO_ISEL 0x40
++#define PPC_APUINFO_PMR 0x41
++#define PPC_APUINFO_RFMCI 0x42
++#define PPC_APUINFO_CACHELCK 0x43
++#define PPC_APUINFO_SPE 0x100
++#define PPC_APUINFO_EFS 0x101
++#define PPC_APUINFO_BRLOCK 0x102
++#define PPC_APUINFO_VLE 0x104
++
+ /* Object attribute tags. */
+ enum
+ {
+### a/opcodes/ChangeLog
+### b/opcodes/ChangeLog
+## -1,3 +1,14 @@
++2016-06-07 Alan Modra <amodra@gmail.com>
++
++ * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
++ cpu for "vle" to e500.
++ * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
++ (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
++ (PPCNONE): Delete, substitute throughout.
++ (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
++ except for major opcode 4 and 31.
++ (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
++
+ 2016-06-07 Matthew Wahab <matthew.wahab@arm.com>
+
+ * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
+--- a/opcodes/ppc-dis.c
++++ b/opcodes/ppc-dis.c
+@@ -51,9 +51,9 @@ struct ppc_mopt {
+ };
+
+ struct ppc_mopt ppc_opts[] = {
+- { "403", (PPC_OPCODE_PPC | PPC_OPCODE_403),
++ { "403", PPC_OPCODE_PPC | PPC_OPCODE_403,
+ 0 },
+- { "405", (PPC_OPCODE_PPC | PPC_OPCODE_403 | PPC_OPCODE_405),
++ { "405", PPC_OPCODE_PPC | PPC_OPCODE_403 | PPC_OPCODE_405,
+ 0 },
+ { "440", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
+ | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
+@@ -64,48 +64,48 @@ struct ppc_mopt ppc_opts[] = {
+ { "476", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_440
+ | PPC_OPCODE_476 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5),
+ 0 },
+- { "601", (PPC_OPCODE_PPC | PPC_OPCODE_601),
++ { "601", PPC_OPCODE_PPC | PPC_OPCODE_601,
+ 0 },
+- { "603", (PPC_OPCODE_PPC),
++ { "603", PPC_OPCODE_PPC,
+ 0 },
+- { "604", (PPC_OPCODE_PPC),
++ { "604", PPC_OPCODE_PPC,
+ 0 },
+- { "620", (PPC_OPCODE_PPC | PPC_OPCODE_64),
++ { "620", PPC_OPCODE_PPC | PPC_OPCODE_64,
+ 0 },
+- { "7400", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
++ { "7400", PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
+ 0 },
+- { "7410", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
++ { "7410", PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
+ 0 },
+- { "7450", (PPC_OPCODE_PPC | PPC_OPCODE_7450 | PPC_OPCODE_ALTIVEC),
++ { "7450", PPC_OPCODE_PPC | PPC_OPCODE_7450 | PPC_OPCODE_ALTIVEC,
+ 0 },
+- { "7455", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
++ { "7455", PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
+ 0 },
+- { "750cl", (PPC_OPCODE_PPC | PPC_OPCODE_750 | PPC_OPCODE_PPCPS)
++ { "750cl", PPC_OPCODE_PPC | PPC_OPCODE_750 | PPC_OPCODE_PPCPS
+ , 0 },
+- { "821", (PPC_OPCODE_PPC | PPC_OPCODE_860),
++ { "821", PPC_OPCODE_PPC | PPC_OPCODE_860,
+ 0 },
+- { "850", (PPC_OPCODE_PPC | PPC_OPCODE_860),
++ { "850", PPC_OPCODE_PPC | PPC_OPCODE_860,
+ 0 },
+- { "860", (PPC_OPCODE_PPC | PPC_OPCODE_860),
++ { "860", PPC_OPCODE_PPC | PPC_OPCODE_860,
+ 0 },
+ { "a2", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_POWER4
+ | PPC_OPCODE_POWER5 | PPC_OPCODE_CACHELCK | PPC_OPCODE_64
+ | PPC_OPCODE_A2),
+ 0 },
+- { "altivec", (PPC_OPCODE_PPC),
++ { "altivec", PPC_OPCODE_PPC,
+ PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 },
+ { "any", 0,
+ PPC_OPCODE_ANY },
+- { "booke", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE),
++ { "booke", PPC_OPCODE_PPC | PPC_OPCODE_BOOKE,
+ 0 },
+- { "booke32", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE),
++ { "booke32", PPC_OPCODE_PPC | PPC_OPCODE_BOOKE,
+ 0 },
+ { "cell", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
+ | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC),
+ 0 },
+- { "com", (PPC_OPCODE_COMMON),
++ { "com", PPC_OPCODE_COMMON,
+ 0 },
+- { "e300", (PPC_OPCODE_PPC | PPC_OPCODE_E300),
++ { "e300", PPC_OPCODE_PPC | PPC_OPCODE_E300,
+ 0 },
+ { "e500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
+ | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
+@@ -138,9 +138,9 @@ struct ppc_mopt ppc_opts[] = {
+ | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
+ | PPC_OPCODE_E500),
+ 0 },
+- { "efs", (PPC_OPCODE_PPC | PPC_OPCODE_EFS),
++ { "efs", PPC_OPCODE_PPC | PPC_OPCODE_EFS,
+ 0 },
+- { "power4", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4),
++ { "power4", PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4,
+ 0 },
+ { "power5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
+ | PPC_OPCODE_POWER5),
+@@ -163,21 +163,21 @@ struct ppc_mopt ppc_opts[] = {
+ | PPC_OPCODE_HTM | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2
+ | PPC_OPCODE_VSX | PPC_OPCODE_VSX3 ),
+ 0 },
+- { "ppc", (PPC_OPCODE_PPC),
++ { "ppc", PPC_OPCODE_PPC,
+ 0 },
+- { "ppc32", (PPC_OPCODE_PPC),
++ { "ppc32", PPC_OPCODE_PPC,
+ 0 },
+- { "ppc64", (PPC_OPCODE_PPC | PPC_OPCODE_64),
++ { "ppc64", PPC_OPCODE_PPC | PPC_OPCODE_64,
+ 0 },
+- { "ppc64bridge", (PPC_OPCODE_PPC | PPC_OPCODE_64_BRIDGE),
++ { "ppc64bridge", PPC_OPCODE_PPC | PPC_OPCODE_64_BRIDGE,
+ 0 },
+- { "ppcps", (PPC_OPCODE_PPC | PPC_OPCODE_PPCPS),
++ { "ppcps", PPC_OPCODE_PPC | PPC_OPCODE_PPCPS,
+ 0 },
+- { "pwr", (PPC_OPCODE_POWER),
++ { "pwr", PPC_OPCODE_POWER,
+ 0 },
+- { "pwr2", (PPC_OPCODE_POWER | PPC_OPCODE_POWER2),
++ { "pwr2", PPC_OPCODE_POWER | PPC_OPCODE_POWER2,
+ 0 },
+- { "pwr4", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4),
++ { "pwr4", PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4,
+ 0 },
+ { "pwr5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
+ | PPC_OPCODE_POWER5),
+@@ -203,18 +203,21 @@ struct ppc_mopt ppc_opts[] = {
+ | PPC_OPCODE_HTM | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2
+ | PPC_OPCODE_VSX | PPC_OPCODE_VSX3 ),
+ 0 },
+- { "pwrx", (PPC_OPCODE_POWER | PPC_OPCODE_POWER2),
++ { "pwrx", PPC_OPCODE_POWER | PPC_OPCODE_POWER2,
+ 0 },
+- { "spe", (PPC_OPCODE_PPC | PPC_OPCODE_EFS),
++ { "spe", PPC_OPCODE_PPC | PPC_OPCODE_EFS,
+ PPC_OPCODE_SPE },
+ { "titan", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR
+ | PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN),
+ 0 },
+- { "vle", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_VLE),
++ { "vle", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE
++ | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
++ | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
++ | PPC_OPCODE_E500),
+ PPC_OPCODE_VLE },
+- { "vsx", (PPC_OPCODE_PPC),
++ { "vsx", PPC_OPCODE_PPC,
+ PPC_OPCODE_VSX | PPC_OPCODE_VSX3 },
+- { "htm", (PPC_OPCODE_PPC),
++ { "htm", PPC_OPCODE_PPC,
+ PPC_OPCODE_HTM },
+ };
+
+--- a/opcodes/ppc-opc.c
++++ b/opcodes/ppc-opc.c
+@@ -2049,7 +2049,7 @@ extract_spr (unsigned long insn,
+ }
+
+ /* Some dialects have 8 SPRG registers instead of the standard 4. */
+-#define ALLOW8_SPRG (PPC_OPCODE_BOOKE | PPC_OPCODE_405 | PPC_OPCODE_VLE)
++#define ALLOW8_SPRG (PPC_OPCODE_BOOKE | PPC_OPCODE_405)
+
+ static unsigned long
+ insert_sprg (unsigned long insn,
+@@ -2977,7 +2977,6 @@ extract_vleil (unsigned long insn,
+
+ /* Smaller names for the flags so each entry in the opcodes table will
+ fit on a single line. */
+-#define PPCNONE 0
+ #undef PPC
+ #define PPC PPC_OPCODE_PPC
+ #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
+@@ -3016,11 +3015,11 @@ extract_vleil (unsigned long insn,
+ #define MFDEC1 PPC_OPCODE_POWER
+ #define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE | PPC_OPCODE_TITAN
+ #define BOOKE PPC_OPCODE_BOOKE
+-#define NO371 PPC_OPCODE_BOOKE | PPC_OPCODE_PPCPS | PPC_OPCODE_EFS | PPC_OPCODE_VLE
++#define NO371 PPC_OPCODE_BOOKE | PPC_OPCODE_PPCPS | PPC_OPCODE_EFS
+ #define PPCE300 PPC_OPCODE_E300
+-#define PPCSPE PPC_OPCODE_SPE | PPC_OPCODE_VLE
+-#define PPCISEL PPC_OPCODE_ISEL | PPC_OPCODE_VLE
+-#define PPCEFS PPC_OPCODE_EFS | PPC_OPCODE_VLE
++#define PPCSPE PPC_OPCODE_SPE
++#define PPCISEL PPC_OPCODE_ISEL
++#define PPCEFS PPC_OPCODE_EFS
+ #define PPCBRLK PPC_OPCODE_BRLOCK
+ #define PPCPMR PPC_OPCODE_PMR
+ #define PPCTMR PPC_OPCODE_TMR
+@@ -3029,7 +3028,7 @@ extract_vleil (unsigned long insn,
+ #define E500MC PPC_OPCODE_E500MC
+ #define PPCA2 PPC_OPCODE_A2
+ #define TITAN PPC_OPCODE_TITAN
+-#define MULHW PPC_OPCODE_405 | PPC_OPCODE_440 | TITAN | PPC_OPCODE_VLE
++#define MULHW PPC_OPCODE_405 | PPC_OPCODE_440 | TITAN
+ #define E500 PPC_OPCODE_E500
+ #define E6500 PPC_OPCODE_E6500
+ #define PPCVLE PPC_OPCODE_VLE
+@@ -3037,7 +3036,7 @@ extract_vleil (unsigned long insn,
+ /* The list of embedded processors that use the embedded operand ordering
+ for the 3 operand dcbt and dcbtst instructions. */
+ #define DCBT_EO (PPC_OPCODE_E500 | PPC_OPCODE_E500MC | PPC_OPCODE_476 \
+- | PPC_OPCODE_A2 | PPC_OPCODE_VLE)
++ | PPC_OPCODE_A2)
+
+
+
+@@ -3064,3930 +3063,3930 @@ extract_vleil (unsigned long insn,
+ constrained otherwise by disassembler operation. */
+
+ const struct powerpc_opcode powerpc_opcodes[] = {
+-{"attn", X(0,256), X_MASK, POWER4|PPCA2, PPC476, {0}},
+-{"tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
+-{"tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
+-{"tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
+-{"tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
+-{"tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
+-{"tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
+-{"tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
+-{"tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
+-{"tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
+-{"tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
+-{"tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
+-{"tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
+-{"tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
+-{"tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
+-{"tdui", OPTO(2,TOU), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
+-{"tdi", OP(2), OP_MASK, PPC64, PPCNONE, {TO, RA, SI}},
+-
+-{"twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
+-{"tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
+-{"twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
+-{"tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
+-{"tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
+-{"teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
+-{"twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
+-{"tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
+-{"twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
+-{"tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
+-{"twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
+-{"tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
+-{"twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
+-{"tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
+-{"twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
+-{"tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
+-{"twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
+-{"tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
+-{"twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
+-{"tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
+-{"twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
+-{"tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
+-{"twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
+-{"tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
+-{"twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
+-{"tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
+-{"twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
+-{"tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
+-{"twui", OPTO(3,TOU), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
+-{"tui", OPTO(3,TOU), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
+-{"twi", OP(3), OP_MASK, PPCCOM, PPCNONE, {TO, RA, SI}},
+-{"ti", OP(3), OP_MASK, PWRCOM, PPCNONE, {TO, RA, SI}},
+-
+-{"ps_cmpu0", X (4, 0), XBF_MASK, PPCPS, PPCNONE, {BF, FRA, FRB}},
+-{"vaddubm", VX (4, 0), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vmul10cuq", VX (4, 1), VXVB_MASK, PPCVEC3, PPCNONE, {VD, VA}},
+-{"vmaxub", VX (4, 2), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vrlb", VX (4, 4), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vcmpequb", VXR(4, 6,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vcmpneb", VXR(4, 7,0), VXR_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}},
+-{"vmuloub", VX (4, 8), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vaddfp", VX (4, 10), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"psq_lx", XW (4, 6,0), XW_MASK, PPCPS, PPCNONE, {FRT,RA,RB,PSWM,PSQM}},
+-{"vmrghb", VX (4, 12), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"psq_stx", XW (4, 7,0), XW_MASK, PPCPS, PPCNONE, {FRS,RA,RB,PSWM,PSQM}},
+-{"vpkuhum", VX (4, 14), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"mulhhwu", XRC(4, 8,0), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"mulhhwu.", XRC(4, 8,1), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"ps_sum0", A (4, 10,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
+-{"ps_sum0.", A (4, 10,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
+-{"ps_sum1", A (4, 11,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
+-{"ps_sum1.", A (4, 11,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
+-{"ps_muls0", A (4, 12,0), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}},
+-{"machhwu", XO (4, 12,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"ps_muls0.", A (4, 12,1), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}},
+-{"machhwu.", XO (4, 12,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"ps_muls1", A (4, 13,0), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}},
+-{"ps_muls1.", A (4, 13,1), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}},
+-{"ps_madds0", A (4, 14,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
+-{"ps_madds0.", A (4, 14,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
+-{"ps_madds1", A (4, 15,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
+-{"ps_madds1.", A (4, 15,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
+-{"vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}},
+-{"vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}},
+-{"vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}},
+-{"vmsumudm", VXA(4, 35), VXA_MASK, PPCVEC3, PPCNONE, {VD, VA, VB, VC}},
+-{"ps_div", A (4, 18,0), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
+-{"vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}},
+-{"ps_div.", A (4, 18,1), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
+-{"vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}},
+-{"vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}},
+-{"vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}},
+-{"ps_sub", A (4, 20,0), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
+-{"vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}},
+-{"ps_sub.", A (4, 20,1), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
+-{"vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}},
+-{"ps_add", A (4, 21,0), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
+-{"vsel", VXA(4, 42), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}},
+-{"ps_add.", A (4, 21,1), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
+-{"vperm", VXA(4, 43), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}},
+-{"vsldoi", VXA(4, 44), VXASHB_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, SHB}},
+-{"vpermxor", VXA(4, 45), VXA_MASK, PPCVEC2, PPCNONE, {VD, VA, VB, VC}},
+-{"ps_sel", A (4, 23,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
+-{"vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VC, VB}},
+-{"ps_sel.", A (4, 23,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
+-{"vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VC, VB}},
+-{"ps_res", A (4, 24,0), AFRAFRC_MASK, PPCPS, PPCNONE, {FRT, FRB}},
+-{"maddhd", VXA(4, 48), VXA_MASK, POWER9, PPCNONE, {RT, RA, RB, RC}},
+-{"ps_res.", A (4, 24,1), AFRAFRC_MASK, PPCPS, PPCNONE, {FRT, FRB}},
+-{"maddhdu", VXA(4, 49), VXA_MASK, POWER9, PPCNONE, {RT, RA, RB, RC}},
+-{"ps_mul", A (4, 25,0), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}},
+-{"ps_mul.", A (4, 25,1), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}},
+-{"maddld", VXA(4, 51), VXA_MASK, POWER9, PPCNONE, {RT, RA, RB, RC}},
+-{"ps_rsqrte", A (4, 26,0), AFRAFRC_MASK, PPCPS, PPCNONE, {FRT, FRB}},
+-{"ps_rsqrte.", A (4, 26,1), AFRAFRC_MASK, PPCPS, PPCNONE, {FRT, FRB}},
+-{"ps_msub", A (4, 28,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
+-{"ps_msub.", A (4, 28,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
+-{"ps_madd", A (4, 29,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
+-{"ps_madd.", A (4, 29,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
+-{"vpermr", VXA(4, 59), VXA_MASK, PPCVEC3, PPCNONE, {VD, VA, VB, VC}},
+-{"ps_nmsub", A (4, 30,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
+-{"vaddeuqm", VXA(4, 60), VXA_MASK, PPCVEC2, PPCNONE, {VD, VA, VB, VC}},
+-{"ps_nmsub.", A (4, 30,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
+-{"vaddecuq", VXA(4, 61), VXA_MASK, PPCVEC2, PPCNONE, {VD, VA, VB, VC}},
+-{"ps_nmadd", A (4, 31,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
+-{"vsubeuqm", VXA(4, 62), VXA_MASK, PPCVEC2, PPCNONE, {VD, VA, VB, VC}},
+-{"ps_nmadd.", A (4, 31,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
+-{"vsubecuq", VXA(4, 63), VXA_MASK, PPCVEC2, PPCNONE, {VD, VA, VB, VC}},
+-{"ps_cmpo0", X (4, 32), XBF_MASK, PPCPS, PPCNONE, {BF, FRA, FRB}},
+-{"vadduhm", VX (4, 64), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vmul10ecuq", VX (4, 65), VX_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}},
+-{"vmaxuh", VX (4, 66), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vrlh", VX (4, 68), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vcmpequh", VXR(4, 70,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vcmpneh", VXR(4, 71,0), VXR_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}},
+-{"vmulouh", VX (4, 72), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vsubfp", VX (4, 74), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"psq_lux", XW (4, 38,0), XW_MASK, PPCPS, PPCNONE, {FRT,RA,RB,PSWM,PSQM}},
+-{"vmrghh", VX (4, 76), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"psq_stux", XW (4, 39,0), XW_MASK, PPCPS, PPCNONE, {FRS,RA,RB,PSWM,PSQM}},
+-{"vpkuwum", VX (4, 78), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"ps_neg", XRC(4, 40,0), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}},
+-{"mulhhw", XRC(4, 40,0), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"ps_neg.", XRC(4, 40,1), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}},
+-{"mulhhw.", XRC(4, 40,1), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"machhw", XO (4, 44,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"machhw.", XO (4, 44,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"nmachhw", XO (4, 46,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"nmachhw.", XO (4, 46,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"ps_cmpu1", X (4, 64), XBF_MASK, PPCPS, PPCNONE, {BF, FRA, FRB}},
+-{"vadduwm", VX (4, 128), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vmaxuw", VX (4, 130), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vrlw", VX (4, 132), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vrlwmi", VX (4, 133), VX_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}},
+-{"vcmpequw", VXR(4, 134,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vcmpnew", VXR(4, 135,0), VXR_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}},
+-{"vmulouw", VX (4, 136), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+-{"vmuluwm", VX (4, 137), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+-{"vmrghw", VX (4, 140), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vpkuhus", VX (4, 142), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"ps_mr", XRC(4, 72,0), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}},
+-{"ps_mr.", XRC(4, 72,1), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}},
+-{"machhwsu", XO (4, 76,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"machhwsu.", XO (4, 76,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"ps_cmpo1", X (4, 96), XBF_MASK, PPCPS, PPCNONE, {BF, FRA, FRB}},
+-{"vaddudm", VX (4, 192), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+-{"vmaxud", VX (4, 194), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+-{"vrld", VX (4, 196), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+-{"vrldmi", VX (4, 197), VX_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}},
+-{"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vcmpequd", VXR(4, 199,0), VXR_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+-{"vpkuwus", VX (4, 206), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"machhws", XO (4, 108,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"machhws.", XO (4, 108,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"nmachhws", XO (4, 110,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"nmachhws.", XO (4, 110,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"vadduqm", VX (4, 256), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+-{"vmaxsb", VX (4, 258), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vslb", VX (4, 260), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vcmpnezb", VXR(4, 263,0), VXR_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}},
+-{"vmulosb", VX (4, 264), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vrefp", VX (4, 266), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}},
+-{"vmrglb", VX (4, 268), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vpkshus", VX (4, 270), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"ps_nabs", XRC(4, 136,0), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}},
+-{"mulchwu", XRC(4, 136,0), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"ps_nabs.", XRC(4, 136,1), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}},
+-{"mulchwu.", XRC(4, 136,1), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"macchwu", XO (4, 140,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"macchwu.", XO (4, 140,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"vaddcuq", VX (4, 320), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+-{"vmaxsh", VX (4, 322), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vslh", VX (4, 324), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vcmpnezh", VXR(4, 327,0), VXR_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}},
+-{"vmulosh", VX (4, 328), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vrsqrtefp", VX (4, 330), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}},
+-{"vmrglh", VX (4, 332), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vpkswus", VX (4, 334), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"mulchw", XRC(4, 168,0), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"mulchw.", XRC(4, 168,1), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"macchw", XO (4, 172,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"macchw.", XO (4, 172,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"nmacchw", XO (4, 174,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"nmacchw.", XO (4, 174,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"vaddcuw", VX (4, 384), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vmaxsw", VX (4, 386), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vslw", VX (4, 388), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vrlwnm", VX (4, 389), VX_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}},
+-{"vcmpnezw", VXR(4, 391,0), VXR_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}},
+-{"vmulosw", VX (4, 392), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+-{"vexptefp", VX (4, 394), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}},
+-{"vmrglw", VX (4, 396), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vpkshss", VX (4, 398), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"macchwsu", XO (4, 204,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"macchwsu.", XO (4, 204,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"vmaxsd", VX (4, 450), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+-{"vsl", VX (4, 452), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vrldnm", VX (4, 453), VX_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}},
+-{"vcmpgefp", VXR(4, 454,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vlogefp", VX (4, 458), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}},
+-{"vpkswss", VX (4, 462), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"macchws", XO (4, 236,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"macchws.", XO (4, 236,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"nmacchws", XO (4, 238,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"nmacchws.", XO (4, 238,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"evaddw", VX (4, 512), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"vaddubs", VX (4, 512), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vmul10uq", VX (4, 513), VXVB_MASK, PPCVEC3, PPCNONE, {VD, VA}},
+-{"evaddiw", VX (4, 514), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RB, UIMM}},
+-{"vminub", VX (4, 514), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"evsubfw", VX (4, 516), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evsubw", VX (4, 516), VX_MASK, PPCSPE, PPCNONE, {RS, RB, RA}},
+-{"vsrb", VX (4, 516), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"evsubifw", VX (4, 518), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, UIMM, RB}},
+-{"evsubiw", VX (4, 518), VX_MASK, PPCSPE, PPCNONE, {RS, RB, UIMM}},
+-{"vcmpgtub", VXR(4, 518,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"evabs", VX (4, 520), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
+-{"vmuleub", VX (4, 520), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"evneg", VX (4, 521), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
+-{"evextsb", VX (4, 522), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
+-{"vrfin", VX (4, 522), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}},
+-{"evextsh", VX (4, 523), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
+-{"evrndw", VX (4, 524), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
+-{"vspltb", VX (4, 524), VXUIMM4_MASK,PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM4}},
+-{"vextractub", VX (4, 525), VXUIMM4_MASK,PPCVEC3, PPCNONE, {VD, VB, UIMM4}},
+-{"evcntlzw", VX (4, 525), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
+-{"evcntlsw", VX (4, 526), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
+-{"vupkhsb", VX (4, 526), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}},
+-{"brinc", VX (4, 527), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"ps_abs", XRC(4, 264,0), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}},
+-{"ps_abs.", XRC(4, 264,1), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}},
+-{"evand", VX (4, 529), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evandc", VX (4, 530), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evxor", VX (4, 534), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evmr", VX (4, 535), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, BBA}},
+-{"evor", VX (4, 535), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evnor", VX (4, 536), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evnot", VX (4, 536), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, BBA}},
+-{"get", APU(4, 268,0), APU_RA_MASK, PPC405, PPCNONE, {RT, FSL}},
+-{"eveqv", VX (4, 537), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evorc", VX (4, 539), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evnand", VX (4, 542), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evsrwu", VX (4, 544), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evsrws", VX (4, 545), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evsrwiu", VX (4, 546), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, EVUIMM}},
+-{"evsrwis", VX (4, 547), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, EVUIMM}},
+-{"evslw", VX (4, 548), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evslwi", VX (4, 550), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, EVUIMM}},
+-{"evrlw", VX (4, 552), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evsplati", VX (4, 553), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, SIMM}},
+-{"evrlwi", VX (4, 554), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, EVUIMM}},
+-{"evsplatfi", VX (4, 555), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, SIMM}},
+-{"evmergehi", VX (4, 556), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evmergelo", VX (4, 557), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evmergehilo", VX (4, 558), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evmergelohi", VX (4, 559), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evcmpgtu", VX (4, 560), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {CRFD, RA, RB}},
+-{"evcmpgts", VX (4, 561), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {CRFD, RA, RB}},
+-{"evcmpltu", VX (4, 562), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {CRFD, RA, RB}},
+-{"evcmplts", VX (4, 563), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {CRFD, RA, RB}},
+-{"evcmpeq", VX (4, 564), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {CRFD, RA, RB}},
+-{"cget", APU(4, 284,0), APU_RA_MASK, PPC405, PPCNONE, {RT, FSL}},
+-{"vadduhs", VX (4, 576), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vmul10euq", VX (4, 577), VX_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}},
+-{"vminuh", VX (4, 578), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vsrh", VX (4, 580), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vcmpgtuh", VXR(4, 582,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vmuleuh", VX (4, 584), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vrfiz", VX (4, 586), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}},
+-{"vsplth", VX (4, 588), VXUIMM3_MASK,PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM3}},
+-{"vextractuh", VX (4, 589), VXUIMM4_MASK,PPCVEC3, PPCNONE, {VD, VB, UIMM4}},
+-{"vupkhsh", VX (4, 590), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}},
+-{"nget", APU(4, 300,0), APU_RA_MASK, PPC405, PPCNONE, {RT, FSL}},
+-{"evsel", EVSEL(4,79), EVSEL_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB, CRFS}},
+-{"ncget", APU(4, 316,0), APU_RA_MASK, PPC405, PPCNONE, {RT, FSL}},
+-{"evfsadd", VX (4, 640), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"vadduws", VX (4, 640), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"evfssub", VX (4, 641), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"vminuw", VX (4, 642), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"evfsabs", VX (4, 644), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
+-{"vsrw", VX (4, 644), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"evfsnabs", VX (4, 645), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
+-{"evfsneg", VX (4, 646), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
+-{"vcmpgtuw", VXR(4, 646,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vmuleuw", VX (4, 648), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+-{"evfsmul", VX (4, 648), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evfsdiv", VX (4, 649), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"vrfip", VX (4, 650), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}},
+-{"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {CRFD, RA, RB}},
+-{"vspltw", VX (4, 652), VXUIMM2_MASK,PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM2}},
+-{"vextractuw", VX (4, 653), VXUIMM4_MASK,PPCVEC3, PPCNONE, {VD, VB, UIMM4}},
+-{"evfscmplt", VX (4, 653), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {CRFD, RA, RB}},
+-{"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {CRFD, RA, RB}},
+-{"vupklsb", VX (4, 654), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}},
+-{"evfscfui", VX (4, 656), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RB}},
+-{"evfscfsi", VX (4, 657), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RB}},
+-{"evfscfuf", VX (4, 658), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RB}},
+-{"evfscfsf", VX (4, 659), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RB}},
+-{"evfsctui", VX (4, 660), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RB}},
+-{"evfsctsi", VX (4, 661), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RB}},
+-{"evfsctuf", VX (4, 662), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RB}},
+-{"evfsctsf", VX (4, 663), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RB}},
+-{"evfsctuiz", VX (4, 664), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RB}},
+-{"put", APU(4, 332,0), APU_RT_MASK, PPC405, PPCNONE, {RA, FSL}},
+-{"evfsctsiz", VX (4, 666), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RB}},
+-{"evfststgt", VX (4, 668), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {CRFD, RA, RB}},
+-{"evfststlt", VX (4, 669), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {CRFD, RA, RB}},
+-{"evfststeq", VX (4, 670), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {CRFD, RA, RB}},
+-{"cput", APU(4, 348,0), APU_RT_MASK, PPC405, PPCNONE, {RA, FSL}},
+-{"efsadd", VX (4, 704), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"efssub", VX (4, 705), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"vminud", VX (4, 706), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+-{"efsabs", VX (4, 708), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA}},
+-{"vsr", VX (4, 708), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"efsnabs", VX (4, 709), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA}},
+-{"efsneg", VX (4, 710), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA}},
+-{"vcmpgtfp", VXR(4, 710,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vcmpgtud", VXR(4, 711,0), VXR_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+-{"efsmul", VX (4, 712), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"efsdiv", VX (4, 713), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"vrfim", VX (4, 714), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}},
+-{"efscmpgt", VX (4, 716), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {CRFD, RA, RB}},
+-{"vextractd", VX (4, 717), VXUIMM4_MASK,PPCVEC3, PPCNONE, {VD, VB, UIMM4}},
+-{"efscmplt", VX (4, 717), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {CRFD, RA, RB}},
+-{"efscmpeq", VX (4, 718), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {CRFD, RA, RB}},
+-{"vupklsh", VX (4, 718), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}},
+-{"efscfd", VX (4, 719), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}},
+-{"efscfui", VX (4, 720), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}},
+-{"efscfsi", VX (4, 721), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}},
+-{"efscfuf", VX (4, 722), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}},
+-{"efscfsf", VX (4, 723), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}},
+-{"efsctui", VX (4, 724), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}},
+-{"efsctsi", VX (4, 725), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}},
+-{"efsctuf", VX (4, 726), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}},
+-{"efsctsf", VX (4, 727), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}},
+-{"efsctuiz", VX (4, 728), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}},
+-{"nput", APU(4, 364,0), APU_RT_MASK, PPC405, PPCNONE, {RA, FSL}},
+-{"efsctsiz", VX (4, 730), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}},
+-{"efststgt", VX (4, 732), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {CRFD, RA, RB}},
+-{"efststlt", VX (4, 733), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {CRFD, RA, RB}},
+-{"efststeq", VX (4, 734), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {CRFD, RA, RB}},
+-{"efdadd", VX (4, 736), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"efdsub", VX (4, 737), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"efdcfuid", VX (4, 738), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}},
+-{"efdcfsid", VX (4, 739), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}},
+-{"efdabs", VX (4, 740), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA}},
+-{"efdnabs", VX (4, 741), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA}},
+-{"efdneg", VX (4, 742), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA}},
+-{"efdmul", VX (4, 744), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"efddiv", VX (4, 745), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"efdctuidz", VX (4, 746), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}},
+-{"efdctsidz", VX (4, 747), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}},
+-{"efdcmpgt", VX (4, 748), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {CRFD, RA, RB}},
+-{"efdcmplt", VX (4, 749), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {CRFD, RA, RB}},
+-{"efdcmpeq", VX (4, 750), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {CRFD, RA, RB}},
+-{"efdcfs", VX (4, 751), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}},
+-{"efdcfui", VX (4, 752), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}},
+-{"efdcfsi", VX (4, 753), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}},
+-{"efdcfuf", VX (4, 754), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}},
+-{"efdcfsf", VX (4, 755), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}},
+-{"efdctui", VX (4, 756), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}},
+-{"efdctsi", VX (4, 757), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}},
+-{"efdctuf", VX (4, 758), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}},
+-{"efdctsf", VX (4, 759), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}},
+-{"efdctuiz", VX (4, 760), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}},
+-{"ncput", APU(4, 380,0), APU_RT_MASK, PPC405, PPCNONE, {RA, FSL}},
+-{"efdctsiz", VX (4, 762), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}},
+-{"efdtstgt", VX (4, 764), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {CRFD, RA, RB}},
+-{"efdtstlt", VX (4, 765), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {CRFD, RA, RB}},
+-{"efdtsteq", VX (4, 766), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {CRFD, RA, RB}},
+-{"evlddx", VX (4, 768), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"vaddsbs", VX (4, 768), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"evldd", VX (4, 769), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_8, RA}},
+-{"evldwx", VX (4, 770), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"vminsb", VX (4, 770), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"evldw", VX (4, 771), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_8, RA}},
+-{"evldhx", VX (4, 772), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"vsrab", VX (4, 772), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"evldh", VX (4, 773), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_8, RA}},
+-{"vcmpgtsb", VXR(4, 774,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"evlhhesplatx",VX (4, 776), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"vmulesb", VX (4, 776), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"evlhhesplat", VX (4, 777), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_2, RA}},
+-{"vcfux", VX (4, 778), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}},
+-{"vcuxwfp", VX (4, 778), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}},
+-{"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"vspltisb", VX (4, 780), VXVB_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, SIMM}},
+-{"vinsertb", VX (4, 781), VXUIMM4_MASK,PPCVEC3, PPCNONE, {VD, VB, UIMM4}},
+-{"evlhhousplat",VX (4, 781), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_2, RA}},
+-{"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"vpkpx", VX (4, 782), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"evlhhossplat",VX (4, 783), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_2, RA}},
+-{"mullhwu", XRC(4, 392,0), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"evlwhex", VX (4, 784), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"mullhwu.", XRC(4, 392,1), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"evlwhe", VX (4, 785), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_4, RA}},
+-{"evlwhoux", VX (4, 788), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evlwhou", VX (4, 789), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_4, RA}},
+-{"evlwhosx", VX (4, 790), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evlwhos", VX (4, 791), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_4, RA}},
+-{"maclhwu", XO (4, 396,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"evlwwsplatx", VX (4, 792), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"maclhwu.", XO (4, 396,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"evlwwsplat", VX (4, 793), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_4, RA}},
+-{"evlwhsplatx", VX (4, 796), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evlwhsplat", VX (4, 797), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_4, RA}},
+-{"evstddx", VX (4, 800), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evstdd", VX (4, 801), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_8, RA}},
+-{"evstdwx", VX (4, 802), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evstdw", VX (4, 803), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_8, RA}},
+-{"evstdhx", VX (4, 804), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evstdh", VX (4, 805), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_8, RA}},
+-{"evstwhex", VX (4, 816), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evstwhe", VX (4, 817), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_4, RA}},
+-{"evstwhox", VX (4, 820), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evstwho", VX (4, 821), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_4, RA}},
+-{"evstwwex", VX (4, 824), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evstwwe", VX (4, 825), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_4, RA}},
+-{"evstwwox", VX (4, 828), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evstwwo", VX (4, 829), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_4, RA}},
+-{"vaddshs", VX (4, 832), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"bcdcpsgn.", VX (4, 833), VX_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}},
+-{"vminsh", VX (4, 834), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vsrah", VX (4, 836), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vcmpgtsh", VXR(4, 838,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vmulesh", VX (4, 840), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vcfsx", VX (4, 842), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}},
+-{"vcsxwfp", VX (4, 842), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}},
+-{"vspltish", VX (4, 844), VXVB_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, SIMM}},
+-{"vinserth", VX (4, 845), VXUIMM4_MASK,PPCVEC3, PPCNONE, {VD, VB, UIMM4}},
+-{"vupkhpx", VX (4, 846), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}},
+-{"mullhw", XRC(4, 424,0), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"mullhw.", XRC(4, 424,1), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"maclhw", XO (4, 428,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"maclhw.", XO (4, 428,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"nmaclhw", XO (4, 430,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"nmaclhw.", XO (4, 430,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"vaddsws", VX (4, 896), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vminsw", VX (4, 898), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vsraw", VX (4, 900), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vcmpgtsw", VXR(4, 902,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vmulesw", VX (4, 904), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+-{"vctuxs", VX (4, 906), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}},
+-{"vcfpuxws", VX (4, 906), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}},
+-{"vspltisw", VX (4, 908), VXVB_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, SIMM}},
+-{"vinsertw", VX (4, 909), VXUIMM4_MASK,PPCVEC3, PPCNONE, {VD, VB, UIMM4}},
+-{"maclhwsu", XO (4, 460,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"maclhwsu.", XO (4, 460,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"vminsd", VX (4, 962), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+-{"vsrad", VX (4, 964), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+-{"vcmpbfp", VXR(4, 966,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vcmpgtsd", VXR(4, 967,0), VXR_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+-{"vctsxs", VX (4, 970), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}},
+-{"vcfpsxws", VX (4, 970), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}},
+-{"vinsertd", VX (4, 973), VXUIMM4_MASK,PPCVEC3, PPCNONE, {VD, VB, UIMM4}},
+-{"vupklpx", VX (4, 974), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}},
+-{"maclhws", XO (4, 492,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"maclhws.", XO (4, 492,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"nmaclhws", XO (4, 494,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"nmaclhws.", XO (4, 494,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"vsububm", VX (4,1024), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"bcdadd.", VX (4,1025), VXPS_MASK, PPCVEC2, PPCNONE, {VD, VA, VB, PS}},
+-{"vavgub", VX (4,1026), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vabsdub", VX (4,1027), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+-{"evmhessf", VX (4,1027), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"vand", VX (4,1028), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vcmpequb.", VXR(4, 6,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vcmpneb.", VXR(4, 7,1), VXR_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}},
+-{"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
+-{"udi0fcm", APU(4, 515,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
+-{"evmhossf", VX (4,1031), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"vpmsumb", VX (4,1032), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+-{"evmheumi", VX (4,1032), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evmhesmi", VX (4,1033), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"vmaxfp", VX (4,1034), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"evmhesmf", VX (4,1035), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evmhoumi", VX (4,1036), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"vslo", VX (4,1036), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"evmhosmi", VX (4,1037), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evmhosmf", VX (4,1039), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"machhwuo", XO (4, 12,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"machhwuo.", XO (4, 12,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"ps_merge00", XOPS(4,528,0), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
+-{"ps_merge00.", XOPS(4,528,1), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
+-{"evmhessfa", VX (4,1059), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evmhossfa", VX (4,1063), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evmheumia", VX (4,1064), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evmhesmia", VX (4,1065), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evmhesmfa", VX (4,1067), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evmhoumia", VX (4,1068), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evmhosmia", VX (4,1069), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evmhosmfa", VX (4,1071), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"vsubuhm", VX (4,1088), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"bcdsub.", VX (4,1089), VXPS_MASK, PPCVEC2, PPCNONE, {VD, VA, VB, PS}},
+-{"vavguh", VX (4,1090), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vabsduh", VX (4,1091), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+-{"vandc", VX (4,1092), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vcmpequh.", VXR(4, 70,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"udi1fcm.", APU(4, 547,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
+-{"udi1fcm", APU(4, 547,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
+-{"vcmpneh.", VXR(4, 71,1), VXR_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}},
+-{"evmwhssf", VX (4,1095), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"vpmsumh", VX (4,1096), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+-{"evmwlumi", VX (4,1096), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"vminfp", VX (4,1098), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"evmwhumi", VX (4,1100), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"vsro", VX (4,1100), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"vpkudum", VX (4,1102), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+-{"evmwhsmf", VX (4,1103), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evmwssf", VX (4,1107), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"machhwo", XO (4, 44,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"evmwumi", VX (4,1112), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"machhwo.", XO (4, 44,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"evmwsmi", VX (4,1113), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evmwsmf", VX (4,1115), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"nmachhwo", XO (4, 46,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"nmachhwo.", XO (4, 46,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"ps_merge01", XOPS(4,560,0), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
+-{"ps_merge01.", XOPS(4,560,1), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
+-{"evmwhssfa", VX (4,1127), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evmwlumia", VX (4,1128), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evmwhumia", VX (4,1132), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evmwhsmia", VX (4,1133), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evmwssfa", VX (4,1139), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evmwumia", VX (4,1144), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evmwsmia", VX (4,1145), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evmwsmfa", VX (4,1147), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"vsubuwm", VX (4,1152), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"bcdus.", VX (4,1153), VX_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}},
+-{"vavguw", VX (4,1154), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vabsduw", VX (4,1155), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+-{"vmr", VX (4,1156), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VBA}},
+-{"vor", VX (4,1156), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vcmpnew.", VXR(4, 135,1), VXR_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}},
+-{"vpmsumw", VX (4,1160), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+-{"vcmpequw.", VXR(4, 134,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"udi2fcm.", APU(4, 579,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
+-{"udi2fcm", APU(4, 579,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
+-{"machhwsuo", XO (4, 76,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"machhwsuo.", XO (4, 76,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"ps_merge10", XOPS(4,592,0), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
+-{"ps_merge10.", XOPS(4,592,1), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
+-{"vsubudm", VX (4,1216), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+-{"evaddusiaaw", VX (4,1216), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
+-{"bcds.", VX (4,1217), VXPS_MASK, PPCVEC3, PPCNONE, {VD, VA, VB, PS}},
+-{"evaddssiaaw", VX (4,1217), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
+-{"evsubfusiaaw",VX (4,1218), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
+-{"evsubfssiaaw",VX (4,1219), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
+-{"evmra", VX (4,1220), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
+-{"vxor", VX (4,1220), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"evdivws", VX (4,1222), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"vcmpeqfp.", VXR(4, 198,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"udi3fcm.", APU(4, 611,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
+-{"vcmpequd.", VXR(4, 199,1), VXR_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+-{"udi3fcm", APU(4, 611,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
+-{"evdivwu", VX (4,1223), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"vpmsumd", VX (4,1224), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+-{"evaddumiaaw", VX (4,1224), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
+-{"evaddsmiaaw", VX (4,1225), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
+-{"evsubfumiaaw",VX (4,1226), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
+-{"evsubfsmiaaw",VX (4,1227), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
+-{"vpkudus", VX (4,1230), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+-{"machhwso", XO (4, 108,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"machhwso.", XO (4, 108,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"nmachhwso", XO (4, 110,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"nmachhwso.", XO (4, 110,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"ps_merge11", XOPS(4,624,0), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
+-{"ps_merge11.", XOPS(4,624,1), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
+-{"vsubuqm", VX (4,1280), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+-{"evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"bcdtrunc.", VX (4,1281), VXPS_MASK, PPCVEC3, PPCNONE, {VD, VA, VB, PS}},
+-{"evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"vavgsb", VX (4,1282), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"vnot", VX (4,1284), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VBA}},
+-{"vnor", VX (4,1284), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"udi4fcm.", APU(4, 643,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
+-{"udi4fcm", APU(4, 643,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
+-{"vcmpnezb.", VXR(4, 263,1), VXR_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}},
+-{"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"vcipher", VX (4,1288), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+-{"vcipherlast", VX (4,1289), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+-{"evmhesmiaaw", VX (4,1289), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evmhesmfaaw", VX (4,1291), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"vgbbd", VX (4,1292), VXVA_MASK, PPCVEC2, PPCNONE, {VD, VB}},
+-{"evmhoumiaaw", VX (4,1292), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evmhosmiaaw", VX (4,1293), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evmhosmfaaw", VX (4,1295), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"macchwuo", XO (4, 140,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"macchwuo.", XO (4, 140,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"evmhegumiaa", VX (4,1320), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evmhegsmiaa", VX (4,1321), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evmhegsmfaa", VX (4,1323), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evmhogumiaa", VX (4,1324), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evmhogsmiaa", VX (4,1325), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"vsubcuq", VX (4,1344), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+-{"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"bcdutrunc.", VX (4,1345), VX_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}},
+-{"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"vavgsh", VX (4,1346), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vorc", VX (4,1348), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+-{"udi5fcm.", APU(4, 675,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
+-{"udi5fcm", APU(4, 675,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
+-{"vcmpnezh.", VXR(4, 327,1), VXR_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}},
+-{"vncipher", VX (4,1352), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+-{"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"vncipherlast",VX (4,1353), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+-{"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"vbpermq", VX (4,1356), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+-{"vpksdus", VX (4,1358), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+-{"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"macchwo", XO (4, 172,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"macchwo.", XO (4, 172,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"evmwsmiaa", VX (4,1369), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"nmacchwo", XO (4, 174,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"nmacchwo.", XO (4, 174,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"evmheusianw", VX (4,1408), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"vsubcuw", VX (4,1408), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"evmhessianw", VX (4,1409), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"bcdctsq.", VXVA(4,1409,0), VXVA_MASK, PPCVEC3, PPCNONE, {VD, VB}},
+-{"bcdcfsq.", VXVA(4,1409,2), VXVAPS_MASK, PPCVEC3, PPCNONE, {VD, VB, PS}},
+-{"bcdctz.", VXVA(4,1409,4), VXVAPS_MASK, PPCVEC3, PPCNONE, {VD, VB, PS}},
+-{"bcdctn.", VXVA(4,1409,5), VXVA_MASK, PPCVEC3, PPCNONE, {VD, VB}},
+-{"bcdcfz.", VXVA(4,1409,6), VXVAPS_MASK, PPCVEC3, PPCNONE, {VD, VB, PS}},
+-{"bcdcfn.", VXVA(4,1409,7), VXVAPS_MASK, PPCVEC3, PPCNONE, {VD, VB, PS}},
+-{"bcdsetsgn.", VXVA(4,1409,31),VXVAPS_MASK, PPCVEC3, PPCNONE, {VD, VB, PS}},
+-{"vavgsw", VX (4,1410), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"vnand", VX (4,1412), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+-{"evmhousianw", VX (4,1412), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evmhossianw", VX (4,1413), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"udi6fcm.", APU(4, 707,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
+-{"udi6fcm", APU(4, 707,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
+-{"vcmpnezw.", VXR(4, 391,1), VXR_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}},
+-{"evmhossfanw", VX (4,1415), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evmheumianw", VX (4,1416), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evmhesmfanw", VX (4,1419), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evmhoumianw", VX (4,1420), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evmhosmianw", VX (4,1421), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evmhosmfanw", VX (4,1423), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"macchwsuo", XO (4, 204,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"macchwsuo.", XO (4, 204,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"evmhegumian", VX (4,1448), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evmhegsmian", VX (4,1449), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evmhegsmfan", VX (4,1451), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evmhogumian", VX (4,1452), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evmhogsmian", VX (4,1453), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"bcdsr.", VX (4,1473), VXPS_MASK, PPCVEC3, PPCNONE, {VD, VA, VB, PS}},
+-{"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"vsld", VX (4,1476), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+-{"vcmpgefp.", VXR(4, 454,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"udi7fcm.", APU(4, 739,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
+-{"udi7fcm", APU(4, 739,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
+-{"vsbox", VX (4,1480), VXVB_MASK, PPCVEC2, PPCNONE, {VD, VA}},
+-{"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"vbpermd", VX (4,1484), VX_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}},
+-{"vpksdss", VX (4,1486), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+-{"evmwssfan", VX (4,1491), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"macchwso", XO (4, 236,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"evmwumian", VX (4,1496), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"macchwso.", XO (4, 236,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"evmwsmian", VX (4,1497), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"evmwsmfan", VX (4,1499), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+-{"nmacchwso", XO (4, 238,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"nmacchwso.", XO (4, 238,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"vsububs", VX (4,1536), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vclzlsbb", VXVA(4,1538,0), VXVA_MASK, PPCVEC3, PPCNONE, {RT, VB}},
+-{"vctzlsbb", VXVA(4,1538,1), VXVA_MASK, PPCVEC3, PPCNONE, {RT, VB}},
+-{"vnegw", VXVA(4,1538,6), VXVA_MASK, PPCVEC3, PPCNONE, {VD, VB}},
+-{"vnegd", VXVA(4,1538,7), VXVA_MASK, PPCVEC3, PPCNONE, {VD, VB}},
+-{"vprtybw", VXVA(4,1538,8), VXVA_MASK, PPCVEC3, PPCNONE, {VD, VB}},
+-{"vprtybd", VXVA(4,1538,9), VXVA_MASK, PPCVEC3, PPCNONE, {VD, VB}},
+-{"vprtybq", VXVA(4,1538,10),VXVA_MASK, PPCVEC3, PPCNONE, {VD, VB}},
+-{"vextsb2w", VXVA(4,1538,16),VXVA_MASK, PPCVEC3, PPCNONE, {VD, VB}},
+-{"vextsh2w", VXVA(4,1538,17),VXVA_MASK, PPCVEC3, PPCNONE, {VD, VB}},
+-{"vextsb2d", VXVA(4,1538,24),VXVA_MASK, PPCVEC3, PPCNONE, {VD, VB}},
+-{"vextsh2d", VXVA(4,1538,25),VXVA_MASK, PPCVEC3, PPCNONE, {VD, VB}},
+-{"vextsw2d", VXVA(4,1538,26),VXVA_MASK, PPCVEC3, PPCNONE, {VD, VB}},
+-{"vctzb", VXVA(4,1538,28),VXVA_MASK, PPCVEC3, PPCNONE, {VD, VB}},
+-{"vctzh", VXVA(4,1538,29),VXVA_MASK, PPCVEC3, PPCNONE, {VD, VB}},
+-{"vctzw", VXVA(4,1538,30),VXVA_MASK, PPCVEC3, PPCNONE, {VD, VB}},
+-{"vctzd", VXVA(4,1538,31),VXVA_MASK, PPCVEC3, PPCNONE, {VD, VB}},
+-{"mfvscr", VX (4,1540), VXVAVB_MASK, PPCVEC|PPCVLE, PPCNONE, {VD}},
+-{"vcmpgtub.", VXR(4, 518,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
++{"attn", X(0,256), X_MASK, POWER4|PPCA2, PPC476|PPCVLE, {0}},
++{"tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
++{"tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
++{"tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
++{"tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
++{"tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
++{"tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
++{"tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
++{"tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
++{"tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
++{"tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
++{"tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
++{"tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
++{"tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
++{"tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
++{"tdui", OPTO(2,TOU), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
++{"tdi", OP(2), OP_MASK, PPC64, PPCVLE, {TO, RA, SI}},
++
++{"twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
++{"tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
++{"twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
++{"tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
++{"tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
++{"teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
++{"twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
++{"tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
++{"twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
++{"tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
++{"twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
++{"tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
++{"twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
++{"tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
++{"twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
++{"tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
++{"twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
++{"tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
++{"twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
++{"tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
++{"twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
++{"tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
++{"twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
++{"tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
++{"twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
++{"tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
++{"twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
++{"tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
++{"twui", OPTO(3,TOU), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
++{"tui", OPTO(3,TOU), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
++{"twi", OP(3), OP_MASK, PPCCOM, PPCVLE, {TO, RA, SI}},
++{"ti", OP(3), OP_MASK, PWRCOM, PPCVLE, {TO, RA, SI}},
++
++{"ps_cmpu0", X (4, 0), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
++{"vaddubm", VX (4, 0), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vmul10cuq", VX (4, 1), VXVB_MASK, PPCVEC3, 0, {VD, VA}},
++{"vmaxub", VX (4, 2), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vrlb", VX (4, 4), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vcmpequb", VXR(4, 6,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vcmpneb", VXR(4, 7,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
++{"vmuloub", VX (4, 8), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vaddfp", VX (4, 10), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"psq_lx", XW (4, 6,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}},
++{"vmrghb", VX (4, 12), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"psq_stx", XW (4, 7,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},
++{"vpkuhum", VX (4, 14), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"mulhhwu", XRC(4, 8,0), X_MASK, MULHW, 0, {RT, RA, RB}},
++{"mulhhwu.", XRC(4, 8,1), X_MASK, MULHW, 0, {RT, RA, RB}},
++{"ps_sum0", A (4, 10,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
++{"ps_sum0.", A (4, 10,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
++{"ps_sum1", A (4, 11,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
++{"ps_sum1.", A (4, 11,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
++{"ps_muls0", A (4, 12,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
++{"machhwu", XO (4, 12,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"ps_muls0.", A (4, 12,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
++{"machhwu.", XO (4, 12,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"ps_muls1", A (4, 13,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
++{"ps_muls1.", A (4, 13,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
++{"ps_madds0", A (4, 14,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
++{"ps_madds0.", A (4, 14,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
++{"ps_madds1", A (4, 15,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
++{"ps_madds1.", A (4, 15,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
++{"vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
++{"vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
++{"vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
++{"vmsumudm", VXA(4, 35), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}},
++{"ps_div", A (4, 18,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
++{"vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
++{"ps_div.", A (4, 18,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
++{"vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
++{"vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
++{"vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
++{"ps_sub", A (4, 20,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
++{"vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
++{"ps_sub.", A (4, 20,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
++{"vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
++{"ps_add", A (4, 21,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
++{"vsel", VXA(4, 42), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
++{"ps_add.", A (4, 21,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
++{"vperm", VXA(4, 43), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
++{"vsldoi", VXA(4, 44), VXASHB_MASK, PPCVEC, 0, {VD, VA, VB, SHB}},
++{"vpermxor", VXA(4, 45), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
++{"ps_sel", A (4, 23,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
++{"vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, 0, {VD, VA, VC, VB}},
++{"ps_sel.", A (4, 23,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
++{"vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, 0, {VD, VA, VC, VB}},
++{"ps_res", A (4, 24,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
++{"maddhd", VXA(4, 48), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
++{"ps_res.", A (4, 24,1), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
++{"maddhdu", VXA(4, 49), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
++{"ps_mul", A (4, 25,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
++{"ps_mul.", A (4, 25,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
++{"maddld", VXA(4, 51), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
++{"ps_rsqrte", A (4, 26,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
++{"ps_rsqrte.", A (4, 26,1), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
++{"ps_msub", A (4, 28,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
++{"ps_msub.", A (4, 28,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
++{"ps_madd", A (4, 29,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
++{"ps_madd.", A (4, 29,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
++{"vpermr", VXA(4, 59), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}},
++{"ps_nmsub", A (4, 30,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
++{"vaddeuqm", VXA(4, 60), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
++{"ps_nmsub.", A (4, 30,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
++{"vaddecuq", VXA(4, 61), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
++{"ps_nmadd", A (4, 31,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
++{"vsubeuqm", VXA(4, 62), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
++{"ps_nmadd.", A (4, 31,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
++{"vsubecuq", VXA(4, 63), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
++{"ps_cmpo0", X (4, 32), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
++{"vadduhm", VX (4, 64), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vmul10ecuq", VX (4, 65), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
++{"vmaxuh", VX (4, 66), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vrlh", VX (4, 68), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vcmpequh", VXR(4, 70,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vcmpneh", VXR(4, 71,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
++{"vmulouh", VX (4, 72), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vsubfp", VX (4, 74), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"psq_lux", XW (4, 38,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}},
++{"vmrghh", VX (4, 76), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"psq_stux", XW (4, 39,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},
++{"vpkuwum", VX (4, 78), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"ps_neg", XRC(4, 40,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
++{"mulhhw", XRC(4, 40,0), X_MASK, MULHW, 0, {RT, RA, RB}},
++{"ps_neg.", XRC(4, 40,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
++{"mulhhw.", XRC(4, 40,1), X_MASK, MULHW, 0, {RT, RA, RB}},
++{"machhw", XO (4, 44,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"machhw.", XO (4, 44,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"nmachhw", XO (4, 46,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"nmachhw.", XO (4, 46,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"ps_cmpu1", X (4, 64), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
++{"vadduwm", VX (4, 128), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vmaxuw", VX (4, 130), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vrlw", VX (4, 132), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vrlwmi", VX (4, 133), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
++{"vcmpequw", VXR(4, 134,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vcmpnew", VXR(4, 135,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
++{"vmulouw", VX (4, 136), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
++{"vmuluwm", VX (4, 137), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
++{"vmrghw", VX (4, 140), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vpkuhus", VX (4, 142), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"ps_mr", XRC(4, 72,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
++{"ps_mr.", XRC(4, 72,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
++{"machhwsu", XO (4, 76,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"machhwsu.", XO (4, 76,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"ps_cmpo1", X (4, 96), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
++{"vaddudm", VX (4, 192), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
++{"vmaxud", VX (4, 194), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
++{"vrld", VX (4, 196), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
++{"vrldmi", VX (4, 197), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
++{"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vcmpequd", VXR(4, 199,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
++{"vpkuwus", VX (4, 206), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"machhws", XO (4, 108,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"machhws.", XO (4, 108,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"nmachhws", XO (4, 110,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"nmachhws.", XO (4, 110,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"vadduqm", VX (4, 256), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
++{"vmaxsb", VX (4, 258), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vslb", VX (4, 260), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vcmpnezb", VXR(4, 263,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
++{"vmulosb", VX (4, 264), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vrefp", VX (4, 266), VXVA_MASK, PPCVEC, 0, {VD, VB}},
++{"vmrglb", VX (4, 268), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vpkshus", VX (4, 270), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"ps_nabs", XRC(4, 136,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
++{"mulchwu", XRC(4, 136,0), X_MASK, MULHW, 0, {RT, RA, RB}},
++{"ps_nabs.", XRC(4, 136,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
++{"mulchwu.", XRC(4, 136,1), X_MASK, MULHW, 0, {RT, RA, RB}},
++{"macchwu", XO (4, 140,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"macchwu.", XO (4, 140,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"vaddcuq", VX (4, 320), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
++{"vmaxsh", VX (4, 322), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vslh", VX (4, 324), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vcmpnezh", VXR(4, 327,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
++{"vmulosh", VX (4, 328), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vrsqrtefp", VX (4, 330), VXVA_MASK, PPCVEC, 0, {VD, VB}},
++{"vmrglh", VX (4, 332), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vpkswus", VX (4, 334), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"mulchw", XRC(4, 168,0), X_MASK, MULHW, 0, {RT, RA, RB}},
++{"mulchw.", XRC(4, 168,1), X_MASK, MULHW, 0, {RT, RA, RB}},
++{"macchw", XO (4, 172,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"macchw.", XO (4, 172,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"nmacchw", XO (4, 174,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"nmacchw.", XO (4, 174,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"vaddcuw", VX (4, 384), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vmaxsw", VX (4, 386), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vslw", VX (4, 388), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vrlwnm", VX (4, 389), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
++{"vcmpnezw", VXR(4, 391,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
++{"vmulosw", VX (4, 392), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
++{"vexptefp", VX (4, 394), VXVA_MASK, PPCVEC, 0, {VD, VB}},
++{"vmrglw", VX (4, 396), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vpkshss", VX (4, 398), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"macchwsu", XO (4, 204,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"macchwsu.", XO (4, 204,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"vmaxsd", VX (4, 450), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
++{"vsl", VX (4, 452), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vrldnm", VX (4, 453), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
++{"vcmpgefp", VXR(4, 454,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vlogefp", VX (4, 458), VXVA_MASK, PPCVEC, 0, {VD, VB}},
++{"vpkswss", VX (4, 462), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"macchws", XO (4, 236,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"macchws.", XO (4, 236,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"nmacchws", XO (4, 238,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"nmacchws.", XO (4, 238,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"evaddw", VX (4, 512), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"vaddubs", VX (4, 512), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vmul10uq", VX (4, 513), VXVB_MASK, PPCVEC3, 0, {VD, VA}},
++{"evaddiw", VX (4, 514), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}},
++{"vminub", VX (4, 514), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"evsubfw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evsubw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RB, RA}},
++{"vsrb", VX (4, 516), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"evsubifw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, UIMM, RB}},
++{"evsubiw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}},
++{"vcmpgtub", VXR(4, 518,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"evabs", VX (4, 520), VX_MASK, PPCSPE, 0, {RS, RA}},
++{"vmuleub", VX (4, 520), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"evneg", VX (4, 521), VX_MASK, PPCSPE, 0, {RS, RA}},
++{"evextsb", VX (4, 522), VX_MASK, PPCSPE, 0, {RS, RA}},
++{"vrfin", VX (4, 522), VXVA_MASK, PPCVEC, 0, {VD, VB}},
++{"evextsh", VX (4, 523), VX_MASK, PPCSPE, 0, {RS, RA}},
++{"evrndw", VX (4, 524), VX_MASK, PPCSPE, 0, {RS, RA}},
++{"vspltb", VX (4, 524), VXUIMM4_MASK, PPCVEC, 0, {VD, VB, UIMM4}},
++{"vextractub", VX (4, 525), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
++{"evcntlzw", VX (4, 525), VX_MASK, PPCSPE, 0, {RS, RA}},
++{"evcntlsw", VX (4, 526), VX_MASK, PPCSPE, 0, {RS, RA}},
++{"vupkhsb", VX (4, 526), VXVA_MASK, PPCVEC, 0, {VD, VB}},
++{"brinc", VX (4, 527), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"ps_abs", XRC(4, 264,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
++{"ps_abs.", XRC(4, 264,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
++{"evand", VX (4, 529), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evandc", VX (4, 530), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evxor", VX (4, 534), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evmr", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, BBA}},
++{"evor", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evnor", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evnot", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, BBA}},
++{"get", APU(4, 268,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
++{"eveqv", VX (4, 537), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evorc", VX (4, 539), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evnand", VX (4, 542), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evsrwu", VX (4, 544), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evsrws", VX (4, 545), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evsrwiu", VX (4, 546), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
++{"evsrwis", VX (4, 547), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
++{"evslw", VX (4, 548), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evslwi", VX (4, 550), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
++{"evrlw", VX (4, 552), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evsplati", VX (4, 553), VX_MASK, PPCSPE, 0, {RS, SIMM}},
++{"evrlwi", VX (4, 554), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
++{"evsplatfi", VX (4, 555), VX_MASK, PPCSPE, 0, {RS, SIMM}},
++{"evmergehi", VX (4, 556), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evmergelo", VX (4, 557), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evmergehilo", VX (4, 558), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evmergelohi", VX (4, 559), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evcmpgtu", VX (4, 560), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
++{"evcmpgts", VX (4, 561), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
++{"evcmpltu", VX (4, 562), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
++{"evcmplts", VX (4, 563), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
++{"evcmpeq", VX (4, 564), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
++{"cget", APU(4, 284,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
++{"vadduhs", VX (4, 576), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vmul10euq", VX (4, 577), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
++{"vminuh", VX (4, 578), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vsrh", VX (4, 580), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vcmpgtuh", VXR(4, 582,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vmuleuh", VX (4, 584), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vrfiz", VX (4, 586), VXVA_MASK, PPCVEC, 0, {VD, VB}},
++{"vsplth", VX (4, 588), VXUIMM3_MASK, PPCVEC, 0, {VD, VB, UIMM3}},
++{"vextractuh", VX (4, 589), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
++{"vupkhsh", VX (4, 590), VXVA_MASK, PPCVEC, 0, {VD, VB}},
++{"nget", APU(4, 300,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
++{"evsel", EVSEL(4,79), EVSEL_MASK, PPCSPE, 0, {RS, RA, RB, CRFS}},
++{"ncget", APU(4, 316,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
++{"evfsadd", VX (4, 640), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"vadduws", VX (4, 640), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"evfssub", VX (4, 641), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"vminuw", VX (4, 642), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"evfsabs", VX (4, 644), VX_MASK, PPCSPE, 0, {RS, RA}},
++{"vsrw", VX (4, 644), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"evfsnabs", VX (4, 645), VX_MASK, PPCSPE, 0, {RS, RA}},
++{"evfsneg", VX (4, 646), VX_MASK, PPCSPE, 0, {RS, RA}},
++{"vcmpgtuw", VXR(4, 646,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vmuleuw", VX (4, 648), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
++{"evfsmul", VX (4, 648), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evfsdiv", VX (4, 649), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"vrfip", VX (4, 650), VXVA_MASK, PPCVEC, 0, {VD, VB}},
++{"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
++{"vspltw", VX (4, 652), VXUIMM2_MASK, PPCVEC, 0, {VD, VB, UIMM2}},
++{"vextractuw", VX (4, 653), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
++{"evfscmplt", VX (4, 653), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
++{"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
++{"vupklsb", VX (4, 654), VXVA_MASK, PPCVEC, 0, {VD, VB}},
++{"evfscfui", VX (4, 656), VX_MASK, PPCSPE, 0, {RS, RB}},
++{"evfscfsi", VX (4, 657), VX_MASK, PPCSPE, 0, {RS, RB}},
++{"evfscfuf", VX (4, 658), VX_MASK, PPCSPE, 0, {RS, RB}},
++{"evfscfsf", VX (4, 659), VX_MASK, PPCSPE, 0, {RS, RB}},
++{"evfsctui", VX (4, 660), VX_MASK, PPCSPE, 0, {RS, RB}},
++{"evfsctsi", VX (4, 661), VX_MASK, PPCSPE, 0, {RS, RB}},
++{"evfsctuf", VX (4, 662), VX_MASK, PPCSPE, 0, {RS, RB}},
++{"evfsctsf", VX (4, 663), VX_MASK, PPCSPE, 0, {RS, RB}},
++{"evfsctuiz", VX (4, 664), VX_MASK, PPCSPE, 0, {RS, RB}},
++{"put", APU(4, 332,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
++{"evfsctsiz", VX (4, 666), VX_MASK, PPCSPE, 0, {RS, RB}},
++{"evfststgt", VX (4, 668), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
++{"evfststlt", VX (4, 669), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
++{"evfststeq", VX (4, 670), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
++{"cput", APU(4, 348,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
++{"efsadd", VX (4, 704), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
++{"efssub", VX (4, 705), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
++{"vminud", VX (4, 706), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
++{"efsabs", VX (4, 708), VX_MASK, PPCEFS, 0, {RS, RA}},
++{"vsr", VX (4, 708), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"efsnabs", VX (4, 709), VX_MASK, PPCEFS, 0, {RS, RA}},
++{"efsneg", VX (4, 710), VX_MASK, PPCEFS, 0, {RS, RA}},
++{"vcmpgtfp", VXR(4, 710,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vcmpgtud", VXR(4, 711,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
++{"efsmul", VX (4, 712), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
++{"efsdiv", VX (4, 713), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
++{"vrfim", VX (4, 714), VXVA_MASK, PPCVEC, 0, {VD, VB}},
++{"efscmpgt", VX (4, 716), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
++{"vextractd", VX (4, 717), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
++{"efscmplt", VX (4, 717), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
++{"efscmpeq", VX (4, 718), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
++{"vupklsh", VX (4, 718), VXVA_MASK, PPCVEC, 0, {VD, VB}},
++{"efscfd", VX (4, 719), VX_MASK, PPCEFS, 0, {RS, RB}},
++{"efscfui", VX (4, 720), VX_MASK, PPCEFS, 0, {RS, RB}},
++{"efscfsi", VX (4, 721), VX_MASK, PPCEFS, 0, {RS, RB}},
++{"efscfuf", VX (4, 722), VX_MASK, PPCEFS, 0, {RS, RB}},
++{"efscfsf", VX (4, 723), VX_MASK, PPCEFS, 0, {RS, RB}},
++{"efsctui", VX (4, 724), VX_MASK, PPCEFS, 0, {RS, RB}},
++{"efsctsi", VX (4, 725), VX_MASK, PPCEFS, 0, {RS, RB}},
++{"efsctuf", VX (4, 726), VX_MASK, PPCEFS, 0, {RS, RB}},
++{"efsctsf", VX (4, 727), VX_MASK, PPCEFS, 0, {RS, RB}},
++{"efsctuiz", VX (4, 728), VX_MASK, PPCEFS, 0, {RS, RB}},
++{"nput", APU(4, 364,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
++{"efsctsiz", VX (4, 730), VX_MASK, PPCEFS, 0, {RS, RB}},
++{"efststgt", VX (4, 732), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
++{"efststlt", VX (4, 733), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
++{"efststeq", VX (4, 734), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
++{"efdadd", VX (4, 736), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
++{"efdsub", VX (4, 737), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
++{"efdcfuid", VX (4, 738), VX_MASK, PPCEFS, 0, {RS, RB}},
++{"efdcfsid", VX (4, 739), VX_MASK, PPCEFS, 0, {RS, RB}},
++{"efdabs", VX (4, 740), VX_MASK, PPCEFS, 0, {RS, RA}},
++{"efdnabs", VX (4, 741), VX_MASK, PPCEFS, 0, {RS, RA}},
++{"efdneg", VX (4, 742), VX_MASK, PPCEFS, 0, {RS, RA}},
++{"efdmul", VX (4, 744), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
++{"efddiv", VX (4, 745), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
++{"efdctuidz", VX (4, 746), VX_MASK, PPCEFS, 0, {RS, RB}},
++{"efdctsidz", VX (4, 747), VX_MASK, PPCEFS, 0, {RS, RB}},
++{"efdcmpgt", VX (4, 748), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
++{"efdcmplt", VX (4, 749), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
++{"efdcmpeq", VX (4, 750), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
++{"efdcfs", VX (4, 751), VX_MASK, PPCEFS, 0, {RS, RB}},
++{"efdcfui", VX (4, 752), VX_MASK, PPCEFS, 0, {RS, RB}},
++{"efdcfsi", VX (4, 753), VX_MASK, PPCEFS, 0, {RS, RB}},
++{"efdcfuf", VX (4, 754), VX_MASK, PPCEFS, 0, {RS, RB}},
++{"efdcfsf", VX (4, 755), VX_MASK, PPCEFS, 0, {RS, RB}},
++{"efdctui", VX (4, 756), VX_MASK, PPCEFS, 0, {RS, RB}},
++{"efdctsi", VX (4, 757), VX_MASK, PPCEFS, 0, {RS, RB}},
++{"efdctuf", VX (4, 758), VX_MASK, PPCEFS, 0, {RS, RB}},
++{"efdctsf", VX (4, 759), VX_MASK, PPCEFS, 0, {RS, RB}},
++{"efdctuiz", VX (4, 760), VX_MASK, PPCEFS, 0, {RS, RB}},
++{"ncput", APU(4, 380,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
++{"efdctsiz", VX (4, 762), VX_MASK, PPCEFS, 0, {RS, RB}},
++{"efdtstgt", VX (4, 764), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
++{"efdtstlt", VX (4, 765), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
++{"efdtsteq", VX (4, 766), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
++{"evlddx", VX (4, 768), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"vaddsbs", VX (4, 768), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"evldd", VX (4, 769), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
++{"evldwx", VX (4, 770), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"vminsb", VX (4, 770), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"evldw", VX (4, 771), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
++{"evldhx", VX (4, 772), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"vsrab", VX (4, 772), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"evldh", VX (4, 773), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
++{"vcmpgtsb", VXR(4, 774,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"evlhhesplatx",VX (4, 776), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"vmulesb", VX (4, 776), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"evlhhesplat", VX (4, 777), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
++{"vcfux", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
++{"vcuxwfp", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
++{"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"vspltisb", VX (4, 780), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
++{"vinsertb", VX (4, 781), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
++{"evlhhousplat",VX (4, 781), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
++{"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"vpkpx", VX (4, 782), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"evlhhossplat",VX (4, 783), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
++{"mullhwu", XRC(4, 392,0), X_MASK, MULHW, 0, {RT, RA, RB}},
++{"evlwhex", VX (4, 784), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"mullhwu.", XRC(4, 392,1), X_MASK, MULHW, 0, {RT, RA, RB}},
++{"evlwhe", VX (4, 785), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
++{"evlwhoux", VX (4, 788), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evlwhou", VX (4, 789), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
++{"evlwhosx", VX (4, 790), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evlwhos", VX (4, 791), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
++{"maclhwu", XO (4, 396,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"evlwwsplatx", VX (4, 792), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"maclhwu.", XO (4, 396,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"evlwwsplat", VX (4, 793), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
++{"evlwhsplatx", VX (4, 796), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evlwhsplat", VX (4, 797), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
++{"evstddx", VX (4, 800), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evstdd", VX (4, 801), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
++{"evstdwx", VX (4, 802), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evstdw", VX (4, 803), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
++{"evstdhx", VX (4, 804), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evstdh", VX (4, 805), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
++{"evstwhex", VX (4, 816), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evstwhe", VX (4, 817), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
++{"evstwhox", VX (4, 820), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evstwho", VX (4, 821), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
++{"evstwwex", VX (4, 824), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evstwwe", VX (4, 825), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
++{"evstwwox", VX (4, 828), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evstwwo", VX (4, 829), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
++{"vaddshs", VX (4, 832), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"bcdcpsgn.", VX (4, 833), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
++{"vminsh", VX (4, 834), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vsrah", VX (4, 836), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vcmpgtsh", VXR(4, 838,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vmulesh", VX (4, 840), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vcfsx", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
++{"vcsxwfp", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
++{"vspltish", VX (4, 844), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
++{"vinserth", VX (4, 845), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
++{"vupkhpx", VX (4, 846), VXVA_MASK, PPCVEC, 0, {VD, VB}},
++{"mullhw", XRC(4, 424,0), X_MASK, MULHW, 0, {RT, RA, RB}},
++{"mullhw.", XRC(4, 424,1), X_MASK, MULHW, 0, {RT, RA, RB}},
++{"maclhw", XO (4, 428,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"maclhw.", XO (4, 428,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"nmaclhw", XO (4, 430,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"nmaclhw.", XO (4, 430,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"vaddsws", VX (4, 896), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vminsw", VX (4, 898), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vsraw", VX (4, 900), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vcmpgtsw", VXR(4, 902,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vmulesw", VX (4, 904), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
++{"vctuxs", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
++{"vcfpuxws", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
++{"vspltisw", VX (4, 908), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
++{"vinsertw", VX (4, 909), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
++{"maclhwsu", XO (4, 460,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"maclhwsu.", XO (4, 460,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"vminsd", VX (4, 962), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
++{"vsrad", VX (4, 964), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
++{"vcmpbfp", VXR(4, 966,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vcmpgtsd", VXR(4, 967,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
++{"vctsxs", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
++{"vcfpsxws", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
++{"vinsertd", VX (4, 973), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
++{"vupklpx", VX (4, 974), VXVA_MASK, PPCVEC, 0, {VD, VB}},
++{"maclhws", XO (4, 492,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"maclhws.", XO (4, 492,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"nmaclhws", XO (4, 494,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"nmaclhws.", XO (4, 494,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"vsububm", VX (4,1024), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"bcdadd.", VX (4,1025), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}},
++{"vavgub", VX (4,1026), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vabsdub", VX (4,1027), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
++{"evmhessf", VX (4,1027), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"vand", VX (4,1028), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vcmpequb.", VXR(4, 6,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vcmpneb.", VXR(4, 7,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
++{"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
++{"udi0fcm", APU(4, 515,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
++{"evmhossf", VX (4,1031), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"vpmsumb", VX (4,1032), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
++{"evmheumi", VX (4,1032), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evmhesmi", VX (4,1033), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"vmaxfp", VX (4,1034), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"evmhesmf", VX (4,1035), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evmhoumi", VX (4,1036), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"vslo", VX (4,1036), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"evmhosmi", VX (4,1037), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evmhosmf", VX (4,1039), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"machhwuo", XO (4, 12,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"machhwuo.", XO (4, 12,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"ps_merge00", XOPS(4,528,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
++{"ps_merge00.", XOPS(4,528,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
++{"evmhessfa", VX (4,1059), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evmhossfa", VX (4,1063), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evmheumia", VX (4,1064), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evmhesmia", VX (4,1065), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evmhesmfa", VX (4,1067), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evmhoumia", VX (4,1068), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evmhosmia", VX (4,1069), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evmhosmfa", VX (4,1071), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"vsubuhm", VX (4,1088), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"bcdsub.", VX (4,1089), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}},
++{"vavguh", VX (4,1090), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vabsduh", VX (4,1091), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
++{"vandc", VX (4,1092), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vcmpequh.", VXR(4, 70,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"udi1fcm.", APU(4, 547,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
++{"udi1fcm", APU(4, 547,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
++{"vcmpneh.", VXR(4, 71,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
++{"evmwhssf", VX (4,1095), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"vpmsumh", VX (4,1096), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
++{"evmwlumi", VX (4,1096), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"vminfp", VX (4,1098), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"evmwhumi", VX (4,1100), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"vsro", VX (4,1100), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"vpkudum", VX (4,1102), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
++{"evmwhsmf", VX (4,1103), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evmwssf", VX (4,1107), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"machhwo", XO (4, 44,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"evmwumi", VX (4,1112), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"machhwo.", XO (4, 44,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"evmwsmi", VX (4,1113), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evmwsmf", VX (4,1115), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"nmachhwo", XO (4, 46,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"nmachhwo.", XO (4, 46,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"ps_merge01", XOPS(4,560,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
++{"ps_merge01.", XOPS(4,560,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
++{"evmwhssfa", VX (4,1127), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evmwlumia", VX (4,1128), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evmwhumia", VX (4,1132), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evmwhsmia", VX (4,1133), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evmwssfa", VX (4,1139), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evmwumia", VX (4,1144), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evmwsmia", VX (4,1145), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evmwsmfa", VX (4,1147), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"vsubuwm", VX (4,1152), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"bcdus.", VX (4,1153), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
++{"vavguw", VX (4,1154), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vabsduw", VX (4,1155), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
++{"vmr", VX (4,1156), VX_MASK, PPCVEC, 0, {VD, VA, VBA}},
++{"vor", VX (4,1156), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vcmpnew.", VXR(4, 135,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
++{"vpmsumw", VX (4,1160), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
++{"vcmpequw.", VXR(4, 134,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"udi2fcm.", APU(4, 579,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
++{"udi2fcm", APU(4, 579,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
++{"machhwsuo", XO (4, 76,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"machhwsuo.", XO (4, 76,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"ps_merge10", XOPS(4,592,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
++{"ps_merge10.", XOPS(4,592,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
++{"vsubudm", VX (4,1216), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
++{"evaddusiaaw", VX (4,1216), VX_MASK, PPCSPE, 0, {RS, RA}},
++{"bcds.", VX (4,1217), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
++{"evaddssiaaw", VX (4,1217), VX_MASK, PPCSPE, 0, {RS, RA}},
++{"evsubfusiaaw",VX (4,1218), VX_MASK, PPCSPE, 0, {RS, RA}},
++{"evsubfssiaaw",VX (4,1219), VX_MASK, PPCSPE, 0, {RS, RA}},
++{"evmra", VX (4,1220), VX_MASK, PPCSPE, 0, {RS, RA}},
++{"vxor", VX (4,1220), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"evdivws", VX (4,1222), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"vcmpeqfp.", VXR(4, 198,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"udi3fcm.", APU(4, 611,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
++{"vcmpequd.", VXR(4, 199,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
++{"udi3fcm", APU(4, 611,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
++{"evdivwu", VX (4,1223), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"vpmsumd", VX (4,1224), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
++{"evaddumiaaw", VX (4,1224), VX_MASK, PPCSPE, 0, {RS, RA}},
++{"evaddsmiaaw", VX (4,1225), VX_MASK, PPCSPE, 0, {RS, RA}},
++{"evsubfumiaaw",VX (4,1226), VX_MASK, PPCSPE, 0, {RS, RA}},
++{"evsubfsmiaaw",VX (4,1227), VX_MASK, PPCSPE, 0, {RS, RA}},
++{"vpkudus", VX (4,1230), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
++{"machhwso", XO (4, 108,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"machhwso.", XO (4, 108,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"nmachhwso", XO (4, 110,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"nmachhwso.", XO (4, 110,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"ps_merge11", XOPS(4,624,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
++{"ps_merge11.", XOPS(4,624,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
++{"vsubuqm", VX (4,1280), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
++{"evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"bcdtrunc.", VX (4,1281), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
++{"evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"vavgsb", VX (4,1282), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"vnot", VX (4,1284), VX_MASK, PPCVEC, 0, {VD, VA, VBA}},
++{"vnor", VX (4,1284), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"udi4fcm.", APU(4, 643,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
++{"udi4fcm", APU(4, 643,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
++{"vcmpnezb.", VXR(4, 263,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
++{"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"vcipher", VX (4,1288), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
++{"vcipherlast", VX (4,1289), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
++{"evmhesmiaaw", VX (4,1289), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evmhesmfaaw", VX (4,1291), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"vgbbd", VX (4,1292), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
++{"evmhoumiaaw", VX (4,1292), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evmhosmiaaw", VX (4,1293), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evmhosmfaaw", VX (4,1295), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"macchwuo", XO (4, 140,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"macchwuo.", XO (4, 140,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"evmhegumiaa", VX (4,1320), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evmhegsmiaa", VX (4,1321), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evmhegsmfaa", VX (4,1323), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evmhogumiaa", VX (4,1324), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evmhogsmiaa", VX (4,1325), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"vsubcuq", VX (4,1344), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
++{"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"bcdutrunc.", VX (4,1345), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
++{"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"vavgsh", VX (4,1346), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vorc", VX (4,1348), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
++{"udi5fcm.", APU(4, 675,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
++{"udi5fcm", APU(4, 675,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
++{"vcmpnezh.", VXR(4, 327,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
++{"vncipher", VX (4,1352), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
++{"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"vncipherlast",VX (4,1353), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
++{"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"vbpermq", VX (4,1356), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
++{"vpksdus", VX (4,1358), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
++{"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"macchwo", XO (4, 172,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"macchwo.", XO (4, 172,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"evmwsmiaa", VX (4,1369), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"nmacchwo", XO (4, 174,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"nmacchwo.", XO (4, 174,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"evmheusianw", VX (4,1408), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"vsubcuw", VX (4,1408), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"evmhessianw", VX (4,1409), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"bcdctsq.", VXVA(4,1409,0), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
++{"bcdcfsq.", VXVA(4,1409,2), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
++{"bcdctz.", VXVA(4,1409,4), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
++{"bcdctn.", VXVA(4,1409,5), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
++{"bcdcfz.", VXVA(4,1409,6), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
++{"bcdcfn.", VXVA(4,1409,7), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
++{"bcdsetsgn.", VXVA(4,1409,31), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
++{"vavgsw", VX (4,1410), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"vnand", VX (4,1412), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
++{"evmhousianw", VX (4,1412), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evmhossianw", VX (4,1413), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"udi6fcm.", APU(4, 707,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
++{"udi6fcm", APU(4, 707,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
++{"vcmpnezw.", VXR(4, 391,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
++{"evmhossfanw", VX (4,1415), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evmheumianw", VX (4,1416), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evmhesmfanw", VX (4,1419), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evmhoumianw", VX (4,1420), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evmhosmianw", VX (4,1421), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evmhosmfanw", VX (4,1423), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"macchwsuo", XO (4, 204,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"macchwsuo.", XO (4, 204,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"evmhegumian", VX (4,1448), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evmhegsmian", VX (4,1449), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evmhegsmfan", VX (4,1451), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evmhogumian", VX (4,1452), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evmhogsmian", VX (4,1453), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"bcdsr.", VX (4,1473), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
++{"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"vsld", VX (4,1476), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
++{"vcmpgefp.", VXR(4, 454,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"udi7fcm.", APU(4, 739,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
++{"udi7fcm", APU(4, 739,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
++{"vsbox", VX (4,1480), VXVB_MASK, PPCVEC2, 0, {VD, VA}},
++{"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"vbpermd", VX (4,1484), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
++{"vpksdss", VX (4,1486), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
++{"evmwssfan", VX (4,1491), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"macchwso", XO (4, 236,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"evmwumian", VX (4,1496), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"macchwso.", XO (4, 236,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"evmwsmian", VX (4,1497), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"evmwsmfan", VX (4,1499), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
++{"nmacchwso", XO (4, 238,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"nmacchwso.", XO (4, 238,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"vsububs", VX (4,1536), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vclzlsbb", VXVA(4,1538,0), VXVA_MASK, PPCVEC3, 0, {RT, VB}},
++{"vctzlsbb", VXVA(4,1538,1), VXVA_MASK, PPCVEC3, 0, {RT, VB}},
++{"vnegw", VXVA(4,1538,6), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
++{"vnegd", VXVA(4,1538,7), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
++{"vprtybw", VXVA(4,1538,8), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
++{"vprtybd", VXVA(4,1538,9), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
++{"vprtybq", VXVA(4,1538,10), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
++{"vextsb2w", VXVA(4,1538,16), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
++{"vextsh2w", VXVA(4,1538,17), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
++{"vextsb2d", VXVA(4,1538,24), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
++{"vextsh2d", VXVA(4,1538,25), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
++{"vextsw2d", VXVA(4,1538,26), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
++{"vctzb", VXVA(4,1538,28), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
++{"vctzh", VXVA(4,1538,29), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
++{"vctzw", VXVA(4,1538,30), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
++{"vctzd", VXVA(4,1538,31), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
++{"mfvscr", VX (4,1540), VXVAVB_MASK, PPCVEC, 0, {VD}},
++{"vcmpgtub.", VXR(4, 518,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
+ {"udi8fcm.", APU(4, 771,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
+ {"udi8fcm", APU(4, 771,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
+-{"vsum4ubs", VX (4,1544), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vextublx", VX (4,1549), VX_MASK, PPCVEC3, PPCNONE, {RT, RA, VB}},
+-{"vsubuhs", VX (4,1600), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"mtvscr", VX (4,1604), VXVDVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VB}},
+-{"vcmpgtuh.", VXR(4, 582,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vsum4shs", VX (4,1608), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
++{"vsum4ubs", VX (4,1544), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vextublx", VX (4,1549), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
++{"vsubuhs", VX (4,1600), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"mtvscr", VX (4,1604), VXVDVA_MASK, PPCVEC, 0, {VB}},
++{"vcmpgtuh.", VXR(4, 582,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vsum4shs", VX (4,1608), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
+ {"udi9fcm.", APU(4, 804,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
+ {"udi9fcm", APU(4, 804,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
+-{"vextuhlx", VX (4,1613), VX_MASK, PPCVEC3, PPCNONE, {RT, RA, VB}},
+-{"vupkhsw", VX (4,1614), VXVA_MASK, PPCVEC2, PPCNONE, {VD, VB}},
+-{"vsubuws", VX (4,1664), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vshasigmaw", VX (4,1666), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, ST, SIX}},
+-{"veqv", VX (4,1668), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+-{"vcmpgtuw.", VXR(4, 646,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
++{"vextuhlx", VX (4,1613), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
++{"vupkhsw", VX (4,1614), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
++{"vsubuws", VX (4,1664), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vshasigmaw", VX (4,1666), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}},
++{"veqv", VX (4,1668), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
++{"vcmpgtuw.", VXR(4, 646,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
+ {"udi10fcm.", APU(4, 835,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
+ {"udi10fcm", APU(4, 835,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
+-{"vsum2sws", VX (4,1672), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vmrgow", VX (4,1676), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+-{"vextuwlx", VX (4,1677), VX_MASK, PPCVEC3, PPCNONE, {RT, RA, VB}},
+-{"vshasigmad", VX (4,1730), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, ST, SIX}},
+-{"vsrd", VX (4,1732), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+-{"vcmpgtfp.", VXR(4, 710,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
++{"vsum2sws", VX (4,1672), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vmrgow", VX (4,1676), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
++{"vextuwlx", VX (4,1677), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
++{"vshasigmad", VX (4,1730), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}},
++{"vsrd", VX (4,1732), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
++{"vcmpgtfp.", VXR(4, 710,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
+ {"udi11fcm.", APU(4, 867,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
+-{"vcmpgtud.", VXR(4, 711,1), VXR_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
++{"vcmpgtud.", VXR(4, 711,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
+ {"udi11fcm", APU(4, 867,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
+-{"vupklsw", VX (4,1742), VXVA_MASK, PPCVEC2, PPCNONE, {VD, VB}},
+-{"vsubsbs", VX (4,1792), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vclzb", VX (4,1794), VXVA_MASK, PPCVEC2, PPCNONE, {VD, VB}},
+-{"vpopcntb", VX (4,1795), VXVA_MASK, PPCVEC2, PPCNONE, {VD, VB}},
+-{"vsrv", VX (4,1796), VX_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}},
+-{"vcmpgtsb.", VXR(4, 774,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
++{"vupklsw", VX (4,1742), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
++{"vsubsbs", VX (4,1792), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vclzb", VX (4,1794), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
++{"vpopcntb", VX (4,1795), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
++{"vsrv", VX (4,1796), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
++{"vcmpgtsb.", VXR(4, 774,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
+ {"udi12fcm.", APU(4, 899,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
+ {"udi12fcm", APU(4, 899,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
+-{"vsum4sbs", VX (4,1800), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vextubrx", VX (4,1805), VX_MASK, PPCVEC3, PPCNONE, {RT, RA, VB}},
+-{"maclhwuo", XO (4, 396,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"maclhwuo.", XO (4, 396,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"vsubshs", VX (4,1856), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vclzh", VX (4,1858), VXVA_MASK, PPCVEC2, PPCNONE, {VD, VB}},
+-{"vpopcnth", VX (4,1859), VXVA_MASK, PPCVEC2, PPCNONE, {VD, VB}},
+-{"vslv", VX (4,1860), VX_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}},
+-{"vcmpgtsh.", VXR(4, 838,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vextuhrx", VX (4,1869), VX_MASK, PPCVEC3, PPCNONE, {RT, RA, VB}},
++{"vsum4sbs", VX (4,1800), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vextubrx", VX (4,1805), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
++{"maclhwuo", XO (4, 396,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"maclhwuo.", XO (4, 396,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"vsubshs", VX (4,1856), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vclzh", VX (4,1858), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
++{"vpopcnth", VX (4,1859), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
++{"vslv", VX (4,1860), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
++{"vcmpgtsh.", VXR(4, 838,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vextuhrx", VX (4,1869), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
+ {"udi13fcm.", APU(4, 931,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
+ {"udi13fcm", APU(4, 931,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
+-{"maclhwo", XO (4, 428,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"maclhwo.", XO (4, 428,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"nmaclhwo", XO (4, 430,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"nmaclhwo.", XO (4, 430,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"vsubsws", VX (4,1920), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vclzw", VX (4,1922), VXVA_MASK, PPCVEC2, PPCNONE, {VD, VB}},
+-{"vpopcntw", VX (4,1923), VXVA_MASK, PPCVEC2, PPCNONE, {VD, VB}},
+-{"vcmpgtsw.", VXR(4, 902,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
++{"maclhwo", XO (4, 428,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"maclhwo.", XO (4, 428,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"nmaclhwo", XO (4, 430,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"nmaclhwo.", XO (4, 430,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"vsubsws", VX (4,1920), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vclzw", VX (4,1922), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
++{"vpopcntw", VX (4,1923), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
++{"vcmpgtsw.", VXR(4, 902,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
+ {"udi14fcm.", APU(4, 963,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
+ {"udi14fcm", APU(4, 963,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
+-{"vsumsws", VX (4,1928), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+-{"vmrgew", VX (4,1932), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+-{"vextuwrx", VX (4,1933), VX_MASK, PPCVEC3, PPCNONE, {RT, RA, VB}},
+-{"maclhwsuo", XO (4, 460,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"maclhwsuo.", XO (4, 460,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"vclzd", VX (4,1986), VXVA_MASK, PPCVEC2, PPCNONE, {VD, VB}},
+-{"vpopcntd", VX (4,1987), VXVA_MASK, PPCVEC2, PPCNONE, {VD, VB}},
+-{"vcmpbfp.", VXR(4, 966,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
++{"vsumsws", VX (4,1928), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
++{"vmrgew", VX (4,1932), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
++{"vextuwrx", VX (4,1933), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
++{"maclhwsuo", XO (4, 460,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"maclhwsuo.", XO (4, 460,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"vclzd", VX (4,1986), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
++{"vpopcntd", VX (4,1987), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
++{"vcmpbfp.", VXR(4, 966,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
+ {"udi15fcm.", APU(4, 995,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
+-{"vcmpgtsd.", VXR(4, 967,1), VXR_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
++{"vcmpgtsd.", VXR(4, 967,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
+ {"udi15fcm", APU(4, 995,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
+-{"maclhwso", XO (4, 492,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"maclhwso.", XO (4, 492,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"nmaclhwso", XO (4, 494,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"nmaclhwso.", XO (4, 494,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"dcbz_l", X (4,1014), XRT_MASK, PPCPS, PPCNONE, {RA, RB}},
+-
+-{"mulli", OP(7), OP_MASK, PPCCOM, PPCNONE, {RT, RA, SI}},
+-{"muli", OP(7), OP_MASK, PWRCOM, PPCNONE, {RT, RA, SI}},
+-
+-{"subfic", OP(8), OP_MASK, PPCCOM, PPCNONE, {RT, RA, SI}},
+-{"sfi", OP(8), OP_MASK, PWRCOM, PPCNONE, {RT, RA, SI}},
+-
+-{"dozi", OP(9), OP_MASK, M601, PPCNONE, {RT, RA, SI}},
+-
+-{"cmplwi", OPL(10,0), OPL_MASK, PPCCOM, PPCNONE, {OBF, RA, UISIGNOPT}},
+-{"cmpldi", OPL(10,1), OPL_MASK, PPC64, PPCNONE, {OBF, RA, UISIGNOPT}},
+-{"cmpli", OP(10), OP_MASK, PPC, PPCNONE, {BF, L, RA, UISIGNOPT}},
+-{"cmpli", OP(10), OP_MASK, PWRCOM, PPC, {BF, RA, UISIGNOPT}},
+-
+-{"cmpwi", OPL(11,0), OPL_MASK, PPCCOM, PPCNONE, {OBF, RA, SI}},
+-{"cmpdi", OPL(11,1), OPL_MASK, PPC64, PPCNONE, {OBF, RA, SI}},
+-{"cmpi", OP(11), OP_MASK, PPC, PPCNONE, {BF, L, RA, SI}},
+-{"cmpi", OP(11), OP_MASK, PWRCOM, PPC, {BF, RA, SI}},
+-
+-{"addic", OP(12), OP_MASK, PPCCOM, PPCNONE, {RT, RA, SI}},
+-{"ai", OP(12), OP_MASK, PWRCOM, PPCNONE, {RT, RA, SI}},
+-{"subic", OP(12), OP_MASK, PPCCOM, PPCNONE, {RT, RA, NSI}},
+-
+-{"addic.", OP(13), OP_MASK, PPCCOM, PPCNONE, {RT, RA, SI}},
+-{"ai.", OP(13), OP_MASK, PWRCOM, PPCNONE, {RT, RA, SI}},
+-{"subic.", OP(13), OP_MASK, PPCCOM, PPCNONE, {RT, RA, NSI}},
+-
+-{"li", OP(14), DRA_MASK, PPCCOM, PPCNONE, {RT, SI}},
+-{"lil", OP(14), DRA_MASK, PWRCOM, PPCNONE, {RT, SI}},
+-{"addi", OP(14), OP_MASK, PPCCOM, PPCNONE, {RT, RA0, SI}},
+-{"cal", OP(14), OP_MASK, PWRCOM, PPCNONE, {RT, D, RA0}},
+-{"subi", OP(14), OP_MASK, PPCCOM, PPCNONE, {RT, RA0, NSI}},
+-{"la", OP(14), OP_MASK, PPCCOM, PPCNONE, {RT, D, RA0}},
+-
+-{"lis", OP(15), DRA_MASK, PPCCOM, PPCNONE, {RT, SISIGNOPT}},
+-{"liu", OP(15), DRA_MASK, PWRCOM, PPCNONE, {RT, SISIGNOPT}},
+-{"addis", OP(15), OP_MASK, PPCCOM, PPCNONE, {RT, RA0, SISIGNOPT}},
+-{"cau", OP(15), OP_MASK, PWRCOM, PPCNONE, {RT, RA0, SISIGNOPT}},
+-{"subis", OP(15), OP_MASK, PPCCOM, PPCNONE, {RT, RA0, NSISIGNOPT}},
+-
+-{"bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDM}},
+-{"bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDP}},
+-{"bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BD}},
+-{"bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, PPCNONE, {BD}},
+-{"bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDM}},
+-{"bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDP}},
+-{"bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BD}},
+-{"bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, PPCNONE, {BD}},
+-{"bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDMA}},
+-{"bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDPA}},
+-{"bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDA}},
+-{"bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, PPCNONE, {BDA}},
+-{"bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDMA}},
+-{"bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDPA}},
+-{"bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDA}},
+-{"bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, PPCNONE, {BDA}},
+-{"bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDM}},
+-{"bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDP}},
+-{"bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, PPCNONE, {BD}},
+-{"bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDM}},
+-{"bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDP}},
+-{"bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, PPCNONE, {BD}},
+-{"bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDMA}},
+-{"bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDPA}},
+-{"bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, PPCNONE, {BDA}},
+-{"bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDMA}},
+-{"bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDPA}},
+-{"bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, PPCNONE, {BDA}},
+-
+-{"bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
+-{"bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
+-{"bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
+-{"bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
+-{"bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
+-{"bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
+-{"bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
+-{"bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
+-{"bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
+-{"bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
+-{"bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
+-{"bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
+-{"bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
+-{"bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
+-{"bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
+-{"bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
+-{"bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
+-{"bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
+-{"bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
+-{"bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
+-{"bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
+-{"bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
+-{"bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
+-{"bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
+-{"ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
+-{"ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
+-{"ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
+-{"bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
+-{"bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
+-{"bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
+-{"blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
+-{"blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
+-{"blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
+-{"bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
+-{"bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
+-{"bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
+-{"blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
+-{"blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
+-{"blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
+-{"bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
+-{"bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
+-{"bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
+-{"blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
+-{"blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
+-{"blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
+-{"bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
+-{"bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
+-{"bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
+-{"bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
+-{"bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
+-{"bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
+-{"bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
+-{"bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
+-{"bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
+-{"bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
+-{"bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
+-{"bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
+-{"bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
+-{"bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
+-{"bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
+-{"bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
+-{"bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
+-{"bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
+-{"bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
+-{"bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
+-{"bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BD}},
+-{"bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
+-{"bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
+-{"bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
+-{"bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
+-{"bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
+-{"bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BD}},
+-{"bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
+-{"bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
+-{"bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
+-{"bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
+-{"bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
+-{"bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDA}},
+-{"bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
+-{"bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
+-{"bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
+-{"bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
+-{"bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
+-{"bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDA}},
+-
+-{"blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
+-{"blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
+-{"blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
+-{"bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
+-{"bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
+-{"bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
+-{"blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
+-{"blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
+-{"blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
+-{"bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
+-{"bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
+-{"bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
+-{"bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
+-{"bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
+-{"bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
+-{"bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
+-{"bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
+-{"bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
+-{"bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
+-{"bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
+-{"bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
+-{"bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
+-{"bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
+-{"bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
+-{"beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
+-{"beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
+-{"beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
+-{"beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
+-{"beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
+-{"beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
+-{"beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
+-{"beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
+-{"beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
+-{"beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
+-{"beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
+-{"beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
+-{"bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
+-{"bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
+-{"bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
+-{"bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
+-{"bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
+-{"bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BD}},
+-{"bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
+-{"bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
+-{"bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
+-{"bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
+-{"bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
+-{"bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BD}},
+-{"bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
+-{"bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
+-{"bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
+-{"buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
+-{"buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
+-{"buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDA}},
+-{"bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
+-{"bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
+-{"bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
+-{"bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
+-{"bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
+-{"bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDA}},
+-
+-{"bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDM}},
+-{"bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDP}},
+-{"bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}},
+-{"bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDM}},
+-{"bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDP}},
+-{"bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}},
+-{"bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDMA}},
+-{"bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDPA}},
+-{"bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}},
+-{"bdnzfla-", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDMA}},
+-{"bdnzfla+", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDPA}},
+-{"bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}},
+-{"bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDM}},
+-{"bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDP}},
+-{"bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}},
+-{"bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDM}},
+-{"bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDP}},
+-{"bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}},
+-{"bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDMA}},
+-{"bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDPA}},
+-{"bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}},
+-{"bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDMA}},
+-{"bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDPA}},
+-{"bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}},
+-
+-{"bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDM}},
+-{"bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDP}},
+-{"bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BD}},
+-{"bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BD}},
+-{"bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDM}},
+-{"bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDP}},
+-{"bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BD}},
+-{"bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BD}},
+-{"bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDMA}},
+-{"bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDPA}},
+-{"bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDA}},
+-{"bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BDA}},
+-{"bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDMA}},
+-{"bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDPA}},
+-{"bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDA}},
+-{"bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BDA}},
+-
+-{"bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDM}},
+-{"bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDP}},
+-{"bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}},
+-{"bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDM}},
+-{"bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDP}},
+-{"bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}},
+-{"bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDMA}},
+-{"bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDPA}},
+-{"bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}},
+-{"bdnztla-", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDMA}},
+-{"bdnztla+", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDPA}},
+-{"bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}},
+-{"bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDM}},
+-{"bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDP}},
+-{"bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}},
+-{"bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDM}},
+-{"bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDP}},
+-{"bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}},
+-{"bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDMA}},
+-{"bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDPA}},
+-{"bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}},
+-{"bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDMA}},
+-{"bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDPA}},
+-{"bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}},
+-
+-{"bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDM}},
+-{"bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDP}},
+-{"bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BD}},
+-{"bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BD}},
+-{"btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDM}},
+-{"btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDP}},
+-{"btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BD}},
+-{"bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BD}},
+-{"bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDMA}},
+-{"bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDPA}},
+-{"bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDA}},
+-{"bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BDA}},
+-{"btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDMA}},
+-{"btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDPA}},
+-{"btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDA}},
+-{"bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BDA}},
+-
+-{"bc-", B(16,0,0), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDM}},
+-{"bc+", B(16,0,0), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDP}},
+-{"bc", B(16,0,0), B_MASK, COM, PPCNONE, {BO, BI, BD}},
+-{"bcl-", B(16,0,1), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDM}},
+-{"bcl+", B(16,0,1), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDP}},
+-{"bcl", B(16,0,1), B_MASK, COM, PPCNONE, {BO, BI, BD}},
+-{"bca-", B(16,1,0), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDMA}},
+-{"bca+", B(16,1,0), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDPA}},
+-{"bca", B(16,1,0), B_MASK, COM, PPCNONE, {BO, BI, BDA}},
+-{"bcla-", B(16,1,1), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDMA}},
+-{"bcla+", B(16,1,1), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDPA}},
+-{"bcla", B(16,1,1), B_MASK, COM, PPCNONE, {BO, BI, BDA}},
+-
+-{"svc", SC(17,0,0), SC_MASK, POWER, PPCNONE, {SVC_LEV, FL1, FL2}},
+-{"svcl", SC(17,0,1), SC_MASK, POWER, PPCNONE, {SVC_LEV, FL1, FL2}},
+-{"sc", SC(17,1,0), SC_MASK, PPC, PPCNONE, {LEV}},
+-{"svca", SC(17,1,0), SC_MASK, PWRCOM, PPCNONE, {SV}},
+-{"svcla", SC(17,1,1), SC_MASK, POWER, PPCNONE, {SV}},
+-
+-{"b", B(18,0,0), B_MASK, COM, PPCNONE, {LI}},
+-{"bl", B(18,0,1), B_MASK, COM, PPCNONE, {LI}},
+-{"ba", B(18,1,0), B_MASK, COM, PPCNONE, {LIA}},
+-{"bla", B(18,1,1), B_MASK, COM, PPCNONE, {LIA}},
+-
+-{"mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, PPCNONE, {BF, BFA}},
+-
+-{"addpcis", DX(19,2), DX_MASK, POWER9, PPCNONE, {RT, DXD}},
+-{"subpcis", DX(19,2), DX_MASK, POWER9, PPCNONE, {RT, NDXD}},
+-
+-{"bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}},
+-{"bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2, {0}},
+-{"bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}},
+-{"bdnzlrl-", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2, {0}},
+-{"bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2, {0}},
+-{"bdnzlrl+", XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2, {0}},
+-{"bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}},
+-{"bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2, {0}},
+-{"bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}},
+-{"bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2, {0}},
+-{"bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2, {0}},
+-{"bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2, {0}},
+-{"blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}},
+-{"br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, PPCNONE, {0}},
+-{"blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}},
+-{"brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, PPCNONE, {0}},
+-{"bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, ISA_V2, PPCNONE, {0}},
+-{"bdnzlrl-", XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, ISA_V2, PPCNONE, {0}},
+-{"bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, ISA_V2, PPCNONE, {0}},
+-{"bdnzlrl+", XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, ISA_V2, PPCNONE, {0}},
+-{"bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, ISA_V2, PPCNONE, {0}},
+-{"bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, ISA_V2, PPCNONE, {0}},
+-{"bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, ISA_V2, PPCNONE, {0}},
+-{"bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, ISA_V2, PPCNONE, {0}},
+-
+-{"bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
+-{"bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
+-{"bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
+-{"bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
+-{"bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
+-{"bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
+-{"bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
+-{"bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
+-{"blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
+-{"blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
+-{"bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
+-{"bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
+-{"blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
+-{"blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
+-{"bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
+-{"bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
+-{"bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
+-{"bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
+-{"bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
+-{"bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
+-{"bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
+-{"bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
+-{"bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
+-{"bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
+-{"bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
+-{"bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
+-{"bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
+-{"bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
+-{"bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
+-{"bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
+-{"bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
+-{"bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
+-{"bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
+-{"bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
+-{"beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
+-{"beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
+-{"beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
+-{"beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
+-{"bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
+-{"bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
+-{"bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
+-{"bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
+-{"bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
+-{"bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
+-{"bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-
+-{"bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
+-{"bdnzflr-", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
+-{"bdnzflrl", XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
+-{"bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
+-{"bdnzflr+", XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
+-{"bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
+-{"bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
+-{"bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
+-{"bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
+-{"bdzflrl-", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
+-{"bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
+-{"bdzflrl+", XLO(19,BODZFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
+-{"bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
+-{"bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
+-{"bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, PPCNONE, {BI}},
+-{"bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
+-{"bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
+-{"bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, PPCNONE, {BI}},
+-{"bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
+-{"bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
+-{"bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
+-{"bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
+-{"bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
+-{"bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
+-{"bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
+-{"bdnztlr-", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
+-{"bdnztlrl", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
+-{"bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
+-{"bdnztlr+", XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
+-{"bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
+-{"bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
+-{"bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
+-{"bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
+-{"bdztlrl-", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
+-{"bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
+-{"bdztlrl+", XLO(19,BODZTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
+-{"btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
+-{"btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
+-{"bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, PPCNONE, {BI}},
+-{"btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
+-{"btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
+-{"bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, PPCNONE, {BI}},
+-{"btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
+-{"btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
+-{"btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
+-{"btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
+-{"btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
+-{"btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
+-
+-{"bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}},
+-{"bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}},
+-{"bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}},
+-{"bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}},
+-{"bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, PPCNONE, {BO, BI, BH}},
+-{"bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, PPCNONE, {BO, BI}},
+-{"bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, PPCNONE, {BO, BI, BH}},
+-{"bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, PPCNONE, {BO, BI}},
+-
+-{"rfid", XL(19,18), 0xffffffff, PPC64, PPCNONE, {0}},
+-
+-{"crnot", XL(19,33), XL_MASK, PPCCOM, PPCNONE, {BT, BA, BBA}},
+-{"crnor", XL(19,33), XL_MASK, COM, PPCNONE, {BT, BA, BB}},
+-{"rfmci", X(19,38), 0xffffffff, PPCRFMCI|PPCA2|PPC476, PPCNONE, {0}},
+-
+-{"rfdi", XL(19,39), 0xffffffff, E500MC, PPCNONE, {0}},
+-{"rfi", XL(19,50), 0xffffffff, COM, PPCNONE, {0}},
+-{"rfci", XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300|PPCA2|PPC476, PPCNONE, {0}},
+-
+-{"rfsvc", XL(19,82), 0xffffffff, POWER, PPCNONE, {0}},
+-
+-{"rfgi", XL(19,102), 0xffffffff, E500MC|PPCA2, PPCNONE, {0}},
+-
+-{"crandc", XL(19,129), XL_MASK, COM, PPCNONE, {BT, BA, BB}},
+-
+-{"rfebb", XL(19,146), XLS_MASK, POWER8, PPCNONE, {SXL}},
+-
+-{"isync", XL(19,150), 0xffffffff, PPCCOM, PPCNONE, {0}},
+-{"ics", XL(19,150), 0xffffffff, PWRCOM, PPCNONE, {0}},
+-
+-{"crclr", XL(19,193), XL_MASK, PPCCOM, PPCNONE, {BT, BAT, BBA}},
+-{"crxor", XL(19,193), XL_MASK, COM, PPCNONE, {BT, BA, BB}},
+-
+-{"dnh", X(19,198), X_MASK, E500MC, PPCNONE, {DUI, DUIS}},
+-
+-{"crnand", XL(19,225), XL_MASK, COM, PPCNONE, {BT, BA, BB}},
+-
+-{"crand", XL(19,257), XL_MASK, COM, PPCNONE, {BT, BA, BB}},
+-
+-{"hrfid", XL(19,274), 0xffffffff, POWER5|CELL, PPC476, {0}},
+-
+-{"crset", XL(19,289), XL_MASK, PPCCOM, PPCNONE, {BT, BAT, BBA}},
+-{"creqv", XL(19,289), XL_MASK, COM, PPCNONE, {BT, BA, BB}},
+-
+-{"urfid", XL(19,306), 0xffffffff, POWER9, PPCNONE, {0}},
+-{"stop", XL(19,370), 0xffffffff, POWER9, PPCNONE, {0}},
+-
+-{"doze", XL(19,402), 0xffffffff, POWER6, POWER9, {0}},
+-
+-{"crorc", XL(19,417), XL_MASK, COM, PPCNONE, {BT, BA, BB}},
+-
+-{"nap", XL(19,434), 0xffffffff, POWER6, POWER9, {0}},
+-
+-{"crmove", XL(19,449), XL_MASK, PPCCOM, PPCNONE, {BT, BA, BBA}},
+-{"cror", XL(19,449), XL_MASK, COM, PPCNONE, {BT, BA, BB}},
+-
+-{"sleep", XL(19,466), 0xffffffff, POWER6, POWER9, {0}},
+-{"rvwinkle", XL(19,498), 0xffffffff, POWER6, POWER9, {0}},
+-
+-{"bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, PPCNONE, {0}},
+-{"bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, PPCNONE, {0}},
+-
+-{"bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
+-{"bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
+-{"bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
+-{"bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
+-{"bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
+-{"blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
+-{"bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
+-{"blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
+-{"bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
+-{"bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
+-{"bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
+-{"bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
+-{"bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
+-{"bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
+-{"bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
+-{"bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
+-{"bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
+-{"bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
+-{"bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
+-{"beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
+-{"beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
+-{"bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
+-{"bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
+-{"bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
+-{"bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
+-{"bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-{"bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
+-
+-{"bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
+-{"bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
+-{"bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
+-{"bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
+-{"bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
+-{"bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
+-{"bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
+-{"bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
+-{"bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
+-{"bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
+-{"btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
+-{"btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
+-{"btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
+-{"btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
+-{"btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
+-{"btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
+-{"btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
+-{"btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
+-{"btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
+-{"btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
+-
+-{"bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}},
+-{"bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}},
+-{"bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}},
+-{"bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}},
+-{"bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, PPCNONE, {BO, BI, BH}},
+-{"bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, PPCNONE, {BO, BI}},
+-{"bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, PPCNONE, {BO, BI, BH}},
+-{"bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, PPCNONE, {BO, BI}},
+-
+-{"bctar-", XLYLK(19,560,0,0), XLYBB_MASK, POWER8, PPCNONE, {BOE, BI}},
+-{"bctarl-", XLYLK(19,560,0,1), XLYBB_MASK, POWER8, PPCNONE, {BOE, BI}},
+-{"bctar+", XLYLK(19,560,1,0), XLYBB_MASK, POWER8, PPCNONE, {BOE, BI}},
+-{"bctarl+", XLYLK(19,560,1,1), XLYBB_MASK, POWER8, PPCNONE, {BOE, BI}},
+-{"bctar", XLLK(19,560,0), XLBH_MASK, POWER8, PPCNONE, {BO, BI, BH}},
+-{"bctarl", XLLK(19,560,1), XLBH_MASK, POWER8, PPCNONE, {BO, BI, BH}},
+-
+-{"rlwimi", M(20,0), M_MASK, PPCCOM, PPCNONE, {RA, RS, SH, MBE, ME}},
+-{"rlimi", M(20,0), M_MASK, PWRCOM, PPCNONE, {RA, RS, SH, MBE, ME}},
+-
+-{"rlwimi.", M(20,1), M_MASK, PPCCOM, PPCNONE, {RA, RS, SH, MBE, ME}},
+-{"rlimi.", M(20,1), M_MASK, PWRCOM, PPCNONE, {RA, RS, SH, MBE, ME}},
+-
+-{"rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, PPCNONE, {RA, RS, SH}},
+-{"clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, PPCNONE, {RA, RS, MB}},
+-{"rlwinm", M(21,0), M_MASK, PPCCOM, PPCNONE, {RA, RS, SH, MBE, ME}},
+-{"rlinm", M(21,0), M_MASK, PWRCOM, PPCNONE, {RA, RS, SH, MBE, ME}},
+-{"rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, PPCNONE, {RA, RS, SH}},
+-{"clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, PPCNONE, {RA, RS, MB}},
+-{"rlwinm.", M(21,1), M_MASK, PPCCOM, PPCNONE, {RA, RS, SH, MBE, ME}},
+-{"rlinm.", M(21,1), M_MASK, PWRCOM, PPCNONE, {RA, RS, SH, MBE, ME}},
+-
+-{"rlmi", M(22,0), M_MASK, M601, PPCNONE, {RA, RS, RB, MBE, ME}},
+-{"rlmi.", M(22,1), M_MASK, M601, PPCNONE, {RA, RS, RB, MBE, ME}},
+-
+-{"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCNONE, {RA, RS, RB}},
+-{"rlwnm", M(23,0), M_MASK, PPCCOM, PPCNONE, {RA, RS, RB, MBE, ME}},
+-{"rlnm", M(23,0), M_MASK, PWRCOM, PPCNONE, {RA, RS, RB, MBE, ME}},
+-{"rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, PPCNONE, {RA, RS, RB}},
+-{"rlwnm.", M(23,1), M_MASK, PPCCOM, PPCNONE, {RA, RS, RB, MBE, ME}},
+-{"rlnm.", M(23,1), M_MASK, PWRCOM, PPCNONE, {RA, RS, RB, MBE, ME}},
+-
+-{"nop", OP(24), 0xffffffff, PPCCOM, PPCNONE, {0}},
+-{"ori", OP(24), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}},
+-{"oril", OP(24), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}},
+-
+-{"oris", OP(25), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}},
+-{"oriu", OP(25), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}},
+-
+-{"xnop", OP(26), 0xffffffff, PPCCOM, PPCNONE, {0}},
+-{"xori", OP(26), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}},
+-{"xoril", OP(26), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}},
+-
+-{"xoris", OP(27), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}},
+-{"xoriu", OP(27), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}},
+-
+-{"andi.", OP(28), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}},
+-{"andil.", OP(28), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}},
+-
+-{"andis.", OP(29), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}},
+-{"andiu.", OP(29), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}},
+-
+-{"rotldi", MD(30,0,0), MDMB_MASK, PPC64, PPCNONE, {RA, RS, SH6}},
+-{"clrldi", MD(30,0,0), MDSH_MASK, PPC64, PPCNONE, {RA, RS, MB6}},
+-{"rldicl", MD(30,0,0), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}},
+-{"rotldi.", MD(30,0,1), MDMB_MASK, PPC64, PPCNONE, {RA, RS, SH6}},
+-{"clrldi.", MD(30,0,1), MDSH_MASK, PPC64, PPCNONE, {RA, RS, MB6}},
+-{"rldicl.", MD(30,0,1), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}},
+-
+-{"rldicr", MD(30,1,0), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, ME6}},
+-{"rldicr.", MD(30,1,1), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, ME6}},
+-
+-{"rldic", MD(30,2,0), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}},
+-{"rldic.", MD(30,2,1), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}},
+-
+-{"rldimi", MD(30,3,0), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}},
+-{"rldimi.", MD(30,3,1), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}},
+-
+-{"rotld", MDS(30,8,0), MDSMB_MASK, PPC64, PPCNONE, {RA, RS, RB}},
+-{"rldcl", MDS(30,8,0), MDS_MASK, PPC64, PPCNONE, {RA, RS, RB, MB6}},
+-{"rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, PPCNONE, {RA, RS, RB}},
+-{"rldcl.", MDS(30,8,1), MDS_MASK, PPC64, PPCNONE, {RA, RS, RB, MB6}},
+-
+-{"rldcr", MDS(30,9,0), MDS_MASK, PPC64, PPCNONE, {RA, RS, RB, ME6}},
+-{"rldcr.", MDS(30,9,1), MDS_MASK, PPC64, PPCNONE, {RA, RS, RB, ME6}},
+-
+-{"cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, PPCNONE, {OBF, RA, RB}},
+-{"cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, PPCNONE, {OBF, RA, RB}},
+-{"cmp", X(31,0), XCMP_MASK, PPC|PPCVLE, PPCNONE, {BF, L, RA, RB}},
++{"maclhwso", XO (4, 492,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"maclhwso.", XO (4, 492,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"nmaclhwso", XO (4, 494,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"nmaclhwso.", XO (4, 494,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
++{"dcbz_l", X (4,1014), XRT_MASK, PPCPS, 0, {RA, RB}},
++
++{"mulli", OP(7), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
++{"muli", OP(7), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
++
++{"subfic", OP(8), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
++{"sfi", OP(8), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
++
++{"dozi", OP(9), OP_MASK, M601, PPCVLE, {RT, RA, SI}},
++
++{"cmplwi", OPL(10,0), OPL_MASK, PPCCOM, PPCVLE, {OBF, RA, UISIGNOPT}},
++{"cmpldi", OPL(10,1), OPL_MASK, PPC64, PPCVLE, {OBF, RA, UISIGNOPT}},
++{"cmpli", OP(10), OP_MASK, PPC, PPCVLE, {BF, L, RA, UISIGNOPT}},
++{"cmpli", OP(10), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, UISIGNOPT}},
++
++{"cmpwi", OPL(11,0), OPL_MASK, PPCCOM, PPCVLE, {OBF, RA, SI}},
++{"cmpdi", OPL(11,1), OPL_MASK, PPC64, PPCVLE, {OBF, RA, SI}},
++{"cmpi", OP(11), OP_MASK, PPC, PPCVLE, {BF, L, RA, SI}},
++{"cmpi", OP(11), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, SI}},
++
++{"addic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
++{"ai", OP(12), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
++{"subic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, NSI}},
++
++{"addic.", OP(13), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
++{"ai.", OP(13), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
++{"subic.", OP(13), OP_MASK, PPCCOM, PPCVLE, {RT, RA, NSI}},
++
++{"li", OP(14), DRA_MASK, PPCCOM, PPCVLE, {RT, SI}},
++{"lil", OP(14), DRA_MASK, PWRCOM, PPCVLE, {RT, SI}},
++{"addi", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, SI}},
++{"cal", OP(14), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
++{"subi", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, NSI}},
++{"la", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, D, RA0}},
++
++{"lis", OP(15), DRA_MASK, PPCCOM, PPCVLE, {RT, SISIGNOPT}},
++{"liu", OP(15), DRA_MASK, PWRCOM, PPCVLE, {RT, SISIGNOPT}},
++{"addis", OP(15), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, SISIGNOPT}},
++{"cau", OP(15), OP_MASK, PWRCOM, PPCVLE, {RT, RA0, SISIGNOPT}},
++{"subis", OP(15), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, NSISIGNOPT}},
++
++{"bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}},
++{"bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}},
++{"bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BD}},
++{"bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, PPCVLE, {BD}},
++{"bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}},
++{"bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}},
++{"bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BD}},
++{"bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, PPCVLE, {BD}},
++{"bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}},
++{"bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}},
++{"bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDA}},
++{"bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, PPCVLE, {BDA}},
++{"bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}},
++{"bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}},
++{"bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDA}},
++{"bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, PPCVLE, {BDA}},
++{"bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}},
++{"bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}},
++{"bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, PPCVLE, {BD}},
++{"bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}},
++{"bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}},
++{"bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, PPCVLE, {BD}},
++{"bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}},
++{"bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}},
++{"bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, PPCVLE, {BDA}},
++{"bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}},
++{"bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}},
++{"bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, PPCVLE, {BDA}},
++
++{"bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
++{"bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
++{"bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
++{"bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
++{"bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
++{"bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
++{"bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
++{"bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
++{"bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
++{"bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
++{"bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
++{"bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
++{"bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
++{"bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
++{"bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
++{"bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
++{"bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
++{"bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
++{"bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
++{"bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
++{"bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
++{"bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
++{"bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
++{"bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
++{"ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
++{"ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
++{"ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
++{"bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
++{"bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
++{"bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
++{"blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
++{"blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
++{"blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
++{"bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
++{"bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
++{"bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
++{"blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
++{"blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
++{"blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
++{"bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
++{"bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
++{"bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
++{"blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
++{"blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
++{"blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
++{"bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
++{"bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
++{"bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
++{"bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
++{"bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
++{"bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
++{"bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
++{"bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
++{"bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
++{"bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
++{"bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
++{"bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
++{"bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
++{"bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
++{"bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
++{"bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
++{"bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
++{"bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
++{"bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
++{"bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
++{"bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}},
++{"bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
++{"bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
++{"bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
++{"bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
++{"bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
++{"bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}},
++{"bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
++{"bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
++{"bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
++{"bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
++{"bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
++{"bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}},
++{"bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
++{"bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
++{"bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
++{"bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
++{"bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
++{"bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}},
++
++{"blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
++{"blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
++{"blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
++{"bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
++{"bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
++{"bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
++{"blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
++{"blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
++{"blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
++{"bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
++{"bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
++{"bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
++{"bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
++{"bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
++{"bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
++{"bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
++{"bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
++{"bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
++{"bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
++{"bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
++{"bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
++{"bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
++{"bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
++{"bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
++{"beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
++{"beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
++{"beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
++{"beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
++{"beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
++{"beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
++{"beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
++{"beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
++{"beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
++{"beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
++{"beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
++{"beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
++{"bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
++{"bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
++{"bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
++{"bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
++{"bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
++{"bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}},
++{"bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
++{"bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
++{"bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
++{"bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
++{"bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
++{"bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}},
++{"bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
++{"bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
++{"bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
++{"buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
++{"buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
++{"buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}},
++{"bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
++{"bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
++{"bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
++{"bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
++{"bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
++{"bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}},
++
++{"bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
++{"bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
++{"bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
++{"bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
++{"bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
++{"bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
++{"bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
++{"bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
++{"bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
++{"bdnzfla-", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
++{"bdnzfla+", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
++{"bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
++{"bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
++{"bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
++{"bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
++{"bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
++{"bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
++{"bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
++{"bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
++{"bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
++{"bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
++{"bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
++{"bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
++{"bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
++
++{"bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}},
++{"bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}},
++{"bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}},
++{"bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}},
++{"bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}},
++{"bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}},
++{"bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}},
++{"bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}},
++{"bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}},
++{"bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}},
++{"bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}},
++{"bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}},
++{"bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}},
++{"bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}},
++{"bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}},
++{"bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}},
++
++{"bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
++{"bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
++{"bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
++{"bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
++{"bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
++{"bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
++{"bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
++{"bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
++{"bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
++{"bdnztla-", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
++{"bdnztla+", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
++{"bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
++{"bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
++{"bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
++{"bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
++{"bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
++{"bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
++{"bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
++{"bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
++{"bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
++{"bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
++{"bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
++{"bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
++{"bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
++
++{"bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}},
++{"bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}},
++{"bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}},
++{"bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}},
++{"btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}},
++{"btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}},
++{"btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}},
++{"bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}},
++{"bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}},
++{"bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}},
++{"bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}},
++{"bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}},
++{"btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}},
++{"btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}},
++{"btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}},
++{"bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}},
++
++{"bc-", B(16,0,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDM}},
++{"bc+", B(16,0,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDP}},
++{"bc", B(16,0,0), B_MASK, COM, PPCVLE, {BO, BI, BD}},
++{"bcl-", B(16,0,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDM}},
++{"bcl+", B(16,0,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDP}},
++{"bcl", B(16,0,1), B_MASK, COM, PPCVLE, {BO, BI, BD}},
++{"bca-", B(16,1,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDMA}},
++{"bca+", B(16,1,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDPA}},
++{"bca", B(16,1,0), B_MASK, COM, PPCVLE, {BO, BI, BDA}},
++{"bcla-", B(16,1,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDMA}},
++{"bcla+", B(16,1,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDPA}},
++{"bcla", B(16,1,1), B_MASK, COM, PPCVLE, {BO, BI, BDA}},
++
++{"svc", SC(17,0,0), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}},
++{"svcl", SC(17,0,1), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}},
++{"sc", SC(17,1,0), SC_MASK, PPC, PPCVLE, {LEV}},
++{"svca", SC(17,1,0), SC_MASK, PWRCOM, PPCVLE, {SV}},
++{"svcla", SC(17,1,1), SC_MASK, POWER, PPCVLE, {SV}},
++
++{"b", B(18,0,0), B_MASK, COM, PPCVLE, {LI}},
++{"bl", B(18,0,1), B_MASK, COM, PPCVLE, {LI}},
++{"ba", B(18,1,0), B_MASK, COM, PPCVLE, {LIA}},
++{"bla", B(18,1,1), B_MASK, COM, PPCVLE, {LIA}},
++
++{"mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, PPCVLE, {BF, BFA}},
++
++{"addpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, DXD}},
++{"subpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, NDXD}},
++
++{"bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
++{"bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
++{"bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
++{"bdnzlrl-", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
++{"bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
++{"bdnzlrl+", XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
++{"bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
++{"bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
++{"bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
++{"bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
++{"bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
++{"bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
++{"blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
++{"br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, PPCVLE, {0}},
++{"blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
++{"brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, PPCVLE, {0}},
++{"bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
++{"bdnzlrl-", XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
++{"bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
++{"bdnzlrl+", XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
++{"bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
++{"bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
++{"bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
++{"bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
++
++{"bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
++{"bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
++{"bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
++{"bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
++{"bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
++{"bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
++{"bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
++{"bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
++{"blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
++{"blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
++{"bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
++{"bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
++{"blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
++{"blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
++{"bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
++{"bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
++{"bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
++{"bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
++{"bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
++{"bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
++{"bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
++{"bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
++{"bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
++{"bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
++{"bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
++{"bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
++{"bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
++{"bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
++{"bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
++{"bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
++{"bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
++{"bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
++{"bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
++{"bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
++{"beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
++{"beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
++{"beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
++{"beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
++{"bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
++{"bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
++{"bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
++{"bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
++{"bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
++{"bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
++{"bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++
++{"bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
++{"bdnzflr-", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
++{"bdnzflrl", XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
++{"bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
++{"bdnzflr+", XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
++{"bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
++{"bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
++{"bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
++{"bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
++{"bdzflrl-", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
++{"bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
++{"bdzflrl+", XLO(19,BODZFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
++{"bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
++{"bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
++{"bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}},
++{"bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
++{"bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
++{"bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}},
++{"bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
++{"bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
++{"bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
++{"bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
++{"bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
++{"bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
++{"bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
++{"bdnztlr-", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
++{"bdnztlrl", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
++{"bdnztlrl-", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
++{"bdnztlr+", XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
++{"bdnztlrl+", XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
++{"bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
++{"bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
++{"bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
++{"bdztlrl-", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
++{"bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
++{"bdztlrl+", XLO(19,BODZTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
++{"btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
++{"btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
++{"bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}},
++{"btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
++{"btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
++{"bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}},
++{"btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
++{"btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
++{"btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
++{"btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
++{"btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
++{"btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
++
++{"bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
++{"bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
++{"bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
++{"bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
++{"bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}},
++{"bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}},
++{"bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}},
++{"bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}},
++
++{"rfid", XL(19,18), 0xffffffff, PPC64, PPCVLE, {0}},
++
++{"crnot", XL(19,33), XL_MASK, PPCCOM, PPCVLE, {BT, BA, BBA}},
++{"crnor", XL(19,33), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
++{"rfmci", X(19,38), 0xffffffff, PPCRFMCI|PPCA2|PPC476, PPCVLE, {0}},
++
++{"rfdi", XL(19,39), 0xffffffff, E500MC, PPCVLE, {0}},
++{"rfi", XL(19,50), 0xffffffff, COM, PPCVLE, {0}},
++{"rfci", XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300|PPCA2|PPC476, PPCVLE, {0}},
++
++{"rfsvc", XL(19,82), 0xffffffff, POWER, PPCVLE, {0}},
++
++{"rfgi", XL(19,102), 0xffffffff, E500MC|PPCA2, PPCVLE, {0}},
++
++{"crandc", XL(19,129), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
++
++{"rfebb", XL(19,146), XLS_MASK, POWER8, PPCVLE, {SXL}},
++
++{"isync", XL(19,150), 0xffffffff, PPCCOM, PPCVLE, {0}},
++{"ics", XL(19,150), 0xffffffff, PWRCOM, PPCVLE, {0}},
++
++{"crclr", XL(19,193), XL_MASK, PPCCOM, PPCVLE, {BT, BAT, BBA}},
++{"crxor", XL(19,193), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
++
++{"dnh", X(19,198), X_MASK, E500MC, PPCVLE, {DUI, DUIS}},
++
++{"crnand", XL(19,225), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
++
++{"crand", XL(19,257), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
++
++{"hrfid", XL(19,274), 0xffffffff, POWER5|CELL, PPC476|PPCVLE, {0}},
++
++{"crset", XL(19,289), XL_MASK, PPCCOM, PPCVLE, {BT, BAT, BBA}},
++{"creqv", XL(19,289), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
++
++{"urfid", XL(19,306), 0xffffffff, POWER9, PPCVLE, {0}},
++{"stop", XL(19,370), 0xffffffff, POWER9, PPCVLE, {0}},
++
++{"doze", XL(19,402), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
++
++{"crorc", XL(19,417), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
++
++{"nap", XL(19,434), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
++
++{"crmove", XL(19,449), XL_MASK, PPCCOM, PPCVLE, {BT, BA, BBA}},
++{"cror", XL(19,449), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
++
++{"sleep", XL(19,466), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
++{"rvwinkle", XL(19,498), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
++
++{"bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, PPCVLE, {0}},
++{"bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, PPCVLE, {0}},
++
++{"bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
++{"bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
++{"bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
++{"bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
++{"bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
++{"blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
++{"bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
++{"blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
++{"bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
++{"bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
++{"bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
++{"bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
++{"bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
++{"bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
++{"bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
++{"bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
++{"bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
++{"bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
++{"bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
++{"beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
++{"beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
++{"bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
++{"bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
++{"bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
++{"bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
++{"bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++{"bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
++
++{"bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
++{"bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
++{"bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
++{"bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
++{"bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
++{"bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
++{"bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
++{"bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
++{"bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
++{"bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
++{"btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
++{"btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
++{"btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
++{"btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
++{"btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
++{"btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
++{"btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
++{"btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
++{"btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
++{"btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
++
++{"bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
++{"bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
++{"bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
++{"bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
++{"bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}},
++{"bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}},
++{"bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}},
++{"bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}},
++
++{"bctar-", XLYLK(19,560,0,0), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}},
++{"bctarl-", XLYLK(19,560,0,1), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}},
++{"bctar+", XLYLK(19,560,1,0), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}},
++{"bctarl+", XLYLK(19,560,1,1), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}},
++{"bctar", XLLK(19,560,0), XLBH_MASK, POWER8, PPCVLE, {BO, BI, BH}},
++{"bctarl", XLLK(19,560,1), XLBH_MASK, POWER8, PPCVLE, {BO, BI, BH}},
++
++{"rlwimi", M(20,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
++{"rlimi", M(20,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
++
++{"rlwimi.", M(20,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
++{"rlimi.", M(20,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
++
++{"rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, SH}},
++{"clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, PPCVLE, {RA, RS, MB}},
++{"rlwinm", M(21,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
++{"rlinm", M(21,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
++{"rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, SH}},
++{"clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, PPCVLE, {RA, RS, MB}},
++{"rlwinm.", M(21,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
++{"rlinm.", M(21,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
++
++{"rlmi", M(22,0), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
++{"rlmi.", M(22,1), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
++
++{"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, RB}},
++{"rlwnm", M(23,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
++{"rlnm", M(23,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
++{"rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, RB}},
++{"rlwnm.", M(23,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
++{"rlnm.", M(23,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
++
++{"nop", OP(24), 0xffffffff, PPCCOM, PPCVLE, {0}},
++{"ori", OP(24), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
++{"oril", OP(24), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
++
++{"oris", OP(25), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
++{"oriu", OP(25), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
++
++{"xnop", OP(26), 0xffffffff, PPCCOM, PPCVLE, {0}},
++{"xori", OP(26), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
++{"xoril", OP(26), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
++
++{"xoris", OP(27), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
++{"xoriu", OP(27), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
++
++{"andi.", OP(28), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
++{"andil.", OP(28), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
++
++{"andis.", OP(29), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
++{"andiu.", OP(29), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
++
++{"rotldi", MD(30,0,0), MDMB_MASK, PPC64, PPCVLE, {RA, RS, SH6}},
++{"clrldi", MD(30,0,0), MDSH_MASK, PPC64, PPCVLE, {RA, RS, MB6}},
++{"rldicl", MD(30,0,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
++{"rotldi.", MD(30,0,1), MDMB_MASK, PPC64, PPCVLE, {RA, RS, SH6}},
++{"clrldi.", MD(30,0,1), MDSH_MASK, PPC64, PPCVLE, {RA, RS, MB6}},
++{"rldicl.", MD(30,0,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
++
++{"rldicr", MD(30,1,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}},
++{"rldicr.", MD(30,1,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}},
++
++{"rldic", MD(30,2,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
++{"rldic.", MD(30,2,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
++
++{"rldimi", MD(30,3,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
++{"rldimi.", MD(30,3,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
++
++{"rotld", MDS(30,8,0), MDSMB_MASK, PPC64, PPCVLE, {RA, RS, RB}},
++{"rldcl", MDS(30,8,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}},
++{"rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, PPCVLE, {RA, RS, RB}},
++{"rldcl.", MDS(30,8,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}},
++
++{"rldcr", MDS(30,9,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}},
++{"rldcr.", MDS(30,9,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}},
++
++{"cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}},
++{"cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}},
++{"cmp", X(31,0), XCMP_MASK, PPC, 0, {BF, L, RA, RB}},
+ {"cmp", X(31,0), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
+
+-{"twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}},
+-{"tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
+-{"twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}},
+-{"tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
+-{"tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}},
+-{"teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
+-{"twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}},
+-{"tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
+-{"twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}},
+-{"tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
+-{"twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}},
+-{"tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
+-{"twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}},
+-{"tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
+-{"twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}},
+-{"tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
+-{"twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}},
+-{"tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
+-{"twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}},
+-{"tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
+-{"twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}},
+-{"tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
+-{"twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}},
+-{"tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
+-{"twng", XTO(31,4,TONG), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}},
+-{"tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
+-{"twne", XTO(31,4,TONE), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}},
+-{"tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
+-{"trap", XTO(31,4,TOU), 0xffffffff, PPCCOM|PPCVLE, PPCNONE, {0}},
+-{"twu", XTO(31,4,TOU), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}},
+-{"tu", XTO(31,4,TOU), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
+-{"tw", X(31,4), X_MASK, PPCCOM|PPCVLE, PPCNONE, {TO, RA, RB}},
+-{"t", X(31,4), X_MASK, PWRCOM, PPCNONE, {TO, RA, RB}},
+-
+-{"lvsl", X(31,6), X_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, RA0, RB}},
+-{"lvebx", X(31,7), X_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, RA0, RB}},
+-{"lbfcmx", APU(31,7,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
+-
+-{"subfc", XO(31,8,0,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"sf", XO(31,8,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
+-{"subc", XO(31,8,0,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RB, RA}},
+-{"subfc.", XO(31,8,0,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"sf.", XO(31,8,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
+-{"subc.", XO(31,8,0,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RB, RA}},
+-
+-{"mulhdu", XO(31,9,0,0), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"mulhdu.", XO(31,9,0,1), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
+-
+-{"addc", XO(31,10,0,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"a", XO(31,10,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
+-{"addc.", XO(31,10,0,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"a.", XO(31,10,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
+-
+-{"mulhwu", XO(31,11,0,0), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"mulhwu.", XO(31,11,0,1), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
+-
+-{"lxsiwzx", X(31,12), XX1_MASK, PPCVSX2, PPCNONE, {XT6, RA0, RB}},
+-
+-{"isellt", X(31,15), X_MASK, PPCISEL, PPCNONE, {RT, RA0, RB}},
+-
+-{"tlbilxlpid", XTO(31,18,0), XTO_MASK, E500MC|PPCA2, PPCNONE, {0}},
+-{"tlbilxpid", XTO(31,18,1), XTO_MASK, E500MC|PPCA2, PPCNONE, {0}},
+-{"tlbilxva", XTO(31,18,3), XTO_MASK, E500MC|PPCA2, PPCNONE, {RA0, RB}},
+-{"tlbilx", X(31,18), X_MASK, E500MC|PPCA2, PPCNONE, {T, RA0, RB}},
+-
+-{"mfcr", XFXM(31,19,0,0), XFXFXM_MASK, COM|PPCVLE, PPCNONE, {RT, FXM4}},
+-{"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM|PPCVLE, PPCNONE, {RT, FXM}},
+-
+-{"lwarx", X(31,20), XEH_MASK, PPC|PPCVLE, PPCNONE, {RT, RA0, RB, EH}},
+-
+-{"ldx", X(31,21), X_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA0, RB}},
+-
+-{"icbt", X(31,22), X_MASK, BOOKE|PPCE300|PPCA2|PPC476|PPCVLE, PPCNONE, {CT, RA0, RB}},
+-
+-{"lwzx", X(31,23), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA0, RB}},
+-{"lx", X(31,23), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
+-
+-{"slw", XRC(31,24,0), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS, RB}},
+-{"sl", XRC(31,24,0), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}},
+-{"slw.", XRC(31,24,1), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS, RB}},
+-{"sl.", XRC(31,24,1), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}},
+-
+-{"cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS}},
+-{"cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, PPCNONE, {RA, RS}},
+-{"cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS}},
+-{"cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, PPCNONE, {RA, RS}},
+-
+-{"sld", XRC(31,27,0), X_MASK, PPC64, PPCNONE, {RA, RS, RB}},
+-{"sld.", XRC(31,27,1), X_MASK, PPC64, PPCNONE, {RA, RS, RB}},
+-
+-{"and", XRC(31,28,0), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
+-{"and.", XRC(31,28,1), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
+-
+-{"maskg", XRC(31,29,0), X_MASK, M601, PPCA2, {RA, RS, RB}},
+-{"maskg.", XRC(31,29,1), X_MASK, M601, PPCA2, {RA, RS, RB}},
+-
+-{"ldepx", X(31,29), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA0, RB}},
+-
+-{"waitasec", X(31,30), XRTRARB_MASK,POWER8, POWER9, {0}},
+-{"wait", X(31,30), XWC_MASK, POWER9, PPCNONE, {WC}},
+-
+-{"lwepx", X(31,31), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA0, RB}},
+-
+-{"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM|PPCVLE, PPCNONE, {OBF, RA, RB}},
+-{"cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, PPCNONE, {OBF, RA, RB}},
+-{"cmpl", X(31,32), XCMP_MASK, PPC|PPCVLE, PPCNONE, {BF, L, RA, RB}},
++{"twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, 0, {RA, RB}},
++{"tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, 0, {RA, RB}},
++{"twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, 0, {RA, RB}},
++{"tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, 0, {RA, RB}},
++{"tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, 0, {RA, RB}},
++{"teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, 0, {RA, RB}},
++{"twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, 0, {RA, RB}},
++{"tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, 0, {RA, RB}},
++{"twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, 0, {RA, RB}},
++{"tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, 0, {RA, RB}},
++{"twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, 0, {RA, RB}},
++{"tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, 0, {RA, RB}},
++{"twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, 0, {RA, RB}},
++{"tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, 0, {RA, RB}},
++{"twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, 0, {RA, RB}},
++{"tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, 0, {RA, RB}},
++{"twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, 0, {RA, RB}},
++{"tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, 0, {RA, RB}},
++{"twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, 0, {RA, RB}},
++{"tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, 0, {RA, RB}},
++{"twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, 0, {RA, RB}},
++{"tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, 0, {RA, RB}},
++{"twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, 0, {RA, RB}},
++{"tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, 0, {RA, RB}},
++{"twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, 0, {RA, RB}},
++{"tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, 0, {RA, RB}},
++{"twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, 0, {RA, RB}},
++{"tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, 0, {RA, RB}},
++{"trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, 0, {0}},
++{"twu", XTO(31,4,TOU), XTO_MASK, PPCCOM, 0, {RA, RB}},
++{"tu", XTO(31,4,TOU), XTO_MASK, PWRCOM, 0, {RA, RB}},
++{"tw", X(31,4), X_MASK, PPCCOM, 0, {TO, RA, RB}},
++{"t", X(31,4), X_MASK, PWRCOM, 0, {TO, RA, RB}},
++
++{"lvsl", X(31,6), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
++{"lvebx", X(31,7), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
++{"lbfcmx", APU(31,7,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
++
++{"subfc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
++{"sf", XO(31,8,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
++{"subc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
++{"subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
++{"sf.", XO(31,8,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
++{"subc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
++
++{"mulhdu", XO(31,9,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
++{"mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
++
++{"addc", XO(31,10,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
++{"a", XO(31,10,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
++{"addc.", XO(31,10,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
++{"a.", XO(31,10,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
++
++{"mulhwu", XO(31,11,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
++{"mulhwu.", XO(31,11,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
++
++{"lxsiwzx", X(31,12), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},
++
++{"isellt", X(31,15), X_MASK, PPCISEL, 0, {RT, RA0, RB}},
++
++{"tlbilxlpid", XTO(31,18,0), XTO_MASK, E500MC|PPCA2, 0, {0}},
++{"tlbilxpid", XTO(31,18,1), XTO_MASK, E500MC|PPCA2, 0, {0}},
++{"tlbilxva", XTO(31,18,3), XTO_MASK, E500MC|PPCA2, 0, {RA0, RB}},
++{"tlbilx", X(31,18), X_MASK, E500MC|PPCA2, 0, {T, RA0, RB}},
++
++{"mfcr", XFXM(31,19,0,0), XFXFXM_MASK, COM, 0, {RT, FXM4}},
++{"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, 0, {RT, FXM}},
++
++{"lwarx", X(31,20), XEH_MASK, PPC, 0, {RT, RA0, RB, EH}},
++
++{"ldx", X(31,21), X_MASK, PPC64, 0, {RT, RA0, RB}},
++
++{"icbt", X(31,22), X_MASK, BOOKE|PPCE300|PPCA2|PPC476, 0, {CT, RA0, RB}},
++
++{"lwzx", X(31,23), X_MASK, PPCCOM, 0, {RT, RA0, RB}},
++{"lx", X(31,23), X_MASK, PWRCOM, 0, {RT, RA, RB}},
++
++{"slw", XRC(31,24,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
++{"sl", XRC(31,24,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
++{"slw.", XRC(31,24,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
++{"sl.", XRC(31,24,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
++
++{"cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, 0, {RA, RS}},
++{"cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, 0, {RA, RS}},
++{"cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, 0, {RA, RS}},
++{"cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, 0, {RA, RS}},
++
++{"sld", XRC(31,27,0), X_MASK, PPC64, 0, {RA, RS, RB}},
++{"sld.", XRC(31,27,1), X_MASK, PPC64, 0, {RA, RS, RB}},
++
++{"and", XRC(31,28,0), X_MASK, COM, 0, {RA, RS, RB}},
++{"and.", XRC(31,28,1), X_MASK, COM, 0, {RA, RS, RB}},
++
++{"maskg", XRC(31,29,0), X_MASK, M601, PPCA2, {RA, RS, RB}},
++{"maskg.", XRC(31,29,1), X_MASK, M601, PPCA2, {RA, RS, RB}},
++
++{"ldepx", X(31,29), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
++
++{"waitasec", X(31,30), XRTRARB_MASK, POWER8, POWER9, {0}},
++{"wait", X(31,30), XWC_MASK, POWER9, 0, {WC}},
++
++{"lwepx", X(31,31), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
++
++{"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}},
++{"cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}},
++{"cmpl", X(31,32), XCMP_MASK, PPC, 0, {BF, L, RA, RB}},
+ {"cmpl", X(31,32), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
+
+-{"lvsr", X(31,38), X_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, RA0, RB}},
+-{"lvehx", X(31,39), X_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, RA0, RB}},
+-{"lhfcmx", APU(31,39,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
++{"lvsr", X(31,38), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
++{"lvehx", X(31,39), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
++{"lhfcmx", APU(31,39,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
+
+-{"mviwsplt", X(31,46), X_MASK, PPCVEC2, PPCNONE, {VD, RA, RB}},
++{"mviwsplt", X(31,46), X_MASK, PPCVEC2, 0, {VD, RA, RB}},
+
+-{"iselgt", X(31,47), X_MASK, PPCISEL, PPCNONE, {RT, RA0, RB}},
++{"iselgt", X(31,47), X_MASK, PPCISEL, 0, {RT, RA0, RB}},
+
+-{"lvewx", X(31,71), X_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, RA0, RB}},
++{"lvewx", X(31,71), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
+
+-{"addg6s", XO(31,74,0,0), XO_MASK, POWER6, PPCNONE, {RT, RA, RB}},
++{"addg6s", XO(31,74,0,0), XO_MASK, POWER6, 0, {RT, RA, RB}},
+
+-{"lxsiwax", X(31,76), XX1_MASK, PPCVSX2, PPCNONE, {XT6, RA0, RB}},
++{"lxsiwax", X(31,76), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},
+
+-{"iseleq", X(31,79), X_MASK, PPCISEL, PPCNONE, {RT, RA0, RB}},
++{"iseleq", X(31,79), X_MASK, PPCISEL, 0, {RT, RA0, RB}},
+
+-{"isel", XISEL(31,15), XISEL_MASK, PPCISEL|TITAN|PPCVLE, PPCNONE, {RT, RA0, RB, CRB}},
++{"isel", XISEL(31,15), XISEL_MASK, PPCISEL|TITAN, 0, {RT, RA0, RB, CRB}},
+
+-{"subf", XO(31,40,0,0), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"sub", XO(31,40,0,0), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RB, RA}},
+-{"subf.", XO(31,40,0,1), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"sub.", XO(31,40,0,1), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RB, RA}},
++{"subf", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
++{"sub", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RB, RA}},
++{"subf.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
++{"sub.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RB, RA}},
+
+-{"mfvsrd", X(31,51), XX1RB_MASK, PPCVSX2, PPCNONE, {RA, XS6}},
+-{"mffprd", X(31,51), XX1RB_MASK|1, PPCVSX2, PPCNONE, {RA, FRS}},
+-{"mfvrd", X(31,51)|1, XX1RB_MASK|1, PPCVSX2, PPCNONE, {RA, VS}},
+-{"eratilx", X(31,51), X_MASK, PPCA2, PPCNONE, {ERAT_T, RA, RB}},
++{"mfvsrd", X(31,51), XX1RB_MASK, PPCVSX2, 0, {RA, XS6}},
++{"mffprd", X(31,51), XX1RB_MASK|1, PPCVSX2, 0, {RA, FRS}},
++{"mfvrd", X(31,51)|1, XX1RB_MASK|1, PPCVSX2, 0, {RA, VS}},
++{"eratilx", X(31,51), X_MASK, PPCA2, 0, {ERAT_T, RA, RB}},
+
+-{"lbarx", X(31,52), XEH_MASK, POWER8|E6500|PPCVLE, PPCNONE, {RT, RA0, RB, EH}},
++{"lbarx", X(31,52), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}},
+
+-{"ldux", X(31,53), X_MASK, PPC64|PPCVLE, PPCNONE, {RT, RAL, RB}},
++{"ldux", X(31,53), X_MASK, PPC64, 0, {RT, RAL, RB}},
+
+-{"dcbst", X(31,54), XRT_MASK, PPC|PPCVLE, PPCNONE, {RA0, RB}},
++{"dcbst", X(31,54), XRT_MASK, PPC, 0, {RA0, RB}},
+
+-{"lwzux", X(31,55), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RAL, RB}},
+-{"lux", X(31,55), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
++{"lwzux", X(31,55), X_MASK, PPCCOM, 0, {RT, RAL, RB}},
++{"lux", X(31,55), X_MASK, PWRCOM, 0, {RT, RA, RB}},
+
+-{"cntlzd", XRC(31,58,0), XRB_MASK, PPC64|PPCVLE, PPCNONE, {RA, RS}},
+-{"cntlzd.", XRC(31,58,1), XRB_MASK, PPC64|PPCVLE, PPCNONE, {RA, RS}},
++{"cntlzd", XRC(31,58,0), XRB_MASK, PPC64, 0, {RA, RS}},
++{"cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, 0, {RA, RS}},
+
+-{"andc", XRC(31,60,0), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
+-{"andc.", XRC(31,60,1), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
++{"andc", XRC(31,60,0), X_MASK, COM, 0, {RA, RS, RB}},
++{"andc.", XRC(31,60,1), X_MASK, COM, 0, {RA, RS, RB}},
+
+-{"waitrsv", X(31,62)|(1<<21), 0xffffffff, E500MC|PPCA2, PPCNONE, {0}},
+-{"waitimpl", X(31,62)|(2<<21), 0xffffffff, E500MC|PPCA2, PPCNONE, {0}},
+-{"wait", X(31,62), XWC_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {WC}},
++{"waitrsv", X(31,62)|(1<<21), 0xffffffff, E500MC|PPCA2, 0, {0}},
++{"waitimpl", X(31,62)|(2<<21), 0xffffffff, E500MC|PPCA2, 0, {0}},
++{"wait", X(31,62), XWC_MASK, E500MC|PPCA2, 0, {WC}},
+
+-{"dcbstep", XRT(31,63,0), XRT_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RA0, RB}},
++{"dcbstep", XRT(31,63,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
+
+-{"tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
+-{"tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
+-{"tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
+-{"tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
+-{"tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
+-{"tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
+-{"tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
+-{"tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
+-{"tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
+-{"tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
+-{"tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
+-{"tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
+-{"tdng", XTO(31,68,TONG), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
+-{"tdne", XTO(31,68,TONE), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
+-{"tdu", XTO(31,68,TOU), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
+-{"td", X(31,68), X_MASK, PPC64|PPCVLE, PPCNONE, {TO, RA, RB}},
++{"tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, 0, {RA, RB}},
++{"tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, 0, {RA, RB}},
++{"tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, 0, {RA, RB}},
++{"tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, 0, {RA, RB}},
++{"tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, 0, {RA, RB}},
++{"tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, 0, {RA, RB}},
++{"tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, 0, {RA, RB}},
++{"tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, 0, {RA, RB}},
++{"tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, 0, {RA, RB}},
++{"tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, 0, {RA, RB}},
++{"tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, 0, {RA, RB}},
++{"tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, 0, {RA, RB}},
++{"tdng", XTO(31,68,TONG), XTO_MASK, PPC64, 0, {RA, RB}},
++{"tdne", XTO(31,68,TONE), XTO_MASK, PPC64, 0, {RA, RB}},
++{"tdu", XTO(31,68,TOU), XTO_MASK, PPC64, 0, {RA, RB}},
++{"td", X(31,68), X_MASK, PPC64, 0, {TO, RA, RB}},
+
+-{"lwfcmx", APU(31,71,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
+-{"mulhd", XO(31,73,0,0), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"mulhd.", XO(31,73,0,1), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
++{"lwfcmx", APU(31,71,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
++{"mulhd", XO(31,73,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
++{"mulhd.", XO(31,73,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
+
+-{"mulhw", XO(31,75,0,0), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"mulhw.", XO(31,75,0,1), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
++{"mulhw", XO(31,75,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
++{"mulhw.", XO(31,75,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
+
+-{"dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440|TITAN|PPCVLE, PPCNONE, {RA, RS, RB}},
+-{"dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440|TITAN|PPCVLE, PPCNONE, {RA, RS, RB}},
++{"dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440|TITAN, 0, {RA, RS, RB}},
++{"dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440|TITAN, 0, {RA, RS, RB}},
+
+-{"mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, PPCNONE, {SR, RS}},
++{"mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, 0, {SR, RS}},
+
+-{"mfmsr", X(31,83), XRARB_MASK, COM|PPCVLE, PPCNONE, {RT}},
++{"mfmsr", X(31,83), XRARB_MASK, COM, 0, {RT}},
+
+-{"ldarx", X(31,84), XEH_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA0, RB, EH}},
++{"ldarx", X(31,84), XEH_MASK, PPC64, 0, {RT, RA0, RB, EH}},
+
+ {"dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, PPC476, {RA0, RB}},
+-{"dcbf", X(31,86), XLRT_MASK, PPC|PPCVLE, PPCNONE, {RA0, RB, L}},
++{"dcbf", X(31,86), XLRT_MASK, PPC, 0, {RA0, RB, L}},
+
+-{"lbzx", X(31,87), X_MASK, COM|PPCVLE, PPCNONE, {RT, RA0, RB}},
++{"lbzx", X(31,87), X_MASK, COM, 0, {RT, RA0, RB}},
+
+-{"lbepx", X(31,95), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA0, RB}},
++{"lbepx", X(31,95), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
+
+-{"dni", XRC(31,97,1), XRB_MASK, E6500, PPCNONE, {DUI, DCTL}},
++{"dni", XRC(31,97,1), XRB_MASK, E6500, 0, {DUI, DCTL}},
+
+-{"lvx", X(31,103), X_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, RA0, RB}},
+-{"lqfcmx", APU(31,103,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
++{"lvx", X(31,103), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
++{"lqfcmx", APU(31,103,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
+
+-{"neg", XO(31,104,0,0), XORB_MASK, COM|PPCVLE, PPCNONE, {RT, RA}},
+-{"neg.", XO(31,104,0,1), XORB_MASK, COM|PPCVLE, PPCNONE, {RT, RA}},
++{"neg", XO(31,104,0,0), XORB_MASK, COM, 0, {RT, RA}},
++{"neg.", XO(31,104,0,1), XORB_MASK, COM, 0, {RT, RA}},
+
+-{"mul", XO(31,107,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
+-{"mul.", XO(31,107,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
++{"mul", XO(31,107,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
++{"mul.", XO(31,107,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
+
+-{"mvidsplt", X(31,110), X_MASK, PPCVEC2, PPCNONE, {VD, RA, RB}},
++{"mvidsplt", X(31,110), X_MASK, PPCVEC2, 0, {VD, RA, RB}},
+
+-{"mtsrdin", X(31,114), XRA_MASK, PPC64, PPCNONE, {RS, RB}},
++{"mtsrdin", X(31,114), XRA_MASK, PPC64, 0, {RS, RB}},
+
+-{"mffprwz", X(31,115), XX1RB_MASK|1, PPCVSX2, PPCNONE, {RA, FRS}},
+-{"mfvrwz", X(31,115)|1, XX1RB_MASK|1, PPCVSX2, PPCNONE, {RA, VS}},
+-{"mfvsrwz", X(31,115), XX1RB_MASK, PPCVSX2, PPCNONE, {RA, XS6}},
++{"mffprwz", X(31,115), XX1RB_MASK|1, PPCVSX2, 0, {RA, FRS}},
++{"mfvrwz", X(31,115)|1, XX1RB_MASK|1, PPCVSX2, 0, {RA, VS}},
++{"mfvsrwz", X(31,115), XX1RB_MASK, PPCVSX2, 0, {RA, XS6}},
+
+-{"lharx", X(31,116), XEH_MASK, POWER8|E6500|PPCVLE, PPCNONE, {RT, RA0, RB, EH}},
++{"lharx", X(31,116), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}},
+
+-{"clf", X(31,118), XTO_MASK, POWER, PPCNONE, {RA, RB}},
++{"clf", X(31,118), XTO_MASK, POWER, 0, {RA, RB}},
+
+-{"lbzux", X(31,119), X_MASK, COM|PPCVLE, PPCNONE, {RT, RAL, RB}},
++{"lbzux", X(31,119), X_MASK, COM, 0, {RT, RAL, RB}},
+
+-{"popcntb", X(31,122), XRB_MASK, POWER5|PPCVLE, PPCNONE, {RA, RS}},
++{"popcntb", X(31,122), XRB_MASK, POWER5, 0, {RA, RS}},
+
+-{"not", XRC(31,124,0), X_MASK, COM, PPCNONE, {RA, RS, RBS}},
+-{"nor", XRC(31,124,0), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
+-{"not.", XRC(31,124,1), X_MASK, COM, PPCNONE, {RA, RS, RBS}},
+-{"nor.", XRC(31,124,1), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
++{"not", XRC(31,124,0), X_MASK, COM, 0, {RA, RS, RBS}},
++{"nor", XRC(31,124,0), X_MASK, COM, 0, {RA, RS, RB}},
++{"not.", XRC(31,124,1), X_MASK, COM, 0, {RA, RS, RBS}},
++{"nor.", XRC(31,124,1), X_MASK, COM, 0, {RA, RS, RB}},
+
+-{"dcbfep", XRT(31,127,0), XRT_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RA0, RB}},
++{"dcbfep", XRT(31,127,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
+
+-{"setb", X(31,128), XRB_MASK|(3<<16), POWER9, PPCNONE, {RT, BFA}},
++{"setb", X(31,128), XRB_MASK|(3<<16), POWER9, 0, {RT, BFA}},
+
+-{"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {RS}},
++{"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RS}},
+
+-{"dcbtstls", X(31,134), X_MASK, PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA0, RB}},
++{"dcbtstls", X(31,134), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
+
+-{"stvebx", X(31,135), X_MASK, PPCVEC, PPCNONE, {VS, RA0, RB}},
+-{"stbfcmx", APU(31,135,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
++{"stvebx", X(31,135), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
++{"stbfcmx", APU(31,135,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
+
+-{"subfe", XO(31,136,0,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"sfe", XO(31,136,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
+-{"subfe.", XO(31,136,0,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
++{"subfe", XO(31,136,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
++{"sfe", XO(31,136,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
++{"subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
++{"sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
+
+-{"adde", XO(31,138,0,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"ae", XO(31,138,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
+-{"adde.", XO(31,138,0,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"ae.", XO(31,138,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
++{"adde", XO(31,138,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
++{"ae", XO(31,138,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
++{"adde.", XO(31,138,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
++{"ae.", XO(31,138,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
+
+-{"stxsiwx", X(31,140), XX1_MASK, PPCVSX2, PPCNONE, {XS6, RA0, RB}},
++{"stxsiwx", X(31,140), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}},
+
+-{"msgsndp", XRTRA(31,142,0,0), XRTRA_MASK, POWER8, PPCNONE, {RB}},
+-{"dcbtstlse", X(31,142), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}},
++{"msgsndp", XRTRA(31,142,0,0), XRTRA_MASK, POWER8, 0, {RB}},
++{"dcbtstlse", X(31,142), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}},
+
+-{"mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, PPCNONE, {RS}},
+-{"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK, COM|PPCVLE, PPCNONE, {FXM, RS}},
+-{"mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM|PPCVLE, PPCNONE, {FXM, RS}},
++{"mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, 0, {RS}},
++{"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK, COM, 0, {FXM, RS}},
++{"mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, 0, {FXM, RS}},
+
+-{"mtmsr", X(31,146), XRLARB_MASK, COM|PPCVLE, PPCNONE, {RS, A_L}},
++{"mtmsr", X(31,146), XRLARB_MASK, COM, 0, {RS, A_L}},
+
+-{"mtsle", X(31,147), XRTLRARB_MASK, POWER8, PPCNONE, {L}},
++{"mtsle", X(31,147), XRTLRARB_MASK, POWER8, 0, {L}},
+
+-{"eratsx", XRC(31,147,0), X_MASK, PPCA2, PPCNONE, {RT, RA0, RB}},
+-{"eratsx.", XRC(31,147,1), X_MASK, PPCA2, PPCNONE, {RT, RA0, RB}},
++{"eratsx", XRC(31,147,0), X_MASK, PPCA2, 0, {RT, RA0, RB}},
++{"eratsx.", XRC(31,147,1), X_MASK, PPCA2, 0, {RT, RA0, RB}},
+
+-{"stdx", X(31,149), X_MASK, PPC64|PPCVLE, PPCNONE, {RS, RA0, RB}},
++{"stdx", X(31,149), X_MASK, PPC64, 0, {RS, RA0, RB}},
+
+-{"stwcx.", XRC(31,150,1), X_MASK, PPC|PPCVLE, PPCNONE, {RS, RA0, RB}},
++{"stwcx.", XRC(31,150,1), X_MASK, PPC, 0, {RS, RA0, RB}},
+
+-{"stwx", X(31,151), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RS, RA0, RB}},
+-{"stx", X(31,151), X_MASK, PWRCOM, PPCNONE, {RS, RA, RB}},
++{"stwx", X(31,151), X_MASK, PPCCOM, 0, {RS, RA0, RB}},
++{"stx", X(31,151), X_MASK, PWRCOM, 0, {RS, RA, RB}},
+
+-{"slq", XRC(31,152,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
+-{"slq.", XRC(31,152,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
++{"slq", XRC(31,152,0), X_MASK, M601, 0, {RA, RS, RB}},
++{"slq.", XRC(31,152,1), X_MASK, M601, 0, {RA, RS, RB}},
+
+-{"sle", XRC(31,153,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
+-{"sle.", XRC(31,153,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
++{"sle", XRC(31,153,0), X_MASK, M601, 0, {RA, RS, RB}},
++{"sle.", XRC(31,153,1), X_MASK, M601, 0, {RA, RS, RB}},
+
+-{"prtyw", X(31,154), XRB_MASK, POWER6|PPCA2|PPC476, PPCNONE, {RA, RS}},
++{"prtyw", X(31,154), XRB_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS}},
+
+-{"stdepx", X(31,157), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RS, RA0, RB}},
++{"stdepx", X(31,157), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
+
+-{"stwepx", X(31,159), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RS, RA0, RB}},
++{"stwepx", X(31,159), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
+
+-{"wrteei", X(31,163), XE_MASK, PPC403|BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {E}},
++{"wrteei", X(31,163), XE_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {E}},
+
+-{"dcbtls", X(31,166), X_MASK, PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA0, RB}},
++{"dcbtls", X(31,166), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
+
+-{"stvehx", X(31,167), X_MASK, PPCVEC, PPCNONE, {VS, RA0, RB}},
+-{"sthfcmx", APU(31,167,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
++{"stvehx", X(31,167), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
++{"sthfcmx", APU(31,167,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
+
+-{"addex", ZRC(31,170,0), Z2_MASK, POWER9, PPCNONE, {RT, RA, RB, CY}},
+-{"addex.", ZRC(31,170,1), Z2_MASK, POWER9, PPCNONE, {RT, RA, RB, CY}},
++{"addex", ZRC(31,170,0), Z2_MASK, POWER9, 0, {RT, RA, RB, CY}},
++{"addex.", ZRC(31,170,1), Z2_MASK, POWER9, 0, {RT, RA, RB, CY}},
+
+-{"msgclrp", XRTRA(31,174,0,0), XRTRA_MASK, POWER8, PPCNONE, {RB}},
+-{"dcbtlse", X(31,174), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}},
++{"msgclrp", XRTRA(31,174,0,0), XRTRA_MASK, POWER8, 0, {RB}},
++{"dcbtlse", X(31,174), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}},
+
+-{"mtmsrd", X(31,178), XRLARB_MASK, PPC64, PPCNONE, {RS, A_L}},
++{"mtmsrd", X(31,178), XRLARB_MASK, PPC64, 0, {RS, A_L}},
+
+-{"mtvsrd", X(31,179), XX1RB_MASK, PPCVSX2, PPCNONE, {XT6, RA}},
+-{"mtfprd", X(31,179), XX1RB_MASK|1, PPCVSX2, PPCNONE, {FRT, RA}},
+-{"mtvrd", X(31,179)|1, XX1RB_MASK|1, PPCVSX2, PPCNONE, {VD, RA}},
+-{"eratre", X(31,179), X_MASK, PPCA2, PPCNONE, {RT, RA, WS}},
++{"mtvsrd", X(31,179), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}},
++{"mtfprd", X(31,179), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}},
++{"mtvrd", X(31,179)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}},
++{"eratre", X(31,179), X_MASK, PPCA2, 0, {RT, RA, WS}},
+
+-{"stdux", X(31,181), X_MASK, PPC64|PPCVLE, PPCNONE, {RS, RAS, RB}},
++{"stdux", X(31,181), X_MASK, PPC64, 0, {RS, RAS, RB}},
+
+-{"stqcx.", XRC(31,182,1), X_MASK, POWER8, PPCNONE, {RSQ, RA0, RB}},
+-{"wchkall", X(31,182), X_MASK, PPCA2, PPCNONE, {OBF}},
++{"stqcx.", XRC(31,182,1), X_MASK, POWER8, 0, {RSQ, RA0, RB}},
++{"wchkall", X(31,182), X_MASK, PPCA2, 0, {OBF}},
+
+-{"stwux", X(31,183), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RS, RAS, RB}},
+-{"stux", X(31,183), X_MASK, PWRCOM, PPCNONE, {RS, RA0, RB}},
++{"stwux", X(31,183), X_MASK, PPCCOM, 0, {RS, RAS, RB}},
++{"stux", X(31,183), X_MASK, PWRCOM, 0, {RS, RA0, RB}},
+
+-{"sliq", XRC(31,184,0), X_MASK, M601, PPCNONE, {RA, RS, SH}},
+-{"sliq.", XRC(31,184,1), X_MASK, M601, PPCNONE, {RA, RS, SH}},
++{"sliq", XRC(31,184,0), X_MASK, M601, 0, {RA, RS, SH}},
++{"sliq.", XRC(31,184,1), X_MASK, M601, 0, {RA, RS, SH}},
+
+-{"prtyd", X(31,186), XRB_MASK, POWER6|PPCA2, PPCNONE, {RA, RS}},
++{"prtyd", X(31,186), XRB_MASK, POWER6|PPCA2, 0, {RA, RS}},
+
+-{"cmprb", X(31,192), XCMP_MASK, POWER9, PPCNONE, {BF, L, RA, RB}},
++{"cmprb", X(31,192), XCMP_MASK, POWER9, 0, {BF, L, RA, RB}},
+
+-{"icblq.", XRC(31,198,1), X_MASK, E6500, PPCNONE, {CT, RA0, RB}},
++{"icblq.", XRC(31,198,1), X_MASK, E6500, 0, {CT, RA0, RB}},
+
+-{"stvewx", X(31,199), X_MASK, PPCVEC, PPCNONE, {VS, RA0, RB}},
+-{"stwfcmx", APU(31,199,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
++{"stvewx", X(31,199), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
++{"stwfcmx", APU(31,199,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
+
+-{"subfze", XO(31,200,0,0), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}},
+-{"sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
+-{"subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}},
+-{"sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
++{"subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
++{"sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
++{"subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
++{"sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
+
+-{"addze", XO(31,202,0,0), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}},
+-{"aze", XO(31,202,0,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
+-{"addze.", XO(31,202,0,1), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}},
+-{"aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
++{"addze", XO(31,202,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
++{"aze", XO(31,202,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
++{"addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
++{"aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
+
+-{"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8|PPCVLE, PPCNONE, {RB}},
++{"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0, {RB}},
+
+-{"mtsr", X(31,210), XRB_MASK|(1<<20), COM, NON32, {SR, RS}},
++{"mtsr", X(31,210), XRB_MASK|(1<<20), COM, NON32, {SR, RS}},
+
+-{"mtfprwa", X(31,211), XX1RB_MASK|1, PPCVSX2, PPCNONE, {FRT, RA}},
+-{"mtvrwa", X(31,211)|1, XX1RB_MASK|1, PPCVSX2, PPCNONE, {VD, RA}},
+-{"mtvsrwa", X(31,211), XX1RB_MASK, PPCVSX2, PPCNONE, {XT6, RA}},
+-{"eratwe", X(31,211), X_MASK, PPCA2, PPCNONE, {RS, RA, WS}},
++{"mtfprwa", X(31,211), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}},
++{"mtvrwa", X(31,211)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}},
++{"mtvsrwa", X(31,211), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}},
++{"eratwe", X(31,211), X_MASK, PPCA2, 0, {RS, RA, WS}},
+
+-{"ldawx.", XRC(31,212,1), X_MASK, PPCA2, PPCNONE, {RT, RA0, RB}},
++{"ldawx.", XRC(31,212,1), X_MASK, PPCA2, 0, {RT, RA0, RB}},
+
+-{"stdcx.", XRC(31,214,1), X_MASK, PPC64|PPCVLE, PPCNONE, {RS, RA0, RB}},
++{"stdcx.", XRC(31,214,1), X_MASK, PPC64, 0, {RS, RA0, RB}},
+
+-{"stbx", X(31,215), X_MASK, COM|PPCVLE, PPCNONE, {RS, RA0, RB}},
++{"stbx", X(31,215), X_MASK, COM, 0, {RS, RA0, RB}},
+
+-{"sllq", XRC(31,216,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
+-{"sllq.", XRC(31,216,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
++{"sllq", XRC(31,216,0), X_MASK, M601, 0, {RA, RS, RB}},
++{"sllq.", XRC(31,216,1), X_MASK, M601, 0, {RA, RS, RB}},
+
+-{"sleq", XRC(31,217,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
+-{"sleq.", XRC(31,217,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
++{"sleq", XRC(31,217,0), X_MASK, M601, 0, {RA, RS, RB}},
++{"sleq.", XRC(31,217,1), X_MASK, M601, 0, {RA, RS, RB}},
+
+-{"stbepx", X(31,223), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RS, RA0, RB}},
++{"stbepx", X(31,223), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
+
+-{"cmpeqb", X(31,224), XCMPL_MASK, POWER9, PPCNONE, {BF, RA, RB}},
++{"cmpeqb", X(31,224), XCMPL_MASK, POWER9, 0, {BF, RA, RB}},
+
+-{"icblc", X(31,230), X_MASK, PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA0, RB}},
++{"icblc", X(31,230), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
+
+-{"stvx", X(31,231), X_MASK, PPCVEC|PPCVLE, PPCNONE, {VS, RA0, RB}},
+-{"stqfcmx", APU(31,231,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
++{"stvx", X(31,231), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
++{"stqfcmx", APU(31,231,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
+
+-{"subfme", XO(31,232,0,0), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}},
+-{"sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
+-{"subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}},
+-{"sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
++{"subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
++{"sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
++{"subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
++{"sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
+
+-{"mulld", XO(31,233,0,0), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"mulld.", XO(31,233,0,1), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
++{"mulld", XO(31,233,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
++{"mulld.", XO(31,233,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
+
+-{"addme", XO(31,234,0,0), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}},
+-{"ame", XO(31,234,0,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
+-{"addme.", XO(31,234,0,1), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}},
+-{"ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
++{"addme", XO(31,234,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
++{"ame", XO(31,234,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
++{"addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
++{"ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
+
+-{"mullw", XO(31,235,0,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"muls", XO(31,235,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
+-{"mullw.", XO(31,235,0,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
++{"mullw", XO(31,235,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
++{"muls", XO(31,235,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
++{"mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
++{"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
+
+-{"icblce", X(31,238), X_MASK, PPCCHLK, E500MC|PPCA2, {CT, RA, RB}},
+-{"msgclr", XRTRA(31,238,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8|PPCVLE, PPCNONE, {RB}},
+-{"mtsrin", X(31,242), XRA_MASK, PPC, NON32, {RS, RB}},
++{"icblce", X(31,238), X_MASK, PPCCHLK, E500MC|PPCA2, {CT, RA, RB}},
++{"msgclr", XRTRA(31,238,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0, {RB}},
++{"mtsrin", X(31,242), XRA_MASK, PPC, NON32, {RS, RB}},
+ {"mtsri", X(31,242), XRA_MASK, POWER, NON32, {RS, RB}},
+
+-{"mtfprwz", X(31,243), XX1RB_MASK|1, PPCVSX2, PPCNONE, {FRT, RA}},
+-{"mtvrwz", X(31,243)|1, XX1RB_MASK|1, PPCVSX2, PPCNONE, {VD, RA}},
+-{"mtvsrwz", X(31,243), XX1RB_MASK, PPCVSX2, PPCNONE, {XT6, RA}},
++{"mtfprwz", X(31,243), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}},
++{"mtvrwz", X(31,243)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}},
++{"mtvsrwz", X(31,243), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}},
+
+-{"dcbtstt", XRT(31,246,0x10), XRT_MASK, POWER7, PPCNONE, {RA0, RB}},
+-{"dcbtst", X(31,246), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}},
+-{"dcbtst", X(31,246), X_MASK, DCBT_EO, PPCNONE, {CT, RA0, RB}},
+-{"dcbtst", X(31,246), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}},
++{"dcbtstt", XRT(31,246,0x10), XRT_MASK, POWER7, 0, {RA0, RB}},
++{"dcbtst", X(31,246), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}},
++{"dcbtst", X(31,246), X_MASK, DCBT_EO, 0, {CT, RA0, RB}},
++{"dcbtst", X(31,246), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}},
+
+-{"stbux", X(31,247), X_MASK, COM|PPCVLE, PPCNONE, {RS, RAS, RB}},
++{"stbux", X(31,247), X_MASK, COM, 0, {RS, RAS, RB}},
+
+-{"slliq", XRC(31,248,0), X_MASK, M601, PPCNONE, {RA, RS, SH}},
+-{"slliq.", XRC(31,248,1), X_MASK, M601, PPCNONE, {RA, RS, SH}},
++{"slliq", XRC(31,248,0), X_MASK, M601, 0, {RA, RS, SH}},
++{"slliq.", XRC(31,248,1), X_MASK, M601, 0, {RA, RS, SH}},
+
+-{"bpermd", X(31,252), X_MASK, POWER7|PPCA2, PPCNONE, {RA, RS, RB}},
++{"bpermd", X(31,252), X_MASK, POWER7|PPCA2, 0, {RA, RS, RB}},
+
+-{"dcbtstep", XRT(31,255,0), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA0, RB}},
++{"dcbtstep", XRT(31,255,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
+
+-{"mfdcrx", X(31,259), X_MASK, BOOKE|PPCA2|PPC476|PPCVLE, TITAN, {RS, RA}},
+-{"mfdcrx.", XRC(31,259,1), X_MASK, PPCA2, PPCNONE, {RS, RA}},
++{"mfdcrx", X(31,259), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RS, RA}},
++{"mfdcrx.", XRC(31,259,1), X_MASK, PPCA2, 0, {RS, RA}},
+
+-{"lvexbx", X(31,261), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
++{"lvexbx", X(31,261), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
+
+-{"icbt", X(31,262), XRT_MASK, PPC403, PPCNONE, {RA, RB}},
++{"icbt", X(31,262), XRT_MASK, PPC403, 0, {RA, RB}},
+
+-{"lvepxl", X(31,263), X_MASK, PPCVEC2|PPCVLE, PPCNONE, {VD, RA0, RB}},
++{"lvepxl", X(31,263), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
+
+-{"ldfcmx", APU(31,263,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
+-{"doz", XO(31,264,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
+-{"doz.", XO(31,264,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
++{"ldfcmx", APU(31,263,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
++{"doz", XO(31,264,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
++{"doz.", XO(31,264,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
+
+-{"modud", X(31,265), X_MASK, POWER9, PPCNONE, {RT, RA, RB}},
++{"modud", X(31,265), X_MASK, POWER9, 0, {RT, RA, RB}},
+
+-{"add", XO(31,266,0,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"cax", XO(31,266,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
+-{"add.", XO(31,266,0,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"cax.", XO(31,266,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
++{"add", XO(31,266,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
++{"cax", XO(31,266,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
++{"add.", XO(31,266,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
++{"cax.", XO(31,266,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
+
+-{"moduw", X(31,267), X_MASK, POWER9, PPCNONE, {RT, RA, RB}},
++{"moduw", X(31,267), X_MASK, POWER9, 0, {RT, RA, RB}},
+
+-{"lxvx", X(31,268), XX1_MASK|1<<6, PPCVSX3, PPCNONE, {XT6, RA0, RB}},
+-{"lxvl", X(31,269), XX1_MASK, PPCVSX3, PPCNONE, {XT6, RA0, RB}},
++{"lxvx", X(31,268), XX1_MASK|1<<6, PPCVSX3, 0, {XT6, RA0, RB}},
++{"lxvl", X(31,269), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
+
+-{"ehpriv", X(31,270), 0xffffffff, E500MC|PPCA2|PPCVLE, PPCNONE, {0}},
++{"ehpriv", X(31,270), 0xffffffff, E500MC|PPCA2, 0, {0}},
+
+-{"tlbiel", X(31,274), X_MASK|1<<20,POWER9, PPC476, {RB, RSO, RIC, PRS, X_R}},
++{"tlbiel", X(31,274), X_MASK|1<<20,POWER9, PPC476, {RB, RSO, RIC, PRS, X_R}},
+ {"tlbiel", X(31,274), XRTLRA_MASK, POWER4, POWER9|PPC476, {RB, L}},
+
+-{"mfapidi", X(31,275), X_MASK, BOOKE, E500|TITAN, {RT, RA}},
++{"mfapidi", X(31,275), X_MASK, BOOKE, E500|TITAN, {RT, RA}},
+
+-{"lqarx", X(31,276), XEH_MASK, POWER8, PPCNONE, {RTQ, RAX, RBX, EH}},
++{"lqarx", X(31,276), XEH_MASK, POWER8, 0, {RTQ, RAX, RBX, EH}},
+
+-{"lscbx", XRC(31,277,0), X_MASK, M601, PPCNONE, {RT, RA, RB}},
+-{"lscbx.", XRC(31,277,1), X_MASK, M601, PPCNONE, {RT, RA, RB}},
++{"lscbx", XRC(31,277,0), X_MASK, M601, 0, {RT, RA, RB}},
++{"lscbx.", XRC(31,277,1), X_MASK, M601, 0, {RT, RA, RB}},
+
+-{"dcbtt", XRT(31,278,0x10), XRT_MASK, POWER7, PPCNONE, {RA0, RB}},
+-{"dcbt", X(31,278), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}},
+-{"dcbt", X(31,278), X_MASK, DCBT_EO, PPCNONE, {CT, RA0, RB}},
+-{"dcbt", X(31,278), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}},
++{"dcbtt", XRT(31,278,0x10), XRT_MASK, POWER7, 0, {RA0, RB}},
++{"dcbt", X(31,278), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}},
++{"dcbt", X(31,278), X_MASK, DCBT_EO, 0, {CT, RA0, RB}},
++{"dcbt", X(31,278), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}},
+
+-{"lhzx", X(31,279), X_MASK, COM|PPCVLE, PPCNONE, {RT, RA0, RB}},
++{"lhzx", X(31,279), X_MASK, COM, 0, {RT, RA0, RB}},
+
+-{"cdtbcd", X(31,282), XRB_MASK, POWER6, PPCNONE, {RA, RS}},
++{"cdtbcd", X(31,282), XRB_MASK, POWER6, 0, {RA, RS}},
+
+-{"eqv", XRC(31,284,0), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
+-{"eqv.", XRC(31,284,1), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
++{"eqv", XRC(31,284,0), X_MASK, COM, 0, {RA, RS, RB}},
++{"eqv.", XRC(31,284,1), X_MASK, COM, 0, {RA, RS, RB}},
+
+-{"lhepx", X(31,287), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA0, RB}},
++{"lhepx", X(31,287), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
+
+-{"mfdcrux", X(31,291), X_MASK, PPC464|PPCVLE, PPCNONE, {RS, RA}},
++{"mfdcrux", X(31,291), X_MASK, PPC464, 0, {RS, RA}},
+
+-{"lvexhx", X(31,293), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
+-{"lvepx", X(31,295), X_MASK, PPCVEC2|PPCVLE, PPCNONE, {VD, RA0, RB}},
++{"lvexhx", X(31,293), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
++{"lvepx", X(31,295), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
+
+-{"lxvll", X(31,301), XX1_MASK, PPCVSX3, PPCNONE, {XT6, RA0, RB}},
++{"lxvll", X(31,301), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
+
+-{"mfbhrbe", X(31,302), X_MASK, POWER8, PPCNONE, {RT, BHRBE}},
++{"mfbhrbe", X(31,302), X_MASK, POWER8, 0, {RT, BHRBE}},
+
+-{"tlbie", X(31,306), X_MASK|1<<20,POWER9, TITAN, {RB, RS, RIC, PRS, X_R}},
+-{"tlbie", X(31,306), XRA_MASK, POWER7, POWER9|TITAN, {RB, RS}},
+-{"tlbie", X(31,306), XRTLRA_MASK, PPC, E500|POWER7|TITAN, {RB, L}},
+-{"tlbi", X(31,306), XRT_MASK, POWER, PPCNONE, {RA0, RB}},
++{"tlbie", X(31,306), X_MASK|1<<20,POWER9, TITAN, {RB, RS, RIC, PRS, X_R}},
++{"tlbie", X(31,306), XRA_MASK, POWER7, POWER9|TITAN, {RB, RS}},
++{"tlbie", X(31,306), XRTLRA_MASK, PPC, E500|POWER7|TITAN, {RB, L}},
++{"tlbi", X(31,306), XRT_MASK, POWER, 0, {RA0, RB}},
+
+-{"mfvsrld", X(31,307), XX1RB_MASK, PPCVSX3, PPCNONE, {RA, XS6}},
++{"mfvsrld", X(31,307), XX1RB_MASK, PPCVSX3, 0, {RA, XS6}},
+
+-{"ldmx", X(31,309), X_MASK, POWER9, PPCNONE, {RT, RA0, RB}},
++{"ldmx", X(31,309), X_MASK, POWER9, 0, {RT, RA0, RB}},
+
+-{"eciwx", X(31,310), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
++{"eciwx", X(31,310), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
+
+-{"lhzux", X(31,311), X_MASK, COM|PPCVLE, PPCNONE, {RT, RAL, RB}},
++{"lhzux", X(31,311), X_MASK, COM, 0, {RT, RAL, RB}},
+
+-{"cbcdtd", X(31,314), XRB_MASK, POWER6, PPCNONE, {RA, RS}},
++{"cbcdtd", X(31,314), XRB_MASK, POWER6, 0, {RA, RS}},
+
+-{"xor", XRC(31,316,0), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
+-{"xor.", XRC(31,316,1), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
++{"xor", XRC(31,316,0), X_MASK, COM, 0, {RA, RS, RB}},
++{"xor.", XRC(31,316,1), X_MASK, COM, 0, {RA, RS, RB}},
+
+-{"dcbtep", XRT(31,319,0), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA0, RB}},
++{"dcbtep", XRT(31,319,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
+
+-{"mfexisr", XSPR(31,323, 64), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mfexier", XSPR(31,323, 66), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mfdcr", X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476|PPCVLE, E500|TITAN, {RT, SPR}},
+-{"mfdcr.", XRC(31,323,1), X_MASK, PPCA2, PPCNONE, {RT, SPR}},
++{"mfexisr", XSPR(31,323, 64), XSPR_MASK, PPC403, 0, {RT}},
++{"mfexier", XSPR(31,323, 66), XSPR_MASK, PPC403, 0, {RT}},
++{"mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, 0, {RT}},
++{"mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, 0, {RT}},
++{"mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, 0, {RT}},
++{"mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, 0, {RT}},
++{"mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, 0, {RT}},
++{"mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, 0, {RT}},
++{"mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, 0, {RT}},
++{"mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, 0, {RT}},
++{"mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, 0, {RT}},
++{"mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, 0, {RT}},
++{"mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, 0, {RT}},
++{"mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, 0, {RT}},
++{"mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, 0, {RT}},
++{"mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, 0, {RT}},
++{"mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, 0, {RT}},
++{"mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, 0, {RT}},
++{"mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, 0, {RT}},
++{"mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, 0, {RT}},
++{"mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, 0, {RT}},
++{"mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, 0, {RT}},
++{"mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, 0, {RT}},
++{"mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, 0, {RT}},
++{"mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, 0, {RT}},
++{"mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, 0, {RT}},
++{"mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, 0, {RT}},
++{"mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, 0, {RT}},
++{"mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, 0, {RT}},
++{"mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, 0, {RT}},
++{"mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, 0, {RT}},
++{"mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, 0, {RT}},
++{"mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, 0, {RT}},
++{"mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, 0, {RT}},
++{"mfdcr", X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {RT, SPR}},
++{"mfdcr.", XRC(31,323,1), X_MASK, PPCA2, 0, {RT, SPR}},
+
+-{"lvexwx", X(31,325), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
++{"lvexwx", X(31,325), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
+
+-{"dcread", X(31,326), X_MASK, PPC476|TITAN, PPCNONE, {RT, RA0, RB}},
++{"dcread", X(31,326), X_MASK, PPC476|TITAN, 0, {RT, RA0, RB}},
+
+-{"div", XO(31,331,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
+-{"div.", XO(31,331,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
++{"div", XO(31,331,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
++{"div.", XO(31,331,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
+
+-{"lxvdsx", X(31,332), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA0, RB}},
++{"lxvdsx", X(31,332), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
+
+-{"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300|PPCVLE, PPCNONE, {RT, PMR}},
+-{"mftmr", X(31,366), X_MASK, PPCTMR|E6500, PPCNONE, {RT, TMR}},
++{"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, 0, {RT, PMR}},
++{"mftmr", X(31,366), X_MASK, PPCTMR|E6500, 0, {RT, TMR}},
+
+-{"slbsync", X(31,338), 0xffffffff, POWER9, PPCNONE, {0}},
+-
+-{"mfmq", XSPR(31,339, 0), XSPR_MASK, M601, PPCNONE, {RT}},
+-{"mfxer", XSPR(31,339, 1), XSPR_MASK, COM|PPCVLE, PPCNONE, {RT}},
+-{"mfrtcu", XSPR(31,339, 4), XSPR_MASK, COM, TITAN, {RT}},
+-{"mfrtcl", XSPR(31,339, 5), XSPR_MASK, COM, TITAN, {RT}},
+-{"mfdec", XSPR(31,339, 6), XSPR_MASK, MFDEC1, PPCNONE, {RT}},
+-{"mflr", XSPR(31,339, 8), XSPR_MASK, COM|PPCVLE, PPCNONE, {RT}},
+-{"mfctr", XSPR(31,339, 9), XSPR_MASK, COM|PPCVLE, PPCNONE, {RT}},
+-{"mfdscr", XSPR(31,339, 17), XSPR_MASK, POWER6, PPCNONE, {RT}},
+-{"mftid", XSPR(31,339, 17), XSPR_MASK, POWER, PPCNONE, {RT}},
+-{"mfdsisr", XSPR(31,339, 18), XSPR_MASK, COM, TITAN, {RT}},
+-{"mfdar", XSPR(31,339, 19), XSPR_MASK, COM, TITAN, {RT}},
++{"slbsync", X(31,338), 0xffffffff, POWER9, 0, {0}},
++
++{"mfmq", XSPR(31,339, 0), XSPR_MASK, M601, 0, {RT}},
++{"mfxer", XSPR(31,339, 1), XSPR_MASK, COM, 0, {RT}},
++{"mfrtcu", XSPR(31,339, 4), XSPR_MASK, COM, TITAN, {RT}},
++{"mfrtcl", XSPR(31,339, 5), XSPR_MASK, COM, TITAN, {RT}},
++{"mfdec", XSPR(31,339, 6), XSPR_MASK, MFDEC1, 0, {RT}},
++{"mflr", XSPR(31,339, 8), XSPR_MASK, COM, 0, {RT}},
++{"mfctr", XSPR(31,339, 9), XSPR_MASK, COM, 0, {RT}},
++{"mfdscr", XSPR(31,339, 17), XSPR_MASK, POWER6, 0, {RT}},
++{"mftid", XSPR(31,339, 17), XSPR_MASK, POWER, 0, {RT}},
++{"mfdsisr", XSPR(31,339, 18), XSPR_MASK, COM, TITAN, {RT}},
++{"mfdar", XSPR(31,339, 19), XSPR_MASK, COM, TITAN, {RT}},
+ {"mfdec", XSPR(31,339, 22), XSPR_MASK, MFDEC2, MFDEC1, {RT}},
+-{"mfsdr0", XSPR(31,339, 24), XSPR_MASK, POWER, PPCNONE, {RT}},
+-{"mfsdr1", XSPR(31,339, 25), XSPR_MASK, COM, TITAN, {RT}},
+-{"mfsrr0", XSPR(31,339, 26), XSPR_MASK, COM, PPCNONE, {RT}},
+-{"mfsrr1", XSPR(31,339, 27), XSPR_MASK, COM, PPCNONE, {RT}},
+-{"mfcfar", XSPR(31,339, 28), XSPR_MASK, POWER6, PPCNONE, {RT}},
+-{"mfpid", XSPR(31,339, 48), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+-{"mfcsrr0", XSPR(31,339, 58), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+-{"mfcsrr1", XSPR(31,339, 59), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+-{"mfdear", XSPR(31,339, 61), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+-{"mfesr", XSPR(31,339, 62), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+-{"mfivpr", XSPR(31,339, 63), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+-{"mfctrl", XSPR(31,339,136), XSPR_MASK, POWER4, PPCNONE, {RT}},
+-{"mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, PPCNONE, {RT}},
+-{"mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, PPCNONE, {RT}},
+-{"mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, PPCNONE, {RT}},
+-{"mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, PPCNONE, {RT}},
+-{"mficr", XSPR(31,339,148), XSPR_MASK, PPC860, PPCNONE, {RT}},
+-{"mfder", XSPR(31,339,149), XSPR_MASK, PPC860, PPCNONE, {RT}},
+-{"mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, PPCNONE, {RT}},
+-{"mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, PPCNONE, {RT}},
+-{"mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, PPCNONE, {RT}},
+-{"mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, PPCNONE, {RT}},
+-{"mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, PPCNONE, {RT}},
+-{"mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, PPCNONE, {RT}},
+-{"mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, PPCNONE, {RT}},
+-{"mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, PPCNONE, {RT}},
+-{"mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, PPCNONE, {RT}},
+-{"mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, PPCNONE, {RT}},
+-{"mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, PPCNONE, {RT}},
+-{"mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+-{"mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC|PPCVLE, PPCNONE, {RT, SPRG}},
+-{"mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RT}},
+-{"mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RT}},
+-{"mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RT}},
+-{"mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RT}},
+-{"mftbu", XSPR(31,339,269), XSPR_MASK, POWER4|BOOKE|PPCVLE, PPCNONE, {RT}},
+-{"mftb", X(31,339), X_MASK, POWER4|BOOKE|PPCVLE, PPCNONE, {RT, TBR}},
+-{"mftbl", XSPR(31,339,268), XSPR_MASK, POWER4|BOOKE|PPCVLE, PPCNONE, {RT}},
+-{"mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC|PPCVLE, PPCNONE, {RT}},
+-{"mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC|PPCVLE, PPCNONE, {RT}},
+-{"mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC|PPCVLE, PPCNONE, {RT}},
+-{"mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC|PPCVLE, PPCNONE, {RT}},
+-{"mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, PPCNONE, {RT}},
+-{"mfear", XSPR(31,339,282), XSPR_MASK, PPC, TITAN, {RT}},
+-{"mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+-{"mfpvr", XSPR(31,339,287), XSPR_MASK, PPC|PPCVLE, PPCNONE, {RT}},
+-{"mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+-{"mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+-{"mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+-{"mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+-{"mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+-{"mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+-{"mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+-{"mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+-{"mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+-{"mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+-{"mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+-{"mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+-{"mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+-{"mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+-{"mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+-{"mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+-{"mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+-{"mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+-{"mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+-{"mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+-{"mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+-{"mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+-{"mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+-{"mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+-{"mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+-{"mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+-{"mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+-{"mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+-{"mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+-{"mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+-{"mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, PPCNONE, {RT}},
+-{"mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, PPCNONE, {RT}},
+-{"mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, PPCNONE, {RT}},
+-{"mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, PPCNONE, {RT}},
+-{"mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
+-{"mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, PPCNONE, {RT}},
+-{"mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
+-{"mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, PPCNONE, {RT}},
+-{"mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, PPCNONE, {RT}},
+-{"mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
+-{"mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
+-{"mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, PPCNONE, {RT}},
+-{"mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, PPCNONE, {RT}},
+-{"mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, PPCNONE, {RT}},
+-{"mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, PPCNONE, {RT}},
+-{"mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, PPCNONE, {RT}},
+-{"mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, PPCNONE, {RT}},
+-{"mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, PPCNONE, {RT}},
+-{"mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, PPCNONE, {RT}},
+-{"mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, PPCNONE, {RT}},
+-{"mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, TITAN, {RT}},
+-{"mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, PPCNONE, {RT}},
+-{"mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, PPCNONE, {RT}},
+-{"mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, PPCNONE, {RT}},
+-{"mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, PPCNONE, {RT}},
+-{"mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, PPCNONE, {RT}},
+-{"mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, PPCNONE, {RT}},
+-{"mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, PPCNONE, {RT}},
+-{"mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, PPCNONE, {RT}},
+-{"mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, PPCNONE, {RT}},
+-{"mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, PPCNONE, {RT}},
+-{"mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, PPCNONE, {RT}},
+-{"mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, PPCNONE, {RT}},
+-{"mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, PPCNONE, {RT}},
+-{"mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, PPCNONE, {RT}},
+-{"mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, PPCNONE, {RT}},
+-{"mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, PPCNONE, {RT}},
+-{"mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, PPCNONE, {RT}},
+-{"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK, PPC860, PPCNONE, {RT}},
+-{"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK, PPC860, PPCNONE, {RT}},
+-{"mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, PPCNONE, {RT}},
+-{"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK, PPC860, PPCNONE, {RT}},
+-{"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK, PPC860, PPCNONE, {RT}},
+-{"mfivndx", XSPR(31,339,880), XSPR_MASK, TITAN, PPCNONE, {RT}},
+-{"mfdvndx", XSPR(31,339,881), XSPR_MASK, TITAN, PPCNONE, {RT}},
+-{"mfivlim", XSPR(31,339,882), XSPR_MASK, TITAN, PPCNONE, {RT}},
+-{"mfdvlim", XSPR(31,339,883), XSPR_MASK, TITAN, PPCNONE, {RT}},
+-{"mfclcsr", XSPR(31,339,884), XSPR_MASK, TITAN, PPCNONE, {RT}},
+-{"mfccr1", XSPR(31,339,888), XSPR_MASK, TITAN, PPCNONE, {RT}},
+-{"mfppr", XSPR(31,339,896), XSPR_MASK, POWER7, PPCNONE, {RT}},
+-{"mfppr32", XSPR(31,339,898), XSPR_MASK, POWER7, PPCNONE, {RT}},
+-{"mfrstcfg", XSPR(31,339,923), XSPR_MASK, TITAN, PPCNONE, {RT}},
+-{"mfdcdbtrl", XSPR(31,339,924), XSPR_MASK, TITAN, PPCNONE, {RT}},
+-{"mfdcdbtrh", XSPR(31,339,925), XSPR_MASK, TITAN, PPCNONE, {RT}},
+-{"mficdbtr", XSPR(31,339,927), XSPR_MASK, TITAN, PPCNONE, {RT}},
+-{"mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, PPCNONE, {RT}},
+-{"mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, PPCNONE, {RT}},
+-{"mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, PPCNONE, {RT}},
+-{"mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, PPCNONE, {RT}},
+-{"mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, PPCNONE, {RT}},
+-{"mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, PPCNONE, {RT}},
+-{"mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, PPCNONE, {RT}},
+-{"mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mfmmucr", XSPR(31,339,946), XSPR_MASK, TITAN, PPCNONE, {RT}},
+-{"mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405|TITAN, PPCNONE, {RT}},
+-{"mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, PPCNONE, {RT}},
+-{"mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, PPCNONE, {RT}},
+-{"mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, PPCNONE, {RT}},
+-{"mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, PPCNONE, {RT}},
+-{"mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, PPCNONE, {RT}},
+-{"mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, PPCNONE, {RT}},
+-{"mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, PPCNONE, {RT}},
+-{"mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, PPCNONE, {RT}},
+-{"mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, PPCNONE, {RT}},
+-{"mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, PPCNONE, {RT}},
+-{"mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, PPCNONE, {RT}},
+-{"mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, PPCNONE, {RT}},
+-{"mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, PPCNONE, {RT}},
+-{"mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, PPCNONE, {RT}},
+-{"mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403|TITAN, PPCNONE, {RT}},
+-{"mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, PPCNONE, {RT}},
+-{"mfdbdr", XSPR(31,339,1011), XSPR_MASK, TITAN, PPCNONE, {RS}},
+-{"mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, PPCNONE, {RT}},
+-{"mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, PPCNONE, {RT}},
+-{"mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, PPCNONE, {RT}},
+-{"mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, PPCNONE, {RT}},
+-{"mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, PPCNONE, {RT}},
+-{"mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, PPCNONE, {RT}},
+-{"mfspr", X(31,339), X_MASK, COM|PPCVLE, PPCNONE, {RT, SPR}},
+-
+-{"lwax", X(31,341), X_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA0, RB}},
+-
+-{"dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, PPCNONE, {RA, RB, STRM}},
+-
+-{"lhax", X(31,343), X_MASK, COM|PPCVLE, PPCNONE, {RT, RA0, RB}},
+-
+-{"lvxl", X(31,359), X_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, RA0, RB}},
+-
+-{"abs", XO(31,360,0,0), XORB_MASK, M601, PPCNONE, {RT, RA}},
+-{"abs.", XO(31,360,0,1), XORB_MASK, M601, PPCNONE, {RT, RA}},
+-
+-{"divs", XO(31,363,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
+-{"divs.", XO(31,363,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
+-
+-{"lxvwsx", X(31,364), XX1_MASK, PPCVSX3, PPCNONE, {XT6, RA0, RB}},
+-
+-{"tlbia", X(31,370), 0xffffffff, PPC, E500|TITAN, {0}},
++{"mfsdr0", XSPR(31,339, 24), XSPR_MASK, POWER, 0, {RT}},
++{"mfsdr1", XSPR(31,339, 25), XSPR_MASK, COM, TITAN, {RT}},
++{"mfsrr0", XSPR(31,339, 26), XSPR_MASK, COM, 0, {RT}},
++{"mfsrr1", XSPR(31,339, 27), XSPR_MASK, COM, 0, {RT}},
++{"mfcfar", XSPR(31,339, 28), XSPR_MASK, POWER6, 0, {RT}},
++{"mfpid", XSPR(31,339, 48), XSPR_MASK, BOOKE, 0, {RT}},
++{"mfcsrr0", XSPR(31,339, 58), XSPR_MASK, BOOKE, 0, {RT}},
++{"mfcsrr1", XSPR(31,339, 59), XSPR_MASK, BOOKE, 0, {RT}},
++{"mfdear", XSPR(31,339, 61), XSPR_MASK, BOOKE, 0, {RT}},
++{"mfesr", XSPR(31,339, 62), XSPR_MASK, BOOKE, 0, {RT}},
++{"mfivpr", XSPR(31,339, 63), XSPR_MASK, BOOKE, 0, {RT}},
++{"mfctrl", XSPR(31,339,136), XSPR_MASK, POWER4, 0, {RT}},
++{"mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, 0, {RT}},
++{"mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, 0, {RT}},
++{"mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, 0, {RT}},
++{"mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, 0, {RT}},
++{"mficr", XSPR(31,339,148), XSPR_MASK, PPC860, 0, {RT}},
++{"mfder", XSPR(31,339,149), XSPR_MASK, PPC860, 0, {RT}},
++{"mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, 0, {RT}},
++{"mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, 0, {RT}},
++{"mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, 0, {RT}},
++{"mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, 0, {RT}},
++{"mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, 0, {RT}},
++{"mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, 0, {RT}},
++{"mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, 0, {RT}},
++{"mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, 0, {RT}},
++{"mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, 0, {RT}},
++{"mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, 0, {RT}},
++{"mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, 0, {RT}},
++{"mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, 0, {RT}},
++{"mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, 0, {RT, SPRG}},
++{"mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
++{"mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
++{"mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
++{"mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
++{"mftbu", XSPR(31,339,269), XSPR_MASK, POWER4|BOOKE, 0, {RT}},
++{"mftb", X(31,339), X_MASK, POWER4|BOOKE, 0, {RT, TBR}},
++{"mftbl", XSPR(31,339,268), XSPR_MASK, POWER4|BOOKE, 0, {RT}},
++{"mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, 0, {RT}},
++{"mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, 0, {RT}},
++{"mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, 0, {RT}},
++{"mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, 0, {RT}},
++{"mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, 0, {RT}},
++{"mfear", XSPR(31,339,282), XSPR_MASK, PPC, TITAN, {RT}},
++{"mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, 0, {RT}},
++{"mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, 0, {RT}},
++{"mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, 0, {RT}},
++{"mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, 0, {RT}},
++{"mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, 0, {RT}},
++{"mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, 0, {RT}},
++{"mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, 0, {RT}},
++{"mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, 0, {RT}},
++{"mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, 0, {RT}},
++{"mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, 0, {RT}},
++{"mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, 0, {RT}},
++{"mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, 0, {RT}},
++{"mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, 0, {RT}},
++{"mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, 0, {RT}},
++{"mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, 0, {RT}},
++{"mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, 0, {RT}},
++{"mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, 0, {RT}},
++{"mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, 0, {RT}},
++{"mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, 0, {RT}},
++{"mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, 0, {RT}},
++{"mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, 0, {RT}},
++{"mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, 0, {RT}},
++{"mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, 0, {RT}},
++{"mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, 0, {RT}},
++{"mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, 0, {RT}},
++{"mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, 0, {RT}},
++{"mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, 0, {RT}},
++{"mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, 0, {RT}},
++{"mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, 0, {RT}},
++{"mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, 0, {RT}},
++{"mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, 0, {RT}},
++{"mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, 0, {RT}},
++{"mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, 0, {RT}},
++{"mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, 0, {RT}},
++{"mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, 0, {RT}},
++{"mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, 0, {RT}},
++{"mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
++{"mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, 0, {RT}},
++{"mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
++{"mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, 0, {RT}},
++{"mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, 0, {RT}},
++{"mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
++{"mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
++{"mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, 0, {RT}},
++{"mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, 0, {RT}},
++{"mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, 0, {RT}},
++{"mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, 0, {RT}},
++{"mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, 0, {RT}},
++{"mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, 0, {RT}},
++{"mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, 0, {RT}},
++{"mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, 0, {RT}},
++{"mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, 0, {RT}},
++{"mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, TITAN, {RT}},
++{"mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, 0, {RT}},
++{"mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, 0, {RT}},
++{"mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, 0, {RT}},
++{"mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, 0, {RT}},
++{"mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, 0, {RT}},
++{"mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, 0, {RT}},
++{"mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, 0, {RT}},
++{"mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, 0, {RT}},
++{"mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, 0, {RT}},
++{"mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, 0, {RT}},
++{"mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, 0, {RT}},
++{"mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, 0, {RT}},
++{"mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, 0, {RT}},
++{"mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, 0, {RT}},
++{"mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, 0, {RT}},
++{"mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, 0, {RT}},
++{"mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, 0, {RT}},
++{"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK, PPC860, 0, {RT}},
++{"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK, PPC860, 0, {RT}},
++{"mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, 0, {RT}},
++{"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK, PPC860, 0, {RT}},
++{"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK, PPC860, 0, {RT}},
++{"mfivndx", XSPR(31,339,880), XSPR_MASK, TITAN, 0, {RT}},
++{"mfdvndx", XSPR(31,339,881), XSPR_MASK, TITAN, 0, {RT}},
++{"mfivlim", XSPR(31,339,882), XSPR_MASK, TITAN, 0, {RT}},
++{"mfdvlim", XSPR(31,339,883), XSPR_MASK, TITAN, 0, {RT}},
++{"mfclcsr", XSPR(31,339,884), XSPR_MASK, TITAN, 0, {RT}},
++{"mfccr1", XSPR(31,339,888), XSPR_MASK, TITAN, 0, {RT}},
++{"mfppr", XSPR(31,339,896), XSPR_MASK, POWER7, 0, {RT}},
++{"mfppr32", XSPR(31,339,898), XSPR_MASK, POWER7, 0, {RT}},
++{"mfrstcfg", XSPR(31,339,923), XSPR_MASK, TITAN, 0, {RT}},
++{"mfdcdbtrl", XSPR(31,339,924), XSPR_MASK, TITAN, 0, {RT}},
++{"mfdcdbtrh", XSPR(31,339,925), XSPR_MASK, TITAN, 0, {RT}},
++{"mficdbtr", XSPR(31,339,927), XSPR_MASK, TITAN, 0, {RT}},
++{"mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, 0, {RT}},
++{"mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, 0, {RT}},
++{"mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, 0, {RT}},
++{"mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, 0, {RT}},
++{"mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, 0, {RT}},
++{"mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, 0, {RT}},
++{"mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, 0, {RT}},
++{"mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, 0, {RT}},
++{"mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, 0, {RT}},
++{"mfmmucr", XSPR(31,339,946), XSPR_MASK, TITAN, 0, {RT}},
++{"mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405|TITAN, 0, {RT}},
++{"mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, 0, {RT}},
++{"mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, 0, {RT}},
++{"mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, 0, {RT}},
++{"mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, 0, {RT}},
++{"mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, 0, {RT}},
++{"mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, 0, {RT}},
++{"mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, 0, {RT}},
++{"mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, 0, {RT}},
++{"mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, 0, {RT}},
++{"mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, 0, {RT}},
++{"mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, 0, {RT}},
++{"mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, 0, {RT}},
++{"mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, 0, {RT}},
++{"mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, 0, {RT}},
++{"mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, 0, {RT}},
++{"mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, 0, {RT}},
++{"mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403|TITAN, 0, {RT}},
++{"mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, 0, {RT}},
++{"mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, 0, {RT}},
++{"mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, 0, {RT}},
++{"mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, 0, {RT}},
++{"mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, 0, {RT}},
++{"mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, 0, {RT}},
++{"mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, 0, {RT}},
++{"mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, 0, {RT}},
++{"mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, 0, {RT}},
++{"mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, 0, {RT}},
++{"mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, 0, {RT}},
++{"mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, 0, {RT}},
++{"mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, 0, {RT}},
++{"mfdbdr", XSPR(31,339,1011), XSPR_MASK, TITAN, 0, {RS}},
++{"mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, 0, {RT}},
++{"mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, 0, {RT}},
++{"mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, 0, {RT}},
++{"mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, 0, {RT}},
++{"mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, 0, {RT}},
++{"mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, 0, {RT}},
++{"mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, 0, {RT}},
++{"mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, 0, {RT}},
++{"mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, 0, {RT}},
++{"mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, 0, {RT}},
++{"mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, 0, {RT}},
++{"mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, 0, {RT}},
++{"mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, 0, {RT}},
++{"mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, 0, {RT}},
++{"mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, 0, {RT}},
++{"mfspr", X(31,339), X_MASK, COM, 0, {RT, SPR}},
++
++{"lwax", X(31,341), X_MASK, PPC64, 0, {RT, RA0, RB}},
++
++{"dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
++
++{"lhax", X(31,343), X_MASK, COM, 0, {RT, RA0, RB}},
++
++{"lvxl", X(31,359), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
++
++{"abs", XO(31,360,0,0), XORB_MASK, M601, 0, {RT, RA}},
++{"abs.", XO(31,360,0,1), XORB_MASK, M601, 0, {RT, RA}},
++
++{"divs", XO(31,363,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
++{"divs.", XO(31,363,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
++
++{"lxvwsx", X(31,364), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
++
++{"tlbia", X(31,370), 0xffffffff, PPC, E500|TITAN, {0}},
+
+ {"mftbu", XSPR(31,371,269), XSPR_MASK, PPC, NO371|POWER4, {RT}},
+-{"mftb", X(31,371), X_MASK, PPC, NO371|POWER4, {RT, TBR}},
++{"mftb", X(31,371), X_MASK, PPC, NO371|POWER4, {RT, TBR}},
+ {"mftbl", XSPR(31,371,268), XSPR_MASK, PPC, NO371|POWER4, {RT}},
+
+-{"lwaux", X(31,373), X_MASK, PPC64|PPCVLE, PPCNONE, {RT, RAL, RB}},
++{"lwaux", X(31,373), X_MASK, PPC64, 0, {RT, RAL, RB}},
+
+-{"dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, PPCNONE, {RA, RB, STRM}},
++{"dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
+
+-{"lhaux", X(31,375), X_MASK, COM|PPCVLE, PPCNONE, {RT, RAL, RB}},
++{"lhaux", X(31,375), X_MASK, COM, 0, {RT, RAL, RB}},
+
+-{"popcntw", X(31,378), XRB_MASK, POWER7|PPCA2, PPCNONE, {RA, RS}},
++{"popcntw", X(31,378), XRB_MASK, POWER7|PPCA2, 0, {RA, RS}},
+
+-{"mtdcrx", X(31,387), X_MASK, BOOKE|PPCA2|PPC476|PPCVLE, TITAN, {RA, RS}},
+-{"mtdcrx.", XRC(31,387,1), X_MASK, PPCA2, PPCNONE, {RA, RS}},
++{"mtdcrx", X(31,387), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RA, RS}},
++{"mtdcrx.", XRC(31,387,1), X_MASK, PPCA2, 0, {RA, RS}},
+
+-{"stvexbx", X(31,389), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
++{"stvexbx", X(31,389), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
+
+-{"dcblc", X(31,390), X_MASK, PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA0, RB}},
+-{"stdfcmx", APU(31,391,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
++{"dcblc", X(31,390), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
++{"stdfcmx", APU(31,391,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
+
+-{"divdeu", XO(31,393,0,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
+-{"divdeu.", XO(31,393,0,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
+-{"divweu", XO(31,395,0,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
+-{"divweu.", XO(31,395,0,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
++{"divdeu", XO(31,393,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
++{"divdeu.", XO(31,393,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
++{"divweu", XO(31,395,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
++{"divweu.", XO(31,395,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
+
+-{"stxvx", X(31,396), XX1_MASK, PPCVSX3, PPCNONE, {XS6, RA0, RB}},
+-{"stxvl", X(31,397), XX1_MASK, PPCVSX3, PPCNONE, {XS6, RA0, RB}},
++{"stxvx", X(31,396), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
++{"stxvl", X(31,397), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
+
+-{"dcblce", X(31,398), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},
++{"dcblce", X(31,398), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},
+
+-{"slbmte", X(31,402), XRA_MASK, PPC64, PPCNONE, {RS, RB}},
++{"slbmte", X(31,402), XRA_MASK, PPC64, 0, {RS, RB}},
+
+-{"mtvsrws", X(31,403), XX1RB_MASK, PPCVSX3, PPCNONE, {XT6, RA}},
++{"mtvsrws", X(31,403), XX1RB_MASK, PPCVSX3, 0, {XT6, RA}},
+
+-{"pbt.", XRC(31,404,1), X_MASK, POWER8, PPCNONE, {RS, RA0, RB}},
++{"pbt.", XRC(31,404,1), X_MASK, POWER8, 0, {RS, RA0, RB}},
+
+-{"icswx", XRC(31,406,0), X_MASK, POWER7|PPCA2, PPCNONE, {RS, RA, RB}},
+-{"icswx.", XRC(31,406,1), X_MASK, POWER7|PPCA2, PPCNONE, {RS, RA, RB}},
++{"icswx", XRC(31,406,0), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}},
++{"icswx.", XRC(31,406,1), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}},
+
+-{"sthx", X(31,407), X_MASK, COM|PPCVLE, PPCNONE, {RS, RA0, RB}},
++{"sthx", X(31,407), X_MASK, COM, 0, {RS, RA0, RB}},
+
+-{"orc", XRC(31,412,0), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
+-{"orc.", XRC(31,412,1), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
++{"orc", XRC(31,412,0), X_MASK, COM, 0, {RA, RS, RB}},
++{"orc.", XRC(31,412,1), X_MASK, COM, 0, {RA, RS, RB}},
+
+-{"sthepx", X(31,415), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RS, RA0, RB}},
++{"sthepx", X(31,415), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
+
+-{"mtdcrux", X(31,419), X_MASK, PPC464|PPCVLE, PPCNONE, {RA, RS}},
++{"mtdcrux", X(31,419), X_MASK, PPC464, 0, {RA, RS}},
+
+-{"stvexhx", X(31,421), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
++{"stvexhx", X(31,421), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
+
+-{"dcblq.", XRC(31,422,1), X_MASK, E6500, PPCNONE, {CT, RA0, RB}},
++{"dcblq.", XRC(31,422,1), X_MASK, E6500, 0, {CT, RA0, RB}},
+
+-{"divde", XO(31,425,0,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
+-{"divde.", XO(31,425,0,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
+-{"divwe", XO(31,427,0,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
+-{"divwe.", XO(31,427,0,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
++{"divde", XO(31,425,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
++{"divde.", XO(31,425,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
++{"divwe", XO(31,427,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
++{"divwe.", XO(31,427,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
+
+-{"stxvll", X(31,429), XX1_MASK, PPCVSX3, PPCNONE, {XS6, RA0, RB}},
++{"stxvll", X(31,429), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
+
+-{"clrbhrb", X(31,430), 0xffffffff, POWER8, PPCNONE, {0}},
++{"clrbhrb", X(31,430), 0xffffffff, POWER8, 0, {0}},
+
+-{"slbie", X(31,434), XRTRA_MASK, PPC64, PPCNONE, {RB}},
++{"slbie", X(31,434), XRTRA_MASK, PPC64, 0, {RB}},
+
+-{"mtvsrdd", X(31,435), XX1_MASK, PPCVSX3, PPCNONE, {XT6, RA0, RB}},
++{"mtvsrdd", X(31,435), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
+
+-{"lwzmx", X(31,437), X_MASK, POWER9, PPCNONE, {RT, RA0, RB}},
++{"lwzmx", X(31,437), X_MASK, POWER9, 0, {RT, RA0, RB}},
+
+-{"ecowx", X(31,438), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
++{"ecowx", X(31,438), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
+
+-{"sthux", X(31,439), X_MASK, COM|PPCVLE, PPCNONE, {RS, RAS, RB}},
++{"sthux", X(31,439), X_MASK, COM, 0, {RS, RAS, RB}},
+
+-{"mdors", 0x7f9ce378, 0xffffffff, E500MC, PPCNONE, {0}},
++{"mdors", 0x7f9ce378, 0xffffffff, E500MC, 0, {0}},
+
+-{"miso", 0x7f5ad378, 0xffffffff, E6500, PPCNONE, {0}},
++{"miso", 0x7f5ad378, 0xffffffff, E6500, 0, {0}},
+
+ /* The "yield", "mdoio" and "mdoom" instructions are extended mnemonics for
+- "or rX,rX,rX", with rX being r27, r29 and r30 respectively. */
+-{"yield", 0x7f7bdb78, 0xffffffff, POWER7, PPCNONE, {0}},
+-{"mdoio", 0x7fbdeb78, 0xffffffff, POWER7, PPCNONE, {0}},
+-{"mdoom", 0x7fdef378, 0xffffffff, POWER7, PPCNONE, {0}},
+-{"mr", XRC(31,444,0), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RBS}},
+-{"or", XRC(31,444,0), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
+-{"mr.", XRC(31,444,1), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RBS}},
+-{"or.", XRC(31,444,1), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
+-
+-{"mtexisr", XSPR(31,451, 64), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mtexier", XSPR(31,451, 66), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mtdcr", X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476|PPCVLE, E500|TITAN, {SPR, RS}},
+-{"mtdcr.", XRC(31,451,1), X_MASK, PPCA2, PPCNONE, {SPR, RS}},
+-
+-{"stvexwx", X(31,453), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
+-
+-{"dccci", X(31,454), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, PPCNONE, {RAOPT, RBOPT}},
+-{"dci", X(31,454), XRARB_MASK, PPCA2|PPC476|PPCVLE, PPCNONE, {CT}},
+-
+-{"divdu", XO(31,457,0,0), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"divdu.", XO(31,457,0,1), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
+-
+-{"divwu", XO(31,459,0,0), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"divwu.", XO(31,459,0,1), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
+-
+-{"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300|PPCVLE, PPCNONE, {PMR, RS}},
+-{"mttmr", X(31,494), X_MASK, PPCTMR|E6500, PPCNONE, {TMR, RS}},
+-
+-{"slbieg", X(31,466), XRA_MASK, POWER9, PPCNONE, {RS, RB}},
+-
+-{"mtmq", XSPR(31,467, 0), XSPR_MASK, M601, PPCNONE, {RS}},
+-{"mtxer", XSPR(31,467, 1), XSPR_MASK, COM|PPCVLE, PPCNONE, {RS}},
+-{"mtlr", XSPR(31,467, 8), XSPR_MASK, COM|PPCVLE, PPCNONE, {RS}},
+-{"mtctr", XSPR(31,467, 9), XSPR_MASK, COM|PPCVLE, PPCNONE, {RS}},
+-{"mtdscr", XSPR(31,467, 17), XSPR_MASK, POWER6, PPCNONE, {RS}},
+-{"mttid", XSPR(31,467, 17), XSPR_MASK, POWER, PPCNONE, {RS}},
+-{"mtdsisr", XSPR(31,467, 18), XSPR_MASK, COM, TITAN, {RS}},
+-{"mtdar", XSPR(31,467, 19), XSPR_MASK, COM, TITAN, {RS}},
+-{"mtrtcu", XSPR(31,467, 20), XSPR_MASK, COM, TITAN, {RS}},
+-{"mtrtcl", XSPR(31,467, 21), XSPR_MASK, COM, TITAN, {RS}},
+-{"mtdec", XSPR(31,467, 22), XSPR_MASK, COM, PPCNONE, {RS}},
+-{"mtsdr0", XSPR(31,467, 24), XSPR_MASK, POWER, PPCNONE, {RS}},
+-{"mtsdr1", XSPR(31,467, 25), XSPR_MASK, COM, TITAN, {RS}},
+-{"mtsrr0", XSPR(31,467, 26), XSPR_MASK, COM|PPCVLE, PPCNONE, {RS}},
+-{"mtsrr1", XSPR(31,467, 27), XSPR_MASK, COM|PPCVLE, PPCNONE, {RS}},
+-{"mtcfar", XSPR(31,467, 28), XSPR_MASK, POWER6, PPCNONE, {RS}},
+-{"mtpid", XSPR(31,467, 48), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+-{"mtdecar", XSPR(31,467, 54), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+-{"mtcsrr0", XSPR(31,467, 58), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+-{"mtcsrr1", XSPR(31,467, 59), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+-{"mtdear", XSPR(31,467, 61), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+-{"mtesr", XSPR(31,467, 62), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+-{"mtivpr", XSPR(31,467, 63), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+-{"mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, PPCNONE, {RS}},
+-{"mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, PPCNONE, {RS}},
+-{"mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, PPCNONE, {RS}},
+-{"mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, PPCNONE, {RS}},
+-{"mticr", XSPR(31,467,148), XSPR_MASK, PPC860, PPCNONE, {RS}},
+-{"mtder", XSPR(31,467,149), XSPR_MASK, PPC860, PPCNONE, {RS}},
+-{"mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, PPCNONE, {RS}},
+-{"mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, PPCNONE, {RS}},
+-{"mtctrl", XSPR(31,467,152), XSPR_MASK, POWER4, PPCNONE, {RS}},
+-{"mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, PPCNONE, {RS}},
+-{"mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, PPCNONE, {RS}},
+-{"mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, PPCNONE, {RS}},
+-{"mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, PPCNONE, {RS}},
+-{"mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, PPCNONE, {RS}},
+-{"mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, PPCNONE, {RS}},
+-{"mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, PPCNONE, {RS}},
+-{"mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, PPCNONE, {RS}},
+-{"mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, PPCNONE, {RS}},
+-{"mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+-{"mtsprg", XSPR(31,467,256), XSPRG_MASK, PPC|PPCVLE, PPCNONE, {SPRG, RS}},
+-{"mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC|PPCVLE, PPCNONE, {RS}},
+-{"mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC|PPCVLE, PPCNONE, {RS}},
+-{"mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC|PPCVLE, PPCNONE, {RS}},
+-{"mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC|PPCVLE, PPCNONE, {RS}},
+-{"mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RS}},
+-{"mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RS}},
+-{"mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RS}},
+-{"mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RS}},
+-{"mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, PPCNONE, {RS}},
+-{"mtear", XSPR(31,467,282), XSPR_MASK, PPC, TITAN, {RS}},
+-{"mttbl", XSPR(31,467,284), XSPR_MASK, PPC, PPCNONE, {RS}},
+-{"mttbu", XSPR(31,467,285), XSPR_MASK, PPC, PPCNONE, {RS}},
+-{"mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+-{"mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+-{"mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+-{"mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+-{"mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+-{"mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+-{"mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+-{"mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+-{"mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+-{"mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+-{"mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+-{"mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+-{"mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+-{"mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+-{"mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+-{"mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+-{"mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+-{"mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+-{"mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+-{"mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+-{"mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+-{"mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+-{"mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+-{"mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+-{"mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+-{"mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+-{"mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+-{"mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+-{"mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+-{"mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+-{"mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, PPCNONE, {RS}},
+-{"mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, PPCNONE, {RS}},
+-{"mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, PPCNONE, {RS}},
+-{"mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, PPCNONE, {RS}},
+-{"mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
+-{"mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, PPCNONE, {RS}},
+-{"mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
+-{"mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, PPCNONE, {RS}},
+-{"mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, PPCNONE, {RS}},
+-{"mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
+-{"mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
+-{"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI|PPCVLE, PPCNONE, {RS}},
+-{"mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI|PPCVLE, PPCNONE, {RS}},
+-{"mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, PPCNONE, {RS}},
+-{"mtivndx", XSPR(31,467,880), XSPR_MASK, TITAN, PPCNONE, {RS}},
+-{"mtdvndx", XSPR(31,467,881), XSPR_MASK, TITAN, PPCNONE, {RS}},
+-{"mtivlim", XSPR(31,467,882), XSPR_MASK, TITAN, PPCNONE, {RS}},
+-{"mtdvlim", XSPR(31,467,883), XSPR_MASK, TITAN, PPCNONE, {RS}},
+-{"mtclcsr", XSPR(31,467,884), XSPR_MASK, TITAN, PPCNONE, {RS}},
+-{"mtccr1", XSPR(31,467,888), XSPR_MASK, TITAN, PPCNONE, {RS}},
+-{"mtppr", XSPR(31,467,896), XSPR_MASK, POWER7, PPCNONE, {RS}},
+-{"mtppr32", XSPR(31,467,898), XSPR_MASK, POWER7, PPCNONE, {RS}},
+-{"mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, PPCNONE, {RS}},
+-{"mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, PPCNONE, {RS}},
+-{"mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, PPCNONE, {RS}},
+-{"mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, PPCNONE, {RS}},
+-{"mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, PPCNONE, {RS}},
+-{"mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, PPCNONE, {RS}},
+-{"mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, PPCNONE, {RS}},
+-{"mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mtrmmucr", XSPR(31,467,946), XSPR_MASK, TITAN, PPCNONE, {RS}},
+-{"mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405|TITAN, PPCNONE, {RS}},
+-{"mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, PPCNONE, {RS}},
+-{"mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, PPCNONE, {RS}},
+-{"mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, PPCNONE, {RS}},
+-{"mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, PPCNONE, {RS}},
+-{"mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, PPCNONE, {RS}},
+-{"mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, PPCNONE, {RS}},
+-{"mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, PPCNONE, {RS}},
+-{"mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, PPCNONE, {RS}},
+-{"mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, PPCNONE, {RS}},
+-{"mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, PPCNONE, {RS}},
+-{"mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, PPCNONE, {RS}},
+-{"mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, PPCNONE, {RS}},
+-{"mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, PPCNONE, {RS}},
+-{"mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, PPCNONE, {RS}},
+-{"mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mtdbdr", XSPR(31,467,1011), XSPR_MASK, TITAN, PPCNONE, {RS}},
+-{"mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, PPCNONE, {RS}},
+-{"mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, PPCNONE, {RS}},
+-{"mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, PPCNONE, {RS}},
+-{"mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, PPCNONE, {RS}},
+-{"mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, PPCNONE, {RS}},
+-{"mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, PPCNONE, {RS}},
+-{"mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, PPCNONE, {RS}},
+-{"mtspr", X(31,467), X_MASK, COM|PPCVLE, PPCNONE, {SPR, RS}},
+-
+-{"dcbi", X(31,470), XRT_MASK, PPC|PPCVLE, PPCNONE, {RA0, RB}},
+-
+-{"nand", XRC(31,476,0), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
+-{"nand.", XRC(31,476,1), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
+-
+-{"dsn", X(31,483), XRT_MASK, E500MC|PPCVLE, PPCNONE, {RA, RB}},
+-
+-{"dcread", X(31,486), X_MASK, PPC403|PPC440|PPCVLE, PPCA2|PPC476, {RT, RA0, RB}},
+-
+-{"icbtls", X(31,486), X_MASK, PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA0, RB}},
+-
+-{"stvxl", X(31,487), X_MASK, PPCVEC|PPCVLE, PPCNONE, {VS, RA0, RB}},
+-
+-{"nabs", XO(31,488,0,0), XORB_MASK, M601, PPCNONE, {RT, RA}},
+-{"nabs.", XO(31,488,0,1), XORB_MASK, M601, PPCNONE, {RT, RA}},
+-
+-{"divd", XO(31,489,0,0), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"divd.", XO(31,489,0,1), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
+-
+-{"divw", XO(31,491,0,0), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"divw.", XO(31,491,0,1), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
+-
+-{"icbtlse", X(31,494), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},
+-
+-{"slbia", X(31,498), 0xff1fffff, POWER6, PPCNONE, {IH}},
++ "or rX,rX,rX", with rX being r27, r29 and r30 respectively. */
++{"yield", 0x7f7bdb78, 0xffffffff, POWER7, 0, {0}},
++{"mdoio", 0x7fbdeb78, 0xffffffff, POWER7, 0, {0}},
++{"mdoom", 0x7fdef378, 0xffffffff, POWER7, 0, {0}},
++{"mr", XRC(31,444,0), X_MASK, COM, 0, {RA, RS, RBS}},
++{"or", XRC(31,444,0), X_MASK, COM, 0, {RA, RS, RB}},
++{"mr.", XRC(31,444,1), X_MASK, COM, 0, {RA, RS, RBS}},
++{"or.", XRC(31,444,1), X_MASK, COM, 0, {RA, RS, RB}},
++
++{"mtexisr", XSPR(31,451, 64), XSPR_MASK, PPC403, 0, {RS}},
++{"mtexier", XSPR(31,451, 66), XSPR_MASK, PPC403, 0, {RS}},
++{"mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, 0, {RS}},
++{"mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, 0, {RS}},
++{"mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, 0, {RS}},
++{"mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, 0, {RS}},
++{"mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, 0, {RS}},
++{"mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, 0, {RS}},
++{"mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, 0, {RS}},
++{"mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, 0, {RS}},
++{"mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, 0, {RS}},
++{"mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, 0, {RS}},
++{"mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, 0, {RS}},
++{"mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, 0, {RS}},
++{"mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, 0, {RS}},
++{"mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, 0, {RS}},
++{"mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, 0, {RS}},
++{"mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, 0, {RS}},
++{"mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, 0, {RS}},
++{"mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, 0, {RS}},
++{"mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, 0, {RS}},
++{"mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, 0, {RS}},
++{"mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, 0, {RS}},
++{"mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, 0, {RS}},
++{"mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, 0, {RS}},
++{"mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, 0, {RS}},
++{"mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, 0, {RS}},
++{"mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, 0, {RS}},
++{"mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, 0, {RS}},
++{"mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, 0, {RS}},
++{"mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, 0, {RS}},
++{"mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, 0, {RS}},
++{"mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, 0, {RS}},
++{"mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, 0, {RS}},
++{"mtdcr", X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {SPR, RS}},
++{"mtdcr.", XRC(31,451,1), X_MASK, PPCA2, 0, {SPR, RS}},
++
++{"stvexwx", X(31,453), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
++
++{"dccci", X(31,454), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, 0, {RAOPT, RBOPT}},
++{"dci", X(31,454), XRARB_MASK, PPCA2|PPC476, 0, {CT}},
++
++{"divdu", XO(31,457,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
++{"divdu.", XO(31,457,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
++
++{"divwu", XO(31,459,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
++{"divwu.", XO(31,459,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
++
++{"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300, 0, {PMR, RS}},
++{"mttmr", X(31,494), X_MASK, PPCTMR|E6500, 0, {TMR, RS}},
++
++{"slbieg", X(31,466), XRA_MASK, POWER9, 0, {RS, RB}},
++
++{"mtmq", XSPR(31,467, 0), XSPR_MASK, M601, 0, {RS}},
++{"mtxer", XSPR(31,467, 1), XSPR_MASK, COM, 0, {RS}},
++{"mtlr", XSPR(31,467, 8), XSPR_MASK, COM, 0, {RS}},
++{"mtctr", XSPR(31,467, 9), XSPR_MASK, COM, 0, {RS}},
++{"mtdscr", XSPR(31,467, 17), XSPR_MASK, POWER6, 0, {RS}},
++{"mttid", XSPR(31,467, 17), XSPR_MASK, POWER, 0, {RS}},
++{"mtdsisr", XSPR(31,467, 18), XSPR_MASK, COM, TITAN, {RS}},
++{"mtdar", XSPR(31,467, 19), XSPR_MASK, COM, TITAN, {RS}},
++{"mtrtcu", XSPR(31,467, 20), XSPR_MASK, COM, TITAN, {RS}},
++{"mtrtcl", XSPR(31,467, 21), XSPR_MASK, COM, TITAN, {RS}},
++{"mtdec", XSPR(31,467, 22), XSPR_MASK, COM, 0, {RS}},
++{"mtsdr0", XSPR(31,467, 24), XSPR_MASK, POWER, 0, {RS}},
++{"mtsdr1", XSPR(31,467, 25), XSPR_MASK, COM, TITAN, {RS}},
++{"mtsrr0", XSPR(31,467, 26), XSPR_MASK, COM, 0, {RS}},
++{"mtsrr1", XSPR(31,467, 27), XSPR_MASK, COM, 0, {RS}},
++{"mtcfar", XSPR(31,467, 28), XSPR_MASK, POWER6, 0, {RS}},
++{"mtpid", XSPR(31,467, 48), XSPR_MASK, BOOKE, 0, {RS}},
++{"mtdecar", XSPR(31,467, 54), XSPR_MASK, BOOKE, 0, {RS}},
++{"mtcsrr0", XSPR(31,467, 58), XSPR_MASK, BOOKE, 0, {RS}},
++{"mtcsrr1", XSPR(31,467, 59), XSPR_MASK, BOOKE, 0, {RS}},
++{"mtdear", XSPR(31,467, 61), XSPR_MASK, BOOKE, 0, {RS}},
++{"mtesr", XSPR(31,467, 62), XSPR_MASK, BOOKE, 0, {RS}},
++{"mtivpr", XSPR(31,467, 63), XSPR_MASK, BOOKE, 0, {RS}},
++{"mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, 0, {RS}},
++{"mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, 0, {RS}},
++{"mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, 0, {RS}},
++{"mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, 0, {RS}},
++{"mticr", XSPR(31,467,148), XSPR_MASK, PPC860, 0, {RS}},
++{"mtder", XSPR(31,467,149), XSPR_MASK, PPC860, 0, {RS}},
++{"mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, 0, {RS}},
++{"mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, 0, {RS}},
++{"mtctrl", XSPR(31,467,152), XSPR_MASK, POWER4, 0, {RS}},
++{"mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, 0, {RS}},
++{"mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, 0, {RS}},
++{"mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, 0, {RS}},
++{"mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, 0, {RS}},
++{"mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, 0, {RS}},
++{"mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, 0, {RS}},
++{"mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, 0, {RS}},
++{"mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, 0, {RS}},
++{"mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, 0, {RS}},
++{"mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, 0, {RS}},
++{"mtsprg", XSPR(31,467,256), XSPRG_MASK, PPC, 0, {SPRG, RS}},
++{"mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, 0, {RS}},
++{"mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, 0, {RS}},
++{"mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, 0, {RS}},
++{"mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, 0, {RS}},
++{"mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE, 0, {RS}},
++{"mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE, 0, {RS}},
++{"mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE, 0, {RS}},
++{"mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE, 0, {RS}},
++{"mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, 0, {RS}},
++{"mtear", XSPR(31,467,282), XSPR_MASK, PPC, TITAN, {RS}},
++{"mttbl", XSPR(31,467,284), XSPR_MASK, PPC, 0, {RS}},
++{"mttbu", XSPR(31,467,285), XSPR_MASK, PPC, 0, {RS}},
++{"mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, 0, {RS}},
++{"mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, 0, {RS}},
++{"mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, 0, {RS}},
++{"mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, 0, {RS}},
++{"mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, 0, {RS}},
++{"mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, 0, {RS}},
++{"mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, 0, {RS}},
++{"mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, 0, {RS}},
++{"mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, 0, {RS}},
++{"mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, 0, {RS}},
++{"mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, 0, {RS}},
++{"mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, 0, {RS}},
++{"mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, 0, {RS}},
++{"mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, 0, {RS}},
++{"mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, 0, {RS}},
++{"mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, 0, {RS}},
++{"mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, 0, {RS}},
++{"mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, 0, {RS}},
++{"mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, 0, {RS}},
++{"mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, 0, {RS}},
++{"mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, 0, {RS}},
++{"mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, 0, {RS}},
++{"mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, 0, {RS}},
++{"mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, 0, {RS}},
++{"mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, 0, {RS}},
++{"mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, 0, {RS}},
++{"mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, 0, {RS}},
++{"mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, 0, {RS}},
++{"mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, 0, {RS}},
++{"mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, 0, {RS}},
++{"mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, 0, {RS}},
++{"mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, 0, {RS}},
++{"mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, 0, {RS}},
++{"mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, 0, {RS}},
++{"mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
++{"mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, 0, {RS}},
++{"mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
++{"mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, 0, {RS}},
++{"mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, 0, {RS}},
++{"mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
++{"mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
++{"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, 0, {RS}},
++{"mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, 0, {RS}},
++{"mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, 0, {RS}},
++{"mtivndx", XSPR(31,467,880), XSPR_MASK, TITAN, 0, {RS}},
++{"mtdvndx", XSPR(31,467,881), XSPR_MASK, TITAN, 0, {RS}},
++{"mtivlim", XSPR(31,467,882), XSPR_MASK, TITAN, 0, {RS}},
++{"mtdvlim", XSPR(31,467,883), XSPR_MASK, TITAN, 0, {RS}},
++{"mtclcsr", XSPR(31,467,884), XSPR_MASK, TITAN, 0, {RS}},
++{"mtccr1", XSPR(31,467,888), XSPR_MASK, TITAN, 0, {RS}},
++{"mtppr", XSPR(31,467,896), XSPR_MASK, POWER7, 0, {RS}},
++{"mtppr32", XSPR(31,467,898), XSPR_MASK, POWER7, 0, {RS}},
++{"mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, 0, {RS}},
++{"mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, 0, {RS}},
++{"mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, 0, {RS}},
++{"mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, 0, {RS}},
++{"mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, 0, {RS}},
++{"mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, 0, {RS}},
++{"mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, 0, {RS}},
++{"mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, 0, {RS}},
++{"mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, 0, {RS}},
++{"mtrmmucr", XSPR(31,467,946), XSPR_MASK, TITAN, 0, {RS}},
++{"mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405|TITAN, 0, {RS}},
++{"mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, 0, {RS}},
++{"mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, 0, {RS}},
++{"mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, 0, {RS}},
++{"mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, 0, {RS}},
++{"mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, 0, {RS}},
++{"mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, 0, {RS}},
++{"mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, 0, {RS}},
++{"mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, 0, {RS}},
++{"mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, 0, {RS}},
++{"mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, 0, {RS}},
++{"mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, 0, {RS}},
++{"mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, 0, {RS}},
++{"mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, 0, {RS}},
++{"mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, 0, {RS}},
++{"mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, 0, {RS}},
++{"mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, 0, {RS}},
++{"mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, 0, {RS}},
++{"mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, 0, {RS}},
++{"mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, 0, {RS}},
++{"mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, 0, {RS}},
++{"mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, 0, {RS}},
++{"mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, 0, {RS}},
++{"mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, 0, {RS}},
++{"mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, 0, {RS}},
++{"mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, 0, {RS}},
++{"mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, 0, {RS}},
++{"mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, 0, {RS}},
++{"mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, 0, {RS}},
++{"mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, 0, {RS}},
++{"mtdbdr", XSPR(31,467,1011), XSPR_MASK, TITAN, 0, {RS}},
++{"mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, 0, {RS}},
++{"mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, 0, {RS}},
++{"mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, 0, {RS}},
++{"mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, 0, {RS}},
++{"mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, 0, {RS}},
++{"mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, 0, {RS}},
++{"mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, 0, {RS}},
++{"mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, 0, {RS}},
++{"mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, 0, {RS}},
++{"mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, 0, {RS}},
++{"mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, 0, {RS}},
++{"mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, 0, {RS}},
++{"mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, 0, {RS}},
++{"mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, 0, {RS}},
++{"mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, 0, {RS}},
++{"mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, 0, {RS}},
++{"mtspr", X(31,467), X_MASK, COM, 0, {SPR, RS}},
++
++{"dcbi", X(31,470), XRT_MASK, PPC, 0, {RA0, RB}},
++
++{"nand", XRC(31,476,0), X_MASK, COM, 0, {RA, RS, RB}},
++{"nand.", XRC(31,476,1), X_MASK, COM, 0, {RA, RS, RB}},
++
++{"dsn", X(31,483), XRT_MASK, E500MC, 0, {RA, RB}},
++
++{"dcread", X(31,486), X_MASK, PPC403|PPC440, PPCA2|PPC476, {RT, RA0, RB}},
++
++{"icbtls", X(31,486), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
++
++{"stvxl", X(31,487), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
++
++{"nabs", XO(31,488,0,0), XORB_MASK, M601, 0, {RT, RA}},
++{"nabs.", XO(31,488,0,1), XORB_MASK, M601, 0, {RT, RA}},
++
++{"divd", XO(31,489,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
++{"divd.", XO(31,489,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
++
++{"divw", XO(31,491,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
++{"divw.", XO(31,491,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
++
++{"icbtlse", X(31,494), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},
++
++{"slbia", X(31,498), 0xff1fffff, POWER6, 0, {IH}},
+ {"slbia", X(31,498), 0xffffffff, PPC64, POWER6, {0}},
+
+-{"cli", X(31,502), XRB_MASK, POWER, PPCNONE, {RT, RA}},
++{"cli", X(31,502), XRB_MASK, POWER, 0, {RT, RA}},
+
+-{"popcntd", X(31,506), XRB_MASK, POWER7|PPCA2, PPCNONE, {RA, RS}},
++{"popcntd", X(31,506), XRB_MASK, POWER7|PPCA2, 0, {RA, RS}},
+
+-{"cmpb", X(31,508), X_MASK, POWER6|PPCA2|PPC476, PPCNONE, {RA, RS, RB}},
++{"cmpb", X(31,508), X_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS, RB}},
+
+-{"mcrxr", X(31,512), XBFRARB_MASK, COM|PPCVLE, POWER7, {BF}},
++{"mcrxr", X(31,512), XBFRARB_MASK, COM, POWER7, {BF}},
+
+-{"lbdx", X(31,515), X_MASK, E500MC|PPCVLE, PPCNONE, {RT, RA, RB}},
++{"lbdx", X(31,515), X_MASK, E500MC, 0, {RT, RA, RB}},
+
+-{"bblels", X(31,518), X_MASK, PPCBRLK, PPCNONE, {0}},
++{"bblels", X(31,518), X_MASK, PPCBRLK, 0, {0}},
+
+-{"lvlx", X(31,519), X_MASK, CELL, PPCNONE, {VD, RA0, RB}},
+-{"lbfcmux", APU(31,519,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
++{"lvlx", X(31,519), X_MASK, CELL, 0, {VD, RA0, RB}},
++{"lbfcmux", APU(31,519,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
+
+-{"subfco", XO(31,8,1,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"sfo", XO(31,8,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
+-{"subco", XO(31,8,1,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RB, RA}},
+-{"subfco.", XO(31,8,1,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
+-{"subco.", XO(31,8,1,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RB, RA}},
++{"subfco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
++{"sfo", XO(31,8,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
++{"subco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
++{"subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
++{"sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
++{"subco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
+
+-{"addco", XO(31,10,1,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"ao", XO(31,10,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
+-{"addco.", XO(31,10,1,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"ao.", XO(31,10,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
++{"addco", XO(31,10,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
++{"ao", XO(31,10,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
++{"addco.", XO(31,10,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
++{"ao.", XO(31,10,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
+
+-{"lxsspx", X(31,524), XX1_MASK, PPCVSX2, PPCNONE, {XT6, RA0, RB}},
++{"lxsspx", X(31,524), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},
+
+-{"clcs", X(31,531), XRB_MASK, M601, PPCNONE, {RT, RA}},
++{"clcs", X(31,531), XRB_MASK, M601, 0, {RT, RA}},
+
+-{"ldbrx", X(31,532), X_MASK, CELL|POWER7|PPCA2, PPCNONE, {RT, RA0, RB}},
++{"ldbrx", X(31,532), X_MASK, CELL|POWER7|PPCA2, 0, {RT, RA0, RB}},
+
+-{"lswx", X(31,533), X_MASK, PPCCOM|PPCVLE, E500|E500MC, {RT, RAX, RBX}},
+-{"lsx", X(31,533), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
++{"lswx", X(31,533), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, RBX}},
++{"lsx", X(31,533), X_MASK, PWRCOM, 0, {RT, RA, RB}},
+
+-{"lwbrx", X(31,534), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA0, RB}},
+-{"lbrx", X(31,534), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
++{"lwbrx", X(31,534), X_MASK, PPCCOM, 0, {RT, RA0, RB}},
++{"lbrx", X(31,534), X_MASK, PWRCOM, 0, {RT, RA, RB}},
+
+-{"lfsx", X(31,535), X_MASK, COM, PPCEFS, {FRT, RA0, RB}},
++{"lfsx", X(31,535), X_MASK, COM, PPCEFS, {FRT, RA0, RB}},
+
+-{"srw", XRC(31,536,0), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS, RB}},
+-{"sr", XRC(31,536,0), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}},
+-{"srw.", XRC(31,536,1), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS, RB}},
+-{"sr.", XRC(31,536,1), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}},
++{"srw", XRC(31,536,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
++{"sr", XRC(31,536,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
++{"srw.", XRC(31,536,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
++{"sr.", XRC(31,536,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
+
+-{"rrib", XRC(31,537,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
+-{"rrib.", XRC(31,537,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
++{"rrib", XRC(31,537,0), X_MASK, M601, 0, {RA, RS, RB}},
++{"rrib.", XRC(31,537,1), X_MASK, M601, 0, {RA, RS, RB}},
+
+-{"cnttzw", XRC(31,538,0), XRB_MASK, POWER9, PPCNONE, {RA, RS}},
+-{"cnttzw.", XRC(31,538,1), XRB_MASK, POWER9, PPCNONE, {RA, RS}},
++{"cnttzw", XRC(31,538,0), XRB_MASK, POWER9, 0, {RA, RS}},
++{"cnttzw.", XRC(31,538,1), XRB_MASK, POWER9, 0, {RA, RS}},
+
+-{"srd", XRC(31,539,0), X_MASK, PPC64, PPCNONE, {RA, RS, RB}},
+-{"srd.", XRC(31,539,1), X_MASK, PPC64, PPCNONE, {RA, RS, RB}},
++{"srd", XRC(31,539,0), X_MASK, PPC64, 0, {RA, RS, RB}},
++{"srd.", XRC(31,539,1), X_MASK, PPC64, 0, {RA, RS, RB}},
+
+-{"maskir", XRC(31,541,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
+-{"maskir.", XRC(31,541,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
++{"maskir", XRC(31,541,0), X_MASK, M601, 0, {RA, RS, RB}},
++{"maskir.", XRC(31,541,1), X_MASK, M601, 0, {RA, RS, RB}},
+
+-{"lhdx", X(31,547), X_MASK, E500MC|PPCVLE, PPCNONE, {RT, RA, RB}},
++{"lhdx", X(31,547), X_MASK, E500MC, 0, {RT, RA, RB}},
+
+-{"lvtrx", X(31,549), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
++{"lvtrx", X(31,549), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
+
+-{"bbelr", X(31,550), X_MASK, PPCBRLK, PPCNONE, {0}},
++{"bbelr", X(31,550), X_MASK, PPCBRLK, 0, {0}},
+
+-{"lvrx", X(31,551), X_MASK, CELL, PPCNONE, {VD, RA0, RB}},
+-{"lhfcmux", APU(31,551,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
++{"lvrx", X(31,551), X_MASK, CELL, 0, {VD, RA0, RB}},
++{"lhfcmux", APU(31,551,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
+
+-{"subfo", XO(31,40,1,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
+-{"subo", XO(31,40,1,0), XO_MASK, PPC, PPCNONE, {RT, RB, RA}},
+-{"subfo.", XO(31,40,1,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
+-{"subo.", XO(31,40,1,1), XO_MASK, PPC, PPCNONE, {RT, RB, RA}},
++{"subfo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
++{"subo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RB, RA}},
++{"subfo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
++{"subo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RB, RA}},
+
+-{"tlbsync", X(31,566), 0xffffffff, PPC|PPCVLE, PPCNONE, {0}},
++{"tlbsync", X(31,566), 0xffffffff, PPC, 0, {0}},
+
+-{"lfsux", X(31,567), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},
++{"lfsux", X(31,567), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},
+
+-{"cnttzd", XRC(31,570,0), XRB_MASK, POWER9, PPCNONE, {RA, RS}},
+-{"cnttzd.", XRC(31,570,1), XRB_MASK, POWER9, PPCNONE, {RA, RS}},
++{"cnttzd", XRC(31,570,0), XRB_MASK, POWER9, 0, {RA, RS}},
++{"cnttzd.", XRC(31,570,1), XRB_MASK, POWER9, 0, {RA, RS}},
+
+-{"mcrxrx", X(31,576), XBFRARB_MASK, POWER9, PPCNONE, {BF}},
++{"mcrxrx", X(31,576), XBFRARB_MASK, POWER9, 0, {BF}},
+
+-{"lwdx", X(31,579), X_MASK, E500MC|PPCVLE, PPCNONE, {RT, RA, RB}},
++{"lwdx", X(31,579), X_MASK, E500MC, 0, {RT, RA, RB}},
+
+-{"lvtlx", X(31,581), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
++{"lvtlx", X(31,581), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
+
+-{"lwat", X(31,582), X_MASK, POWER9, PPCNONE, {RT, RA0, FC}},
++{"lwat", X(31,582), X_MASK, POWER9, 0, {RT, RA0, FC}},
+
+-{"lwfcmux", APU(31,583,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
++{"lwfcmux", APU(31,583,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
+
+-{"lxsdx", X(31,588), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA0, RB}},
++{"lxsdx", X(31,588), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
+
+-{"mfsr", X(31,595), XRB_MASK|(1<<20), COM, NON32, {RT, SR}},
++{"mfsr", X(31,595), XRB_MASK|(1<<20), COM, NON32, {RT, SR}},
+
+-{"lswi", X(31,597), X_MASK, PPCCOM|PPCVLE, E500|E500MC, {RT, RAX, NBI}},
+-{"lsi", X(31,597), X_MASK, PWRCOM, PPCNONE, {RT, RA0, NB}},
++{"lswi", X(31,597), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, NBI}},
++{"lsi", X(31,597), X_MASK, PWRCOM, 0, {RT, RA0, NB}},
+
+ {"hwsync", XSYNC(31,598,0), 0xffffffff, POWER4, BOOKE|PPC476, {0}},
+ {"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, E500, {0}},
+-{"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, PPCNONE, {0}},
+-{"sync", X(31,598), XSYNCLE_MASK,POWER9|E6500, PPCNONE, {LS, ESYNC}},
+-{"sync", X(31,598), XSYNC_MASK, PPCCOM|PPCVLE, BOOKE|PPC476|POWER9, {LS}},
+-{"msync", X(31,598), 0xffffffff, BOOKE|PPCA2|PPC476, PPCNONE, {0}},
+-{"sync", X(31,598), 0xffffffff, BOOKE|PPC476, E6500, {0}},
+-{"lwsync", X(31,598), 0xffffffff, E500, PPCNONE, {0}},
+-{"dcs", X(31,598), 0xffffffff, PWRCOM, PPCNONE, {0}},
++{"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, 0, {0}},
++{"sync", X(31,598), XSYNCLE_MASK, POWER9|E6500, 0, {LS, ESYNC}},
++{"sync", X(31,598), XSYNC_MASK, PPCCOM, BOOKE|PPC476|POWER9, {LS}},
++{"msync", X(31,598), 0xffffffff, BOOKE|PPCA2|PPC476, 0, {0}},
++{"sync", X(31,598), 0xffffffff, BOOKE|PPC476, E6500, {0}},
++{"lwsync", X(31,598), 0xffffffff, E500, 0, {0}},
++{"dcs", X(31,598), 0xffffffff, PWRCOM, 0, {0}},
+
+-{"lfdx", X(31,599), X_MASK, COM, PPCEFS, {FRT, RA0, RB}},
++{"lfdx", X(31,599), X_MASK, COM, PPCEFS, {FRT, RA0, RB}},
+
+ {"mffgpr", XRC(31,607,0), XRA_MASK, POWER6, POWER7, {FRT, RB}},
+-{"lfdepx", X(31,607), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {FRT, RA0, RB}},
++{"lfdepx", X(31,607), X_MASK, E500MC|PPCA2, 0, {FRT, RA0, RB}},
+
+-{"lddx", X(31,611), X_MASK, E500MC|PPCVLE, PPCNONE, {RT, RA, RB}},
++{"lddx", X(31,611), X_MASK, E500MC, 0, {RT, RA, RB}},
+
+-{"lvswx", X(31,613), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
++{"lvswx", X(31,613), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
+
+-{"ldat", X(31,614), X_MASK, POWER9, PPCNONE, {RT, RA0, FC}},
++{"ldat", X(31,614), X_MASK, POWER9, 0, {RT, RA0, FC}},
+
+-{"lqfcmux", APU(31,615,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
++{"lqfcmux", APU(31,615,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
+
+-{"nego", XO(31,104,1,0), XORB_MASK, COM|PPCVLE, PPCNONE, {RT, RA}},
+-{"nego.", XO(31,104,1,1), XORB_MASK, COM|PPCVLE, PPCNONE, {RT, RA}},
++{"nego", XO(31,104,1,0), XORB_MASK, COM, 0, {RT, RA}},
++{"nego.", XO(31,104,1,1), XORB_MASK, COM, 0, {RT, RA}},
+
+-{"mulo", XO(31,107,1,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
+-{"mulo.", XO(31,107,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
++{"mulo", XO(31,107,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
++{"mulo.", XO(31,107,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
+
+-{"mfsri", X(31,627), X_MASK, M601, PPCNONE, {RT, RA, RB}},
++{"mfsri", X(31,627), X_MASK, M601, 0, {RT, RA, RB}},
+
+-{"dclst", X(31,630), XRB_MASK, M601, PPCNONE, {RS, RA}},
++{"dclst", X(31,630), XRB_MASK, M601, 0, {RS, RA}},
+
+-{"lfdux", X(31,631), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},
++{"lfdux", X(31,631), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},
+
+-{"stbdx", X(31,643), X_MASK, E500MC, PPCNONE, {RS, RA, RB}},
++{"stbdx", X(31,643), X_MASK, E500MC, 0, {RS, RA, RB}},
+
+-{"stvlx", X(31,647), X_MASK, CELL, PPCNONE, {VS, RA0, RB}},
+-{"stbfcmux", APU(31,647,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
++{"stvlx", X(31,647), X_MASK, CELL, 0, {VS, RA0, RB}},
++{"stbfcmux", APU(31,647,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
+
+-{"stxsspx", X(31,652), XX1_MASK, PPCVSX2, PPCNONE, {XS6, RA0, RB}},
++{"stxsspx", X(31,652), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}},
+
+-{"tbegin.", XRC(31,654,1), XRTLRARB_MASK,PPCHTM, PPCNONE, {HTM_R}},
++{"tbegin.", XRC(31,654,1), XRTLRARB_MASK, PPCHTM, 0, {HTM_R}},
+
+-{"subfeo", XO(31,136,1,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
+-{"subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
++{"subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
++{"sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
++{"subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
++{"sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
+
+-{"addeo", XO(31,138,1,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"aeo", XO(31,138,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
+-{"addeo.", XO(31,138,1,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
++{"addeo", XO(31,138,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
++{"aeo", XO(31,138,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
++{"addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
++{"aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
+
+-{"mfsrin", X(31,659), XRA_MASK, PPC, NON32, {RT, RB}},
++{"mfsrin", X(31,659), XRA_MASK, PPC, NON32, {RT, RB}},
+
+-{"stdbrx", X(31,660), X_MASK, CELL|POWER7|PPCA2, PPCNONE, {RS, RA0, RB}},
++{"stdbrx", X(31,660), X_MASK, CELL|POWER7|PPCA2, 0, {RS, RA0, RB}},
+
+-{"stswx", X(31,661), X_MASK, PPCCOM|PPCVLE, E500|E500MC, {RS, RA0, RB}},
+-{"stsx", X(31,661), X_MASK, PWRCOM, PPCNONE, {RS, RA0, RB}},
++{"stswx", X(31,661), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, RB}},
++{"stsx", X(31,661), X_MASK, PWRCOM, 0, {RS, RA0, RB}},
+
+-{"stwbrx", X(31,662), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RS, RA0, RB}},
+-{"stbrx", X(31,662), X_MASK, PWRCOM, PPCNONE, {RS, RA0, RB}},
++{"stwbrx", X(31,662), X_MASK, PPCCOM, 0, {RS, RA0, RB}},
++{"stbrx", X(31,662), X_MASK, PWRCOM, 0, {RS, RA0, RB}},
+
+-{"stfsx", X(31,663), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
++{"stfsx", X(31,663), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
+
+-{"srq", XRC(31,664,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
+-{"srq.", XRC(31,664,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
++{"srq", XRC(31,664,0), X_MASK, M601, 0, {RA, RS, RB}},
++{"srq.", XRC(31,664,1), X_MASK, M601, 0, {RA, RS, RB}},
+
+-{"sre", XRC(31,665,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
+-{"sre.", XRC(31,665,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
++{"sre", XRC(31,665,0), X_MASK, M601, 0, {RA, RS, RB}},
++{"sre.", XRC(31,665,1), X_MASK, M601, 0, {RA, RS, RB}},
+
+-{"sthdx", X(31,675), X_MASK, E500MC, PPCNONE, {RS, RA, RB}},
++{"sthdx", X(31,675), X_MASK, E500MC, 0, {RS, RA, RB}},
+
+-{"stvfrx", X(31,677), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
++{"stvfrx", X(31,677), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
+
+-{"stvrx", X(31,679), X_MASK, CELL, PPCNONE, {VS, RA0, RB}},
+-{"sthfcmux", APU(31,679,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
++{"stvrx", X(31,679), X_MASK, CELL, 0, {VS, RA0, RB}},
++{"sthfcmux", APU(31,679,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
+
+-{"tendall.", XRC(31,686,1)|(1<<25), XRTRARB_MASK, PPCHTM, PPCNONE, {0}},
+-{"tend.", XRC(31,686,1), XRTARARB_MASK, PPCHTM, PPCNONE, {HTM_A}},
++{"tendall.", XRC(31,686,1)|(1<<25), XRTRARB_MASK, PPCHTM, 0, {0}},
++{"tend.", XRC(31,686,1), XRTARARB_MASK, PPCHTM, 0, {HTM_A}},
+
+-{"stbcx.", XRC(31,694,1), X_MASK, POWER8|E6500, PPCNONE, {RS, RA0, RB}},
++{"stbcx.", XRC(31,694,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}},
+
+-{"stfsux", X(31,695), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},
++{"stfsux", X(31,695), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},
+
+-{"sriq", XRC(31,696,0), X_MASK, M601, PPCNONE, {RA, RS, SH}},
+-{"sriq.", XRC(31,696,1), X_MASK, M601, PPCNONE, {RA, RS, SH}},
++{"sriq", XRC(31,696,0), X_MASK, M601, 0, {RA, RS, SH}},
++{"sriq.", XRC(31,696,1), X_MASK, M601, 0, {RA, RS, SH}},
+
+-{"stwdx", X(31,707), X_MASK, E500MC, PPCNONE, {RS, RA, RB}},
++{"stwdx", X(31,707), X_MASK, E500MC, 0, {RS, RA, RB}},
+
+-{"stvflx", X(31,709), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
++{"stvflx", X(31,709), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
+
+-{"stwat", X(31,710), X_MASK, POWER9, PPCNONE, {RS, RA0, FC}},
++{"stwat", X(31,710), X_MASK, POWER9, 0, {RS, RA0, FC}},
+
+-{"stwfcmux", APU(31,711,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
++{"stwfcmux", APU(31,711,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
+
+-{"stxsdx", X(31,716), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA0, RB}},
++{"stxsdx", X(31,716), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}},
+
+-{"tcheck", X(31,718), XRTBFRARB_MASK, PPCHTM, PPCNONE, {BF}},
++{"tcheck", X(31,718), XRTBFRARB_MASK, PPCHTM, 0, {BF}},
+
+-{"subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}},
+-{"sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
+-{"subfzeo.", XO(31,200,1,1), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}},
+-{"sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
++{"subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
++{"sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
++{"subfzeo.", XO(31,200,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
++{"sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
+
+-{"addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}},
+-{"azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
+-{"addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}},
+-{"azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
++{"addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
++{"azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
++{"addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
++{"azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
+
+-{"stswi", X(31,725), X_MASK, PPCCOM|PPCVLE, E500|E500MC, {RS, RA0, NB}},
+-{"stsi", X(31,725), X_MASK, PWRCOM, PPCNONE, {RS, RA0, NB}},
++{"stswi", X(31,725), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, NB}},
++{"stsi", X(31,725), X_MASK, PWRCOM, 0, {RS, RA0, NB}},
+
+-{"sthcx.", XRC(31,726,1), X_MASK, POWER8|E6500, PPCNONE, {RS, RA0, RB}},
++{"sthcx.", XRC(31,726,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}},
+
+-{"stfdx", X(31,727), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
++{"stfdx", X(31,727), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
+
+-{"srlq", XRC(31,728,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
+-{"srlq.", XRC(31,728,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
++{"srlq", XRC(31,728,0), X_MASK, M601, 0, {RA, RS, RB}},
++{"srlq.", XRC(31,728,1), X_MASK, M601, 0, {RA, RS, RB}},
+
+-{"sreq", XRC(31,729,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
+-{"sreq.", XRC(31,729,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
++{"sreq", XRC(31,729,0), X_MASK, M601, 0, {RA, RS, RB}},
++{"sreq.", XRC(31,729,1), X_MASK, M601, 0, {RA, RS, RB}},
+
+ {"mftgpr", XRC(31,735,0), XRA_MASK, POWER6, POWER7, {RT, FRB}},
+-{"stfdepx", X(31,735), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {FRS, RA0, RB}},
++{"stfdepx", X(31,735), X_MASK, E500MC|PPCA2, 0, {FRS, RA0, RB}},
+
+-{"stddx", X(31,739), X_MASK, E500MC, PPCNONE, {RS, RA, RB}},
++{"stddx", X(31,739), X_MASK, E500MC, 0, {RS, RA, RB}},
+
+-{"stvswx", X(31,741), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
++{"stvswx", X(31,741), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
+
+-{"stdat", X(31,742), X_MASK, POWER9, PPCNONE, {RS, RA0, FC}},
++{"stdat", X(31,742), X_MASK, POWER9, 0, {RS, RA0, FC}},
+
+-{"stqfcmux", APU(31,743,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
++{"stqfcmux", APU(31,743,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
+
+-{"subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
+-{"sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
+-{"subfmeo.", XO(31,232,1,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
+-{"sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
++{"subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
++{"sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
++{"subfmeo.", XO(31,232,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
++{"sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
+
+-{"mulldo", XO(31,233,1,0), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"mulldo.", XO(31,233,1,1), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
++{"mulldo", XO(31,233,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
++{"mulldo.", XO(31,233,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
+
+-{"addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}},
+-{"ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
+-{"addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}},
+-{"ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
++{"addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
++{"ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
++{"addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
++{"ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
+
+-{"mullwo", XO(31,235,1,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"mulso", XO(31,235,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
+-{"mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
++{"mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
++{"mulso", XO(31,235,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
++{"mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
++{"mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
+
+-{"tsuspend.", XRCL(31,750,0,1), XRTRARB_MASK,PPCHTM, PPCNONE, {0}},
+-{"tresume.", XRCL(31,750,1,1), XRTRARB_MASK,PPCHTM, PPCNONE, {0}},
+-{"tsr.", XRC(31,750,1), XRTLRARB_MASK,PPCHTM, PPCNONE, {L}},
++{"tsuspend.", XRCL(31,750,0,1), XRTRARB_MASK,PPCHTM, 0, {0}},
++{"tresume.", XRCL(31,750,1,1), XRTRARB_MASK,PPCHTM, 0, {0}},
++{"tsr.", XRC(31,750,1), XRTLRARB_MASK,PPCHTM, 0, {L}},
+
+-{"darn", X(31,755), XLRAND_MASK, POWER9, PPCNONE, {RT, LRAND}},
++{"darn", X(31,755), XLRAND_MASK, POWER9, 0, {RT, LRAND}},
+
+-{"dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {RA0, RB}},
+-{"dcbal", XOPL(31,758,1), XRT_MASK, E500MC, PPCNONE, {RA0, RB}},
++{"dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476, 0, {RA0, RB}},
++{"dcbal", XOPL(31,758,1), XRT_MASK, E500MC, 0, {RA0, RB}},
+
+-{"stfdux", X(31,759), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},
++{"stfdux", X(31,759), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},
+
+-{"srliq", XRC(31,760,0), X_MASK, M601, PPCNONE, {RA, RS, SH}},
+-{"srliq.", XRC(31,760,1), X_MASK, M601, PPCNONE, {RA, RS, SH}},
++{"srliq", XRC(31,760,0), X_MASK, M601, 0, {RA, RS, SH}},
++{"srliq.", XRC(31,760,1), X_MASK, M601, 0, {RA, RS, SH}},
+
+-{"lvsm", X(31,773), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
++{"lvsm", X(31,773), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
+
+-{"copy_first", XOPL(31,774,1), XRT_MASK, POWER9, PPCNONE, {RA0, RB}},
+-{"copy", X(31,774), XLRT_MASK, POWER9, PPCNONE, {RA0, RB, L}},
++{"copy_first", XOPL(31,774,1), XRT_MASK, POWER9, 0, {RA0, RB}},
++{"copy", X(31,774), XLRT_MASK, POWER9, 0, {RA0, RB, L}},
+
+-{"stvepxl", X(31,775), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
+-{"lvlxl", X(31,775), X_MASK, CELL, PPCNONE, {VD, RA0, RB}},
+-{"ldfcmux", APU(31,775,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
++{"stvepxl", X(31,775), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
++{"lvlxl", X(31,775), X_MASK, CELL, 0, {VD, RA0, RB}},
++{"ldfcmux", APU(31,775,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
+
+-{"dozo", XO(31,264,1,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
+-{"dozo.", XO(31,264,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
++{"dozo", XO(31,264,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
++{"dozo.", XO(31,264,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
+
+-{"addo", XO(31,266,1,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"caxo", XO(31,266,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
+-{"addo.", XO(31,266,1,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
++{"addo", XO(31,266,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
++{"caxo", XO(31,266,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
++{"addo.", XO(31,266,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
++{"caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
+
+-{"modsd", X(31,777), X_MASK, POWER9, PPCNONE, {RT, RA, RB}},
+-{"modsw", X(31,779), X_MASK, POWER9, PPCNONE, {RT, RA, RB}},
++{"modsd", X(31,777), X_MASK, POWER9, 0, {RT, RA, RB}},
++{"modsw", X(31,779), X_MASK, POWER9, 0, {RT, RA, RB}},
+
+-{"lxvw4x", X(31,780), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA0, RB}},
+-{"lxsibzx", X(31,781), XX1_MASK, PPCVSX3, PPCNONE, {XT6, RA0, RB}},
++{"lxvw4x", X(31,780), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
++{"lxsibzx", X(31,781), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
+
+-{"tabortwc.", XRC(31,782,1), X_MASK, PPCHTM, PPCNONE, {TO, RA, RB}},
++{"tabortwc.", XRC(31,782,1), X_MASK, PPCHTM, 0, {TO, RA, RB}},
+
+-{"tlbivax", X(31,786), XRT_MASK, BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {RA0, RB}},
++{"tlbivax", X(31,786), XRT_MASK, BOOKE|PPCA2|PPC476, 0, {RA0, RB}},
+
+-{"lwzcix", X(31,789), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}},
++{"lwzcix", X(31,789), X_MASK, POWER6, 0, {RT, RA0, RB}},
+
+-{"lhbrx", X(31,790), X_MASK, COM|PPCVLE, PPCNONE, {RT, RA0, RB}},
++{"lhbrx", X(31,790), X_MASK, COM, 0, {RT, RA0, RB}},
+
+-{"lfdpx", X(31,791), X_MASK, POWER6, POWER7, {FRTp, RA0, RB}},
+-{"lfqx", X(31,791), X_MASK, POWER2, PPCNONE, {FRT, RA, RB}},
++{"lfdpx", X(31,791), X_MASK, POWER6, POWER7, {FRTp, RA0, RB}},
++{"lfqx", X(31,791), X_MASK, POWER2, 0, {FRT, RA, RB}},
+
+-{"sraw", XRC(31,792,0), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS, RB}},
+-{"sra", XRC(31,792,0), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}},
+-{"sraw.", XRC(31,792,1), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS, RB}},
+-{"sra.", XRC(31,792,1), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}},
++{"sraw", XRC(31,792,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
++{"sra", XRC(31,792,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
++{"sraw.", XRC(31,792,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
++{"sra.", XRC(31,792,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
+
+-{"srad", XRC(31,794,0), X_MASK, PPC64, PPCNONE, {RA, RS, RB}},
+-{"srad.", XRC(31,794,1), X_MASK, PPC64, PPCNONE, {RA, RS, RB}},
++{"srad", XRC(31,794,0), X_MASK, PPC64, 0, {RA, RS, RB}},
++{"srad.", XRC(31,794,1), X_MASK, PPC64, 0, {RA, RS, RB}},
+
+-{"lfddx", X(31,803), X_MASK, E500MC|PPCVLE, PPCNONE, {FRT, RA, RB}},
++{"lfddx", X(31,803), X_MASK, E500MC, 0, {FRT, RA, RB}},
+
+-{"lvtrxl", X(31,805), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
+-{"stvepx", X(31,807), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
+-{"lvrxl", X(31,807), X_MASK, CELL, PPCNONE, {VD, RA0, RB}},
++{"lvtrxl", X(31,805), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
++{"stvepx", X(31,807), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
++{"lvrxl", X(31,807), X_MASK, CELL, 0, {VD, RA0, RB}},
+
+-{"lxvh8x", X(31,812), XX1_MASK, PPCVSX3, PPCNONE, {XT6, RA0, RB}},
+-{"lxsihzx", X(31,813), XX1_MASK, PPCVSX3, PPCNONE, {XT6, RA0, RB}},
++{"lxvh8x", X(31,812), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
++{"lxsihzx", X(31,813), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
+
+-{"tabortdc.", XRC(31,814,1), X_MASK, PPCHTM, PPCNONE, {TO, RA, RB}},
++{"tabortdc.", XRC(31,814,1), X_MASK, PPCHTM, 0, {TO, RA, RB}},
+
+-{"rac", X(31,818), X_MASK, M601, PPCNONE, {RT, RA, RB}},
++{"rac", X(31,818), X_MASK, M601, 0, {RT, RA, RB}},
+
+-{"erativax", X(31,819), X_MASK, PPCA2, PPCNONE, {RS, RA0, RB}},
++{"erativax", X(31,819), X_MASK, PPCA2, 0, {RS, RA0, RB}},
+
+-{"lhzcix", X(31,821), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}},
++{"lhzcix", X(31,821), X_MASK, POWER6, 0, {RT, RA0, RB}},
+
+-{"dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, PPCNONE, {STRM}},
++{"dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, 0, {STRM}},
+
+-{"lfqux", X(31,823), X_MASK, POWER2, PPCNONE, {FRT, RA, RB}},
++{"lfqux", X(31,823), X_MASK, POWER2, 0, {FRT, RA, RB}},
+
+-{"srawi", XRC(31,824,0), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS, SH}},
+-{"srai", XRC(31,824,0), X_MASK, PWRCOM, PPCNONE, {RA, RS, SH}},
+-{"srawi.", XRC(31,824,1), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS, SH}},
+-{"srai.", XRC(31,824,1), X_MASK, PWRCOM, PPCNONE, {RA, RS, SH}},
++{"srawi", XRC(31,824,0), X_MASK, PPCCOM, 0, {RA, RS, SH}},
++{"srai", XRC(31,824,0), X_MASK, PWRCOM, 0, {RA, RS, SH}},
++{"srawi.", XRC(31,824,1), X_MASK, PPCCOM, 0, {RA, RS, SH}},
++{"srai.", XRC(31,824,1), X_MASK, PWRCOM, 0, {RA, RS, SH}},
+
+-{"sradi", XS(31,413,0), XS_MASK, PPC64|PPCVLE, PPCNONE, {RA, RS, SH6}},
+-{"sradi.", XS(31,413,1), XS_MASK, PPC64|PPCVLE, PPCNONE, {RA, RS, SH6}},
++{"sradi", XS(31,413,0), XS_MASK, PPC64, 0, {RA, RS, SH6}},
++{"sradi.", XS(31,413,1), XS_MASK, PPC64, 0, {RA, RS, SH6}},
+
+-{"lvtlxl", X(31,837), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
++{"lvtlxl", X(31,837), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
+
+-{"cp_abort", X(31,838), XRTRARB_MASK,POWER9, PPCNONE, {0}},
++{"cp_abort", X(31,838), XRTRARB_MASK,POWER9, 0, {0}},
+
+-{"divo", XO(31,331,1,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
+-{"divo.", XO(31,331,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
++{"divo", XO(31,331,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
++{"divo.", XO(31,331,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
+
+-{"lxvd2x", X(31,844), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA0, RB}},
++{"lxvd2x", X(31,844), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
+ {"lxvx", X(31,844), XX1_MASK, POWER8, POWER9|PPCVSX3, {XT6, RA0, RB}},
+
+-{"tabortwci.", XRC(31,846,1), X_MASK, PPCHTM, PPCNONE, {TO, RA, HTM_SI}},
++{"tabortwci.", XRC(31,846,1), X_MASK, PPCHTM, 0, {TO, RA, HTM_SI}},
+
+-{"tlbsrx.", XRC(31,850,1), XRT_MASK, PPCA2, PPCNONE, {RA0, RB}},
++{"tlbsrx.", XRC(31,850,1), XRT_MASK, PPCA2, 0, {RA0, RB}},
+
+-{"slbmfev", X(31,851), XRLA_MASK, POWER9, PPCNONE, {RT, RB, A_L}},
++{"slbmfev", X(31,851), XRLA_MASK, POWER9, 0, {RT, RB, A_L}},
+ {"slbmfev", X(31,851), XRA_MASK, PPC64, POWER9, {RT, RB}},
+
+-{"lbzcix", X(31,853), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}},
++{"lbzcix", X(31,853), X_MASK, POWER6, 0, {RT, RA0, RB}},
+
+ {"eieio", X(31,854), 0xffffffff, PPC, BOOKE|PPCA2|PPC476, {0}},
+-{"mbar", X(31,854), X_MASK, BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {MO}},
+-{"eieio", XMBAR(31,854,1),0xffffffff, E500, PPCNONE, {0}},
+-{"eieio", X(31,854), 0xffffffff, PPCA2|PPC476, PPCNONE, {0}},
++{"mbar", X(31,854), X_MASK, BOOKE|PPCA2|PPC476, 0, {MO}},
++{"eieio", XMBAR(31,854,1),0xffffffff, E500, 0, {0}},
++{"eieio", X(31,854), 0xffffffff, PPCA2|PPC476, 0, {0}},
+
+-{"lfiwax", X(31,855), X_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FRT, RA0, RB}},
++{"lfiwax", X(31,855), X_MASK, POWER6|PPCA2|PPC476, 0, {FRT, RA0, RB}},
+
+-{"lvswxl", X(31,869), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
++{"lvswxl", X(31,869), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
+
+-{"abso", XO(31,360,1,0), XORB_MASK, M601, PPCNONE, {RT, RA}},
+-{"abso.", XO(31,360,1,1), XORB_MASK, M601, PPCNONE, {RT, RA}},
++{"abso", XO(31,360,1,0), XORB_MASK, M601, 0, {RT, RA}},
++{"abso.", XO(31,360,1,1), XORB_MASK, M601, 0, {RT, RA}},
+
+-{"divso", XO(31,363,1,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
+-{"divso.", XO(31,363,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
++{"divso", XO(31,363,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
++{"divso.", XO(31,363,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
+
+-{"lxvb16x", X(31,876), XX1_MASK, PPCVSX3, PPCNONE, {XT6, RA0, RB}},
++{"lxvb16x", X(31,876), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
+
+-{"tabortdci.", XRC(31,878,1), X_MASK, PPCHTM, PPCNONE, {TO, RA, HTM_SI}},
++{"tabortdci.", XRC(31,878,1), X_MASK, PPCHTM, 0, {TO, RA, HTM_SI}},
+
+-{"rmieg", X(31,882), XRTRA_MASK, POWER9, PPCNONE, {RB}},
++{"rmieg", X(31,882), XRTRA_MASK, POWER9, 0, {RB}},
+
+-{"ldcix", X(31,885), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}},
++{"ldcix", X(31,885), X_MASK, POWER6, 0, {RT, RA0, RB}},
+
+-{"msgsync", X(31,886), 0xffffffff, POWER9, PPCNONE, {0}},
++{"msgsync", X(31,886), 0xffffffff, POWER9, 0, {0}},
+
+-{"lfiwzx", X(31,887), X_MASK, POWER7|PPCA2, PPCNONE, {FRT, RA0, RB}},
++{"lfiwzx", X(31,887), X_MASK, POWER7|PPCA2, 0, {FRT, RA0, RB}},
+
+-{"extswsli", XS(31,445,0), XS_MASK, POWER9, PPCNONE, {RA, RS, SH6}},
+-{"extswsli.", XS(31,445,1), XS_MASK, POWER9, PPCNONE, {RA, RS, SH6}},
++{"extswsli", XS(31,445,0), XS_MASK, POWER9, 0, {RA, RS, SH6}},
++{"extswsli.", XS(31,445,1), XS_MASK, POWER9, 0, {RA, RS, SH6}},
+
+-{"paste", XRC(31,902,0), XLRT_MASK, POWER9, PPCNONE, {RA0, RB, L0}},
+-{"paste_last", XRCL(31,902,1,1),XRT_MASK, POWER9, PPCNONE, {RA0, RB}},
+-{"paste.", XRC(31,902,1), XLRT_MASK, POWER9, PPCNONE, {RA0, RB, L1}},
++{"paste", XRC(31,902,0), XLRT_MASK, POWER9, 0, {RA0, RB, L0}},
++{"paste_last", XRCL(31,902,1,1),XRT_MASK, POWER9, 0, {RA0, RB}},
++{"paste.", XRC(31,902,1), XLRT_MASK, POWER9, 0, {RA0, RB, L1}},
+
+-{"stvlxl", X(31,903), X_MASK, CELL, PPCNONE, {VS, RA0, RB}},
+-{"stdfcmux", APU(31,903,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
++{"stvlxl", X(31,903), X_MASK, CELL, 0, {VS, RA0, RB}},
++{"stdfcmux", APU(31,903,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
+
+-{"divdeuo", XO(31,393,1,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
+-{"divdeuo.", XO(31,393,1,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
+-{"divweuo", XO(31,395,1,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
+-{"divweuo.", XO(31,395,1,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
++{"divdeuo", XO(31,393,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
++{"divdeuo.", XO(31,393,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
++{"divweuo", XO(31,395,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
++{"divweuo.", XO(31,395,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
+
+-{"stxvw4x", X(31,908), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA0, RB}},
+-{"stxsibx", X(31,909), XX1_MASK, PPCVSX3, PPCNONE, {XS6, RA0, RB}},
++{"stxvw4x", X(31,908), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}},
++{"stxsibx", X(31,909), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
+
+-{"tabort.", XRC(31,910,1), XRTRB_MASK, PPCHTM, PPCNONE, {RA}},
++{"tabort.", XRC(31,910,1), XRTRB_MASK, PPCHTM, 0, {RA}},
+
+-{"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RTO, RA0, RB}},
+-{"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RTO, RA0, RB}},
++{"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}},
++{"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}},
+
+-{"slbmfee", X(31,915), XRLA_MASK, POWER9, PPCNONE, {RT, RB, A_L}},
++{"slbmfee", X(31,915), XRLA_MASK, POWER9, 0, {RT, RB, A_L}},
+ {"slbmfee", X(31,915), XRA_MASK, PPC64, POWER9, {RT, RB}},
+
+-{"stwcix", X(31,917), X_MASK, POWER6, PPCNONE, {RS, RA0, RB}},
++{"stwcix", X(31,917), X_MASK, POWER6, 0, {RS, RA0, RB}},
+
+-{"sthbrx", X(31,918), X_MASK, COM, PPCNONE, {RS, RA0, RB}},
++{"sthbrx", X(31,918), X_MASK, COM, 0, {RS, RA0, RB}},
+
+-{"stfdpx", X(31,919), X_MASK, POWER6, POWER7, {FRSp, RA0, RB}},
+-{"stfqx", X(31,919), X_MASK, POWER2, PPCNONE, {FRS, RA0, RB}},
++{"stfdpx", X(31,919), X_MASK, POWER6, POWER7, {FRSp, RA0, RB}},
++{"stfqx", X(31,919), X_MASK, POWER2, 0, {FRS, RA0, RB}},
+
+-{"sraq", XRC(31,920,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
+-{"sraq.", XRC(31,920,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
++{"sraq", XRC(31,920,0), X_MASK, M601, 0, {RA, RS, RB}},
++{"sraq.", XRC(31,920,1), X_MASK, M601, 0, {RA, RS, RB}},
+
+-{"srea", XRC(31,921,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
+-{"srea.", XRC(31,921,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
++{"srea", XRC(31,921,0), X_MASK, M601, 0, {RA, RS, RB}},
++{"srea.", XRC(31,921,1), X_MASK, M601, 0, {RA, RS, RB}},
+
+-{"extsh", XRC(31,922,0), XRB_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS}},
+-{"exts", XRC(31,922,0), XRB_MASK, PWRCOM, PPCNONE, {RA, RS}},
+-{"extsh.", XRC(31,922,1), XRB_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS}},
+-{"exts.", XRC(31,922,1), XRB_MASK, PWRCOM, PPCNONE, {RA, RS}},
++{"extsh", XRC(31,922,0), XRB_MASK, PPCCOM, 0, {RA, RS}},
++{"exts", XRC(31,922,0), XRB_MASK, PWRCOM, 0, {RA, RS}},
++{"extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, 0, {RA, RS}},
++{"exts.", XRC(31,922,1), XRB_MASK, PWRCOM, 0, {RA, RS}},
+
+-{"stfddx", X(31,931), X_MASK, E500MC, PPCNONE, {FRS, RA, RB}},
++{"stfddx", X(31,931), X_MASK, E500MC, 0, {FRS, RA, RB}},
+
+-{"stvfrxl", X(31,933), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
++{"stvfrxl", X(31,933), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
+
+-{"wclrone", XOPL2(31,934,2),XRT_MASK, PPCA2, PPCNONE, {RA0, RB}},
+-{"wclrall", X(31,934), XRARB_MASK, PPCA2, PPCNONE, {L}},
+-{"wclr", X(31,934), X_MASK, PPCA2, PPCNONE, {L, RA0, RB}},
++{"wclrone", XOPL2(31,934,2),XRT_MASK, PPCA2, 0, {RA0, RB}},
++{"wclrall", X(31,934), XRARB_MASK, PPCA2, 0, {L}},
++{"wclr", X(31,934), X_MASK, PPCA2, 0, {L, RA0, RB}},
+
+-{"stvrxl", X(31,935), X_MASK, CELL, PPCNONE, {VS, RA0, RB}},
++{"stvrxl", X(31,935), X_MASK, CELL, 0, {VS, RA0, RB}},
+
+-{"divdeo", XO(31,425,1,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
+-{"divdeo.", XO(31,425,1,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
+-{"divweo", XO(31,427,1,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
+-{"divweo.", XO(31,427,1,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
++{"divdeo", XO(31,425,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
++{"divdeo.", XO(31,425,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
++{"divweo", XO(31,427,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
++{"divweo.", XO(31,427,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
+
+-{"stxvh8x", X(31,940), XX1_MASK, PPCVSX3, PPCNONE, {XS6, RA0, RB}},
+-{"stxsihx", X(31,941), XX1_MASK, PPCVSX3, PPCNONE, {XS6, RA0, RB}},
++{"stxvh8x", X(31,940), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
++{"stxsihx", X(31,941), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
+
+-{"treclaim.", XRC(31,942,1), XRTRB_MASK, PPCHTM, PPCNONE, {RA}},
++{"treclaim.", XRC(31,942,1), XRTRB_MASK, PPCHTM, 0, {RA}},
+
+ {"tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, PPCA2, {RT, RA}},
+ {"tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, PPCA2, {RT, RA}},
+-{"tlbre", X(31,946), X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RSO, RAOPT, SHO}},
++{"tlbre", X(31,946), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RSO, RAOPT, SHO}},
+
+-{"sthcix", X(31,949), X_MASK, POWER6, PPCNONE, {RS, RA0, RB}},
++{"sthcix", X(31,949), X_MASK, POWER6, 0, {RS, RA0, RB}},
+
+-{"icswepx", XRC(31,950,0), X_MASK, PPCA2, PPCNONE, {RS, RA, RB}},
+-{"icswepx.", XRC(31,950,1), X_MASK, PPCA2, PPCNONE, {RS, RA, RB}},
++{"icswepx", XRC(31,950,0), X_MASK, PPCA2, 0, {RS, RA, RB}},
++{"icswepx.", XRC(31,950,1), X_MASK, PPCA2, 0, {RS, RA, RB}},
+
+-{"stfqux", X(31,951), X_MASK, POWER2, PPCNONE, {FRS, RA, RB}},
++{"stfqux", X(31,951), X_MASK, POWER2, 0, {FRS, RA, RB}},
+
+-{"sraiq", XRC(31,952,0), X_MASK, M601, PPCNONE, {RA, RS, SH}},
+-{"sraiq.", XRC(31,952,1), X_MASK, M601, PPCNONE, {RA, RS, SH}},
++{"sraiq", XRC(31,952,0), X_MASK, M601, 0, {RA, RS, SH}},
++{"sraiq.", XRC(31,952,1), X_MASK, M601, 0, {RA, RS, SH}},
+
+-{"extsb", XRC(31,954,0), XRB_MASK, PPC|PPCVLE, PPCNONE, {RA, RS}},
+-{"extsb.", XRC(31,954,1), XRB_MASK, PPC|PPCVLE, PPCNONE, {RA, RS}},
++{"extsb", XRC(31,954,0), XRB_MASK, PPC, 0, {RA, RS}},
++{"extsb.", XRC(31,954,1), XRB_MASK, PPC, 0, {RA, RS}},
+
+-{"stvflxl", X(31,965), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
++{"stvflxl", X(31,965), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
+
+-{"iccci", X(31,966), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, PPCNONE, {RAOPT, RBOPT}},
+-{"ici", X(31,966), XRARB_MASK, PPCA2|PPC476|PPCVLE, PPCNONE, {CT}},
++{"iccci", X(31,966), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, 0, {RAOPT, RBOPT}},
++{"ici", X(31,966), XRARB_MASK, PPCA2|PPC476, 0, {CT}},
+
+-{"divduo", XO(31,457,1,0), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"divduo.", XO(31,457,1,1), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
++{"divduo", XO(31,457,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
++{"divduo.", XO(31,457,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
+
+-{"divwuo", XO(31,459,1,0), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"divwuo.", XO(31,459,1,1), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
++{"divwuo", XO(31,459,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
++{"divwuo.", XO(31,459,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
+
+-{"stxvd2x", X(31,972), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA0, RB}},
++{"stxvd2x", X(31,972), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}},
+ {"stxvx", X(31,972), XX1_MASK, POWER8, POWER9|PPCVSX3, {XS6, RA0, RB}},
+
+ {"tlbld", X(31,978), XRTRA_MASK, PPC, PPC403|BOOKE|PPCA2|PPC476, {RB}},
+-{"tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, PPCNONE, {RT, RA}},
+-{"tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, PPCNONE, {RT, RA}},
+-{"tlbwe", X(31,978), X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RSO, RAOPT, SHO}},
++{"tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, 0, {RT, RA}},
++{"tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, 0, {RT, RA}},
++{"tlbwe", X(31,978), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RSO, RAOPT, SHO}},
+
+-{"slbfee.", XRC(31,979,1), XRA_MASK, POWER6, PPCNONE, {RT, RB}},
++{"slbfee.", XRC(31,979,1), XRA_MASK, POWER6, 0, {RT, RB}},
+
+-{"stbcix", X(31,981), X_MASK, POWER6, PPCNONE, {RS, RA0, RB}},
++{"stbcix", X(31,981), X_MASK, POWER6, 0, {RS, RA0, RB}},
+
+-{"icbi", X(31,982), XRT_MASK, PPC|PPCVLE, PPCNONE, {RA0, RB}},
++{"icbi", X(31,982), XRT_MASK, PPC, 0, {RA0, RB}},
+
+-{"stfiwx", X(31,983), X_MASK, PPC, PPCEFS, {FRS, RA0, RB}},
++{"stfiwx", X(31,983), X_MASK, PPC, PPCEFS, {FRS, RA0, RB}},
+
+-{"extsw", XRC(31,986,0), XRB_MASK, PPC64|PPCVLE, PPCNONE, {RA, RS}},
+-{"extsw.", XRC(31,986,1), XRB_MASK, PPC64|PPCVLE, PPCNONE, {RA, RS}},
++{"extsw", XRC(31,986,0), XRB_MASK, PPC64, 0, {RA, RS}},
++{"extsw.", XRC(31,986,1), XRB_MASK, PPC64, 0, {RA, RS}},
+
+-{"icbiep", XRT(31,991,0), XRT_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RA0, RB}},
++{"icbiep", XRT(31,991,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
+
+-{"stvswxl", X(31,997), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
++{"stvswxl", X(31,997), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
+
+-{"icread", X(31,998), XRT_MASK, PPC403|PPC440|PPC476|TITAN|PPCVLE, PPCNONE, {RA0, RB}},
++{"icread", X(31,998), XRT_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA0, RB}},
+
+-{"nabso", XO(31,488,1,0), XORB_MASK, M601, PPCNONE, {RT, RA}},
+-{"nabso.", XO(31,488,1,1), XORB_MASK, M601, PPCNONE, {RT, RA}},
++{"nabso", XO(31,488,1,0), XORB_MASK, M601, 0, {RT, RA}},
++{"nabso.", XO(31,488,1,1), XORB_MASK, M601, 0, {RT, RA}},
+
+-{"divdo", XO(31,489,1,0), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"divdo.", XO(31,489,1,1), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
++{"divdo", XO(31,489,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
++{"divdo.", XO(31,489,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
+
+-{"divwo", XO(31,491,1,0), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
+-{"divwo.", XO(31,491,1,1), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
++{"divwo", XO(31,491,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
++{"divwo.", XO(31,491,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
+
+-{"stxvb16x", X(31,1004), XX1_MASK, PPCVSX3, PPCNONE, {XS6, RA0, RB}},
++{"stxvb16x", X(31,1004), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
+
+-{"trechkpt.", XRC(31,1006,1), XRTRARB_MASK,PPCHTM, PPCNONE, {0}},
++{"trechkpt.", XRC(31,1006,1), XRTRARB_MASK,PPCHTM, 0, {0}},
+
+-{"tlbli", X(31,1010), XRTRA_MASK, PPC, TITAN, {RB}},
++{"tlbli", X(31,1010), XRTRA_MASK, PPC, TITAN, {RB}},
+
+-{"stdcix", X(31,1013), X_MASK, POWER6, PPCNONE, {RS, RA0, RB}},
++{"stdcix", X(31,1013), X_MASK, POWER6, 0, {RS, RA0, RB}},
+
+-{"dcbz", X(31,1014), XRT_MASK, PPC|PPCVLE, PPCNONE, {RA0, RB}},
+-{"dclz", X(31,1014), XRT_MASK, PPC, PPCNONE, {RA0, RB}},
++{"dcbz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}},
++{"dclz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}},
+
+-{"dcbzep", XRT(31,1023,0), XRT_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RA0, RB}},
++{"dcbzep", XRT(31,1023,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
+
+-{"dcbzl", XOPL(31,1014,1), XRT_MASK, POWER4|E500MC, PPC476, {RA0, RB}},
++{"dcbzl", XOPL(31,1014,1), XRT_MASK, POWER4|E500MC, PPC476, {RA0, RB}},
+
+-{"cctpl", 0x7c210b78, 0xffffffff, CELL, PPCNONE, {0}},
+-{"cctpm", 0x7c421378, 0xffffffff, CELL, PPCNONE, {0}},
+-{"cctph", 0x7c631b78, 0xffffffff, CELL, PPCNONE, {0}},
++{"cctpl", 0x7c210b78, 0xffffffff, CELL, 0, {0}},
++{"cctpm", 0x7c421378, 0xffffffff, CELL, 0, {0}},
++{"cctph", 0x7c631b78, 0xffffffff, CELL, 0, {0}},
+
+-{"dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, PPCNONE, {RA, RB, STRM}},
+-{"dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, PPCNONE, {RA, RB, STRM}},
+-{"dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, PPCNONE, {0}},
++{"dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
++{"dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
++{"dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, 0, {0}},
+
+-{"db8cyc", 0x7f9ce378, 0xffffffff, CELL, PPCNONE, {0}},
+-{"db10cyc", 0x7fbdeb78, 0xffffffff, CELL, PPCNONE, {0}},
+-{"db12cyc", 0x7fdef378, 0xffffffff, CELL, PPCNONE, {0}},
+-{"db16cyc", 0x7ffffb78, 0xffffffff, CELL, PPCNONE, {0}},
++{"db8cyc", 0x7f9ce378, 0xffffffff, CELL, 0, {0}},
++{"db10cyc", 0x7fbdeb78, 0xffffffff, CELL, 0, {0}},
++{"db12cyc", 0x7fdef378, 0xffffffff, CELL, 0, {0}},
++{"db16cyc", 0x7ffffb78, 0xffffffff, CELL, 0, {0}},
+
+-{"lwz", OP(32), OP_MASK, PPCCOM, PPCNONE, {RT, D, RA0}},
+-{"l", OP(32), OP_MASK, PWRCOM, PPCNONE, {RT, D, RA0}},
++{"lwz", OP(32), OP_MASK, PPCCOM, PPCVLE, {RT, D, RA0}},
++{"l", OP(32), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
+
+-{"lwzu", OP(33), OP_MASK, PPCCOM, PPCNONE, {RT, D, RAL}},
+-{"lu", OP(33), OP_MASK, PWRCOM, PPCNONE, {RT, D, RA0}},
++{"lwzu", OP(33), OP_MASK, PPCCOM, PPCVLE, {RT, D, RAL}},
++{"lu", OP(33), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
+
+-{"lbz", OP(34), OP_MASK, COM, PPCNONE, {RT, D, RA0}},
++{"lbz", OP(34), OP_MASK, COM, PPCVLE, {RT, D, RA0}},
+
+-{"lbzu", OP(35), OP_MASK, COM, PPCNONE, {RT, D, RAL}},
++{"lbzu", OP(35), OP_MASK, COM, PPCVLE, {RT, D, RAL}},
+
+-{"stw", OP(36), OP_MASK, PPCCOM, PPCNONE, {RS, D, RA0}},
+-{"st", OP(36), OP_MASK, PWRCOM, PPCNONE, {RS, D, RA0}},
++{"stw", OP(36), OP_MASK, PPCCOM, PPCVLE, {RS, D, RA0}},
++{"st", OP(36), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}},
+
+-{"stwu", OP(37), OP_MASK, PPCCOM, PPCNONE, {RS, D, RAS}},
+-{"stu", OP(37), OP_MASK, PWRCOM, PPCNONE, {RS, D, RA0}},
++{"stwu", OP(37), OP_MASK, PPCCOM, PPCVLE, {RS, D, RAS}},
++{"stu", OP(37), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}},
+
+-{"stb", OP(38), OP_MASK, COM, PPCNONE, {RS, D, RA0}},
++{"stb", OP(38), OP_MASK, COM, PPCVLE, {RS, D, RA0}},
+
+-{"stbu", OP(39), OP_MASK, COM, PPCNONE, {RS, D, RAS}},
++{"stbu", OP(39), OP_MASK, COM, PPCVLE, {RS, D, RAS}},
+
+-{"lhz", OP(40), OP_MASK, COM, PPCNONE, {RT, D, RA0}},
++{"lhz", OP(40), OP_MASK, COM, PPCVLE, {RT, D, RA0}},
+
+-{"lhzu", OP(41), OP_MASK, COM, PPCNONE, {RT, D, RAL}},
++{"lhzu", OP(41), OP_MASK, COM, PPCVLE, {RT, D, RAL}},
+
+-{"lha", OP(42), OP_MASK, COM, PPCNONE, {RT, D, RA0}},
++{"lha", OP(42), OP_MASK, COM, PPCVLE, {RT, D, RA0}},
+
+-{"lhau", OP(43), OP_MASK, COM, PPCNONE, {RT, D, RAL}},
++{"lhau", OP(43), OP_MASK, COM, PPCVLE, {RT, D, RAL}},
+
+-{"sth", OP(44), OP_MASK, COM, PPCNONE, {RS, D, RA0}},
++{"sth", OP(44), OP_MASK, COM, PPCVLE, {RS, D, RA0}},
+
+-{"sthu", OP(45), OP_MASK, COM, PPCNONE, {RS, D, RAS}},
++{"sthu", OP(45), OP_MASK, COM, PPCVLE, {RS, D, RAS}},
+
+-{"lmw", OP(46), OP_MASK, PPCCOM, PPCNONE, {RT, D, RAM}},
+-{"lm", OP(46), OP_MASK, PWRCOM, PPCNONE, {RT, D, RA0}},
++{"lmw", OP(46), OP_MASK, PPCCOM, PPCVLE, {RT, D, RAM}},
++{"lm", OP(46), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
+
+-{"stmw", OP(47), OP_MASK, PPCCOM, PPCNONE, {RS, D, RA0}},
+-{"stm", OP(47), OP_MASK, PWRCOM, PPCNONE, {RS, D, RA0}},
++{"stmw", OP(47), OP_MASK, PPCCOM, PPCVLE, {RS, D, RA0}},
++{"stm", OP(47), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}},
+
+-{"lfs", OP(48), OP_MASK, COM, PPCEFS, {FRT, D, RA0}},
++{"lfs", OP(48), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RA0}},
+
+-{"lfsu", OP(49), OP_MASK, COM, PPCEFS, {FRT, D, RAS}},
++{"lfsu", OP(49), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RAS}},
+
+-{"lfd", OP(50), OP_MASK, COM, PPCEFS, {FRT, D, RA0}},
++{"lfd", OP(50), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RA0}},
+
+-{"lfdu", OP(51), OP_MASK, COM, PPCEFS, {FRT, D, RAS}},
++{"lfdu", OP(51), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RAS}},
+
+-{"stfs", OP(52), OP_MASK, COM, PPCEFS, {FRS, D, RA0}},
++{"stfs", OP(52), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RA0}},
+
+-{"stfsu", OP(53), OP_MASK, COM, PPCEFS, {FRS, D, RAS}},
++{"stfsu", OP(53), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RAS}},
+
+-{"stfd", OP(54), OP_MASK, COM, PPCEFS, {FRS, D, RA0}},
++{"stfd", OP(54), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RA0}},
+
+-{"stfdu", OP(55), OP_MASK, COM, PPCEFS, {FRS, D, RAS}},
++{"stfdu", OP(55), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RAS}},
+
+-{"lq", OP(56), OP_MASK, POWER4, PPC476, {RTQ, DQ, RAQ}},
+-{"psq_l", OP(56), OP_MASK, PPCPS, PPCNONE, {FRT,PSD,RA,PSW,PSQ}},
+-{"lfq", OP(56), OP_MASK, POWER2, PPCNONE, {FRT, D, RA0}},
++{"lq", OP(56), OP_MASK, POWER4, PPC476|PPCVLE, {RTQ, DQ, RAQ}},
++{"psq_l", OP(56), OP_MASK, PPCPS, PPCVLE, {FRT,PSD,RA,PSW,PSQ}},
++{"lfq", OP(56), OP_MASK, POWER2, PPCVLE, {FRT, D, RA0}},
+
+-{"lxsd", DSO(57,2), DS_MASK, PPCVSX3, PPCNONE, {VD, DS, RA0}},
+-{"lxssp", DSO(57,3), DS_MASK, PPCVSX3, PPCNONE, {VD, DS, RA0}},
+-{"lfdp", OP(57), OP_MASK, POWER6, POWER7, {FRTp, DS, RA0}},
+-{"psq_lu", OP(57), OP_MASK, PPCPS, PPCNONE, {FRT,PSD,RA,PSW,PSQ}},
+-{"lfqu", OP(57), OP_MASK, POWER2, PPCNONE, {FRT, D, RA0}},
++{"lxsd", DSO(57,2), DS_MASK, PPCVSX3, PPCVLE, {VD, DS, RA0}},
++{"lxssp", DSO(57,3), DS_MASK, PPCVSX3, PPCVLE, {VD, DS, RA0}},
++{"lfdp", OP(57), OP_MASK, POWER6, POWER7|PPCVLE, {FRTp, DS, RA0}},
++{"psq_lu", OP(57), OP_MASK, PPCPS, PPCVLE, {FRT,PSD,RA,PSW,PSQ}},
++{"lfqu", OP(57), OP_MASK, POWER2, PPCVLE, {FRT, D, RA0}},
+
+-{"ld", DSO(58,0), DS_MASK, PPC64, PPCNONE, {RT, DS, RA0}},
+-{"ldu", DSO(58,1), DS_MASK, PPC64, PPCNONE, {RT, DS, RAL}},
+-{"lwa", DSO(58,2), DS_MASK, PPC64, PPCNONE, {RT, DS, RA0}},
++{"ld", DSO(58,0), DS_MASK, PPC64, PPCVLE, {RT, DS, RA0}},
++{"ldu", DSO(58,1), DS_MASK, PPC64, PPCVLE, {RT, DS, RAL}},
++{"lwa", DSO(58,2), DS_MASK, PPC64, PPCVLE, {RT, DS, RA0}},
+
+-{"dadd", XRC(59,2,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
+-{"dadd.", XRC(59,2,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
++{"dadd", XRC(59,2,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
++{"dadd.", XRC(59,2,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
+
+-{"dqua", ZRC(59,3,0), Z2_MASK, POWER6, PPCNONE, {FRT,FRA,FRB,RMC}},
+-{"dqua.", ZRC(59,3,1), Z2_MASK, POWER6, PPCNONE, {FRT,FRA,FRB,RMC}},
++{"dqua", ZRC(59,3,0), Z2_MASK, POWER6, PPCVLE, {FRT,FRA,FRB,RMC}},
++{"dqua.", ZRC(59,3,1), Z2_MASK, POWER6, PPCVLE, {FRT,FRA,FRB,RMC}},
+
+-{"fdivs", A(59,18,0), AFRC_MASK, PPC, PPCEFS, {FRT, FRA, FRB}},
+-{"fdivs.", A(59,18,1), AFRC_MASK, PPC, PPCEFS, {FRT, FRA, FRB}},
++{"fdivs", A(59,18,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
++{"fdivs.", A(59,18,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
+
+-{"fsubs", A(59,20,0), AFRC_MASK, PPC, PPCEFS, {FRT, FRA, FRB}},
+-{"fsubs.", A(59,20,1), AFRC_MASK, PPC, PPCEFS, {FRT, FRA, FRB}},
++{"fsubs", A(59,20,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
++{"fsubs.", A(59,20,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
+
+-{"fadds", A(59,21,0), AFRC_MASK, PPC, PPCEFS, {FRT, FRA, FRB}},
+-{"fadds.", A(59,21,1), AFRC_MASK, PPC, PPCEFS, {FRT, FRA, FRB}},
++{"fadds", A(59,21,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
++{"fadds.", A(59,21,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
+
+-{"fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, TITAN, {FRT, FRB}},
+-{"fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, TITAN, {FRT, FRB}},
++{"fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, TITAN|PPCVLE, {FRT, FRB}},
++{"fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, TITAN|PPCVLE, {FRT, FRB}},
+
+-{"fres", A(59,24,0), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}},
+-{"fres", A(59,24,0), AFRALFRC_MASK, PPC, POWER7, {FRT, FRB, A_L}},
+-{"fres.", A(59,24,1), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}},
+-{"fres.", A(59,24,1), AFRALFRC_MASK, PPC, POWER7, {FRT, FRB, A_L}},
++{"fres", A(59,24,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
++{"fres", A(59,24,0), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
++{"fres.", A(59,24,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
++{"fres.", A(59,24,1), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
+
+-{"fmuls", A(59,25,0), AFRB_MASK, PPC, PPCEFS, {FRT, FRA, FRC}},
+-{"fmuls.", A(59,25,1), AFRB_MASK, PPC, PPCEFS, {FRT, FRA, FRC}},
++{"fmuls", A(59,25,0), AFRB_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
++{"fmuls.", A(59,25,1), AFRB_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
+
+-{"frsqrtes", A(59,26,0), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}},
+-{"frsqrtes", A(59,26,0), AFRALFRC_MASK, POWER5, POWER7, {FRT, FRB, A_L}},
+-{"frsqrtes.", A(59,26,1), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}},
+-{"frsqrtes.", A(59,26,1), AFRALFRC_MASK, POWER5, POWER7, {FRT, FRB, A_L}},
++{"frsqrtes", A(59,26,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
++{"frsqrtes", A(59,26,0), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}},
++{"frsqrtes.", A(59,26,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
++{"frsqrtes.", A(59,26,1), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}},
+
+-{"fmsubs", A(59,28,0), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}},
+-{"fmsubs.", A(59,28,1), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}},
++{"fmsubs", A(59,28,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
++{"fmsubs.", A(59,28,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
+
+-{"fmadds", A(59,29,0), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}},
+-{"fmadds.", A(59,29,1), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}},
++{"fmadds", A(59,29,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
++{"fmadds.", A(59,29,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
+
+-{"fnmsubs", A(59,30,0), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}},
+-{"fnmsubs.", A(59,30,1), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}},
++{"fnmsubs", A(59,30,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
++{"fnmsubs.", A(59,30,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
+
+-{"fnmadds", A(59,31,0), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}},
+-{"fnmadds.", A(59,31,1), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}},
++{"fnmadds", A(59,31,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
++{"fnmadds.", A(59,31,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
+
+-{"dmul", XRC(59,34,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
+-{"dmul.", XRC(59,34,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
++{"dmul", XRC(59,34,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
++{"dmul.", XRC(59,34,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
+
+-{"drrnd", ZRC(59,35,0), Z2_MASK, POWER6, PPCNONE, {FRT, FRA, FRB, RMC}},
+-{"drrnd.", ZRC(59,35,1), Z2_MASK, POWER6, PPCNONE, {FRT, FRA, FRB, RMC}},
++{"drrnd", ZRC(59,35,0), Z2_MASK, POWER6, PPCVLE, {FRT, FRA, FRB, RMC}},
++{"drrnd.", ZRC(59,35,1), Z2_MASK, POWER6, PPCVLE, {FRT, FRA, FRB, RMC}},
+
+-{"dscli", ZRC(59,66,0), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}},
+-{"dscli.", ZRC(59,66,1), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}},
++{"dscli", ZRC(59,66,0), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
++{"dscli.", ZRC(59,66,1), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
+
+-{"dquai", ZRC(59,67,0), Z2_MASK, POWER6, PPCNONE, {TE, FRT,FRB,RMC}},
+-{"dquai.", ZRC(59,67,1), Z2_MASK, POWER6, PPCNONE, {TE, FRT,FRB,RMC}},
++{"dquai", ZRC(59,67,0), Z2_MASK, POWER6, PPCVLE, {TE, FRT,FRB,RMC}},
++{"dquai.", ZRC(59,67,1), Z2_MASK, POWER6, PPCVLE, {TE, FRT,FRB,RMC}},
+
+-{"dscri", ZRC(59,98,0), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}},
+-{"dscri.", ZRC(59,98,1), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}},
++{"dscri", ZRC(59,98,0), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
++{"dscri.", ZRC(59,98,1), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
+
+-{"drintx", ZRC(59,99,0), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}},
+-{"drintx.", ZRC(59,99,1), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}},
++{"drintx", ZRC(59,99,0), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
++{"drintx.", ZRC(59,99,1), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
+
+-{"dcmpo", X(59,130), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}},
++{"dcmpo", X(59,130), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
+
+-{"dtstex", X(59,162), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}},
+-{"dtstdc", Z(59,194), Z_MASK, POWER6, PPCNONE, {BF, FRA, DCM}},
+-{"dtstdg", Z(59,226), Z_MASK, POWER6, PPCNONE, {BF, FRA, DGM}},
+-
+-{"drintn", ZRC(59,227,0), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}},
+-{"drintn.", ZRC(59,227,1), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}},
+-
+-{"dctdp", XRC(59,258,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
+-{"dctdp.", XRC(59,258,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
+-
+-{"dctfix", XRC(59,290,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
+-{"dctfix.", XRC(59,290,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
+-
+-{"ddedpd", XRC(59,322,0), X_MASK, POWER6, PPCNONE, {SP, FRT, FRB}},
+-{"ddedpd.", XRC(59,322,1), X_MASK, POWER6, PPCNONE, {SP, FRT, FRB}},
+-
+-{"dxex", XRC(59,354,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
+-{"dxex.", XRC(59,354,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
+-
+-{"dsub", XRC(59,514,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
+-{"dsub.", XRC(59,514,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
+-
+-{"ddiv", XRC(59,546,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
+-{"ddiv.", XRC(59,546,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
+-
+-{"dcmpu", X(59,642), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}},
+-
+-{"dtstsf", X(59,674), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}},
+-{"dtstsfi", X(59,675), X_MASK|1<<22,POWER9, PPCNONE, {BF, UIM6, FRB}},
+-
+-{"drsp", XRC(59,770,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
+-{"drsp.", XRC(59,770,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
+-
+-{"dcffix", XRC(59,802,0), X_MASK|FRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
+-{"dcffix.", XRC(59,802,1), X_MASK|FRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
+-
+-{"denbcd", XRC(59,834,0), X_MASK, POWER6, PPCNONE, {S, FRT, FRB}},
+-{"denbcd.", XRC(59,834,1), X_MASK, POWER6, PPCNONE, {S, FRT, FRB}},
+-
+-{"fcfids", XRC(59,846,0), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
+-{"fcfids.", XRC(59,846,1), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
+-
+-{"diex", XRC(59,866,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
+-{"diex.", XRC(59,866,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
+-
+-{"fcfidus", XRC(59,974,0), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
+-{"fcfidus.", XRC(59,974,1), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
+-
+-{"xsaddsp", XX3(60,0), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}},
+-{"xsmaddasp", XX3(60,1), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}},
+-{"xxsldwi", XX3(60,2), XX3SHW_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6, SHW}},
+-{"xscmpeqdp", XX3(60,3), XX3_MASK, PPCVSX3, PPCNONE, {XT6, XA6, XB6}},
+-{"xsrsqrtesp", XX2(60,10), XX2_MASK, PPCVSX2, PPCNONE, {XT6, XB6}},
+-{"xssqrtsp", XX2(60,11), XX2_MASK, PPCVSX2, PPCNONE, {XT6, XB6}},
+-{"xxsel", XX4(60,3), XX4_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6, XC6}},
+-{"xssubsp", XX3(60,8), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}},
+-{"xsmaddmsp", XX3(60,9), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}},
+-{"xxspltd", XX3(60,10), XX3DM_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6S, DMEX}},
+-{"xxmrghd", XX3(60,10), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xxswapd", XX3(60,10)|(2<<8), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6S}},
+-{"xxmrgld", XX3(60,10)|(3<<8), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xxpermdi", XX3(60,10), XX3DM_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6, DM}},
+-{"xscmpgtdp", XX3(60,11), XX3_MASK, PPCVSX3, PPCNONE, {XT6, XA6, XB6}},
+-{"xsresp", XX2(60,26), XX2_MASK, PPCVSX2, PPCNONE, {XT6, XB6}},
+-{"xsmulsp", XX3(60,16), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}},
+-{"xsmsubasp", XX3(60,17), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}},
+-{"xxmrghw", XX3(60,18), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xscmpgedp", XX3(60,19), XX3_MASK, PPCVSX3, PPCNONE, {XT6, XA6, XB6}},
+-{"xsdivsp", XX3(60,24), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}},
+-{"xsmsubmsp", XX3(60,25), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}},
+-{"xxperm", XX3(60,26), XX3_MASK, PPCVSX3, PPCNONE, {XT6, XA6, XB6}},
+-{"xsadddp", XX3(60,32), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xsmaddadp", XX3(60,33), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xscmpudp", XX3(60,35), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}},
+-{"xscvdpuxws", XX2(60,72), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xsrdpi", XX2(60,73), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xsrsqrtedp", XX2(60,74), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xssqrtdp", XX2(60,75), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xssubdp", XX3(60,40), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xsmaddmdp", XX3(60,41), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xscmpodp", XX3(60,43), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}},
+-{"xscvdpsxws", XX2(60,88), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xsrdpiz", XX2(60,89), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xsredp", XX2(60,90), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xsmuldp", XX3(60,48), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xsmsubadp", XX3(60,49), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xxmrglw", XX3(60,50), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xsrdpip", XX2(60,105), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xstsqrtdp", XX2(60,106), XX2BF_MASK, PPCVSX, PPCNONE, {BF, XB6}},
+-{"xsrdpic", XX2(60,107), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xsdivdp", XX3(60,56), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xsmsubmdp", XX3(60,57), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xxpermr", XX3(60,58), XX3_MASK, PPCVSX3, PPCNONE, {XT6, XA6, XB6}},
+-{"xscmpexpdp", XX3(60,59), XX3BF_MASK, PPCVSX3, PPCNONE, {BF, XA6, XB6}},
+-{"xsrdpim", XX2(60,121), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xstdivdp", XX3(60,61), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}},
+-{"xvaddsp", XX3(60,64), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvmaddasp", XX3(60,65), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvcmpeqsp", XX3RC(60,67,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvcmpeqsp.", XX3RC(60,67,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvcvspuxws", XX2(60,136), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xvrspi", XX2(60,137), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xvrsqrtesp", XX2(60,138), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xvsqrtsp", XX2(60,139), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xvsubsp", XX3(60,72), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvmaddmsp", XX3(60,73), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvcmpgtsp", XX3RC(60,75,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvcmpgtsp.", XX3RC(60,75,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvcvspsxws", XX2(60,152), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xvrspiz", XX2(60,153), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xvresp", XX2(60,154), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xvmulsp", XX3(60,80), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvmsubasp", XX3(60,81), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xxspltw", XX2(60,164), XX2UIM_MASK, PPCVSX, PPCNONE, {XT6, XB6, UIM}},
+-{"xxextractuw", XX2(60,165), XX2UIM4_MASK,PPCVSX3, PPCNONE, {XT6, XB6, UIMM4}},
+-{"xvcmpgesp", XX3RC(60,83,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvcmpgesp.", XX3RC(60,83,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvcvuxwsp", XX2(60,168), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xvrspip", XX2(60,169), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xvtsqrtsp", XX2(60,170), XX2BF_MASK, PPCVSX, PPCNONE, {BF, XB6}},
+-{"xvrspic", XX2(60,171), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xvdivsp", XX3(60,88), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvmsubmsp", XX3(60,89), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xxspltib", X(60,360), XX1_MASK|3<<19, PPCVSX3,PPCNONE, {XT6, IMM8}},
+-{"xxinsertw", XX2(60,181), XX2UIM4_MASK,PPCVSX3, PPCNONE, {XT6, XB6, UIMM4}},
+-{"xvcvsxwsp", XX2(60,184), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xvrspim", XX2(60,185), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xvtdivsp", XX3(60,93), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}},
+-{"xvadddp", XX3(60,96), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvmaddadp", XX3(60,97), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvcmpeqdp", XX3RC(60,99,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvcmpeqdp.", XX3RC(60,99,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvcvdpuxws", XX2(60,200), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xvrdpi", XX2(60,201), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xvrsqrtedp", XX2(60,202), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xvsqrtdp", XX2(60,203), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xvsubdp", XX3(60,104), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvmaddmdp", XX3(60,105), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvcmpgtdp", XX3RC(60,107,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvcmpgtdp.", XX3RC(60,107,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvcvdpsxws", XX2(60,216), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xvrdpiz", XX2(60,217), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xvredp", XX2(60,218), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xvmuldp", XX3(60,112), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvmsubadp", XX3(60,113), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvcmpgedp", XX3RC(60,115,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvcmpgedp.", XX3RC(60,115,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvcvuxwdp", XX2(60,232), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xvrdpip", XX2(60,233), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xvtsqrtdp", XX2(60,234), XX2BF_MASK, PPCVSX, PPCNONE, {BF, XB6}},
+-{"xvrdpic", XX2(60,235), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xvdivdp", XX3(60,120), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvmsubmdp", XX3(60,121), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvcvsxwdp", XX2(60,248), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xvrdpim", XX2(60,249), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xvtdivdp", XX3(60,125), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}},
+-{"xsmaxcdp", XX3(60,128), XX3_MASK, PPCVSX3, PPCNONE, {XT6, XA6, XB6}},
+-{"xsnmaddasp", XX3(60,129), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}},
+-{"xxland", XX3(60,130), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xscvdpsp", XX2(60,265), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xscvdpspn", XX2(60,267), XX2_MASK, PPCVSX2, PPCNONE, {XT6, XB6}},
+-{"xsmincdp", XX3(60,136), XX3_MASK, PPCVSX3, PPCNONE, {XT6, XA6, XB6}},
+-{"xsnmaddmsp", XX3(60,137), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}},
+-{"xxlandc", XX3(60,138), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xsrsp", XX2(60,281), XX2_MASK, PPCVSX2, PPCNONE, {XT6, XB6}},
+-{"xsmaxjdp", XX3(60,144), XX3_MASK, PPCVSX3, PPCNONE, {XT6, XA6, XB6}},
+-{"xsnmsubasp", XX3(60,145), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}},
+-{"xxlor", XX3(60,146), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xscvuxdsp", XX2(60,296), XX2_MASK, PPCVSX2, PPCNONE, {XT6, XB6}},
+-{"xststdcsp", XX2(60,298), XX2BFD_MASK, PPCVSX3, PPCNONE, {BF, XB6, DCMX}},
+-{"xsminjdp", XX3(60,152), XX3_MASK, PPCVSX3, PPCNONE, {XT6, XA6, XB6}},
+-{"xsnmsubmsp", XX3(60,153), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}},
+-{"xxlxor", XX3(60,154), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xscvsxdsp", XX2(60,312), XX2_MASK, PPCVSX2, PPCNONE, {XT6, XB6}},
+-{"xsmaxdp", XX3(60,160), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xsnmaddadp", XX3(60,161), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xxlnor", XX3(60,162), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xscvdpuxds", XX2(60,328), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xscvspdp", XX2(60,329), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xscvspdpn", XX2(60,331), XX2_MASK, PPCVSX2, PPCNONE, {XT6, XB6}},
+-{"xsmindp", XX3(60,168), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xsnmaddmdp", XX3(60,169), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xxlorc", XX3(60,170), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}},
+-{"xscvdpsxds", XX2(60,344), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xsabsdp", XX2(60,345), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xsxexpdp", XX2VA(60,347,0),XX2_MASK|1, PPCVSX3, PPCNONE, {RT, XB6}},
+-{"xsxsigdp", XX2VA(60,347,1),XX2_MASK|1, PPCVSX3, PPCNONE, {RT, XB6}},
+-{"xscvhpdp", XX2VA(60,347,16),XX2_MASK, PPCVSX3, PPCNONE, {XT6, XB6}},
+-{"xscvdphp", XX2VA(60,347,17),XX2_MASK, PPCVSX3, PPCNONE, {XT6, XB6}},
+-{"xscpsgndp", XX3(60,176), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xsnmsubadp", XX3(60,177), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xxlnand", XX3(60,178), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}},
+-{"xscvuxddp", XX2(60,360), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xsnabsdp", XX2(60,361), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xststdcdp", XX2(60,362), XX2BFD_MASK, PPCVSX3, PPCNONE, {BF, XB6, DCMX}},
+-{"xsnmsubmdp", XX3(60,185), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xxleqv", XX3(60,186), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}},
+-{"xscvsxddp", XX2(60,376), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xsnegdp", XX2(60,377), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xvmaxsp", XX3(60,192), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvnmaddasp", XX3(60,193), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvcvspuxds", XX2(60,392), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xvcvdpsp", XX2(60,393), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xvminsp", XX3(60,200), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvnmaddmsp", XX3(60,201), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvcvspsxds", XX2(60,408), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xvabssp", XX2(60,409), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xvmovsp", XX3(60,208), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6S}},
+-{"xvcpsgnsp", XX3(60,208), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvnmsubasp", XX3(60,209), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvcvuxdsp", XX2(60,424), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xvnabssp", XX2(60,425), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xvtstdcsp", XX2(60,426), XX2DCMXS_MASK,PPCVSX3, PPCNONE, {XT6, XB6, DCMXS}},
+-{"xviexpsp", XX3(60,216), XX3_MASK, PPCVSX3, PPCNONE, {XT6, XA6, XB6}},
+-{"xvnmsubmsp", XX3(60,217), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvcvsxdsp", XX2(60,440), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xvnegsp", XX2(60,441), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xvmaxdp", XX3(60,224), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvnmaddadp", XX3(60,225), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvcvdpuxds", XX2(60,456), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xvcvspdp", XX2(60,457), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xsiexpdp", X(60,918), XX1_MASK, PPCVSX3, PPCNONE, {XT6, RA, RB}},
+-{"xvmindp", XX3(60,232), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvnmaddmdp", XX3(60,233), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvcvdpsxds", XX2(60,472), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xvabsdp", XX2(60,473), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xvxexpdp", XX2VA(60,475,0),XX2_MASK, PPCVSX3, PPCNONE, {XT6, XB6}},
+-{"xvxsigdp", XX2VA(60,475,1),XX2_MASK, PPCVSX3, PPCNONE, {XT6, XB6}},
+-{"xxbrh", XX2VA(60,475,7),XX2_MASK, PPCVSX3, PPCNONE, {XT6, XB6}},
+-{"xvxexpsp", XX2VA(60,475,8),XX2_MASK, PPCVSX3, PPCNONE, {XT6, XB6}},
+-{"xvxsigsp", XX2VA(60,475,9),XX2_MASK, PPCVSX3, PPCNONE, {XT6, XB6}},
+-{"xxbrw", XX2VA(60,475,15),XX2_MASK, PPCVSX3, PPCNONE, {XT6, XB6}},
+-{"xxbrd", XX2VA(60,475,23),XX2_MASK, PPCVSX3, PPCNONE, {XT6, XB6}},
+-{"xvcvhpsp", XX2VA(60,475,24),XX2_MASK, PPCVSX3, PPCNONE, {XT6, XB6}},
+-{"xvcvsphp", XX2VA(60,475,25),XX2_MASK, PPCVSX3, PPCNONE, {XT6, XB6}},
+-{"xxbrq", XX2VA(60,475,31),XX2_MASK, PPCVSX3, PPCNONE, {XT6, XB6}},
+-{"xvmovdp", XX3(60,240), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6S}},
+-{"xvcpsgndp", XX3(60,240), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvnmsubadp", XX3(60,241), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvcvuxddp", XX2(60,488), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xvnabsdp", XX2(60,489), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xvtstdcdp", XX2(60,490), XX2DCMXS_MASK,PPCVSX3, PPCNONE, {XT6, XB6, DCMXS}},
+-{"xviexpdp", XX3(60,248), XX3_MASK, PPCVSX3, PPCNONE, {XT6, XA6, XB6}},
+-{"xvnmsubmdp", XX3(60,249), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+-{"xvcvsxddp", XX2(60,504), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-{"xvnegdp", XX2(60,505), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+-
+-{"psq_st", OP(60), OP_MASK, PPCPS, PPCNONE, {FRS,PSD,RA,PSW,PSQ}},
+-{"stfq", OP(60), OP_MASK, POWER2, PPCNONE, {FRS, D, RA}},
+-
+-{"lxv", DQX(61,1), DQX_MASK, PPCVSX3, PPCNONE, {XTQ6, DQ, RA0}},
+-{"stxv", DQX(61,5), DQX_MASK, PPCVSX3, PPCNONE, {XSQ6, DQ, RA0}},
+-{"stxsd", DSO(61,2), DS_MASK, PPCVSX3, PPCNONE, {VS, DS, RA0}},
+-{"stxssp", DSO(61,3), DS_MASK, PPCVSX3, PPCNONE, {VS, DS, RA0}},
+-{"stfdp", OP(61), OP_MASK, POWER6, POWER7, {FRSp, DS, RA0}},
+-{"psq_stu", OP(61), OP_MASK, PPCPS, PPCNONE, {FRS,PSD,RA,PSW,PSQ}},
+-{"stfqu", OP(61), OP_MASK, POWER2, PPCNONE, {FRS, D, RA}},
+-
+-{"std", DSO(62,0), DS_MASK, PPC64, PPCNONE, {RS, DS, RA0}},
+-{"stdu", DSO(62,1), DS_MASK, PPC64, PPCNONE, {RS, DS, RAS}},
+-{"stq", DSO(62,2), DS_MASK, POWER4, PPC476, {RSQ, DS, RA0}},
+-
+-{"fcmpu", X(63,0), XBF_MASK, COM, PPCEFS, {BF, FRA, FRB}},
+-
+-{"daddq", XRC(63,2,0), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}},
+-{"daddq.", XRC(63,2,1), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}},
+-
+-{"dquaq", ZRC(63,3,0), Z2_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp, RMC}},
+-{"dquaq.", ZRC(63,3,1), Z2_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp, RMC}},
+-
+-{"xsaddqp", XRC(63,4,0), X_MASK, PPCVSX3, PPCNONE, {VD, VA, VB}},
+-{"xsaddqpo", XRC(63,4,1), X_MASK, PPCVSX3, PPCNONE, {VD, VA, VB}},
+-
+-{"xsrqpi", ZRC(63,5,0), Z2_MASK, PPCVSX3, PPCNONE, {R, VD, VB, RMC}},
+-{"xsrqpix", ZRC(63,5,1), Z2_MASK, PPCVSX3, PPCNONE, {R, VD, VB, RMC}},
+-
+-{"fcpsgn", XRC(63,8,0), X_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FRT, FRA, FRB}},
+-{"fcpsgn.", XRC(63,8,1), X_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FRT, FRA, FRB}},
+-
+-{"frsp", XRC(63,12,0), XRA_MASK, COM, PPCEFS, {FRT, FRB}},
+-{"frsp.", XRC(63,12,1), XRA_MASK, COM, PPCEFS, {FRT, FRB}},
+-
+-{"fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, PPCEFS, {FRT, FRB}},
+-{"fcir", XRC(63,14,0), XRA_MASK, PWR2COM, PPCNONE, {FRT, FRB}},
+-{"fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, PPCEFS, {FRT, FRB}},
+-{"fcir.", XRC(63,14,1), XRA_MASK, PWR2COM, PPCNONE, {FRT, FRB}},
+-
+-{"fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, PPCEFS, {FRT, FRB}},
+-{"fcirz", XRC(63,15,0), XRA_MASK, PWR2COM, PPCNONE, {FRT, FRB}},
+-{"fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, PPCEFS, {FRT, FRB}},
+-{"fcirz.", XRC(63,15,1), XRA_MASK, PWR2COM, PPCNONE, {FRT, FRB}},
+-
+-{"fdiv", A(63,18,0), AFRC_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRB}},
+-{"fd", A(63,18,0), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}},
+-{"fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRB}},
+-{"fd.", A(63,18,1), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}},
+-
+-{"fsub", A(63,20,0), AFRC_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRB}},
+-{"fs", A(63,20,0), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}},
+-{"fsub.", A(63,20,1), AFRC_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRB}},
+-{"fs.", A(63,20,1), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}},
+-
+-{"fadd", A(63,21,0), AFRC_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRB}},
+-{"fa", A(63,21,0), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}},
+-{"fadd.", A(63,21,1), AFRC_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRB}},
+-{"fa.", A(63,21,1), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}},
+-
+-{"fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, TITAN, {FRT, FRB}},
+-{"fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, TITAN, {FRT, FRB}},
+-
+-{"fsel", A(63,23,0), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}},
+-{"fsel.", A(63,23,1), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}},
+-
+-{"fre", A(63,24,0), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}},
+-{"fre", A(63,24,0), AFRALFRC_MASK, POWER5, POWER7, {FRT, FRB, A_L}},
+-{"fre.", A(63,24,1), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}},
+-{"fre.", A(63,24,1), AFRALFRC_MASK, POWER5, POWER7, {FRT, FRB, A_L}},
++{"dtstex", X(59,162), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
++{"dtstdc", Z(59,194), Z_MASK, POWER6, PPCVLE, {BF, FRA, DCM}},
++{"dtstdg", Z(59,226), Z_MASK, POWER6, PPCVLE, {BF, FRA, DGM}},
++
++{"drintn", ZRC(59,227,0), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
++{"drintn.", ZRC(59,227,1), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
++
++{"dctdp", XRC(59,258,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
++{"dctdp.", XRC(59,258,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
++
++{"dctfix", XRC(59,290,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
++{"dctfix.", XRC(59,290,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
++
++{"ddedpd", XRC(59,322,0), X_MASK, POWER6, PPCVLE, {SP, FRT, FRB}},
++{"ddedpd.", XRC(59,322,1), X_MASK, POWER6, PPCVLE, {SP, FRT, FRB}},
++
++{"dxex", XRC(59,354,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
++{"dxex.", XRC(59,354,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
++
++{"dsub", XRC(59,514,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
++{"dsub.", XRC(59,514,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
++
++{"ddiv", XRC(59,546,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
++{"ddiv.", XRC(59,546,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
++
++{"dcmpu", X(59,642), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
++
++{"dtstsf", X(59,674), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
++{"dtstsfi", X(59,675), X_MASK|1<<22,POWER9, PPCVLE, {BF, UIM6, FRB}},
++
++{"drsp", XRC(59,770,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
++{"drsp.", XRC(59,770,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
++
++{"dcffix", XRC(59,802,0), X_MASK|FRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
++{"dcffix.", XRC(59,802,1), X_MASK|FRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
++
++{"denbcd", XRC(59,834,0), X_MASK, POWER6, PPCVLE, {S, FRT, FRB}},
++{"denbcd.", XRC(59,834,1), X_MASK, POWER6, PPCVLE, {S, FRT, FRB}},
++
++{"fcfids", XRC(59,846,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
++{"fcfids.", XRC(59,846,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
++
++{"diex", XRC(59,866,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
++{"diex.", XRC(59,866,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
++
++{"fcfidus", XRC(59,974,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
++{"fcfidus.", XRC(59,974,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
++
++{"xsaddsp", XX3(60,0), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
++{"xsmaddasp", XX3(60,1), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
++{"xxsldwi", XX3(60,2), XX3SHW_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, SHW}},
++{"xscmpeqdp", XX3(60,3), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
++{"xsrsqrtesp", XX2(60,10), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
++{"xssqrtsp", XX2(60,11), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
++{"xxsel", XX4(60,3), XX4_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, XC6}},
++{"xssubsp", XX3(60,8), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
++{"xsmaddmsp", XX3(60,9), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
++{"xxspltd", XX3(60,10), XX3DM_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S, DMEX}},
++{"xxmrghd", XX3(60,10), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xxswapd", XX3(60,10)|(2<<8), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S}},
++{"xxmrgld", XX3(60,10)|(3<<8), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xxpermdi", XX3(60,10), XX3DM_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, DM}},
++{"xscmpgtdp", XX3(60,11), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
++{"xsresp", XX2(60,26), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
++{"xsmulsp", XX3(60,16), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
++{"xsmsubasp", XX3(60,17), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
++{"xxmrghw", XX3(60,18), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xscmpgedp", XX3(60,19), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
++{"xsdivsp", XX3(60,24), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
++{"xsmsubmsp", XX3(60,25), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
++{"xxperm", XX3(60,26), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
++{"xsadddp", XX3(60,32), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xsmaddadp", XX3(60,33), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xscmpudp", XX3(60,35), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
++{"xscvdpuxws", XX2(60,72), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xsrdpi", XX2(60,73), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xsrsqrtedp", XX2(60,74), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xssqrtdp", XX2(60,75), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xssubdp", XX3(60,40), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xsmaddmdp", XX3(60,41), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xscmpodp", XX3(60,43), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
++{"xscvdpsxws", XX2(60,88), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xsrdpiz", XX2(60,89), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xsredp", XX2(60,90), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xsmuldp", XX3(60,48), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xsmsubadp", XX3(60,49), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xxmrglw", XX3(60,50), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xsrdpip", XX2(60,105), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xstsqrtdp", XX2(60,106), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}},
++{"xsrdpic", XX2(60,107), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xsdivdp", XX3(60,56), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xsmsubmdp", XX3(60,57), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xxpermr", XX3(60,58), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
++{"xscmpexpdp", XX3(60,59), XX3BF_MASK, PPCVSX3, PPCVLE, {BF, XA6, XB6}},
++{"xsrdpim", XX2(60,121), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xstdivdp", XX3(60,61), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
++{"xvaddsp", XX3(60,64), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xvmaddasp", XX3(60,65), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xvcmpeqsp", XX3RC(60,67,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xvcmpeqsp.", XX3RC(60,67,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xvcvspuxws", XX2(60,136), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xvrspi", XX2(60,137), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xvrsqrtesp", XX2(60,138), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xvsqrtsp", XX2(60,139), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xvsubsp", XX3(60,72), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xvmaddmsp", XX3(60,73), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xvcmpgtsp", XX3RC(60,75,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xvcmpgtsp.", XX3RC(60,75,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xvcvspsxws", XX2(60,152), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xvrspiz", XX2(60,153), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xvresp", XX2(60,154), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xvmulsp", XX3(60,80), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xvmsubasp", XX3(60,81), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xxspltw", XX2(60,164), XX2UIM_MASK, PPCVSX, PPCVLE, {XT6, XB6, UIM}},
++{"xxextractuw", XX2(60,165), XX2UIM4_MASK, PPCVSX3, PPCVLE, {XT6, XB6, UIMM4}},
++{"xvcmpgesp", XX3RC(60,83,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xvcmpgesp.", XX3RC(60,83,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xvcvuxwsp", XX2(60,168), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xvrspip", XX2(60,169), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xvtsqrtsp", XX2(60,170), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}},
++{"xvrspic", XX2(60,171), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xvdivsp", XX3(60,88), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xvmsubmsp", XX3(60,89), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xxspltib", X(60,360), XX1_MASK|3<<19, PPCVSX3, PPCVLE, {XT6, IMM8}},
++{"xxinsertw", XX2(60,181), XX2UIM4_MASK, PPCVSX3, PPCVLE, {XT6, XB6, UIMM4}},
++{"xvcvsxwsp", XX2(60,184), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xvrspim", XX2(60,185), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xvtdivsp", XX3(60,93), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
++{"xvadddp", XX3(60,96), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xvmaddadp", XX3(60,97), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xvcmpeqdp", XX3RC(60,99,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xvcmpeqdp.", XX3RC(60,99,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xvcvdpuxws", XX2(60,200), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xvrdpi", XX2(60,201), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xvrsqrtedp", XX2(60,202), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xvsqrtdp", XX2(60,203), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xvsubdp", XX3(60,104), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xvmaddmdp", XX3(60,105), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xvcmpgtdp", XX3RC(60,107,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xvcmpgtdp.", XX3RC(60,107,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xvcvdpsxws", XX2(60,216), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xvrdpiz", XX2(60,217), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xvredp", XX2(60,218), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xvmuldp", XX3(60,112), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xvmsubadp", XX3(60,113), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xvcmpgedp", XX3RC(60,115,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xvcmpgedp.", XX3RC(60,115,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xvcvuxwdp", XX2(60,232), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xvrdpip", XX2(60,233), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xvtsqrtdp", XX2(60,234), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}},
++{"xvrdpic", XX2(60,235), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xvdivdp", XX3(60,120), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xvmsubmdp", XX3(60,121), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xvcvsxwdp", XX2(60,248), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xvrdpim", XX2(60,249), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xvtdivdp", XX3(60,125), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
++{"xsmaxcdp", XX3(60,128), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
++{"xsnmaddasp", XX3(60,129), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
++{"xxland", XX3(60,130), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xscvdpsp", XX2(60,265), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xscvdpspn", XX2(60,267), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
++{"xsmincdp", XX3(60,136), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
++{"xsnmaddmsp", XX3(60,137), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
++{"xxlandc", XX3(60,138), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xsrsp", XX2(60,281), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
++{"xsmaxjdp", XX3(60,144), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
++{"xsnmsubasp", XX3(60,145), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
++{"xxlor", XX3(60,146), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xscvuxdsp", XX2(60,296), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
++{"xststdcsp", XX2(60,298), XX2BFD_MASK, PPCVSX3, PPCVLE, {BF, XB6, DCMX}},
++{"xsminjdp", XX3(60,152), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
++{"xsnmsubmsp", XX3(60,153), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
++{"xxlxor", XX3(60,154), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xscvsxdsp", XX2(60,312), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
++{"xsmaxdp", XX3(60,160), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xsnmaddadp", XX3(60,161), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xxlnor", XX3(60,162), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xscvdpuxds", XX2(60,328), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xscvspdp", XX2(60,329), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xscvspdpn", XX2(60,331), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
++{"xsmindp", XX3(60,168), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xsnmaddmdp", XX3(60,169), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xxlorc", XX3(60,170), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
++{"xscvdpsxds", XX2(60,344), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xsabsdp", XX2(60,345), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xsxexpdp", XX2VA(60,347,0),XX2_MASK|1, PPCVSX3, PPCVLE, {RT, XB6}},
++{"xsxsigdp", XX2VA(60,347,1),XX2_MASK|1, PPCVSX3, PPCVLE, {RT, XB6}},
++{"xscvhpdp", XX2VA(60,347,16),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
++{"xscvdphp", XX2VA(60,347,17),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
++{"xscpsgndp", XX3(60,176), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xsnmsubadp", XX3(60,177), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xxlnand", XX3(60,178), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
++{"xscvuxddp", XX2(60,360), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xsnabsdp", XX2(60,361), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xststdcdp", XX2(60,362), XX2BFD_MASK, PPCVSX3, PPCVLE, {BF, XB6, DCMX}},
++{"xsnmsubmdp", XX3(60,185), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xxleqv", XX3(60,186), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
++{"xscvsxddp", XX2(60,376), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xsnegdp", XX2(60,377), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xvmaxsp", XX3(60,192), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xvnmaddasp", XX3(60,193), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xvcvspuxds", XX2(60,392), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xvcvdpsp", XX2(60,393), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xvminsp", XX3(60,200), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xvnmaddmsp", XX3(60,201), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xvcvspsxds", XX2(60,408), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xvabssp", XX2(60,409), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xvmovsp", XX3(60,208), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S}},
++{"xvcpsgnsp", XX3(60,208), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xvnmsubasp", XX3(60,209), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xvcvuxdsp", XX2(60,424), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xvnabssp", XX2(60,425), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xvtstdcsp", XX2(60,426), XX2DCMXS_MASK, PPCVSX3, PPCVLE, {XT6, XB6, DCMXS}},
++{"xviexpsp", XX3(60,216), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
++{"xvnmsubmsp", XX3(60,217), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xvcvsxdsp", XX2(60,440), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xvnegsp", XX2(60,441), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xvmaxdp", XX3(60,224), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xvnmaddadp", XX3(60,225), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xvcvdpuxds", XX2(60,456), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xvcvspdp", XX2(60,457), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xsiexpdp", X(60,918), XX1_MASK, PPCVSX3, PPCVLE, {XT6, RA, RB}},
++{"xvmindp", XX3(60,232), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xvnmaddmdp", XX3(60,233), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xvcvdpsxds", XX2(60,472), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xvabsdp", XX2(60,473), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xvxexpdp", XX2VA(60,475,0),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
++{"xvxsigdp", XX2VA(60,475,1),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
++{"xxbrh", XX2VA(60,475,7),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
++{"xvxexpsp", XX2VA(60,475,8),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
++{"xvxsigsp", XX2VA(60,475,9),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
++{"xxbrw", XX2VA(60,475,15),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
++{"xxbrd", XX2VA(60,475,23),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
++{"xvcvhpsp", XX2VA(60,475,24),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
++{"xvcvsphp", XX2VA(60,475,25),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
++{"xxbrq", XX2VA(60,475,31),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
++{"xvmovdp", XX3(60,240), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S}},
++{"xvcpsgndp", XX3(60,240), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xvnmsubadp", XX3(60,241), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xvcvuxddp", XX2(60,488), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xvnabsdp", XX2(60,489), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xvtstdcdp", XX2(60,490), XX2DCMXS_MASK, PPCVSX3, PPCVLE, {XT6, XB6, DCMXS}},
++{"xviexpdp", XX3(60,248), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
++{"xvnmsubmdp", XX3(60,249), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
++{"xvcvsxddp", XX2(60,504), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++{"xvnegdp", XX2(60,505), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
++
++{"psq_st", OP(60), OP_MASK, PPCPS, PPCVLE, {FRS,PSD,RA,PSW,PSQ}},
++{"stfq", OP(60), OP_MASK, POWER2, PPCVLE, {FRS, D, RA}},
++
++{"lxv", DQX(61,1), DQX_MASK, PPCVSX3, PPCVLE, {XTQ6, DQ, RA0}},
++{"stxv", DQX(61,5), DQX_MASK, PPCVSX3, PPCVLE, {XSQ6, DQ, RA0}},
++{"stxsd", DSO(61,2), DS_MASK, PPCVSX3, PPCVLE, {VS, DS, RA0}},
++{"stxssp", DSO(61,3), DS_MASK, PPCVSX3, PPCVLE, {VS, DS, RA0}},
++{"stfdp", OP(61), OP_MASK, POWER6, POWER7|PPCVLE, {FRSp, DS, RA0}},
++{"psq_stu", OP(61), OP_MASK, PPCPS, PPCVLE, {FRS,PSD,RA,PSW,PSQ}},
++{"stfqu", OP(61), OP_MASK, POWER2, PPCVLE, {FRS, D, RA}},
++
++{"std", DSO(62,0), DS_MASK, PPC64, PPCVLE, {RS, DS, RA0}},
++{"stdu", DSO(62,1), DS_MASK, PPC64, PPCVLE, {RS, DS, RAS}},
++{"stq", DSO(62,2), DS_MASK, POWER4, PPC476|PPCVLE, {RSQ, DS, RA0}},
++
++{"fcmpu", X(63,0), XBF_MASK, COM, PPCEFS|PPCVLE, {BF, FRA, FRB}},
++
++{"daddq", XRC(63,2,0), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
++{"daddq.", XRC(63,2,1), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
++
++{"dquaq", ZRC(63,3,0), Z2_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp, RMC}},
++{"dquaq.", ZRC(63,3,1), Z2_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp, RMC}},
++
++{"xsaddqp", XRC(63,4,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
++{"xsaddqpo", XRC(63,4,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
++
++{"xsrqpi", ZRC(63,5,0), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}},
++{"xsrqpix", ZRC(63,5,1), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}},
++
++{"fcpsgn", XRC(63,8,0), X_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FRT, FRA, FRB}},
++{"fcpsgn.", XRC(63,8,1), X_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FRT, FRA, FRB}},
++
++{"frsp", XRC(63,12,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
++{"frsp.", XRC(63,12,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
++
++{"fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}},
++{"fcir", XRC(63,14,0), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}},
++{"fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}},
++{"fcir.", XRC(63,14,1), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}},
++
++{"fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}},
++{"fcirz", XRC(63,15,0), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}},
++{"fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}},
++{"fcirz.", XRC(63,15,1), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}},
++
++{"fdiv", A(63,18,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
++{"fd", A(63,18,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
++{"fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
++{"fd.", A(63,18,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
++
++{"fsub", A(63,20,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
++{"fs", A(63,20,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
++{"fsub.", A(63,20,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
++{"fs.", A(63,20,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
++
++{"fadd", A(63,21,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
++{"fa", A(63,21,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
++{"fadd.", A(63,21,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
++{"fa.", A(63,21,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
++
++{"fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, TITAN|PPCVLE, {FRT, FRB}},
++{"fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, TITAN|PPCVLE, {FRT, FRB}},
++
++{"fsel", A(63,23,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
++{"fsel.", A(63,23,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
++
++{"fre", A(63,24,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
++{"fre", A(63,24,0), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}},
++{"fre.", A(63,24,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
++{"fre.", A(63,24,1), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}},
+
+-{"fmul", A(63,25,0), AFRB_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC}},
+-{"fm", A(63,25,0), AFRB_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC}},
+-{"fmul.", A(63,25,1), AFRB_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC}},
+-{"fm.", A(63,25,1), AFRB_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC}},
++{"fmul", A(63,25,0), AFRB_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
++{"fm", A(63,25,0), AFRB_MASK, PWRCOM, PPCVLE|PPCVLE, {FRT, FRA, FRC}},
++{"fmul.", A(63,25,1), AFRB_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
++{"fm.", A(63,25,1), AFRB_MASK, PWRCOM, PPCVLE|PPCVLE, {FRT, FRA, FRC}},
+
+-{"frsqrte", A(63,26,0), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}},
+-{"frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, POWER7, {FRT, FRB, A_L}},
+-{"frsqrte.", A(63,26,1), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}},
+-{"frsqrte.", A(63,26,1), AFRALFRC_MASK, PPC, POWER7, {FRT, FRB, A_L}},
++{"frsqrte", A(63,26,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
++{"frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
++{"frsqrte.", A(63,26,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
++{"frsqrte.", A(63,26,1), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
+
+-{"fmsub", A(63,28,0), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}},
+-{"fms", A(63,28,0), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
+-{"fmsub.", A(63,28,1), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}},
+-{"fms.", A(63,28,1), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
++{"fmsub", A(63,28,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
++{"fms", A(63,28,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
++{"fmsub.", A(63,28,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
++{"fms.", A(63,28,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
+
+-{"fmadd", A(63,29,0), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}},
+-{"fma", A(63,29,0), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
+-{"fmadd.", A(63,29,1), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}},
+-{"fma.", A(63,29,1), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
++{"fmadd", A(63,29,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
++{"fma", A(63,29,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
++{"fmadd.", A(63,29,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
++{"fma.", A(63,29,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
+
+-{"fnmsub", A(63,30,0), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}},
+-{"fnms", A(63,30,0), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
+-{"fnmsub.", A(63,30,1), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}},
+-{"fnms.", A(63,30,1), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
++{"fnmsub", A(63,30,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
++{"fnms", A(63,30,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
++{"fnmsub.", A(63,30,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
++{"fnms.", A(63,30,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
+
+-{"fnmadd", A(63,31,0), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}},
+-{"fnma", A(63,31,0), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
+-{"fnmadd.", A(63,31,1), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}},
+-{"fnma.", A(63,31,1), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
++{"fnmadd", A(63,31,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
++{"fnma", A(63,31,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
++{"fnmadd.", A(63,31,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
++{"fnma.", A(63,31,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
+
+-{"fcmpo", X(63,32), XBF_MASK, COM, PPCEFS, {BF, FRA, FRB}},
++{"fcmpo", X(63,32), XBF_MASK, COM, PPCEFS|PPCVLE, {BF, FRA, FRB}},
+
+-{"dmulq", XRC(63,34,0), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}},
+-{"dmulq.", XRC(63,34,1), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}},
++{"dmulq", XRC(63,34,0), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
++{"dmulq.", XRC(63,34,1), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
+
+-{"drrndq", ZRC(63,35,0), Z2_MASK, POWER6, PPCNONE, {FRTp, FRA, FRBp, RMC}},
+-{"drrndq.", ZRC(63,35,1), Z2_MASK, POWER6, PPCNONE, {FRTp, FRA, FRBp, RMC}},
++{"drrndq", ZRC(63,35,0), Z2_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp, RMC}},
++{"drrndq.", ZRC(63,35,1), Z2_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp, RMC}},
+
+-{"xsmulqp", XRC(63,36,0), X_MASK, PPCVSX3, PPCNONE, {VD, VA, VB}},
+-{"xsmulqpo", XRC(63,36,1), X_MASK, PPCVSX3, PPCNONE, {VD, VA, VB}},
++{"xsmulqp", XRC(63,36,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
++{"xsmulqpo", XRC(63,36,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
+
+-{"xsrqpxp", Z(63,37), Z2_MASK, PPCVSX3, PPCNONE, {R, VD, VB, RMC}},
++{"xsrqpxp", Z(63,37), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}},
+
+-{"mtfsb1", XRC(63,38,0), XRARB_MASK, COM, PPCNONE, {BT}},
+-{"mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, PPCNONE, {BT}},
++{"mtfsb1", XRC(63,38,0), XRARB_MASK, COM, PPCVLE, {BT}},
++{"mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, PPCVLE, {BT}},
+
+-{"fneg", XRC(63,40,0), XRA_MASK, COM, PPCEFS, {FRT, FRB}},
+-{"fneg.", XRC(63,40,1), XRA_MASK, COM, PPCEFS, {FRT, FRB}},
++{"fneg", XRC(63,40,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
++{"fneg.", XRC(63,40,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
+
+-{"mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, PPCNONE, {BF, BFA}},
++{"mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, PPCVLE, {BF, BFA}},
+
+-{"dscliq", ZRC(63,66,0), Z_MASK, POWER6, PPCNONE, {FRTp, FRAp, SH16}},
+-{"dscliq.", ZRC(63,66,1), Z_MASK, POWER6, PPCNONE, {FRTp, FRAp, SH16}},
++{"dscliq", ZRC(63,66,0), Z_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}},
++{"dscliq.", ZRC(63,66,1), Z_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}},
+
+-{"dquaiq", ZRC(63,67,0), Z2_MASK, POWER6, PPCNONE, {TE, FRTp, FRBp, RMC}},
+-{"dquaiq.", ZRC(63,67,1), Z2_MASK, POWER6, PPCNONE, {TE, FRTp, FRBp, RMC}},
++{"dquaiq", ZRC(63,67,0), Z2_MASK, POWER6, PPCVLE, {TE, FRTp, FRBp, RMC}},
++{"dquaiq.", ZRC(63,67,1), Z2_MASK, POWER6, PPCVLE, {TE, FRTp, FRBp, RMC}},
+
+-{"mtfsb0", XRC(63,70,0), XRARB_MASK, COM, PPCNONE, {BT}},
+-{"mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, PPCNONE, {BT}},
++{"mtfsb0", XRC(63,70,0), XRARB_MASK, COM, PPCVLE, {BT}},
++{"mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, PPCVLE, {BT}},
+
+-{"fmr", XRC(63,72,0), XRA_MASK, COM, PPCEFS, {FRT, FRB}},
+-{"fmr.", XRC(63,72,1), XRA_MASK, COM, PPCEFS, {FRT, FRB}},
++{"fmr", XRC(63,72,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
++{"fmr.", XRC(63,72,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
+
+-{"dscriq", ZRC(63,98,0), Z_MASK, POWER6, PPCNONE, {FRTp, FRAp, SH16}},
+-{"dscriq.", ZRC(63,98,1), Z_MASK, POWER6, PPCNONE, {FRTp, FRAp, SH16}},
++{"dscriq", ZRC(63,98,0), Z_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}},
++{"dscriq.", ZRC(63,98,1), Z_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}},
+
+-{"drintxq", ZRC(63,99,0), Z2_MASK, POWER6, PPCNONE, {R, FRTp, FRBp, RMC}},
+-{"drintxq.", ZRC(63,99,1), Z2_MASK, POWER6, PPCNONE, {R, FRTp, FRBp, RMC}},
++{"drintxq", ZRC(63,99,0), Z2_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}},
++{"drintxq.", ZRC(63,99,1), Z2_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}},
+
+-{"xscpsgnqp", X(63,100), X_MASK, PPCVSX3, PPCNONE, {VD, VA, VB}},
++{"xscpsgnqp", X(63,100), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
+
+-{"ftdiv", X(63,128), XBF_MASK, POWER7, PPCNONE, {BF, FRA, FRB}},
++{"ftdiv", X(63,128), XBF_MASK, POWER7, PPCVLE, {BF, FRA, FRB}},
+
+-{"dcmpoq", X(63,130), X_MASK, POWER6, PPCNONE, {BF, FRAp, FRBp}},
++{"dcmpoq", X(63,130), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}},
+
+-{"xscmpoqp", X(63,132), XBF_MASK, PPCVSX3, PPCNONE, {BF, VA, VB}},
++{"xscmpoqp", X(63,132), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}},
+
+-{"mtfsfi", XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCNONE, {BFF, U, W}},
+-{"mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476, {BFF, U}},
+-{"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCNONE, {BFF, U, W}},
+-{"mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476, {BFF, U}},
++{"mtfsfi", XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCVLE, {BFF, U, W}},
++{"mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476|PPCVLE, {BFF, U}},
++{"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCVLE, {BFF, U, W}},
++{"mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476|PPCVLE, {BFF, U}},
+
+-{"fnabs", XRC(63,136,0), XRA_MASK, COM, PPCEFS, {FRT, FRB}},
+-{"fnabs.", XRC(63,136,1), XRA_MASK, COM, PPCEFS, {FRT, FRB}},
++{"fnabs", XRC(63,136,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
++{"fnabs.", XRC(63,136,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
+
+-{"fctiwu", XRC(63,142,0), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
+-{"fctiwu.", XRC(63,142,1), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
+-{"fctiwuz", XRC(63,143,0), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
+-{"fctiwuz.", XRC(63,143,1), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
++{"fctiwu", XRC(63,142,0), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
++{"fctiwu.", XRC(63,142,1), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
++{"fctiwuz", XRC(63,143,0), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
++{"fctiwuz.", XRC(63,143,1), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
+
+-{"ftsqrt", X(63,160), XBF_MASK|FRA_MASK, POWER7, PPCNONE, {BF, FRB}},
++{"ftsqrt", X(63,160), XBF_MASK|FRA_MASK, POWER7, PPCVLE, {BF, FRB}},
+
+-{"dtstexq", X(63,162), X_MASK, POWER6, PPCNONE, {BF, FRAp, FRBp}},
++{"dtstexq", X(63,162), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}},
+
+-{"xscmpexpqp", X(63,164), XBF_MASK, PPCVSX3, PPCNONE, {BF, VA, VB}},
++{"xscmpexpqp", X(63,164), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}},
+
+-{"dtstdcq", Z(63,194), Z_MASK, POWER6, PPCNONE, {BF, FRAp, DCM}},
+-{"dtstdgq", Z(63,226), Z_MASK, POWER6, PPCNONE, {BF, FRAp, DGM}},
++{"dtstdcq", Z(63,194), Z_MASK, POWER6, PPCVLE, {BF, FRAp, DCM}},
++{"dtstdgq", Z(63,226), Z_MASK, POWER6, PPCVLE, {BF, FRAp, DGM}},
+
+-{"drintnq", ZRC(63,227,0), Z2_MASK, POWER6, PPCNONE, {R, FRTp, FRBp, RMC}},
+-{"drintnq.", ZRC(63,227,1), Z2_MASK, POWER6, PPCNONE, {R, FRTp, FRBp, RMC}},
++{"drintnq", ZRC(63,227,0), Z2_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}},
++{"drintnq.", ZRC(63,227,1), Z2_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}},
+
+-{"dctqpq", XRC(63,258,0), X_MASK, POWER6, PPCNONE, {FRTp, FRB}},
+-{"dctqpq.", XRC(63,258,1), X_MASK, POWER6, PPCNONE, {FRTp, FRB}},
++{"dctqpq", XRC(63,258,0), X_MASK, POWER6, PPCVLE, {FRTp, FRB}},
++{"dctqpq.", XRC(63,258,1), X_MASK, POWER6, PPCVLE, {FRTp, FRB}},
+
+-{"fabs", XRC(63,264,0), XRA_MASK, COM, PPCEFS, {FRT, FRB}},
+-{"fabs.", XRC(63,264,1), XRA_MASK, COM, PPCEFS, {FRT, FRB}},
++{"fabs", XRC(63,264,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
++{"fabs.", XRC(63,264,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
+
+-{"dctfixq", XRC(63,290,0), X_MASK, POWER6, PPCNONE, {FRT, FRBp}},
+-{"dctfixq.", XRC(63,290,1), X_MASK, POWER6, PPCNONE, {FRT, FRBp}},
++{"dctfixq", XRC(63,290,0), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
++{"dctfixq.", XRC(63,290,1), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
+
+-{"ddedpdq", XRC(63,322,0), X_MASK, POWER6, PPCNONE, {SP, FRTp, FRBp}},
+-{"ddedpdq.", XRC(63,322,1), X_MASK, POWER6, PPCNONE, {SP, FRTp, FRBp}},
++{"ddedpdq", XRC(63,322,0), X_MASK, POWER6, PPCVLE, {SP, FRTp, FRBp}},
++{"ddedpdq.", XRC(63,322,1), X_MASK, POWER6, PPCVLE, {SP, FRTp, FRBp}},
+
+-{"dxexq", XRC(63,354,0), X_MASK, POWER6, PPCNONE, {FRT, FRBp}},
+-{"dxexq.", XRC(63,354,1), X_MASK, POWER6, PPCNONE, {FRT, FRBp}},
++{"dxexq", XRC(63,354,0), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
++{"dxexq.", XRC(63,354,1), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
+
+-{"xsmaddqp", XRC(63,388,0), X_MASK, PPCVSX3, PPCNONE, {VD, VA, VB}},
+-{"xsmaddqpo", XRC(63,388,1), X_MASK, PPCVSX3, PPCNONE, {VD, VA, VB}},
++{"xsmaddqp", XRC(63,388,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
++{"xsmaddqpo", XRC(63,388,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
+
+-{"frin", XRC(63,392,0), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}},
+-{"frin.", XRC(63,392,1), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}},
++{"frin", XRC(63,392,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
++{"frin.", XRC(63,392,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
+
+-{"xsmsubqp", XRC(63,420,0), X_MASK, PPCVSX3, PPCNONE, {VD, VA, VB}},
+-{"xsmsubqpo", XRC(63,420,1), X_MASK, PPCVSX3, PPCNONE, {VD, VA, VB}},
++{"xsmsubqp", XRC(63,420,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
++{"xsmsubqpo", XRC(63,420,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
+
+-{"friz", XRC(63,424,0), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}},
+-{"friz.", XRC(63,424,1), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}},
++{"friz", XRC(63,424,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
++{"friz.", XRC(63,424,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
+
+-{"xsnmaddqp", XRC(63,452,0), X_MASK, PPCVSX3, PPCNONE, {VD, VA, VB}},
+-{"xsnmaddqpo", XRC(63,452,1), X_MASK, PPCVSX3, PPCNONE, {VD, VA, VB}},
++{"xsnmaddqp", XRC(63,452,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
++{"xsnmaddqpo", XRC(63,452,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
+
+-{"frip", XRC(63,456,0), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}},
+-{"frip.", XRC(63,456,1), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}},
++{"frip", XRC(63,456,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
++{"frip.", XRC(63,456,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
+
+-{"xsnmsubqp", XRC(63,484,0), X_MASK, PPCVSX3, PPCNONE, {VD, VA, VB}},
+-{"xsnmsubqpo", XRC(63,484,1), X_MASK, PPCVSX3, PPCNONE, {VD, VA, VB}},
++{"xsnmsubqp", XRC(63,484,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
++{"xsnmsubqpo", XRC(63,484,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
+
+-{"frim", XRC(63,488,0), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}},
+-{"frim.", XRC(63,488,1), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}},
++{"frim", XRC(63,488,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
++{"frim.", XRC(63,488,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
+
+-{"dsubq", XRC(63,514,0), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}},
+-{"dsubq.", XRC(63,514,1), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}},
++{"dsubq", XRC(63,514,0), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
++{"dsubq.", XRC(63,514,1), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
+
+-{"xssubqp", XRC(63,516,0), X_MASK, PPCVSX3, PPCNONE, {VD, VA, VB}},
+-{"xssubqpo", XRC(63,516,1), X_MASK, PPCVSX3, PPCNONE, {VD, VA, VB}},
++{"xssubqp", XRC(63,516,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
++{"xssubqpo", XRC(63,516,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
+
+-{"ddivq", XRC(63,546,0), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}},
+-{"ddivq.", XRC(63,546,1), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}},
++{"ddivq", XRC(63,546,0), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
++{"ddivq.", XRC(63,546,1), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
+
+-{"xsdivqp", XRC(63,548,0), X_MASK, PPCVSX3, PPCNONE, {VD, VA, VB}},
+-{"xsdivqpo", XRC(63,548,1), X_MASK, PPCVSX3, PPCNONE, {VD, VA, VB}},
++{"xsdivqp", XRC(63,548,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
++{"xsdivqpo", XRC(63,548,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
+
+-{"mffs", XRC(63,583,0), XRARB_MASK, COM, PPCEFS, {FRT}},
+-{"mffs.", XRC(63,583,1), XRARB_MASK, COM, PPCEFS, {FRT}},
++{"mffs", XRC(63,583,0), XRARB_MASK, COM, PPCEFS|PPCVLE, {FRT}},
++{"mffs.", XRC(63,583,1), XRARB_MASK, COM, PPCEFS|PPCVLE, {FRT}},
+
+-{"dcmpuq", X(63,642), X_MASK, POWER6, PPCNONE, {BF, FRAp, FRBp}},
++{"dcmpuq", X(63,642), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}},
+
+-{"xscmpuqp", X(63,644), XBF_MASK, PPCVSX3, PPCNONE, {BF, VA, VB}},
++{"xscmpuqp", X(63,644), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}},
+
+-{"dtstsfq", X(63,674), X_MASK, POWER6, PPCNONE, {BF, FRA, FRBp}},
+-{"dtstsfiq", X(63,675), X_MASK|1<<22,POWER9, PPCNONE, {BF, UIM6, FRBp}},
++{"dtstsfq", X(63,674), X_MASK, POWER6, PPCVLE, {BF, FRA, FRBp}},
++{"dtstsfiq", X(63,675), X_MASK|1<<22,POWER9, PPCVLE, {BF, UIM6, FRBp}},
+
+-{"xststdcqp", X(63,708), X_MASK, PPCVSX3, PPCNONE, {BF, VB, DCMX}},
++{"xststdcqp", X(63,708), X_MASK, PPCVSX3, PPCVLE, {BF, VB, DCMX}},
+
+-{"mtfsf", XFL(63,711,0), XFL_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FLM, FRB, XFL_L, W}},
+-{"mtfsf", XFL(63,711,0), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS, {FLM, FRB}},
+-{"mtfsf.", XFL(63,711,1), XFL_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FLM, FRB, XFL_L, W}},
+-{"mtfsf.", XFL(63,711,1), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS, {FLM, FRB}},
++{"mtfsf", XFL(63,711,0), XFL_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FLM, FRB, XFL_L, W}},
++{"mtfsf", XFL(63,711,0), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS|PPCVLE, {FLM, FRB}},
++{"mtfsf.", XFL(63,711,1), XFL_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FLM, FRB, XFL_L, W}},
++{"mtfsf.", XFL(63,711,1), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS|PPCVLE, {FLM, FRB}},
+
+-{"drdpq", XRC(63,770,0), X_MASK, POWER6, PPCNONE, {FRTp, FRBp}},
+-{"drdpq.", XRC(63,770,1), X_MASK, POWER6, PPCNONE, {FRTp, FRBp}},
++{"drdpq", XRC(63,770,0), X_MASK, POWER6, PPCVLE, {FRTp, FRBp}},
++{"drdpq.", XRC(63,770,1), X_MASK, POWER6, PPCVLE, {FRTp, FRBp}},
+
+-{"dcffixq", XRC(63,802,0), X_MASK, POWER6, PPCNONE, {FRTp, FRB}},
+-{"dcffixq.", XRC(63,802,1), X_MASK, POWER6, PPCNONE, {FRTp, FRB}},
++{"dcffixq", XRC(63,802,0), X_MASK, POWER6, PPCVLE, {FRTp, FRB}},
++{"dcffixq.", XRC(63,802,1), X_MASK, POWER6, PPCVLE, {FRTp, FRB}},
+
+-{"xsabsqp", XVA(63,804,0), XVA_MASK, PPCVSX3, PPCNONE, {VD, VB}},
+-{"xsxexpqp", XVA(63,804,2), XVA_MASK, PPCVSX3, PPCNONE, {VD, VB}},
+-{"xsnabsqp", XVA(63,804,8), XVA_MASK, PPCVSX3, PPCNONE, {VD, VB}},
+-{"xsnegqp", XVA(63,804,16), XVA_MASK, PPCVSX3, PPCNONE, {VD, VB}},
+-{"xsxsigqp", XVA(63,804,18), XVA_MASK, PPCVSX3, PPCNONE, {VD, VB}},
+-{"xssqrtqp", XVARC(63,804,27,0), XVA_MASK, PPCVSX3, PPCNONE, {VD, VB}},
+-{"xssqrtqpo", XVARC(63,804,27,1), XVA_MASK, PPCVSX3, PPCNONE, {VD, VB}},
++{"xsabsqp", XVA(63,804,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
++{"xsxexpqp", XVA(63,804,2), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
++{"xsnabsqp", XVA(63,804,8), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
++{"xsnegqp", XVA(63,804,16), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
++{"xsxsigqp", XVA(63,804,18), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
++{"xssqrtqp", XVARC(63,804,27,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
++{"xssqrtqpo", XVARC(63,804,27,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
+
+-{"fctid", XRC(63,814,0), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}},
+-{"fctid", XRC(63,814,0), XRA_MASK, PPC476, PPCNONE, {FRT, FRB}},
+-{"fctid.", XRC(63,814,1), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}},
+-{"fctid.", XRC(63,814,1), XRA_MASK, PPC476, PPCNONE, {FRT, FRB}},
++{"fctid", XRC(63,814,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
++{"fctid", XRC(63,814,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
++{"fctid.", XRC(63,814,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
++{"fctid.", XRC(63,814,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
+
+-{"fctidz", XRC(63,815,0), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}},
+-{"fctidz", XRC(63,815,0), XRA_MASK, PPC476, PPCNONE, {FRT, FRB}},
+-{"fctidz.", XRC(63,815,1), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}},
+-{"fctidz.", XRC(63,815,1), XRA_MASK, PPC476, PPCNONE, {FRT, FRB}},
++{"fctidz", XRC(63,815,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
++{"fctidz", XRC(63,815,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
++{"fctidz.", XRC(63,815,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
++{"fctidz.", XRC(63,815,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
+
+-{"denbcdq", XRC(63,834,0), X_MASK, POWER6, PPCNONE, {S, FRTp, FRBp}},
+-{"denbcdq.", XRC(63,834,1), X_MASK, POWER6, PPCNONE, {S, FRTp, FRBp}},
++{"denbcdq", XRC(63,834,0), X_MASK, POWER6, PPCVLE, {S, FRTp, FRBp}},
++{"denbcdq.", XRC(63,834,1), X_MASK, POWER6, PPCVLE, {S, FRTp, FRBp}},
+
+-{"xscvqpuwz", XVA(63,836,1), XVA_MASK, PPCVSX3, PPCNONE, {VD, VB}},
+-{"xscvudqp", XVA(63,836,2), XVA_MASK, PPCVSX3, PPCNONE, {VD, VB}},
+-{"xscvqpswz", XVA(63,836,9), XVA_MASK, PPCVSX3, PPCNONE, {VD, VB}},
+-{"xscvsdqp", XVA(63,836,10), XVA_MASK, PPCVSX3, PPCNONE, {VD, VB}},
+-{"xscvqpudz", XVA(63,836,17), XVA_MASK, PPCVSX3, PPCNONE, {VD, VB}},
+-{"xscvqpdp", XVARC(63,836,20,0), XVA_MASK, PPCVSX3, PPCNONE, {VD, VB}},
+-{"xscvqpdpo", XVARC(63,836,20,1), XVA_MASK, PPCVSX3, PPCNONE, {VD, VB}},
+-{"xscvdpqp", XVA(63,836,22), XVA_MASK, PPCVSX3, PPCNONE, {VD, VB}},
+-{"xscvqpsdz", XVA(63,836,25), XVA_MASK, PPCVSX3, PPCNONE, {VD, VB}},
++{"xscvqpuwz", XVA(63,836,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
++{"xscvudqp", XVA(63,836,2), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
++{"xscvqpswz", XVA(63,836,9), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
++{"xscvsdqp", XVA(63,836,10), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
++{"xscvqpudz", XVA(63,836,17), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
++{"xscvqpdp", XVARC(63,836,20,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
++{"xscvqpdpo", XVARC(63,836,20,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
++{"xscvdpqp", XVA(63,836,22), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
++{"xscvqpsdz", XVA(63,836,25), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
+
+-{"fmrgow", X(63,838), X_MASK, PPCVSX2, PPCNONE, {FRT, FRA, FRB}},
++{"fmrgow", X(63,838), X_MASK, PPCVSX2, PPCVLE, {FRT, FRA, FRB}},
+
+-{"fcfid", XRC(63,846,0), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}},
+-{"fcfid", XRC(63,846,0), XRA_MASK, PPC476, PPCNONE, {FRT, FRB}},
+-{"fcfid.", XRC(63,846,1), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}},
+-{"fcfid.", XRC(63,846,1), XRA_MASK, PPC476, PPCNONE, {FRT, FRB}},
++{"fcfid", XRC(63,846,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
++{"fcfid", XRC(63,846,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
++{"fcfid.", XRC(63,846,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
++{"fcfid.", XRC(63,846,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
+
+-{"diexq", XRC(63,866,0), X_MASK, POWER6, PPCNONE, {FRTp, FRA, FRBp}},
+-{"diexq.", XRC(63,866,1), X_MASK, POWER6, PPCNONE, {FRTp, FRA, FRBp}},
++{"diexq", XRC(63,866,0), X_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp}},
++{"diexq.", XRC(63,866,1), X_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp}},
+
+-{"xsiexpqp", X(63,868), X_MASK, PPCVSX3, PPCNONE, {VD, VA, VB}},
++{"xsiexpqp", X(63,868), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
+
+-{"fctidu", XRC(63,942,0), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
+-{"fctidu.", XRC(63,942,1), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
++{"fctidu", XRC(63,942,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
++{"fctidu.", XRC(63,942,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
+
+-{"fctiduz", XRC(63,943,0), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
+-{"fctiduz.", XRC(63,943,1), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
++{"fctiduz", XRC(63,943,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
++{"fctiduz.", XRC(63,943,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
+
+-{"fmrgew", X(63,966), X_MASK, PPCVSX2, PPCNONE, {FRT, FRA, FRB}},
++{"fmrgew", X(63,966), X_MASK, PPCVSX2, PPCVLE, {FRT, FRA, FRB}},
+
+-{"fcfidu", XRC(63,974,0), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
+-{"fcfidu.", XRC(63,974,1), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
++{"fcfidu", XRC(63,974,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
++{"fcfidu.", XRC(63,974,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
+ };
+
+ const int powerpc_num_opcodes =
+@@ -6998,226 +6997,225 @@ const int powerpc_num_opcodes =
+ The format of this opcode table is the same as the main opcode table. */
+
+ const struct powerpc_opcode vle_opcodes[] = {
+-
+-{"se_illegal", C(0), C_MASK, PPCVLE, PPCNONE, {}},
+-{"se_isync", C(1), C_MASK, PPCVLE, PPCNONE, {}},
+-{"se_sc", C(2), C_MASK, PPCVLE, PPCNONE, {}},
+-{"se_blr", C_LK(2,0), C_LK_MASK, PPCVLE, PPCNONE, {}},
+-{"se_blrl", C_LK(2,1), C_LK_MASK, PPCVLE, PPCNONE, {}},
+-{"se_bctr", C_LK(3,0), C_LK_MASK, PPCVLE, PPCNONE, {}},
+-{"se_bctrl", C_LK(3,1), C_LK_MASK, PPCVLE, PPCNONE, {}},
+-{"se_rfi", C(8), C_MASK, PPCVLE, PPCNONE, {}},
+-{"se_rfci", C(9), C_MASK, PPCVLE, PPCNONE, {}},
+-{"se_rfdi", C(10), C_MASK, PPCVLE, PPCNONE, {}},
+-{"se_rfmci", C(11), C_MASK, PPCVLE, PPCNONE, {}},
+-{"se_not", SE_R(0,2), SE_R_MASK, PPCVLE, PPCNONE, {RX}},
+-{"se_neg", SE_R(0,3), SE_R_MASK, PPCVLE, PPCNONE, {RX}},
+-{"se_mflr", SE_R(0,8), SE_R_MASK, PPCVLE, PPCNONE, {RX}},
+-{"se_mtlr", SE_R(0,9), SE_R_MASK, PPCVLE, PPCNONE, {RX}},
+-{"se_mfctr", SE_R(0,10), SE_R_MASK, PPCVLE, PPCNONE, {RX}},
+-{"se_mtctr", SE_R(0,11), SE_R_MASK, PPCVLE, PPCNONE, {RX}},
+-{"se_extzb", SE_R(0,12), SE_R_MASK, PPCVLE, PPCNONE, {RX}},
+-{"se_extsb", SE_R(0,13), SE_R_MASK, PPCVLE, PPCNONE, {RX}},
+-{"se_extzh", SE_R(0,14), SE_R_MASK, PPCVLE, PPCNONE, {RX}},
+-{"se_extsh", SE_R(0,15), SE_R_MASK, PPCVLE, PPCNONE, {RX}},
+-{"se_mr", SE_RR(0,1), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}},
+-{"se_mtar", SE_RR(0,2), SE_RR_MASK, PPCVLE, PPCNONE, {ARX, RY}},
+-{"se_mfar", SE_RR(0,3), SE_RR_MASK, PPCVLE, PPCNONE, {RX, ARY}},
+-{"se_add", SE_RR(1,0), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}},
+-{"se_mullw", SE_RR(1,1), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}},
+-{"se_sub", SE_RR(1,2), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}},
+-{"se_subf", SE_RR(1,3), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}},
+-{"se_cmp", SE_RR(3,0), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}},
+-{"se_cmpl", SE_RR(3,1), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}},
+-{"se_cmph", SE_RR(3,2), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}},
+-{"se_cmphl", SE_RR(3,3), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}},
+-
+-{"e_cmpi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, PPCNONE, {CRD32, RA, SCLSCI8}},
+-{"e_cmpli", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, PPCNONE, {CRD32, RA, SCLSCI8}},
+-{"e_addi", SCI8(6,16), SCI8_MASK, PPCVLE, PPCNONE, {RT, RA, SCLSCI8}},
+-{"e_subi", SCI8(6,16), SCI8_MASK, PPCVLE, PPCNONE, {RT, RA, SCLSCI8N}},
+-{"e_addi.", SCI8(6,17), SCI8_MASK, PPCVLE, PPCNONE, {RT, RA, SCLSCI8}},
+-{"e_addic", SCI8(6,18), SCI8_MASK, PPCVLE, PPCNONE, {RT, RA, SCLSCI8}},
+-{"e_subic", SCI8(6,18), SCI8_MASK, PPCVLE, PPCNONE, {RT, RA, SCLSCI8N}},
+-{"e_addic.", SCI8(6,19), SCI8_MASK, PPCVLE, PPCNONE, {RT, RA, SCLSCI8}},
+-{"e_subic.", SCI8(6,19), SCI8_MASK, PPCVLE, PPCNONE, {RT, RA, SCLSCI8N}},
+-{"e_mulli", SCI8(6,20), SCI8_MASK, PPCVLE, PPCNONE, {RT, RA, SCLSCI8}},
+-{"e_subfic", SCI8(6,22), SCI8_MASK, PPCVLE, PPCNONE, {RT, RA, SCLSCI8}},
+-{"e_subfic.", SCI8(6,23), SCI8_MASK, PPCVLE, PPCNONE, {RT, RA, SCLSCI8}},
+-{"e_andi", SCI8(6,24), SCI8_MASK, PPCVLE, PPCNONE, {RA, RS, SCLSCI8}},
+-{"e_andi.", SCI8(6,25), SCI8_MASK, PPCVLE, PPCNONE, {RA, RS, SCLSCI8}},
+-{"e_nop", SCI8(6,26), 0xffffffff, PPCVLE, PPCNONE, {0}},
+-{"e_ori", SCI8(6,26), SCI8_MASK, PPCVLE, PPCNONE, {RA, RS, SCLSCI8}},
+-{"e_ori.", SCI8(6,27), SCI8_MASK, PPCVLE, PPCNONE, {RA, RS, SCLSCI8}},
+-{"e_xori", SCI8(6,28), SCI8_MASK, PPCVLE, PPCNONE, {RA, RS, SCLSCI8}},
+-{"e_xori.", SCI8(6,29), SCI8_MASK, PPCVLE, PPCNONE, {RA, RS, SCLSCI8}},
+-{"e_lbzu", OPVUP(6,0), OPVUP_MASK, PPCVLE, PPCNONE, {RT, D8, RA0}},
+-{"e_lhau", OPVUP(6,3), OPVUP_MASK, PPCVLE, PPCNONE, {RT, D8, RA0}},
+-{"e_lhzu", OPVUP(6,1), OPVUP_MASK, PPCVLE, PPCNONE, {RT, D8, RA0}},
+-{"e_lmw", OPVUP(6,8), OPVUP_MASK, PPCVLE, PPCNONE, {RT, D8, RA0}},
+-{"e_lwzu", OPVUP(6,2), OPVUP_MASK, PPCVLE, PPCNONE, {RT, D8, RA0}},
+-{"e_stbu", OPVUP(6,4), OPVUP_MASK, PPCVLE, PPCNONE, {RT, D8, RA0}},
+-{"e_sthu", OPVUP(6,5), OPVUP_MASK, PPCVLE, PPCNONE, {RT, D8, RA0}},
+-{"e_stwu", OPVUP(6,6), OPVUP_MASK, PPCVLE, PPCNONE, {RT, D8, RA0}},
+-{"e_stmw", OPVUP(6,9), OPVUP_MASK, PPCVLE, PPCNONE, {RT, D8, RA0}},
+-{"e_add16i", OP(7), OP_MASK, PPCVLE, PPCNONE, {RT, RA, SI}},
+-{"e_la", OP(7), OP_MASK, PPCVLE, PPCNONE, {RT, D, RA0}},
+-{"e_sub16i", OP(7), OP_MASK, PPCVLE, PPCNONE, {RT, RA, NSI}},
+-
+-{"se_addi", SE_IM5(8,0), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, OIMM5}},
+-{"se_cmpli", SE_IM5(8,1), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, OIMM5}},
+-{"se_subi", SE_IM5(9,0), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, OIMM5}},
+-{"se_subi.", SE_IM5(9,1), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, OIMM5}},
+-{"se_cmpi", SE_IM5(10,1), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, UI5}},
+-{"se_bmaski", SE_IM5(11,0), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, UI5}},
+-{"se_andi", SE_IM5(11,1), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, UI5}},
+-
+-{"e_lbz", OP(12), OP_MASK, PPCVLE, PPCNONE, {RT, D, RA0}},
+-{"e_stb", OP(13), OP_MASK, PPCVLE, PPCNONE, {RT, D, RA0}},
+-{"e_lha", OP(14), OP_MASK, PPCVLE, PPCNONE, {RT, D, RA0}},
+-
+-{"se_srw", SE_RR(16,0), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}},
+-{"se_sraw", SE_RR(16,1), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}},
+-{"se_slw", SE_RR(16,2), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}},
+-{"se_nop", SE_RR(17,0), 0xffff, PPCVLE, PPCNONE, {0}},
+-{"se_or", SE_RR(17,0), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}},
+-{"se_andc", SE_RR(17,1), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}},
+-{"se_and", SE_RR(17,2), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}},
+-{"se_and.", SE_RR(17,3), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}},
+-{"se_li", IM7(9), IM7_MASK, PPCVLE, PPCNONE, {RX, UI7}},
+-
+-{"e_lwz", OP(20), OP_MASK, PPCVLE, PPCNONE, {RT, D, RA0}},
+-{"e_stw", OP(21), OP_MASK, PPCVLE, PPCNONE, {RT, D, RA0}},
+-{"e_lhz", OP(22), OP_MASK, PPCVLE, PPCNONE, {RT, D, RA0}},
+-{"e_sth", OP(23), OP_MASK, PPCVLE, PPCNONE, {RT, D, RA0}},
+-
+-{"se_bclri", SE_IM5(24,0), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, UI5}},
+-{"se_bgeni", SE_IM5(24,1), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, UI5}},
+-{"se_bseti", SE_IM5(25,0), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, UI5}},
+-{"se_btsti", SE_IM5(25,1), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, UI5}},
+-{"se_srwi", SE_IM5(26,0), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, UI5}},
+-{"se_srawi", SE_IM5(26,1), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, UI5}},
+-{"se_slwi", SE_IM5(27,0), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, UI5}},
+-
+-{"e_lis", I16L(28,28), I16L_MASK, PPCVLE, PPCNONE, {RD, VLEUIMML}},
+-{"e_and2is.", I16L(28,29), I16L_MASK, PPCVLE, PPCNONE, {RD, VLEUIMML}},
+-{"e_or2is", I16L(28,26), I16L_MASK, PPCVLE, PPCNONE, {RD, VLEUIMML}},
+-{"e_and2i.", I16L(28,25), I16L_MASK, PPCVLE, PPCNONE, {RD, VLEUIMML}},
+-{"e_or2i", I16L(28,24), I16L_MASK, PPCVLE, PPCNONE, {RD, VLEUIMML}},
+-{"e_cmphl16i", IA16(28,23), IA16_MASK, PPCVLE, PPCNONE, {RA, VLEUIMM}},
+-{"e_cmph16i", IA16(28,22), IA16_MASK, PPCVLE, PPCNONE, {RA, VLESIMM}},
+-{"e_cmpl16i", I16A(28,21), I16A_MASK, PPCVLE, PPCNONE, {RA, VLEUIMM}},
+-{"e_cmplwi", I16A(28,21), I16A_MASK, PPCVLE, PPCNONE, {RA, VLESIMM}},
+-{"e_mull2i", I16A(28,20), I16A_MASK, PPCVLE, PPCNONE, {RA, VLESIMM}},
+-{"e_cmp16i", IA16(28,19), IA16_MASK, PPCVLE, PPCNONE, {RA, VLESIMM}},
+-{"e_cmpwi", IA16(28,19), IA16_MASK, PPCVLE, PPCNONE, {RA, VLESIMM}},
+-{"e_sub2is", I16A(28,18), I16A_MASK, PPCVLE, PPCNONE, {RA, VLENSIMM}},
+-{"e_add2is", I16A(28,18), I16A_MASK, PPCVLE, PPCNONE, {RA, VLESIMM}},
+-{"e_sub2i.", I16A(28,17), I16A_MASK, PPCVLE, PPCNONE, {RA, VLENSIMM}},
+-{"e_add2i.", I16A(28,17), I16A_MASK, PPCVLE, PPCNONE, {RA, VLESIMM}},
+-{"e_li", LI20(28,0), LI20_MASK, PPCVLE, PPCNONE, {RT, IMM20}},
+-{"e_rlwimi", M(29,0), M_MASK, PPCVLE, PPCNONE, {RA, RS, SH, MB, ME}},
+-{"e_rlwinm", M(29,1), M_MASK, PPCVLE, PPCNONE, {RA, RT, SH, MBE, ME}},
+-{"e_b", BD24(30,0,0), BD24_MASK, PPCVLE, PPCNONE, {B24}},
+-{"e_bl", BD24(30,0,1), BD24_MASK, PPCVLE, PPCNONE, {B24}},
+-{"e_bdnz", EBD15(30,8,BO32DNZ,0), EBD15_MASK, PPCVLE, PPCNONE, {B15}},
+-{"e_bdnzl", EBD15(30,8,BO32DNZ,1), EBD15_MASK, PPCVLE, PPCNONE, {B15}},
+-{"e_bdz", EBD15(30,8,BO32DZ,0), EBD15_MASK, PPCVLE, PPCNONE, {B15}},
+-{"e_bdzl", EBD15(30,8,BO32DZ,1), EBD15_MASK, PPCVLE, PPCNONE, {B15}},
+-{"e_bge", EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
+-{"e_bgel", EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
+-{"e_bnl", EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
+-{"e_bnll", EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
+-{"e_blt", EBD15BI(30,8,BO32T,CBLT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
+-{"e_bltl", EBD15BI(30,8,BO32T,CBLT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
+-{"e_bgt", EBD15BI(30,8,BO32T,CBGT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
+-{"e_bgtl", EBD15BI(30,8,BO32T,CBGT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
+-{"e_ble", EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
+-{"e_blel", EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
+-{"e_bng", EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
+-{"e_bngl", EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
+-{"e_bne", EBD15BI(30,8,BO32F,CBEQ,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
+-{"e_bnel", EBD15BI(30,8,BO32F,CBEQ,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
+-{"e_beq", EBD15BI(30,8,BO32T,CBEQ,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
+-{"e_beql", EBD15BI(30,8,BO32T,CBEQ,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
+-{"e_bso", EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
+-{"e_bsol", EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
+-{"e_bun", EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
+-{"e_bunl", EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
+-{"e_bns", EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
+-{"e_bnsl", EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
+-{"e_bnu", EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
+-{"e_bnul", EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
+-{"e_bc", BD15(30,8,0), BD15_MASK, PPCVLE, PPCNONE, {BO32, BI32, B15}},
+-{"e_bcl", BD15(30,8,1), BD15_MASK, PPCVLE, PPCNONE, {BO32, BI32, B15}},
+-
+-{"e_bf", EBD15(30,8,BO32F,0), EBD15_MASK, PPCVLE, PPCNONE, {BI32,B15}},
+-{"e_bfl", EBD15(30,8,BO32F,1), EBD15_MASK, PPCVLE, PPCNONE, {BI32,B15}},
+-{"e_bt", EBD15(30,8,BO32T,0), EBD15_MASK, PPCVLE, PPCNONE, {BI32,B15}},
+-{"e_btl", EBD15(30,8,BO32T,1), EBD15_MASK, PPCVLE, PPCNONE, {BI32,B15}},
+-
+-{"e_cmph", X(31,14), X_MASK, PPCVLE, PPCNONE, {CRD, RA, RB}},
+-{"e_cmphl", X(31,46), X_MASK, PPCVLE, PPCNONE, {CRD, RA, RB}},
+-{"e_crandc", XL(31,129), XL_MASK, PPCVLE, PPCNONE, {BT, BA, BB}},
+-{"e_crnand", XL(31,225), XL_MASK, PPCVLE, PPCNONE, {BT, BA, BB}},
+-{"e_crnot", XL(31,33), XL_MASK, PPCVLE, PPCNONE, {BT, BA, BBA}},
+-{"e_crnor", XL(31,33), XL_MASK, PPCVLE, PPCNONE, {BT, BA, BB}},
+-{"e_crclr", XL(31,193), XL_MASK, PPCVLE, PPCNONE, {BT, BAT, BBA}},
+-{"e_crxor", XL(31,193), XL_MASK, PPCVLE, PPCNONE, {BT, BA, BB}},
+-{"e_mcrf", XL(31,16), XL_MASK, PPCVLE, PPCNONE, {CRD, CR}},
+-{"e_slwi", EX(31,112), EX_MASK, PPCVLE, PPCNONE, {RA, RS, SH}},
+-{"e_slwi.", EX(31,113), EX_MASK, PPCVLE, PPCNONE, {RA, RS, SH}},
+-
+-{"e_crand", XL(31,257), XL_MASK, PPCVLE, PPCNONE, {BT, BA, BB}},
+-
+-{"e_rlw", EX(31,560), EX_MASK, PPCVLE, PPCNONE, {RA, RS, RB}},
+-{"e_rlw.", EX(31,561), EX_MASK, PPCVLE, PPCNONE, {RA, RS, RB}},
+-
+-{"e_crset", XL(31,289), XL_MASK, PPCVLE, PPCNONE, {BT, BAT, BBA}},
+-{"e_creqv", XL(31,289), XL_MASK, PPCVLE, PPCNONE, {BT, BA, BB}},
+-
+-{"e_rlwi", EX(31,624), EX_MASK, PPCVLE, PPCNONE, {RA, RS, SH}},
+-{"e_rlwi.", EX(31,625), EX_MASK, PPCVLE, PPCNONE, {RA, RS, SH}},
+-
+-{"e_crorc", XL(31,417), XL_MASK, PPCVLE, PPCNONE, {BT, BA, BB}},
+-
+-{"e_crmove", XL(31,449), XL_MASK, PPCVLE, PPCNONE, {BT, BA, BBA}},
+-{"e_cror", XL(31,449), XL_MASK, PPCVLE, PPCNONE, {BT, BA, BB}},
+-
+-{"mtmas1", XSPR(31,467,625), XSPR_MASK, PPCVLE, PPCNONE, {RS}},
+-
+-{"e_srwi", EX(31,1136), EX_MASK, PPCVLE, PPCNONE, {RA, RS, SH}},
+-{"e_srwi.", EX(31,1137), EX_MASK, PPCVLE, PPCNONE, {RA, RS, SH}},
+-
+-{"se_lbz", SD4(8), SD4_MASK, PPCVLE, PPCNONE, {RZ, SE_SD, RX}},
+-
+-{"se_stb", SD4(9), SD4_MASK, PPCVLE, PPCNONE, {RZ, SE_SD, RX}},
+-
+-{"se_lhz", SD4(10), SD4_MASK, PPCVLE, PPCNONE, {RZ, SE_SDH, RX}},
+-
+-{"se_sth", SD4(11), SD4_MASK, PPCVLE, PPCNONE, {RZ, SE_SDH, RX}},
+-
+-{"se_lwz", SD4(12), SD4_MASK, PPCVLE, PPCNONE, {RZ, SE_SDW, RX}},
+-
+-{"se_stw", SD4(13), SD4_MASK, PPCVLE, PPCNONE, {RZ, SE_SDW, RX}},
+-
+-{"se_bge", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}},
+-{"se_bnl", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}},
+-{"se_ble", EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}},
+-{"se_bng", EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}},
+-{"se_bne", EBD8IO(28,0,2), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}},
+-{"se_bns", EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}},
+-{"se_bnu", EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}},
+-{"se_bf", EBD8IO(28,0,0), EBD8IO2_MASK, PPCVLE, PPCNONE, {BI16, B8}},
+-{"se_blt", EBD8IO(28,1,0), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}},
+-{"se_bgt", EBD8IO(28,1,1), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}},
+-{"se_beq", EBD8IO(28,1,2), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}},
+-{"se_bso", EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}},
+-{"se_bun", EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}},
+-{"se_bt", EBD8IO(28,1,0), EBD8IO2_MASK, PPCVLE, PPCNONE, {BI16, B8}},
+-{"se_bc", BD8IO(28), BD8IO_MASK, PPCVLE, PPCNONE, {BO16, BI16, B8}},
+-{"se_b", BD8(58,0,0), BD8_MASK, PPCVLE, PPCNONE, {B8}},
+-{"se_bl", BD8(58,0,1), BD8_MASK, PPCVLE, PPCNONE, {B8}},
++{"se_illegal", C(0), C_MASK, PPCVLE, 0, {}},
++{"se_isync", C(1), C_MASK, PPCVLE, 0, {}},
++{"se_sc", C(2), C_MASK, PPCVLE, 0, {}},
++{"se_blr", C_LK(2,0), C_LK_MASK, PPCVLE, 0, {}},
++{"se_blrl", C_LK(2,1), C_LK_MASK, PPCVLE, 0, {}},
++{"se_bctr", C_LK(3,0), C_LK_MASK, PPCVLE, 0, {}},
++{"se_bctrl", C_LK(3,1), C_LK_MASK, PPCVLE, 0, {}},
++{"se_rfi", C(8), C_MASK, PPCVLE, 0, {}},
++{"se_rfci", C(9), C_MASK, PPCVLE, 0, {}},
++{"se_rfdi", C(10), C_MASK, PPCVLE, 0, {}},
++{"se_rfmci", C(11), C_MASK, PPCRFMCI|PPCVLE, 0, {}},
++{"se_not", SE_R(0,2), SE_R_MASK, PPCVLE, 0, {RX}},
++{"se_neg", SE_R(0,3), SE_R_MASK, PPCVLE, 0, {RX}},
++{"se_mflr", SE_R(0,8), SE_R_MASK, PPCVLE, 0, {RX}},
++{"se_mtlr", SE_R(0,9), SE_R_MASK, PPCVLE, 0, {RX}},
++{"se_mfctr", SE_R(0,10), SE_R_MASK, PPCVLE, 0, {RX}},
++{"se_mtctr", SE_R(0,11), SE_R_MASK, PPCVLE, 0, {RX}},
++{"se_extzb", SE_R(0,12), SE_R_MASK, PPCVLE, 0, {RX}},
++{"se_extsb", SE_R(0,13), SE_R_MASK, PPCVLE, 0, {RX}},
++{"se_extzh", SE_R(0,14), SE_R_MASK, PPCVLE, 0, {RX}},
++{"se_extsh", SE_R(0,15), SE_R_MASK, PPCVLE, 0, {RX}},
++{"se_mr", SE_RR(0,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
++{"se_mtar", SE_RR(0,2), SE_RR_MASK, PPCVLE, 0, {ARX, RY}},
++{"se_mfar", SE_RR(0,3), SE_RR_MASK, PPCVLE, 0, {RX, ARY}},
++{"se_add", SE_RR(1,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
++{"se_mullw", SE_RR(1,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
++{"se_sub", SE_RR(1,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
++{"se_subf", SE_RR(1,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
++{"se_cmp", SE_RR(3,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
++{"se_cmpl", SE_RR(3,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
++{"se_cmph", SE_RR(3,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
++{"se_cmphl", SE_RR(3,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
++
++{"e_cmpi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
++{"e_cmpli", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
++{"e_addi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
++{"e_subi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}},
++{"e_addi.", SCI8(6,17), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
++{"e_addic", SCI8(6,18), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
++{"e_subic", SCI8(6,18), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}},
++{"e_addic.", SCI8(6,19), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
++{"e_subic.", SCI8(6,19), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}},
++{"e_mulli", SCI8(6,20), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
++{"e_subfic", SCI8(6,22), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
++{"e_subfic.", SCI8(6,23), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
++{"e_andi", SCI8(6,24), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
++{"e_andi.", SCI8(6,25), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
++{"e_nop", SCI8(6,26), 0xffffffff, PPCVLE, 0, {0}},
++{"e_ori", SCI8(6,26), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
++{"e_ori.", SCI8(6,27), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
++{"e_xori", SCI8(6,28), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
++{"e_xori.", SCI8(6,29), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
++{"e_lbzu", OPVUP(6,0), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
++{"e_lhau", OPVUP(6,3), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
++{"e_lhzu", OPVUP(6,1), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
++{"e_lmw", OPVUP(6,8), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
++{"e_lwzu", OPVUP(6,2), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
++{"e_stbu", OPVUP(6,4), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
++{"e_sthu", OPVUP(6,5), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
++{"e_stwu", OPVUP(6,6), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
++{"e_stmw", OPVUP(6,9), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
++{"e_add16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, SI}},
++{"e_la", OP(7), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
++{"e_sub16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, NSI}},
++
++{"se_addi", SE_IM5(8,0), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
++{"se_cmpli", SE_IM5(8,1), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
++{"se_subi", SE_IM5(9,0), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
++{"se_subi.", SE_IM5(9,1), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
++{"se_cmpi", SE_IM5(10,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
++{"se_bmaski", SE_IM5(11,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
++{"se_andi", SE_IM5(11,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
++
++{"e_lbz", OP(12), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
++{"e_stb", OP(13), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
++{"e_lha", OP(14), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
++
++{"se_srw", SE_RR(16,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
++{"se_sraw", SE_RR(16,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
++{"se_slw", SE_RR(16,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
++{"se_nop", SE_RR(17,0), 0xffff, PPCVLE, 0, {0}},
++{"se_or", SE_RR(17,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
++{"se_andc", SE_RR(17,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
++{"se_and", SE_RR(17,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
++{"se_and.", SE_RR(17,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
++{"se_li", IM7(9), IM7_MASK, PPCVLE, 0, {RX, UI7}},
++
++{"e_lwz", OP(20), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
++{"e_stw", OP(21), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
++{"e_lhz", OP(22), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
++{"e_sth", OP(23), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
++
++{"se_bclri", SE_IM5(24,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
++{"se_bgeni", SE_IM5(24,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
++{"se_bseti", SE_IM5(25,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
++{"se_btsti", SE_IM5(25,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
++{"se_srwi", SE_IM5(26,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
++{"se_srawi", SE_IM5(26,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
++{"se_slwi", SE_IM5(27,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
++
++{"e_lis", I16L(28,28), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
++{"e_and2is.", I16L(28,29), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
++{"e_or2is", I16L(28,26), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
++{"e_and2i.", I16L(28,25), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
++{"e_or2i", I16L(28,24), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
++{"e_cmphl16i", IA16(28,23), IA16_MASK, PPCVLE, 0, {RA, VLEUIMM}},
++{"e_cmph16i", IA16(28,22), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
++{"e_cmpl16i", I16A(28,21), I16A_MASK, PPCVLE, 0, {RA, VLEUIMM}},
++{"e_cmplwi", I16A(28,21), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
++{"e_mull2i", I16A(28,20), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
++{"e_cmp16i", IA16(28,19), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
++{"e_cmpwi", IA16(28,19), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
++{"e_sub2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
++{"e_add2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
++{"e_sub2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
++{"e_add2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
++{"e_li", LI20(28,0), LI20_MASK, PPCVLE, 0, {RT, IMM20}},
++{"e_rlwimi", M(29,0), M_MASK, PPCVLE, 0, {RA, RS, SH, MB, ME}},
++{"e_rlwinm", M(29,1), M_MASK, PPCVLE, 0, {RA, RT, SH, MBE, ME}},
++{"e_b", BD24(30,0,0), BD24_MASK, PPCVLE, 0, {B24}},
++{"e_bl", BD24(30,0,1), BD24_MASK, PPCVLE, 0, {B24}},
++{"e_bdnz", EBD15(30,8,BO32DNZ,0), EBD15_MASK, PPCVLE, 0, {B15}},
++{"e_bdnzl", EBD15(30,8,BO32DNZ,1), EBD15_MASK, PPCVLE, 0, {B15}},
++{"e_bdz", EBD15(30,8,BO32DZ,0), EBD15_MASK, PPCVLE, 0, {B15}},
++{"e_bdzl", EBD15(30,8,BO32DZ,1), EBD15_MASK, PPCVLE, 0, {B15}},
++{"e_bge", EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
++{"e_bgel", EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
++{"e_bnl", EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
++{"e_bnll", EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
++{"e_blt", EBD15BI(30,8,BO32T,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
++{"e_bltl", EBD15BI(30,8,BO32T,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
++{"e_bgt", EBD15BI(30,8,BO32T,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
++{"e_bgtl", EBD15BI(30,8,BO32T,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
++{"e_ble", EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
++{"e_blel", EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
++{"e_bng", EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
++{"e_bngl", EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
++{"e_bne", EBD15BI(30,8,BO32F,CBEQ,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
++{"e_bnel", EBD15BI(30,8,BO32F,CBEQ,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
++{"e_beq", EBD15BI(30,8,BO32T,CBEQ,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
++{"e_beql", EBD15BI(30,8,BO32T,CBEQ,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
++{"e_bso", EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
++{"e_bsol", EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
++{"e_bun", EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
++{"e_bunl", EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
++{"e_bns", EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
++{"e_bnsl", EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
++{"e_bnu", EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
++{"e_bnul", EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
++{"e_bc", BD15(30,8,0), BD15_MASK, PPCVLE, 0, {BO32, BI32, B15}},
++{"e_bcl", BD15(30,8,1), BD15_MASK, PPCVLE, 0, {BO32, BI32, B15}},
++
++{"e_bf", EBD15(30,8,BO32F,0), EBD15_MASK, PPCVLE, 0, {BI32,B15}},
++{"e_bfl", EBD15(30,8,BO32F,1), EBD15_MASK, PPCVLE, 0, {BI32,B15}},
++{"e_bt", EBD15(30,8,BO32T,0), EBD15_MASK, PPCVLE, 0, {BI32,B15}},
++{"e_btl", EBD15(30,8,BO32T,1), EBD15_MASK, PPCVLE, 0, {BI32,B15}},
++
++{"e_cmph", X(31,14), X_MASK, PPCVLE, 0, {CRD, RA, RB}},
++{"e_cmphl", X(31,46), X_MASK, PPCVLE, 0, {CRD, RA, RB}},
++{"e_crandc", XL(31,129), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
++{"e_crnand", XL(31,225), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
++{"e_crnot", XL(31,33), XL_MASK, PPCVLE, 0, {BT, BA, BBA}},
++{"e_crnor", XL(31,33), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
++{"e_crclr", XL(31,193), XL_MASK, PPCVLE, 0, {BT, BAT, BBA}},
++{"e_crxor", XL(31,193), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
++{"e_mcrf", XL(31,16), XL_MASK, PPCVLE, 0, {CRD, CR}},
++{"e_slwi", EX(31,112), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
++{"e_slwi.", EX(31,113), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
++
++{"e_crand", XL(31,257), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
++
++{"e_rlw", EX(31,560), EX_MASK, PPCVLE, 0, {RA, RS, RB}},
++{"e_rlw.", EX(31,561), EX_MASK, PPCVLE, 0, {RA, RS, RB}},
++
++{"e_crset", XL(31,289), XL_MASK, PPCVLE, 0, {BT, BAT, BBA}},
++{"e_creqv", XL(31,289), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
++
++{"e_rlwi", EX(31,624), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
++{"e_rlwi.", EX(31,625), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
++
++{"e_crorc", XL(31,417), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
++
++{"e_crmove", XL(31,449), XL_MASK, PPCVLE, 0, {BT, BA, BBA}},
++{"e_cror", XL(31,449), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
++
++{"mtmas1", XSPR(31,467,625), XSPR_MASK, PPCVLE, 0, {RS}},
++
++{"e_srwi", EX(31,1136), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
++{"e_srwi.", EX(31,1137), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
++
++{"se_lbz", SD4(8), SD4_MASK, PPCVLE, 0, {RZ, SE_SD, RX}},
++
++{"se_stb", SD4(9), SD4_MASK, PPCVLE, 0, {RZ, SE_SD, RX}},
++
++{"se_lhz", SD4(10), SD4_MASK, PPCVLE, 0, {RZ, SE_SDH, RX}},
++
++{"se_sth", SD4(11), SD4_MASK, PPCVLE, 0, {RZ, SE_SDH, RX}},
++
++{"se_lwz", SD4(12), SD4_MASK, PPCVLE, 0, {RZ, SE_SDW, RX}},
++
++{"se_stw", SD4(13), SD4_MASK, PPCVLE, 0, {RZ, SE_SDW, RX}},
++
++{"se_bge", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, 0, {B8}},
++{"se_bnl", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, 0, {B8}},
++{"se_ble", EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, 0, {B8}},
++{"se_bng", EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, 0, {B8}},
++{"se_bne", EBD8IO(28,0,2), EBD8IO3_MASK, PPCVLE, 0, {B8}},
++{"se_bns", EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, 0, {B8}},
++{"se_bnu", EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, 0, {B8}},
++{"se_bf", EBD8IO(28,0,0), EBD8IO2_MASK, PPCVLE, 0, {BI16, B8}},
++{"se_blt", EBD8IO(28,1,0), EBD8IO3_MASK, PPCVLE, 0, {B8}},
++{"se_bgt", EBD8IO(28,1,1), EBD8IO3_MASK, PPCVLE, 0, {B8}},
++{"se_beq", EBD8IO(28,1,2), EBD8IO3_MASK, PPCVLE, 0, {B8}},
++{"se_bso", EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, 0, {B8}},
++{"se_bun", EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, 0, {B8}},
++{"se_bt", EBD8IO(28,1,0), EBD8IO2_MASK, PPCVLE, 0, {BI16, B8}},
++{"se_bc", BD8IO(28), BD8IO_MASK, PPCVLE, 0, {BO16, BI16, B8}},
++{"se_b", BD8(58,0,0), BD8_MASK, PPCVLE, 0, {B8}},
++{"se_bl", BD8(58,0,1), BD8_MASK, PPCVLE, 0, {B8}},
+ };
+
+ const int vle_num_opcodes =
+@@ -7251,7 +7249,7 @@ const struct powerpc_macro powerpc_macros[] = {
+ {"clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)"},
+ {"clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)"},
+ {"clrlsldi", 4, PPC64, "rldic %0,%1,%3,(%2)-(%3)"},
+-{"clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)"},
++{"clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)"},
+
+ {"extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1"},
+ {"extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1"},
diff --git a/SOURCES/gdb-rhbz1320945-power9-32of38.patch b/SOURCES/gdb-rhbz1320945-power9-32of38.patch
new file mode 100644
index 0000000..022f015
--- /dev/null
+++ b/SOURCES/gdb-rhbz1320945-power9-32of38.patch
@@ -0,0 +1,187 @@
+commit 6fd3a02da5548c71ff469f978444ef6c3af18783
+Author: Peter Bergner <bergner@vnet.ibm.com>
+Date: Wed Jun 22 17:55:17 2016 -0500
+
+ Add support for yet some more new ISA 3.0 instructions.
+
+ opcodes/
+ * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
+ (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
+ mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
+ xor3>: New mnemonics.
+ <setb>: Change to a VX form instruction.
+ (insert_sh6): Add support for rldixor.
+ (extract_sh6): Likewise.
+
+ gas/
+ * testsuite/gas/ppc/power9.d <brd, brh, brw, mffs, mffs., mffsce,
+ mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl, nandxor, rldixor,
+ setbool, xor3>: New tests.
+ * testsuite/gas/ppc/power9.s: Likewise.
+
+### a/opcodes/ChangeLog
+### b/opcodes/ChangeLog
+## -1,3 +1,13 @@
++2016-06-22 Peter Bergner <bergner@vnet.ibm.com>
++
++ * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
++ (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
++ mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
++ xor3>: New mnemonics.
++ <setb>: Change to a VX form instruction.
++ (insert_sh6): Add support for rldixor.
++ (extract_sh6): Likewise.
++
+ 2016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
+
+ * arc-ext.h: Wrap in extern C.
+--- a/opcodes/ppc-opc.c
++++ b/opcodes/ppc-opc.c
+@@ -238,7 +238,11 @@ const struct powerpc_operand powerpc_operands[] =
+ #define BOE BO + 1
+ { 0x1e, 21, insert_boe, extract_boe, 0 },
+
+-#define BH BOE + 1
++ /* The RM field in an X form instruction. */
++#define RM BOE + 1
++ { 0x3, 11, NULL, NULL, 0 },
++
++#define BH RM + 1
+ { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
+
+ /* The BT field in an X or XL form instruction. */
+@@ -786,8 +790,9 @@ const struct powerpc_operand powerpc_operands[] =
+ #define EVUIMM_8 EVUIMM_4 + 1
+ { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS },
+
+- /* The WS field. */
++ /* The WS or DRM field in an X form instruction. */
+ #define WS EVUIMM_8 + 1
++#define DRM WS
+ { 0x7, 11, NULL, NULL, 0 },
+
+ /* PowerPC paired singles extensions. */
+@@ -2017,7 +2022,11 @@ insert_sh6 (unsigned long insn,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+ {
+- return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
++ /* SH6 operand in the rldixor instructions. */
++ if (PPC_OP (insn) == 4)
++ return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 5);
++ else
++ return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
+ }
+
+ static long
+@@ -2025,7 +2034,11 @@ extract_sh6 (unsigned long insn,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid ATTRIBUTE_UNUSED)
+ {
+- return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
++ /* SH6 operand in the rldixor instructions. */
++ if (PPC_OP (insn) == 4)
++ return ((insn >> 6) & 0x1f) | ((insn << 5) & 0x20);
++ else
++ return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
+ }
+
+ /* The SPR field in an XFX form instruction. This is flipped--the
+@@ -2608,6 +2621,9 @@ extract_vleil (unsigned long insn,
+ /* A VX form instruction with a VA tertiary opcode. */
+ #define VXVA(op, xop, vaop) (VX(op,xop) | (((vaop) & 0x1f) << 16))
+
++#define VXASH(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
++#define VXASH_MASK VXASH (0x3f, 0x1f)
++
+ /* An X form instruction. */
+ #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
+
+@@ -2644,6 +2660,9 @@ extract_vleil (unsigned long insn,
+ /* A X form instruction for Quad-Precision FP Instructions with RC bit. */
+ #define XVARC(op, xop, vaop, rc) (XVA ((op), (xop), (vaop)) | ((rc) & 1))
+
++/* An X form instruction with the RA bits specified as two ops. */
++#define XMMF(op, xop, mop0, mop1) (X ((op), (xop)) | ((mop0) & 3) << 19 | ((mop1) & 7) << 16)
++
+ /* A Z form instruction with the RC bit specified. */
+ #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
+
+@@ -2696,6 +2715,9 @@ extract_vleil (unsigned long insn,
+ /* An X form wait instruction with everything filled in except the WC field. */
+ #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
+
++/* The mask for an XMMF form instruction. */
++#define XMMF_MASK (XMMF (0x3f, 0x3ff, 3, 7) | (1))
++
+ /* The mask for a Z form instruction. */
+ #define Z_MASK ZRC (0x3f, 0x1ff, 1)
+ #define Z2_MASK ZRC (0x3f, 0xff, 1)
+@@ -3139,6 +3161,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"machhwu.", XO (4, 12,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
+ {"ps_muls1", A (4, 13,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
+ {"ps_muls1.", A (4, 13,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
++{"rldixor", VXASH(4,26), VXASH_MASK, POWER9, 0, {RA, RS, SH6, RB}},
+ {"ps_madds0", A (4, 14,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
+ {"ps_madds0.", A (4, 14,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
+ {"ps_madds1", A (4, 15,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
+@@ -3180,6 +3203,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"ps_msub.", A (4, 28,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
+ {"ps_madd", A (4, 29,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
+ {"ps_madd.", A (4, 29,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
++{"xor3", VXA(4, 54), VXA_MASK, POWER9, 0, {RA, RS, RB, RC}},
++{"nandxor", VXA(4, 55), VXA_MASK, POWER9, 0, {RA, RS, RB, RC}},
+ {"vpermr", VXA(4, 59), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}},
+ {"ps_nmsub", A (4, 30,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
+ {"vaddeuqm", VXA(4, 60), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
+@@ -4918,7 +4943,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+
+ {"dcbfep", XRT(31,127,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
+
+-{"setb", X(31,128), XRB_MASK|(3<<16), POWER9, 0, {RT, BFA}},
++{"setb", VX(31,256), VXVB_MASK|(3<<16), POWER9, 0, {RT, BFA}},
++{"setbool", VX(31,257), VXVB_MASK, POWER9, 0, {RT, BA}},
+
+ {"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RS}},
+
+@@ -4968,6 +4994,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+
+ {"prtyw", X(31,154), XRB_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS}},
+
++{"brw", X(31,155), XRB_MASK, POWER9, 0, {RA, RS}},
++
+ {"stdepx", X(31,157), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
+
+ {"stwepx", X(31,159), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
+@@ -5005,6 +5033,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+
+ {"prtyd", X(31,186), XRB_MASK, POWER6|PPCA2, 0, {RA, RS}},
+
++{"brd", X(31,187), XRB_MASK, POWER9, 0, {RA, RS}},
++
+ {"cmprb", X(31,192), XCMP_MASK, POWER9, 0, {BF, L, RA, RB}},
+
+ {"icblq.", XRC(31,198,1), X_MASK, E6500, 0, {CT, RA0, RB}},
+@@ -5043,6 +5073,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"sleq", XRC(31,217,0), X_MASK, M601, 0, {RA, RS, RB}},
+ {"sleq.", XRC(31,217,1), X_MASK, M601, 0, {RA, RS, RB}},
+
++{"brh", X(31,219), XRB_MASK, POWER9, 0, {RA, RS}},
++
+ {"stbepx", X(31,223), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
+
+ {"cmpeqb", X(31,224), XCMPL_MASK, POWER9, 0, {BF, RA, RB}},
+@@ -6914,6 +6946,13 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"mffs", XRC(63,583,0), XRARB_MASK, COM, PPCEFS|PPCVLE, {FRT}},
+ {"mffs.", XRC(63,583,1), XRARB_MASK, COM, PPCEFS|PPCVLE, {FRT}},
+
++{"mffsce", XMMF(63,583,0,1), XMMF_MASK|RB_MASK, POWER9, PPCVLE, {FRT}},
++{"mffscdrn", XMMF(63,583,2,4), XMMF_MASK, POWER9, PPCVLE, {FRT, FRB}},
++{"mffscdrni", XMMF(63,583,2,5), XMMF_MASK|(3<<14), POWER9, PPCVLE, {FRT, DRM}},
++{"mffscrn", XMMF(63,583,2,6), XMMF_MASK, POWER9, PPCVLE, {FRT, FRB}},
++{"mffscrni", XMMF(63,583,2,7), XMMF_MASK|(7<<13), POWER9, PPCVLE, {FRT, RM}},
++{"mffsl", XMMF(63,583,3,0), XMMF_MASK|RB_MASK, POWER9, PPCVLE, {FRT}},
++
+ {"dcmpuq", X(63,642), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}},
+
+ {"xscmpuqp", X(63,644), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}},
diff --git a/SOURCES/gdb-rhbz1320945-power9-33of38.patch b/SOURCES/gdb-rhbz1320945-power9-33of38.patch
new file mode 100644
index 0000000..8e127ec
--- /dev/null
+++ b/SOURCES/gdb-rhbz1320945-power9-33of38.patch
@@ -0,0 +1,172 @@
+commit fd486b633e87f8ab2977592d56a6d98168814e2e
+Author: Peter Bergner <bergner@vnet.ibm.com>
+Date: Wed Sep 14 22:10:51 2016 -0500
+
+ Modify POWER9 support to match final ISA 3.0 documentation.
+
+ opcodes/
+ * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
+ <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
+ xor3>: Delete mnemonics.
+ <cp_abort>: Rename mnemonic from ...
+ <cpabort>: ...to this.
+ <setb>: Change to a X form instruction.
+ <sync>: Change to 1 operand form.
+ <copy>: Delete mnemonic.
+ <copy_first>: Rename mnemonic from ...
+ <copy>: ...to this.
+ <paste, paste.>: Delete mnemonics.
+ <paste_last>: Rename mnemonic from ...
+ <paste.>: ...to this.
+
+ gas/
+ * testsuite/gas/ppc/power9.d <slbiag, cpabort> New tests.
+ <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
+ xor3, cp_abort, copy_first, paste, paste_last, sync>: Remove tests.
+ <copy, paste.>: Update tests.
+ * testsuite/gas/ppc/power9.s: Likewise.
+
+### a/opcodes/ChangeLog
+### b/opcodes/ChangeLog
+## -1,3 +1,19 @@
++2016-09-14 Peter Bergner <bergner@vnet.ibm.com>
++
++ * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
++ <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
++ xor3>: Delete mnemonics.
++ <cp_abort>: Rename mnemonic from ...
++ <cpabort>: ...to this.
++ <setb>: Change to a X form instruction.
++ <sync>: Change to 1 operand form.
++ <copy>: Delete mnemonic.
++ <copy_first>: Rename mnemonic from ...
++ <copy>: ...to this.
++ <paste, paste.>: Delete mnemonics.
++ <paste_last>: Rename mnemonic from ...
++ <paste.>: ...to this.
++
+ 2016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
+
+ * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
+--- a/opcodes/ppc-opc.c
++++ b/opcodes/ppc-opc.c
+@@ -3168,7 +3168,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"machhwu.", XO (4, 12,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
+ {"ps_muls1", A (4, 13,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
+ {"ps_muls1.", A (4, 13,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
+-{"rldixor", VXASH(4,26), VXASH_MASK, POWER9, 0, {RA, RS, SH6, RB}},
+ {"ps_madds0", A (4, 14,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
+ {"ps_madds0.", A (4, 14,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
+ {"ps_madds1", A (4, 15,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
+@@ -3210,8 +3209,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"ps_msub.", A (4, 28,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
+ {"ps_madd", A (4, 29,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
+ {"ps_madd.", A (4, 29,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
+-{"xor3", VXA(4, 54), VXA_MASK, POWER9, 0, {RA, RS, RB, RC}},
+-{"nandxor", VXA(4, 55), VXA_MASK, POWER9, 0, {RA, RS, RB, RC}},
+ {"vpermr", VXA(4, 59), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}},
+ {"ps_nmsub", A (4, 30,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
+ {"vaddeuqm", VXA(4, 60), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
+@@ -4950,8 +4947,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+
+ {"dcbfep", XRT(31,127,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
+
+-{"setb", VX(31,256), VXVB_MASK|(3<<16), POWER9, 0, {RT, BFA}},
+-{"setbool", VX(31,257), VXVB_MASK, POWER9, 0, {RT, BA}},
++{"setb", X(31,128), XRB_MASK|(3<<16), POWER9, 0, {RT, BFA}},
+
+ {"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RS}},
+
+@@ -5001,8 +4997,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+
+ {"prtyw", X(31,154), XRB_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS}},
+
+-{"brw", X(31,155), XRB_MASK, POWER9, 0, {RA, RS}},
+-
+ {"stdepx", X(31,157), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
+
+ {"stwepx", X(31,159), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
+@@ -5015,7 +5009,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"sthfcmx", APU(31,167,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
+
+ {"addex", ZRC(31,170,0), Z2_MASK, POWER9, 0, {RT, RA, RB, CY}},
+-{"addex.", ZRC(31,170,1), Z2_MASK, POWER9, 0, {RT, RA, RB, CY}},
+
+ {"msgclrp", XRTRA(31,174,0,0), XRTRA_MASK, POWER8, 0, {RB}},
+ {"dcbtlse", X(31,174), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}},
+@@ -5040,8 +5033,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+
+ {"prtyd", X(31,186), XRB_MASK, POWER6|PPCA2, 0, {RA, RS}},
+
+-{"brd", X(31,187), XRB_MASK, POWER9, 0, {RA, RS}},
+-
+ {"cmprb", X(31,192), XCMP_MASK, POWER9, 0, {BF, L, RA, RB}},
+
+ {"icblq.", XRC(31,198,1), X_MASK, E6500, 0, {CT, RA0, RB}},
+@@ -5080,8 +5071,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"sleq", XRC(31,217,0), X_MASK, M601, 0, {RA, RS, RB}},
+ {"sleq.", XRC(31,217,1), X_MASK, M601, 0, {RA, RS, RB}},
+
+-{"brh", X(31,219), XRB_MASK, POWER9, 0, {RA, RS}},
+-
+ {"stbepx", X(31,223), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
+
+ {"cmpeqb", X(31,224), XCMPL_MASK, POWER9, 0, {BF, RA, RB}},
+@@ -5548,8 +5537,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+
+ {"mtvsrdd", X(31,435), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
+
+-{"lwzmx", X(31,437), X_MASK, POWER9, 0, {RT, RA0, RB}},
+-
+ {"ecowx", X(31,438), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
+
+ {"sthux", X(31,439), X_MASK, COM, 0, {RS, RAS, RB}},
+@@ -5916,8 +5903,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"hwsync", XSYNC(31,598,0), 0xffffffff, POWER4, BOOKE|PPC476, {0}},
+ {"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, E500, {0}},
+ {"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, 0, {0}},
+-{"sync", X(31,598), XSYNCLE_MASK, POWER9|E6500, 0, {LS, ESYNC}},
+-{"sync", X(31,598), XSYNC_MASK, PPCCOM, BOOKE|PPC476|POWER9, {LS}},
++{"sync", X(31,598), XSYNCLE_MASK, E6500, 0, {LS, ESYNC}},
++{"sync", X(31,598), XSYNC_MASK, PPCCOM, BOOKE|PPC476, {LS}},
+ {"msync", X(31,598), 0xffffffff, BOOKE|PPCA2|PPC476, 0, {0}},
+ {"sync", X(31,598), 0xffffffff, BOOKE|PPC476, E6500, {0}},
+ {"lwsync", X(31,598), 0xffffffff, E500, 0, {0}},
+@@ -6085,8 +6072,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+
+ {"lvsm", X(31,773), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
+
+-{"copy_first", XOPL(31,774,1), XRT_MASK, POWER9, 0, {RA0, RB}},
+-{"copy", X(31,774), XLRT_MASK, POWER9, 0, {RA0, RB, L}},
++{"copy", XOPL(31,774,1), XRT_MASK, POWER9, 0, {RA0, RB}},
+
+ {"stvepxl", X(31,775), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
+ {"lvlxl", X(31,775), X_MASK, CELL, 0, {VD, RA0, RB}},
+@@ -6156,7 +6142,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+
+ {"lvtlxl", X(31,837), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
+
+-{"cp_abort", X(31,838), XRTRARB_MASK,POWER9, 0, {0}},
++{"cpabort", X(31,838), XRTRARB_MASK,POWER9, 0, {0}},
+
+ {"divo", XO(31,331,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
+ {"divo.", XO(31,331,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
+@@ -6168,6 +6154,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+
+ {"tlbsrx.", XRC(31,850,1), XRT_MASK, PPCA2, 0, {RA0, RB}},
+
++{"slbiag", X(31,850), XRARB_MASK, POWER9, 0, {RS}},
+ {"slbmfev", X(31,851), XRLA_MASK, POWER9, 0, {RT, RB, A_L}},
+ {"slbmfev", X(31,851), XRA_MASK, PPC64, POWER9, {RT, RB}},
+
+@@ -6203,9 +6190,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"extswsli", XS(31,445,0), XS_MASK, POWER9, 0, {RA, RS, SH6}},
+ {"extswsli.", XS(31,445,1), XS_MASK, POWER9, 0, {RA, RS, SH6}},
+
+-{"paste", XRC(31,902,0), XLRT_MASK, POWER9, 0, {RA0, RB, L0}},
+-{"paste_last", XRCL(31,902,1,1),XRT_MASK, POWER9, 0, {RA0, RB}},
+-{"paste.", XRC(31,902,1), XLRT_MASK, POWER9, 0, {RA0, RB, L1}},
++{"paste.", XRCL(31,902,1,1),XRT_MASK, POWER9, 0, {RA0, RB}},
+
+ {"stvlxl", X(31,903), X_MASK, CELL, 0, {VS, RA0, RB}},
+ {"stdfcmux", APU(31,903,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
diff --git a/SOURCES/gdb-rhbz1320945-power9-34of38.patch b/SOURCES/gdb-rhbz1320945-power9-34of38.patch
new file mode 100644
index 0000000..9f9d831
--- /dev/null
+++ b/SOURCES/gdb-rhbz1320945-power9-34of38.patch
@@ -0,0 +1,806 @@
+commit 6ec2b213de6962ceeb81bfa33354ea6e60c57049
+Author: Edjunior Barbosa Machado <emachado@linux.vnet.ibm.com>
+Date: Wed Sep 21 13:30:39 2016 -0300
+
+ ppc: Add Power ISA 3.0/POWER9 instructions record support
+
+ gdb/ChangeLog:
+ 2016-09-21 Edjunior Barbosa Machado <emachado@linux.vnet.ibm.com>
+
+ * rs6000-tdep.c (PPC_DQ): New macro.
+ (ppc_process_record_op4): Add Power ISA 3.0 instructions.
+ (ppc_process_record_op19): Likewise.
+ (ppc_process_record_op31): Likewise.
+ (ppc_process_record_op59): Likewise.
+ (ppc_process_record_op60): Likewise.
+ (ppc_process_record_op63): Likewise.
+ (ppc_process_record): Likewise.
+ (ppc_process_record_op61): New function.
+
+### a/gdb/ChangeLog
+### b/gdb/ChangeLog
+## -1,3 +1,15 @@
++2016-09-21 Edjunior Barbosa Machado <emachado@linux.vnet.ibm.com>
++
++ * rs6000-tdep.c (PPC_DQ): New macro.
++ (ppc_process_record_op4): Add Power ISA 3.0 instructions.
++ (ppc_process_record_op19): Likewise.
++ (ppc_process_record_op31): Likewise.
++ (ppc_process_record_op59): Likewise.
++ (ppc_process_record_op60): Likewise.
++ (ppc_process_record_op63): Likewise.
++ (ppc_process_record): Likewise.
++ (ppc_process_record_op61): New function.
++
+ 2016-09-21 Yao Qi <yao.qi@linaro.org>
+
+ * aarch32-linux-nat.c (aarch32_gp_regcache_collect): Keep
+Index: gdb-7.6.1/gdb/rs6000-tdep.c
+===================================================================
+--- gdb-7.6.1.orig/gdb/rs6000-tdep.c 2017-03-19 00:08:32.893569127 +0100
++++ gdb-7.6.1/gdb/rs6000-tdep.c 2017-03-19 00:08:49.775687752 +0100
+@@ -3721,6 +3721,7 @@
+ #define PPC_T(insn) PPC_FIELD (insn, 6, 5)
+ #define PPC_D(insn) PPC_SEXT (PPC_FIELD (insn, 16, 16), 16)
+ #define PPC_DS(insn) PPC_SEXT (PPC_FIELD (insn, 16, 14), 14)
++#define PPC_DQ(insn) PPC_SEXT (PPC_FIELD (insn, 16, 12), 12)
+ #define PPC_BIT(insn,n) ((insn & (1 << (31 - (n)))) ? 1 : 0)
+ #define PPC_OE(insn) PPC_BIT (insn, 21)
+ #define PPC_RC(insn) PPC_BIT (insn, 31)
+@@ -3768,6 +3769,7 @@
+ {
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ int ext = PPC_FIELD (insn, 21, 11);
++ int vra = PPC_FIELD (insn, 11, 5);
+
+ switch (ext & 0x3f)
+ {
+@@ -3779,6 +3781,7 @@
+ /* FALL-THROUGH */
+ case 42: /* Vector Select */
+ case 43: /* Vector Permute */
++ case 59: /* Vector Permute Right-indexed */
+ case 44: /* Vector Shift Left Double by Octet Immediate */
+ case 45: /* Vector Permute and Exclusive-OR */
+ case 60: /* Vector Add Extended Unsigned Quadword Modulo */
+@@ -3786,6 +3789,7 @@
+ case 62: /* Vector Subtract Extended Unsigned Quadword Modulo */
+ case 63: /* Vector Subtract Extended & write Carry Unsigned Quadword */
+ case 34: /* Vector Multiply-Low-Add Unsigned Halfword Modulo */
++ case 35: /* Vector Multiply-Sum Unsigned Doubleword Modulo */
+ case 36: /* Vector Multiply-Sum Unsigned Byte Modulo */
+ case 37: /* Vector Multiply-Sum Mixed Byte Modulo */
+ case 38: /* Vector Multiply-Sum Unsigned Halfword Modulo */
+@@ -3795,14 +3799,37 @@
+ record_full_arch_list_add_reg (regcache,
+ tdep->ppc_vr0_regnum + PPC_VRT (insn));
+ return 0;
++
++ case 48: /* Multiply-Add High Doubleword */
++ case 49: /* Multiply-Add High Doubleword Unsigned */
++ case 51: /* Multiply-Add Low Doubleword */
++ record_full_arch_list_add_reg (regcache,
++ tdep->ppc_gp0_regnum + PPC_RT (insn));
++ return 0;
+ }
+
+ switch ((ext & 0x1ff))
+ {
++ case 385:
++ if (vra != 0 /* Decimal Convert To Signed Quadword */
++ && vra != 2 /* Decimal Convert From Signed Quadword */
++ && vra != 4 /* Decimal Convert To Zoned */
++ && vra != 5 /* Decimal Convert To National */
++ && vra != 6 /* Decimal Convert From Zoned */
++ && vra != 7 /* Decimal Convert From National */
++ && vra != 31) /* Decimal Set Sign */
++ break;
+ /* 5.16 Decimal Integer Arithmetic Instructions */
+ case 1: /* Decimal Add Modulo */
+ case 65: /* Decimal Subtract Modulo */
+
++ case 193: /* Decimal Shift */
++ case 129: /* Decimal Unsigned Shift */
++ case 449: /* Decimal Shift and Round */
++
++ case 257: /* Decimal Truncate */
++ case 321: /* Decimal Unsigned Truncate */
++
+ /* Bit-21 should be set. */
+ if (!PPC_BIT (insn, 21))
+ break;
+@@ -3832,6 +3859,12 @@
+ case 198: /* Vector Compare Equal To Single-Precision */
+ case 454: /* Vector Compare Greater Than or Equal To Single-Precision */
+ case 710: /* Vector Compare Greater Than Single-Precision */
++ case 7: /* Vector Compare Not Equal Byte */
++ case 71: /* Vector Compare Not Equal Halfword */
++ case 135: /* Vector Compare Not Equal Word */
++ case 263: /* Vector Compare Not Equal or Zero Byte */
++ case 327: /* Vector Compare Not Equal or Zero Halfword */
++ case 391: /* Vector Compare Not Equal or Zero Word */
+ if (PPC_Rc (insn))
+ record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
+ record_full_arch_list_add_reg (regcache,
+@@ -3839,6 +3872,38 @@
+ return 0;
+ }
+
++ if (ext == 1538)
++ {
++ switch (vra)
++ {
++ case 0: /* Vector Count Leading Zero Least-Significant Bits
++ Byte */
++ case 1: /* Vector Count Trailing Zero Least-Significant Bits
++ Byte */
++ record_full_arch_list_add_reg (regcache,
++ tdep->ppc_gp0_regnum + PPC_RT (insn));
++ return 0;
++
++ case 6: /* Vector Negate Word */
++ case 7: /* Vector Negate Doubleword */
++ case 8: /* Vector Parity Byte Word */
++ case 9: /* Vector Parity Byte Doubleword */
++ case 10: /* Vector Parity Byte Quadword */
++ case 16: /* Vector Extend Sign Byte To Word */
++ case 17: /* Vector Extend Sign Halfword To Word */
++ case 24: /* Vector Extend Sign Byte To Doubleword */
++ case 25: /* Vector Extend Sign Halfword To Doubleword */
++ case 26: /* Vector Extend Sign Word To Doubleword */
++ case 28: /* Vector Count Trailing Zeros Byte */
++ case 29: /* Vector Count Trailing Zeros Halfword */
++ case 30: /* Vector Count Trailing Zeros Word */
++ case 31: /* Vector Count Trailing Zeros Doubleword */
++ record_full_arch_list_add_reg (regcache,
++ tdep->ppc_vr0_regnum + PPC_VRT (insn));
++ return 0;
++ }
++ }
++
+ switch (ext)
+ {
+ case 142: /* Vector Pack Unsigned Halfword Unsigned Saturate */
+@@ -4010,10 +4075,44 @@
+ case 1923: /* Vector Population Count Word */
+ case 1987: /* Vector Population Count Doubleword */
+ case 1356: /* Vector Bit Permute Quadword */
++ case 1484: /* Vector Bit Permute Doubleword */
++ case 513: /* Vector Multiply-by-10 Unsigned Quadword */
++ case 1: /* Vector Multiply-by-10 & write Carry Unsigned
++ Quadword */
++ case 577: /* Vector Multiply-by-10 Extended Unsigned Quadword */
++ case 65: /* Vector Multiply-by-10 Extended & write Carry
++ Unsigned Quadword */
++ case 1027: /* Vector Absolute Difference Unsigned Byte */
++ case 1091: /* Vector Absolute Difference Unsigned Halfword */
++ case 1155: /* Vector Absolute Difference Unsigned Word */
++ case 1796: /* Vector Shift Right Variable */
++ case 1860: /* Vector Shift Left Variable */
++ case 133: /* Vector Rotate Left Word then Mask Insert */
++ case 197: /* Vector Rotate Left Doubleword then Mask Insert */
++ case 389: /* Vector Rotate Left Word then AND with Mask */
++ case 453: /* Vector Rotate Left Doubleword then AND with Mask */
++ case 525: /* Vector Extract Unsigned Byte */
++ case 589: /* Vector Extract Unsigned Halfword */
++ case 653: /* Vector Extract Unsigned Word */
++ case 717: /* Vector Extract Doubleword */
++ case 781: /* Vector Insert Byte */
++ case 845: /* Vector Insert Halfword */
++ case 909: /* Vector Insert Word */
++ case 973: /* Vector Insert Doubleword */
+ record_full_arch_list_add_reg (regcache,
+ tdep->ppc_vr0_regnum + PPC_VRT (insn));
+ return 0;
+
++ case 1549: /* Vector Extract Unsigned Byte Left-Indexed */
++ case 1613: /* Vector Extract Unsigned Halfword Left-Indexed */
++ case 1677: /* Vector Extract Unsigned Word Left-Indexed */
++ case 1805: /* Vector Extract Unsigned Byte Right-Indexed */
++ case 1869: /* Vector Extract Unsigned Halfword Right-Indexed */
++ case 1933: /* Vector Extract Unsigned Word Right-Indexed */
++ record_full_arch_list_add_reg (regcache,
++ tdep->ppc_gp0_regnum + PPC_RT (insn));
++ return 0;
++
+ case 1604: /* Move To Vector Status and Control Register */
+ record_full_arch_list_add_reg (regcache, PPC_VSCR_REGNUM);
+ return 0;
+@@ -4021,6 +4120,11 @@
+ record_full_arch_list_add_reg (regcache,
+ tdep->ppc_vr0_regnum + PPC_VRT (insn));
+ return 0;
++ case 833: /* Decimal Copy Sign */
++ record_full_arch_list_add_reg (regcache,
++ tdep->ppc_vr0_regnum + PPC_VRT (insn));
++ record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
++ return 0;
+ }
+
+ fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x "
+@@ -4038,6 +4142,14 @@
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ int ext = PPC_EXTOP (insn);
+
++ switch (ext & 0x01f)
++ {
++ case 2: /* Add PC Immediate Shifted */
++ record_full_arch_list_add_reg (regcache,
++ tdep->ppc_gp0_regnum + PPC_RT (insn));
++ return 0;
++ }
++
+ switch (ext)
+ {
+ case 0: /* Move Condition Register Field */
+@@ -4143,6 +4255,15 @@
+ return 0;
+ }
+
++ if ((ext & 0xff) == 170)
++ {
++ /* Add Extended using alternate carry bits */
++ record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum);
++ record_full_arch_list_add_reg (regcache,
++ tdep->ppc_gp0_regnum + PPC_RT (insn));
++ return 0;
++ }
++
+ switch (ext)
+ {
+ case 78: /* Determine Leftmost Zero Byte */
+@@ -4161,6 +4282,9 @@
+ case 302: /* Move From Branch History Rolling Buffer */
+ case 339: /* Move From Special Purpose Register */
+ case 371: /* Move From Time Base [Phased-Out] */
++ case 309: /* Load Doubleword Monitored Indexed */
++ case 128: /* Set Boolean */
++ case 755: /* Deliver A Random Number */
+ record_full_arch_list_add_reg (regcache,
+ tdep->ppc_gp0_regnum + PPC_RT (insn));
+ return 0;
+@@ -4177,6 +4301,7 @@
+ case 282: /* Convert Declets To Binary Coded Decimal */
+ case 314: /* Convert Binary Coded Decimal To Declets */
+ case 508: /* Compare bytes */
++ case 307: /* Move From VSR Lower Doubleword */
+ record_full_arch_list_add_reg (regcache,
+ tdep->ppc_gp0_regnum + PPC_RA (insn));
+ return 0;
+@@ -4195,6 +4320,12 @@
+ case 32: /* Compare logical */
+ case 144: /* Move To Condition Register Fields */
+ /* Move To One Condition Register Field */
++ case 192: /* Compare Ranged Byte */
++ case 224: /* Compare Equal Byte */
++ case 576: /* Move XER to CR Extended */
++ case 902: /* Paste (should always fail due to single-stepping and
++ the memory location might not be accessible, so
++ record only CR) */
+ record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
+ return 0;
+
+@@ -4221,6 +4352,12 @@
+ case 790: /* Load Halfword Byte-Reverse Indexed */
+ case 534: /* Load Word Byte-Reverse Indexed */
+ case 532: /* Load Doubleword Byte-Reverse Indexed */
++ case 582: /* Load Word Atomic */
++ case 614: /* Load Doubleword Atomic */
++ case 265: /* Modulo Unsigned Doubleword */
++ case 777: /* Modulo Signed Doubleword */
++ case 267: /* Modulo Unsigned Word */
++ case 779: /* Modulo Signed Word */
+ record_full_arch_list_add_reg (regcache,
+ tdep->ppc_gp0_regnum + PPC_RT (insn));
+ return 0;
+@@ -4299,6 +4436,16 @@
+ case 844: /* Load VSX Vector Doubleword*2 Indexed */
+ case 332: /* Load VSX Vector Doubleword & Splat Indexed */
+ case 780: /* Load VSX Vector Word*4 Indexed */
++ case 268: /* Load VSX Vector Indexed */
++ case 364: /* Load VSX Vector Word & Splat Indexed */
++ case 812: /* Load VSX Vector Halfword*8 Indexed */
++ case 876: /* Load VSX Vector Byte*16 Indexed */
++ case 269: /* Load VSX Vector with Length */
++ case 301: /* Load VSX Vector Left-justified with Length */
++ case 781: /* Load VSX Scalar as Integer Byte & Zero Indexed */
++ case 813: /* Load VSX Scalar as Integer Halfword & Zero Indexed */
++ case 403: /* Move To VSR Word & Splat */
++ case 435: /* Move To VSR Double Doubleword */
+ ppc_record_vsr (regcache, tdep, PPC_XT (insn));
+ return 0;
+
+@@ -4320,6 +4467,10 @@
+ case 922: /* Extend Sign Halfword */
+ case 954: /* Extend Sign Byte */
+ case 986: /* Extend Sign Word */
++ case 538: /* Count Trailing Zeros Word */
++ case 570: /* Count Trailing Zeros Doubleword */
++ case 890: /* Extend-Sign Word and Shift Left Immediate (445) */
++ case 890 | 1: /* Extend-Sign Word and Shift Left Immediate (445) */
+ if (PPC_RC (insn))
+ record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
+ record_full_arch_list_add_reg (regcache,
+@@ -4362,6 +4513,11 @@
+ case 727: /* Store Floating-Point Double Indexed */
+ case 919: /* Store Floating-Point Double Pair Indexed */
+ case 983: /* Store Floating-Point as Integer Word Indexed */
++ case 396: /* Store VSX Vector Indexed */
++ case 940: /* Store VSX Vector Halfword*8 Indexed */
++ case 1004: /* Store VSX Vector Byte*16 Indexed */
++ case 909: /* Store VSX Scalar as Integer Byte Indexed */
++ case 941: /* Store VSX Scalar as Integer Halfword Indexed */
+ if (ext == 694 || ext == 726 || ext == 150 || ext == 214 || ext == 182)
+ record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
+
+@@ -4391,6 +4547,7 @@
+ case 135: /* Store Vector Element Byte Indexed */
+ case 215: /* Store Byte Indexed */
+ case 694: /* Store Byte Conditional Indexed */
++ case 909: /* Store VSX Scalar as Integer Byte Indexed */
+ size = 1;
+ break;
+ case 439: /* Store Halfword with Update Indexed */
+@@ -4398,6 +4555,7 @@
+ case 407: /* Store Halfword Indexed */
+ case 726: /* Store Halfword Conditional Indexed */
+ case 918: /* Store Halfword Byte-Reverse Indexed */
++ case 941: /* Store VSX Scalar as Integer Halfword Indexed */
+ size = 2;
+ break;
+ case 181: /* Store Doubleword with Update Indexed */
+@@ -4415,6 +4573,9 @@
+ case 231: /* Store Vector Indexed */
+ case 487: /* Store Vector Indexed LRU */
+ case 919: /* Store Floating-Point Double Pair Indexed */
++ case 396: /* Store VSX Vector Indexed */
++ case 940: /* Store VSX Vector Halfword*8 Indexed */
++ case 1004: /* Store VSX Vector Byte*16 Indexed */
+ size = 16;
+ break;
+ default:
+@@ -4442,6 +4603,38 @@
+ return -1;
+ return 0;
+
++ case 397: /* Store VSX Vector with Length */
++ case 429: /* Store VSX Vector Left-justified with Length */
++ if (PPC_RA (insn) != 0)
++ regcache_raw_read_unsigned (regcache,
++ tdep->ppc_gp0_regnum + PPC_RA (insn), &ea);
++ regcache_raw_read_unsigned (regcache,
++ tdep->ppc_gp0_regnum + PPC_RB (insn), &rb);
++ /* Store up to 16 bytes. */
++ nb = (rb & 0xff) > 16 ? 16 : (rb & 0xff);
++ if (nb > 0)
++ record_full_arch_list_add_mem (ea, nb);
++ return 0;
++
++ case 710: /* Store Word Atomic */
++ case 742: /* Store Doubleword Atomic */
++ if (PPC_RA (insn) != 0)
++ regcache_raw_read_unsigned (regcache,
++ tdep->ppc_gp0_regnum + PPC_RA (insn), &ea);
++ switch (ext)
++ {
++ case 710: /* Store Word Atomic */
++ size = 8;
++ break;
++ case 742: /* Store Doubleword Atomic */
++ size = 16;
++ break;
++ default:
++ gdb_assert (0);
++ }
++ record_full_arch_list_add_mem (ea, size);
++ return 0;
++
+ case 725: /* Store String Word Immediate */
+ ra = 0;
+ if (PPC_RA (insn) != 0)
+@@ -4509,6 +4702,7 @@
+ case 430: /* Clear BHRB */
+ case 598: /* Synchronize */
+ case 62: /* Wait for Interrupt */
++ case 30: /* Wait */
+ case 22: /* Instruction Cache Block Touch */
+ case 854: /* Enforce In-order Execution of I/O */
+ case 246: /* Data Cache Block Touch for Store */
+@@ -4517,6 +4711,8 @@
+ case 278: /* Data Cache Block Touch */
+ case 758: /* Data Cache Block Allocate */
+ case 982: /* Instruction Cache Block Invalidate */
++ case 774: /* Copy */
++ case 838: /* CP_Abort */
+ return 0;
+
+ case 654: /* Transaction Begin */
+@@ -4617,6 +4813,7 @@
+ case 226: /* DFP Test Data Group */
+ case 642: /* DFP Compare Unordered */
+ case 674: /* DFP Test Significance */
++ case 675: /* DFP Test Significance Immediate */
+ record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
+ record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
+ return 0;
+@@ -4716,7 +4913,16 @@
+ case 217: /* ditto */
+ case 104: /* VSX Vector Subtract Double-Precision */
+ case 72: /* VSX Vector Subtract Single-Precision */
++ case 128: /* VSX Scalar Maximum Type-C Double-Precision */
++ case 136: /* VSX Scalar Minimum Type-C Double-Precision */
++ case 144: /* VSX Scalar Maximum Type-J Double-Precision */
++ case 152: /* VSX Scalar Minimum Type-J Double-Precision */
++ case 3: /* VSX Scalar Compare Equal Double-Precision */
++ case 11: /* VSX Scalar Compare Greater Than Double-Precision */
++ case 19: /* VSX Scalar Compare Greater Than or Equal
++ Double-Precision */
+ record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
++ /* FALL-THROUGH */
+ case 240: /* VSX Vector Copy Sign Double-Precision */
+ case 208: /* VSX Vector Copy Sign Single-Precision */
+ case 130: /* VSX Logical AND */
+@@ -4737,6 +4943,14 @@
+ case 2 | 0x20: /* VSX Shift Left Double by Word Immediate (SHW=1) */
+ case 2 | 0x40: /* VSX Shift Left Double by Word Immediate (SHW=2) */
+ case 2 | 0x60: /* VSX Shift Left Double by Word Immediate (SHW=3) */
++ case 216: /* VSX Vector Insert Exponent Single-Precision */
++ case 248: /* VSX Vector Insert Exponent Double-Precision */
++ case 26: /* VSX Vector Permute */
++ case 58: /* VSX Vector Permute Right-indexed */
++ case 213: /* VSX Vector Test Data Class Single-Precision (DC=0) */
++ case 213 | 0x8: /* VSX Vector Test Data Class Single-Precision (DC=1) */
++ case 245: /* VSX Vector Test Data Class Double-Precision (DC=0) */
++ case 245 | 0x8: /* VSX Vector Test Data Class Double-Precision (DC=1) */
+ ppc_record_vsr (regcache, tdep, PPC_XT (insn));
+ return 0;
+
+@@ -4748,6 +4962,7 @@
+
+ case 35: /* VSX Scalar Compare Unordered Double-Precision */
+ case 43: /* VSX Scalar Compare Ordered Double-Precision */
++ case 59: /* VSX Scalar Compare Exponents Double-Precision */
+ record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
+ record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
+ return 0;
+@@ -4894,6 +5109,7 @@
+ case 203: /* VSX Vector Square Root Double-Precision */
+ case 139: /* VSX Vector Square Root Single-Precision */
+ record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
++ /* FALL-THROUGH */
+ case 345: /* VSX Scalar Absolute Value Double-Precision */
+ case 267: /* VSX Scalar Convert Scalar Single-Precision to
+ Vector Single-Precision format Non-signalling */
+@@ -4908,9 +5124,15 @@
+ case 505: /* VSX Vector Negate Double-Precision */
+ case 441: /* VSX Vector Negate Single-Precision */
+ case 164: /* VSX Splat Word */
++ case 165: /* VSX Vector Extract Unsigned Word */
++ case 181: /* VSX Vector Insert Word */
+ ppc_record_vsr (regcache, tdep, PPC_XT (insn));
+ return 0;
+
++ case 298: /* VSX Scalar Test Data Class Single-Precision */
++ case 362: /* VSX Scalar Test Data Class Double-Precision */
++ record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
++ /* FALL-THROUGH */
+ case 106: /* VSX Scalar Test for software Square Root
+ Double-Precision */
+ case 234: /* VSX Vector Test for software Square Root
+@@ -4919,6 +5141,60 @@
+ Single-Precision */
+ record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
+ return 0;
++
++ case 347:
++ switch (PPC_FIELD (insn, 11, 5))
++ {
++ case 0: /* VSX Scalar Extract Exponent Double-Precision */
++ case 1: /* VSX Scalar Extract Significand Double-Precision */
++ record_full_arch_list_add_reg (regcache,
++ tdep->ppc_gp0_regnum + PPC_RT (insn));
++ return 0;
++ case 16: /* VSX Scalar Convert Half-Precision format to
++ Double-Precision format */
++ case 17: /* VSX Scalar round & Convert Double-Precision format
++ to Half-Precision format */
++ record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
++ ppc_record_vsr (regcache, tdep, PPC_XT (insn));
++ return 0;
++ }
++ break;
++
++ case 475:
++ switch (PPC_FIELD (insn, 11, 5))
++ {
++ case 24: /* VSX Vector Convert Half-Precision format to
++ Single-Precision format */
++ case 25: /* VSX Vector round and Convert Single-Precision format
++ to Half-Precision format */
++ record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
++ /* FALL-THROUGH */
++ case 0: /* VSX Vector Extract Exponent Double-Precision */
++ case 1: /* VSX Vector Extract Significand Double-Precision */
++ case 7: /* VSX Vector Byte-Reverse Halfword */
++ case 8: /* VSX Vector Extract Exponent Single-Precision */
++ case 9: /* VSX Vector Extract Significand Single-Precision */
++ case 15: /* VSX Vector Byte-Reverse Word */
++ case 23: /* VSX Vector Byte-Reverse Doubleword */
++ case 31: /* VSX Vector Byte-Reverse Quadword */
++ ppc_record_vsr (regcache, tdep, PPC_XT (insn));
++ return 0;
++ }
++ break;
++ }
++
++ switch (ext)
++ {
++ case 360: /* VSX Vector Splat Immediate Byte */
++ if (PPC_FIELD (insn, 11, 2) == 0)
++ {
++ ppc_record_vsr (regcache, tdep, PPC_XT (insn));
++ return 0;
++ }
++ break;
++ case 918: /* VSX Scalar Insert Exponent Double-Precision */
++ ppc_record_vsr (regcache, tdep, PPC_XT (insn));
++ return 0;
+ }
+
+ if (((ext >> 3) & 0x3) == 3) /* VSX Select */
+@@ -4932,6 +5208,65 @@
+ return -1;
+ }
+
++/* Parse and record instructions of primary opcode-61 at ADDR.
++ Return 0 if successful. */
++
++static int
++ppc_process_record_op61 (struct gdbarch *gdbarch, struct regcache *regcache,
++ CORE_ADDR addr, uint32_t insn)
++{
++ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++ ULONGEST ea = 0;
++ int size;
++
++ switch (insn & 0x3)
++ {
++ case 0: /* Store Floating-Point Double Pair */
++ case 2: /* Store VSX Scalar Doubleword */
++ case 3: /* Store VSX Scalar Single */
++ if (PPC_RA (insn) != 0)
++ regcache_raw_read_unsigned (regcache,
++ tdep->ppc_gp0_regnum + PPC_RA (insn),
++ &ea);
++ ea += PPC_DS (insn) << 2;
++ switch (insn & 0x3)
++ {
++ case 0: /* Store Floating-Point Double Pair */
++ size = 16;
++ break;
++ case 2: /* Store VSX Scalar Doubleword */
++ size = 8;
++ break;
++ case 3: /* Store VSX Scalar Single */
++ size = 4;
++ break;
++ default:
++ gdb_assert (0);
++ }
++ record_full_arch_list_add_mem (ea, size);
++ return 0;
++ }
++
++ switch (insn & 0x7)
++ {
++ case 1: /* Load VSX Vector */
++ ppc_record_vsr (regcache, tdep, PPC_XT (insn));
++ return 0;
++ case 5: /* Store VSX Vector */
++ if (PPC_RA (insn) != 0)
++ regcache_raw_read_unsigned (regcache,
++ tdep->ppc_gp0_regnum + PPC_RA (insn),
++ &ea);
++ ea += PPC_DQ (insn) << 4;
++ record_full_arch_list_add_mem (ea, 16);
++ return 0;
++ }
++
++ fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x "
++ "at %s.\n", insn, paddress (gdbarch, addr));
++ return -1;
++}
++
+ /* Parse and record instructions of primary opcode-63 at ADDR.
+ Return 0 if successful. */
+
+@@ -4970,6 +5305,16 @@
+ record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
+ }
+
++ switch (ext & 0xff)
++ {
++ case 5: /* VSX Scalar Round to Quad-Precision Integer */
++ case 37: /* VSX Scalar Round Quad-Precision to Double-Extended
++ Precision */
++ record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
++ ppc_record_vsr (regcache, tdep, PPC_VRT (insn) + 32);
++ return 0;
++ }
++
+ switch (ext)
+ {
+ case 2: /* DFP Add Quad */
+@@ -4999,6 +5344,7 @@
+ case 226: /* DFP Test Data Group Quad */
+ case 642: /* DFP Compare Unordered Quad */
+ case 674: /* DFP Test Significance Quad */
++ case 675: /* DFP Test Significance Immediate Quad */
+ record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
+ record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
+ return 0;
+@@ -5055,7 +5401,26 @@
+ record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
+ return 0;
+
+- case 583: /* Move From FPSCR */
++ case 583:
++ switch (PPC_FIELD (insn, 11, 5))
++ {
++ case 1: /* Move From FPSCR & Clear Enables */
++ case 20: /* Move From FPSCR Control & set DRN */
++ case 21: /* Move From FPSCR Control & set DRN Immediate */
++ case 22: /* Move From FPSCR Control & set RN */
++ case 23: /* Move From FPSCR Control & set RN Immediate */
++ record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
++ case 0: /* Move From FPSCR */
++ case 24: /* Move From FPSCR Lightweight */
++ if (PPC_FIELD (insn, 11, 5) == 0 && PPC_RC (insn))
++ record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
++ record_full_arch_list_add_reg (regcache,
++ tdep->ppc_fp0_regnum
++ + PPC_FRT (insn));
++ return 0;
++ }
++ break;
++
+ case 8: /* Floating Copy Sign */
+ case 40: /* Floating Negate */
+ case 72: /* Floating Move Register */
+@@ -5085,6 +5450,10 @@
+ case 0: /* Floating Compare Unordered */
+ case 32: /* Floating Compare Ordered */
+ case 64: /* Move to Condition Register from FPSCR */
++ case 132: /* VSX Scalar Compare Ordered Quad-Precision */
++ case 164: /* VSX Scalar Compare Exponents Quad-Precision */
++ case 644: /* VSX Scalar Compare Unordered Quad-Precision */
++ case 708: /* VSX Scalar Test Data Class Quad-Precision */
+ record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
+ /* FALL-THROUGH */
+ case 128: /* Floating Test for software Divide */
+@@ -5092,10 +5461,65 @@
+ record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
+ return 0;
+
++ case 4: /* VSX Scalar Add Quad-Precision */
++ case 36: /* VSX Scalar Multiply Quad-Precision */
++ case 388: /* VSX Scalar Multiply-Add Quad-Precision */
++ case 420: /* VSX Scalar Multiply-Subtract Quad-Precision */
++ case 452: /* VSX Scalar Negative Multiply-Add Quad-Precision */
++ case 484: /* VSX Scalar Negative Multiply-Subtract
++ Quad-Precision */
++ case 516: /* VSX Scalar Subtract Quad-Precision */
++ case 548: /* VSX Scalar Divide Quad-Precision */
++ record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
++ /* FALL-THROUGH */
++ case 100: /* VSX Scalar Copy Sign Quad-Precision */
++ case 868: /* VSX Scalar Insert Exponent Quad-Precision */
++ ppc_record_vsr (regcache, tdep, PPC_VRT (insn) + 32);
++ return 0;
++
++ case 804:
++ switch (PPC_FIELD (insn, 11, 5))
++ {
++ case 27: /* VSX Scalar Square Root Quad-Precision */
++ record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
++ /* FALL-THROUGH */
++ case 0: /* VSX Scalar Absolute Quad-Precision */
++ case 2: /* VSX Scalar Extract Exponent Quad-Precision */
++ case 8: /* VSX Scalar Negative Absolute Quad-Precision */
++ case 16: /* VSX Scalar Negate Quad-Precision */
++ case 18: /* VSX Scalar Extract Significand Quad-Precision */
++ ppc_record_vsr (regcache, tdep, PPC_VRT (insn) + 32);
++ return 0;
++ }
++ break;
++
++ case 836:
++ switch (PPC_FIELD (insn, 11, 5))
++ {
++ case 1: /* VSX Scalar truncate & Convert Quad-Precision format
++ to Unsigned Word format */
++ case 2: /* VSX Scalar Convert Unsigned Doubleword format to
++ Quad-Precision format */
++ case 9: /* VSX Scalar truncate & Convert Quad-Precision format
++ to Signed Word format */
++ case 10: /* VSX Scalar Convert Signed Doubleword format to
++ Quad-Precision format */
++ case 17: /* VSX Scalar truncate & Convert Quad-Precision format
++ to Unsigned Doubleword format */
++ case 20: /* VSX Scalar round & Convert Quad-Precision format to
++ Double-Precision format */
++ case 22: /* VSX Scalar Convert Double-Precision format to
++ Quad-Precision format */
++ case 25: /* VSX Scalar truncate & Convert Quad-Precision format
++ to Signed Doubleword format */
++ record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
++ ppc_record_vsr (regcache, tdep, PPC_VRT (insn) + 32);
++ return 0;
++ }
+ }
+
+ fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x "
+- "at %s, 59-%d.\n", insn, paddress (gdbarch, addr), ext);
++ "at %s, 63-%d.\n", insn, paddress (gdbarch, addr), ext);
+ return -1;
+ }
+
+@@ -5308,12 +5732,21 @@
+ }
+ break;
+
+- case 57: /* Load Floating-Point Double Pair */
+- if (PPC_FIELD (insn, 30, 2) != 0)
+- goto UNKNOWN_OP;
+- tmp = tdep->ppc_fp0_regnum + (PPC_RT (insn) & ~1);
+- record_full_arch_list_add_reg (regcache, tmp);
+- record_full_arch_list_add_reg (regcache, tmp + 1);
++ case 57:
++ switch (insn & 0x3)
++ {
++ case 0: /* Load Floating-Point Double Pair */
++ tmp = tdep->ppc_fp0_regnum + (PPC_RT (insn) & ~1);
++ record_full_arch_list_add_reg (regcache, tmp);
++ record_full_arch_list_add_reg (regcache, tmp + 1);
++ break;
++ case 2: /* Load VSX Scalar Doubleword */
++ case 3: /* Load VSX Scalar Single */
++ ppc_record_vsr (regcache, tdep, PPC_VRT (insn) + 32);
++ break;
++ default:
++ goto UNKNOWN_OP;
++ }
+ break;
+
+ case 58: /* Load Doubleword */
+@@ -5339,7 +5772,11 @@
+ return -1;
+ break;
+
+- case 61: /* Store Floating-Point Double Pair */
++ case 61:
++ if (ppc_process_record_op61 (gdbarch, regcache, addr, insn) != 0)
++ return -1;
++ break;
++
+ case 62: /* Store Doubleword */
+ /* Store Doubleword with Update */
+ /* Store Quadword with Update */
+@@ -5348,7 +5785,7 @@
+ int size;
+ int sub2 = PPC_FIELD (insn, 30, 2);
+
+- if ((op6 == 61 && sub2 != 0) || (op6 == 62 && sub2 > 2))
++ if (sub2 > 2)
+ goto UNKNOWN_OP;
+
+ if (PPC_RA (insn) != 0)
+@@ -5356,7 +5793,7 @@
+ tdep->ppc_gp0_regnum + PPC_RA (insn),
+ &addr);
+
+- size = ((op6 == 61) || sub2 == 2) ? 16 : 8;
++ size = (sub2 == 2) ? 16 : 8;
+
+ addr += PPC_DS (insn) << 2;
+ if (record_full_arch_list_add_mem (addr, size) != 0)
diff --git a/SOURCES/gdb-rhbz1320945-power9-35of38.patch b/SOURCES/gdb-rhbz1320945-power9-35of38.patch
new file mode 100644
index 0000000..2850bd6
--- /dev/null
+++ b/SOURCES/gdb-rhbz1320945-power9-35of38.patch
@@ -0,0 +1,63 @@
+commit de6784544abc97d5e396cb1e83eda1ae09f63d40
+Author: Edjunior Barbosa Machado <emachado@linux.vnet.ibm.com>
+Date: Thu Sep 22 11:33:56 2016 -0300
+
+ Fix build breakage from commit 6ec2b2
+
+ I was notified by buildbot that my patch (commit 6ec2b2) has broken the build
+ on x86_64:
+
+ ../../binutils-gdb/gdb/rs6000-tdep.c: In function int ppc_process_record_op31(gdbarch*, regcache*, CORE_ADDR, uint32_t):
+ ../../binutils-gdb/gdb/rs6000-tdep.c:4705:50: error: cannot convert CORE_ADDR* {aka long unsigned int*} to ULONGEST* {aka long long unsigned int*} for argument 3 to register_status regcache_raw_read_unsigned(regcache*, int, ULONGEST*)
+ tdep->ppc_gp0_regnum + PPC_RA (insn), &ea);
+ ^
+ ../../binutils-gdb/gdb/rs6000-tdep.c:4718:50: error: cannot convert CORE_ADDR* {aka long unsigned int*} to ULONGEST* {aka long long unsigned int*} for argument 3 to register_status regcache_raw_read_unsigned(regcache*, int, ULONGEST*)
+ tdep->ppc_gp0_regnum + PPC_RA (insn), &ea);
+ ^
+ The patch below should fix it.
+
+ gdb/ChangeLog:
+ 2016-09-22 Edjunior Barbosa Machado <emachado@linux.vnet.ibm.com>
+
+ * rs6000-tdep.c (ppc_process_record_op31): Fix
+ regcache_raw_read_unsigned call using the correct parameter type.
+
+### a/gdb/ChangeLog
+### b/gdb/ChangeLog
+## -1,3 +1,8 @@
++2016-09-22 Edjunior Barbosa Machado <emachado@linux.vnet.ibm.com>
++
++ * rs6000-tdep.c (ppc_process_record_op31): Fix
++ regcache_raw_read_unsigned call using the correct parameter type.
++
+ 2016-09-22 Anton Kolesov <anton.kolesov@synopsys.com>
+
+ * arc-tdep.c: Fix ARI warning for printf(%p).
+--- a/gdb/rs6000-tdep.c
++++ b/gdb/rs6000-tdep.c
+@@ -4700,9 +4700,11 @@ ppc_process_record_op31 (struct gdbarch *gdbarch, struct regcache *regcache,
+
+ case 397: /* Store VSX Vector with Length */
+ case 429: /* Store VSX Vector Left-justified with Length */
++ ra = 0;
+ if (PPC_RA (insn) != 0)
+ regcache_raw_read_unsigned (regcache,
+- tdep->ppc_gp0_regnum + PPC_RA (insn), &ea);
++ tdep->ppc_gp0_regnum + PPC_RA (insn), &ra);
++ ea = ra;
+ regcache_raw_read_unsigned (regcache,
+ tdep->ppc_gp0_regnum + PPC_RB (insn), &rb);
+ /* Store up to 16 bytes. */
+@@ -4713,9 +4715,11 @@ ppc_process_record_op31 (struct gdbarch *gdbarch, struct regcache *regcache,
+
+ case 710: /* Store Word Atomic */
+ case 742: /* Store Doubleword Atomic */
++ ra = 0;
+ if (PPC_RA (insn) != 0)
+ regcache_raw_read_unsigned (regcache,
+- tdep->ppc_gp0_regnum + PPC_RA (insn), &ea);
++ tdep->ppc_gp0_regnum + PPC_RA (insn), &ra);
++ ea = ra;
+ switch (ext)
+ {
+ case 710: /* Store Word Atomic */
diff --git a/SOURCES/gdb-rhbz1320945-power9-36of38.patch b/SOURCES/gdb-rhbz1320945-power9-36of38.patch
new file mode 100644
index 0000000..ab7603c
--- /dev/null
+++ b/SOURCES/gdb-rhbz1320945-power9-36of38.patch
@@ -0,0 +1,265 @@
+commit a5721ba270ddf860e0e5a45bba456214e8eac2be
+Author: Alan Modra <amodra@gmail.com>
+Date: Thu Sep 29 15:12:47 2016 +0930
+
+ Disallow 3-operand cmp[l][i] for ppc64
+
+ cmp[l][o] get an optional L field only when generating 32-bit code.
+ dcbf, tlbie and tlbiel keep their optional L field, ditto for R field
+ of tbegin. cmprb, tsr., wlcr[all] and mtsle all change to a
+ compulsory L field.
+
+ L field of dcbf and wclr is 2 bits.
+
+ PR 20641
+ include/
+ * opcode/ppc.h (PPC_OPERAND_OPTIONAL32): Define.
+ opcodes/
+ * ppc-opc.c (L): Make compulsory.
+ (LOPT): New, optional form of L.
+ (HTM_R): Define as LOPT.
+ (L0, L1): Delete.
+ (L32OPT): New, optional for 32-bit L.
+ (L2OPT): New, 2-bit L for dcbf.
+ (SVC_LEC): Update.
+ (L2): Define.
+ (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
+ (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
+ <dcbf>: Use L2OPT.
+ <tlbiel, tlbie>: Use LOPT.
+ <wclr, wclrall>: Use L2.
+ gas/
+ * config/tc-ppc.c (md_assemble): Handle PPC_OPERAND_OPTIONAL32.
+ * testsuite/gas/ppc/power8.s: Provide tbegin. operand.
+ * testsuite/gas/ppc/power9.d: Update cmprb disassembly.
+
+### a/include/ChangeLog
+### b/include/ChangeLog
+## -1,3 +1,7 @@
++2016-09-29 Alan Modra <amodra@gmail.com>
++
++ * opcode/ppc.h (PPC_OPERAND_OPTIONAL32): Define.
++
+ 2016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * opcode/arc.h (insn_class_t): Add two new classes.
+--- a/include/opcode/ppc.h
++++ b/include/opcode/ppc.h
+@@ -407,6 +407,10 @@ extern const unsigned int num_powerpc_operands;
+ is omitted, then the value it should use for the operand is stored
+ in the SHIFT field of the immediatly following operand field. */
+ #define PPC_OPERAND_OPTIONAL_VALUE (0x400000)
++
++/* This flag is only used with PPC_OPERAND_OPTIONAL. The operand is
++ only optional when generating 32-bit code. */
++#define PPC_OPERAND_OPTIONAL32 (0x800000)
+
+ /* The POWER and PowerPC assemblers use a few macros. We keep them
+ with the operands table for simplicity. The macro table is an
+### a/opcodes/ChangeLog
+### b/opcodes/ChangeLog
+## -1,3 +1,19 @@
++2016-09-29 Alan Modra <amodra@gmail.com>
++
++ * ppc-opc.c (L): Make compulsory.
++ (LOPT): New, optional form of L.
++ (HTM_R): Define as LOPT.
++ (L0, L1): Delete.
++ (L32OPT): New, optional for 32-bit L.
++ (L2OPT): New, 2-bit L for dcbf.
++ (SVC_LEC): Update.
++ (L2): Define.
++ (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
++ (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
++ <dcbf>: Use L2OPT.
++ <tlbiel, tlbie>: Use LOPT.
++ <wclr, wclrall>: Use L2.
++
+ 2016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
+
+ * Makefile.in: Regenerate.
+--- a/opcodes/ppc-opc.c
++++ b/opcodes/ppc-opc.c
+@@ -62,10 +62,6 @@ static unsigned long insert_dxdn (unsigned long, long, ppc_cpu_t, const char **)
+ static long extract_dxdn (unsigned long, ppc_cpu_t, int *);
+ static unsigned long insert_fxm (unsigned long, long, ppc_cpu_t, const char **);
+ static long extract_fxm (unsigned long, ppc_cpu_t, int *);
+-static unsigned long insert_l0 (unsigned long, long, ppc_cpu_t, const char **);
+-static long extract_l0 (unsigned long, ppc_cpu_t, int *);
+-static unsigned long insert_l1 (unsigned long, long, ppc_cpu_t, const char **);
+-static long extract_l1 (unsigned long, ppc_cpu_t, int *);
+ static unsigned long insert_li20 (unsigned long, long, ppc_cpu_t, const char **);
+ static long extract_li20 (unsigned long, ppc_cpu_t, int *);
+ static unsigned long insert_ls (unsigned long, long, ppc_cpu_t, const char **);
+@@ -429,20 +425,24 @@ const struct powerpc_operand powerpc_operands[] =
+
+ /* The L field in a D or X form instruction. */
+ #define L IMM20 + 1
++ { 0x1, 21, NULL, NULL, 0 },
++
++ /* The optional L field in tlbie and tlbiel instructions. */
++#define LOPT L + 1
+ /* The R field in a HTM X form instruction. */
+-#define HTM_R L
++#define HTM_R LOPT
+ { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
+
+- /* The L field in an X form instruction which must be zero. */
+-#define L0 L + 1
+- { 0x1, 21, insert_l0, extract_l0, PPC_OPERAND_OPTIONAL },
++ /* The optional (for 32-bit) L field in cmp[l][i] instructions. */
++#define L32OPT LOPT + 1
++ { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL32 },
+
+- /* The L field in an X form instruction which must be one. */
+-#define L1 L0 + 1
+- { 0x1, 21, insert_l1, extract_l1, 0 },
++ /* The L field in dcbf instruction. */
++#define L2OPT L32OPT + 1
++ { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
+
+ /* The LEV field in a POWER SVC form instruction. */
+-#define SVC_LEV L1 + 1
++#define SVC_LEV L2OPT + 1
+ { 0x7f, 5, NULL, NULL, 0 },
+
+ /* The LEV field in an SC form instruction. */
+@@ -688,6 +688,8 @@ const struct powerpc_operand powerpc_operands[] =
+ #define STRM SR + 1
+ /* The T field in a tlbilx form instruction. */
+ #define T STRM
++ /* The L field in wclr instructions. */
++#define L2 STRM
+ { 0x3, 21, NULL, NULL, 0 },
+
+ /* The ESYNC field in an X (sync) form instruction. */
+@@ -1483,58 +1485,6 @@ extract_fxm (unsigned long insn,
+ return mask;
+ }
+
+-/* The L field in an X form instruction which must have the value zero. */
+-
+-static unsigned long
+-insert_l0 (unsigned long insn,
+- long value,
+- ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+- const char **errmsg)
+-{
+- if (value != 0)
+- *errmsg = _("invalid operand constant");
+- return insn & ~(0x1 << 21);
+-}
+-
+-static long
+-extract_l0 (unsigned long insn,
+- ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+- int *invalid)
+-{
+- long value;
+-
+- value = (insn >> 21) & 0x1;
+- if (value != 0)
+- *invalid = 1;
+- return value;
+-}
+-
+-/* The L field in an X form instruction which must have the value one. */
+-
+-static unsigned long
+-insert_l1 (unsigned long insn,
+- long value,
+- ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+- const char **errmsg)
+-{
+- if (value != 1)
+- *errmsg = _("invalid operand constant");
+- return insn | (0x1 << 21);
+-}
+-
+-static long
+-extract_l1 (unsigned long insn,
+- ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+- int *invalid)
+-{
+- long value;
+-
+- value = (insn >> 21) & 0x1;
+- if (value != 1)
+- *invalid = 1;
+- return value;
+-}
+-
+ static unsigned long
+ insert_li20 (unsigned long insn,
+ long value,
+@@ -3890,12 +3840,12 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+
+ {"cmplwi", OPL(10,0), OPL_MASK, PPCCOM, PPCVLE, {OBF, RA, UISIGNOPT}},
+ {"cmpldi", OPL(10,1), OPL_MASK, PPC64, PPCVLE, {OBF, RA, UISIGNOPT}},
+-{"cmpli", OP(10), OP_MASK, PPC, PPCVLE, {BF, L, RA, UISIGNOPT}},
++{"cmpli", OP(10), OP_MASK, PPC, PPCVLE, {BF, L32OPT, RA, UISIGNOPT}},
+ {"cmpli", OP(10), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, UISIGNOPT}},
+
+ {"cmpwi", OPL(11,0), OPL_MASK, PPCCOM, PPCVLE, {OBF, RA, SI}},
+ {"cmpdi", OPL(11,1), OPL_MASK, PPC64, PPCVLE, {OBF, RA, SI}},
+-{"cmpi", OP(11), OP_MASK, PPC, PPCVLE, {BF, L, RA, SI}},
++{"cmpi", OP(11), OP_MASK, PPC, PPCVLE, {BF, L32OPT, RA, SI}},
+ {"cmpi", OP(11), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, SI}},
+
+ {"addic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
+@@ -4713,7 +4663,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+
+ {"cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}},
+ {"cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}},
+-{"cmp", X(31,0), XCMP_MASK, PPC, 0, {BF, L, RA, RB}},
++{"cmp", X(31,0), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}},
+ {"cmp", X(31,0), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
+
+ {"twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, 0, {RA, RB}},
+@@ -4821,7 +4771,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+
+ {"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}},
+ {"cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}},
+-{"cmpl", X(31,32), XCMP_MASK, PPC, 0, {BF, L, RA, RB}},
++{"cmpl", X(31,32), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}},
+ {"cmpl", X(31,32), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
+
+ {"lvsr", X(31,38), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
+@@ -4907,7 +4857,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"ldarx", X(31,84), XEH_MASK, PPC64, 0, {RT, RA0, RB, EH}},
+
+ {"dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, PPC476, {RA0, RB}},
+-{"dcbf", X(31,86), XLRT_MASK, PPC, 0, {RA0, RB, L}},
++{"dcbf", X(31,86), XLRT_MASK, PPC, 0, {RA0, RB, L2OPT}},
+
+ {"lbzx", X(31,87), X_MASK, COM, 0, {RT, RA0, RB}},
+
+@@ -5149,7 +5099,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"ehpriv", X(31,270), 0xffffffff, E500MC|PPCA2, 0, {0}},
+
+ {"tlbiel", X(31,274), X_MASK|1<<20,POWER9, PPC476, {RB, RSO, RIC, PRS, X_R}},
+-{"tlbiel", X(31,274), XRTLRA_MASK, POWER4, POWER9|PPC476, {RB, L}},
++{"tlbiel", X(31,274), XRTLRA_MASK, POWER4, POWER9|PPC476, {RB, LOPT}},
+
+ {"mfapidi", X(31,275), X_MASK, BOOKE, E500|TITAN, {RT, RA}},
+
+@@ -5183,7 +5133,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+
+ {"tlbie", X(31,306), X_MASK|1<<20,POWER9, TITAN, {RB, RS, RIC, PRS, X_R}},
+ {"tlbie", X(31,306), XRA_MASK, POWER7, POWER9|TITAN, {RB, RS}},
+-{"tlbie", X(31,306), XRTLRA_MASK, PPC, E500|POWER7|TITAN, {RB, L}},
++{"tlbie", X(31,306), XRTLRA_MASK, PPC, E500|POWER7|TITAN, {RB, LOPT}},
+ {"tlbi", X(31,306), XRT_MASK, POWER, 0, {RA0, RB}},
+
+ {"mfvsrld", X(31,307), XX1RB_MASK, PPCVSX3, 0, {RA, XS6}},
+@@ -6234,8 +6184,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"stvfrxl", X(31,933), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
+
+ {"wclrone", XOPL2(31,934,2),XRT_MASK, PPCA2, 0, {RA0, RB}},
+-{"wclrall", X(31,934), XRARB_MASK, PPCA2, 0, {L}},
+-{"wclr", X(31,934), X_MASK, PPCA2, 0, {L, RA0, RB}},
++{"wclrall", X(31,934), XRARB_MASK, PPCA2, 0, {L2}},
++{"wclr", X(31,934), X_MASK, PPCA2, 0, {L2, RA0, RB}},
+
+ {"stvrxl", X(31,935), X_MASK, CELL, 0, {VS, RA0, RB}},
+
diff --git a/SOURCES/gdb-rhbz1320945-power9-37of38.patch b/SOURCES/gdb-rhbz1320945-power9-37of38.patch
new file mode 100644
index 0000000..f8797d2
--- /dev/null
+++ b/SOURCES/gdb-rhbz1320945-power9-37of38.patch
@@ -0,0 +1,49 @@
+commit dce75bf9848c88583377c608e9734a2f8616d12b
+Author: Nicholas Piggin <npiggin@gmail.com>
+Date: Fri Feb 10 14:18:23 2017 +1000
+
+ POWER9 add scv/rfscv instruction support
+
+ opcodes/
+ * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
+
+ gas/
+ * testsuite/gas/ppc/power9.d <scv, rfscv>: New tests.
+
+### a/opcodes/ChangeLog
+### b/opcodes/ChangeLog
+## -1,3 +1,7 @@
++2017-02-10 Nicholas Piggin <npiggin@gmail.com>
++
++ * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
++
+ 2017-02-03 Nick Clifton <nickc@redhat.com>
+
+ PR 21096
+--- a/opcodes/ppc-opc.c
++++ b/opcodes/ppc-opc.c
+@@ -441,7 +441,7 @@ const struct powerpc_operand powerpc_operands[] =
+ #define L2OPT L32OPT + 1
+ { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
+
+- /* The LEV field in a POWER SVC form instruction. */
++ /* The LEV field in a POWER SVC / POWER9 SCV form instruction. */
+ #define SVC_LEV L2OPT + 1
+ { 0x7f, 5, NULL, NULL, 0 },
+
+@@ -4142,6 +4142,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"bcla", B(16,1,1), B_MASK, COM, PPCVLE, {BO, BI, BDA}},
+
+ {"svc", SC(17,0,0), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}},
++{"scv", SC(17,0,1), SC_MASK, POWER9, PPCVLE, {SVC_LEV}},
+ {"svcl", SC(17,0,1), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}},
+ {"sc", SC(17,1,0), SC_MASK, PPC, PPCVLE, {LEV}},
+ {"svca", SC(17,1,0), SC_MASK, PWRCOM, PPCVLE, {SV}},
+@@ -4391,6 +4392,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"rfi", XL(19,50), 0xffffffff, COM, PPCVLE, {0}},
+ {"rfci", XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300|PPCA2|PPC476, PPCVLE, {0}},
+
++{"rfscv", XL(19,82), 0xffffffff, POWER9, PPCVLE, {0}},
+ {"rfsvc", XL(19,82), 0xffffffff, POWER, PPCVLE, {0}},
+
+ {"rfgi", XL(19,102), 0xffffffff, E500MC|PPCA2, PPCVLE, {0}},
diff --git a/SOURCES/gdb-rhbz1320945-power9-38of38.patch b/SOURCES/gdb-rhbz1320945-power9-38of38.patch
new file mode 100644
index 0000000..51bafd1
--- /dev/null
+++ b/SOURCES/gdb-rhbz1320945-power9-38of38.patch
@@ -0,0 +1,42 @@
+commit 1437d0631b209500db8371c425e896deb66ec9f9
+Author: Peter Bergner <bergner@vnet.ibm.com>
+Date: Wed Mar 8 14:00:42 2017 -0600
+
+ Add support for the new 'lnia' extended mnemonic.
+
+ opcodes/
+ * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
+
+ gas/
+ * testsuite/gas/ppc/power9.d <lnia> New test.
+ * testsuite/gas/ppc/power9.s: Likewise.
+
+### a/opcodes/ChangeLog
+### b/opcodes/ChangeLog
+## -1,3 +1,7 @@
++2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
++
++ * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
++
+ 2017-03-06 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (REG_0F1E_MOD_3): New enum.
+--- a/opcodes/ppc-opc.c
++++ b/opcodes/ppc-opc.c
+@@ -2552,6 +2552,8 @@ extract_vleil (unsigned long insn,
+ /* An DX form instruction. */
+ #define DX(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
+ #define DX_MASK DX (0x3f, 0x1f)
++/* An DX form instruction with the D bits specified. */
++#define NODX_MASK (DX_MASK | 0x1fffc1)
+
+ /* An EVSEL form instruction. */
+ #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
+@@ -4264,6 +4266,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+
+ {"mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, PPCVLE, {BF, BFA}},
+
++{"lnia", DX(19,2), NODX_MASK, POWER9, PPCVLE, {RT}},
+ {"addpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, DXD}},
+ {"subpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, NDXD}},
+
diff --git a/SOURCES/gdb-rhbz1320945-power9pre-1of3.patch b/SOURCES/gdb-rhbz1320945-power9pre-1of3.patch
new file mode 100644
index 0000000..ae3a306
--- /dev/null
+++ b/SOURCES/gdb-rhbz1320945-power9pre-1of3.patch
@@ -0,0 +1,52 @@
+commit 58ae08f29af8b8261fddecc9618fd8ea1ebe1532
+Author: Alan Modra <amodra@gmail.com>
+Date: Thu Jul 4 01:42:08 2013 +0000
+
+ * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
+
+### a/opcodes/ChangeLog
+### b/opcodes/ChangeLog
+## -1,3 +1,7 @@
++2013-07-04 Alan Modra <amodra@gmail.com>
++
++ * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
++
+ 2013-06-26 Nick Clifton <nickc@redhat.com>
+
+ * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
+--- a/opcodes/ppc-opc.c
++++ b/opcodes/ppc-opc.c
+@@ -2792,6 +2792,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
+ {"tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
+ {"tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
++{"tdui", OPTO(2,TOU), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
+ {"tdi", OP(2), OP_MASK, PPC64, PPCNONE, {TO, RA, SI}},
+
+ {"twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
+@@ -2822,6 +2823,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
+ {"twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
+ {"tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
++{"twui", OPTO(3,TOU), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
++{"tui", OPTO(3,TOU), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
+ {"twi", OP(3), OP_MASK, PPCCOM, PPCNONE, {TO, RA, SI}},
+ {"ti", OP(3), OP_MASK, PWRCOM, PPCNONE, {TO, RA, SI}},
+
+@@ -4350,6 +4353,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"twne", XTO(31,4,TONE), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}},
+ {"tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
+ {"trap", XTO(31,4,TOU), 0xffffffff, PPCCOM|PPCVLE, PPCNONE, {0}},
++{"twu", XTO(31,4,TOU), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}},
++{"tu", XTO(31,4,TOU), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
+ {"tw", X(31,4), X_MASK, PPCCOM|PPCVLE, PPCNONE, {TO, RA, RB}},
+ {"t", X(31,4), X_MASK, PWRCOM, PPCNONE, {TO, RA, RB}},
+
+@@ -4490,6 +4495,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
+ {"tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
+ {"tdng", XTO(31,68,TONG), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
+ {"tdne", XTO(31,68,TONE), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
++{"tdu", XTO(31,68,TOU), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
+ {"td", X(31,68), X_MASK, PPC64|PPCVLE, PPCNONE, {TO, RA, RB}},
+
+ {"lwfcmx", APU(31,71,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
diff --git a/SOURCES/gdb-rhbz1320945-power9pre-2of3.patch b/SOURCES/gdb-rhbz1320945-power9pre-2of3.patch
new file mode 100644
index 0000000..4512f0c
--- /dev/null
+++ b/SOURCES/gdb-rhbz1320945-power9pre-2of3.patch
@@ -0,0 +1,87 @@
+commit 4f6ffcd38d90eef0e0afc2fd32d7086c706b9bb0
+Author: Peter Bergner <bergner@vnet.ibm.com>
+Date: Tue Jul 30 02:26:09 2013 +0000
+
+ opcodes/
+ * ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect.
+
+### a/opcodes/ChangeLog
+### b/opcodes/ChangeLog
+## -1,3 +1,7 @@
++2013-07-29 Peter Bergner <bergner@vnet.ibm.com>
++
++ * ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect.
++
+ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
+ Alexander Ivchenko <alexander.ivchenko@intel.com>
+ Maxim Kuznetsov <maxim.kuznetsov@intel.com>
+--- a/opcodes/ppc-dis.c
++++ b/opcodes/ppc-dis.c
+@@ -263,56 +263,39 @@ powerpc_init_dialect (struct disassemble_info *info)
+ {
+ case bfd_mach_ppc_403:
+ case bfd_mach_ppc_403gc:
+- dialect = (PPC_OPCODE_PPC | PPC_OPCODE_403);
++ dialect = ppc_parse_cpu (dialect, &sticky, "403");
+ break;
+ case bfd_mach_ppc_405:
+- dialect = (PPC_OPCODE_PPC | PPC_OPCODE_403 | PPC_OPCODE_405);
++ dialect = ppc_parse_cpu (dialect, &sticky, "405");
+ break;
+ case bfd_mach_ppc_601:
+- dialect = (PPC_OPCODE_PPC | PPC_OPCODE_601);
++ dialect = ppc_parse_cpu (dialect, &sticky, "601");
+ break;
+ case bfd_mach_ppc_a35:
+ case bfd_mach_ppc_rs64ii:
+ case bfd_mach_ppc_rs64iii:
+- dialect = (PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_64);
++ dialect = ppc_parse_cpu (dialect, &sticky, "pwr2") | PPC_OPCODE_64;
+ break;
+ case bfd_mach_ppc_e500:
+- dialect = (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
+- | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
+- | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
+- | PPC_OPCODE_E500);
++ dialect = ppc_parse_cpu (dialect, &sticky, "e500");
+ break;
+ case bfd_mach_ppc_e500mc:
+- dialect = (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
+- | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
+- | PPC_OPCODE_E500MC);
++ dialect = ppc_parse_cpu (dialect, &sticky, "e500mc");
+ break;
+ case bfd_mach_ppc_e500mc64:
+- dialect = (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
+- | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
+- | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER5
+- | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7);
++ dialect = ppc_parse_cpu (dialect, &sticky, "e500mc64");
+ break;
+ case bfd_mach_ppc_e5500:
+- dialect = (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
+- | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
+- | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
+- | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
+- | PPC_OPCODE_POWER7);
++ dialect = ppc_parse_cpu (dialect, &sticky, "e5500");
+ break;
+ case bfd_mach_ppc_e6500:
+- dialect = (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
+- | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
+- | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_ALTIVEC
+- | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_E6500 | PPC_OPCODE_POWER4
+- | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7);
++ dialect = ppc_parse_cpu (dialect, &sticky, "e6500");
+ break;
+ case bfd_mach_ppc_titan:
+- dialect = (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR
+- | PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN);
++ dialect = ppc_parse_cpu (dialect, &sticky, "titan");
+ break;
+ case bfd_mach_ppc_vle:
+- dialect = (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_VLE);
++ dialect = ppc_parse_cpu (dialect, &sticky, "vle");
+ break;
+ default:
+ dialect = ppc_parse_cpu (dialect, &sticky, "power8") | PPC_OPCODE_ANY;
diff --git a/SOURCES/gdb-rhbz1320945-power9pre-3of3.patch b/SOURCES/gdb-rhbz1320945-power9pre-3of3.patch
new file mode 100644
index 0000000..25f633d
--- /dev/null
+++ b/SOURCES/gdb-rhbz1320945-power9pre-3of3.patch
@@ -0,0 +1,673 @@
+commit f9c6b9078c54ea0f018b673e2ff128e61a0aa666
+Author: Alan Modra <amodra@gmail.com>
+Date: Tue Oct 29 16:53:25 2013 +1030
+
+ Report overflow on PowerPC64 @h and @ha relocations.
+
+ This changes the behaviour of @h and @ha on PowerPC64 to report errors
+ on 32-bit overflow. The motivation for this change is that on
+ PowerPC64, most uses of @h and @ha modifiers and their corresponding
+ relocations are to build up 32-bit offsets. We'd like to know when
+ such offsets overflow. Only rarely do people use @h or @ha with the
+ high 32-bit modifiers to build a 64-bit constant. Those uses will now
+ need to use two new modifiers, @high and @higha, if the constant isn't
+ known at assembly time. For now, we won't report overflow at assembly
+ time..
+
+ This also fixes an error when applying some of the HIGHER and HIGHEST
+ relocations.
+
+ include/elf/
+ * ppc64.h (R_PPC64_ADDR16_HIGH, R_PPC64_ADDR16_HIGHA,
+ R_PPC64_TPREL16_HIGH, R_PPC64_TPREL16_HIGHA,
+ R_PPC64_DTPREL16_HIGH, R_PPC64_DTPREL16_HIGHA): New.
+ (IS_PPC64_TLS_RELOC): Match new tls relocs.
+ bfd/
+ * reloc.c (BFD_RELOC_PPC64_ADDR16_HIGH, BFD_RELOC_PPC64_ADDR16_HIGHA,
+ BFD_RELOC_PPC64_TPREL16_HIGH, BFD_RELOC_PPC64_TPREL16_HIGHA,
+ BFD_RELOC_PPC64_DTPREL16_HIGH, BFD_RELOC_PPC64_DTPREL16_HIGHA): New.
+ * elf64-ppc.c (ppc64_elf_howto_raw): Add entries for new relocs.
+ Make all _HA and _HI relocs report signed overflow.
+ (ppc64_elf_reloc_type_lookup): Handle new relocs.
+ (must_be_dyn_reloc, ppc64_elf_check_relocs): Likewise.
+ (dec_dynrel_count, ppc64_elf_relocate_section): Likewise.
+ (ppc64_elf_relocate_section): Don't apply 0x8000 adjust to
+ R_PPC64_TPREL16_HIGHER, R_PPC64_TPREL16_HIGHEST,
+ R_PPC64_DTPREL16_HIGHER, and R_PPC64_DTPREL16_HIGHEST.
+ * libbfd.h: Regenerate.
+ * bfd-in2.h: Regenerate.
+ gas/
+ * config/tc-ppc.c (SEX16): Don't mask.
+ (REPORT_OVERFLOW_HI): Define as zero.
+ (ppc_elf_suffix): Support @high, @higha, @dtprel@high, @dtprel@higha,
+ @tprel@high, and @tprel@higha modifiers.
+ (md_assemble): Ignore X_unsigned when applying 16-bit insn fields.
+ Add (disabled) code to check @h and @ha reloc overflow for powerpc64.
+ Handle new relocs.
+ (md_apply_fix): Similarly.
+ elfcpp/
+ * powerpc.h (R_PPC64_ADDR16_HIGH, R_PPC64_ADDR16_HIGHA,
+ R_PPC64_TPREL16_HIGH, R_PPC64_TPREL16_HIGHA,
+ R_PPC64_DTPREL16_HIGH, R_PPC64_DTPREL16_HIGHA): Define.
+ gold/
+ * powerpc.cc (Target_powerpc::Scan::check_non_pic): Handle new relocs.
+ (Target_powerpc::Scan::global, local): Likewise.
+ (Target_powerpc::Relocate::relocate): Likewise. Check for overflow
+ on all ppc64 @h and @ha relocs.
+
+### a/bfd/ChangeLog
+### b/bfd/ChangeLog
+## -1,3 +1,19 @@
++2013-10-30 Alan Modra <amodra@gmail.com>
++
++ * reloc.c (BFD_RELOC_PPC64_ADDR16_HIGH, BFD_RELOC_PPC64_ADDR16_HIGHA,
++ BFD_RELOC_PPC64_TPREL16_HIGH, BFD_RELOC_PPC64_TPREL16_HIGHA,
++ BFD_RELOC_PPC64_DTPREL16_HIGH, BFD_RELOC_PPC64_DTPREL16_HIGHA): New.
++ * elf64-ppc.c (ppc64_elf_howto_raw): Add entries for new relocs.
++ Make all _HA and _HI relocs report signed overflow.
++ (ppc64_elf_reloc_type_lookup): Handle new relocs.
++ (must_be_dyn_reloc, ppc64_elf_check_relocs): Likewise.
++ (dec_dynrel_count, ppc64_elf_relocate_section): Likewise.
++ (ppc64_elf_relocate_section): Don't apply 0x8000 adjust to
++ R_PPC64_TPREL16_HIGHER, R_PPC64_TPREL16_HIGHEST,
++ R_PPC64_DTPREL16_HIGHER, and R_PPC64_DTPREL16_HIGHEST.
++ * libbfd.h: Regenerate.
++ * bfd-in2.h: Regenerate.
++
+ 2013-10-29 Roland McGrath <mcgrathr@google.com>
+
+ * elf64-x86-64.c (elf_x86_64_nacl_plt0_entry): Correct 9-byte nop
+--- a/bfd/bfd-in2.h
++++ b/bfd/bfd-in2.h
+@@ -3223,6 +3223,8 @@ instruction. */
+ BFD_RELOC_PPC64_TOC16_LO_DS,
+ BFD_RELOC_PPC64_PLTGOT16_DS,
+ BFD_RELOC_PPC64_PLTGOT16_LO_DS,
++ BFD_RELOC_PPC64_ADDR16_HIGH,
++ BFD_RELOC_PPC64_ADDR16_HIGHA,
+
+ /* PowerPC and PowerPC64 thread-local storage relocations. */
+ BFD_RELOC_PPC_TLS,
+@@ -3267,6 +3269,10 @@ instruction. */
+ BFD_RELOC_PPC64_DTPREL16_HIGHERA,
+ BFD_RELOC_PPC64_DTPREL16_HIGHEST,
+ BFD_RELOC_PPC64_DTPREL16_HIGHESTA,
++ BFD_RELOC_PPC64_TPREL16_HIGH,
++ BFD_RELOC_PPC64_TPREL16_HIGHA,
++ BFD_RELOC_PPC64_DTPREL16_HIGH,
++ BFD_RELOC_PPC64_DTPREL16_HIGHA,
+
+ /* IBM 370/390 relocations */
+ BFD_RELOC_I370_D12,
+--- a/bfd/elf64-ppc.c
++++ b/bfd/elf64-ppc.c
+@@ -309,7 +309,7 @@ static reloc_howto_type ppc64_elf_howto_raw[] = {
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_dont, /* complain_on_overflow */
++ complain_overflow_signed, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_PPC64_ADDR16_HI", /* name */
+ FALSE, /* partial_inplace */
+@@ -325,7 +325,7 @@ static reloc_howto_type ppc64_elf_howto_raw[] = {
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_dont, /* complain_on_overflow */
++ complain_overflow_signed, /* complain_on_overflow */
+ ppc64_elf_ha_reloc, /* special_function */
+ "R_PPC64_ADDR16_HA", /* name */
+ FALSE, /* partial_inplace */
+@@ -487,7 +487,7 @@ static reloc_howto_type ppc64_elf_howto_raw[] = {
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_dont,/* complain_on_overflow */
++ complain_overflow_signed,/* complain_on_overflow */
+ ppc64_elf_unhandled_reloc, /* special_function */
+ "R_PPC64_GOT16_HI", /* name */
+ FALSE, /* partial_inplace */
+@@ -503,7 +503,7 @@ static reloc_howto_type ppc64_elf_howto_raw[] = {
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_dont,/* complain_on_overflow */
++ complain_overflow_signed,/* complain_on_overflow */
+ ppc64_elf_unhandled_reloc, /* special_function */
+ "R_PPC64_GOT16_HA", /* name */
+ FALSE, /* partial_inplace */
+@@ -680,7 +680,7 @@ static reloc_howto_type ppc64_elf_howto_raw[] = {
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_dont, /* complain_on_overflow */
++ complain_overflow_signed, /* complain_on_overflow */
+ ppc64_elf_unhandled_reloc, /* special_function */
+ "R_PPC64_PLT16_HI", /* name */
+ FALSE, /* partial_inplace */
+@@ -696,7 +696,7 @@ static reloc_howto_type ppc64_elf_howto_raw[] = {
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_dont, /* complain_on_overflow */
++ complain_overflow_signed, /* complain_on_overflow */
+ ppc64_elf_unhandled_reloc, /* special_function */
+ "R_PPC64_PLT16_HA", /* name */
+ FALSE, /* partial_inplace */
+@@ -741,7 +741,7 @@ static reloc_howto_type ppc64_elf_howto_raw[] = {
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_dont, /* complain_on_overflow */
++ complain_overflow_signed, /* complain_on_overflow */
+ ppc64_elf_sectoff_reloc, /* special_function */
+ "R_PPC64_SECTOFF_HI", /* name */
+ FALSE, /* partial_inplace */
+@@ -756,7 +756,7 @@ static reloc_howto_type ppc64_elf_howto_raw[] = {
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_dont, /* complain_on_overflow */
++ complain_overflow_signed, /* complain_on_overflow */
+ ppc64_elf_sectoff_ha_reloc, /* special_function */
+ "R_PPC64_SECTOFF_HA", /* name */
+ FALSE, /* partial_inplace */
+@@ -963,7 +963,7 @@ static reloc_howto_type ppc64_elf_howto_raw[] = {
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_dont, /* complain_on_overflow */
++ complain_overflow_signed, /* complain_on_overflow */
+ ppc64_elf_toc_reloc, /* special_function */
+ "R_PPC64_TOC16_HI", /* name */
+ FALSE, /* partial_inplace */
+@@ -982,7 +982,7 @@ static reloc_howto_type ppc64_elf_howto_raw[] = {
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_dont, /* complain_on_overflow */
++ complain_overflow_signed, /* complain_on_overflow */
+ ppc64_elf_toc_ha_reloc, /* special_function */
+ "R_PPC64_TOC16_HA", /* name */
+ FALSE, /* partial_inplace */
+@@ -1054,7 +1054,7 @@ static reloc_howto_type ppc64_elf_howto_raw[] = {
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_dont, /* complain_on_overflow */
++ complain_overflow_signed, /* complain_on_overflow */
+ ppc64_elf_unhandled_reloc, /* special_function */
+ "R_PPC64_PLTGOT16_HI", /* name */
+ FALSE, /* partial_inplace */
+@@ -1072,7 +1072,7 @@ static reloc_howto_type ppc64_elf_howto_raw[] = {
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_dont,/* complain_on_overflow */
++ complain_overflow_signed, /* complain_on_overflow */
+ ppc64_elf_unhandled_reloc, /* special_function */
+ "R_PPC64_PLTGOT16_HA", /* name */
+ FALSE, /* partial_inplace */
+@@ -1374,7 +1374,7 @@ static reloc_howto_type ppc64_elf_howto_raw[] = {
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_dont, /* complain_on_overflow */
++ complain_overflow_signed, /* complain_on_overflow */
+ ppc64_elf_unhandled_reloc, /* special_function */
+ "R_PPC64_DTPREL16_HI", /* name */
+ FALSE, /* partial_inplace */
+@@ -1389,7 +1389,7 @@ static reloc_howto_type ppc64_elf_howto_raw[] = {
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_dont, /* complain_on_overflow */
++ complain_overflow_signed, /* complain_on_overflow */
+ ppc64_elf_unhandled_reloc, /* special_function */
+ "R_PPC64_DTPREL16_HA", /* name */
+ FALSE, /* partial_inplace */
+@@ -1540,7 +1540,7 @@ static reloc_howto_type ppc64_elf_howto_raw[] = {
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_dont, /* complain_on_overflow */
++ complain_overflow_signed, /* complain_on_overflow */
+ ppc64_elf_unhandled_reloc, /* special_function */
+ "R_PPC64_TPREL16_HI", /* name */
+ FALSE, /* partial_inplace */
+@@ -1555,7 +1555,7 @@ static reloc_howto_type ppc64_elf_howto_raw[] = {
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_dont, /* complain_on_overflow */
++ complain_overflow_signed, /* complain_on_overflow */
+ ppc64_elf_unhandled_reloc, /* special_function */
+ "R_PPC64_TPREL16_HA", /* name */
+ FALSE, /* partial_inplace */
+@@ -1692,7 +1692,7 @@ static reloc_howto_type ppc64_elf_howto_raw[] = {
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_dont, /* complain_on_overflow */
++ complain_overflow_signed, /* complain_on_overflow */
+ ppc64_elf_unhandled_reloc, /* special_function */
+ "R_PPC64_GOT_TLSGD16_HI", /* name */
+ FALSE, /* partial_inplace */
+@@ -1707,7 +1707,7 @@ static reloc_howto_type ppc64_elf_howto_raw[] = {
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_dont, /* complain_on_overflow */
++ complain_overflow_signed, /* complain_on_overflow */
+ ppc64_elf_unhandled_reloc, /* special_function */
+ "R_PPC64_GOT_TLSGD16_HA", /* name */
+ FALSE, /* partial_inplace */
+@@ -1754,7 +1754,7 @@ static reloc_howto_type ppc64_elf_howto_raw[] = {
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_dont, /* complain_on_overflow */
++ complain_overflow_signed, /* complain_on_overflow */
+ ppc64_elf_unhandled_reloc, /* special_function */
+ "R_PPC64_GOT_TLSLD16_HI", /* name */
+ FALSE, /* partial_inplace */
+@@ -1769,7 +1769,7 @@ static reloc_howto_type ppc64_elf_howto_raw[] = {
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_dont, /* complain_on_overflow */
++ complain_overflow_signed, /* complain_on_overflow */
+ ppc64_elf_unhandled_reloc, /* special_function */
+ "R_PPC64_GOT_TLSLD16_HA", /* name */
+ FALSE, /* partial_inplace */
+@@ -1815,7 +1815,7 @@ static reloc_howto_type ppc64_elf_howto_raw[] = {
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_dont, /* complain_on_overflow */
++ complain_overflow_signed, /* complain_on_overflow */
+ ppc64_elf_unhandled_reloc, /* special_function */
+ "R_PPC64_GOT_DTPREL16_HI", /* name */
+ FALSE, /* partial_inplace */
+@@ -1830,7 +1830,7 @@ static reloc_howto_type ppc64_elf_howto_raw[] = {
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_dont, /* complain_on_overflow */
++ complain_overflow_signed, /* complain_on_overflow */
+ ppc64_elf_unhandled_reloc, /* special_function */
+ "R_PPC64_GOT_DTPREL16_HA", /* name */
+ FALSE, /* partial_inplace */
+@@ -1876,7 +1876,7 @@ static reloc_howto_type ppc64_elf_howto_raw[] = {
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_dont, /* complain_on_overflow */
++ complain_overflow_signed, /* complain_on_overflow */
+ ppc64_elf_unhandled_reloc, /* special_function */
+ "R_PPC64_GOT_TPREL16_HI", /* name */
+ FALSE, /* partial_inplace */
+@@ -1891,7 +1891,7 @@ static reloc_howto_type ppc64_elf_howto_raw[] = {
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_dont, /* complain_on_overflow */
++ complain_overflow_signed, /* complain_on_overflow */
+ ppc64_elf_unhandled_reloc, /* special_function */
+ "R_PPC64_GOT_TPREL16_HA", /* name */
+ FALSE, /* partial_inplace */
+@@ -1964,7 +1964,7 @@ static reloc_howto_type ppc64_elf_howto_raw[] = {
+ 16, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_dont, /* complain_on_overflow */
++ complain_overflow_signed, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_PPC64_REL16_HI", /* name */
+ FALSE, /* partial_inplace */
+@@ -1980,7 +1980,7 @@ static reloc_howto_type ppc64_elf_howto_raw[] = {
+ 16, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+- complain_overflow_dont, /* complain_on_overflow */
++ complain_overflow_signed, /* complain_on_overflow */
+ ppc64_elf_ha_reloc, /* special_function */
+ "R_PPC64_REL16_HA", /* name */
+ FALSE, /* partial_inplace */
+@@ -1988,6 +1988,96 @@ static reloc_howto_type ppc64_elf_howto_raw[] = {
+ 0xffff, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
++ /* Like R_PPC64_ADDR16_HI, but no overflow. */
++ HOWTO (R_PPC64_ADDR16_HIGH, /* type */
++ 16, /* rightshift */
++ 1, /* size (0 = byte, 1 = short, 2 = long) */
++ 16, /* bitsize */
++ FALSE, /* pc_relative */
++ 0, /* bitpos */
++ complain_overflow_dont, /* complain_on_overflow */
++ bfd_elf_generic_reloc, /* special_function */
++ "R_PPC64_ADDR16_HIGH", /* name */
++ FALSE, /* partial_inplace */
++ 0, /* src_mask */
++ 0xffff, /* dst_mask */
++ FALSE), /* pcrel_offset */
++
++ /* Like R_PPC64_ADDR16_HA, but no overflow. */
++ HOWTO (R_PPC64_ADDR16_HIGHA, /* type */
++ 16, /* rightshift */
++ 1, /* size (0 = byte, 1 = short, 2 = long) */
++ 16, /* bitsize */
++ FALSE, /* pc_relative */
++ 0, /* bitpos */
++ complain_overflow_dont, /* complain_on_overflow */
++ ppc64_elf_ha_reloc, /* special_function */
++ "R_PPC64_ADDR16_HIGHA", /* name */
++ FALSE, /* partial_inplace */
++ 0, /* src_mask */
++ 0xffff, /* dst_mask */
++ FALSE), /* pcrel_offset */
++
++ /* Like R_PPC64_DTPREL16_HI, but no overflow. */
++ HOWTO (R_PPC64_DTPREL16_HIGH,
++ 16, /* rightshift */
++ 1, /* size (0 = byte, 1 = short, 2 = long) */
++ 16, /* bitsize */
++ FALSE, /* pc_relative */
++ 0, /* bitpos */
++ complain_overflow_dont, /* complain_on_overflow */
++ ppc64_elf_unhandled_reloc, /* special_function */
++ "R_PPC64_DTPREL16_HIGH", /* name */
++ FALSE, /* partial_inplace */
++ 0, /* src_mask */
++ 0xffff, /* dst_mask */
++ FALSE), /* pcrel_offset */
++
++ /* Like R_PPC64_DTPREL16_HA, but no overflow. */
++ HOWTO (R_PPC64_DTPREL16_HIGHA,
++ 16, /* rightshift */
++ 1, /* size (0 = byte, 1 = short, 2 = long) */
++ 16, /* bitsize */
++ FALSE, /* pc_relative */
++ 0, /* bitpos */
++ complain_overflow_dont, /* complain_on_overflow */
++ ppc64_elf_unhandled_reloc, /* special_function */
++ "R_PPC64_DTPREL16_HIGHA", /* name */
++ FALSE, /* partial_inplace */
++ 0, /* src_mask */
++ 0xffff, /* dst_mask */
++ FALSE), /* pcrel_offset */
++
++ /* Like R_PPC64_TPREL16_HI, but no overflow. */
++ HOWTO (R_PPC64_TPREL16_HIGH,
++ 16, /* rightshift */
++ 1, /* size (0 = byte, 1 = short, 2 = long) */
++ 16, /* bitsize */
++ FALSE, /* pc_relative */
++ 0, /* bitpos */
++ complain_overflow_dont, /* complain_on_overflow */
++ ppc64_elf_unhandled_reloc, /* special_function */
++ "R_PPC64_TPREL16_HIGH", /* name */
++ FALSE, /* partial_inplace */
++ 0, /* src_mask */
++ 0xffff, /* dst_mask */
++ FALSE), /* pcrel_offset */
++
++ /* Like R_PPC64_TPREL16_HA, but no overflow. */
++ HOWTO (R_PPC64_TPREL16_HIGHA,
++ 16, /* rightshift */
++ 1, /* size (0 = byte, 1 = short, 2 = long) */
++ 16, /* bitsize */
++ FALSE, /* pc_relative */
++ 0, /* bitpos */
++ complain_overflow_dont, /* complain_on_overflow */
++ ppc64_elf_unhandled_reloc, /* special_function */
++ "R_PPC64_TPREL16_HIGHA", /* name */
++ FALSE, /* partial_inplace */
++ 0, /* src_mask */
++ 0xffff, /* dst_mask */
++ FALSE), /* pcrel_offset */
++
+ /* GNU extension to record C++ vtable hierarchy. */
+ HOWTO (R_PPC64_GNU_VTINHERIT, /* type */
+ 0, /* rightshift */
+@@ -2066,8 +2156,12 @@ ppc64_elf_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
+ break;
+ case BFD_RELOC_HI16: r = R_PPC64_ADDR16_HI;
+ break;
++ case BFD_RELOC_PPC64_ADDR16_HIGH: r = R_PPC64_ADDR16_HIGH;
++ break;
+ case BFD_RELOC_HI16_S: r = R_PPC64_ADDR16_HA;
+ break;
++ case BFD_RELOC_PPC64_ADDR16_HIGHA: r = R_PPC64_ADDR16_HIGHA;
++ break;
+ case BFD_RELOC_PPC_BA16: r = R_PPC64_ADDR14;
+ break;
+ case BFD_RELOC_PPC_BA16_BRTAKEN: r = R_PPC64_ADDR14_BRTAKEN;
+@@ -2186,8 +2280,12 @@ ppc64_elf_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
+ break;
+ case BFD_RELOC_PPC_TPREL16_HI: r = R_PPC64_TPREL16_HI;
+ break;
++ case BFD_RELOC_PPC64_TPREL16_HIGH: r = R_PPC64_TPREL16_HIGH;
++ break;
+ case BFD_RELOC_PPC_TPREL16_HA: r = R_PPC64_TPREL16_HA;
+ break;
++ case BFD_RELOC_PPC64_TPREL16_HIGHA: r = R_PPC64_TPREL16_HIGHA;
++ break;
+ case BFD_RELOC_PPC_TPREL: r = R_PPC64_TPREL64;
+ break;
+ case BFD_RELOC_PPC_DTPREL16: r = R_PPC64_DTPREL16;
+@@ -2196,8 +2294,12 @@ ppc64_elf_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
+ break;
+ case BFD_RELOC_PPC_DTPREL16_HI: r = R_PPC64_DTPREL16_HI;
+ break;
++ case BFD_RELOC_PPC64_DTPREL16_HIGH: r = R_PPC64_DTPREL16_HIGH;
++ break;
+ case BFD_RELOC_PPC_DTPREL16_HA: r = R_PPC64_DTPREL16_HA;
+ break;
++ case BFD_RELOC_PPC64_DTPREL16_HIGHA: r = R_PPC64_DTPREL16_HIGHA;
++ break;
+ case BFD_RELOC_PPC_DTPREL: r = R_PPC64_DTPREL64;
+ break;
+ case BFD_RELOC_PPC_GOT_TLSGD16: r = R_PPC64_GOT_TLSGD16;
+@@ -3514,6 +3616,8 @@ must_be_dyn_reloc (struct bfd_link_info *info,
+ case R_PPC64_TPREL16_HA:
+ case R_PPC64_TPREL16_DS:
+ case R_PPC64_TPREL16_LO_DS:
++ case R_PPC64_TPREL16_HIGH:
++ case R_PPC64_TPREL16_HIGHA:
+ case R_PPC64_TPREL16_HIGHER:
+ case R_PPC64_TPREL16_HIGHERA:
+ case R_PPC64_TPREL16_HIGHEST:
+@@ -5208,6 +5312,8 @@ ppc64_elf_check_relocs (bfd *abfd, struct bfd_link_info *info,
+ case R_PPC64_DTPREL16_HA:
+ case R_PPC64_DTPREL16_DS:
+ case R_PPC64_DTPREL16_LO_DS:
++ case R_PPC64_DTPREL16_HIGH:
++ case R_PPC64_DTPREL16_HIGHA:
+ case R_PPC64_DTPREL16_HIGHER:
+ case R_PPC64_DTPREL16_HIGHERA:
+ case R_PPC64_DTPREL16_HIGHEST:
+@@ -5368,6 +5474,8 @@ ppc64_elf_check_relocs (bfd *abfd, struct bfd_link_info *info,
+ case R_PPC64_TPREL16_HA:
+ case R_PPC64_TPREL16_DS:
+ case R_PPC64_TPREL16_LO_DS:
++ case R_PPC64_TPREL16_HIGH:
++ case R_PPC64_TPREL16_HIGHA:
+ case R_PPC64_TPREL16_HIGHER:
+ case R_PPC64_TPREL16_HIGHERA:
+ case R_PPC64_TPREL16_HIGHEST:
+@@ -5421,6 +5529,8 @@ ppc64_elf_check_relocs (bfd *abfd, struct bfd_link_info *info,
+ case R_PPC64_ADDR16_DS:
+ case R_PPC64_ADDR16_HA:
+ case R_PPC64_ADDR16_HI:
++ case R_PPC64_ADDR16_HIGH:
++ case R_PPC64_ADDR16_HIGHA:
+ case R_PPC64_ADDR16_HIGHER:
+ case R_PPC64_ADDR16_HIGHERA:
+ case R_PPC64_ADDR16_HIGHEST:
+@@ -7052,6 +7162,8 @@ dec_dynrel_count (bfd_vma r_info,
+ case R_PPC64_TPREL16_HA:
+ case R_PPC64_TPREL16_DS:
+ case R_PPC64_TPREL16_LO_DS:
++ case R_PPC64_TPREL16_HIGH:
++ case R_PPC64_TPREL16_HIGHA:
+ case R_PPC64_TPREL16_HIGHER:
+ case R_PPC64_TPREL16_HIGHERA:
+ case R_PPC64_TPREL16_HIGHEST:
+@@ -7073,6 +7185,8 @@ dec_dynrel_count (bfd_vma r_info,
+ case R_PPC64_ADDR16_DS:
+ case R_PPC64_ADDR16_HA:
+ case R_PPC64_ADDR16_HI:
++ case R_PPC64_ADDR16_HIGH:
++ case R_PPC64_ADDR16_HIGHA:
+ case R_PPC64_ADDR16_HIGHER:
+ case R_PPC64_ADDR16_HIGHERA:
+ case R_PPC64_ADDR16_HIGHEST:
+@@ -13531,6 +13645,8 @@ ppc64_elf_relocate_section (bfd *output_bfd,
+ case R_PPC64_TPREL16_HA:
+ case R_PPC64_TPREL16_DS:
+ case R_PPC64_TPREL16_LO_DS:
++ case R_PPC64_TPREL16_HIGH:
++ case R_PPC64_TPREL16_HIGHA:
+ case R_PPC64_TPREL16_HIGHER:
+ case R_PPC64_TPREL16_HIGHERA:
+ case R_PPC64_TPREL16_HIGHEST:
+@@ -13565,6 +13681,8 @@ ppc64_elf_relocate_section (bfd *output_bfd,
+ case R_PPC64_DTPREL16_HA:
+ case R_PPC64_DTPREL16_DS:
+ case R_PPC64_DTPREL16_LO_DS:
++ case R_PPC64_DTPREL16_HIGH:
++ case R_PPC64_DTPREL16_HIGHA:
+ case R_PPC64_DTPREL16_HIGHER:
+ case R_PPC64_DTPREL16_HIGHERA:
+ case R_PPC64_DTPREL16_HIGHEST:
+@@ -13597,6 +13715,8 @@ ppc64_elf_relocate_section (bfd *output_bfd,
+ case R_PPC64_ADDR16_DS:
+ case R_PPC64_ADDR16_HA:
+ case R_PPC64_ADDR16_HI:
++ case R_PPC64_ADDR16_HIGH:
++ case R_PPC64_ADDR16_HIGHA:
+ case R_PPC64_ADDR16_HIGHER:
+ case R_PPC64_ADDR16_HIGHERA:
+ case R_PPC64_ADDR16_HIGHEST:
+@@ -13911,21 +14031,20 @@ ppc64_elf_relocate_section (bfd *output_bfd,
+ default:
+ break;
+
+- case R_PPC64_ADDR16_HA:
+ case R_PPC64_REL16_HA:
++ case R_PPC64_ADDR16_HA:
++ case R_PPC64_ADDR16_HIGHA:
+ case R_PPC64_ADDR16_HIGHERA:
+ case R_PPC64_ADDR16_HIGHESTA:
+ case R_PPC64_TOC16_HA:
+ case R_PPC64_SECTOFF_HA:
+ case R_PPC64_TPREL16_HA:
+- case R_PPC64_DTPREL16_HA:
+- case R_PPC64_TPREL16_HIGHER:
++ case R_PPC64_TPREL16_HIGHA:
+ case R_PPC64_TPREL16_HIGHERA:
+- case R_PPC64_TPREL16_HIGHEST:
+ case R_PPC64_TPREL16_HIGHESTA:
+- case R_PPC64_DTPREL16_HIGHER:
++ case R_PPC64_DTPREL16_HA:
++ case R_PPC64_DTPREL16_HIGHA:
+ case R_PPC64_DTPREL16_HIGHERA:
+- case R_PPC64_DTPREL16_HIGHEST:
+ case R_PPC64_DTPREL16_HIGHESTA:
+ /* It's just possible that this symbol is a weak symbol
+ that's not actually defined anywhere. In that case,
+--- a/bfd/libbfd.h
++++ b/bfd/libbfd.h
+@@ -1397,6 +1397,8 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
+ "BFD_RELOC_PPC64_TOC16_LO_DS",
+ "BFD_RELOC_PPC64_PLTGOT16_DS",
+ "BFD_RELOC_PPC64_PLTGOT16_LO_DS",
++ "BFD_RELOC_PPC64_ADDR16_HIGH",
++ "BFD_RELOC_PPC64_ADDR16_HIGHA",
+ "BFD_RELOC_PPC_TLS",
+ "BFD_RELOC_PPC_TLSGD",
+ "BFD_RELOC_PPC_TLSLD",
+@@ -1439,6 +1441,10 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
+ "BFD_RELOC_PPC64_DTPREL16_HIGHERA",
+ "BFD_RELOC_PPC64_DTPREL16_HIGHEST",
+ "BFD_RELOC_PPC64_DTPREL16_HIGHESTA",
++ "BFD_RELOC_PPC64_TPREL16_HIGH",
++ "BFD_RELOC_PPC64_TPREL16_HIGHA",
++ "BFD_RELOC_PPC64_DTPREL16_HIGH",
++ "BFD_RELOC_PPC64_DTPREL16_HIGHA",
+ "BFD_RELOC_I370_D12",
+ "BFD_RELOC_CTOR",
+ "BFD_RELOC_ARM_PCREL_BRANCH",
+--- a/bfd/reloc.c
++++ b/bfd/reloc.c
+@@ -2891,6 +2891,10 @@ ENUMX
+ BFD_RELOC_PPC64_PLTGOT16_DS
+ ENUMX
+ BFD_RELOC_PPC64_PLTGOT16_LO_DS
++ENUMX
++ BFD_RELOC_PPC64_ADDR16_HIGH
++ENUMX
++ BFD_RELOC_PPC64_ADDR16_HIGHA
+ ENUMDOC
+ Power(rs6000) and PowerPC relocations.
+
+@@ -2978,6 +2982,14 @@ ENUMX
+ BFD_RELOC_PPC64_DTPREL16_HIGHEST
+ ENUMX
+ BFD_RELOC_PPC64_DTPREL16_HIGHESTA
++ENUMX
++ BFD_RELOC_PPC64_TPREL16_HIGH
++ENUMX
++ BFD_RELOC_PPC64_TPREL16_HIGHA
++ENUMX
++ BFD_RELOC_PPC64_DTPREL16_HIGH
++ENUMX
++ BFD_RELOC_PPC64_DTPREL16_HIGHA
+ ENUMDOC
+ PowerPC and PowerPC64 thread-local storage relocations.
+
+### a/include/elf/ChangeLog
+### b/include/elf/ChangeLog
+## -1,3 +1,10 @@
++2013-10-30 Alan Modra <amodra@gmail.com>
++
++ * ppc64.h (R_PPC64_ADDR16_HIGH, R_PPC64_ADDR16_HIGHA,
++ R_PPC64_TPREL16_HIGH, R_PPC64_TPREL16_HIGHA,
++ R_PPC64_DTPREL16_HIGH, R_PPC64_DTPREL16_HIGHA): New.
++ (IS_PPC64_TLS_RELOC): Match new tls relocs.
++
+ 2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
+
+ * mips.h (enum): Add Tag_GNU_MIPS_ABI_MSA.
+--- a/include/elf/ppc64.h
++++ b/include/elf/ppc64.h
+@@ -141,6 +141,14 @@ START_RELOC_NUMBERS (elf_ppc64_reloc_type)
+ RELOC_NUMBER (R_PPC64_TLSLD, 108)
+ RELOC_NUMBER (R_PPC64_TOCSAVE, 109)
+
++/* Added when HA and HI relocs were changed to report overflows. */
++ RELOC_NUMBER (R_PPC64_ADDR16_HIGH, 110)
++ RELOC_NUMBER (R_PPC64_ADDR16_HIGHA, 111)
++ RELOC_NUMBER (R_PPC64_TPREL16_HIGH, 112)
++ RELOC_NUMBER (R_PPC64_TPREL16_HIGHA, 113)
++ RELOC_NUMBER (R_PPC64_DTPREL16_HIGH, 114)
++ RELOC_NUMBER (R_PPC64_DTPREL16_HIGHA, 115)
++
+ #ifndef RELOC_MACROS_GEN_FUNC
+ /* Fake relocation only used internally by ld. */
+ RELOC_NUMBER (R_PPC64_LO_DS_OPT, 128)
+@@ -161,8 +169,9 @@ START_RELOC_NUMBERS (elf_ppc64_reloc_type)
+
+ END_RELOC_NUMBERS (R_PPC64_max)
+
+-#define IS_PPC64_TLS_RELOC(R) \
+- ((R) >= R_PPC64_TLS && (R) <= R_PPC64_DTPREL16_HIGHESTA)
++#define IS_PPC64_TLS_RELOC(R) \
++ (((R) >= R_PPC64_TLS && (R) <= R_PPC64_DTPREL16_HIGHESTA) \
++ || ((R) >= R_PPC64_TPREL16_HIGH && (R) <= R_PPC64_DTPREL16_HIGHA))
+
+ /* Specify the start of the .glink section. */
+ #define DT_PPC64_GLINK DT_LOPROC
diff --git a/SPECS/gdb.spec b/SPECS/gdb.spec
index dcea07e..9d4e98e 100644
--- a/SPECS/gdb.spec
+++ b/SPECS/gdb.spec
@@ -18,6 +18,9 @@
%global el5 1
%endif
+# Fix RHEL GDB build with devtoolset-*-build installed (RH BZ 1422193).
+%undefine scl
+
%{?scl:%scl_package gdb}
%{!?scl:
%global pkg_name %{name}
@@ -39,7 +42,7 @@ Version: 7.6.1
# The release always contains a leading reserved number, start it at 1.
# `upstream' is not a part of `name' to stay fully rpm dependencies compatible for the testing.
-Release: 94%{?dist}
+Release: 100%{?dist}
License: GPLv3+ and GPLv3+ with exceptions and GPLv2+ and GPLv2+ with exceptions and GPL+ and LGPLv2+ and BSD and Public Domain
Group: Development/Debuggers
@@ -833,6 +836,58 @@ Patch992: gdb-rhbz1350436-type-printers-error.patch
# (Andrew Pinski, RH BZ 1363635).
Patch1141: gdb-rhbz1363635-aarch64-armv8182.patch
+# [ppc*] IBM Power9 and __float128 backport (RH BZ 1320945).
+Patch1156: gdb-rhbz1320945-float128-1of9.patch
+Patch1157: gdb-rhbz1320945-float128-2of9.patch
+Patch1158: gdb-rhbz1320945-float128-3of9.patch
+Patch1159: gdb-rhbz1320945-float128-4of9.patch
+Patch1160: gdb-rhbz1320945-float128-5of9.patch
+Patch1161: gdb-rhbz1320945-float128-6of9.patch
+Patch1162: gdb-rhbz1320945-float128-7of9.patch
+Patch1163: gdb-rhbz1320945-float128-8of9.patch
+Patch1164: gdb-rhbz1320945-float128-9of9.patch
+Patch1165: gdb-rhbz1320945-power9pre-1of3.patch
+Patch1166: gdb-rhbz1320945-power9pre-2of3.patch
+Patch1167: gdb-rhbz1320945-power9pre-3of3.patch
+Patch1172: gdb-rhbz1320945-power9-01of38.patch
+Patch1173: gdb-rhbz1320945-power9-02of38.patch
+Patch1174: gdb-rhbz1320945-power9-03of38.patch
+Patch1175: gdb-rhbz1320945-power9-04of38.patch
+Patch1176: gdb-rhbz1320945-power9-05of38.patch
+Patch1177: gdb-rhbz1320945-power9-06of38.patch
+Patch1178: gdb-rhbz1320945-power9-07of38.patch
+Patch1179: gdb-rhbz1320945-power9-08of38.patch
+Patch1180: gdb-rhbz1320945-power9-09of38.patch
+Patch1181: gdb-rhbz1320945-power9-10of38.patch
+Patch1182: gdb-rhbz1320945-power9-11of38.patch
+Patch1183: gdb-rhbz1320945-power9-12of38.patch
+Patch1184: gdb-rhbz1320945-power9-13of38.patch
+Patch1185: gdb-rhbz1320945-power9-14of38.patch
+Patch1186: gdb-rhbz1320945-power9-15of38.patch
+Patch1187: gdb-rhbz1320945-power9-16of38.patch
+Patch1188: gdb-rhbz1320945-power9-17of38.patch
+Patch1189: gdb-rhbz1320945-power9-18of38.patch
+Patch1190: gdb-rhbz1320945-power9-19of38.patch
+Patch1191: gdb-rhbz1320945-power9-20of38.patch
+Patch1192: gdb-rhbz1320945-power9-21of38.patch
+Patch1193: gdb-rhbz1320945-power9-22of38.patch
+Patch1194: gdb-rhbz1320945-power9-23of38.patch
+Patch1195: gdb-rhbz1320945-power9-24of38.patch
+Patch1196: gdb-rhbz1320945-power9-25of38.patch
+Patch1197: gdb-rhbz1320945-power9-26of38.patch
+Patch1198: gdb-rhbz1320945-power9-27of38.patch
+Patch1199: gdb-rhbz1320945-power9-28of38.patch
+Patch1200: gdb-rhbz1320945-power9-29of38.patch
+Patch1201: gdb-rhbz1320945-power9-30of38.patch
+Patch1202: gdb-rhbz1320945-power9-31of38.patch
+Patch1203: gdb-rhbz1320945-power9-32of38.patch
+Patch1204: gdb-rhbz1320945-power9-33of38.patch
+Patch1205: gdb-rhbz1320945-power9-34of38.patch
+Patch1206: gdb-rhbz1320945-power9-35of38.patch
+Patch1207: gdb-rhbz1320945-power9-36of38.patch
+Patch1208: gdb-rhbz1320945-power9-37of38.patch
+Patch1209: gdb-rhbz1320945-power9-38of38.patch
+
%if 0%{!?rhel:1} || 0%{?rhel} > 6
# RL_STATE_FEDORA_GDB would not be found for:
# Patch642: gdb-readline62-ask-more-rh.patch
@@ -1172,6 +1227,9 @@ find -name "*.info*"|xargs rm -f
%patch850 -p1
%patch851 -p1
%patch852 -p1
+%patch1165 -p1
+%patch1166 -p1
+%patch1167 -p1
%patch928 -p1
%patch929 -p1
%patch930 -p1
@@ -1309,6 +1367,53 @@ find -name "*.info*"|xargs rm -f
%patch1128 -p1
%patch1129 -p1
%patch1141 -p1
+%patch1156 -p1
+%patch1157 -p1
+%patch1158 -p1
+%patch1159 -p1
+%patch1160 -p1
+%patch1161 -p1
+%patch1162 -p1
+%patch1163 -p1
+%patch1164 -p1
+%patch1172 -p1
+%patch1173 -p1
+%patch1174 -p1
+%patch1175 -p1
+%patch1176 -p1
+%patch1177 -p1
+%patch1178 -p1
+%patch1179 -p1
+%patch1180 -p1
+%patch1181 -p1
+%patch1182 -p1
+%patch1183 -p1
+%patch1184 -p1
+%patch1185 -p1
+%patch1186 -p1
+%patch1187 -p1
+%patch1188 -p1
+%patch1189 -p1
+%patch1190 -p1
+%patch1191 -p1
+%patch1192 -p1
+%patch1193 -p1
+%patch1194 -p1
+%patch1195 -p1
+%patch1196 -p1
+%patch1197 -p1
+%patch1198 -p1
+%patch1199 -p1
+%patch1200 -p1
+%patch1201 -p1
+%patch1202 -p1
+%patch1203 -p1
+%patch1204 -p1
+%patch1205 -p1
+%patch1206 -p1
+%patch1207 -p1
+%patch1208 -p1
+%patch1209 -p1
%if 0%{?scl:1}
%patch836 -p1 -R
@@ -1834,6 +1939,25 @@ fi
%endif # 0%{!?el5:1} || "%{_target_cpu}" == "noarch"
%changelog
+* Tue Jun 13 2017 Jan Kratochvil <jan.kratochvil@redhat.com> - 7.6.1-100.el7
+- [ppc*] IBM Power9 backport extension (RH BZ 1320945).
+
+* Fri Apr 21 2017 Jan Kratochvil <jan.kratochvil@redhat.com> - 7.6.1-99.el7
+- [ppc*] Fix gdb.arch/powerpc-power7.exp testcase regression (RH BZ 1440044).
+
+* Sun Mar 19 2017 Jan Kratochvil <jan.kratochvil@redhat.com> - 7.6.1-98.el7
+- [ppc*] IBM Power9 and __float128 backport (RH BZ 1320945).
+
+* Fri Mar 10 2017 Jan Kratochvil <jan.kratochvil@redhat.com> - 7.6.1-97.el7
+- [testsuite] [ppc*,s390*] Do not FAIL rhbz1261564-aarch64-watchpoint.exp
+ (RH BZ 1352563).
+
+* Wed Mar 8 2017 Jan Kratochvil <jan.kratochvil@redhat.com> - 7.6.1-96.el7
+- [testsuite] Fix ppc64 run of dw2-lexical-block-bare.exp (RH BZ 1357079).
+
+* Mon Mar 6 2017 Jan Kratochvil <jan.kratochvil@redhat.com> - 7.6.1-95.el7
+- Fix RHEL GDB build with devtoolset-*-build installed (RH BZ 1422193).
+
* Wed Aug 3 2016 Jan Kratochvil <jan.kratochvil@redhat.com> - 7.6.1-94.el7
- [aarch64] Fix ARMv8.1/v8.2 for hw watchpoint and breakpoint
(Andrew Pinski, RH BZ 1363635).