diff --git a/SOURCES/_gdb.spec.Patch.include b/SOURCES/_gdb.spec.Patch.include
index 66854cf..0b35c97 100644
--- a/SOURCES/_gdb.spec.Patch.include
+++ b/SOURCES/_gdb.spec.Patch.include
@@ -656,3 +656,21 @@ Patch160: gdb-rhbz1708192-parse_macro_definition-crash.patch
# Keith Seitz, RH BZ 1740299.
Patch161: gdb-rhbz1742099-reject-sections-with-invalid-sizes.patch
+# Fix 'GDB needs s390x arch13 binutils patches'
+# RHBZ 1768593, Andreas Krebbel
+# This patch contains only the opcodes change.
+Patch162: gdb-rhbz1768593-s390x-arch13-01.patch
+
+# Fix 'GDB needs s390x arch13 binutils patches'
+# RHBZ 1768593, Andreas Krebbel
+# This patch contains only the opcodes and include changes.
+Patch163: gdb-rhbz1768593-s390x-arch13-02.patch
+
+# Fix 'GDB needs s390x arch13 binutils patches'
+# RHBZ 1768593, Andreas Krebbel
+Patch164: gdb-rhbz1768593-s390x-arch13-03.patch
+
+# Backport z15 record/replay
+# Andreas Arnaz, RH BZ 1659535
+Patch165: gdb-rhbz1659535-z15-record-replay.patch
+
diff --git a/SOURCES/_gdb.spec.patch.include b/SOURCES/_gdb.spec.patch.include
index aac0638..526e285 100644
--- a/SOURCES/_gdb.spec.patch.include
+++ b/SOURCES/_gdb.spec.patch.include
@@ -159,3 +159,7 @@
%patch159 -p1
%patch160 -p1
%patch161 -p1
+%patch162 -p1
+%patch163 -p1
+%patch164 -p1
+%patch165 -p1
diff --git a/SOURCES/gdb-rhbz1659535-z15-record-replay.patch b/SOURCES/gdb-rhbz1659535-z15-record-replay.patch
new file mode 100644
index 0000000..6385b36
--- /dev/null
+++ b/SOURCES/gdb-rhbz1659535-z15-record-replay.patch
@@ -0,0 +1,170 @@
+;; Backport z15 record/replay
+;; Andreas Arnaz, RH BZ 1659535
+
+commit 6d9d6da48e84a65871a9d72fa785105d603990a6
+Author: Andreas Arnez <arnez@linux.ibm.com>
+Date: Wed Oct 9 11:09:22 2019 +0200
+
+ s390: Add record/replay support for arch13 instructions
+
+ Enable recording most of the new "arch13" instructions on z/Architecture
+ targets, except for the specialized-function-assist instructions:
+
+ SORTL - sort lists
+ DFLTCC - deflate conversion call
+ KDSA - compute digital signature authentication
+
+ gdb/ChangeLog:
+
+ * s390-tdep.c (390_process_record): Handle new arch13 instructions
+ except SORTL, DFLTCC, and KDSA.
+
+diff --git a/gdb/s390-tdep.c b/gdb/s390-tdep.c
+--- a/gdb/s390-tdep.c
++++ b/gdb/s390-tdep.c
+@@ -4101,6 +4101,7 @@ ex:
+ case 0xb998: /* ALCR - add logical with carry */
+ case 0xb999: /* SLBR - subtract logical with borrow */
+ case 0xb9f4: /* NRK - and */
++ case 0xb9f5: /* NCRK - and with complement */
+ case 0xb9f6: /* ORK - or */
+ case 0xb9f7: /* XRK - xor */
+ case 0xb9f8: /* ARK - add */
+@@ -4133,20 +4134,32 @@ ex:
+ case 0xb919: /* SGFR - subtract */
+ case 0xb91a: /* ALGFR - add logical */
+ case 0xb91b: /* SLGFR - subtract logical */
++ case 0xb964: /* NNGRK - and 64 bit */
++ case 0xb965: /* OCGRK - or with complement 64 bit */
++ case 0xb966: /* NOGRK - or 64 bit */
++ case 0xb967: /* NXGRK - not exclusive or 64 bit */
++ case 0xb974: /* NNRK - and 32 bit */
++ case 0xb975: /* OCRK - or with complement 32 bit */
++ case 0xb976: /* NORK - or 32 bit */
++ case 0xb977: /* NXRK - not exclusive or 32 bit */
+ case 0xb980: /* NGR - and */
+ case 0xb981: /* OGR - or */
+ case 0xb982: /* XGR - xor */
+ case 0xb988: /* ALCGR - add logical with carry */
+ case 0xb989: /* SLBGR - subtract logical with borrow */
++ case 0xb9c0: /* SELFHR - select high */
+ case 0xb9e1: /* POPCNT - population count */
+ case 0xb9e4: /* NGRK - and */
++ case 0xb9e5: /* NCGRK - and with complement */
+ case 0xb9e6: /* OGRK - or */
+ case 0xb9e7: /* XGRK - xor */
+ case 0xb9e8: /* AGRK - add */
+ case 0xb9e9: /* SGRK - subtract */
+ case 0xb9ea: /* ALGRK - add logical */
++ case 0xb9e3: /* SELGR - select 64 bit */
+ case 0xb9eb: /* SLGRK - subtract logical */
+ case 0xb9ed: /* MSGRKC - multiply single 64x64 -> 64 */
++ case 0xb9f0: /* SELR - select 32 bit */
+ case 0xb9fd: /* MSRKC - multiply single 32x32 -> 32 */
+ /* 64-bit gpr destination + flags */
+ if (s390_record_gpr_g (gdbarch, regcache, inib[6]))
+@@ -4522,7 +4535,13 @@ ex:
+ return -1;
+ break;
+
+- /* 0xb932-0xb93b undefined */
++ /* 0xb932-0xb937 undefined */
++
++ /* 0xb938 unsupported: SORTL - sort lists */
++ /* 0xb939 unsupported: DFLTCC - deflate conversion call */
++ /* 0xb93a unsupported: KDSA - compute dig. signature auth. */
++
++ /* 0xb93b undefined */
+
+ case 0xb93c: /* PPNO - perform pseudorandom number operation [partial] */
+ regcache_raw_read_unsigned (regcache, S390_R1_REGNUM, &tmp);
+@@ -5452,6 +5471,13 @@ ex:
+ /* 0xe3ce undefined */
+ /* 0xe3d0-0xe3ff undefined */
+
++ case 0xe601: /* VLEBRH - vector load byte reversed element */
++ case 0xe602: /* VLEBRG - vector load byte reversed element */
++ case 0xe603: /* VLEBRF - vector load byte reversed element */
++ case 0xe604: /* VLLEBRZ - vector load byte rev. el. and zero */
++ case 0xe605: /* VLBRREP - vector load byte rev. el. and replicate */
++ case 0xe606: /* VLBR - vector load byte reversed elements */
++ case 0xe607: /* VLER - vector load elements reversed */
+ case 0xe634: /* VPKZ - vector pack zoned */
+ case 0xe635: /* VLRL - vector load rightmost with immed. length */
+ case 0xe637: /* VLRLR - vector load rightmost with length */
+@@ -5514,6 +5540,9 @@ ex:
+ case 0xe77f: /* VSRAB - vector shift right arithmetic by byte */
+ case 0xe784: /* VPDI - vector permute doubleword immediate */
+ case 0xe785: /* VBPERM - vector bit permute */
++ case 0xe786: /* VSLD - vector shift left double by bit */
++ case 0xe787: /* VSRD - vector shift right double by bit */
++ case 0xe78b: /* VSTRS - vector string search */
+ case 0xe78c: /* VPERM - vector permute */
+ case 0xe78d: /* VSEL - vector select */
+ case 0xe78e: /* VFMS - vector fp multiply and subtract */
+@@ -5542,10 +5571,10 @@ ex:
+ case 0xe7bc: /* VGFMA - vector Galois field multiply sum and accumulate */
+ case 0xe7bd: /* VSBCBI - vector subtract with borrow compute borrow indication */
+ case 0xe7bf: /* VSBI - vector subtract with borrow indication */
+- case 0xe7c0: /* VCLGD - vector convert to logical 64-bit */
+- case 0xe7c1: /* VCDLG - vector convert from logical 64-bit */
+- case 0xe7c2: /* VCGD - vector convert to fixed 64-bit */
+- case 0xe7c3: /* VCDG - vector convert from fixed 64-bit */
++ case 0xe7c0: /* VCLFP - vector fp convert to logical */
++ case 0xe7c1: /* VCFPL - vector fp convert from logical */
++ case 0xe7c2: /* VCSFP - vector fp convert to fixed */
++ case 0xe7c3: /* VCFPS - vector fp convert from fixed */
+ case 0xe7c4: /* VLDE/VFLL - vector fp load lengthened */
+ case 0xe7c5: /* VLED/VFLR - vector fp load rounded */
+ case 0xe7c7: /* VFI - vector load fp integer */
+@@ -5596,6 +5625,7 @@ ex:
+ return -1;
+ break;
+
++ case 0xe609: /* VSTEBRH - vector store byte reversed element */
+ case 0xe709: /* VSTEH - vector store element */
+ oaddr = s390_record_calc_disp (gdbarch, regcache, inib[3], insn[1], 0);
+ if (record_full_arch_list_add_mem (oaddr, 2))
+@@ -5604,6 +5634,7 @@ ex:
+ return -1;
+ break;
+
++ case 0xe60a: /* VSTEBRG - vector store byte reversed element */
+ case 0xe70a: /* VSTEG - vector store element */
+ oaddr = s390_record_calc_disp (gdbarch, regcache, inib[3], insn[1], 0);
+ if (record_full_arch_list_add_mem (oaddr, 8))
+@@ -5612,6 +5643,7 @@ ex:
+ return -1;
+ break;
+
++ case 0xe60b: /* VSTEBRF - vector store byte reversed element */
+ case 0xe70b: /* VSTEF - vector store element */
+ oaddr = s390_record_calc_disp (gdbarch, regcache, inib[3], insn[1], 0);
+ if (record_full_arch_list_add_mem (oaddr, 4))
+@@ -5622,6 +5654,8 @@ ex:
+
+ /* 0xe70c-0xe70d undefined */
+
++ case 0xe60e: /* VSTBR - vector store byte reversed elements */
++ case 0xe60f: /* VSTER - vector store elements reversed */
+ case 0xe70e: /* VST - vector store */
+ oaddr = s390_record_calc_disp (gdbarch, regcache, inib[3], insn[1], 0);
+ if (record_full_arch_list_add_mem (oaddr, 16))
+@@ -6201,7 +6235,16 @@ ex:
+ /* SSE/SIL-format instruction */
+ switch (insn[0])
+ {
+- /* 0xe500-0xe543 undefined, privileged, or unsupported */
++ /* 0xe500-0xe509 undefined, privileged, or unsupported */
++
++ case 0xe50a: /* MVCRL - move right to left */
++ regcache_raw_read_unsigned (regcache, S390_R0_REGNUM, &tmp);
++ oaddr = s390_record_calc_disp (gdbarch, regcache, 0, insn[1], 0);
++ if (record_full_arch_list_add_mem (oaddr, (tmp & 0xff) + 1))
++ return -1;
++ break;
++
++ /* 0xe50b-0xe543 undefined, privileged, or unsupported */
+
+ case 0xe544: /* MVHHI - move */
+ oaddr = s390_record_calc_disp (gdbarch, regcache, 0, insn[1], 0);
diff --git a/SOURCES/gdb-rhbz1768593-s390x-arch13-01.patch b/SOURCES/gdb-rhbz1768593-s390x-arch13-01.patch
new file mode 100644
index 0000000..fcb8707
--- /dev/null
+++ b/SOURCES/gdb-rhbz1768593-s390x-arch13-01.patch
@@ -0,0 +1,49 @@
+From FEDORA_PATCHES Mon Sep 17 00:00:00 2001
+From: Sergio Durigan Junior <sergiodj@redhat.com>
+Date: Tue, 7 Jan 2020 21:02:19 -0500
+Subject: gdb-rhbz1768593-s390x-arch13-01.patch
+
+;; Fix 'GDB needs s390x arch13 binutils patches'
+;; RHBZ 1768593, Andreas Krebbel
+;; This patch contains only the opcodes change.
+
+S/390: Support vector alignment hints
+
+This patch adds the vector alignment hints to the vector load and
+store instructions as documented in the IBM z14 Principles of
+Operations manual:
+
+http://publibfi.boulder.ibm.com/epubs/pdf/dz9zr011.pdf
+
+opcodes/ChangeLog:
+
+2018-10-23 Andreas Krebbel <krebbel@linux.ibm.com>
+
+ * s390-opc.txt: Add vector load/store instructions with additional
+ alignment parameter.
+
+gas/ChangeLog:
+
+2018-10-23 Andreas Krebbel <krebbel@linux.ibm.com>
+
+ * config/tc-s390.c (md_gather_operands): Fix for optional operands
+ following memory addresses.
+ * testsuite/gas/s390/zarch-arch12.d: Add regexp checks for new
+ instruction variants.
+ * testsuite/gas/s390/zarch-arch12.s: Emit new instruction
+ variants.
+
+diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt
+--- a/opcodes/s390-opc.txt
++++ b/opcodes/s390-opc.txt
+@@ -1880,3 +1880,10 @@ b929 kma RRF_R0RR "cipher message with galois counter mode" arch12 zarch
+ b93c prno RRE_RR "perform pseudorandom number operation" arch12 zarch
+ b9a1 tpei RRE_RR "test pending external interruption" arch12 zarch
+ b9ac irbm RRE_RR "insert reference bits multiple" arch12 zarch
++
++# Aligned vector store hints
++
++e70000000006 vl VRX_VRRDU "vector memory load" arch12 zarch optparm
++e70000000036 vlm VRS_VVRDU "vector load multiple" arch12 zarch optparm
++e7000000000e vst VRX_VRRDU "vector store" arch12 zarch optparm
++e7000000003e vstm VRS_VVRDU "vector store multiple" arch12 zarch optparm
diff --git a/SOURCES/gdb-rhbz1768593-s390x-arch13-02.patch b/SOURCES/gdb-rhbz1768593-s390x-arch13-02.patch
new file mode 100644
index 0000000..8db5282
--- /dev/null
+++ b/SOURCES/gdb-rhbz1768593-s390x-arch13-02.patch
@@ -0,0 +1,217 @@
+From FEDORA_PATCHES Mon Sep 17 00:00:00 2001
+From: Sergio Durigan Junior <sergiodj@redhat.com>
+Date: Tue, 7 Jan 2020 21:07:53 -0500
+Subject: gdb-rhbz1768593-s390x-arch13-02.patch
+
+;; Fix 'GDB needs s390x arch13 binutils patches'
+;; RHBZ 1768593, Andreas Krebbel
+;; This patch contains only the opcodes and include changes.
+
+S/390: Implement instruction set extensions
+
+opcodes/ChangeLog:
+
+2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
+
+ Backport from mainline
+ 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
+
+ * s390-mkopc.c (main): Accept arch13 as cpu string.
+ * s390-opc.c: Add new instruction formats and instruction opcode
+ masks.
+ * s390-opc.txt: Add new arch13 instructions.
+
+include/ChangeLog:
+
+2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
+
+ Backport from mainline
+ 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
+
+ * opcode/s390.h (enum s390_opcode_cpu_val): Add
+ S390_OPCODE_ARCH13.
+
+gas/ChangeLog:
+
+2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
+
+ Backport from mainline
+ 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
+
+ * config/tc-s390.c (s390_parse_cpu): New entry for arch13.
+ * doc/c-s390.texi: Document arch13 march option.
+ * testsuite/gas/s390/s390.exp: Run the arch13 related tests.
+ * testsuite/gas/s390/zarch-arch13.d: New test.
+ * testsuite/gas/s390/zarch-arch13.s: New test.
+ * testsuite/gas/s390/zarch-z13.d: Expect the renamed mnemonics
+ also for z13.
+
+diff --git a/include/opcode/s390.h b/include/opcode/s390.h
+--- a/include/opcode/s390.h
++++ b/include/opcode/s390.h
+@@ -43,6 +43,7 @@ enum s390_opcode_cpu_val
+ S390_OPCODE_ZEC12,
+ S390_OPCODE_Z13,
+ S390_OPCODE_ARCH12,
++ S390_OPCODE_ARCH13,
+ S390_OPCODE_MAXCPU
+ };
+
+diff --git a/opcodes/s390-mkopc.c b/opcodes/s390-mkopc.c
+--- a/opcodes/s390-mkopc.c
++++ b/opcodes/s390-mkopc.c
+@@ -377,6 +377,8 @@ main (void)
+ else if (strcmp (cpu_string, "z14") == 0
+ || strcmp (cpu_string, "arch12") == 0)
+ min_cpu = S390_OPCODE_ARCH12;
++ else if (strcmp (cpu_string, "arch13") == 0)
++ min_cpu = S390_OPCODE_ARCH13;
+ else {
+ fprintf (stderr, "Couldn't parse cpu string %s\n", cpu_string);
+ exit (1);
+diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c
+--- a/opcodes/s390-opc.c
++++ b/opcodes/s390-opc.c
+@@ -359,6 +359,7 @@ const struct s390_operand s390_operands[] =
+ #define INSTR_RRF_RURR2 4, { R_24,R_16,R_28,U4_20,0,0 } /* e.g. lptea */
+ #define INSTR_RRF_R0RR 4, { R_24,R_16,R_28,0,0,0 } /* e.g. idte */
+ #define INSTR_RRF_R0RR2 4, { R_24,R_28,R_16,0,0,0 } /* e.g. ark */
++#define INSTR_RRF_R0RR3 4, { R_24,R_28,R_16,0,0,0 } /* e.g. selrz */
+ #define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. fidbr */
+ #define INSTR_RRF_U0FEFE 4, { FE_24,U4_16,FE_28,0,0,0 } /* e.g. fixbr */
+ #define INSTR_RRF_U0RF 4, { R_24,U4_16,F_28,0,0,0 } /* e.g. cfebr */
+@@ -513,6 +514,7 @@ const struct s390_operand s390_operands[] =
+ #define INSTR_VRR_VV0U0U 6, { V_8,V_12,U4_32,U4_24,0,0 } /* e.g. vistr */
+ #define INSTR_VRR_0VV0U 6, { V_12,V_16,U4_24,0,0,0 } /* e.g. vcp */
+ #define INSTR_VRR_RV0U 6, { R_8,V_12,U4_24,0,0,0 } /* e.g. vcvb */
++#define INSTR_VRR_RV0UU 6, { R_8,V_12,U4_24,U4_28,0,0 } /* e.g. vcvb */
+ #define INSTR_VSI_URDV 6, { V_32,D_20,B_16,U8_8,0,0 } /* e.g. vlrl */
+
+ #define MASK_E { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
+@@ -578,6 +580,7 @@ const struct s390_operand s390_operands[] =
+ #define MASK_RRF_RURR2 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
+ #define MASK_RRF_R0RR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
+ #define MASK_RRF_R0RR2 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
++#define MASK_RRF_R0RR3 { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
+ #define MASK_RRF_U0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
+ #define MASK_RRF_U0FEFE { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
+ #define MASK_RRF_U0RF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
+@@ -732,6 +735,7 @@ const struct s390_operand s390_operands[] =
+ #define MASK_VRR_VV0U0U { 0xff, 0x00, 0xff, 0x0f, 0x00, 0xff }
+ #define MASK_VRR_0VV0U { 0xff, 0xf0, 0x0f, 0x0f, 0xf0, 0xff }
+ #define MASK_VRR_RV0U { 0xff, 0x00, 0xff, 0x0f, 0xf0, 0xff }
++#define MASK_VRR_RV0UU { 0xff, 0x00, 0xff, 0x00, 0xf0, 0xff }
+ #define MASK_VSI_URDV { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+
+
+diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt
+--- a/opcodes/s390-opc.txt
++++ b/opcodes/s390-opc.txt
+@@ -1887,3 +1887,107 @@ e70000000006 vl VRX_VRRDU "vector memory load" arch12 zarch optparm
+ e70000000036 vlm VRS_VVRDU "vector load multiple" arch12 zarch optparm
+ e7000000000e vst VRX_VRRDU "vector store" arch12 zarch optparm
+ e7000000003e vstm VRS_VVRDU "vector store multiple" arch12 zarch optparm
++
++# arch13 instructions
++
++b9f5 ncrk RRF_R0RR2 " " arch13 zarch
++b9e5 ncgrk RRF_R0RR2 " " arch13 zarch
++e50a mvcrl SSE_RDRD " " arch13 zarch
++b974 nnrk RRF_R0RR2 " " arch13 zarch
++b964 nngrk RRF_R0RR2 " " arch13 zarch
++b976 nork RRF_R0RR2 " " arch13 zarch
++b966 nogrk RRF_R0RR2 " " arch13 zarch
++b977 nxrk RRF_R0RR2 " " arch13 zarch
++b967 nxgrk RRF_R0RR2 " " arch13 zarch
++b975 ocrk RRF_R0RR2 " " arch13 zarch
++b965 ocgrk RRF_R0RR2 " " arch13 zarch
++b9e1 popcnt RRF_U0RR " " arch13 zarch optparm
++b9f0 selr RRF_RURR " " arch13 zarch
++b9f00000 selr*20 RRF_R0RR3 " " arch13 zarch
++b9e3 selgr RRF_RURR " " arch13 zarch
++b9e30000 selgr*20 RRF_R0RR3 " " arch13 zarch
++b9c0 selhhhr RRF_RURR " " arch13 zarch
++b9c00000 selhhhr*20 RRF_R0RR3 " " arch13 zarch
++
++e60000000006 vlbr VRX_VRRDU " " arch13 zarch
++e60000001006 vlbrh VRX_VRRD " " arch13 zarch
++e60000002006 vlbrf VRX_VRRD " " arch13 zarch
++e60000003006 vlbrg VRX_VRRD " " arch13 zarch
++e60000004006 vlbrq VRX_VRRD " " arch13 zarch
++
++e60000000007 vler VRX_VRRDU " " arch13 zarch
++e60000001007 vlerh VRX_VRRD " " arch13 zarch
++e60000002007 vlerf VRX_VRRD " " arch13 zarch
++e60000003007 vlerg VRX_VRRD " " arch13 zarch
++
++e60000000004 vllebrz VRX_VRRDU " " arch13 zarch
++e60000001004 vllebrzh VRX_VRRD " " arch13 zarch
++e60000002004 vllebrzf VRX_VRRD " " arch13 zarch
++e60000003004 ldrv VRX_VRRD " " arch13 zarch
++e60000003004 vllebrzg VRX_VRRD " " arch13 zarch
++e60000006004 lerv VRX_VRRD " " arch13 zarch
++e60000006004 vllebrze VRX_VRRD " " arch13 zarch
++
++e60000000001 vlebrh VRX_VRRDU " " arch13 zarch
++e60000000003 vlebrf VRX_VRRDU " " arch13 zarch
++e60000000002 vlebrg VRX_VRRDU " " arch13 zarch
++
++e60000000005 vlbrrep VRX_VRRDU " " arch13 zarch
++e60000001005 vlbrreph VRX_VRRD " " arch13 zarch
++e60000002005 vlbrrepf VRX_VRRD " " arch13 zarch
++e60000003005 vlbrrepg VRX_VRRD " " arch13 zarch
++
++e6000000000e vstbr VRX_VRRDU " " arch13 zarch
++e6000000100e vstbrh VRX_VRRD " " arch13 zarch
++e6000000200e vstbrf VRX_VRRD " " arch13 zarch
++e6000000300e vstbrg VRX_VRRD " " arch13 zarch
++e6000000400e vstbrq VRX_VRRD " " arch13 zarch
++
++e6000000000f vster VRX_VRRDU " " arch13 zarch
++e6000000100f vsterh VRX_VRRD " " arch13 zarch
++e6000000200f vsterf VRX_VRRD " " arch13 zarch
++e6000000300f vsterg VRX_VRRD " " arch13 zarch
++
++e60000000009 vstebrh VRX_VRRDU " " arch13 zarch
++e6000000000b vstebrf VRX_VRRDU " " arch13 zarch
++e6000000000b sterv VRX_VRRD " " arch13 zarch
++e6000000000a vstebrg VRX_VRRDU " " arch13 zarch
++e6000000000a stdrv VRX_VRRD " " arch13 zarch
++
++e70000000086 vsld VRI_VVV0U " " arch13 zarch
++e70000000087 vsrd VRI_VVV0U " " arch13 zarch
++
++e7000000008b vstrs VRR_VVVUU0V " " arch13 zarch optparm
++
++e7000000008b vstrsb VRR_VVVU0VB " " arch13 zarch optparm
++e7000100008b vstrsh VRR_VVVU0VB " " arch13 zarch optparm
++e7000200008b vstrsf VRR_VVVU0VB " " arch13 zarch optparm
++
++e7000020008b vstrszb VRR_VVVU0VB2 " " arch13 zarch optparm
++e7000120008b vstrszh VRR_VVVU0VB2 " " arch13 zarch optparm
++e7000220008b vstrszf VRR_VVVU0VB2 " " arch13 zarch optparm
++
++e700000000c3 vcfps VRR_VV0UUU " " arch13 zarch
++e700000020c3 vcefb VRR_VV0UU " " arch13 zarch
++e700000820c3 wcefb VRR_VV0UU8 " " arch13 zarch
++
++e700000000c1 vcfpl VRR_VV0UUU " " arch13 zarch
++e700000020c1 vcelfb VRR_VV0UU " " arch13 zarch
++e700000820c1 wcelfb VRR_VV0UU8 " " arch13 zarch
++
++e700000000c2 vcsfp VRR_VV0UUU " " arch13 zarch
++e700000020c2 vcfeb VRR_VV0UU " " arch13 zarch
++e700000820c2 wcfeb VRR_VV0UU8 " " arch13 zarch
++
++e700000000c0 vclfp VRR_VV0UUU " " arch13 zarch
++e700000020c0 vclfeb VRR_VV0UU " " arch13 zarch
++e700000820c0 wclfeb VRR_VV0UU8 " " arch13 zarch
++
++b939 dfltcc RRF_R0RR2 " " arch13 zarch
++
++b938 sortl RRE_RR " " arch13 zarch
++
++e60000000050 vcvb VRR_RV0UU " " arch13 zarch optparm
++e60000000052 vcvbg VRR_RV0UU " " arch13 zarch optparm
++
++b93a kdsa RRE_RR " " arch13 zarch
diff --git a/SOURCES/gdb-rhbz1768593-s390x-arch13-03.patch b/SOURCES/gdb-rhbz1768593-s390x-arch13-03.patch
new file mode 100644
index 0000000..60861a6
--- /dev/null
+++ b/SOURCES/gdb-rhbz1768593-s390x-arch13-03.patch
@@ -0,0 +1,241 @@
+From FEDORA_PATCHES Mon Sep 17 00:00:00 2001
+From: Sergio Durigan Junior <sergiodj@redhat.com>
+Date: Tue, 7 Jan 2020 21:08:22 -0500
+Subject: gdb-rhbz1768593-s390x-arch13-03.patch
+
+;; Fix 'GDB needs s390x arch13 binutils patches'
+;; RHBZ 1768593, Andreas Krebbel
+
+S/390: arch13: Add instruction descriptions
+
+opcodes/ChangeLog:
+
+2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
+
+ * s390-opc.txt: Add instruction descriptions.
+
+diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt
+--- a/opcodes/s390-opc.txt
++++ b/opcodes/s390-opc.txt
+@@ -1888,106 +1888,120 @@ e70000000036 vlm VRS_VVRDU "vector load multiple" arch12 zarch optparm
+ e7000000000e vst VRX_VRRDU "vector store" arch12 zarch optparm
+ e7000000003e vstm VRS_VVRDU "vector store multiple" arch12 zarch optparm
+
++
+ # arch13 instructions
+
+-b9f5 ncrk RRF_R0RR2 " " arch13 zarch
+-b9e5 ncgrk RRF_R0RR2 " " arch13 zarch
+-e50a mvcrl SSE_RDRD " " arch13 zarch
+-b974 nnrk RRF_R0RR2 " " arch13 zarch
+-b964 nngrk RRF_R0RR2 " " arch13 zarch
+-b976 nork RRF_R0RR2 " " arch13 zarch
+-b966 nogrk RRF_R0RR2 " " arch13 zarch
+-b977 nxrk RRF_R0RR2 " " arch13 zarch
+-b967 nxgrk RRF_R0RR2 " " arch13 zarch
+-b975 ocrk RRF_R0RR2 " " arch13 zarch
+-b965 ocgrk RRF_R0RR2 " " arch13 zarch
+-b9e1 popcnt RRF_U0RR " " arch13 zarch optparm
+-b9f0 selr RRF_RURR " " arch13 zarch
+-b9f00000 selr*20 RRF_R0RR3 " " arch13 zarch
+-b9e3 selgr RRF_RURR " " arch13 zarch
+-b9e30000 selgr*20 RRF_R0RR3 " " arch13 zarch
+-b9c0 selhhhr RRF_RURR " " arch13 zarch
+-b9c00000 selhhhr*20 RRF_R0RR3 " " arch13 zarch
+-
+-e60000000006 vlbr VRX_VRRDU " " arch13 zarch
+-e60000001006 vlbrh VRX_VRRD " " arch13 zarch
+-e60000002006 vlbrf VRX_VRRD " " arch13 zarch
+-e60000003006 vlbrg VRX_VRRD " " arch13 zarch
+-e60000004006 vlbrq VRX_VRRD " " arch13 zarch
+-
+-e60000000007 vler VRX_VRRDU " " arch13 zarch
+-e60000001007 vlerh VRX_VRRD " " arch13 zarch
+-e60000002007 vlerf VRX_VRRD " " arch13 zarch
+-e60000003007 vlerg VRX_VRRD " " arch13 zarch
+-
+-e60000000004 vllebrz VRX_VRRDU " " arch13 zarch
+-e60000001004 vllebrzh VRX_VRRD " " arch13 zarch
+-e60000002004 vllebrzf VRX_VRRD " " arch13 zarch
+-e60000003004 ldrv VRX_VRRD " " arch13 zarch
+-e60000003004 vllebrzg VRX_VRRD " " arch13 zarch
+-e60000006004 lerv VRX_VRRD " " arch13 zarch
+-e60000006004 vllebrze VRX_VRRD " " arch13 zarch
+-
+-e60000000001 vlebrh VRX_VRRDU " " arch13 zarch
+-e60000000003 vlebrf VRX_VRRDU " " arch13 zarch
+-e60000000002 vlebrg VRX_VRRDU " " arch13 zarch
+-
+-e60000000005 vlbrrep VRX_VRRDU " " arch13 zarch
+-e60000001005 vlbrreph VRX_VRRD " " arch13 zarch
+-e60000002005 vlbrrepf VRX_VRRD " " arch13 zarch
+-e60000003005 vlbrrepg VRX_VRRD " " arch13 zarch
+-
+-e6000000000e vstbr VRX_VRRDU " " arch13 zarch
+-e6000000100e vstbrh VRX_VRRD " " arch13 zarch
+-e6000000200e vstbrf VRX_VRRD " " arch13 zarch
+-e6000000300e vstbrg VRX_VRRD " " arch13 zarch
+-e6000000400e vstbrq VRX_VRRD " " arch13 zarch
+-
+-e6000000000f vster VRX_VRRDU " " arch13 zarch
+-e6000000100f vsterh VRX_VRRD " " arch13 zarch
+-e6000000200f vsterf VRX_VRRD " " arch13 zarch
+-e6000000300f vsterg VRX_VRRD " " arch13 zarch
+-
+-e60000000009 vstebrh VRX_VRRDU " " arch13 zarch
+-e6000000000b vstebrf VRX_VRRDU " " arch13 zarch
+-e6000000000b sterv VRX_VRRD " " arch13 zarch
+-e6000000000a vstebrg VRX_VRRDU " " arch13 zarch
+-e6000000000a stdrv VRX_VRRD " " arch13 zarch
+-
+-e70000000086 vsld VRI_VVV0U " " arch13 zarch
+-e70000000087 vsrd VRI_VVV0U " " arch13 zarch
+-
+-e7000000008b vstrs VRR_VVVUU0V " " arch13 zarch optparm
+-
+-e7000000008b vstrsb VRR_VVVU0VB " " arch13 zarch optparm
+-e7000100008b vstrsh VRR_VVVU0VB " " arch13 zarch optparm
+-e7000200008b vstrsf VRR_VVVU0VB " " arch13 zarch optparm
+-
+-e7000020008b vstrszb VRR_VVVU0VB2 " " arch13 zarch optparm
+-e7000120008b vstrszh VRR_VVVU0VB2 " " arch13 zarch optparm
+-e7000220008b vstrszf VRR_VVVU0VB2 " " arch13 zarch optparm
+-
+-e700000000c3 vcfps VRR_VV0UUU " " arch13 zarch
+-e700000020c3 vcefb VRR_VV0UU " " arch13 zarch
+-e700000820c3 wcefb VRR_VV0UU8 " " arch13 zarch
+-
+-e700000000c1 vcfpl VRR_VV0UUU " " arch13 zarch
+-e700000020c1 vcelfb VRR_VV0UU " " arch13 zarch
+-e700000820c1 wcelfb VRR_VV0UU8 " " arch13 zarch
+-
+-e700000000c2 vcsfp VRR_VV0UUU " " arch13 zarch
+-e700000020c2 vcfeb VRR_VV0UU " " arch13 zarch
+-e700000820c2 wcfeb VRR_VV0UU8 " " arch13 zarch
+-
+-e700000000c0 vclfp VRR_VV0UUU " " arch13 zarch
+-e700000020c0 vclfeb VRR_VV0UU " " arch13 zarch
+-e700000820c0 wclfeb VRR_VV0UU8 " " arch13 zarch
+-
+-b939 dfltcc RRF_R0RR2 " " arch13 zarch
+-
+-b938 sortl RRE_RR " " arch13 zarch
+-
+-e60000000050 vcvb VRR_RV0UU " " arch13 zarch optparm
+-e60000000052 vcvbg VRR_RV0UU " " arch13 zarch optparm
+-
+-b93a kdsa RRE_RR " " arch13 zarch
++
++# Miscellaneous Instruction Extensions Facility 2
++
++b9f5 ncrk RRF_R0RR2 "and with complement 32 bit" arch13 zarch
++b9e5 ncgrk RRF_R0RR2 "and with complement 64 bit" arch13 zarch
++e50a mvcrl SSE_RDRD "move right to left" arch13 zarch
++b974 nnrk RRF_R0RR2 "nand 32 bit" arch13 zarch
++b964 nngrk RRF_R0RR2 "nand 64 bit" arch13 zarch
++b976 nork RRF_R0RR2 "nor 32 bit" arch13 zarch
++b966 nogrk RRF_R0RR2 "nor 64 bit" arch13 zarch
++b977 nxrk RRF_R0RR2 "not exclusive or 32 bit" arch13 zarch
++b967 nxgrk RRF_R0RR2 "not exclusive or 64 bit" arch13 zarch
++b975 ocrk RRF_R0RR2 "or with complement 32 bit" arch13 zarch
++b965 ocgrk RRF_R0RR2 "or with complement 64 bit" arch13 zarch
++b9e1 popcnt RRF_U0RR "population count arch13" arch13 zarch optparm
++b9f0 selr RRF_RURR "select 32 bit" arch13 zarch
++b9f00000 selr*20 RRF_R0RR3 "select 32 bit" arch13 zarch
++b9e3 selgr RRF_RURR "select 64 bit" arch13 zarch
++b9e30000 selgr*20 RRF_R0RR3 "select 64 bit" arch13 zarch
++b9c0 selfhr RRF_RURR "select high" arch13 zarch
++b9c00000 selfhr*20 RRF_R0RR3 "select high" arch13 zarch
++
++# Vector Enhancements Facility 2
++
++e60000000006 vlbr VRX_VRRDU "vector load byte reversed elements" arch13 zarch
++e60000001006 vlbrh VRX_VRRD "vector load byte reversed halfword elements" arch13 zarch
++e60000002006 vlbrf VRX_VRRD "vector load byte reversed word elements" arch13 zarch
++e60000003006 vlbrg VRX_VRRD "vector load byte reversed doubleword elements" arch13 zarch
++e60000004006 vlbrq VRX_VRRD "vector load byte reversed quadword elements" arch13 zarch
++
++e60000000007 vler VRX_VRRDU "vector load elements reversed" arch13 zarch
++e60000001007 vlerh VRX_VRRD "vector load halfword elements reversed" arch13 zarch
++e60000002007 vlerf VRX_VRRD "vector load word elements reversed" arch13 zarch
++e60000003007 vlerg VRX_VRRD "vector load doubleword elements reversed" arch13 zarch
++
++e60000000004 vllebrz VRX_VRRDU "vector load byte reversed element and zero" arch13 zarch
++e60000001004 vllebrzh VRX_VRRD "vector load byte reversed halfword element and zero" arch13 zarch
++e60000002004 vllebrzf VRX_VRRD "vector load byte reversed word element and zero" arch13 zarch
++e60000003004 ldrv VRX_VRRD "load byte reversed doubleword" arch13 zarch
++e60000003004 vllebrzg VRX_VRRD "vector load byte reversed doubleword element and zero" arch13 zarch
++e60000006004 lerv VRX_VRRD "load byte reversed word" arch13 zarch
++e60000006004 vllebrze VRX_VRRD "vector load byte reversed word element left-aligned and zero" arch13 zarch
++
++e60000000001 vlebrh VRX_VRRDU "vector load byte reversed halfword element" arch13 zarch
++e60000000003 vlebrf VRX_VRRDU "vector load byte reversed word element" arch13 zarch
++e60000000002 vlebrg VRX_VRRDU "vector load byte reversed doubleword element" arch13 zarch
++
++e60000000005 vlbrrep VRX_VRRDU "vector load byte reversed element and replicate" arch13 zarch
++e60000001005 vlbrreph VRX_VRRD "vector load byte reversed halfword element and replicate" arch13 zarch
++e60000002005 vlbrrepf VRX_VRRD "vector load byte reversed word element and replicate" arch13 zarch
++e60000003005 vlbrrepg VRX_VRRD "vector load byte reversed doubleword element and replicate" arch13 zarch
++
++e6000000000e vstbr VRX_VRRDU "vector store byte reversed elements" arch13 zarch
++e6000000100e vstbrh VRX_VRRD "vector store byte reversed halfword elements" arch13 zarch
++e6000000200e vstbrf VRX_VRRD "vector store byte reversed word elements" arch13 zarch
++e6000000300e vstbrg VRX_VRRD "vector store byte reversed doubleword elements" arch13 zarch
++e6000000400e vstbrq VRX_VRRD "vector store byte reversed quadword elements" arch13 zarch
++
++e6000000000f vster VRX_VRRDU "vector store elements reversed" arch13 zarch
++e6000000100f vsterh VRX_VRRD "vector store halfword elements reversed" arch13 zarch
++e6000000200f vsterf VRX_VRRD "vector store word elements reversed" arch13 zarch
++e6000000300f vsterg VRX_VRRD "vector store doubleword elements reversed" arch13 zarch
++
++e60000000009 vstebrh VRX_VRRDU "vector store byte reversed halfword element" arch13 zarch
++e6000000000b vstebrf VRX_VRRDU "vector store byte reversed word element" arch13 zarch
++e6000000000b sterv VRX_VRRD "store byte reversed word" arch13 zarch
++e6000000000a vstebrg VRX_VRRDU "vector store byte reversed doubleword element" arch13 zarch
++e6000000000a stdrv VRX_VRRD "store byte reversed doubleword" arch13 zarch
++
++e70000000086 vsld VRI_VVV0U "vector shift left double by bit" arch13 zarch
++e70000000087 vsrd VRI_VVV0U "vector shift right double by bit" arch13 zarch
++
++e7000000008b vstrs VRR_VVVUU0V "vector string search" arch13 zarch optparm
++
++e7000000008b vstrsb VRR_VVVU0VB "vector string search byte" arch13 zarch optparm
++e7000100008b vstrsh VRR_VVVU0VB "vector string search halfword" arch13 zarch optparm
++e7000200008b vstrsf VRR_VVVU0VB "vector string search word" arch13 zarch optparm
++
++e7000020008b vstrszb VRR_VVV0V "vector string search byte zero" arch13 zarch
++e7000120008b vstrszh VRR_VVV0V "vector string search halfword zero" arch13 zarch
++e7000220008b vstrszf VRR_VVV0V "vector string search word zero" arch13 zarch
++
++e700000000c3 vcfps VRR_VV0UUU "vector fp convert from fixed" arch13 zarch
++e700000020c3 vcefb VRR_VV0UU "vector fp convert from fixed 32 bit" arch13 zarch
++e700000820c3 wcefb VRR_VV0UU8 "vector fp convert from fixed 32 bit" arch13 zarch
++
++e700000000c1 vcfpl VRR_VV0UUU "vector fp convert from logical" arch13 zarch
++e700000020c1 vcelfb VRR_VV0UU "vector fp convert from logical 32 bit" arch13 zarch
++e700000820c1 wcelfb VRR_VV0UU8 "vector fp convert from logical 32 bit" arch13 zarch
++
++e700000000c2 vcsfp VRR_VV0UUU "vector fp convert to fixed" arch13 zarch
++e700000020c2 vcfeb VRR_VV0UU "vector fp convert to fixed 32 bit" arch13 zarch
++e700000820c2 wcfeb VRR_VV0UU8 "vector fp convert to fixed 32 bit" arch13 zarch
++
++e700000000c0 vclfp VRR_VV0UUU "vector fp convert to logical" arch13 zarch
++e700000020c0 vclfeb VRR_VV0UU "vector fp convert to logical 32 bit" arch13 zarch
++e700000820c0 wclfeb VRR_VV0UU8 "vector fp convert to logical 32 bit" arch13 zarch
++
++# Deflate conversion facility
++
++b939 dfltcc RRF_R0RR2 "deflate conversion call" arch13 zarch
++
++# Enhanced-Sort Facility
++
++b938 sortl RRE_RR "sort lists" arch13 zarch
++
++# Vector packed decimal enhancement facility
++
++e60000000050 vcvb VRR_RV0UU "vector convert to binary 32 bit" arch13 zarch optparm
++e60000000052 vcvbg VRR_RV0UU "vector convert to binary 64 bit" arch13 zarch optparm
++
++# Message Security Assist Extension 9
++
++b93a kdsa RRE_RR "compute digital signature authentication" arch13 zarch
diff --git a/SPECS/gdb.spec b/SPECS/gdb.spec
index 30139f8..41ef67d 100644
--- a/SPECS/gdb.spec
+++ b/SPECS/gdb.spec
@@ -26,7 +26,7 @@ Version: 8.2
# The release always contains a leading reserved number, start it at 1.
# `upstream' is not a part of `name' to stay fully rpm dependencies compatible for the testing.
-Release: 8%{?dist}
+Release: 12%{?dist}
License: GPLv3+ and GPLv3+ with exceptions and GPLv2+ and GPLv2+ with exceptions and GPL+ and LGPLv2+ and LGPLv3+ and BSD and Public Domain and GFDL
Group: Development/Debuggers
@@ -1034,6 +1034,19 @@ fi
%endif
%changelog
+* Tue May 12 2020 Keith Seitz <keiths@redhat.com> - 8.2-12.el8
+- Include support for z15 record/replay (RH BZ 1659535)
+
+* Thu Jan 23 2020 Sergio Durigan Junior <sergiodj@redhat.com> - 8.2-11.el8
+- Revert previous change (RH BZ 1786466).
+
+* Thu Jan 16 2020 Sergio Durigan Junior <sergiodj@redhat.com> - 8.2-10.el8
+- Do not build i686 RPMs. Make the x86_64 RPMs Obsoletes/Provides
+ previous i686 RPMs (RH BZ 1786466).
+
+* Wed Jan 8 2020 Sergio Durigan Junior <sergiodj@redhat.com> - 8.2-9.el8
+- Implement s390x arch13 support (Andreas Krebbel, RH BZ 1768593).
+
* Tue Oct 22 2019 Keith Seitz <keiths@redhat.com> - 8.2-8.el8
- Fix buffer overflow reading sections with invalid sizes
(Keith Seitz, RH BZ 1742099)