commit 6dca4fd141fd0b9fe0ea662295833b8ed43cb4e8
Author: Anton Blanchard <anton@samba.org>
Date:   Tue Sep 22 15:39:24 2015 +1000

    opcodes/ppc-opc.c: Add dscr and ctrl SPR mnemonics
    
    opcodes/
            * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.

### a/opcodes/ChangeLog
### b/opcodes/ChangeLog
## -1,3 +1,7 @@
+2015-09-22  Anton Blanchard  <anton@samba.org>
+
+	* ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
+
 2015-08-25  Jose E. Marchesi  <jose.marchesi@oracle.com>
 
 	* sparc-dis.c (print_insn_sparc): Handle the privileged register
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -4878,6 +4878,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"mfdec",	XSPR(31,339,  6), XSPR_MASK, MFDEC1,	PPCNONE,	{RT}},
 {"mflr",	XSPR(31,339,  8), XSPR_MASK, COM|PPCVLE, PPCNONE,	{RT}},
 {"mfctr",	XSPR(31,339,  9), XSPR_MASK, COM|PPCVLE, PPCNONE,	{RT}},
+{"mfdscr",	XSPR(31,339, 17), XSPR_MASK, POWER6,	PPCNONE,	{RT}},
 {"mftid",	XSPR(31,339, 17), XSPR_MASK, POWER,	PPCNONE,	{RT}},
 {"mfdsisr",	XSPR(31,339, 18), XSPR_MASK, COM,	TITAN,  	{RT}},
 {"mfdar",	XSPR(31,339, 19), XSPR_MASK, COM,	TITAN,  	{RT}},
@@ -4893,6 +4894,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"mfdear",	XSPR(31,339, 61), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,	{RT}},
 {"mfesr",	XSPR(31,339, 62), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,	{RT}},
 {"mfivpr",	XSPR(31,339, 63), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,	{RT}},
+{"mfctrl",	XSPR(31,339,136), XSPR_MASK, POWER4,	PPCNONE,	{RT}},
 {"mfcmpa",	XSPR(31,339,144), XSPR_MASK, PPC860,	PPCNONE,	{RT}},
 {"mfcmpb",	XSPR(31,339,145), XSPR_MASK, PPC860,	PPCNONE,	{RT}},
 {"mfcmpc",	XSPR(31,339,146), XSPR_MASK, PPC860,	PPCNONE,	{RT}},
@@ -5216,6 +5218,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"mtxer",	XSPR(31,467,  1), XSPR_MASK, COM|PPCVLE, PPCNONE,	{RS}},
 {"mtlr",	XSPR(31,467,  8), XSPR_MASK, COM|PPCVLE, PPCNONE,	{RS}},
 {"mtctr", 	XSPR(31,467,  9), XSPR_MASK, COM|PPCVLE, PPCNONE,	{RS}},
+{"mtdscr",	XSPR(31,467, 17), XSPR_MASK, POWER6,	PPCNONE,	{RS}},
 {"mttid",	XSPR(31,467, 17), XSPR_MASK, POWER,	PPCNONE,	{RS}},
 {"mtdsisr",	XSPR(31,467, 18), XSPR_MASK, COM,	TITAN,  	{RS}},
 {"mtdar",	XSPR(31,467, 19), XSPR_MASK, COM,	TITAN,  	{RS}},
@@ -5242,6 +5245,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"mtder",	XSPR(31,467,149), XSPR_MASK, PPC860,	PPCNONE,	{RS}},
 {"mtcounta",	XSPR(31,467,150), XSPR_MASK, PPC860,	PPCNONE,	{RS}},
 {"mtcountb",	XSPR(31,467,151), XSPR_MASK, PPC860,	PPCNONE,	{RS}},
+{"mtctrl",	XSPR(31,467,152), XSPR_MASK, POWER4,	PPCNONE,	{RS}},
 {"mtcmpe",	XSPR(31,467,152), XSPR_MASK, PPC860,	PPCNONE,	{RS}},
 {"mtcmpf",	XSPR(31,467,153), XSPR_MASK, PPC860,	PPCNONE,	{RS}},
 {"mtcmpg",	XSPR(31,467,154), XSPR_MASK, PPC860,	PPCNONE,	{RS}},