Blame SOURCES/gdb-rhbz1553104-s390x-arch12-1of6.patch

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commit 3b78cfe1033fafa6ca36c69cf8587c1bd96996ca
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Author: Andreas Krebbel <krebbel@linux.vnet.ibm.com>
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Date:   Mon Apr 27 10:29:16 2015 +0200
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    S/390: Fixes for z13 instructions.
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    opcodes/
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            * s390-opc.c: New instruction type VV0UU2.
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            * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
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            and WFC.
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    gas/testsuite/
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            * gas/s390/zarch-z13.d: Fix tests for VFCE, VLDE, VFSQ, WFK, and
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            WFC.
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            * gas/s390/zarch-z13.s: Likewise.
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### a/opcodes/ChangeLog
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### b/opcodes/ChangeLog
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## -1,3 +1,9 @@
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+2015-04-27  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
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+
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+	* s390-opc.c: New instruction type VV0UU2.
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+	* s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
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+	and WFC.
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+
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 2015-04-23  Jan Beulich  <jbeulich@suse.com>
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 	* i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
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--- a/opcodes/s390-opc.c
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+++ b/opcodes/s390-opc.c
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@@ -484,6 +484,7 @@ const struct s390_operand s390_operands[] =
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 #define INSTR_VRR_VV0U     6, { V_8,V_12,U4_32,0,0,0 }           /* e.g. vseg  */
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 #define INSTR_VRR_VV0U2    6, { V_8,V_12,U4_24,0,0,0 }           /* e.g. vistrb*/
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 #define INSTR_VRR_VV0UU    6, { V_8,V_12,U4_28,U4_24,0,0 }       /* e.g. vcdgb */
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+#define INSTR_VRR_VV0UU2   6, { V_8,V_12,U4_32,U4_28,0,0 }       /* e.g. wfc */
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 #define INSTR_VRR_VV0UU8   6, { V_8,V_12,U4_OR8_28,U4_24,0,0 }   /* e.g. wcdgb */
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 #define INSTR_VRR_VV       6, { V_8,V_12,0,0,0,0 }               /* e.g. vsegb */
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 #define INSTR_VRR_VVVUU0V  6, { V_8,V_12,V_16,V_32,U4_20,U4_24 } /* e.g. vstrc */
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@@ -690,6 +691,7 @@ const struct s390_operand s390_operands[] =
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 #define MASK_VRR_VV0U     { 0xff, 0x00, 0xff, 0xff, 0x00, 0xff }
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 #define MASK_VRR_VV0U2    { 0xff, 0x00, 0xff, 0x0f, 0xf0, 0xff }
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 #define MASK_VRR_VV0UU    { 0xff, 0x00, 0xff, 0x00, 0xf0, 0xff }
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+#define MASK_VRR_VV0UU2   { 0xff, 0x00, 0xff, 0xf0, 0x00, 0xff }
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 #define MASK_VRR_VV0UU8   { 0xff, 0x00, 0xff, 0x08, 0xf0, 0xff }
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 #define MASK_VRR_VV       { 0xff, 0x00, 0xff, 0xff, 0xf0, 0xff }
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 #define MASK_VRR_VVVUU0V  { 0xff, 0x00, 0x00, 0x0f, 0x00, 0xff }
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--- a/opcodes/s390-opc.txt
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+++ b/opcodes/s390-opc.txt
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@@ -1586,11 +1586,11 @@ e7000230008a vstrczfs VRR_VVVU0VB3 "vector string range compare word" z13 zarch
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 e700000000e3 vfa VRR_VVV0UU "vector fp add" z13 zarch
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 e700000030e3 vfadb VRR_VVV "vector fp add" z13 zarch
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 e700000830e3 wfadb VRR_VVV "vector fp add" z13 zarch
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-e700000000cb wfc VRR_VV0UU "vector fp compare scalar" z13 zarch
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+e700000000cb wfc VRR_VV0UU2 "vector fp compare scalar" z13 zarch
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 e700000030cb wfcdb VRR_VV "vector fp compare scalar" z13 zarch
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-e700000000ca wfk VRR_VV0UU "vector fp compare and signal scalar" z13 zarch
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+e700000000ca wfk VRR_VV0UU2 "vector fp compare and signal scalar" z13 zarch
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 e700000030ca wfkdb VRR_VV "vector fp compare and signal scalar" z13 zarch
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-e700000000e8 vfce VRR_VVV "vector fp compare equal" z13 zarch
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+e700000000e8 vfce VRR_VVV0UUU "vector fp compare equal" z13 zarch
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 e700000030e8 vfcedb VRR_VVV "vector fp compare equal" z13 zarch
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 e700001030e8 vfcedbs VRR_VVV "vector fp compare equal" z13 zarch
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 e700000830e8 wfcedb VRR_VVV "vector fp compare equal" z13 zarch
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@@ -1623,7 +1623,7 @@ e700000830e5 wfddb VRR_VVV "vector fp divide" z13 zarch
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 e700000000c7 vfi VRR_VV0UUU "vector load fp integer" z13 zarch
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 e700000030c7 vfidb VRR_VV0UU "vector load fp integer" z13 zarch
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 e700000830c7 wfidb VRR_VV0UU8 "vector load fp integer" z13 zarch
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-e700000000c4 vlde VRR_VV0UU "vector fp load lengthened" z13 zarch
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+e700000000c4 vlde VRR_VV0UU2 "vector fp load lengthened" z13 zarch
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 e700000020c4 vldeb VRR_VV "vector fp load lengthened" z13 zarch
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 e700000820c4 wldeb VRR_VV "vector fp load lengthened" z13 zarch
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 e700000000c5 vled VRR_VV0UUU "vector fp load rounded" z13 zarch
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@@ -1647,7 +1647,7 @@ e700001030cc vflndb VRR_VV "vector fp perform sign operation" z13 zarch
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 e700001830cc wflndb VRR_VV "vector fp perform sign operation" z13 zarch
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 e700002030cc vflpdb VRR_VV "vector fp perform sign operation" z13 zarch
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 e700002830cc wflpdb VRR_VV "vector fp perform sign operation" z13 zarch
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-e700000000ce vfsq VRR_VV0UU "vector fp square root" z13 zarch
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+e700000000ce vfsq VRR_VV0UU2 "vector fp square root" z13 zarch
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 e700000030ce vfsqdb VRR_VV "vector fp square root" z13 zarch
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 e700000830ce wfsqdb VRR_VV "vector fp square root" z13 zarch
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 e700000000e2 vfs VRR_VVV0UU "vector fp subtract" z13 zarch