Blame SOURCES/gdb-rhbz1480498-power-record-1of3.patch

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commit d44c67f38178c5ad0c083ebff6429d6e477ea42e
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Author: Edjunior Barbosa Machado <emachado@linux.vnet.ibm.com>
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Date:   Thu Aug 18 10:45:12 2016 -0300
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    ppc: Fix record of HTM instructions
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    The patch fixes the record support of Hardware Transactional Memory
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    instructions on Power. It also solves a large number of unexpected failures
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    from gdb.reverse testcases sigall-precsave.exp and sigall-reverse.exp that
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    occur on distros which glibc uses HTM instructions.
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    gdb/ChangeLog
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    2016-08-18  Edjunior Barbosa Machado  <emachado@linux.vnet.ibm.com>
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            * rs6000-tdep.c (ppc_process_record_op31): Handle HTM instructions.
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### a/gdb/ChangeLog
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### b/gdb/ChangeLog
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## -1,3 +1,7 @@
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+2016-08-18  Edjunior Barbosa Machado  <emachado@linux.vnet.ibm.com>
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+
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+	* rs6000-tdep.c (ppc_process_record_op31): Handle HTM instructions.
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+
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 2016-08-17  Simon Marchi  <simon.marchi@ericsson.com>
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 	* inferior.c (remove_inferior_command): Fix error message.
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--- a/gdb/rs6000-tdep.c
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+++ b/gdb/rs6000-tdep.c
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@@ -4613,17 +4613,17 @@ ppc_process_record_op31 (struct gdbarch *gdbarch, struct regcache *regcache,
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     case 654:		/* Transaction Begin */
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     case 686:		/* Transaction End */
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-    case 718:		/* Transaction Check */
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     case 750:		/* Transaction Suspend or Resume */
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     case 782:		/* Transaction Abort Word Conditional */
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     case 814:		/* Transaction Abort Doubleword Conditional */
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     case 846:		/* Transaction Abort Word Conditional Immediate */
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     case 878:		/* Transaction Abort Doubleword Conditional Immediate */
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     case 910:		/* Transaction Abort */
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-      fprintf_unfiltered (gdb_stdlog, "Cannot record Transaction instructions. "
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-			  "%08x at %s, 31-%d.\n",
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-			  insn, paddress (gdbarch, addr), ext);
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-      return -1;
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+      record_full_arch_list_add_reg (regcache, tdep->ppc_ps_regnum);
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+      /* FALL-THROUGH */
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+    case 718:		/* Transaction Check */
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+      record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
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+      return 0;
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     case 1014:		/* Data Cache Block set to Zero */
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       if (target_auxv_search (&current_target, AT_DCACHEBSIZE, &at_dcsz) <= 0