Blame SOURCES/gdb-rhbz1320945-power9-37of38.patch

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commit dce75bf9848c88583377c608e9734a2f8616d12b
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Author: Nicholas Piggin <npiggin@gmail.com>
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Date:   Fri Feb 10 14:18:23 2017 +1000
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    POWER9 add scv/rfscv instruction support
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    opcodes/
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            * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
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    gas/
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            * testsuite/gas/ppc/power9.d <scv, rfscv>: New tests.
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### a/opcodes/ChangeLog
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### b/opcodes/ChangeLog
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## -1,3 +1,7 @@
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+2017-02-10  Nicholas Piggin  <npiggin@gmail.com>
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+
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+	* ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
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+
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 2017-02-03  Nick Clifton  <nickc@redhat.com>
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 	PR 21096
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--- a/opcodes/ppc-opc.c
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+++ b/opcodes/ppc-opc.c
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@@ -441,7 +441,7 @@ const struct powerpc_operand powerpc_operands[] =
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 #define L2OPT L32OPT + 1
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   { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
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-  /* The LEV field in a POWER SVC form instruction.  */
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+  /* The LEV field in a POWER SVC / POWER9 SCV form instruction.  */
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 #define SVC_LEV L2OPT + 1
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   { 0x7f, 5, NULL, NULL, 0 },
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@@ -4142,6 +4142,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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 {"bcla",	B(16,1,1),	B_MASK,	     COM,	PPCVLE,		{BO, BI, BDA}},
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 {"svc",		SC(17,0,0),	SC_MASK,     POWER,	PPCVLE,		{SVC_LEV, FL1, FL2}},
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+{"scv",		SC(17,0,1),	SC_MASK,     POWER9,	PPCVLE,		{SVC_LEV}},
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 {"svcl",	SC(17,0,1),	SC_MASK,     POWER,	PPCVLE,		{SVC_LEV, FL1, FL2}},
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 {"sc",		SC(17,1,0),	SC_MASK,     PPC,	PPCVLE,		{LEV}},
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 {"svca",	SC(17,1,0),	SC_MASK,     PWRCOM,	PPCVLE,		{SV}},
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@@ -4391,6 +4392,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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 {"rfi",		XL(19,50),	0xffffffff,  COM,	PPCVLE,		{0}},
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 {"rfci",	XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300|PPCA2|PPC476, PPCVLE, {0}},
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+{"rfscv",	XL(19,82),	0xffffffff,  POWER9,	PPCVLE,		{0}},
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 {"rfsvc",	XL(19,82),	0xffffffff,  POWER,	PPCVLE,		{0}},
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 {"rfgi",	XL(19,102),   0xffffffff, E500MC|PPCA2,	PPCVLE,		{0}},