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commit 6ec2b213de6962ceeb81bfa33354ea6e60c57049
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Author: Edjunior Barbosa Machado <emachado@linux.vnet.ibm.com>
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Date: Wed Sep 21 13:30:39 2016 -0300
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ppc: Add Power ISA 3.0/POWER9 instructions record support
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gdb/ChangeLog:
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2016-09-21 Edjunior Barbosa Machado <emachado@linux.vnet.ibm.com>
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* rs6000-tdep.c (PPC_DQ): New macro.
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(ppc_process_record_op4): Add Power ISA 3.0 instructions.
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(ppc_process_record_op19): Likewise.
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(ppc_process_record_op31): Likewise.
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(ppc_process_record_op59): Likewise.
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(ppc_process_record_op60): Likewise.
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(ppc_process_record_op63): Likewise.
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(ppc_process_record): Likewise.
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(ppc_process_record_op61): New function.
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### a/gdb/ChangeLog
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### b/gdb/ChangeLog
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## -1,3 +1,15 @@
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+2016-09-21 Edjunior Barbosa Machado <emachado@linux.vnet.ibm.com>
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+
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+ * rs6000-tdep.c (PPC_DQ): New macro.
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+ (ppc_process_record_op4): Add Power ISA 3.0 instructions.
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+ (ppc_process_record_op19): Likewise.
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+ (ppc_process_record_op31): Likewise.
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+ (ppc_process_record_op59): Likewise.
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+ (ppc_process_record_op60): Likewise.
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+ (ppc_process_record_op63): Likewise.
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+ (ppc_process_record): Likewise.
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+ (ppc_process_record_op61): New function.
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+
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2016-09-21 Yao Qi <yao.qi@linaro.org>
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* aarch32-linux-nat.c (aarch32_gp_regcache_collect): Keep
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Index: gdb-7.6.1/gdb/rs6000-tdep.c
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===================================================================
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--- gdb-7.6.1.orig/gdb/rs6000-tdep.c 2017-03-19 00:08:32.893569127 +0100
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+++ gdb-7.6.1/gdb/rs6000-tdep.c 2017-03-19 00:08:49.775687752 +0100
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@@ -3721,6 +3721,7 @@
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#define PPC_T(insn) PPC_FIELD (insn, 6, 5)
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#define PPC_D(insn) PPC_SEXT (PPC_FIELD (insn, 16, 16), 16)
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#define PPC_DS(insn) PPC_SEXT (PPC_FIELD (insn, 16, 14), 14)
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+#define PPC_DQ(insn) PPC_SEXT (PPC_FIELD (insn, 16, 12), 12)
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#define PPC_BIT(insn,n) ((insn & (1 << (31 - (n)))) ? 1 : 0)
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#define PPC_OE(insn) PPC_BIT (insn, 21)
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#define PPC_RC(insn) PPC_BIT (insn, 31)
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@@ -3768,6 +3769,7 @@
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{
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struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
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int ext = PPC_FIELD (insn, 21, 11);
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+ int vra = PPC_FIELD (insn, 11, 5);
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switch (ext & 0x3f)
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{
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@@ -3779,6 +3781,7 @@
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/* FALL-THROUGH */
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case 42: /* Vector Select */
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case 43: /* Vector Permute */
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+ case 59: /* Vector Permute Right-indexed */
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case 44: /* Vector Shift Left Double by Octet Immediate */
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case 45: /* Vector Permute and Exclusive-OR */
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case 60: /* Vector Add Extended Unsigned Quadword Modulo */
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@@ -3786,6 +3789,7 @@
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case 62: /* Vector Subtract Extended Unsigned Quadword Modulo */
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case 63: /* Vector Subtract Extended & write Carry Unsigned Quadword */
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case 34: /* Vector Multiply-Low-Add Unsigned Halfword Modulo */
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+ case 35: /* Vector Multiply-Sum Unsigned Doubleword Modulo */
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case 36: /* Vector Multiply-Sum Unsigned Byte Modulo */
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case 37: /* Vector Multiply-Sum Mixed Byte Modulo */
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case 38: /* Vector Multiply-Sum Unsigned Halfword Modulo */
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@@ -3795,14 +3799,37 @@
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record_full_arch_list_add_reg (regcache,
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tdep->ppc_vr0_regnum + PPC_VRT (insn));
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return 0;
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+
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+ case 48: /* Multiply-Add High Doubleword */
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+ case 49: /* Multiply-Add High Doubleword Unsigned */
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+ case 51: /* Multiply-Add Low Doubleword */
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+ record_full_arch_list_add_reg (regcache,
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+ tdep->ppc_gp0_regnum + PPC_RT (insn));
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+ return 0;
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}
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switch ((ext & 0x1ff))
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{
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+ case 385:
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+ if (vra != 0 /* Decimal Convert To Signed Quadword */
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+ && vra != 2 /* Decimal Convert From Signed Quadword */
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+ && vra != 4 /* Decimal Convert To Zoned */
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+ && vra != 5 /* Decimal Convert To National */
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+ && vra != 6 /* Decimal Convert From Zoned */
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+ && vra != 7 /* Decimal Convert From National */
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+ && vra != 31) /* Decimal Set Sign */
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+ break;
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/* 5.16 Decimal Integer Arithmetic Instructions */
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case 1: /* Decimal Add Modulo */
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case 65: /* Decimal Subtract Modulo */
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+ case 193: /* Decimal Shift */
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+ case 129: /* Decimal Unsigned Shift */
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+ case 449: /* Decimal Shift and Round */
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+
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+ case 257: /* Decimal Truncate */
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+ case 321: /* Decimal Unsigned Truncate */
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+
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/* Bit-21 should be set. */
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if (!PPC_BIT (insn, 21))
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break;
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@@ -3832,6 +3859,12 @@
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case 198: /* Vector Compare Equal To Single-Precision */
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case 454: /* Vector Compare Greater Than or Equal To Single-Precision */
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case 710: /* Vector Compare Greater Than Single-Precision */
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+ case 7: /* Vector Compare Not Equal Byte */
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+ case 71: /* Vector Compare Not Equal Halfword */
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+ case 135: /* Vector Compare Not Equal Word */
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+ case 263: /* Vector Compare Not Equal or Zero Byte */
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+ case 327: /* Vector Compare Not Equal or Zero Halfword */
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+ case 391: /* Vector Compare Not Equal or Zero Word */
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if (PPC_Rc (insn))
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record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
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record_full_arch_list_add_reg (regcache,
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@@ -3839,6 +3872,38 @@
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return 0;
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}
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+ if (ext == 1538)
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+ {
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+ switch (vra)
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+ {
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+ case 0: /* Vector Count Leading Zero Least-Significant Bits
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+ Byte */
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+ case 1: /* Vector Count Trailing Zero Least-Significant Bits
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+ Byte */
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+ record_full_arch_list_add_reg (regcache,
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+ tdep->ppc_gp0_regnum + PPC_RT (insn));
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+ return 0;
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+
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+ case 6: /* Vector Negate Word */
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+ case 7: /* Vector Negate Doubleword */
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+ case 8: /* Vector Parity Byte Word */
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+ case 9: /* Vector Parity Byte Doubleword */
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+ case 10: /* Vector Parity Byte Quadword */
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+ case 16: /* Vector Extend Sign Byte To Word */
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+ case 17: /* Vector Extend Sign Halfword To Word */
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+ case 24: /* Vector Extend Sign Byte To Doubleword */
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+ case 25: /* Vector Extend Sign Halfword To Doubleword */
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+ case 26: /* Vector Extend Sign Word To Doubleword */
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+ case 28: /* Vector Count Trailing Zeros Byte */
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+ case 29: /* Vector Count Trailing Zeros Halfword */
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+ case 30: /* Vector Count Trailing Zeros Word */
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+ case 31: /* Vector Count Trailing Zeros Doubleword */
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+ record_full_arch_list_add_reg (regcache,
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+ tdep->ppc_vr0_regnum + PPC_VRT (insn));
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+ return 0;
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+ }
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+ }
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+
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switch (ext)
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{
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case 142: /* Vector Pack Unsigned Halfword Unsigned Saturate */
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@@ -4010,10 +4075,44 @@
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case 1923: /* Vector Population Count Word */
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case 1987: /* Vector Population Count Doubleword */
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case 1356: /* Vector Bit Permute Quadword */
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+ case 1484: /* Vector Bit Permute Doubleword */
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+ case 513: /* Vector Multiply-by-10 Unsigned Quadword */
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+ case 1: /* Vector Multiply-by-10 & write Carry Unsigned
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+ Quadword */
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+ case 577: /* Vector Multiply-by-10 Extended Unsigned Quadword */
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+ case 65: /* Vector Multiply-by-10 Extended & write Carry
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+ Unsigned Quadword */
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+ case 1027: /* Vector Absolute Difference Unsigned Byte */
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+ case 1091: /* Vector Absolute Difference Unsigned Halfword */
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+ case 1155: /* Vector Absolute Difference Unsigned Word */
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+ case 1796: /* Vector Shift Right Variable */
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+ case 1860: /* Vector Shift Left Variable */
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+ case 133: /* Vector Rotate Left Word then Mask Insert */
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+ case 197: /* Vector Rotate Left Doubleword then Mask Insert */
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+ case 389: /* Vector Rotate Left Word then AND with Mask */
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+ case 453: /* Vector Rotate Left Doubleword then AND with Mask */
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+ case 525: /* Vector Extract Unsigned Byte */
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+ case 589: /* Vector Extract Unsigned Halfword */
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+ case 653: /* Vector Extract Unsigned Word */
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+ case 717: /* Vector Extract Doubleword */
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+ case 781: /* Vector Insert Byte */
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+ case 845: /* Vector Insert Halfword */
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+ case 909: /* Vector Insert Word */
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+ case 973: /* Vector Insert Doubleword */
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record_full_arch_list_add_reg (regcache,
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tdep->ppc_vr0_regnum + PPC_VRT (insn));
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return 0;
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+ case 1549: /* Vector Extract Unsigned Byte Left-Indexed */
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+ case 1613: /* Vector Extract Unsigned Halfword Left-Indexed */
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+ case 1677: /* Vector Extract Unsigned Word Left-Indexed */
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+ case 1805: /* Vector Extract Unsigned Byte Right-Indexed */
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+ case 1869: /* Vector Extract Unsigned Halfword Right-Indexed */
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+ case 1933: /* Vector Extract Unsigned Word Right-Indexed */
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+ record_full_arch_list_add_reg (regcache,
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+ tdep->ppc_gp0_regnum + PPC_RT (insn));
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+ return 0;
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+
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case 1604: /* Move To Vector Status and Control Register */
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record_full_arch_list_add_reg (regcache, PPC_VSCR_REGNUM);
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return 0;
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@@ -4021,6 +4120,11 @@
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record_full_arch_list_add_reg (regcache,
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tdep->ppc_vr0_regnum + PPC_VRT (insn));
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return 0;
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+ case 833: /* Decimal Copy Sign */
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+ record_full_arch_list_add_reg (regcache,
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+ tdep->ppc_vr0_regnum + PPC_VRT (insn));
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+ record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
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+ return 0;
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}
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fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x "
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@@ -4038,6 +4142,14 @@
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struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
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int ext = PPC_EXTOP (insn);
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+ switch (ext & 0x01f)
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+ {
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+ case 2: /* Add PC Immediate Shifted */
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+ record_full_arch_list_add_reg (regcache,
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+ tdep->ppc_gp0_regnum + PPC_RT (insn));
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+ return 0;
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+ }
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+
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switch (ext)
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{
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case 0: /* Move Condition Register Field */
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@@ -4143,6 +4255,15 @@
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return 0;
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}
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+ if ((ext & 0xff) == 170)
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+ {
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+ /* Add Extended using alternate carry bits */
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+ record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum);
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+ record_full_arch_list_add_reg (regcache,
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+ tdep->ppc_gp0_regnum + PPC_RT (insn));
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+ return 0;
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+ }
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+
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switch (ext)
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{
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case 78: /* Determine Leftmost Zero Byte */
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@@ -4161,6 +4282,9 @@
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case 302: /* Move From Branch History Rolling Buffer */
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case 339: /* Move From Special Purpose Register */
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case 371: /* Move From Time Base [Phased-Out] */
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+ case 309: /* Load Doubleword Monitored Indexed */
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+ case 128: /* Set Boolean */
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+ case 755: /* Deliver A Random Number */
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record_full_arch_list_add_reg (regcache,
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tdep->ppc_gp0_regnum + PPC_RT (insn));
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return 0;
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@@ -4177,6 +4301,7 @@
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case 282: /* Convert Declets To Binary Coded Decimal */
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case 314: /* Convert Binary Coded Decimal To Declets */
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case 508: /* Compare bytes */
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+ case 307: /* Move From VSR Lower Doubleword */
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record_full_arch_list_add_reg (regcache,
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tdep->ppc_gp0_regnum + PPC_RA (insn));
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return 0;
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@@ -4195,6 +4320,12 @@
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case 32: /* Compare logical */
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case 144: /* Move To Condition Register Fields */
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/* Move To One Condition Register Field */
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+ case 192: /* Compare Ranged Byte */
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+ case 224: /* Compare Equal Byte */
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+ case 576: /* Move XER to CR Extended */
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a094f6 |
+ case 902: /* Paste (should always fail due to single-stepping and
|
|
|
a094f6 |
+ the memory location might not be accessible, so
|
|
|
a094f6 |
+ record only CR) */
|
|
|
a094f6 |
record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
|
|
|
a094f6 |
return 0;
|
|
|
a094f6 |
|
|
|
a094f6 |
@@ -4221,6 +4352,12 @@
|
|
|
a094f6 |
case 790: /* Load Halfword Byte-Reverse Indexed */
|
|
|
a094f6 |
case 534: /* Load Word Byte-Reverse Indexed */
|
|
|
a094f6 |
case 532: /* Load Doubleword Byte-Reverse Indexed */
|
|
|
a094f6 |
+ case 582: /* Load Word Atomic */
|
|
|
a094f6 |
+ case 614: /* Load Doubleword Atomic */
|
|
|
a094f6 |
+ case 265: /* Modulo Unsigned Doubleword */
|
|
|
a094f6 |
+ case 777: /* Modulo Signed Doubleword */
|
|
|
a094f6 |
+ case 267: /* Modulo Unsigned Word */
|
|
|
a094f6 |
+ case 779: /* Modulo Signed Word */
|
|
|
a094f6 |
record_full_arch_list_add_reg (regcache,
|
|
|
a094f6 |
tdep->ppc_gp0_regnum + PPC_RT (insn));
|
|
|
a094f6 |
return 0;
|
|
|
a094f6 |
@@ -4299,6 +4436,16 @@
|
|
|
a094f6 |
case 844: /* Load VSX Vector Doubleword*2 Indexed */
|
|
|
a094f6 |
case 332: /* Load VSX Vector Doubleword & Splat Indexed */
|
|
|
a094f6 |
case 780: /* Load VSX Vector Word*4 Indexed */
|
|
|
a094f6 |
+ case 268: /* Load VSX Vector Indexed */
|
|
|
a094f6 |
+ case 364: /* Load VSX Vector Word & Splat Indexed */
|
|
|
a094f6 |
+ case 812: /* Load VSX Vector Halfword*8 Indexed */
|
|
|
a094f6 |
+ case 876: /* Load VSX Vector Byte*16 Indexed */
|
|
|
a094f6 |
+ case 269: /* Load VSX Vector with Length */
|
|
|
a094f6 |
+ case 301: /* Load VSX Vector Left-justified with Length */
|
|
|
a094f6 |
+ case 781: /* Load VSX Scalar as Integer Byte & Zero Indexed */
|
|
|
a094f6 |
+ case 813: /* Load VSX Scalar as Integer Halfword & Zero Indexed */
|
|
|
a094f6 |
+ case 403: /* Move To VSR Word & Splat */
|
|
|
a094f6 |
+ case 435: /* Move To VSR Double Doubleword */
|
|
|
a094f6 |
ppc_record_vsr (regcache, tdep, PPC_XT (insn));
|
|
|
a094f6 |
return 0;
|
|
|
a094f6 |
|
|
|
a094f6 |
@@ -4320,6 +4467,10 @@
|
|
|
a094f6 |
case 922: /* Extend Sign Halfword */
|
|
|
a094f6 |
case 954: /* Extend Sign Byte */
|
|
|
a094f6 |
case 986: /* Extend Sign Word */
|
|
|
a094f6 |
+ case 538: /* Count Trailing Zeros Word */
|
|
|
a094f6 |
+ case 570: /* Count Trailing Zeros Doubleword */
|
|
|
a094f6 |
+ case 890: /* Extend-Sign Word and Shift Left Immediate (445) */
|
|
|
a094f6 |
+ case 890 | 1: /* Extend-Sign Word and Shift Left Immediate (445) */
|
|
|
a094f6 |
if (PPC_RC (insn))
|
|
|
a094f6 |
record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
|
|
|
a094f6 |
record_full_arch_list_add_reg (regcache,
|
|
|
a094f6 |
@@ -4362,6 +4513,11 @@
|
|
|
a094f6 |
case 727: /* Store Floating-Point Double Indexed */
|
|
|
a094f6 |
case 919: /* Store Floating-Point Double Pair Indexed */
|
|
|
a094f6 |
case 983: /* Store Floating-Point as Integer Word Indexed */
|
|
|
a094f6 |
+ case 396: /* Store VSX Vector Indexed */
|
|
|
a094f6 |
+ case 940: /* Store VSX Vector Halfword*8 Indexed */
|
|
|
a094f6 |
+ case 1004: /* Store VSX Vector Byte*16 Indexed */
|
|
|
a094f6 |
+ case 909: /* Store VSX Scalar as Integer Byte Indexed */
|
|
|
a094f6 |
+ case 941: /* Store VSX Scalar as Integer Halfword Indexed */
|
|
|
a094f6 |
if (ext == 694 || ext == 726 || ext == 150 || ext == 214 || ext == 182)
|
|
|
a094f6 |
record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
|
|
|
a094f6 |
|
|
|
a094f6 |
@@ -4391,6 +4547,7 @@
|
|
|
a094f6 |
case 135: /* Store Vector Element Byte Indexed */
|
|
|
a094f6 |
case 215: /* Store Byte Indexed */
|
|
|
a094f6 |
case 694: /* Store Byte Conditional Indexed */
|
|
|
a094f6 |
+ case 909: /* Store VSX Scalar as Integer Byte Indexed */
|
|
|
a094f6 |
size = 1;
|
|
|
a094f6 |
break;
|
|
|
a094f6 |
case 439: /* Store Halfword with Update Indexed */
|
|
|
a094f6 |
@@ -4398,6 +4555,7 @@
|
|
|
a094f6 |
case 407: /* Store Halfword Indexed */
|
|
|
a094f6 |
case 726: /* Store Halfword Conditional Indexed */
|
|
|
a094f6 |
case 918: /* Store Halfword Byte-Reverse Indexed */
|
|
|
a094f6 |
+ case 941: /* Store VSX Scalar as Integer Halfword Indexed */
|
|
|
a094f6 |
size = 2;
|
|
|
a094f6 |
break;
|
|
|
a094f6 |
case 181: /* Store Doubleword with Update Indexed */
|
|
|
a094f6 |
@@ -4415,6 +4573,9 @@
|
|
|
a094f6 |
case 231: /* Store Vector Indexed */
|
|
|
a094f6 |
case 487: /* Store Vector Indexed LRU */
|
|
|
a094f6 |
case 919: /* Store Floating-Point Double Pair Indexed */
|
|
|
a094f6 |
+ case 396: /* Store VSX Vector Indexed */
|
|
|
a094f6 |
+ case 940: /* Store VSX Vector Halfword*8 Indexed */
|
|
|
a094f6 |
+ case 1004: /* Store VSX Vector Byte*16 Indexed */
|
|
|
a094f6 |
size = 16;
|
|
|
a094f6 |
break;
|
|
|
a094f6 |
default:
|
|
|
a094f6 |
@@ -4442,6 +4603,38 @@
|
|
|
a094f6 |
return -1;
|
|
|
a094f6 |
return 0;
|
|
|
a094f6 |
|
|
|
a094f6 |
+ case 397: /* Store VSX Vector with Length */
|
|
|
a094f6 |
+ case 429: /* Store VSX Vector Left-justified with Length */
|
|
|
a094f6 |
+ if (PPC_RA (insn) != 0)
|
|
|
a094f6 |
+ regcache_raw_read_unsigned (regcache,
|
|
|
a094f6 |
+ tdep->ppc_gp0_regnum + PPC_RA (insn), &ea);
|
|
|
a094f6 |
+ regcache_raw_read_unsigned (regcache,
|
|
|
a094f6 |
+ tdep->ppc_gp0_regnum + PPC_RB (insn), &rb);
|
|
|
a094f6 |
+ /* Store up to 16 bytes. */
|
|
|
a094f6 |
+ nb = (rb & 0xff) > 16 ? 16 : (rb & 0xff);
|
|
|
a094f6 |
+ if (nb > 0)
|
|
|
a094f6 |
+ record_full_arch_list_add_mem (ea, nb);
|
|
|
a094f6 |
+ return 0;
|
|
|
a094f6 |
+
|
|
|
a094f6 |
+ case 710: /* Store Word Atomic */
|
|
|
a094f6 |
+ case 742: /* Store Doubleword Atomic */
|
|
|
a094f6 |
+ if (PPC_RA (insn) != 0)
|
|
|
a094f6 |
+ regcache_raw_read_unsigned (regcache,
|
|
|
a094f6 |
+ tdep->ppc_gp0_regnum + PPC_RA (insn), &ea);
|
|
|
a094f6 |
+ switch (ext)
|
|
|
a094f6 |
+ {
|
|
|
a094f6 |
+ case 710: /* Store Word Atomic */
|
|
|
a094f6 |
+ size = 8;
|
|
|
a094f6 |
+ break;
|
|
|
a094f6 |
+ case 742: /* Store Doubleword Atomic */
|
|
|
a094f6 |
+ size = 16;
|
|
|
a094f6 |
+ break;
|
|
|
a094f6 |
+ default:
|
|
|
a094f6 |
+ gdb_assert (0);
|
|
|
a094f6 |
+ }
|
|
|
a094f6 |
+ record_full_arch_list_add_mem (ea, size);
|
|
|
a094f6 |
+ return 0;
|
|
|
a094f6 |
+
|
|
|
a094f6 |
case 725: /* Store String Word Immediate */
|
|
|
a094f6 |
ra = 0;
|
|
|
a094f6 |
if (PPC_RA (insn) != 0)
|
|
|
a094f6 |
@@ -4509,6 +4702,7 @@
|
|
|
a094f6 |
case 430: /* Clear BHRB */
|
|
|
a094f6 |
case 598: /* Synchronize */
|
|
|
a094f6 |
case 62: /* Wait for Interrupt */
|
|
|
a094f6 |
+ case 30: /* Wait */
|
|
|
a094f6 |
case 22: /* Instruction Cache Block Touch */
|
|
|
a094f6 |
case 854: /* Enforce In-order Execution of I/O */
|
|
|
a094f6 |
case 246: /* Data Cache Block Touch for Store */
|
|
|
a094f6 |
@@ -4517,6 +4711,8 @@
|
|
|
a094f6 |
case 278: /* Data Cache Block Touch */
|
|
|
a094f6 |
case 758: /* Data Cache Block Allocate */
|
|
|
a094f6 |
case 982: /* Instruction Cache Block Invalidate */
|
|
|
a094f6 |
+ case 774: /* Copy */
|
|
|
a094f6 |
+ case 838: /* CP_Abort */
|
|
|
a094f6 |
return 0;
|
|
|
a094f6 |
|
|
|
a094f6 |
case 654: /* Transaction Begin */
|
|
|
a094f6 |
@@ -4617,6 +4813,7 @@
|
|
|
a094f6 |
case 226: /* DFP Test Data Group */
|
|
|
a094f6 |
case 642: /* DFP Compare Unordered */
|
|
|
a094f6 |
case 674: /* DFP Test Significance */
|
|
|
a094f6 |
+ case 675: /* DFP Test Significance Immediate */
|
|
|
a094f6 |
record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
|
|
|
a094f6 |
record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
|
|
|
a094f6 |
return 0;
|
|
|
a094f6 |
@@ -4716,7 +4913,16 @@
|
|
|
a094f6 |
case 217: /* ditto */
|
|
|
a094f6 |
case 104: /* VSX Vector Subtract Double-Precision */
|
|
|
a094f6 |
case 72: /* VSX Vector Subtract Single-Precision */
|
|
|
a094f6 |
+ case 128: /* VSX Scalar Maximum Type-C Double-Precision */
|
|
|
a094f6 |
+ case 136: /* VSX Scalar Minimum Type-C Double-Precision */
|
|
|
a094f6 |
+ case 144: /* VSX Scalar Maximum Type-J Double-Precision */
|
|
|
a094f6 |
+ case 152: /* VSX Scalar Minimum Type-J Double-Precision */
|
|
|
a094f6 |
+ case 3: /* VSX Scalar Compare Equal Double-Precision */
|
|
|
a094f6 |
+ case 11: /* VSX Scalar Compare Greater Than Double-Precision */
|
|
|
a094f6 |
+ case 19: /* VSX Scalar Compare Greater Than or Equal
|
|
|
a094f6 |
+ Double-Precision */
|
|
|
a094f6 |
record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
|
|
|
a094f6 |
+ /* FALL-THROUGH */
|
|
|
a094f6 |
case 240: /* VSX Vector Copy Sign Double-Precision */
|
|
|
a094f6 |
case 208: /* VSX Vector Copy Sign Single-Precision */
|
|
|
a094f6 |
case 130: /* VSX Logical AND */
|
|
|
a094f6 |
@@ -4737,6 +4943,14 @@
|
|
|
a094f6 |
case 2 | 0x20: /* VSX Shift Left Double by Word Immediate (SHW=1) */
|
|
|
a094f6 |
case 2 | 0x40: /* VSX Shift Left Double by Word Immediate (SHW=2) */
|
|
|
a094f6 |
case 2 | 0x60: /* VSX Shift Left Double by Word Immediate (SHW=3) */
|
|
|
a094f6 |
+ case 216: /* VSX Vector Insert Exponent Single-Precision */
|
|
|
a094f6 |
+ case 248: /* VSX Vector Insert Exponent Double-Precision */
|
|
|
a094f6 |
+ case 26: /* VSX Vector Permute */
|
|
|
a094f6 |
+ case 58: /* VSX Vector Permute Right-indexed */
|
|
|
a094f6 |
+ case 213: /* VSX Vector Test Data Class Single-Precision (DC=0) */
|
|
|
a094f6 |
+ case 213 | 0x8: /* VSX Vector Test Data Class Single-Precision (DC=1) */
|
|
|
a094f6 |
+ case 245: /* VSX Vector Test Data Class Double-Precision (DC=0) */
|
|
|
a094f6 |
+ case 245 | 0x8: /* VSX Vector Test Data Class Double-Precision (DC=1) */
|
|
|
a094f6 |
ppc_record_vsr (regcache, tdep, PPC_XT (insn));
|
|
|
a094f6 |
return 0;
|
|
|
a094f6 |
|
|
|
a094f6 |
@@ -4748,6 +4962,7 @@
|
|
|
a094f6 |
|
|
|
a094f6 |
case 35: /* VSX Scalar Compare Unordered Double-Precision */
|
|
|
a094f6 |
case 43: /* VSX Scalar Compare Ordered Double-Precision */
|
|
|
a094f6 |
+ case 59: /* VSX Scalar Compare Exponents Double-Precision */
|
|
|
a094f6 |
record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
|
|
|
a094f6 |
record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
|
|
|
a094f6 |
return 0;
|
|
|
a094f6 |
@@ -4894,6 +5109,7 @@
|
|
|
a094f6 |
case 203: /* VSX Vector Square Root Double-Precision */
|
|
|
a094f6 |
case 139: /* VSX Vector Square Root Single-Precision */
|
|
|
a094f6 |
record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
|
|
|
a094f6 |
+ /* FALL-THROUGH */
|
|
|
a094f6 |
case 345: /* VSX Scalar Absolute Value Double-Precision */
|
|
|
a094f6 |
case 267: /* VSX Scalar Convert Scalar Single-Precision to
|
|
|
a094f6 |
Vector Single-Precision format Non-signalling */
|
|
|
a094f6 |
@@ -4908,9 +5124,15 @@
|
|
|
a094f6 |
case 505: /* VSX Vector Negate Double-Precision */
|
|
|
a094f6 |
case 441: /* VSX Vector Negate Single-Precision */
|
|
|
a094f6 |
case 164: /* VSX Splat Word */
|
|
|
a094f6 |
+ case 165: /* VSX Vector Extract Unsigned Word */
|
|
|
a094f6 |
+ case 181: /* VSX Vector Insert Word */
|
|
|
a094f6 |
ppc_record_vsr (regcache, tdep, PPC_XT (insn));
|
|
|
a094f6 |
return 0;
|
|
|
a094f6 |
|
|
|
a094f6 |
+ case 298: /* VSX Scalar Test Data Class Single-Precision */
|
|
|
a094f6 |
+ case 362: /* VSX Scalar Test Data Class Double-Precision */
|
|
|
a094f6 |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
|
|
|
a094f6 |
+ /* FALL-THROUGH */
|
|
|
a094f6 |
case 106: /* VSX Scalar Test for software Square Root
|
|
|
a094f6 |
Double-Precision */
|
|
|
a094f6 |
case 234: /* VSX Vector Test for software Square Root
|
|
|
a094f6 |
@@ -4919,6 +5141,60 @@
|
|
|
a094f6 |
Single-Precision */
|
|
|
a094f6 |
record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
|
|
|
a094f6 |
return 0;
|
|
|
a094f6 |
+
|
|
|
a094f6 |
+ case 347:
|
|
|
a094f6 |
+ switch (PPC_FIELD (insn, 11, 5))
|
|
|
a094f6 |
+ {
|
|
|
a094f6 |
+ case 0: /* VSX Scalar Extract Exponent Double-Precision */
|
|
|
a094f6 |
+ case 1: /* VSX Scalar Extract Significand Double-Precision */
|
|
|
a094f6 |
+ record_full_arch_list_add_reg (regcache,
|
|
|
a094f6 |
+ tdep->ppc_gp0_regnum + PPC_RT (insn));
|
|
|
a094f6 |
+ return 0;
|
|
|
a094f6 |
+ case 16: /* VSX Scalar Convert Half-Precision format to
|
|
|
a094f6 |
+ Double-Precision format */
|
|
|
a094f6 |
+ case 17: /* VSX Scalar round & Convert Double-Precision format
|
|
|
a094f6 |
+ to Half-Precision format */
|
|
|
a094f6 |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
|
|
|
a094f6 |
+ ppc_record_vsr (regcache, tdep, PPC_XT (insn));
|
|
|
a094f6 |
+ return 0;
|
|
|
a094f6 |
+ }
|
|
|
a094f6 |
+ break;
|
|
|
a094f6 |
+
|
|
|
a094f6 |
+ case 475:
|
|
|
a094f6 |
+ switch (PPC_FIELD (insn, 11, 5))
|
|
|
a094f6 |
+ {
|
|
|
a094f6 |
+ case 24: /* VSX Vector Convert Half-Precision format to
|
|
|
a094f6 |
+ Single-Precision format */
|
|
|
a094f6 |
+ case 25: /* VSX Vector round and Convert Single-Precision format
|
|
|
a094f6 |
+ to Half-Precision format */
|
|
|
a094f6 |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
|
|
|
a094f6 |
+ /* FALL-THROUGH */
|
|
|
a094f6 |
+ case 0: /* VSX Vector Extract Exponent Double-Precision */
|
|
|
a094f6 |
+ case 1: /* VSX Vector Extract Significand Double-Precision */
|
|
|
a094f6 |
+ case 7: /* VSX Vector Byte-Reverse Halfword */
|
|
|
a094f6 |
+ case 8: /* VSX Vector Extract Exponent Single-Precision */
|
|
|
a094f6 |
+ case 9: /* VSX Vector Extract Significand Single-Precision */
|
|
|
a094f6 |
+ case 15: /* VSX Vector Byte-Reverse Word */
|
|
|
a094f6 |
+ case 23: /* VSX Vector Byte-Reverse Doubleword */
|
|
|
a094f6 |
+ case 31: /* VSX Vector Byte-Reverse Quadword */
|
|
|
a094f6 |
+ ppc_record_vsr (regcache, tdep, PPC_XT (insn));
|
|
|
a094f6 |
+ return 0;
|
|
|
a094f6 |
+ }
|
|
|
a094f6 |
+ break;
|
|
|
a094f6 |
+ }
|
|
|
a094f6 |
+
|
|
|
a094f6 |
+ switch (ext)
|
|
|
a094f6 |
+ {
|
|
|
a094f6 |
+ case 360: /* VSX Vector Splat Immediate Byte */
|
|
|
a094f6 |
+ if (PPC_FIELD (insn, 11, 2) == 0)
|
|
|
a094f6 |
+ {
|
|
|
a094f6 |
+ ppc_record_vsr (regcache, tdep, PPC_XT (insn));
|
|
|
a094f6 |
+ return 0;
|
|
|
a094f6 |
+ }
|
|
|
a094f6 |
+ break;
|
|
|
a094f6 |
+ case 918: /* VSX Scalar Insert Exponent Double-Precision */
|
|
|
a094f6 |
+ ppc_record_vsr (regcache, tdep, PPC_XT (insn));
|
|
|
a094f6 |
+ return 0;
|
|
|
a094f6 |
}
|
|
|
a094f6 |
|
|
|
a094f6 |
if (((ext >> 3) & 0x3) == 3) /* VSX Select */
|
|
|
a094f6 |
@@ -4932,6 +5208,65 @@
|
|
|
a094f6 |
return -1;
|
|
|
a094f6 |
}
|
|
|
a094f6 |
|
|
|
a094f6 |
+/* Parse and record instructions of primary opcode-61 at ADDR.
|
|
|
a094f6 |
+ Return 0 if successful. */
|
|
|
a094f6 |
+
|
|
|
a094f6 |
+static int
|
|
|
a094f6 |
+ppc_process_record_op61 (struct gdbarch *gdbarch, struct regcache *regcache,
|
|
|
a094f6 |
+ CORE_ADDR addr, uint32_t insn)
|
|
|
a094f6 |
+{
|
|
|
a094f6 |
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
|
|
|
a094f6 |
+ ULONGEST ea = 0;
|
|
|
a094f6 |
+ int size;
|
|
|
a094f6 |
+
|
|
|
a094f6 |
+ switch (insn & 0x3)
|
|
|
a094f6 |
+ {
|
|
|
a094f6 |
+ case 0: /* Store Floating-Point Double Pair */
|
|
|
a094f6 |
+ case 2: /* Store VSX Scalar Doubleword */
|
|
|
a094f6 |
+ case 3: /* Store VSX Scalar Single */
|
|
|
a094f6 |
+ if (PPC_RA (insn) != 0)
|
|
|
a094f6 |
+ regcache_raw_read_unsigned (regcache,
|
|
|
a094f6 |
+ tdep->ppc_gp0_regnum + PPC_RA (insn),
|
|
|
a094f6 |
+ &ea);
|
|
|
a094f6 |
+ ea += PPC_DS (insn) << 2;
|
|
|
a094f6 |
+ switch (insn & 0x3)
|
|
|
a094f6 |
+ {
|
|
|
a094f6 |
+ case 0: /* Store Floating-Point Double Pair */
|
|
|
a094f6 |
+ size = 16;
|
|
|
a094f6 |
+ break;
|
|
|
a094f6 |
+ case 2: /* Store VSX Scalar Doubleword */
|
|
|
a094f6 |
+ size = 8;
|
|
|
a094f6 |
+ break;
|
|
|
a094f6 |
+ case 3: /* Store VSX Scalar Single */
|
|
|
a094f6 |
+ size = 4;
|
|
|
a094f6 |
+ break;
|
|
|
a094f6 |
+ default:
|
|
|
a094f6 |
+ gdb_assert (0);
|
|
|
a094f6 |
+ }
|
|
|
a094f6 |
+ record_full_arch_list_add_mem (ea, size);
|
|
|
a094f6 |
+ return 0;
|
|
|
a094f6 |
+ }
|
|
|
a094f6 |
+
|
|
|
a094f6 |
+ switch (insn & 0x7)
|
|
|
a094f6 |
+ {
|
|
|
a094f6 |
+ case 1: /* Load VSX Vector */
|
|
|
a094f6 |
+ ppc_record_vsr (regcache, tdep, PPC_XT (insn));
|
|
|
a094f6 |
+ return 0;
|
|
|
a094f6 |
+ case 5: /* Store VSX Vector */
|
|
|
a094f6 |
+ if (PPC_RA (insn) != 0)
|
|
|
a094f6 |
+ regcache_raw_read_unsigned (regcache,
|
|
|
a094f6 |
+ tdep->ppc_gp0_regnum + PPC_RA (insn),
|
|
|
a094f6 |
+ &ea);
|
|
|
a094f6 |
+ ea += PPC_DQ (insn) << 4;
|
|
|
a094f6 |
+ record_full_arch_list_add_mem (ea, 16);
|
|
|
a094f6 |
+ return 0;
|
|
|
a094f6 |
+ }
|
|
|
a094f6 |
+
|
|
|
a094f6 |
+ fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x "
|
|
|
a094f6 |
+ "at %s.\n", insn, paddress (gdbarch, addr));
|
|
|
a094f6 |
+ return -1;
|
|
|
a094f6 |
+}
|
|
|
a094f6 |
+
|
|
|
a094f6 |
/* Parse and record instructions of primary opcode-63 at ADDR.
|
|
|
a094f6 |
Return 0 if successful. */
|
|
|
a094f6 |
|
|
|
a094f6 |
@@ -4970,6 +5305,16 @@
|
|
|
a094f6 |
record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
|
|
|
a094f6 |
}
|
|
|
a094f6 |
|
|
|
a094f6 |
+ switch (ext & 0xff)
|
|
|
a094f6 |
+ {
|
|
|
a094f6 |
+ case 5: /* VSX Scalar Round to Quad-Precision Integer */
|
|
|
a094f6 |
+ case 37: /* VSX Scalar Round Quad-Precision to Double-Extended
|
|
|
a094f6 |
+ Precision */
|
|
|
a094f6 |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
|
|
|
a094f6 |
+ ppc_record_vsr (regcache, tdep, PPC_VRT (insn) + 32);
|
|
|
a094f6 |
+ return 0;
|
|
|
a094f6 |
+ }
|
|
|
a094f6 |
+
|
|
|
a094f6 |
switch (ext)
|
|
|
a094f6 |
{
|
|
|
a094f6 |
case 2: /* DFP Add Quad */
|
|
|
a094f6 |
@@ -4999,6 +5344,7 @@
|
|
|
a094f6 |
case 226: /* DFP Test Data Group Quad */
|
|
|
a094f6 |
case 642: /* DFP Compare Unordered Quad */
|
|
|
a094f6 |
case 674: /* DFP Test Significance Quad */
|
|
|
a094f6 |
+ case 675: /* DFP Test Significance Immediate Quad */
|
|
|
a094f6 |
record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
|
|
|
a094f6 |
record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
|
|
|
a094f6 |
return 0;
|
|
|
a094f6 |
@@ -5055,7 +5401,26 @@
|
|
|
a094f6 |
record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
|
|
|
a094f6 |
return 0;
|
|
|
a094f6 |
|
|
|
a094f6 |
- case 583: /* Move From FPSCR */
|
|
|
a094f6 |
+ case 583:
|
|
|
a094f6 |
+ switch (PPC_FIELD (insn, 11, 5))
|
|
|
a094f6 |
+ {
|
|
|
a094f6 |
+ case 1: /* Move From FPSCR & Clear Enables */
|
|
|
a094f6 |
+ case 20: /* Move From FPSCR Control & set DRN */
|
|
|
a094f6 |
+ case 21: /* Move From FPSCR Control & set DRN Immediate */
|
|
|
a094f6 |
+ case 22: /* Move From FPSCR Control & set RN */
|
|
|
a094f6 |
+ case 23: /* Move From FPSCR Control & set RN Immediate */
|
|
|
a094f6 |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
|
|
|
a094f6 |
+ case 0: /* Move From FPSCR */
|
|
|
a094f6 |
+ case 24: /* Move From FPSCR Lightweight */
|
|
|
a094f6 |
+ if (PPC_FIELD (insn, 11, 5) == 0 && PPC_RC (insn))
|
|
|
a094f6 |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
|
|
|
a094f6 |
+ record_full_arch_list_add_reg (regcache,
|
|
|
a094f6 |
+ tdep->ppc_fp0_regnum
|
|
|
a094f6 |
+ + PPC_FRT (insn));
|
|
|
a094f6 |
+ return 0;
|
|
|
a094f6 |
+ }
|
|
|
a094f6 |
+ break;
|
|
|
a094f6 |
+
|
|
|
a094f6 |
case 8: /* Floating Copy Sign */
|
|
|
a094f6 |
case 40: /* Floating Negate */
|
|
|
a094f6 |
case 72: /* Floating Move Register */
|
|
|
a094f6 |
@@ -5085,6 +5450,10 @@
|
|
|
a094f6 |
case 0: /* Floating Compare Unordered */
|
|
|
a094f6 |
case 32: /* Floating Compare Ordered */
|
|
|
a094f6 |
case 64: /* Move to Condition Register from FPSCR */
|
|
|
a094f6 |
+ case 132: /* VSX Scalar Compare Ordered Quad-Precision */
|
|
|
a094f6 |
+ case 164: /* VSX Scalar Compare Exponents Quad-Precision */
|
|
|
a094f6 |
+ case 644: /* VSX Scalar Compare Unordered Quad-Precision */
|
|
|
a094f6 |
+ case 708: /* VSX Scalar Test Data Class Quad-Precision */
|
|
|
a094f6 |
record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
|
|
|
a094f6 |
/* FALL-THROUGH */
|
|
|
a094f6 |
case 128: /* Floating Test for software Divide */
|
|
|
a094f6 |
@@ -5092,10 +5461,65 @@
|
|
|
a094f6 |
record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
|
|
|
a094f6 |
return 0;
|
|
|
a094f6 |
|
|
|
a094f6 |
+ case 4: /* VSX Scalar Add Quad-Precision */
|
|
|
a094f6 |
+ case 36: /* VSX Scalar Multiply Quad-Precision */
|
|
|
a094f6 |
+ case 388: /* VSX Scalar Multiply-Add Quad-Precision */
|
|
|
a094f6 |
+ case 420: /* VSX Scalar Multiply-Subtract Quad-Precision */
|
|
|
a094f6 |
+ case 452: /* VSX Scalar Negative Multiply-Add Quad-Precision */
|
|
|
a094f6 |
+ case 484: /* VSX Scalar Negative Multiply-Subtract
|
|
|
a094f6 |
+ Quad-Precision */
|
|
|
a094f6 |
+ case 516: /* VSX Scalar Subtract Quad-Precision */
|
|
|
a094f6 |
+ case 548: /* VSX Scalar Divide Quad-Precision */
|
|
|
a094f6 |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
|
|
|
a094f6 |
+ /* FALL-THROUGH */
|
|
|
a094f6 |
+ case 100: /* VSX Scalar Copy Sign Quad-Precision */
|
|
|
a094f6 |
+ case 868: /* VSX Scalar Insert Exponent Quad-Precision */
|
|
|
a094f6 |
+ ppc_record_vsr (regcache, tdep, PPC_VRT (insn) + 32);
|
|
|
a094f6 |
+ return 0;
|
|
|
a094f6 |
+
|
|
|
a094f6 |
+ case 804:
|
|
|
a094f6 |
+ switch (PPC_FIELD (insn, 11, 5))
|
|
|
a094f6 |
+ {
|
|
|
a094f6 |
+ case 27: /* VSX Scalar Square Root Quad-Precision */
|
|
|
a094f6 |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
|
|
|
a094f6 |
+ /* FALL-THROUGH */
|
|
|
a094f6 |
+ case 0: /* VSX Scalar Absolute Quad-Precision */
|
|
|
a094f6 |
+ case 2: /* VSX Scalar Extract Exponent Quad-Precision */
|
|
|
a094f6 |
+ case 8: /* VSX Scalar Negative Absolute Quad-Precision */
|
|
|
a094f6 |
+ case 16: /* VSX Scalar Negate Quad-Precision */
|
|
|
a094f6 |
+ case 18: /* VSX Scalar Extract Significand Quad-Precision */
|
|
|
a094f6 |
+ ppc_record_vsr (regcache, tdep, PPC_VRT (insn) + 32);
|
|
|
a094f6 |
+ return 0;
|
|
|
a094f6 |
+ }
|
|
|
a094f6 |
+ break;
|
|
|
a094f6 |
+
|
|
|
a094f6 |
+ case 836:
|
|
|
a094f6 |
+ switch (PPC_FIELD (insn, 11, 5))
|
|
|
a094f6 |
+ {
|
|
|
a094f6 |
+ case 1: /* VSX Scalar truncate & Convert Quad-Precision format
|
|
|
a094f6 |
+ to Unsigned Word format */
|
|
|
a094f6 |
+ case 2: /* VSX Scalar Convert Unsigned Doubleword format to
|
|
|
a094f6 |
+ Quad-Precision format */
|
|
|
a094f6 |
+ case 9: /* VSX Scalar truncate & Convert Quad-Precision format
|
|
|
a094f6 |
+ to Signed Word format */
|
|
|
a094f6 |
+ case 10: /* VSX Scalar Convert Signed Doubleword format to
|
|
|
a094f6 |
+ Quad-Precision format */
|
|
|
a094f6 |
+ case 17: /* VSX Scalar truncate & Convert Quad-Precision format
|
|
|
a094f6 |
+ to Unsigned Doubleword format */
|
|
|
a094f6 |
+ case 20: /* VSX Scalar round & Convert Quad-Precision format to
|
|
|
a094f6 |
+ Double-Precision format */
|
|
|
a094f6 |
+ case 22: /* VSX Scalar Convert Double-Precision format to
|
|
|
a094f6 |
+ Quad-Precision format */
|
|
|
a094f6 |
+ case 25: /* VSX Scalar truncate & Convert Quad-Precision format
|
|
|
a094f6 |
+ to Signed Doubleword format */
|
|
|
a094f6 |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
|
|
|
a094f6 |
+ ppc_record_vsr (regcache, tdep, PPC_VRT (insn) + 32);
|
|
|
a094f6 |
+ return 0;
|
|
|
a094f6 |
+ }
|
|
|
a094f6 |
}
|
|
|
a094f6 |
|
|
|
a094f6 |
fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x "
|
|
|
a094f6 |
- "at %s, 59-%d.\n", insn, paddress (gdbarch, addr), ext);
|
|
|
a094f6 |
+ "at %s, 63-%d.\n", insn, paddress (gdbarch, addr), ext);
|
|
|
a094f6 |
return -1;
|
|
|
a094f6 |
}
|
|
|
a094f6 |
|
|
|
a094f6 |
@@ -5308,12 +5732,21 @@
|
|
|
a094f6 |
}
|
|
|
a094f6 |
break;
|
|
|
a094f6 |
|
|
|
a094f6 |
- case 57: /* Load Floating-Point Double Pair */
|
|
|
a094f6 |
- if (PPC_FIELD (insn, 30, 2) != 0)
|
|
|
a094f6 |
- goto UNKNOWN_OP;
|
|
|
a094f6 |
- tmp = tdep->ppc_fp0_regnum + (PPC_RT (insn) & ~1);
|
|
|
a094f6 |
- record_full_arch_list_add_reg (regcache, tmp);
|
|
|
a094f6 |
- record_full_arch_list_add_reg (regcache, tmp + 1);
|
|
|
a094f6 |
+ case 57:
|
|
|
a094f6 |
+ switch (insn & 0x3)
|
|
|
a094f6 |
+ {
|
|
|
a094f6 |
+ case 0: /* Load Floating-Point Double Pair */
|
|
|
a094f6 |
+ tmp = tdep->ppc_fp0_regnum + (PPC_RT (insn) & ~1);
|
|
|
a094f6 |
+ record_full_arch_list_add_reg (regcache, tmp);
|
|
|
a094f6 |
+ record_full_arch_list_add_reg (regcache, tmp + 1);
|
|
|
a094f6 |
+ break;
|
|
|
a094f6 |
+ case 2: /* Load VSX Scalar Doubleword */
|
|
|
a094f6 |
+ case 3: /* Load VSX Scalar Single */
|
|
|
a094f6 |
+ ppc_record_vsr (regcache, tdep, PPC_VRT (insn) + 32);
|
|
|
a094f6 |
+ break;
|
|
|
a094f6 |
+ default:
|
|
|
a094f6 |
+ goto UNKNOWN_OP;
|
|
|
a094f6 |
+ }
|
|
|
a094f6 |
break;
|
|
|
a094f6 |
|
|
|
a094f6 |
case 58: /* Load Doubleword */
|
|
|
a094f6 |
@@ -5339,7 +5772,11 @@
|
|
|
a094f6 |
return -1;
|
|
|
a094f6 |
break;
|
|
|
a094f6 |
|
|
|
a094f6 |
- case 61: /* Store Floating-Point Double Pair */
|
|
|
a094f6 |
+ case 61:
|
|
|
a094f6 |
+ if (ppc_process_record_op61 (gdbarch, regcache, addr, insn) != 0)
|
|
|
a094f6 |
+ return -1;
|
|
|
a094f6 |
+ break;
|
|
|
a094f6 |
+
|
|
|
a094f6 |
case 62: /* Store Doubleword */
|
|
|
a094f6 |
/* Store Doubleword with Update */
|
|
|
a094f6 |
/* Store Quadword with Update */
|
|
|
a094f6 |
@@ -5348,7 +5785,7 @@
|
|
|
a094f6 |
int size;
|
|
|
a094f6 |
int sub2 = PPC_FIELD (insn, 30, 2);
|
|
|
a094f6 |
|
|
|
a094f6 |
- if ((op6 == 61 && sub2 != 0) || (op6 == 62 && sub2 > 2))
|
|
|
a094f6 |
+ if (sub2 > 2)
|
|
|
a094f6 |
goto UNKNOWN_OP;
|
|
|
a094f6 |
|
|
|
a094f6 |
if (PPC_RA (insn) != 0)
|
|
|
a094f6 |
@@ -5356,7 +5793,7 @@
|
|
|
a094f6 |
tdep->ppc_gp0_regnum + PPC_RA (insn),
|
|
|
a094f6 |
&addr);
|
|
|
a094f6 |
|
|
|
a094f6 |
- size = ((op6 == 61) || sub2 == 2) ? 16 : 8;
|
|
|
a094f6 |
+ size = (sub2 == 2) ? 16 : 8;
|
|
|
a094f6 |
|
|
|
a094f6 |
addr += PPC_DS (insn) << 2;
|
|
|
a094f6 |
if (record_full_arch_list_add_mem (addr, size) != 0)
|