|
 |
01917d |
commit 026122a670440bc51266f8e013e5c5877c19b54e
|
|
|
01917d |
Author: Peter Bergner <bergner@vnet.ibm.com>
|
|
|
01917d |
Date: Fri Jun 3 18:38:02 2016 -0500
|
|
|
01917d |
|
|
|
01917d |
Re-add support for lbarx, lharx, stbcx. and sthcx. insns back to the E6500 cpu.
|
|
|
01917d |
|
|
|
01917d |
opcodes/
|
|
|
01917d |
PR binutils/20196
|
|
|
01917d |
* ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
|
|
|
01917d |
opcodes for E6500.
|
|
|
01917d |
|
|
|
01917d |
gas/
|
|
|
01917d |
PR binutils/20196
|
|
|
01917d |
* gas/testsuite/gas/ppc/e6500.s
|
|
|
01917d |
stbcx., sthcx., stwcx., stdcx.>: Add tests.
|
|
|
01917d |
* gas/testsuite/gas/ppc/e6500.d: Likewise.
|
|
|
01917d |
* gas/testsuite/gas/ppc/power8.s: Likewise.
|
|
|
01917d |
* gas/testsuite/gas/ppc/power8.d: Likewise.
|
|
|
01917d |
* gas/testsuite/gas/ppc/power4.s
|
|
|
01917d |
stdcx.>: Add tests.
|
|
|
01917d |
* gas/testsuite/gas/ppc/power4.d: Likewise.
|
|
|
01917d |
|
|
|
01917d |
### a/opcodes/ChangeLog
|
|
|
01917d |
### b/opcodes/ChangeLog
|
|
|
01917d |
## -1,3 +1,9 @@
|
|
|
01917d |
+2016-06-03 Peter Bergner <bergner@vnet.ibm.com>
|
|
|
01917d |
+
|
|
|
01917d |
+ PR binutils/20196
|
|
|
01917d |
+ * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
|
|
|
01917d |
+ opcodes for E6500.
|
|
|
01917d |
+
|
|
|
01917d |
2016-06-03 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
01917d |
|
|
|
01917d |
PR binutis/18386
|
|
|
01917d |
--- a/opcodes/ppc-opc.c
|
|
|
01917d |
+++ b/opcodes/ppc-opc.c
|
|
|
01917d |
@@ -4824,7 +4824,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|
|
01917d |
{"mfvrd", X(31,51)|1, XX1RB_MASK|1, PPCVSX2, PPCNONE, {RA, VS}},
|
|
|
01917d |
{"eratilx", X(31,51), X_MASK, PPCA2, PPCNONE, {ERAT_T, RA, RB}},
|
|
|
01917d |
|
|
|
01917d |
-{"lbarx", X(31,52), XEH_MASK, POWER8|PPCVLE, PPCNONE, {RT, RA0, RB, EH}},
|
|
|
01917d |
+{"lbarx", X(31,52), XEH_MASK, POWER8|E6500|PPCVLE, PPCNONE, {RT, RA0, RB, EH}},
|
|
|
01917d |
|
|
|
01917d |
{"ldux", X(31,53), X_MASK, PPC64|PPCVLE, PPCNONE, {RT, RAL, RB}},
|
|
|
01917d |
|
|
|
01917d |
@@ -4904,7 +4904,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|
|
01917d |
{"mfvrwz", X(31,115)|1, XX1RB_MASK|1, PPCVSX2, PPCNONE, {RA, VS}},
|
|
|
01917d |
{"mfvsrwz", X(31,115), XX1RB_MASK, PPCVSX2, PPCNONE, {RA, XS6}},
|
|
|
01917d |
|
|
|
01917d |
-{"lharx", X(31,116), XEH_MASK, POWER8|PPCVLE, PPCNONE, {RT, RA0, RB, EH}},
|
|
|
01917d |
+{"lharx", X(31,116), XEH_MASK, POWER8|E6500|PPCVLE, PPCNONE, {RT, RA0, RB, EH}},
|
|
|
01917d |
|
|
|
01917d |
{"clf", X(31,118), XTO_MASK, POWER, PPCNONE, {RA, RB}},
|
|
|
01917d |
|
|
|
01917d |
@@ -5954,7 +5954,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|
|
01917d |
{"tendall.", XRC(31,686,1)|(1<<25), XRTRARB_MASK, PPCHTM, PPCNONE, {0}},
|
|
|
01917d |
{"tend.", XRC(31,686,1), XRTARARB_MASK, PPCHTM, PPCNONE, {HTM_A}},
|
|
|
01917d |
|
|
|
01917d |
-{"stbcx.", XRC(31,694,1), X_MASK, POWER8, PPCNONE, {RS, RA0, RB}},
|
|
|
01917d |
+{"stbcx.", XRC(31,694,1), X_MASK, POWER8|E6500, PPCNONE, {RS, RA0, RB}},
|
|
|
01917d |
|
|
|
01917d |
{"stfsux", X(31,695), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},
|
|
|
01917d |
|
|
|
01917d |
@@ -5986,7 +5986,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|
|
01917d |
{"stswi", X(31,725), X_MASK, PPCCOM|PPCVLE, E500|E500MC, {RS, RA0, NB}},
|
|
|
01917d |
{"stsi", X(31,725), X_MASK, PWRCOM, PPCNONE, {RS, RA0, NB}},
|
|
|
01917d |
|
|
|
01917d |
-{"sthcx.", XRC(31,726,1), X_MASK, POWER8, PPCNONE, {RS, RA0, RB}},
|
|
|
01917d |
+{"sthcx.", XRC(31,726,1), X_MASK, POWER8|E6500, PPCNONE, {RS, RA0, RB}},
|
|
|
01917d |
|
|
|
01917d |
{"stfdx", X(31,727), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
|
|
|
01917d |
|