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commit 026122a670440bc51266f8e013e5c5877c19b54e
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Author: Peter Bergner <bergner@vnet.ibm.com>
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Date: Fri Jun 3 18:38:02 2016 -0500
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Re-add support for lbarx, lharx, stbcx. and sthcx. insns back to the E6500 cpu.
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opcodes/
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PR binutils/20196
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* ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
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opcodes for E6500.
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gas/
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PR binutils/20196
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* gas/testsuite/gas/ppc/e6500.s
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stbcx., sthcx., stwcx., stdcx.>: Add tests.
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* gas/testsuite/gas/ppc/e6500.d: Likewise.
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* gas/testsuite/gas/ppc/power8.s: Likewise.
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* gas/testsuite/gas/ppc/power8.d: Likewise.
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* gas/testsuite/gas/ppc/power4.s
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stdcx.>: Add tests.
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* gas/testsuite/gas/ppc/power4.d: Likewise.
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### a/opcodes/ChangeLog
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### b/opcodes/ChangeLog
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## -1,3 +1,9 @@
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+2016-06-03 Peter Bergner <bergner@vnet.ibm.com>
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+
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+ PR binutils/20196
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+ * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
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+ opcodes for E6500.
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+
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2016-06-03 H.J. Lu <hongjiu.lu@intel.com>
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PR binutis/18386
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--- a/opcodes/ppc-opc.c
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+++ b/opcodes/ppc-opc.c
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@@ -4824,7 +4824,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"mfvrd", X(31,51)|1, XX1RB_MASK|1, PPCVSX2, PPCNONE, {RA, VS}},
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{"eratilx", X(31,51), X_MASK, PPCA2, PPCNONE, {ERAT_T, RA, RB}},
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-{"lbarx", X(31,52), XEH_MASK, POWER8|PPCVLE, PPCNONE, {RT, RA0, RB, EH}},
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+{"lbarx", X(31,52), XEH_MASK, POWER8|E6500|PPCVLE, PPCNONE, {RT, RA0, RB, EH}},
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{"ldux", X(31,53), X_MASK, PPC64|PPCVLE, PPCNONE, {RT, RAL, RB}},
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@@ -4904,7 +4904,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"mfvrwz", X(31,115)|1, XX1RB_MASK|1, PPCVSX2, PPCNONE, {RA, VS}},
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{"mfvsrwz", X(31,115), XX1RB_MASK, PPCVSX2, PPCNONE, {RA, XS6}},
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-{"lharx", X(31,116), XEH_MASK, POWER8|PPCVLE, PPCNONE, {RT, RA0, RB, EH}},
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+{"lharx", X(31,116), XEH_MASK, POWER8|E6500|PPCVLE, PPCNONE, {RT, RA0, RB, EH}},
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{"clf", X(31,118), XTO_MASK, POWER, PPCNONE, {RA, RB}},
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@@ -5954,7 +5954,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"tendall.", XRC(31,686,1)|(1<<25), XRTRARB_MASK, PPCHTM, PPCNONE, {0}},
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{"tend.", XRC(31,686,1), XRTARARB_MASK, PPCHTM, PPCNONE, {HTM_A}},
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-{"stbcx.", XRC(31,694,1), X_MASK, POWER8, PPCNONE, {RS, RA0, RB}},
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+{"stbcx.", XRC(31,694,1), X_MASK, POWER8|E6500, PPCNONE, {RS, RA0, RB}},
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{"stfsux", X(31,695), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},
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@@ -5986,7 +5986,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"stswi", X(31,725), X_MASK, PPCCOM|PPCVLE, E500|E500MC, {RS, RA0, NB}},
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{"stsi", X(31,725), X_MASK, PWRCOM, PPCNONE, {RS, RA0, NB}},
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-{"sthcx.", XRC(31,726,1), X_MASK, POWER8, PPCNONE, {RS, RA0, RB}},
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+{"sthcx.", XRC(31,726,1), X_MASK, POWER8|E6500, PPCNONE, {RS, RA0, RB}},
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{"stfdx", X(31,727), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
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