|
 |
2c2fa1 |
commit 6dca4fd141fd0b9fe0ea662295833b8ed43cb4e8
|
|
|
2c2fa1 |
Author: Anton Blanchard <anton@samba.org>
|
|
|
2c2fa1 |
Date: Tue Sep 22 15:39:24 2015 +1000
|
|
|
2c2fa1 |
|
|
|
2c2fa1 |
opcodes/ppc-opc.c: Add dscr and ctrl SPR mnemonics
|
|
|
2c2fa1 |
|
|
|
2c2fa1 |
opcodes/
|
|
|
2c2fa1 |
* ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
|
|
|
2c2fa1 |
|
|
|
2c2fa1 |
### a/opcodes/ChangeLog
|
|
|
2c2fa1 |
### b/opcodes/ChangeLog
|
|
|
2c2fa1 |
## -1,3 +1,7 @@
|
|
|
2c2fa1 |
+2015-09-22 Anton Blanchard <anton@samba.org>
|
|
|
2c2fa1 |
+
|
|
|
2c2fa1 |
+ * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
|
|
|
2c2fa1 |
+
|
|
|
2c2fa1 |
2015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
|
|
|
2c2fa1 |
|
|
|
2c2fa1 |
* sparc-dis.c (print_insn_sparc): Handle the privileged register
|
|
|
2c2fa1 |
--- a/opcodes/ppc-opc.c
|
|
|
2c2fa1 |
+++ b/opcodes/ppc-opc.c
|
|
|
2c2fa1 |
@@ -4878,6 +4878,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|
|
2c2fa1 |
{"mfdec", XSPR(31,339, 6), XSPR_MASK, MFDEC1, PPCNONE, {RT}},
|
|
|
2c2fa1 |
{"mflr", XSPR(31,339, 8), XSPR_MASK, COM|PPCVLE, PPCNONE, {RT}},
|
|
|
2c2fa1 |
{"mfctr", XSPR(31,339, 9), XSPR_MASK, COM|PPCVLE, PPCNONE, {RT}},
|
|
|
2c2fa1 |
+{"mfdscr", XSPR(31,339, 17), XSPR_MASK, POWER6, PPCNONE, {RT}},
|
|
|
2c2fa1 |
{"mftid", XSPR(31,339, 17), XSPR_MASK, POWER, PPCNONE, {RT}},
|
|
|
2c2fa1 |
{"mfdsisr", XSPR(31,339, 18), XSPR_MASK, COM, TITAN, {RT}},
|
|
|
2c2fa1 |
{"mfdar", XSPR(31,339, 19), XSPR_MASK, COM, TITAN, {RT}},
|
|
|
2c2fa1 |
@@ -4893,6 +4894,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|
|
2c2fa1 |
{"mfdear", XSPR(31,339, 61), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
|
|
|
2c2fa1 |
{"mfesr", XSPR(31,339, 62), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
|
|
|
2c2fa1 |
{"mfivpr", XSPR(31,339, 63), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
|
|
|
2c2fa1 |
+{"mfctrl", XSPR(31,339,136), XSPR_MASK, POWER4, PPCNONE, {RT}},
|
|
|
2c2fa1 |
{"mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, PPCNONE, {RT}},
|
|
|
2c2fa1 |
{"mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, PPCNONE, {RT}},
|
|
|
2c2fa1 |
{"mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, PPCNONE, {RT}},
|
|
|
2c2fa1 |
@@ -5216,6 +5218,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|
|
2c2fa1 |
{"mtxer", XSPR(31,467, 1), XSPR_MASK, COM|PPCVLE, PPCNONE, {RS}},
|
|
|
2c2fa1 |
{"mtlr", XSPR(31,467, 8), XSPR_MASK, COM|PPCVLE, PPCNONE, {RS}},
|
|
|
2c2fa1 |
{"mtctr", XSPR(31,467, 9), XSPR_MASK, COM|PPCVLE, PPCNONE, {RS}},
|
|
|
2c2fa1 |
+{"mtdscr", XSPR(31,467, 17), XSPR_MASK, POWER6, PPCNONE, {RS}},
|
|
|
2c2fa1 |
{"mttid", XSPR(31,467, 17), XSPR_MASK, POWER, PPCNONE, {RS}},
|
|
|
2c2fa1 |
{"mtdsisr", XSPR(31,467, 18), XSPR_MASK, COM, TITAN, {RS}},
|
|
|
2c2fa1 |
{"mtdar", XSPR(31,467, 19), XSPR_MASK, COM, TITAN, {RS}},
|
|
|
2c2fa1 |
@@ -5242,6 +5245,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|
|
2c2fa1 |
{"mtder", XSPR(31,467,149), XSPR_MASK, PPC860, PPCNONE, {RS}},
|
|
|
2c2fa1 |
{"mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, PPCNONE, {RS}},
|
|
|
2c2fa1 |
{"mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, PPCNONE, {RS}},
|
|
|
2c2fa1 |
+{"mtctrl", XSPR(31,467,152), XSPR_MASK, POWER4, PPCNONE, {RS}},
|
|
|
2c2fa1 |
{"mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, PPCNONE, {RS}},
|
|
|
2c2fa1 |
{"mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, PPCNONE, {RS}},
|
|
|
2c2fa1 |
{"mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, PPCNONE, {RS}},
|