|
 |
a094f6 |
commit 36f7a9411dcd7dbeb3483bc83a1acbb3dd235deb
|
|
|
a094f6 |
Author: Tom Rix <tom@bumblecow.com>
|
|
|
a094f6 |
Date: Mon Sep 28 12:09:32 2015 +0930
|
|
|
a094f6 |
|
|
|
a094f6 |
Patches for illegal ppc 500 instructions
|
|
|
a094f6 |
|
|
|
a094f6 |
This change marks a few opcodes as invalid for ppc e500 as well as adds
|
|
|
a094f6 |
a test to verify the change.
|
|
|
a094f6 |
|
|
|
a094f6 |
### a/opcodes/ChangeLog
|
|
|
a094f6 |
### b/opcodes/ChangeLog
|
|
|
a094f6 |
## -1,3 +1,7 @@
|
|
|
a094f6 |
+2015-09-28 Tom Rix <tom@bumblecow.com>
|
|
|
a094f6 |
+
|
|
|
a094f6 |
+ * ppc-opc.c (PPC500): Mark some opcodes as invalid
|
|
|
a094f6 |
+
|
|
|
a094f6 |
2015-09-23 Nick Clifton <nickc@redhat.com>
|
|
|
a094f6 |
|
|
|
a094f6 |
* bfin-dis.c (fmtconst): Remove unnecessary call to the abs
|
|
|
a094f6 |
--- a/opcodes/ppc-opc.c
|
|
|
a094f6 |
+++ b/opcodes/ppc-opc.c
|
|
|
a094f6 |
@@ -4779,7 +4779,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|
|
a094f6 |
|
|
|
a094f6 |
{"tlbiel", X(31,274), XRTLRA_MASK, POWER4, PPC476, {RB, L}},
|
|
|
a094f6 |
|
|
|
a094f6 |
-{"mfapidi", X(31,275), X_MASK, BOOKE, TITAN, {RT, RA}},
|
|
|
a094f6 |
+{"mfapidi", X(31,275), X_MASK, BOOKE, E500|TITAN, {RT, RA}},
|
|
|
a094f6 |
|
|
|
a094f6 |
{"lqarx", X(31,276), XEH_MASK, POWER8, PPCNONE, {RTQ, RAX, RBX, EH}},
|
|
|
a094f6 |
|
|
|
a094f6 |
@@ -4808,10 +4808,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|
|
a094f6 |
{"mfbhrbe", X(31,302), X_MASK, POWER8, PPCNONE, {RT, BHRBE}},
|
|
|
a094f6 |
|
|
|
a094f6 |
{"tlbie", X(31,306), XRA_MASK, POWER7, TITAN, {RB, RS}},
|
|
|
a094f6 |
-{"tlbie", X(31,306), XRTLRA_MASK, PPC, POWER7|TITAN, {RB, L}},
|
|
|
a094f6 |
+{"tlbie", X(31,306), XRTLRA_MASK, PPC, E500|POWER7|TITAN, {RB, L}},
|
|
|
a094f6 |
{"tlbi", X(31,306), XRT_MASK, POWER, PPCNONE, {RA0, RB}},
|
|
|
a094f6 |
|
|
|
a094f6 |
-{"eciwx", X(31,310), X_MASK, PPC, TITAN, {RT, RA0, RB}},
|
|
|
a094f6 |
+{"eciwx", X(31,310), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
|
|
|
a094f6 |
|
|
|
a094f6 |
{"lhzux", X(31,311), X_MASK, COM|PPCVLE, PPCNONE, {RT, RAL, RB}},
|
|
|
a094f6 |
|
|
|
a094f6 |
@@ -4856,7 +4856,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|
|
a094f6 |
{"mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, PPCNONE, {RT}},
|
|
|
a094f6 |
{"mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, PPCNONE, {RT}},
|
|
|
a094f6 |
{"mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, PPCNONE, {RT}},
|
|
|
a094f6 |
-{"mfdcr", X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476|PPCVLE, TITAN, {RT, SPR}},
|
|
|
a094f6 |
+{"mfdcr", X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476|PPCVLE, E500|TITAN, {RT, SPR}},
|
|
|
a094f6 |
{"mfdcr.", XRC(31,323,1), X_MASK, PPCA2, PPCNONE, {RT, SPR}},
|
|
|
a094f6 |
|
|
|
a094f6 |
{"lvexwx", X(31,325), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
|
|
|
a094f6 |
@@ -5087,7 +5087,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|
|
a094f6 |
{"divs", XO(31,363,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
|
|
|
a094f6 |
{"divs.", XO(31,363,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
|
|
|
a094f6 |
|
|
|
a094f6 |
-{"tlbia", X(31,370), 0xffffffff, PPC, TITAN, {0}},
|
|
|
a094f6 |
+{"tlbia", X(31,370), 0xffffffff, PPC, E500|TITAN, {0}},
|
|
|
a094f6 |
|
|
|
a094f6 |
{"mftbu", XSPR(31,371,269), XSPR_MASK, PPC, NO371|POWER4, {RT}},
|
|
|
a094f6 |
{"mftb", X(31,371), X_MASK, PPC, NO371|POWER4, {RT, TBR}},
|
|
|
a094f6 |
@@ -5145,7 +5145,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|
|
a094f6 |
|
|
|
a094f6 |
{"slbie", X(31,434), XRTRA_MASK, PPC64, PPCNONE, {RB}},
|
|
|
a094f6 |
|
|
|
a094f6 |
-{"ecowx", X(31,438), X_MASK, PPC, TITAN, {RT, RA0, RB}},
|
|
|
a094f6 |
+{"ecowx", X(31,438), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
|
|
|
a094f6 |
|
|
|
a094f6 |
{"sthux", X(31,439), X_MASK, COM|PPCVLE, PPCNONE, {RS, RAS, RB}},
|
|
|
a094f6 |
|
|
|
a094f6 |
@@ -5197,7 +5197,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|
|
a094f6 |
{"mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, PPCNONE, {RS}},
|
|
|
a094f6 |
{"mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, PPCNONE, {RS}},
|
|
|
a094f6 |
{"mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, PPCNONE, {RS}},
|
|
|
a094f6 |
-{"mtdcr", X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476|PPCVLE, TITAN, {SPR, RS}},
|
|
|
a094f6 |
+{"mtdcr", X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476|PPCVLE, E500|TITAN, {SPR, RS}},
|
|
|
a094f6 |
{"mtdcr.", XRC(31,451,1), X_MASK, PPCA2, PPCNONE, {SPR, RS}},
|
|
|
a094f6 |
|
|
|
a094f6 |
{"stvexwx", X(31,453), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
|