|
 |
a094f6 |
commit dc302c00611b6973fbc55e9fdd643ad24c370bd1
|
|
|
a094f6 |
Author: Peter Bergner <bergner@vnet.ibm.com>
|
|
|
a094f6 |
Date: Thu Jun 4 20:27:03 2015 -0500
|
|
|
a094f6 |
|
|
|
a094f6 |
Add hwsync extended mnemonic.
|
|
|
a094f6 |
|
|
|
a094f6 |
This commit adds a new extended menmonic for "sync 0" (same as "sync").
|
|
|
a094f6 |
The ISA documentation doesn't explicitly mention hwsync as an extended
|
|
|
a094f6 |
mnemonic (yet), but it does mention "heavyweight sync" and "hwsync" as
|
|
|
a094f6 |
the operation that gets performed when the sync's L field is 0.
|
|
|
a094f6 |
This is only enabled for POWER4 and later.
|
|
|
a094f6 |
|
|
|
a094f6 |
opcodes/
|
|
|
a094f6 |
* ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
|
|
|
a094f6 |
|
|
|
a094f6 |
gas/testsuite/
|
|
|
a094f6 |
* gas/ppc/a2.d: Fixup test case due to new extended mnemonic.
|
|
|
a094f6 |
* gas/ppc/power4.s <hwsync, lwsync, ptesync, sync>: Add tests.
|
|
|
a094f6 |
* gas/ppc/power4.d: Likewise.
|
|
|
a094f6 |
|
|
|
a094f6 |
--- a/opcodes/ppc-opc.c
|
|
|
a094f6 |
+++ b/opcodes/ppc-opc.c
|
|
|
a094f6 |
@@ -5465,6 +5465,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|
|
a094f6 |
{"lswi", X(31,597), X_MASK, PPCCOM|PPCVLE, E500|E500MC, {RT, RAX, NBI}},
|
|
|
a094f6 |
{"lsi", X(31,597), X_MASK, PWRCOM, PPCNONE, {RT, RA0, NB}},
|
|
|
a094f6 |
|
|
|
a094f6 |
+{"hwsync", XSYNC(31,598,0), 0xffffffff, POWER4, BOOKE|PPC476, {0}},
|
|
|
a094f6 |
{"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, E500, {0}},
|
|
|
a094f6 |
{"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, PPCNONE, {0}},
|
|
|
a094f6 |
{"sync", X(31,598), XSYNCLE_MASK,E6500, PPCNONE, {LS, ESYNC}},
|