Blame SOURCES/gdb-rhbz1320945-power9-16of38.patch

01917d
commit dc302c00611b6973fbc55e9fdd643ad24c370bd1
01917d
Author: Peter Bergner <bergner@vnet.ibm.com>
01917d
Date:   Thu Jun 4 20:27:03 2015 -0500
01917d
01917d
    Add hwsync extended mnemonic.
01917d
    
01917d
    This commit adds a new extended menmonic for "sync 0" (same as "sync").
01917d
    The ISA documentation doesn't explicitly mention hwsync as an extended
01917d
    mnemonic (yet), but it does mention "heavyweight sync" and "hwsync" as
01917d
    the operation that gets performed when the sync's L field is 0.
01917d
    This is only enabled for POWER4 and later.
01917d
    
01917d
    opcodes/
01917d
            * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
01917d
    
01917d
    gas/testsuite/
01917d
            * gas/ppc/a2.d: Fixup test case due to new extended mnemonic.
01917d
            * gas/ppc/power4.s <hwsync, lwsync, ptesync, sync>: Add tests.
01917d
            * gas/ppc/power4.d: Likewise.
01917d
01917d
--- a/opcodes/ppc-opc.c
01917d
+++ b/opcodes/ppc-opc.c
01917d
@@ -5465,6 +5465,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
01917d
 {"lswi",	X(31,597),	X_MASK,  PPCCOM|PPCVLE, E500|E500MC,	{RT, RAX, NBI}},
01917d
 {"lsi",		X(31,597),	X_MASK,      PWRCOM,	PPCNONE,	{RT, RA0, NB}},
01917d
 
01917d
+{"hwsync",	XSYNC(31,598,0), 0xffffffff, POWER4,	BOOKE|PPC476,	{0}},
01917d
 {"lwsync",	XSYNC(31,598,1), 0xffffffff, PPC,	E500,		{0}},
01917d
 {"ptesync",	XSYNC(31,598,2), 0xffffffff, PPC64,	PPCNONE,	{0}},
01917d
 {"sync",	X(31,598),	XSYNCLE_MASK,E6500,	PPCNONE,	{LS, ESYNC}},