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commit 4fff86c517abb5ba454befe0ec0f284f720dde00
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Author: Peter Bergner <bergner@vnet.ibm.com>
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Date: Mon Apr 27 11:06:54 2015 -0500
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opcodes/
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* ppc-opc.c (DCBT_EO): New define.
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(powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
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<lharx>: Likewise.
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<stbcx.>: Likewise.
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<sthcx.>: Likewise.
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<waitrsv>: Do not enable for POWER7 and later.
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<waitimpl>: Likewise.
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<dcbt>: Default to the two operand form of the instruction for all
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"old" cpus. For "new" cpus, use the operand ordering that matches
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whether the cpu is server or embedded.
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<dcbtst>: Likewise.
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gas/testsuite/
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* gas/ppc/a2.s: Fixup test case due to dcbt/dcbtst embedded operand
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ordering change.
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* gas/ppc/a2.d: Likewise.
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* gas/ppc/476.d: Likewise.
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* gas/ppc/booke.s: Remove invalid 3 operand dcbt tests.
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* gas/ppc/booke.d: Likewise.
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* gas/ppc/power7.s: Remove lbarx, lharx, stbcx., sthcx., waitrsv
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and waitimpl tests.
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* gas/ppc/power7.d: Likewise.
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### a/opcodes/ChangeLog
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### b/opcodes/ChangeLog
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## -1,3 +1,17 @@
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+2015-04-27 Peter Bergner <bergner@vnet.ibm.com>
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+
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+ * ppc-opc.c (DCBT_EO): New define.
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+ (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
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+ <lharx>: Likewise.
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+ <stbcx.>: Likewise.
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+ <sthcx.>: Likewise.
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+ <waitrsv>: Do not enable for POWER7 and later.
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+ <waitimpl>: Likewise.
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+ <dcbt>: Default to the two operand form of the instruction for all
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+ "old" cpus. For "new" cpus, use the operand ordering that matches
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+ whether the cpu is server or embedded.
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+ <dcbtst>: Likewise.
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+
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2015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
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* s390-opc.c: New instruction type VV0UU2.
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--- a/opcodes/ppc-opc.c
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+++ b/opcodes/ppc-opc.c
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@@ -2756,6 +2756,12 @@ extract_vleil (unsigned long insn,
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#define E6500 PPC_OPCODE_E6500
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#define PPCVLE PPC_OPCODE_VLE
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#define PPCHTM PPC_OPCODE_HTM
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+/* The list of embedded processors that use the embedded operand ordering
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+ for the 3 operand dcbt and dcbtst instructions. */
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+#define DCBT_EO (PPC_OPCODE_E500 | PPC_OPCODE_E500MC | PPC_OPCODE_476 \
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+ | PPC_OPCODE_A2 | PPC_OPCODE_VLE)
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+
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+
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/* The opcode table.
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@@ -4463,7 +4469,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"mfvrd", X(31,51)|1, XX1RB_MASK|1, PPCVSX2, PPCNONE, {RA, VS}},
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{"eratilx", X(31,51), X_MASK, PPCA2, PPCNONE, {ERAT_T, RA, RB}},
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-{"lbarx", X(31,52), XEH_MASK, POWER7|PPCVLE, PPCNONE, {RT, RA0, RB, EH}},
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+{"lbarx", X(31,52), XEH_MASK, POWER8|PPCVLE, PPCNONE, {RT, RA0, RB, EH}},
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{"ldux", X(31,53), X_MASK, PPC64|PPCVLE, PPCNONE, {RT, RAL, RB}},
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@@ -4478,8 +4484,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"andc", XRC(31,60,0), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
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{"andc.", XRC(31,60,1), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
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-{"waitrsv", X(31,62)|(1<<21), 0xffffffff, POWER7|E500MC|PPCA2, PPCNONE, {0}},
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-{"waitimpl", X(31,62)|(2<<21), 0xffffffff, POWER7|E500MC|PPCA2, PPCNONE, {0}},
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+{"waitrsv", X(31,62)|(1<<21), 0xffffffff, E500MC|PPCA2, PPCNONE, {0}},
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+{"waitimpl", X(31,62)|(2<<21), 0xffffffff, E500MC|PPCA2, PPCNONE, {0}},
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{"wait", X(31,62), XWC_MASK, POWER7|E500MC|PPCA2|PPCVLE, PPCNONE, {WC}},
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{"dcbstep", XRT(31,63,0), XRT_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RA0, RB}},
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@@ -4543,7 +4549,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"mfvrwz", X(31,115)|1, XX1RB_MASK|1, PPCVSX2, PPCNONE, {RA, VS}},
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{"mfvsrwz", X(31,115), XX1RB_MASK, PPCVSX2, PPCNONE, {RA, XS6}},
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-{"lharx", X(31,116), XEH_MASK, POWER7|PPCVLE, PPCNONE, {RT, RA0, RB, EH}},
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+{"lharx", X(31,116), XEH_MASK, POWER8|PPCVLE, PPCNONE, {RT, RA0, RB, EH}},
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{"clf", X(31,118), XTO_MASK, POWER, PPCNONE, {RA, RB}},
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@@ -4711,9 +4717,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"mtvsrwz", X(31,243), XX1RB_MASK, PPCVSX2, PPCNONE, {XT6, RA}},
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{"dcbtstt", XRT(31,246,0x10), XRT_MASK, POWER7, PPCNONE, {RA0, RB}},
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-{"dcbtst", X(31,246), X_MASK, POWER4, PPCNONE, {RA0, RB, CT}},
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-{"dcbtst", X(31,246), X_MASK, PPC|PPCVLE, POWER4, {CT, RA0, RB}},
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-
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+{"dcbtst", X(31,246), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}},
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+{"dcbtst", X(31,246), X_MASK, DCBT_EO, PPCNONE, {CT, RA0, RB}},
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+{"dcbtst", X(31,246), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}},
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+
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{"stbux", X(31,247), X_MASK, COM|PPCVLE, PPCNONE, {RS, RAS, RB}},
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{"slliq", XRC(31,248,0), X_MASK, M601, PPCNONE, {RA, RS, SH}},
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@@ -4753,9 +4760,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"lscbx.", XRC(31,277,1), X_MASK, M601, PPCNONE, {RT, RA, RB}},
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{"dcbtt", XRT(31,278,0x10), XRT_MASK, POWER7, PPCNONE, {RA0, RB}},
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-{"dcbt", X(31,278), X_MASK, POWER4, PPCNONE, {RA0, RB, CT}},
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-{"dcbt", X(31,278), X_MASK, PPC|PPCVLE, POWER4, {CT, RA0, RB}},
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-
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+{"dcbt", X(31,278), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}},
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+{"dcbt", X(31,278), X_MASK, DCBT_EO, PPCNONE, {CT, RA0, RB}},
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+{"dcbt", X(31,278), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}},
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+
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{"lhzx", X(31,279), X_MASK, COM|PPCVLE, PPCNONE, {RT, RA0, RB}},
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{"cdtbcd", X(31,282), XRB_MASK, POWER6, PPCNONE, {RA, RS}},
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@@ -5531,7 +5539,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"tendall.", XRC(31,686,1)|(1<<25), XRTRARB_MASK, PPCHTM, PPCNONE, {0}},
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{"tend.", XRC(31,686,1), XRTARARB_MASK, PPCHTM, PPCNONE, {HTM_A}},
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-{"stbcx.", XRC(31,694,1), X_MASK, POWER7, PPCNONE, {RS, RA0, RB}},
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+{"stbcx.", XRC(31,694,1), X_MASK, POWER8, PPCNONE, {RS, RA0, RB}},
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{"stfsux", X(31,695), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},
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@@ -5561,7 +5569,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"stswi", X(31,725), X_MASK, PPCCOM|PPCVLE, E500|E500MC, {RS, RA0, NB}},
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{"stsi", X(31,725), X_MASK, PWRCOM, PPCNONE, {RS, RA0, NB}},
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-{"sthcx.", XRC(31,726,1), X_MASK, POWER7, PPCNONE, {RS, RA0, RB}},
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+{"sthcx.", XRC(31,726,1), X_MASK, POWER8, PPCNONE, {RS, RA0, RB}},
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{"stfdx", X(31,727), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
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