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commit 12e87fac5c760b04eed4f5a5948c2dfd6ec8f6d8
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Author: Jan Beulich <jbeulich@novell.com>
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Date: Tue Oct 21 09:56:38 2014 +0200
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ppc: enable msgclr and msgsnd on Power8
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According to my reading of the spec it was an oversight for them to
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not having got enabled when Power8 support got added.
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### a/opcodes/ChangeLog
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### b/opcodes/ChangeLog
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## -1,3 +1,7 @@
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+2014-10-21 Jan Beulich <jbeulich@suse.com>
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+
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+ * ppc-opc.c (powerpc_opcodes): Enable msgclr and msgsnd on Power8.
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+
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2014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
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* sparc-opc.c (sparc-opcodes): Fix several misplaced hwcap
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--- a/opcodes/ppc-opc.c
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+++ b/opcodes/ppc-opc.c
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@@ -4653,7 +4653,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"addze.", XO(31,202,0,1), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}},
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{"aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
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-{"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RB}},
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+{"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8|PPCVLE, PPCNONE, {RB}},
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{"mtsr", X(31,210), XRB_MASK|(1<<20), COM, NON32, {SR, RS}},
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@@ -4700,7 +4700,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
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{"icblce", X(31,238), X_MASK, PPCCHLK, E500MC|PPCA2, {CT, RA, RB}},
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-{"msgclr", XRTRA(31,238,0,0),XRTRA_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RB}},
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+{"msgclr", XRTRA(31,238,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8|PPCVLE, PPCNONE, {RB}},
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{"mtsrin", X(31,242), XRA_MASK, PPC, NON32, {RS, RB}},
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{"mtsri", X(31,242), XRA_MASK, POWER, NON32, {RS, RB}},
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