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Message-ID: <549C48EA.9060206@gmail.com>
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7b26da |
Date: Fri, 26 Dec 2014 01:27:06 +0800
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From: Wei-cheng Wang <cole945 at gmail dot com>
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To: Ulrich Weigand <uweigand at de dot ibm dot com>
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CC: gdb-patches at sourceware dot org
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Subject: Re: [PATCH 2/3 v4] Process record support for PowerPC
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On 12/18/2014 2:41 AM, Ulrich Weigand wrote:
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> you seem to have removed all the 32-bit struct sizes here. Your last
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> iteration had different values for many of those structs for wordsize 4
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> vs. wordsize 8, and I think we need to keep them.
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7b26da |
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7b26da |
Oops, this is a mistake. I'm sorry.
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Fixed now :)
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Thanks,
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Wei-cheng
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--
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7b26da |
2014-12-06 Wei-cheng Wang <cole945@gmail.com>
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7b26da |
Ulrich Weigand <uweigand@de.ibm.com>
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* configure.tgt (powerpc*-*-linux): Add linux-record.o to
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gdb_target_obs.
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(ppc_linux_record_tdep, ppc64_linux_record_tdep): New for linux syscall
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record.
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(ppc_canonicalize_syscall, ppc_linux_syscall_record,
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ppc_linux_record_signal, ppc_init_linux_record_tdep): New functions.
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(ppc_linux_init_abi): Set process_record, process_record_signal.
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* ppc-tdep.h (struct gdbarch_tdep): Add ppc_syscall_record and
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ppc_linux_record_tdep to gdbarch_tdep.
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(ppc_process_record): New declaration.
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* rs6000-tdep.c (ppc_record_vsr, ppc_process_record_op4,
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ppc_process_record_op19, ppc_process_record_op31,
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ppc_process_record_op59, ppc_process_record_op60,
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ppc_process_record_op63, ppc_process_record): New functions.
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changelog for testsuite
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2014-12-06 Wei-cheng Wang <cole945@gmail.com>
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* lib/gdb.exp (supports_process_record): Return true for
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powerpc*-*-linux*.
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(supports_reverse): Likewise.
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commit b4cdae6fe51e532e0b1069c6960b14a610182d14
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Author: Wei-cheng Wang <cole945@gmail.com>
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Date: Sat Jan 17 14:30:33 2015 +0800
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Reverse debugging for PowerPC.
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Index: gdb-7.6.1/gdb/configure.tgt
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===================================================================
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--- gdb-7.6.1.orig/gdb/configure.tgt
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+++ gdb-7.6.1/gdb/configure.tgt
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@@ -428,7 +428,8 @@ powerpc*-*-linux*)
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ppc64-tdep.o solib-svr4.o solib-spu.o \
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spu-multiarch.o \
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glibc-tdep.o symfile-mem.o linux-tdep.o \
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- ravenscar-thread.o ppc-ravenscar-thread.o"
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+ ravenscar-thread.o ppc-ravenscar-thread.o \
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+ linux-record.o "
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gdb_sim=../sim/ppc/libsim.a
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build_gdbserver=yes
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;;
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Index: gdb-7.6.1/gdb/ppc-linux-tdep.c
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===================================================================
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--- gdb-7.6.1.orig/gdb/ppc-linux-tdep.c
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+++ gdb-7.6.1/gdb/ppc-linux-tdep.c
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@@ -50,6 +50,8 @@
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#include "spu-tdep.h"
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#include "xml-syscall.h"
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#include "linux-tdep.h"
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+#include "linux-record.h"
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+#include "record-full.h"
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#include "stap-probe.h"
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#include "ax.h"
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@@ -812,6 +814,167 @@ ppc_linux_get_syscall_number (struct gdb
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return ret;
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}
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+/* PPC process record-replay */
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+
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+static struct linux_record_tdep ppc_linux_record_tdep;
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+static struct linux_record_tdep ppc64_linux_record_tdep;
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+
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+static enum gdb_syscall
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+ppc_canonicalize_syscall (int syscall)
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+{
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+ /* See arch/powerpc/include/uapi/asm/unistd.h */
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+
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+ if (syscall <= 165)
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+ return syscall;
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+ else if (syscall >= 167 && syscall <= 190) /* Skip query_module 166 */
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+ return syscall + 1;
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+ else if (syscall >= 192 && syscall <= 197) /* mmap2 */
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+ return syscall;
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+ else if (syscall == 208) /* tkill */
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+ return gdb_sys_tkill;
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+ else if (syscall >= 207 && syscall <= 220) /* gettid */
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+ return syscall + 224 - 207;
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+ else if (syscall >= 234 && syscall <= 239) /* exit_group */
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+ return syscall + 252 - 234;
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+ else if (syscall >= 240 && syscall <=248) /* timer_create */
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+ return syscall += 259 - 240;
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+ else if (syscall >= 250 && syscall <=251) /* tgkill */
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+ return syscall + 270 - 250;
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+ else if (syscall == 336)
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+ return gdb_sys_recv;
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+ else if (syscall == 337)
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+ return gdb_sys_recvfrom;
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+ else if (syscall == 342)
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+ return gdb_sys_recvmsg;
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+ return -1;
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+}
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+
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+static int
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+ppc_linux_syscall_record (struct regcache *regcache)
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+{
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+ struct gdbarch *gdbarch = get_regcache_arch (regcache);
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+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
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+ ULONGEST scnum;
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+ enum gdb_syscall syscall_gdb;
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+ int ret;
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+ int i;
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+
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+ regcache_raw_read_unsigned (regcache, tdep->ppc_gp0_regnum, &scnum);
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+ syscall_gdb = ppc_canonicalize_syscall (scnum);
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+
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+ if (syscall_gdb < 0)
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+ {
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+ printf_unfiltered (_("Process record and replay target doesn't "
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+ "support syscall number %d\n"), (int) scnum);
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+ return 0;
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+ }
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+
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+ if (syscall_gdb == gdb_sys_sigreturn
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+ || syscall_gdb == gdb_sys_rt_sigreturn)
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+ {
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+ int i, j;
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+ int regsets[] = { tdep->ppc_gp0_regnum,
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+ tdep->ppc_fp0_regnum,
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+ tdep->ppc_vr0_regnum,
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+ tdep->ppc_vsr0_upper_regnum };
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+
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+ for (j = 0; j < 4; j++)
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+ {
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+ if (regsets[j] == -1)
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+ continue;
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+ for (i = 0; i < 32; i++)
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+ {
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+ if (record_full_arch_list_add_reg (regcache, regsets[j] + i))
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+ return -1;
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+ }
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+ }
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+
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+ if (record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum))
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+ return -1;
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+ if (record_full_arch_list_add_reg (regcache, tdep->ppc_ctr_regnum))
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+ return -1;
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+ if (record_full_arch_list_add_reg (regcache, tdep->ppc_lr_regnum))
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+ return -1;
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+ if (record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum))
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+ return -1;
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+
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+ return 0;
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+ }
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+
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+ if (tdep->wordsize == 8)
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+ ret = record_linux_system_call (syscall_gdb, regcache,
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+ &ppc64_linux_record_tdep);
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+ else
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+ ret = record_linux_system_call (syscall_gdb, regcache,
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+ &ppc_linux_record_tdep);
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+
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+ if (ret != 0)
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+ return ret;
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+
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+ /* Record registers clobbered during syscall. */
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+ for (i = 3; i <= 12; i++)
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+ {
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+ if (record_full_arch_list_add_reg (regcache, tdep->ppc_gp0_regnum + i))
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+ return -1;
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+ }
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+ if (record_full_arch_list_add_reg (regcache, tdep->ppc_gp0_regnum + 0))
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+ return -1;
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+ if (record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum))
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+ return -1;
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+ if (record_full_arch_list_add_reg (regcache, tdep->ppc_ctr_regnum))
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+ return -1;
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+ if (record_full_arch_list_add_reg (regcache, tdep->ppc_lr_regnum))
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+ return -1;
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+
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+ return 0;
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+}
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+
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+static int
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+ppc_linux_record_signal (struct gdbarch *gdbarch, struct regcache *regcache,
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+ enum gdb_signal signal)
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+{
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+ /* See handle_rt_signal64 in arch/powerpc/kernel/signal_64.c
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+ handle_rt_signal32 in arch/powerpc/kernel/signal_32.c
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+ arch/powerpc/include/asm/ptrace.h
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+ for details. */
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+ const int SIGNAL_FRAMESIZE = 128;
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+ const int sizeof_rt_sigframe = 1440 * 2 + 8 * 2 + 4 * 6 + 8 + 8 + 128 + 512;
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+ ULONGEST sp;
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+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
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+ int i;
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+
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+ for (i = 3; i <= 12; i++)
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+ {
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+ if (record_full_arch_list_add_reg (regcache, tdep->ppc_gp0_regnum + i))
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+ return -1;
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+ }
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+
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+ if (record_full_arch_list_add_reg (regcache, tdep->ppc_lr_regnum))
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+ return -1;
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+ if (record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum))
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+ return -1;
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+ if (record_full_arch_list_add_reg (regcache, tdep->ppc_ctr_regnum))
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+ return -1;
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+ if (record_full_arch_list_add_reg (regcache, gdbarch_pc_regnum (gdbarch)))
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+ return -1;
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+ if (record_full_arch_list_add_reg (regcache, gdbarch_sp_regnum (gdbarch)))
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+ return -1;
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+
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+ /* Record the change in the stack.
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+ frame-size = sizeof (struct rt_sigframe) + SIGNAL_FRAMESIZE */
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+ regcache_raw_read_unsigned (regcache, gdbarch_sp_regnum (gdbarch), &sp);
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+ sp -= SIGNAL_FRAMESIZE;
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+ sp -= sizeof_rt_sigframe;
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+
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+ if (record_full_arch_list_add_mem (sp, SIGNAL_FRAMESIZE + sizeof_rt_sigframe))
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+ return -1;
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+
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+ if (record_full_arch_list_add_end ())
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+ return -1;
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+
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+ return 0;
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7b26da |
+}
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+
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static void
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ppc_linux_write_pc (struct regcache *regcache, CORE_ADDR pc)
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7b26da |
{
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7b26da |
@@ -1287,6 +1450,234 @@ static const struct frame_unwind ppu2spu
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7b26da |
ppu2spu_prev_arch,
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7b26da |
};
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7b26da |
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7b26da |
+/* Initialize linux_record_tdep if not initialized yet. */
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+
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7b26da |
+static void
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7b26da |
+ppc_init_linux_record_tdep (struct linux_record_tdep *record_tdep,
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7b26da |
+ int wordsize)
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7b26da |
+{
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7b26da |
+ /* Simply return if it had been initialized. */
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7b26da |
+ if (record_tdep->size_pointer != 0)
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7b26da |
+ return;
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7b26da |
+
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7b26da |
+ /* These values are the size of the type that will be used in a system
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7b26da |
+ call. They are obtained from Linux Kernel source. */
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+
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+ if (wordsize == 8)
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+ {
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7b26da |
+ record_tdep->size_pointer = 8;
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7b26da |
+ record_tdep->size__old_kernel_stat = 32;
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7b26da |
+ record_tdep->size_tms = 32;
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7b26da |
+ record_tdep->size_loff_t = 8;
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7b26da |
+ record_tdep->size_flock = 32;
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7b26da |
+ record_tdep->size_oldold_utsname = 45;
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7b26da |
+ record_tdep->size_ustat = 32;
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7b26da |
+ record_tdep->size_old_sigaction = 152;
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7b26da |
+ record_tdep->size_old_sigset_t = 128;
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7b26da |
+ record_tdep->size_rlimit = 16;
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7b26da |
+ record_tdep->size_rusage = 144;
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7b26da |
+ record_tdep->size_timeval = 16;
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7b26da |
+ record_tdep->size_timezone = 8;
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7b26da |
+ record_tdep->size_old_gid_t = 4;
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7b26da |
+ record_tdep->size_old_uid_t = 4;
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7b26da |
+ record_tdep->size_fd_set = 128;
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7b26da |
+ record_tdep->size_dirent = 280;
|
|
|
7b26da |
+ record_tdep->size_dirent64 = 280;
|
|
|
7b26da |
+ record_tdep->size_statfs = 120;
|
|
|
7b26da |
+ record_tdep->size_statfs64 = 120;
|
|
|
7b26da |
+ record_tdep->size_sockaddr = 16;
|
|
|
7b26da |
+ record_tdep->size_int = 4;
|
|
|
7b26da |
+ record_tdep->size_long = 8;
|
|
|
7b26da |
+ record_tdep->size_ulong = 8;
|
|
|
7b26da |
+ record_tdep->size_msghdr = 56;
|
|
|
7b26da |
+ record_tdep->size_itimerval = 32;
|
|
|
7b26da |
+ record_tdep->size_stat = 144;
|
|
|
7b26da |
+ record_tdep->size_old_utsname = 325;
|
|
|
7b26da |
+ record_tdep->size_sysinfo = 112;
|
|
|
7b26da |
+ record_tdep->size_msqid_ds = 120;
|
|
|
7b26da |
+ record_tdep->size_shmid_ds = 112;
|
|
|
7b26da |
+ record_tdep->size_new_utsname = 390;
|
|
|
7b26da |
+ record_tdep->size_timex = 208;
|
|
|
7b26da |
+ record_tdep->size_mem_dqinfo = 24;
|
|
|
7b26da |
+ record_tdep->size_if_dqblk = 72;
|
|
|
7b26da |
+ record_tdep->size_fs_quota_stat = 80;
|
|
|
7b26da |
+ record_tdep->size_timespec = 16;
|
|
|
7b26da |
+ record_tdep->size_pollfd = 8;
|
|
|
7b26da |
+ record_tdep->size_NFS_FHSIZE = 32;
|
|
|
7b26da |
+ record_tdep->size_knfsd_fh = 132;
|
|
|
7b26da |
+ record_tdep->size_TASK_COMM_LEN = 32;
|
|
|
7b26da |
+ record_tdep->size_sigaction = 152;
|
|
|
7b26da |
+ record_tdep->size_sigset_t = 128;
|
|
|
7b26da |
+ record_tdep->size_siginfo_t = 128;
|
|
|
7b26da |
+ record_tdep->size_cap_user_data_t = 8;
|
|
|
7b26da |
+ record_tdep->size_stack_t = 24;
|
|
|
7b26da |
+ record_tdep->size_off_t = 8;
|
|
|
7b26da |
+ record_tdep->size_stat64 = 104;
|
|
|
7b26da |
+ record_tdep->size_gid_t = 4;
|
|
|
7b26da |
+ record_tdep->size_uid_t = 4;
|
|
|
7b26da |
+ record_tdep->size_PAGE_SIZE = 0x10000; /* 64KB */
|
|
|
7b26da |
+ record_tdep->size_flock64 = 32;
|
|
|
7b26da |
+ record_tdep->size_io_event = 32;
|
|
|
7b26da |
+ record_tdep->size_iocb = 64;
|
|
|
7b26da |
+ record_tdep->size_epoll_event = 16;
|
|
|
7b26da |
+ record_tdep->size_itimerspec = 32;
|
|
|
7b26da |
+ record_tdep->size_mq_attr = 64;
|
|
|
7b26da |
+ record_tdep->size_siginfo = 128;
|
|
|
7b26da |
+ record_tdep->size_termios = 44;
|
|
|
7b26da |
+ record_tdep->size_pid_t = 4;
|
|
|
7b26da |
+ record_tdep->size_winsize = 8;
|
|
|
7b26da |
+ record_tdep->size_serial_struct = 72;
|
|
|
7b26da |
+ record_tdep->size_serial_icounter_struct = 80;
|
|
|
7b26da |
+ record_tdep->size_size_t = 8;
|
|
|
7b26da |
+ record_tdep->size_iovec = 16;
|
|
|
7b26da |
+ }
|
|
|
7b26da |
+ else if (wordsize == 4)
|
|
|
7b26da |
+ {
|
|
|
7b26da |
+ record_tdep->size_pointer = 4;
|
|
|
7b26da |
+ record_tdep->size__old_kernel_stat = 32;
|
|
|
7b26da |
+ record_tdep->size_tms = 16;
|
|
|
7b26da |
+ record_tdep->size_loff_t = 8;
|
|
|
7b26da |
+ record_tdep->size_flock = 16;
|
|
|
7b26da |
+ record_tdep->size_oldold_utsname = 45;
|
|
|
7b26da |
+ record_tdep->size_ustat = 20;
|
|
|
7b26da |
+ record_tdep->size_old_sigaction = 152;
|
|
|
7b26da |
+ record_tdep->size_old_sigset_t = 128;
|
|
|
7b26da |
+ record_tdep->size_rlimit = 8;
|
|
|
7b26da |
+ record_tdep->size_rusage = 72;
|
|
|
7b26da |
+ record_tdep->size_timeval = 8;
|
|
|
7b26da |
+ record_tdep->size_timezone = 8;
|
|
|
7b26da |
+ record_tdep->size_old_gid_t = 4;
|
|
|
7b26da |
+ record_tdep->size_old_uid_t = 4;
|
|
|
7b26da |
+ record_tdep->size_fd_set = 128;
|
|
|
7b26da |
+ record_tdep->size_dirent = 268;
|
|
|
7b26da |
+ record_tdep->size_dirent64 = 280;
|
|
|
7b26da |
+ record_tdep->size_statfs = 64;
|
|
|
7b26da |
+ record_tdep->size_statfs64 = 88;
|
|
|
7b26da |
+ record_tdep->size_sockaddr = 16;
|
|
|
7b26da |
+ record_tdep->size_int = 4;
|
|
|
7b26da |
+ record_tdep->size_long = 4;
|
|
|
7b26da |
+ record_tdep->size_ulong = 4;
|
|
|
7b26da |
+ record_tdep->size_msghdr = 28;
|
|
|
7b26da |
+ record_tdep->size_itimerval = 16;
|
|
|
7b26da |
+ record_tdep->size_stat = 88;
|
|
|
7b26da |
+ record_tdep->size_old_utsname = 325;
|
|
|
7b26da |
+ record_tdep->size_sysinfo = 64;
|
|
|
7b26da |
+ record_tdep->size_msqid_ds = 68;
|
|
|
7b26da |
+ record_tdep->size_shmid_ds = 60;
|
|
|
7b26da |
+ record_tdep->size_new_utsname = 390;
|
|
|
7b26da |
+ record_tdep->size_timex = 128;
|
|
|
7b26da |
+ record_tdep->size_mem_dqinfo = 24;
|
|
|
7b26da |
+ record_tdep->size_if_dqblk = 72;
|
|
|
7b26da |
+ record_tdep->size_fs_quota_stat = 80;
|
|
|
7b26da |
+ record_tdep->size_timespec = 8;
|
|
|
7b26da |
+ record_tdep->size_pollfd = 8;
|
|
|
7b26da |
+ record_tdep->size_NFS_FHSIZE = 32;
|
|
|
7b26da |
+ record_tdep->size_knfsd_fh = 132;
|
|
|
7b26da |
+ record_tdep->size_TASK_COMM_LEN = 32;
|
|
|
7b26da |
+ record_tdep->size_sigaction = 140;
|
|
|
7b26da |
+ record_tdep->size_sigset_t = 128;
|
|
|
7b26da |
+ record_tdep->size_siginfo_t = 128;
|
|
|
7b26da |
+ record_tdep->size_cap_user_data_t = 4;
|
|
|
7b26da |
+ record_tdep->size_stack_t = 12;
|
|
|
7b26da |
+ record_tdep->size_off_t = 4;
|
|
|
7b26da |
+ record_tdep->size_stat64 = 104;
|
|
|
7b26da |
+ record_tdep->size_gid_t = 4;
|
|
|
7b26da |
+ record_tdep->size_uid_t = 4;
|
|
|
7b26da |
+ record_tdep->size_PAGE_SIZE = 0x10000; /* 64KB */
|
|
|
7b26da |
+ record_tdep->size_flock64 = 32;
|
|
|
7b26da |
+ record_tdep->size_io_event = 32;
|
|
|
7b26da |
+ record_tdep->size_iocb = 64;
|
|
|
7b26da |
+ record_tdep->size_epoll_event = 16;
|
|
|
7b26da |
+ record_tdep->size_itimerspec = 16;
|
|
|
7b26da |
+ record_tdep->size_mq_attr = 32;
|
|
|
7b26da |
+ record_tdep->size_siginfo = 128;
|
|
|
7b26da |
+ record_tdep->size_termios = 44;
|
|
|
7b26da |
+ record_tdep->size_pid_t = 4;
|
|
|
7b26da |
+ record_tdep->size_winsize = 8;
|
|
|
7b26da |
+ record_tdep->size_serial_struct = 60;
|
|
|
7b26da |
+ record_tdep->size_serial_icounter_struct = 80;
|
|
|
7b26da |
+ record_tdep->size_size_t = 4;
|
|
|
7b26da |
+ record_tdep->size_iovec = 8;
|
|
|
7b26da |
+ }
|
|
|
7b26da |
+ else
|
|
|
7b26da |
+ internal_error (__FILE__, __LINE__, _("unexpected wordsize"));
|
|
|
7b26da |
+
|
|
|
7b26da |
+ /* These values are the second argument of system call "sys_fcntl"
|
|
|
7b26da |
+ and "sys_fcntl64". They are obtained from Linux Kernel source. */
|
|
|
7b26da |
+ record_tdep->fcntl_F_GETLK = 5;
|
|
|
7b26da |
+ record_tdep->fcntl_F_GETLK64 = 12;
|
|
|
7b26da |
+ record_tdep->fcntl_F_SETLK64 = 13;
|
|
|
7b26da |
+ record_tdep->fcntl_F_SETLKW64 = 14;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ record_tdep->arg1 = PPC_R0_REGNUM + 3;
|
|
|
7b26da |
+ record_tdep->arg2 = PPC_R0_REGNUM + 4;
|
|
|
7b26da |
+ record_tdep->arg3 = PPC_R0_REGNUM + 5;
|
|
|
7b26da |
+ record_tdep->arg4 = PPC_R0_REGNUM + 6;
|
|
|
7b26da |
+ record_tdep->arg5 = PPC_R0_REGNUM + 7;
|
|
|
7b26da |
+ record_tdep->arg6 = PPC_R0_REGNUM + 8;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ /* These values are the second argument of system call "sys_ioctl".
|
|
|
7b26da |
+ They are obtained from Linux Kernel source.
|
|
|
7b26da |
+ See arch/powerpc/include/uapi/asm/ioctls.h. */
|
|
|
7b26da |
+ record_tdep->ioctl_TCGETS = 0x403c7413;
|
|
|
7b26da |
+ record_tdep->ioctl_TCSETS = 0x803c7414;
|
|
|
7b26da |
+ record_tdep->ioctl_TCSETSW = 0x803c7415;
|
|
|
7b26da |
+ record_tdep->ioctl_TCSETSF = 0x803c7416;
|
|
|
7b26da |
+ record_tdep->ioctl_TCGETA = 0x40147417;
|
|
|
7b26da |
+ record_tdep->ioctl_TCSETA = 0x80147418;
|
|
|
7b26da |
+ record_tdep->ioctl_TCSETAW = 0x80147419;
|
|
|
7b26da |
+ record_tdep->ioctl_TCSETAF = 0x8014741c;
|
|
|
7b26da |
+ record_tdep->ioctl_TCSBRK = 0x2000741d;
|
|
|
7b26da |
+ record_tdep->ioctl_TCXONC = 0x2000741e;
|
|
|
7b26da |
+ record_tdep->ioctl_TCFLSH = 0x2000741f;
|
|
|
7b26da |
+ record_tdep->ioctl_TIOCEXCL = 0x540c;
|
|
|
7b26da |
+ record_tdep->ioctl_TIOCNXCL = 0x540d;
|
|
|
7b26da |
+ record_tdep->ioctl_TIOCSCTTY = 0x540e;
|
|
|
7b26da |
+ record_tdep->ioctl_TIOCGPGRP = 0x40047477;
|
|
|
7b26da |
+ record_tdep->ioctl_TIOCSPGRP = 0x80047476;
|
|
|
7b26da |
+ record_tdep->ioctl_TIOCOUTQ = 0x40047473;
|
|
|
7b26da |
+ record_tdep->ioctl_TIOCSTI = 0x5412;
|
|
|
7b26da |
+ record_tdep->ioctl_TIOCGWINSZ = 0x40087468;
|
|
|
7b26da |
+ record_tdep->ioctl_TIOCSWINSZ = 0x80087467;
|
|
|
7b26da |
+ record_tdep->ioctl_TIOCMGET = 0x5415;
|
|
|
7b26da |
+ record_tdep->ioctl_TIOCMBIS = 0x5416;
|
|
|
7b26da |
+ record_tdep->ioctl_TIOCMBIC = 0x5417;
|
|
|
7b26da |
+ record_tdep->ioctl_TIOCMSET = 0x5418;
|
|
|
7b26da |
+ record_tdep->ioctl_TIOCGSOFTCAR = 0x5419;
|
|
|
7b26da |
+ record_tdep->ioctl_TIOCSSOFTCAR = 0x541a;
|
|
|
7b26da |
+ record_tdep->ioctl_FIONREAD = 0x4004667f;
|
|
|
7b26da |
+ record_tdep->ioctl_TIOCINQ = 0x4004667f;
|
|
|
7b26da |
+ record_tdep->ioctl_TIOCLINUX = 0x541c;
|
|
|
7b26da |
+ record_tdep->ioctl_TIOCCONS = 0x541d;
|
|
|
7b26da |
+ record_tdep->ioctl_TIOCGSERIAL = 0x541e;
|
|
|
7b26da |
+ record_tdep->ioctl_TIOCSSERIAL = 0x541f;
|
|
|
7b26da |
+ record_tdep->ioctl_TIOCPKT = 0x5420;
|
|
|
7b26da |
+ record_tdep->ioctl_FIONBIO = 0x8004667e;
|
|
|
7b26da |
+ record_tdep->ioctl_TIOCNOTTY = 0x5422;
|
|
|
7b26da |
+ record_tdep->ioctl_TIOCSETD = 0x5423;
|
|
|
7b26da |
+ record_tdep->ioctl_TIOCGETD = 0x5424;
|
|
|
7b26da |
+ record_tdep->ioctl_TCSBRKP = 0x5425;
|
|
|
7b26da |
+ record_tdep->ioctl_TIOCSBRK = 0x5427;
|
|
|
7b26da |
+ record_tdep->ioctl_TIOCCBRK = 0x5428;
|
|
|
7b26da |
+ record_tdep->ioctl_TIOCGSID = 0x5429;
|
|
|
7b26da |
+ record_tdep->ioctl_TIOCGPTN = 0x40045430;
|
|
|
7b26da |
+ record_tdep->ioctl_TIOCSPTLCK = 0x80045431;
|
|
|
7b26da |
+ record_tdep->ioctl_FIONCLEX = 0x20006602;
|
|
|
7b26da |
+ record_tdep->ioctl_FIOCLEX = 0x20006601;
|
|
|
7b26da |
+ record_tdep->ioctl_FIOASYNC = 0x8004667d;
|
|
|
7b26da |
+ record_tdep->ioctl_TIOCSERCONFIG = 0x5453;
|
|
|
7b26da |
+ record_tdep->ioctl_TIOCSERGWILD = 0x5454;
|
|
|
7b26da |
+ record_tdep->ioctl_TIOCSERSWILD = 0x5455;
|
|
|
7b26da |
+ record_tdep->ioctl_TIOCGLCKTRMIOS = 0x5456;
|
|
|
7b26da |
+ record_tdep->ioctl_TIOCSLCKTRMIOS = 0x5457;
|
|
|
7b26da |
+ record_tdep->ioctl_TIOCSERGSTRUCT = 0x5458;
|
|
|
7b26da |
+ record_tdep->ioctl_TIOCSERGETLSR = 0x5459;
|
|
|
7b26da |
+ record_tdep->ioctl_TIOCSERGETMULTI = 0x545a;
|
|
|
7b26da |
+ record_tdep->ioctl_TIOCSERSETMULTI = 0x545b;
|
|
|
7b26da |
+ record_tdep->ioctl_TIOCMIWAIT = 0x545c;
|
|
|
7b26da |
+ record_tdep->ioctl_TIOCGICOUNT = 0x545d;
|
|
|
7b26da |
+ record_tdep->ioctl_FIOQSIZE = 0x40086680;
|
|
|
7b26da |
+}
|
|
|
7b26da |
|
|
|
7b26da |
static void
|
|
|
7b26da |
ppc_linux_init_abi (struct gdbarch_info info,
|
|
|
7b26da |
@@ -1486,6 +1877,14 @@ ppc_linux_init_abi (struct gdbarch_info
|
|
|
7b26da |
}
|
|
|
7b26da |
|
|
|
7b26da |
set_gdbarch_get_siginfo_type (gdbarch, linux_get_siginfo_type);
|
|
|
7b26da |
+
|
|
|
7b26da |
+ /* Support reverse debugging. */
|
|
|
7b26da |
+ set_gdbarch_process_record (gdbarch, ppc_process_record);
|
|
|
7b26da |
+ set_gdbarch_process_record_signal (gdbarch, ppc_linux_record_signal);
|
|
|
7b26da |
+ tdep->ppc_syscall_record = ppc_linux_syscall_record;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ ppc_init_linux_record_tdep (&ppc_linux_record_tdep, 4);
|
|
|
7b26da |
+ ppc_init_linux_record_tdep (&ppc64_linux_record_tdep, 8);
|
|
|
7b26da |
}
|
|
|
7b26da |
|
|
|
7b26da |
/* Provide a prototype to silence -Wmissing-prototypes. */
|
|
|
7b26da |
Index: gdb-7.6.1/gdb/ppc-tdep.h
|
|
|
7b26da |
===================================================================
|
|
|
7b26da |
--- gdb-7.6.1.orig/gdb/ppc-tdep.h
|
|
|
7b26da |
+++ gdb-7.6.1/gdb/ppc-tdep.h
|
|
|
7b26da |
@@ -259,6 +259,8 @@ struct gdbarch_tdep
|
|
|
7b26da |
/* ISA-specific types. */
|
|
|
7b26da |
struct type *ppc_builtin_type_vec64;
|
|
|
7b26da |
struct type *ppc_builtin_type_vec128;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ int (*ppc_syscall_record) (struct regcache *regcache);
|
|
|
7b26da |
};
|
|
|
7b26da |
|
|
|
7b26da |
|
|
|
7b26da |
@@ -318,6 +320,9 @@ extern CORE_ADDR ppc_insn_d_field (unsig
|
|
|
7b26da |
|
|
|
7b26da |
extern CORE_ADDR ppc_insn_ds_field (unsigned int insn);
|
|
|
7b26da |
|
|
|
7b26da |
+extern int ppc_process_record (struct gdbarch *gdbarch,
|
|
|
7b26da |
+ struct regcache *regcache, CORE_ADDR addr);
|
|
|
7b26da |
+
|
|
|
7b26da |
/* Instruction size. */
|
|
|
7b26da |
#define PPC_INSN_SIZE 4
|
|
|
7b26da |
|
|
|
7b26da |
Index: gdb-7.6.1/gdb/rs6000-tdep.c
|
|
|
7b26da |
===================================================================
|
|
|
7b26da |
--- gdb-7.6.1.orig/gdb/rs6000-tdep.c
|
|
|
7b26da |
+++ gdb-7.6.1/gdb/rs6000-tdep.c
|
|
|
7b26da |
@@ -39,6 +39,8 @@
|
|
|
7b26da |
#include "dwarf2-frame.h"
|
|
|
7b26da |
#include "target-descriptions.h"
|
|
|
7b26da |
#include "user-regs.h"
|
|
|
7b26da |
+#include "record-full.h"
|
|
|
7b26da |
+#include "auxv.h"
|
|
|
7b26da |
|
|
|
7b26da |
#include "libbfd.h" /* for bfd_default_set_arch_mach */
|
|
|
7b26da |
#include "coff/internal.h" /* for libcoff.h */
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7b26da |
@@ -3682,6 +3684,1689 @@ bfd_uses_spe_extensions (bfd *abfd)
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7b26da |
return success;
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7b26da |
}
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7b26da |
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7b26da |
+/* These are macros for parsing instruction fields (I.1.6.28) */
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7b26da |
+
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7b26da |
+#define PPC_FIELD(value, from, len) \
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7b26da |
+ (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1))
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7b26da |
+#define PPC_SEXT(v, bs) \
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7b26da |
+ ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \
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7b26da |
+ ^ ((CORE_ADDR) 1 << ((bs) - 1))) \
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7b26da |
+ - ((CORE_ADDR) 1 << ((bs) - 1)))
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7b26da |
+#define PPC_OP6(insn) PPC_FIELD (insn, 0, 6)
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7b26da |
+#define PPC_EXTOP(insn) PPC_FIELD (insn, 21, 10)
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7b26da |
+#define PPC_RT(insn) PPC_FIELD (insn, 6, 5)
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7b26da |
+#define PPC_RS(insn) PPC_FIELD (insn, 6, 5)
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7b26da |
+#define PPC_RA(insn) PPC_FIELD (insn, 11, 5)
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7b26da |
+#define PPC_RB(insn) PPC_FIELD (insn, 16, 5)
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7b26da |
+#define PPC_NB(insn) PPC_FIELD (insn, 16, 5)
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7b26da |
+#define PPC_VRT(insn) PPC_FIELD (insn, 6, 5)
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7b26da |
+#define PPC_FRT(insn) PPC_FIELD (insn, 6, 5)
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7b26da |
+#define PPC_SPR(insn) (PPC_FIELD (insn, 11, 5) \
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7b26da |
+ | (PPC_FIELD (insn, 16, 5) << 5))
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7b26da |
+#define PPC_BO(insn) PPC_FIELD (insn, 6, 5)
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7b26da |
+#define PPC_T(insn) PPC_FIELD (insn, 6, 5)
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7b26da |
+#define PPC_D(insn) PPC_SEXT (PPC_FIELD (insn, 16, 16), 16)
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7b26da |
+#define PPC_DS(insn) PPC_SEXT (PPC_FIELD (insn, 16, 14), 14)
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7b26da |
+#define PPC_BIT(insn,n) ((insn & (1 << (31 - (n)))) ? 1 : 0)
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7b26da |
+#define PPC_OE(insn) PPC_BIT (insn, 21)
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7b26da |
+#define PPC_RC(insn) PPC_BIT (insn, 31)
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7b26da |
+#define PPC_Rc(insn) PPC_BIT (insn, 21)
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7b26da |
+#define PPC_LK(insn) PPC_BIT (insn, 31)
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7b26da |
+#define PPC_TX(insn) PPC_BIT (insn, 31)
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7b26da |
+#define PPC_LEV(insn) PPC_FIELD (insn, 20, 7)
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7b26da |
+
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7b26da |
+#define PPC_XT(insn) ((PPC_TX (insn) << 5) | PPC_T (insn))
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7b26da |
+#define PPC_XER_NB(xer) (xer & 0x7f)
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+
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7b26da |
+/* Record Vector-Scalar Registers. */
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+
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7b26da |
+static int
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+ppc_record_vsr (struct regcache *regcache, struct gdbarch_tdep *tdep, int vsr)
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7b26da |
+{
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+ if (vsr < 0 || vsr >= 64)
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+ return -1;
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+
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7b26da |
+ if (vsr >= 32)
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+ {
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7b26da |
+ if (tdep->ppc_vr0_regnum >= 0)
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+ record_full_arch_list_add_reg (regcache, tdep->ppc_vr0_regnum + vsr - 32);
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+ }
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7b26da |
+ else
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+ {
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7b26da |
+ if (tdep->ppc_fp0_regnum >= 0)
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+ record_full_arch_list_add_reg (regcache, tdep->ppc_fp0_regnum + vsr);
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7b26da |
+ if (tdep->ppc_vsr0_upper_regnum >= 0)
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+ record_full_arch_list_add_reg (regcache,
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+ tdep->ppc_vsr0_upper_regnum + vsr);
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+ }
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+
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+ return 0;
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7b26da |
+}
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+
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7b26da |
+/* Parse instructions of primary opcode-4. */
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+
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+static int
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+ppc_process_record_op4 (struct gdbarch *gdbarch, struct regcache *regcache,
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+ CORE_ADDR addr, uint32_t insn)
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+{
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+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
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+ int ext = PPC_FIELD (insn, 21, 11);
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+
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7b26da |
+ switch (ext & 0x3f)
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+ {
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7b26da |
+ case 32: /* Vector Multiply-High-Add Signed Halfword Saturate */
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7b26da |
+ case 33: /* Vector Multiply-High-Round-Add Signed Halfword Saturate */
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7b26da |
+ case 39: /* Vector Multiply-Sum Unsigned Halfword Saturate */
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7b26da |
+ case 41: /* Vector Multiply-Sum Signed Halfword Saturate */
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+ record_full_arch_list_add_reg (regcache, PPC_VSCR_REGNUM);
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7b26da |
+ /* FALL-THROUGH */
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7b26da |
+ case 42: /* Vector Select */
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7b26da |
+ case 43: /* Vector Permute */
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7b26da |
+ case 44: /* Vector Shift Left Double by Octet Immediate */
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7b26da |
+ case 45: /* Vector Permute and Exclusive-OR */
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7b26da |
+ case 60: /* Vector Add Extended Unsigned Quadword Modulo */
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7b26da |
+ case 61: /* Vector Add Extended & write Carry Unsigned Quadword */
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7b26da |
+ case 62: /* Vector Subtract Extended Unsigned Quadword Modulo */
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7b26da |
+ case 63: /* Vector Subtract Extended & write Carry Unsigned Quadword */
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7b26da |
+ case 34: /* Vector Multiply-Low-Add Unsigned Halfword Modulo */
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+ case 36: /* Vector Multiply-Sum Unsigned Byte Modulo */
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+ case 37: /* Vector Multiply-Sum Mixed Byte Modulo */
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+ case 38: /* Vector Multiply-Sum Unsigned Halfword Modulo */
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+ case 40: /* Vector Multiply-Sum Signed Halfword Modulo */
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7b26da |
+ case 46: /* Vector Multiply-Add Single-Precision */
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+ case 47: /* Vector Negative Multiply-Subtract Single-Precision */
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+ record_full_arch_list_add_reg (regcache,
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+ tdep->ppc_vr0_regnum + PPC_VRT (insn));
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+ return 0;
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+ }
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+
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7b26da |
+ switch ((ext & 0x1ff))
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7b26da |
+ {
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7b26da |
+ /* 5.16 Decimal Integer Arithmetic Instructions */
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7b26da |
+ case 1: /* Decimal Add Modulo */
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+ case 65: /* Decimal Subtract Modulo */
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+
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7b26da |
+ /* Bit-21 should be set. */
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+ if (!PPC_BIT (insn, 21))
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+ break;
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+
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+ record_full_arch_list_add_reg (regcache,
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+ tdep->ppc_vr0_regnum + PPC_VRT (insn));
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+ record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
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+ return 0;
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7b26da |
+ }
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+
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7b26da |
+ /* Bit-21 is used for RC */
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7b26da |
+ switch (ext & 0x3ff)
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+ {
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7b26da |
+ case 6: /* Vector Compare Equal To Unsigned Byte */
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7b26da |
+ case 70: /* Vector Compare Equal To Unsigned Halfword */
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7b26da |
+ case 134: /* Vector Compare Equal To Unsigned Word */
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7b26da |
+ case 199: /* Vector Compare Equal To Unsigned Doubleword */
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7b26da |
+ case 774: /* Vector Compare Greater Than Signed Byte */
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7b26da |
+ case 838: /* Vector Compare Greater Than Signed Halfword */
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7b26da |
+ case 902: /* Vector Compare Greater Than Signed Word */
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7b26da |
+ case 967: /* Vector Compare Greater Than Signed Doubleword */
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7b26da |
+ case 518: /* Vector Compare Greater Than Unsigned Byte */
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7b26da |
+ case 646: /* Vector Compare Greater Than Unsigned Word */
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7b26da |
+ case 582: /* Vector Compare Greater Than Unsigned Halfword */
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7b26da |
+ case 711: /* Vector Compare Greater Than Unsigned Doubleword */
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7b26da |
+ case 966: /* Vector Compare Bounds Single-Precision */
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+ case 198: /* Vector Compare Equal To Single-Precision */
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7b26da |
+ case 454: /* Vector Compare Greater Than or Equal To Single-Precision */
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+ case 710: /* Vector Compare Greater Than Single-Precision */
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+ if (PPC_Rc (insn))
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+ record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
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+ record_full_arch_list_add_reg (regcache,
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+ tdep->ppc_vr0_regnum + PPC_VRT (insn));
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+ return 0;
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+ }
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+
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7b26da |
+ switch (ext)
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+ {
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7b26da |
+ case 142: /* Vector Pack Unsigned Halfword Unsigned Saturate */
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+ case 206: /* Vector Pack Unsigned Word Unsigned Saturate */
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+ case 270: /* Vector Pack Signed Halfword Unsigned Saturate */
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7b26da |
+ case 334: /* Vector Pack Signed Word Unsigned Saturate */
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7b26da |
+ case 398: /* Vector Pack Signed Halfword Signed Saturate */
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+ case 462: /* Vector Pack Signed Word Signed Saturate */
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7b26da |
+ case 1230: /* Vector Pack Unsigned Doubleword Unsigned Saturate */
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7b26da |
+ case 1358: /* Vector Pack Signed Doubleword Unsigned Saturate */
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7b26da |
+ case 1486: /* Vector Pack Signed Doubleword Signed Saturate */
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7b26da |
+ case 512: /* Vector Add Unsigned Byte Saturate */
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7b26da |
+ case 576: /* Vector Add Unsigned Halfword Saturate */
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7b26da |
+ case 640: /* Vector Add Unsigned Word Saturate */
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7b26da |
+ case 768: /* Vector Add Signed Byte Saturate */
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7b26da |
+ case 832: /* Vector Add Signed Halfword Saturate */
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7b26da |
+ case 896: /* Vector Add Signed Word Saturate */
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7b26da |
+ case 1536: /* Vector Subtract Unsigned Byte Saturate */
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7b26da |
+ case 1600: /* Vector Subtract Unsigned Halfword Saturate */
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7b26da |
+ case 1664: /* Vector Subtract Unsigned Word Saturate */
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7b26da |
+ case 1792: /* Vector Subtract Signed Byte Saturate */
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7b26da |
+ case 1856: /* Vector Subtract Signed Halfword Saturate */
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7b26da |
+ case 1920: /* Vector Subtract Signed Word Saturate */
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+
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7b26da |
+ case 1544: /* Vector Sum across Quarter Unsigned Byte Saturate */
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7b26da |
+ case 1800: /* Vector Sum across Quarter Signed Byte Saturate */
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7b26da |
+ case 1608: /* Vector Sum across Quarter Signed Halfword Saturate */
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7b26da |
+ case 1672: /* Vector Sum across Half Signed Word Saturate */
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7b26da |
+ case 1928: /* Vector Sum across Signed Word Saturate */
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7b26da |
+ case 970: /* Vector Convert To Signed Fixed-Point Word Saturate */
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7b26da |
+ case 906: /* Vector Convert To Unsigned Fixed-Point Word Saturate */
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+ record_full_arch_list_add_reg (regcache, PPC_VSCR_REGNUM);
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7b26da |
+ /* FALL-THROUGH */
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7b26da |
+ case 12: /* Vector Merge High Byte */
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7b26da |
+ case 14: /* Vector Pack Unsigned Halfword Unsigned Modulo */
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7b26da |
+ case 76: /* Vector Merge High Halfword */
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7b26da |
+ case 78: /* Vector Pack Unsigned Word Unsigned Modulo */
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7b26da |
+ case 140: /* Vector Merge High Word */
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7b26da |
+ case 268: /* Vector Merge Low Byte */
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7b26da |
+ case 332: /* Vector Merge Low Halfword */
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7b26da |
+ case 396: /* Vector Merge Low Word */
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7b26da |
+ case 526: /* Vector Unpack High Signed Byte */
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7b26da |
+ case 590: /* Vector Unpack High Signed Halfword */
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7b26da |
+ case 654: /* Vector Unpack Low Signed Byte */
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7b26da |
+ case 718: /* Vector Unpack Low Signed Halfword */
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7b26da |
+ case 782: /* Vector Pack Pixel */
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7b26da |
+ case 846: /* Vector Unpack High Pixel */
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7b26da |
+ case 974: /* Vector Unpack Low Pixel */
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7b26da |
+ case 1102: /* Vector Pack Unsigned Doubleword Unsigned Modulo */
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7b26da |
+ case 1614: /* Vector Unpack High Signed Word */
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7b26da |
+ case 1676: /* Vector Merge Odd Word */
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7b26da |
+ case 1742: /* Vector Unpack Low Signed Word */
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7b26da |
+ case 1932: /* Vector Merge Even Word */
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7b26da |
+ case 524: /* Vector Splat Byte */
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7b26da |
+ case 588: /* Vector Splat Halfword */
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7b26da |
+ case 652: /* Vector Splat Word */
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7b26da |
+ case 780: /* Vector Splat Immediate Signed Byte */
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7b26da |
+ case 844: /* Vector Splat Immediate Signed Halfword */
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7b26da |
+ case 908: /* Vector Splat Immediate Signed Word */
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7b26da |
+ case 452: /* Vector Shift Left */
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7b26da |
+ case 708: /* Vector Shift Right */
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7b26da |
+ case 1036: /* Vector Shift Left by Octet */
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7b26da |
+ case 1100: /* Vector Shift Right by Octet */
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7b26da |
+ case 0: /* Vector Add Unsigned Byte Modulo */
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7b26da |
+ case 64: /* Vector Add Unsigned Halfword Modulo */
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7b26da |
+ case 128: /* Vector Add Unsigned Word Modulo */
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7b26da |
+ case 192: /* Vector Add Unsigned Doubleword Modulo */
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7b26da |
+ case 256: /* Vector Add Unsigned Quadword Modulo */
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7b26da |
+ case 320: /* Vector Add & write Carry Unsigned Quadword */
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7b26da |
+ case 384: /* Vector Add and Write Carry-Out Unsigned Word */
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7b26da |
+ case 8: /* Vector Multiply Odd Unsigned Byte */
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7b26da |
+ case 72: /* Vector Multiply Odd Unsigned Halfword */
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7b26da |
+ case 136: /* Vector Multiply Odd Unsigned Word */
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7b26da |
+ case 264: /* Vector Multiply Odd Signed Byte */
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7b26da |
+ case 328: /* Vector Multiply Odd Signed Halfword */
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7b26da |
+ case 392: /* Vector Multiply Odd Signed Word */
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7b26da |
+ case 520: /* Vector Multiply Even Unsigned Byte */
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7b26da |
+ case 584: /* Vector Multiply Even Unsigned Halfword */
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7b26da |
+ case 648: /* Vector Multiply Even Unsigned Word */
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7b26da |
+ case 776: /* Vector Multiply Even Signed Byte */
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7b26da |
+ case 840: /* Vector Multiply Even Signed Halfword */
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7b26da |
+ case 904: /* Vector Multiply Even Signed Word */
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7b26da |
+ case 137: /* Vector Multiply Unsigned Word Modulo */
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7b26da |
+ case 1024: /* Vector Subtract Unsigned Byte Modulo */
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7b26da |
+ case 1088: /* Vector Subtract Unsigned Halfword Modulo */
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7b26da |
+ case 1152: /* Vector Subtract Unsigned Word Modulo */
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7b26da |
+ case 1216: /* Vector Subtract Unsigned Doubleword Modulo */
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7b26da |
+ case 1280: /* Vector Subtract Unsigned Quadword Modulo */
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7b26da |
+ case 1344: /* Vector Subtract & write Carry Unsigned Quadword */
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7b26da |
+ case 1408: /* Vector Subtract and Write Carry-Out Unsigned Word */
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7b26da |
+ case 1282: /* Vector Average Signed Byte */
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7b26da |
+ case 1346: /* Vector Average Signed Halfword */
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7b26da |
+ case 1410: /* Vector Average Signed Word */
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7b26da |
+ case 1026: /* Vector Average Unsigned Byte */
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7b26da |
+ case 1090: /* Vector Average Unsigned Halfword */
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7b26da |
+ case 1154: /* Vector Average Unsigned Word */
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7b26da |
+ case 258: /* Vector Maximum Signed Byte */
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7b26da |
+ case 322: /* Vector Maximum Signed Halfword */
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7b26da |
+ case 386: /* Vector Maximum Signed Word */
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7b26da |
+ case 450: /* Vector Maximum Signed Doubleword */
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7b26da |
+ case 2: /* Vector Maximum Unsigned Byte */
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7b26da |
+ case 66: /* Vector Maximum Unsigned Halfword */
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7b26da |
+ case 130: /* Vector Maximum Unsigned Word */
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7b26da |
+ case 194: /* Vector Maximum Unsigned Doubleword */
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7b26da |
+ case 770: /* Vector Minimum Signed Byte */
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7b26da |
+ case 834: /* Vector Minimum Signed Halfword */
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7b26da |
+ case 898: /* Vector Minimum Signed Word */
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7b26da |
+ case 962: /* Vector Minimum Signed Doubleword */
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7b26da |
+ case 514: /* Vector Minimum Unsigned Byte */
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7b26da |
+ case 578: /* Vector Minimum Unsigned Halfword */
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7b26da |
+ case 642: /* Vector Minimum Unsigned Word */
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7b26da |
+ case 706: /* Vector Minimum Unsigned Doubleword */
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7b26da |
+ case 1028: /* Vector Logical AND */
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7b26da |
+ case 1668: /* Vector Logical Equivalent */
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|
7b26da |
+ case 1092: /* Vector Logical AND with Complement */
|
|
|
7b26da |
+ case 1412: /* Vector Logical NAND */
|
|
|
7b26da |
+ case 1348: /* Vector Logical OR with Complement */
|
|
|
7b26da |
+ case 1156: /* Vector Logical OR */
|
|
|
7b26da |
+ case 1284: /* Vector Logical NOR */
|
|
|
7b26da |
+ case 1220: /* Vector Logical XOR */
|
|
|
7b26da |
+ case 4: /* Vector Rotate Left Byte */
|
|
|
7b26da |
+ case 132: /* Vector Rotate Left Word VX-form */
|
|
|
7b26da |
+ case 68: /* Vector Rotate Left Halfword */
|
|
|
7b26da |
+ case 196: /* Vector Rotate Left Doubleword */
|
|
|
7b26da |
+ case 260: /* Vector Shift Left Byte */
|
|
|
7b26da |
+ case 388: /* Vector Shift Left Word */
|
|
|
7b26da |
+ case 324: /* Vector Shift Left Halfword */
|
|
|
7b26da |
+ case 1476: /* Vector Shift Left Doubleword */
|
|
|
7b26da |
+ case 516: /* Vector Shift Right Byte */
|
|
|
7b26da |
+ case 644: /* Vector Shift Right Word */
|
|
|
7b26da |
+ case 580: /* Vector Shift Right Halfword */
|
|
|
7b26da |
+ case 1732: /* Vector Shift Right Doubleword */
|
|
|
7b26da |
+ case 772: /* Vector Shift Right Algebraic Byte */
|
|
|
7b26da |
+ case 900: /* Vector Shift Right Algebraic Word */
|
|
|
7b26da |
+ case 836: /* Vector Shift Right Algebraic Halfword */
|
|
|
7b26da |
+ case 964: /* Vector Shift Right Algebraic Doubleword */
|
|
|
7b26da |
+ case 10: /* Vector Add Single-Precision */
|
|
|
7b26da |
+ case 74: /* Vector Subtract Single-Precision */
|
|
|
7b26da |
+ case 1034: /* Vector Maximum Single-Precision */
|
|
|
7b26da |
+ case 1098: /* Vector Minimum Single-Precision */
|
|
|
7b26da |
+ case 842: /* Vector Convert From Signed Fixed-Point Word */
|
|
|
7b26da |
+ case 778: /* Vector Convert From Unsigned Fixed-Point Word */
|
|
|
7b26da |
+ case 714: /* Vector Round to Single-Precision Integer toward -Infinity */
|
|
|
7b26da |
+ case 522: /* Vector Round to Single-Precision Integer Nearest */
|
|
|
7b26da |
+ case 650: /* Vector Round to Single-Precision Integer toward +Infinity */
|
|
|
7b26da |
+ case 586: /* Vector Round to Single-Precision Integer toward Zero */
|
|
|
7b26da |
+ case 394: /* Vector 2 Raised to the Exponent Estimate Floating-Point */
|
|
|
7b26da |
+ case 458: /* Vector Log Base 2 Estimate Floating-Point */
|
|
|
7b26da |
+ case 266: /* Vector Reciprocal Estimate Single-Precision */
|
|
|
7b26da |
+ case 330: /* Vector Reciprocal Square Root Estimate Single-Precision */
|
|
|
7b26da |
+ case 1288: /* Vector AES Cipher */
|
|
|
7b26da |
+ case 1289: /* Vector AES Cipher Last */
|
|
|
7b26da |
+ case 1352: /* Vector AES Inverse Cipher */
|
|
|
7b26da |
+ case 1353: /* Vector AES Inverse Cipher Last */
|
|
|
7b26da |
+ case 1480: /* Vector AES SubBytes */
|
|
|
7b26da |
+ case 1730: /* Vector SHA-512 Sigma Doubleword */
|
|
|
7b26da |
+ case 1666: /* Vector SHA-256 Sigma Word */
|
|
|
7b26da |
+ case 1032: /* Vector Polynomial Multiply-Sum Byte */
|
|
|
7b26da |
+ case 1160: /* Vector Polynomial Multiply-Sum Word */
|
|
|
7b26da |
+ case 1096: /* Vector Polynomial Multiply-Sum Halfword */
|
|
|
7b26da |
+ case 1224: /* Vector Polynomial Multiply-Sum Doubleword */
|
|
|
7b26da |
+ case 1292: /* Vector Gather Bits by Bytes by Doubleword */
|
|
|
7b26da |
+ case 1794: /* Vector Count Leading Zeros Byte */
|
|
|
7b26da |
+ case 1858: /* Vector Count Leading Zeros Halfword */
|
|
|
7b26da |
+ case 1922: /* Vector Count Leading Zeros Word */
|
|
|
7b26da |
+ case 1986: /* Vector Count Leading Zeros Doubleword */
|
|
|
7b26da |
+ case 1795: /* Vector Population Count Byte */
|
|
|
7b26da |
+ case 1859: /* Vector Population Count Halfword */
|
|
|
7b26da |
+ case 1923: /* Vector Population Count Word */
|
|
|
7b26da |
+ case 1987: /* Vector Population Count Doubleword */
|
|
|
7b26da |
+ case 1356: /* Vector Bit Permute Quadword */
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache,
|
|
|
7b26da |
+ tdep->ppc_vr0_regnum + PPC_VRT (insn));
|
|
|
7b26da |
+ return 0;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ case 1604: /* Move To Vector Status and Control Register */
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, PPC_VSCR_REGNUM);
|
|
|
7b26da |
+ return 0;
|
|
|
7b26da |
+ case 1540: /* Move From Vector Status and Control Register */
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache,
|
|
|
7b26da |
+ tdep->ppc_vr0_regnum + PPC_VRT (insn));
|
|
|
7b26da |
+ return 0;
|
|
|
7b26da |
+ }
|
|
|
7b26da |
+
|
|
|
7b26da |
+ fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record "
|
|
|
7b26da |
+ "%08x at %08lx, 4-%d.\n", insn, addr, ext);
|
|
|
7b26da |
+ return -1;
|
|
|
7b26da |
+}
|
|
|
7b26da |
+
|
|
|
7b26da |
+/* Parse instructions of primary opcode-19. */
|
|
|
7b26da |
+
|
|
|
7b26da |
+static int
|
|
|
7b26da |
+ppc_process_record_op19 (struct gdbarch *gdbarch, struct regcache *regcache,
|
|
|
7b26da |
+ CORE_ADDR addr, uint32_t insn)
|
|
|
7b26da |
+{
|
|
|
7b26da |
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
|
|
|
7b26da |
+ int ext = PPC_EXTOP (insn);
|
|
|
7b26da |
+
|
|
|
7b26da |
+ switch (ext)
|
|
|
7b26da |
+ {
|
|
|
7b26da |
+ case 0: /* Move Condition Register Field */
|
|
|
7b26da |
+ case 33: /* Condition Register NOR */
|
|
|
7b26da |
+ case 129: /* Condition Register AND with Complement */
|
|
|
7b26da |
+ case 193: /* Condition Register XOR */
|
|
|
7b26da |
+ case 225: /* Condition Register NAND */
|
|
|
7b26da |
+ case 257: /* Condition Register AND */
|
|
|
7b26da |
+ case 289: /* Condition Register Equivalent */
|
|
|
7b26da |
+ case 417: /* Condition Register OR with Complement */
|
|
|
7b26da |
+ case 449: /* Condition Register OR */
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
|
|
|
7b26da |
+ return 0;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ case 16: /* Branch Conditional */
|
|
|
7b26da |
+ case 560: /* Branch Conditional to Branch Target Address Register */
|
|
|
7b26da |
+ if ((PPC_BO (insn) & 0x4) == 0)
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_ctr_regnum);
|
|
|
7b26da |
+ /* FALL-THROUGH */
|
|
|
7b26da |
+ case 528: /* Branch Conditional to Count Register */
|
|
|
7b26da |
+ if (PPC_LK (insn))
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_lr_regnum);
|
|
|
7b26da |
+ return 0;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ case 150: /* Instruction Synchronize */
|
|
|
7b26da |
+ /* Do nothing. */
|
|
|
7b26da |
+ return 0;
|
|
|
7b26da |
+ }
|
|
|
7b26da |
+
|
|
|
7b26da |
+ fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record "
|
|
|
7b26da |
+ "%08x at %08lx, 19-%d.\n", insn, addr, ext);
|
|
|
7b26da |
+ return -1;
|
|
|
7b26da |
+}
|
|
|
7b26da |
+
|
|
|
7b26da |
+/* Parse instructions of primary opcode-31. */
|
|
|
7b26da |
+
|
|
|
7b26da |
+static int
|
|
|
7b26da |
+ppc_process_record_op31 (struct gdbarch *gdbarch, struct regcache *regcache,
|
|
|
7b26da |
+ CORE_ADDR addr, uint32_t insn)
|
|
|
7b26da |
+{
|
|
|
7b26da |
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
|
|
|
7b26da |
+ int ext = PPC_EXTOP (insn);
|
|
|
7b26da |
+ int tmp, nr, nb, i;
|
|
|
7b26da |
+ CORE_ADDR at_dcsz, ea = 0;
|
|
|
7b26da |
+ ULONGEST rb, ra, xer;
|
|
|
7b26da |
+ int size = 0;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ /* These instructions have OE bit. */
|
|
|
7b26da |
+ switch (ext & 0x1ff)
|
|
|
7b26da |
+ {
|
|
|
7b26da |
+ /* These write RT and XER. Update CR if RC is set. */
|
|
|
7b26da |
+ case 8: /* Subtract from carrying */
|
|
|
7b26da |
+ case 10: /* Add carrying */
|
|
|
7b26da |
+ case 136: /* Subtract from extended */
|
|
|
7b26da |
+ case 138: /* Add extended */
|
|
|
7b26da |
+ case 200: /* Subtract from zero extended */
|
|
|
7b26da |
+ case 202: /* Add to zero extended */
|
|
|
7b26da |
+ case 232: /* Subtract from minus one extended */
|
|
|
7b26da |
+ case 234: /* Add to minus one extended */
|
|
|
7b26da |
+ /* CA is always altered, but SO/OV are only altered when OE=1.
|
|
|
7b26da |
+ In any case, XER is always altered. */
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum);
|
|
|
7b26da |
+ if (PPC_RC (insn))
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache,
|
|
|
7b26da |
+ tdep->ppc_gp0_regnum + PPC_RT (insn));
|
|
|
7b26da |
+ return 0;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ /* These write RT. Update CR if RC is set and update XER if OE is set. */
|
|
|
7b26da |
+ case 40: /* Subtract from */
|
|
|
7b26da |
+ case 104: /* Negate */
|
|
|
7b26da |
+ case 233: /* Multiply low doubleword */
|
|
|
7b26da |
+ case 235: /* Multiply low word */
|
|
|
7b26da |
+ case 266: /* Add */
|
|
|
7b26da |
+ case 393: /* Divide Doubleword Extended Unsigned */
|
|
|
7b26da |
+ case 395: /* Divide Word Extended Unsigned */
|
|
|
7b26da |
+ case 425: /* Divide Doubleword Extended */
|
|
|
7b26da |
+ case 427: /* Divide Word Extended */
|
|
|
7b26da |
+ case 457: /* Divide Doubleword Unsigned */
|
|
|
7b26da |
+ case 459: /* Divide Word Unsigned */
|
|
|
7b26da |
+ case 489: /* Divide Doubleword */
|
|
|
7b26da |
+ case 491: /* Divide Word */
|
|
|
7b26da |
+ if (PPC_OE (insn))
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum);
|
|
|
7b26da |
+ /* FALL-THROUGH */
|
|
|
7b26da |
+ case 9: /* Multiply High Doubleword Unsigned */
|
|
|
7b26da |
+ case 11: /* Multiply High Word Unsigned */
|
|
|
7b26da |
+ case 73: /* Multiply High Doubleword */
|
|
|
7b26da |
+ case 75: /* Multiply High Word */
|
|
|
7b26da |
+ if (PPC_RC (insn))
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache,
|
|
|
7b26da |
+ tdep->ppc_gp0_regnum + PPC_RT (insn));
|
|
|
7b26da |
+ return 0;
|
|
|
7b26da |
+ }
|
|
|
7b26da |
+
|
|
|
7b26da |
+ if ((ext & 0x1f) == 15)
|
|
|
7b26da |
+ {
|
|
|
7b26da |
+ /* Integer Select. bit[16:20] is used for BC. */
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache,
|
|
|
7b26da |
+ tdep->ppc_gp0_regnum + PPC_RT (insn));
|
|
|
7b26da |
+ return 0;
|
|
|
7b26da |
+ }
|
|
|
7b26da |
+
|
|
|
7b26da |
+ switch (ext)
|
|
|
7b26da |
+ {
|
|
|
7b26da |
+ case 78: /* Determine Leftmost Zero Byte */
|
|
|
7b26da |
+ if (PPC_RC (insn))
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum);
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache,
|
|
|
7b26da |
+ tdep->ppc_gp0_regnum + PPC_RT (insn));
|
|
|
7b26da |
+ return 0;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ /* These only write RT. */
|
|
|
7b26da |
+ case 19: /* Move from condition register */
|
|
|
7b26da |
+ /* Move From One Condition Register Field */
|
|
|
7b26da |
+ case 74: /* Add and Generate Sixes */
|
|
|
7b26da |
+ case 74 | 0x200: /* Add and Generate Sixes (bit-21 dont-care) */
|
|
|
7b26da |
+ case 302: /* Move From Branch History Rolling Buffer */
|
|
|
7b26da |
+ case 339: /* Move From Special Purpose Register */
|
|
|
7b26da |
+ case 371: /* Move From Time Base [Phased-Out] */
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache,
|
|
|
7b26da |
+ tdep->ppc_gp0_regnum + PPC_RT (insn));
|
|
|
7b26da |
+ return 0;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ /* These only write to RA. */
|
|
|
7b26da |
+ case 51: /* Move From VSR Doubleword */
|
|
|
7b26da |
+ case 115: /* Move From VSR Word and Zero */
|
|
|
7b26da |
+ case 122: /* Population count bytes */
|
|
|
7b26da |
+ case 378: /* Population count words */
|
|
|
7b26da |
+ case 506: /* Population count doublewords */
|
|
|
7b26da |
+ case 154: /* Parity Word */
|
|
|
7b26da |
+ case 186: /* Parity Doubleword */
|
|
|
7b26da |
+ case 252: /* Bit Permute Doubleword */
|
|
|
7b26da |
+ case 282: /* Convert Declets To Binary Coded Decimal */
|
|
|
7b26da |
+ case 314: /* Convert Binary Coded Decimal To Declets */
|
|
|
7b26da |
+ case 508: /* Compare bytes */
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache,
|
|
|
7b26da |
+ tdep->ppc_gp0_regnum + PPC_RA (insn));
|
|
|
7b26da |
+ return 0;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ /* These write CR and optional RA. */
|
|
|
7b26da |
+ case 792: /* Shift Right Algebraic Word */
|
|
|
7b26da |
+ case 794: /* Shift Right Algebraic Doubleword */
|
|
|
7b26da |
+ case 824: /* Shift Right Algebraic Word Immediate */
|
|
|
7b26da |
+ case 826: /* Shift Right Algebraic Doubleword Immediate (413) */
|
|
|
7b26da |
+ case 826 | 1: /* Shift Right Algebraic Doubleword Immediate (413) */
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum);
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache,
|
|
|
7b26da |
+ tdep->ppc_gp0_regnum + PPC_RA (insn));
|
|
|
7b26da |
+ /* FALL-THROUGH */
|
|
|
7b26da |
+ case 0: /* Compare */
|
|
|
7b26da |
+ case 32: /* Compare logical */
|
|
|
7b26da |
+ case 144: /* Move To Condition Register Fields */
|
|
|
7b26da |
+ /* Move To One Condition Register Field */
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
|
|
|
7b26da |
+ return 0;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ /* These write to RT. Update RA if 'update indexed.' */
|
|
|
7b26da |
+ case 53: /* Load Doubleword with Update Indexed */
|
|
|
7b26da |
+ case 119: /* Load Byte and Zero with Update Indexed */
|
|
|
7b26da |
+ case 311: /* Load Halfword and Zero with Update Indexed */
|
|
|
7b26da |
+ case 55: /* Load Word and Zero with Update Indexed */
|
|
|
7b26da |
+ case 375: /* Load Halfword Algebraic with Update Indexed */
|
|
|
7b26da |
+ case 373: /* Load Word Algebraic with Update Indexed */
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache,
|
|
|
7b26da |
+ tdep->ppc_gp0_regnum + PPC_RA (insn));
|
|
|
7b26da |
+ /* FALL-THROUGH */
|
|
|
7b26da |
+ case 21: /* Load Doubleword Indexed */
|
|
|
7b26da |
+ case 52: /* Load Byte And Reserve Indexed */
|
|
|
7b26da |
+ case 116: /* Load Halfword And Reserve Indexed */
|
|
|
7b26da |
+ case 20: /* Load Word And Reserve Indexed */
|
|
|
7b26da |
+ case 84: /* Load Doubleword And Reserve Indexed */
|
|
|
7b26da |
+ case 87: /* Load Byte and Zero Indexed */
|
|
|
7b26da |
+ case 279: /* Load Halfword and Zero Indexed */
|
|
|
7b26da |
+ case 23: /* Load Word and Zero Indexed */
|
|
|
7b26da |
+ case 343: /* Load Halfword Algebraic Indexed */
|
|
|
7b26da |
+ case 341: /* Load Word Algebraic Indexed */
|
|
|
7b26da |
+ case 790: /* Load Halfword Byte-Reverse Indexed */
|
|
|
7b26da |
+ case 534: /* Load Word Byte-Reverse Indexed */
|
|
|
7b26da |
+ case 532: /* Load Doubleword Byte-Reverse Indexed */
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache,
|
|
|
7b26da |
+ tdep->ppc_gp0_regnum + PPC_RT (insn));
|
|
|
7b26da |
+ return 0;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ case 597: /* Load String Word Immediate */
|
|
|
7b26da |
+ case 533: /* Load String Word Indexed */
|
|
|
7b26da |
+ if (ext == 597)
|
|
|
7b26da |
+ {
|
|
|
7b26da |
+ nr = PPC_NB (insn);
|
|
|
7b26da |
+ if (nr == 0)
|
|
|
7b26da |
+ nr = 32;
|
|
|
7b26da |
+ }
|
|
|
7b26da |
+ else
|
|
|
7b26da |
+ {
|
|
|
7b26da |
+ regcache_raw_read_unsigned (regcache, tdep->ppc_xer_regnum, &xer);
|
|
|
7b26da |
+ nr = PPC_XER_NB (xer);
|
|
|
7b26da |
+ }
|
|
|
7b26da |
+
|
|
|
7b26da |
+ nr = (nr + 3) >> 2;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ /* If n=0, the contents of register RT are undefined. */
|
|
|
7b26da |
+ if (nr == 0)
|
|
|
7b26da |
+ nr = 1;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ for (i = 0; i < nr; i++)
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache,
|
|
|
7b26da |
+ tdep->ppc_gp0_regnum
|
|
|
7b26da |
+ + ((PPC_RT (insn) + i) & 0x1f));
|
|
|
7b26da |
+ return 0;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ case 276: /* Load Quadword And Reserve Indexed */
|
|
|
7b26da |
+ tmp = tdep->ppc_gp0_regnum + (PPC_RT (insn) & ~1);
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tmp);
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tmp + 1);
|
|
|
7b26da |
+ return 0;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ /* These write VRT. */
|
|
|
7b26da |
+ case 6: /* Load Vector for Shift Left Indexed */
|
|
|
7b26da |
+ case 38: /* Load Vector for Shift Right Indexed */
|
|
|
7b26da |
+ case 7: /* Load Vector Element Byte Indexed */
|
|
|
7b26da |
+ case 39: /* Load Vector Element Halfword Indexed */
|
|
|
7b26da |
+ case 71: /* Load Vector Element Word Indexed */
|
|
|
7b26da |
+ case 103: /* Load Vector Indexed */
|
|
|
7b26da |
+ case 359: /* Load Vector Indexed LRU */
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache,
|
|
|
7b26da |
+ tdep->ppc_vr0_regnum + PPC_VRT (insn));
|
|
|
7b26da |
+ return 0;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ /* These write FRT. Update RA if 'update indexed.' */
|
|
|
7b26da |
+ case 567: /* Load Floating-Point Single with Update Indexed */
|
|
|
7b26da |
+ case 631: /* Load Floating-Point Double with Update Indexed */
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache,
|
|
|
7b26da |
+ tdep->ppc_gp0_regnum + PPC_RA (insn));
|
|
|
7b26da |
+ /* FALL-THROUGH */
|
|
|
7b26da |
+ case 535: /* Load Floating-Point Single Indexed */
|
|
|
7b26da |
+ case 599: /* Load Floating-Point Double Indexed */
|
|
|
7b26da |
+ case 855: /* Load Floating-Point as Integer Word Algebraic Indexed */
|
|
|
7b26da |
+ case 887: /* Load Floating-Point as Integer Word and Zero Indexed */
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache,
|
|
|
7b26da |
+ tdep->ppc_fp0_regnum + PPC_FRT (insn));
|
|
|
7b26da |
+ return 0;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ case 791: /* Load Floating-Point Double Pair Indexed */
|
|
|
7b26da |
+ tmp = tdep->ppc_fp0_regnum + (PPC_FRT (insn) & ~1);
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tmp);
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tmp + 1);
|
|
|
7b26da |
+ return 0;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ case 179: /* Move To VSR Doubleword */
|
|
|
7b26da |
+ case 211: /* Move To VSR Word Algebraic */
|
|
|
7b26da |
+ case 243: /* Move To VSR Word and Zero */
|
|
|
7b26da |
+ case 588: /* Load VSX Scalar Doubleword Indexed */
|
|
|
7b26da |
+ case 524: /* Load VSX Scalar Single-Precision Indexed */
|
|
|
7b26da |
+ case 76: /* Load VSX Scalar as Integer Word Algebraic Indexed */
|
|
|
7b26da |
+ case 12: /* Load VSX Scalar as Integer Word and Zero Indexed */
|
|
|
7b26da |
+ case 844: /* Load VSX Vector Doubleword*2 Indexed */
|
|
|
7b26da |
+ case 332: /* Load VSX Vector Doubleword & Splat Indexed */
|
|
|
7b26da |
+ case 780: /* Load VSX Vector Word*4 Indexed */
|
|
|
7b26da |
+ ppc_record_vsr (regcache, tdep, PPC_XT (insn));
|
|
|
7b26da |
+ return 0;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ /* These write RA. Update CR if RC is set. */
|
|
|
7b26da |
+ case 24: /* Shift Left Word */
|
|
|
7b26da |
+ case 26: /* Count Leading Zeros Word */
|
|
|
7b26da |
+ case 27: /* Shift Left Doubleword */
|
|
|
7b26da |
+ case 28: /* AND */
|
|
|
7b26da |
+ case 58: /* Count Leading Zeros Doubleword */
|
|
|
7b26da |
+ case 60: /* AND with Complement */
|
|
|
7b26da |
+ case 124: /* NOR */
|
|
|
7b26da |
+ case 284: /* Equivalent */
|
|
|
7b26da |
+ case 316: /* XOR */
|
|
|
7b26da |
+ case 476: /* NAND */
|
|
|
7b26da |
+ case 412: /* OR with Complement */
|
|
|
7b26da |
+ case 444: /* OR */
|
|
|
7b26da |
+ case 536: /* Shift Right Word */
|
|
|
7b26da |
+ case 539: /* Shift Right Doubleword */
|
|
|
7b26da |
+ case 922: /* Extend Sign Halfword */
|
|
|
7b26da |
+ case 954: /* Extend Sign Byte */
|
|
|
7b26da |
+ case 986: /* Extend Sign Word */
|
|
|
7b26da |
+ if (PPC_RC (insn))
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache,
|
|
|
7b26da |
+ tdep->ppc_gp0_regnum + PPC_RA (insn));
|
|
|
7b26da |
+ return 0;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ /* Store memory. */
|
|
|
7b26da |
+ case 181: /* Store Doubleword with Update Indexed */
|
|
|
7b26da |
+ case 183: /* Store Word with Update Indexed */
|
|
|
7b26da |
+ case 247: /* Store Byte with Update Indexed */
|
|
|
7b26da |
+ case 439: /* Store Half Word with Update Indexed */
|
|
|
7b26da |
+ case 695: /* Store Floating-Point Single with Update Indexed */
|
|
|
7b26da |
+ case 759: /* Store Floating-Point Double with Update Indexed */
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache,
|
|
|
7b26da |
+ tdep->ppc_gp0_regnum + PPC_RA (insn));
|
|
|
7b26da |
+ /* FALL-THROUGH */
|
|
|
7b26da |
+ case 135: /* Store Vector Element Byte Indexed */
|
|
|
7b26da |
+ case 167: /* Store Vector Element Halfword Indexed */
|
|
|
7b26da |
+ case 199: /* Store Vector Element Word Indexed */
|
|
|
7b26da |
+ case 231: /* Store Vector Indexed */
|
|
|
7b26da |
+ case 487: /* Store Vector Indexed LRU */
|
|
|
7b26da |
+ case 716: /* Store VSX Scalar Doubleword Indexed */
|
|
|
7b26da |
+ case 140: /* Store VSX Scalar as Integer Word Indexed */
|
|
|
7b26da |
+ case 652: /* Store VSX Scalar Single-Precision Indexed */
|
|
|
7b26da |
+ case 972: /* Store VSX Vector Doubleword*2 Indexed */
|
|
|
7b26da |
+ case 908: /* Store VSX Vector Word*4 Indexed */
|
|
|
7b26da |
+ case 149: /* Store Doubleword Indexed */
|
|
|
7b26da |
+ case 151: /* Store Word Indexed */
|
|
|
7b26da |
+ case 215: /* Store Byte Indexed */
|
|
|
7b26da |
+ case 407: /* Store Half Word Indexed */
|
|
|
7b26da |
+ case 694: /* Store Byte Conditional Indexed */
|
|
|
7b26da |
+ case 726: /* Store Halfword Conditional Indexed */
|
|
|
7b26da |
+ case 150: /* Store Word Conditional Indexed */
|
|
|
7b26da |
+ case 214: /* Store Doubleword Conditional Indexed */
|
|
|
7b26da |
+ case 182: /* Store Quadword Conditional Indexed */
|
|
|
7b26da |
+ case 662: /* Store Word Byte-Reverse Indexed */
|
|
|
7b26da |
+ case 918: /* Store Halfword Byte-Reverse Indexed */
|
|
|
7b26da |
+ case 660: /* Store Doubleword Byte-Reverse Indexed */
|
|
|
7b26da |
+ case 663: /* Store Floating-Point Single Indexed */
|
|
|
7b26da |
+ case 727: /* Store Floating-Point Double Indexed */
|
|
|
7b26da |
+ case 919: /* Store Floating-Point Double Pair Indexed */
|
|
|
7b26da |
+ case 983: /* Store Floating-Point as Integer Word Indexed */
|
|
|
7b26da |
+ if (ext == 694 || ext == 726 || ext == 150 || ext == 214 || ext == 182)
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
|
|
|
7b26da |
+
|
|
|
7b26da |
+ ra = 0;
|
|
|
7b26da |
+ if (PPC_RA (insn) != 0)
|
|
|
7b26da |
+ regcache_raw_read_unsigned (regcache,
|
|
|
7b26da |
+ tdep->ppc_gp0_regnum + PPC_RA (insn), &ra);
|
|
|
7b26da |
+ regcache_raw_read_unsigned (regcache,
|
|
|
7b26da |
+ tdep->ppc_gp0_regnum + PPC_RB (insn), &rb);
|
|
|
7b26da |
+ ea = ra + rb;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ switch (ext)
|
|
|
7b26da |
+ {
|
|
|
7b26da |
+ case 183: /* Store Word with Update Indexed */
|
|
|
7b26da |
+ case 199: /* Store Vector Element Word Indexed */
|
|
|
7b26da |
+ case 140: /* Store VSX Scalar as Integer Word Indexed */
|
|
|
7b26da |
+ case 652: /* Store VSX Scalar Single-Precision Indexed */
|
|
|
7b26da |
+ case 151: /* Store Word Indexed */
|
|
|
7b26da |
+ case 150: /* Store Word Conditional Indexed */
|
|
|
7b26da |
+ case 662: /* Store Word Byte-Reverse Indexed */
|
|
|
7b26da |
+ case 663: /* Store Floating-Point Single Indexed */
|
|
|
7b26da |
+ case 695: /* Store Floating-Point Single with Update Indexed */
|
|
|
7b26da |
+ case 983: /* Store Floating-Point as Integer Word Indexed */
|
|
|
7b26da |
+ size = 4;
|
|
|
7b26da |
+ break;
|
|
|
7b26da |
+ case 247: /* Store Byte with Update Indexed */
|
|
|
7b26da |
+ case 135: /* Store Vector Element Byte Indexed */
|
|
|
7b26da |
+ case 215: /* Store Byte Indexed */
|
|
|
7b26da |
+ case 694: /* Store Byte Conditional Indexed */
|
|
|
7b26da |
+ size = 1;
|
|
|
7b26da |
+ break;
|
|
|
7b26da |
+ case 439: /* Store Halfword with Update Indexed */
|
|
|
7b26da |
+ case 167: /* Store Vector Element Halfword Indexed */
|
|
|
7b26da |
+ case 407: /* Store Halfword Indexed */
|
|
|
7b26da |
+ case 726: /* Store Halfword Conditional Indexed */
|
|
|
7b26da |
+ case 918: /* Store Halfword Byte-Reverse Indexed */
|
|
|
7b26da |
+ size = 2;
|
|
|
7b26da |
+ break;
|
|
|
7b26da |
+ case 181: /* Store Doubleword with Update Indexed */
|
|
|
7b26da |
+ case 716: /* Store VSX Scalar Doubleword Indexed */
|
|
|
7b26da |
+ case 149: /* Store Doubleword Indexed */
|
|
|
7b26da |
+ case 214: /* Store Doubleword Conditional Indexed */
|
|
|
7b26da |
+ case 660: /* Store Doubleword Byte-Reverse Indexed */
|
|
|
7b26da |
+ case 727: /* Store Floating-Point Double Indexed */
|
|
|
7b26da |
+ case 759: /* Store Floating-Point Double with Update Indexed */
|
|
|
7b26da |
+ size = 8;
|
|
|
7b26da |
+ break;
|
|
|
7b26da |
+ case 972: /* Store VSX Vector Doubleword*2 Indexed */
|
|
|
7b26da |
+ case 908: /* Store VSX Vector Word*4 Indexed */
|
|
|
7b26da |
+ case 182: /* Store Quadword Conditional Indexed */
|
|
|
7b26da |
+ case 231: /* Store Vector Indexed */
|
|
|
7b26da |
+ case 487: /* Store Vector Indexed LRU */
|
|
|
7b26da |
+ case 919: /* Store Floating-Point Double Pair Indexed */
|
|
|
7b26da |
+ size = 16;
|
|
|
7b26da |
+ break;
|
|
|
7b26da |
+ default:
|
|
|
7b26da |
+ gdb_assert (0);
|
|
|
7b26da |
+ }
|
|
|
7b26da |
+
|
|
|
7b26da |
+ /* Align address for Store Vector instructions. */
|
|
|
7b26da |
+ switch (ext)
|
|
|
7b26da |
+ {
|
|
|
7b26da |
+ case 167: /* Store Vector Element Halfword Indexed */
|
|
|
7b26da |
+ addr = addr & ~0x1ULL;
|
|
|
7b26da |
+ break;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ case 199: /* Store Vector Element Word Indexed */
|
|
|
7b26da |
+ addr = addr & ~0x3ULL;
|
|
|
7b26da |
+ break;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ case 231: /* Store Vector Indexed */
|
|
|
7b26da |
+ case 487: /* Store Vector Indexed LRU */
|
|
|
7b26da |
+ addr = addr & ~0xfULL;
|
|
|
7b26da |
+ break;
|
|
|
7b26da |
+ }
|
|
|
7b26da |
+
|
|
|
7b26da |
+ if (record_full_arch_list_add_mem (addr, size) != 0)
|
|
|
7b26da |
+ return -1;
|
|
|
7b26da |
+ return 0;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ case 725: /* Store String Word Immediate */
|
|
|
7b26da |
+ ra = 0;
|
|
|
7b26da |
+ if (PPC_RA (insn) != 0)
|
|
|
7b26da |
+ regcache_raw_read_unsigned (regcache, tdep->ppc_xer_regnum, &ra);
|
|
|
7b26da |
+ ea += ra;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ nb = PPC_NB (insn);
|
|
|
7b26da |
+ if (nb == 0)
|
|
|
7b26da |
+ nb = 32;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ if (record_full_arch_list_add_mem (ea, nb) != 0)
|
|
|
7b26da |
+ return -1;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ return 0;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ case 661: /* Store String Word Indexed */
|
|
|
7b26da |
+ ra = 0;
|
|
|
7b26da |
+ if (PPC_RA (insn) != 0)
|
|
|
7b26da |
+ regcache_raw_read_unsigned (regcache, tdep->ppc_xer_regnum, &ra);
|
|
|
7b26da |
+ ea += ra;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ regcache_raw_read_unsigned (regcache, tdep->ppc_xer_regnum, &xer);
|
|
|
7b26da |
+ nb = PPC_XER_NB (xer);
|
|
|
7b26da |
+
|
|
|
7b26da |
+ if (nb != 0)
|
|
|
7b26da |
+ {
|
|
|
7b26da |
+ regcache_raw_read_unsigned (regcache, tdep->ppc_xer_regnum, &rb);
|
|
|
7b26da |
+ ea += rb;
|
|
|
7b26da |
+ if (record_full_arch_list_add_mem (ea, nb) != 0)
|
|
|
7b26da |
+ return -1;
|
|
|
7b26da |
+ }
|
|
|
7b26da |
+
|
|
|
7b26da |
+ return 0;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ case 467: /* Move To Special Purpose Register */
|
|
|
7b26da |
+ switch (PPC_SPR (insn))
|
|
|
7b26da |
+ {
|
|
|
7b26da |
+ case 1: /* XER */
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum);
|
|
|
7b26da |
+ return 0;
|
|
|
7b26da |
+ case 8: /* LR */
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_lr_regnum);
|
|
|
7b26da |
+ return 0;
|
|
|
7b26da |
+ case 9: /* CTR */
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_ctr_regnum);
|
|
|
7b26da |
+ return 0;
|
|
|
7b26da |
+ case 256: /* VRSAVE */
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_vrsave_regnum);
|
|
|
7b26da |
+ return 0;
|
|
|
7b26da |
+ }
|
|
|
7b26da |
+
|
|
|
7b26da |
+ goto UNKNOWN_OP;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ case 147: /* Move To Split Little Endian */
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_ps_regnum);
|
|
|
7b26da |
+ return 0;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ case 512: /* Move to Condition Register from XER */
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum);
|
|
|
7b26da |
+ return 0;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ case 4: /* Trap Word */
|
|
|
7b26da |
+ case 68: /* Trap Doubleword */
|
|
|
7b26da |
+ case 430: /* Clear BHRB */
|
|
|
7b26da |
+ case 598: /* Synchronize */
|
|
|
7b26da |
+ case 62: /* Wait for Interrupt */
|
|
|
7b26da |
+ case 22: /* Instruction Cache Block Touch */
|
|
|
7b26da |
+ case 854: /* Enforce In-order Execution of I/O */
|
|
|
7b26da |
+ case 246: /* Data Cache Block Touch for Store */
|
|
|
7b26da |
+ case 54: /* Data Cache Block Store */
|
|
|
7b26da |
+ case 86: /* Data Cache Block Flush */
|
|
|
7b26da |
+ case 278: /* Data Cache Block Touch */
|
|
|
7b26da |
+ case 758: /* Data Cache Block Allocate */
|
|
|
7b26da |
+ case 982: /* Instruction Cache Block Invalidate */
|
|
|
7b26da |
+ return 0;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ case 654: /* Transaction Begin */
|
|
|
7b26da |
+ case 686: /* Transaction End */
|
|
|
7b26da |
+ case 718: /* Transaction Check */
|
|
|
7b26da |
+ case 750: /* Transaction Suspend or Resume */
|
|
|
7b26da |
+ case 782: /* Transaction Abort Word Conditional */
|
|
|
7b26da |
+ case 814: /* Transaction Abort Doubleword Conditional */
|
|
|
7b26da |
+ case 846: /* Transaction Abort Word Conditional Immediate */
|
|
|
7b26da |
+ case 878: /* Transaction Abort Doubleword Conditional Immediate */
|
|
|
7b26da |
+ case 910: /* Transaction Abort */
|
|
|
7b26da |
+ fprintf_unfiltered (gdb_stdlog, "Cannot record Transaction instructions. "
|
|
|
7b26da |
+ "%08x at %08lx, 31-%d.\n", insn, addr, ext);
|
|
|
7b26da |
+ return -1;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ case 1014: /* Data Cache Block set to Zero */
|
|
|
7b26da |
+ if (target_auxv_search (¤t_target, AT_DCACHEBSIZE, &at_dcsz) <= 0
|
|
|
7b26da |
+ || at_dcsz == 0)
|
|
|
7b26da |
+ at_dcsz = 128; /* Assume 128-byte cache line size (POWER8) */
|
|
|
7b26da |
+
|
|
|
7b26da |
+ ra = 0;
|
|
|
7b26da |
+ if (PPC_RA (insn) != 0)
|
|
|
7b26da |
+ regcache_raw_read_unsigned (regcache,
|
|
|
7b26da |
+ tdep->ppc_gp0_regnum + PPC_RA (insn), &ra);
|
|
|
7b26da |
+ regcache_raw_read_unsigned (regcache,
|
|
|
7b26da |
+ tdep->ppc_gp0_regnum + PPC_RB (insn), &rb);
|
|
|
7b26da |
+ ea = (ra + rb) & ~((ULONGEST) (at_dcsz - 1));
|
|
|
7b26da |
+ if (record_full_arch_list_add_mem (ea, at_dcsz) != 0)
|
|
|
7b26da |
+ return -1;
|
|
|
7b26da |
+ return 0;
|
|
|
7b26da |
+ }
|
|
|
7b26da |
+
|
|
|
7b26da |
+UNKNOWN_OP:
|
|
|
7b26da |
+ fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record "
|
|
|
7b26da |
+ "%08x at %08lx, 31-%d.\n", insn, addr, ext);
|
|
|
7b26da |
+ return -1;
|
|
|
7b26da |
+}
|
|
|
7b26da |
+
|
|
|
7b26da |
+/* Parse instructions of primary opcode-59. */
|
|
|
7b26da |
+
|
|
|
7b26da |
+static int
|
|
|
7b26da |
+ppc_process_record_op59 (struct gdbarch *gdbarch, struct regcache *regcache,
|
|
|
7b26da |
+ CORE_ADDR addr, uint32_t insn)
|
|
|
7b26da |
+{
|
|
|
7b26da |
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
|
|
|
7b26da |
+ int ext = PPC_EXTOP (insn);
|
|
|
7b26da |
+
|
|
|
7b26da |
+ switch (ext & 0x1f)
|
|
|
7b26da |
+ {
|
|
|
7b26da |
+ case 18: /* Floating Divide */
|
|
|
7b26da |
+ case 20: /* Floating Subtract */
|
|
|
7b26da |
+ case 21: /* Floating Add */
|
|
|
7b26da |
+ case 22: /* Floating Square Root */
|
|
|
7b26da |
+ case 24: /* Floating Reciprocal Estimate */
|
|
|
7b26da |
+ case 25: /* Floating Multiply */
|
|
|
7b26da |
+ case 26: /* Floating Reciprocal Square Root Estimate */
|
|
|
7b26da |
+ case 28: /* Floating Multiply-Subtract */
|
|
|
7b26da |
+ case 29: /* Floating Multiply-Add */
|
|
|
7b26da |
+ case 30: /* Floating Negative Multiply-Subtract */
|
|
|
7b26da |
+ case 31: /* Floating Negative Multiply-Add */
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache,
|
|
|
7b26da |
+ tdep->ppc_fp0_regnum + PPC_FRT (insn));
|
|
|
7b26da |
+ if (PPC_RC (insn))
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
|
|
|
7b26da |
+
|
|
|
7b26da |
+ return 0;
|
|
|
7b26da |
+ }
|
|
|
7b26da |
+
|
|
|
7b26da |
+ switch (ext)
|
|
|
7b26da |
+ {
|
|
|
7b26da |
+ case 2: /* DFP Add */
|
|
|
7b26da |
+ case 3: /* DFP Quantize */
|
|
|
7b26da |
+ case 34: /* DFP Multiply */
|
|
|
7b26da |
+ case 35: /* DFP Reround */
|
|
|
7b26da |
+ case 67: /* DFP Quantize Immediate */
|
|
|
7b26da |
+ case 99: /* DFP Round To FP Integer With Inexact */
|
|
|
7b26da |
+ case 227: /* DFP Round To FP Integer Without Inexact */
|
|
|
7b26da |
+ case 258: /* DFP Convert To DFP Long! */
|
|
|
7b26da |
+ case 290: /* DFP Convert To Fixed */
|
|
|
7b26da |
+ case 514: /* DFP Subtract */
|
|
|
7b26da |
+ case 546: /* DFP Divide */
|
|
|
7b26da |
+ case 770: /* DFP Round To DFP Short! */
|
|
|
7b26da |
+ case 802: /* DFP Convert From Fixed */
|
|
|
7b26da |
+ case 834: /* DFP Encode BCD To DPD */
|
|
|
7b26da |
+ if (PPC_RC (insn))
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache,
|
|
|
7b26da |
+ tdep->ppc_fp0_regnum + PPC_FRT (insn));
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
|
|
|
7b26da |
+ return 0;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ case 130: /* DFP Compare Ordered */
|
|
|
7b26da |
+ case 162: /* DFP Test Exponent */
|
|
|
7b26da |
+ case 194: /* DFP Test Data Class */
|
|
|
7b26da |
+ case 226: /* DFP Test Data Group */
|
|
|
7b26da |
+ case 642: /* DFP Compare Unordered */
|
|
|
7b26da |
+ case 674: /* DFP Test Significance */
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
|
|
|
7b26da |
+ return 0;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ case 66: /* DFP Shift Significand Left Immediate */
|
|
|
7b26da |
+ case 98: /* DFP Shift Significand Right Immediate */
|
|
|
7b26da |
+ case 322: /* DFP Decode DPD To BCD */
|
|
|
7b26da |
+ case 354: /* DFP Extract Biased Exponent */
|
|
|
7b26da |
+ case 866: /* DFP Insert Biased Exponent */
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache,
|
|
|
7b26da |
+ tdep->ppc_fp0_regnum + PPC_FRT (insn));
|
|
|
7b26da |
+ if (PPC_RC (insn))
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
|
|
|
7b26da |
+ return 0;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ case 846: /* Floating Convert From Integer Doubleword Single */
|
|
|
7b26da |
+ case 974: /* Floating Convert From Integer Doubleword Unsigned
|
|
|
7b26da |
+ Single */
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache,
|
|
|
7b26da |
+ tdep->ppc_fp0_regnum + PPC_FRT (insn));
|
|
|
7b26da |
+ if (PPC_RC (insn))
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
|
|
|
7b26da |
+
|
|
|
7b26da |
+ return 0;
|
|
|
7b26da |
+ }
|
|
|
7b26da |
+
|
|
|
7b26da |
+ fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record "
|
|
|
7b26da |
+ "%08x at %08lx, 59-%d.\n", insn, addr, ext);
|
|
|
7b26da |
+ return -1;
|
|
|
7b26da |
+}
|
|
|
7b26da |
+
|
|
|
7b26da |
+/* Parse instructions of primary opcode-60. */
|
|
|
7b26da |
+
|
|
|
7b26da |
+static int
|
|
|
7b26da |
+ppc_process_record_op60 (struct gdbarch *gdbarch, struct regcache *regcache,
|
|
|
7b26da |
+ CORE_ADDR addr, uint32_t insn)
|
|
|
7b26da |
+{
|
|
|
7b26da |
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
|
|
|
7b26da |
+ int ext = PPC_EXTOP (insn);
|
|
|
7b26da |
+ int tmp;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ switch (ext >> 2)
|
|
|
7b26da |
+ {
|
|
|
7b26da |
+ case 0: /* VSX Scalar Add Single-Precision */
|
|
|
7b26da |
+ case 32: /* VSX Scalar Add Double-Precision */
|
|
|
7b26da |
+ case 24: /* VSX Scalar Divide Single-Precision */
|
|
|
7b26da |
+ case 56: /* VSX Scalar Divide Double-Precision */
|
|
|
7b26da |
+ case 176: /* VSX Scalar Copy Sign Double-Precision */
|
|
|
7b26da |
+ case 33: /* VSX Scalar Multiply-Add Double-Precision */
|
|
|
7b26da |
+ case 41: /* ditto */
|
|
|
7b26da |
+ case 1: /* VSX Scalar Multiply-Add Single-Precision */
|
|
|
7b26da |
+ case 9: /* ditto */
|
|
|
7b26da |
+ case 160: /* VSX Scalar Maximum Double-Precision */
|
|
|
7b26da |
+ case 168: /* VSX Scalar Minimum Double-Precision */
|
|
|
7b26da |
+ case 49: /* VSX Scalar Multiply-Subtract Double-Precision */
|
|
|
7b26da |
+ case 57: /* ditto */
|
|
|
7b26da |
+ case 17: /* VSX Scalar Multiply-Subtract Single-Precision */
|
|
|
7b26da |
+ case 25: /* ditto */
|
|
|
7b26da |
+ case 48: /* VSX Scalar Multiply Double-Precision */
|
|
|
7b26da |
+ case 16: /* VSX Scalar Multiply Single-Precision */
|
|
|
7b26da |
+ case 161: /* VSX Scalar Negative Multiply-Add Double-Precision */
|
|
|
7b26da |
+ case 169: /* ditto */
|
|
|
7b26da |
+ case 129: /* VSX Scalar Negative Multiply-Add Single-Precision */
|
|
|
7b26da |
+ case 137: /* ditto */
|
|
|
7b26da |
+ case 177: /* VSX Scalar Negative Multiply-Subtract Double-Precision */
|
|
|
7b26da |
+ case 185: /* ditto */
|
|
|
7b26da |
+ case 145: /* VSX Scalar Negative Multiply-Subtract Single-Precision */
|
|
|
7b26da |
+ case 153: /* ditto */
|
|
|
7b26da |
+ case 40: /* VSX Scalar Subtract Double-Precision */
|
|
|
7b26da |
+ case 8: /* VSX Scalar Subtract Single-Precision */
|
|
|
7b26da |
+ case 96: /* VSX Vector Add Double-Precision */
|
|
|
7b26da |
+ case 64: /* VSX Vector Add Single-Precision */
|
|
|
7b26da |
+ case 120: /* VSX Vector Divide Double-Precision */
|
|
|
7b26da |
+ case 88: /* VSX Vector Divide Single-Precision */
|
|
|
7b26da |
+ case 97: /* VSX Vector Multiply-Add Double-Precision */
|
|
|
7b26da |
+ case 105: /* ditto */
|
|
|
7b26da |
+ case 65: /* VSX Vector Multiply-Add Single-Precision */
|
|
|
7b26da |
+ case 73: /* ditto */
|
|
|
7b26da |
+ case 224: /* VSX Vector Maximum Double-Precision */
|
|
|
7b26da |
+ case 192: /* VSX Vector Maximum Single-Precision */
|
|
|
7b26da |
+ case 232: /* VSX Vector Minimum Double-Precision */
|
|
|
7b26da |
+ case 200: /* VSX Vector Minimum Single-Precision */
|
|
|
7b26da |
+ case 113: /* VSX Vector Multiply-Subtract Double-Precision */
|
|
|
7b26da |
+ case 121: /* ditto */
|
|
|
7b26da |
+ case 81: /* VSX Vector Multiply-Subtract Single-Precision */
|
|
|
7b26da |
+ case 89: /* ditto */
|
|
|
7b26da |
+ case 112: /* VSX Vector Multiply Double-Precision */
|
|
|
7b26da |
+ case 80: /* VSX Vector Multiply Single-Precision */
|
|
|
7b26da |
+ case 225: /* VSX Vector Negative Multiply-Add Double-Precision */
|
|
|
7b26da |
+ case 233: /* ditto */
|
|
|
7b26da |
+ case 193: /* VSX Vector Negative Multiply-Add Single-Precision */
|
|
|
7b26da |
+ case 201: /* ditto */
|
|
|
7b26da |
+ case 241: /* VSX Vector Negative Multiply-Subtract Double-Precision */
|
|
|
7b26da |
+ case 249: /* ditto */
|
|
|
7b26da |
+ case 209: /* VSX Vector Negative Multiply-Subtract Single-Precision */
|
|
|
7b26da |
+ case 217: /* ditto */
|
|
|
7b26da |
+ case 104: /* VSX Vector Subtract Double-Precision */
|
|
|
7b26da |
+ case 72: /* VSX Vector Subtract Single-Precision */
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
|
|
|
7b26da |
+ case 240: /* VSX Vector Copy Sign Double-Precision */
|
|
|
7b26da |
+ case 208: /* VSX Vector Copy Sign Single-Precision */
|
|
|
7b26da |
+ case 130: /* VSX Logical AND */
|
|
|
7b26da |
+ case 138: /* VSX Logical AND with Complement */
|
|
|
7b26da |
+ case 186: /* VSX Logical Equivalence */
|
|
|
7b26da |
+ case 178: /* VSX Logical NAND */
|
|
|
7b26da |
+ case 170: /* VSX Logical OR with Complement */
|
|
|
7b26da |
+ case 162: /* VSX Logical NOR */
|
|
|
7b26da |
+ case 146: /* VSX Logical OR */
|
|
|
7b26da |
+ case 154: /* VSX Logical XOR */
|
|
|
7b26da |
+ case 18: /* VSX Merge High Word */
|
|
|
7b26da |
+ case 50: /* VSX Merge Low Word */
|
|
|
7b26da |
+ case 10: /* VSX Permute Doubleword Immediate (DM=0) */
|
|
|
7b26da |
+ case 10 | 0x20: /* VSX Permute Doubleword Immediate (DM=1) */
|
|
|
7b26da |
+ case 10 | 0x40: /* VSX Permute Doubleword Immediate (DM=2) */
|
|
|
7b26da |
+ case 10 | 0x60: /* VSX Permute Doubleword Immediate (DM=3) */
|
|
|
7b26da |
+ case 2: /* VSX Shift Left Double by Word Immediate (SHW=0) */
|
|
|
7b26da |
+ case 2 | 0x20: /* VSX Shift Left Double by Word Immediate (SHW=1) */
|
|
|
7b26da |
+ case 2 | 0x40: /* VSX Shift Left Double by Word Immediate (SHW=2) */
|
|
|
7b26da |
+ case 2 | 0x60: /* VSX Shift Left Double by Word Immediate (SHW=3) */
|
|
|
7b26da |
+ ppc_record_vsr (regcache, tdep, PPC_XT (insn));
|
|
|
7b26da |
+ return 0;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ case 61: /* VSX Scalar Test for software Divide Double-Precision */
|
|
|
7b26da |
+ case 125: /* VSX Vector Test for software Divide Double-Precision */
|
|
|
7b26da |
+ case 93: /* VSX Vector Test for software Divide Single-Precision */
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
|
|
|
7b26da |
+ return 0;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ case 35: /* VSX Scalar Compare Unordered Double-Precision */
|
|
|
7b26da |
+ case 43: /* VSX Scalar Compare Ordered Double-Precision */
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
|
|
|
7b26da |
+ return 0;
|
|
|
7b26da |
+ }
|
|
|
7b26da |
+
|
|
|
7b26da |
+ switch ((ext >> 2) & 0x7f) /* Mask out Rc-bit. */
|
|
|
7b26da |
+ {
|
|
|
7b26da |
+ case 99: /* VSX Vector Compare Equal To Double-Precision */
|
|
|
7b26da |
+ case 67: /* VSX Vector Compare Equal To Single-Precision */
|
|
|
7b26da |
+ case 115: /* VSX Vector Compare Greater Than or
|
|
|
7b26da |
+ Equal To Double-Precision */
|
|
|
7b26da |
+ case 83: /* VSX Vector Compare Greater Than or
|
|
|
7b26da |
+ Equal To Single-Precision */
|
|
|
7b26da |
+ case 107: /* VSX Vector Compare Greater Than Double-Precision */
|
|
|
7b26da |
+ case 75: /* VSX Vector Compare Greater Than Single-Precision */
|
|
|
7b26da |
+ if (PPC_Rc (insn))
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
|
|
|
7b26da |
+ ppc_record_vsr (regcache, tdep, PPC_XT (insn));
|
|
|
7b26da |
+ return 0;
|
|
|
7b26da |
+ }
|
|
|
7b26da |
+
|
|
|
7b26da |
+ switch (ext >> 1)
|
|
|
7b26da |
+ {
|
|
|
7b26da |
+ case 265: /* VSX Scalar round Double-Precision to
|
|
|
7b26da |
+ Single-Precision and Convert to
|
|
|
7b26da |
+ Single-Precision format */
|
|
|
7b26da |
+ case 344: /* VSX Scalar truncate Double-Precision to
|
|
|
7b26da |
+ Integer and Convert to Signed Integer
|
|
|
7b26da |
+ Doubleword format with Saturate */
|
|
|
7b26da |
+ case 88: /* VSX Scalar truncate Double-Precision to
|
|
|
7b26da |
+ Integer and Convert to Signed Integer Word
|
|
|
7b26da |
+ Format with Saturate */
|
|
|
7b26da |
+ case 328: /* VSX Scalar truncate Double-Precision integer
|
|
|
7b26da |
+ and Convert to Unsigned Integer Doubleword
|
|
|
7b26da |
+ Format with Saturate */
|
|
|
7b26da |
+ case 72: /* VSX Scalar truncate Double-Precision to
|
|
|
7b26da |
+ Integer and Convert to Unsigned Integer Word
|
|
|
7b26da |
+ Format with Saturate */
|
|
|
7b26da |
+ case 329: /* VSX Scalar Convert Single-Precision to
|
|
|
7b26da |
+ Double-Precision format */
|
|
|
7b26da |
+ case 376: /* VSX Scalar Convert Signed Integer
|
|
|
7b26da |
+ Doubleword to floating-point format and
|
|
|
7b26da |
+ Round to Double-Precision format */
|
|
|
7b26da |
+ case 312: /* VSX Scalar Convert Signed Integer
|
|
|
7b26da |
+ Doubleword to floating-point format and
|
|
|
7b26da |
+ round to Single-Precision */
|
|
|
7b26da |
+ case 360: /* VSX Scalar Convert Unsigned Integer
|
|
|
7b26da |
+ Doubleword to floating-point format and
|
|
|
7b26da |
+ Round to Double-Precision format */
|
|
|
7b26da |
+ case 296: /* VSX Scalar Convert Unsigned Integer
|
|
|
7b26da |
+ Doubleword to floating-point format and
|
|
|
7b26da |
+ Round to Single-Precision */
|
|
|
7b26da |
+ case 73: /* VSX Scalar Round to Double-Precision Integer
|
|
|
7b26da |
+ Using Round to Nearest Away */
|
|
|
7b26da |
+ case 107: /* VSX Scalar Round to Double-Precision Integer
|
|
|
7b26da |
+ Exact using Current rounding mode */
|
|
|
7b26da |
+ case 121: /* VSX Scalar Round to Double-Precision Integer
|
|
|
7b26da |
+ Using Round toward -Infinity */
|
|
|
7b26da |
+ case 105: /* VSX Scalar Round to Double-Precision Integer
|
|
|
7b26da |
+ Using Round toward +Infinity */
|
|
|
7b26da |
+ case 89: /* VSX Scalar Round to Double-Precision Integer
|
|
|
7b26da |
+ Using Round toward Zero */
|
|
|
7b26da |
+ case 90: /* VSX Scalar Reciprocal Estimate Double-Precision */
|
|
|
7b26da |
+ case 26: /* VSX Scalar Reciprocal Estimate Single-Precision */
|
|
|
7b26da |
+ case 281: /* VSX Scalar Round to Single-Precision */
|
|
|
7b26da |
+ case 74: /* VSX Scalar Reciprocal Square Root Estimate
|
|
|
7b26da |
+ Double-Precision */
|
|
|
7b26da |
+ case 10: /* VSX Scalar Reciprocal Square Root Estimate
|
|
|
7b26da |
+ Single-Precision */
|
|
|
7b26da |
+ case 75: /* VSX Scalar Square Root Double-Precision */
|
|
|
7b26da |
+ case 11: /* VSX Scalar Square Root Single-Precision */
|
|
|
7b26da |
+ case 393: /* VSX Vector round Double-Precision to
|
|
|
7b26da |
+ Single-Precision and Convert to
|
|
|
7b26da |
+ Single-Precision format */
|
|
|
7b26da |
+ case 472: /* VSX Vector truncate Double-Precision to
|
|
|
7b26da |
+ Integer and Convert to Signed Integer
|
|
|
7b26da |
+ Doubleword format with Saturate */
|
|
|
7b26da |
+ case 216: /* VSX Vector truncate Double-Precision to
|
|
|
7b26da |
+ Integer and Convert to Signed Integer Word
|
|
|
7b26da |
+ Format with Saturate */
|
|
|
7b26da |
+ case 456: /* VSX Vector truncate Double-Precision to
|
|
|
7b26da |
+ Integer and Convert to Unsigned Integer
|
|
|
7b26da |
+ Doubleword format with Saturate */
|
|
|
7b26da |
+ case 200: /* VSX Vector truncate Double-Precision to
|
|
|
7b26da |
+ Integer and Convert to Unsigned Integer Word
|
|
|
7b26da |
+ Format with Saturate */
|
|
|
7b26da |
+ case 457: /* VSX Vector Convert Single-Precision to
|
|
|
7b26da |
+ Double-Precision format */
|
|
|
7b26da |
+ case 408: /* VSX Vector truncate Single-Precision to
|
|
|
7b26da |
+ Integer and Convert to Signed Integer
|
|
|
7b26da |
+ Doubleword format with Saturate */
|
|
|
7b26da |
+ case 152: /* VSX Vector truncate Single-Precision to
|
|
|
7b26da |
+ Integer and Convert to Signed Integer Word
|
|
|
7b26da |
+ Format with Saturate */
|
|
|
7b26da |
+ case 392: /* VSX Vector truncate Single-Precision to
|
|
|
7b26da |
+ Integer and Convert to Unsigned Integer
|
|
|
7b26da |
+ Doubleword format with Saturate */
|
|
|
7b26da |
+ case 136: /* VSX Vector truncate Single-Precision to
|
|
|
7b26da |
+ Integer and Convert to Unsigned Integer Word
|
|
|
7b26da |
+ Format with Saturate */
|
|
|
7b26da |
+ case 504: /* VSX Vector Convert and round Signed Integer
|
|
|
7b26da |
+ Doubleword to Double-Precision format */
|
|
|
7b26da |
+ case 440: /* VSX Vector Convert and round Signed Integer
|
|
|
7b26da |
+ Doubleword to Single-Precision format */
|
|
|
7b26da |
+ case 248: /* VSX Vector Convert Signed Integer Word to
|
|
|
7b26da |
+ Double-Precision format */
|
|
|
7b26da |
+ case 184: /* VSX Vector Convert and round Signed Integer
|
|
|
7b26da |
+ Word to Single-Precision format */
|
|
|
7b26da |
+ case 488: /* VSX Vector Convert and round Unsigned
|
|
|
7b26da |
+ Integer Doubleword to Double-Precision format */
|
|
|
7b26da |
+ case 424: /* VSX Vector Convert and round Unsigned
|
|
|
7b26da |
+ Integer Doubleword to Single-Precision format */
|
|
|
7b26da |
+ case 232: /* VSX Vector Convert and round Unsigned
|
|
|
7b26da |
+ Integer Word to Double-Precision format */
|
|
|
7b26da |
+ case 168: /* VSX Vector Convert and round Unsigned
|
|
|
7b26da |
+ Integer Word to Single-Precision format */
|
|
|
7b26da |
+ case 201: /* VSX Vector Round to Double-Precision
|
|
|
7b26da |
+ Integer using round to Nearest Away */
|
|
|
7b26da |
+ case 235: /* VSX Vector Round to Double-Precision
|
|
|
7b26da |
+ Integer Exact using Current rounding mode */
|
|
|
7b26da |
+ case 249: /* VSX Vector Round to Double-Precision
|
|
|
7b26da |
+ Integer using round toward -Infinity */
|
|
|
7b26da |
+ case 233: /* VSX Vector Round to Double-Precision
|
|
|
7b26da |
+ Integer using round toward +Infinity */
|
|
|
7b26da |
+ case 217: /* VSX Vector Round to Double-Precision
|
|
|
7b26da |
+ Integer using round toward Zero */
|
|
|
7b26da |
+ case 218: /* VSX Vector Reciprocal Estimate Double-Precision */
|
|
|
7b26da |
+ case 154: /* VSX Vector Reciprocal Estimate Single-Precision */
|
|
|
7b26da |
+ case 137: /* VSX Vector Round to Single-Precision Integer
|
|
|
7b26da |
+ Using Round to Nearest Away */
|
|
|
7b26da |
+ case 171: /* VSX Vector Round to Single-Precision Integer
|
|
|
7b26da |
+ Exact Using Current rounding mode */
|
|
|
7b26da |
+ case 185: /* VSX Vector Round to Single-Precision Integer
|
|
|
7b26da |
+ Using Round toward -Infinity */
|
|
|
7b26da |
+ case 169: /* VSX Vector Round to Single-Precision Integer
|
|
|
7b26da |
+ Using Round toward +Infinity */
|
|
|
7b26da |
+ case 153: /* VSX Vector Round to Single-Precision Integer
|
|
|
7b26da |
+ Using round toward Zero */
|
|
|
7b26da |
+ case 202: /* VSX Vector Reciprocal Square Root Estimate
|
|
|
7b26da |
+ Double-Precision */
|
|
|
7b26da |
+ case 138: /* VSX Vector Reciprocal Square Root Estimate
|
|
|
7b26da |
+ Single-Precision */
|
|
|
7b26da |
+ case 203: /* VSX Vector Square Root Double-Precision */
|
|
|
7b26da |
+ case 139: /* VSX Vector Square Root Single-Precision */
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
|
|
|
7b26da |
+ case 345: /* VSX Scalar Absolute Value Double-Precision */
|
|
|
7b26da |
+ case 267: /* VSX Scalar Convert Scalar Single-Precision to
|
|
|
7b26da |
+ Vector Single-Precision format Non-signalling */
|
|
|
7b26da |
+ case 331: /* VSX Scalar Convert Single-Precision to
|
|
|
7b26da |
+ Double-Precision format Non-signalling */
|
|
|
7b26da |
+ case 361: /* VSX Scalar Negative Absolute Value Double-Precision */
|
|
|
7b26da |
+ case 377: /* VSX Scalar Negate Double-Precision */
|
|
|
7b26da |
+ case 473: /* VSX Vector Absolute Value Double-Precision */
|
|
|
7b26da |
+ case 409: /* VSX Vector Absolute Value Single-Precision */
|
|
|
7b26da |
+ case 489: /* VSX Vector Negative Absolute Value Double-Precision */
|
|
|
7b26da |
+ case 425: /* VSX Vector Negative Absolute Value Single-Precision */
|
|
|
7b26da |
+ case 505: /* VSX Vector Negate Double-Precision */
|
|
|
7b26da |
+ case 441: /* VSX Vector Negate Single-Precision */
|
|
|
7b26da |
+ case 164: /* VSX Splat Word */
|
|
|
7b26da |
+ ppc_record_vsr (regcache, tdep, PPC_XT (insn));
|
|
|
7b26da |
+ return 0;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ case 106: /* VSX Scalar Test for software Square Root
|
|
|
7b26da |
+ Double-Precision */
|
|
|
7b26da |
+ case 234: /* VSX Vector Test for software Square Root
|
|
|
7b26da |
+ Double-Precision */
|
|
|
7b26da |
+ case 170: /* VSX Vector Test for software Square Root
|
|
|
7b26da |
+ Single-Precision */
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
|
|
|
7b26da |
+ return 0;
|
|
|
7b26da |
+ }
|
|
|
7b26da |
+
|
|
|
7b26da |
+ if (((ext >> 3) & 0x3) == 3) /* VSX Select */
|
|
|
7b26da |
+ {
|
|
|
7b26da |
+ ppc_record_vsr (regcache, tdep, PPC_XT (insn));
|
|
|
7b26da |
+ return 0;
|
|
|
7b26da |
+ }
|
|
|
7b26da |
+
|
|
|
7b26da |
+ fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record "
|
|
|
7b26da |
+ "%08x at %08lx, 60-%d.\n", insn, addr, ext);
|
|
|
7b26da |
+ return -1;
|
|
|
7b26da |
+}
|
|
|
7b26da |
+
|
|
|
7b26da |
+/* Parse instructions of primary opcode-63. */
|
|
|
7b26da |
+
|
|
|
7b26da |
+static int
|
|
|
7b26da |
+ppc_process_record_op63 (struct gdbarch *gdbarch, struct regcache *regcache,
|
|
|
7b26da |
+ CORE_ADDR addr, uint32_t insn)
|
|
|
7b26da |
+{
|
|
|
7b26da |
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
|
|
|
7b26da |
+ int ext = PPC_EXTOP (insn);
|
|
|
7b26da |
+ int tmp;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ switch (ext & 0x1f)
|
|
|
7b26da |
+ {
|
|
|
7b26da |
+ case 18: /* Floating Divide */
|
|
|
7b26da |
+ case 20: /* Floating Subtract */
|
|
|
7b26da |
+ case 21: /* Floating Add */
|
|
|
7b26da |
+ case 22: /* Floating Square Root */
|
|
|
7b26da |
+ case 24: /* Floating Reciprocal Estimate */
|
|
|
7b26da |
+ case 25: /* Floating Multiply */
|
|
|
7b26da |
+ case 26: /* Floating Reciprocal Square Root Estimate */
|
|
|
7b26da |
+ case 28: /* Floating Multiply-Subtract */
|
|
|
7b26da |
+ case 29: /* Floating Multiply-Add */
|
|
|
7b26da |
+ case 30: /* Floating Negative Multiply-Subtract */
|
|
|
7b26da |
+ case 31: /* Floating Negative Multiply-Add */
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache,
|
|
|
7b26da |
+ tdep->ppc_fp0_regnum + PPC_FRT (insn));
|
|
|
7b26da |
+ if (PPC_RC (insn))
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
|
|
|
7b26da |
+ return 0;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ case 23: /* Floating Select */
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache,
|
|
|
7b26da |
+ tdep->ppc_fp0_regnum + PPC_FRT (insn));
|
|
|
7b26da |
+ if (PPC_RC (insn))
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
|
|
|
7b26da |
+ }
|
|
|
7b26da |
+
|
|
|
7b26da |
+ switch (ext)
|
|
|
7b26da |
+ {
|
|
|
7b26da |
+ case 2: /* DFP Add Quad */
|
|
|
7b26da |
+ case 3: /* DFP Quantize Quad */
|
|
|
7b26da |
+ case 34: /* DFP Multiply Quad */
|
|
|
7b26da |
+ case 35: /* DFP Reround Quad */
|
|
|
7b26da |
+ case 67: /* DFP Quantize Immediate Quad */
|
|
|
7b26da |
+ case 99: /* DFP Round To FP Integer With Inexact Quad */
|
|
|
7b26da |
+ case 227: /* DFP Round To FP Integer Without Inexact Quad */
|
|
|
7b26da |
+ case 258: /* DFP Convert To DFP Extended Quad */
|
|
|
7b26da |
+ case 514: /* DFP Subtract Quad */
|
|
|
7b26da |
+ case 546: /* DFP Divide Quad */
|
|
|
7b26da |
+ case 770: /* DFP Round To DFP Long Quad */
|
|
|
7b26da |
+ case 802: /* DFP Convert From Fixed Quad */
|
|
|
7b26da |
+ case 834: /* DFP Encode BCD To DPD Quad */
|
|
|
7b26da |
+ if (PPC_RC (insn))
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
|
|
|
7b26da |
+ tmp = tdep->ppc_fp0_regnum + (PPC_FRT (insn) & ~1);
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tmp);
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tmp + 1);
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
|
|
|
7b26da |
+ return 0;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ case 130: /* DFP Compare Ordered Quad */
|
|
|
7b26da |
+ case 162: /* DFP Test Exponent Quad */
|
|
|
7b26da |
+ case 194: /* DFP Test Data Class Quad */
|
|
|
7b26da |
+ case 226: /* DFP Test Data Group Quad */
|
|
|
7b26da |
+ case 642: /* DFP Compare Unordered Quad */
|
|
|
7b26da |
+ case 674: /* DFP Test Significance Quad */
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
|
|
|
7b26da |
+ return 0;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ case 66: /* DFP Shift Significand Left Immediate Quad */
|
|
|
7b26da |
+ case 98: /* DFP Shift Significand Right Immediate Quad */
|
|
|
7b26da |
+ case 322: /* DFP Decode DPD To BCD Quad */
|
|
|
7b26da |
+ case 866: /* DFP Insert Biased Exponent Quad */
|
|
|
7b26da |
+ tmp = tdep->ppc_fp0_regnum + (PPC_FRT (insn) & ~1);
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tmp);
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tmp + 1);
|
|
|
7b26da |
+ if (PPC_RC (insn))
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
|
|
|
7b26da |
+ return 0;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ case 290: /* DFP Convert To Fixed Quad */
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache,
|
|
|
7b26da |
+ tdep->ppc_fp0_regnum + PPC_FRT (insn));
|
|
|
7b26da |
+ if (PPC_RC (insn))
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
|
|
|
7b26da |
+ break;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ case 354: /* DFP Extract Biased Exponent Quad */
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache,
|
|
|
7b26da |
+ tdep->ppc_fp0_regnum + PPC_FRT (insn));
|
|
|
7b26da |
+ if (PPC_RC (insn))
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
|
|
|
7b26da |
+ return 0;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ case 12: /* Floating Round to Single-Precision */
|
|
|
7b26da |
+ case 14: /* Floating Convert To Integer Word */
|
|
|
7b26da |
+ case 15: /* Floating Convert To Integer Word
|
|
|
7b26da |
+ with round toward Zero */
|
|
|
7b26da |
+ case 142: /* Floating Convert To Integer Word Unsigned */
|
|
|
7b26da |
+ case 143: /* Floating Convert To Integer Word Unsigned
|
|
|
7b26da |
+ with round toward Zero */
|
|
|
7b26da |
+ case 392: /* Floating Round to Integer Nearest */
|
|
|
7b26da |
+ case 424: /* Floating Round to Integer Toward Zero */
|
|
|
7b26da |
+ case 456: /* Floating Round to Integer Plus */
|
|
|
7b26da |
+ case 488: /* Floating Round to Integer Minus */
|
|
|
7b26da |
+ case 814: /* Floating Convert To Integer Doubleword */
|
|
|
7b26da |
+ case 815: /* Floating Convert To Integer Doubleword
|
|
|
7b26da |
+ with round toward Zero */
|
|
|
7b26da |
+ case 846: /* Floating Convert From Integer Doubleword */
|
|
|
7b26da |
+ case 942: /* Floating Convert To Integer Doubleword Unsigned */
|
|
|
7b26da |
+ case 943: /* Floating Convert To Integer Doubleword Unsigned
|
|
|
7b26da |
+ with round toward Zero */
|
|
|
7b26da |
+ case 974: /* Floating Convert From Integer Doubleword Unsigned */
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache,
|
|
|
7b26da |
+ tdep->ppc_fp0_regnum + PPC_FRT (insn));
|
|
|
7b26da |
+ if (PPC_RC (insn))
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
|
|
|
7b26da |
+ return 0;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ case 583: /* Move From FPSCR */
|
|
|
7b26da |
+ case 8: /* Floating Copy Sign */
|
|
|
7b26da |
+ case 40: /* Floating Negate */
|
|
|
7b26da |
+ case 72: /* Floating Move Register */
|
|
|
7b26da |
+ case 136: /* Floating Negative Absolute Value */
|
|
|
7b26da |
+ case 264: /* Floating Absolute Value */
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache,
|
|
|
7b26da |
+ tdep->ppc_fp0_regnum + PPC_FRT (insn));
|
|
|
7b26da |
+ if (PPC_RC (insn))
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
|
|
|
7b26da |
+ return 0;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ case 838: /* Floating Merge Odd Word */
|
|
|
7b26da |
+ case 966: /* Floating Merge Even Word */
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache,
|
|
|
7b26da |
+ tdep->ppc_fp0_regnum + PPC_FRT (insn));
|
|
|
7b26da |
+ return 0;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ case 38: /* Move To FPSCR Bit 1 */
|
|
|
7b26da |
+ case 70: /* Move To FPSCR Bit 0 */
|
|
|
7b26da |
+ case 134: /* Move To FPSCR Field Immediate */
|
|
|
7b26da |
+ case 711: /* Move To FPSCR Fields */
|
|
|
7b26da |
+ if (PPC_RC (insn))
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
|
|
|
7b26da |
+ break;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ case 0: /* Floating Compare Unordered */
|
|
|
7b26da |
+ case 32: /* Floating Compare Ordered */
|
|
|
7b26da |
+ case 64: /* Move to Condition Register from FPSCR */
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
|
|
|
7b26da |
+ /* FALL-THROUGH */
|
|
|
7b26da |
+ case 128: /* Floating Test for software Divide */
|
|
|
7b26da |
+ case 160: /* Floating Test for software Square Root */
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
|
|
|
7b26da |
+ return 0;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ }
|
|
|
7b26da |
+
|
|
|
7b26da |
+ fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record "
|
|
|
7b26da |
+ "%08x at %08lx, 59-%d.\n", insn, addr, ext);
|
|
|
7b26da |
+ return -1;
|
|
|
7b26da |
+}
|
|
|
7b26da |
+
|
|
|
7b26da |
+/* Parse the current instruction and record the values of the registers and
|
|
|
7b26da |
+ memory that will be changed in current instruction to "record_arch_list".
|
|
|
7b26da |
+ Return -1 if something wrong. */
|
|
|
7b26da |
+
|
|
|
7b26da |
+int
|
|
|
7b26da |
+ppc_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
|
|
|
7b26da |
+ CORE_ADDR addr)
|
|
|
7b26da |
+{
|
|
|
7b26da |
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
|
|
|
7b26da |
+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
|
|
|
7b26da |
+ uint32_t insn;
|
|
|
7b26da |
+ int op6, tmp, i;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ insn = read_memory_unsigned_integer (addr, 4, byte_order);
|
|
|
7b26da |
+ op6 = PPC_OP6 (insn);
|
|
|
7b26da |
+
|
|
|
7b26da |
+ switch (op6)
|
|
|
7b26da |
+ {
|
|
|
7b26da |
+ case 2: /* Trap Doubleword Immediate */
|
|
|
7b26da |
+ case 3: /* Trap Word Immediate */
|
|
|
7b26da |
+ /* Do nothing. */
|
|
|
7b26da |
+ break;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ case 4:
|
|
|
7b26da |
+ if (ppc_process_record_op4 (gdbarch, regcache, addr, insn) != 0)
|
|
|
7b26da |
+ return -1;
|
|
|
7b26da |
+ break;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ case 17: /* System call */
|
|
|
7b26da |
+ if (PPC_LEV (insn) != 0)
|
|
|
7b26da |
+ goto UNKNOWN_OP;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ if (tdep->ppc_syscall_record != NULL)
|
|
|
7b26da |
+ {
|
|
|
7b26da |
+ if (tdep->ppc_syscall_record (regcache) != 0)
|
|
|
7b26da |
+ return -1;
|
|
|
7b26da |
+ }
|
|
|
7b26da |
+ else
|
|
|
7b26da |
+ {
|
|
|
7b26da |
+ printf_unfiltered (_("no syscall record support\n"));
|
|
|
7b26da |
+ return -1;
|
|
|
7b26da |
+ }
|
|
|
7b26da |
+ break;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ case 7: /* Multiply Low Immediate */
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache,
|
|
|
7b26da |
+ tdep->ppc_gp0_regnum + PPC_RT (insn));
|
|
|
7b26da |
+ break;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ case 8: /* Subtract From Immediate Carrying */
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum);
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache,
|
|
|
7b26da |
+ tdep->ppc_gp0_regnum + PPC_RT (insn));
|
|
|
7b26da |
+ break;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ case 10: /* Compare Logical Immediate */
|
|
|
7b26da |
+ case 11: /* Compare Immediate */
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
|
|
|
7b26da |
+ break;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ case 13: /* Add Immediate Carrying and Record */
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
|
|
|
7b26da |
+ /* FALL-THROUGH */
|
|
|
7b26da |
+ case 12: /* Add Immediate Carrying */
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum);
|
|
|
7b26da |
+ /* FALL-THROUGH */
|
|
|
7b26da |
+ case 14: /* Add Immediate */
|
|
|
7b26da |
+ case 15: /* Add Immediate Shifted */
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache,
|
|
|
7b26da |
+ tdep->ppc_gp0_regnum + PPC_RT (insn));
|
|
|
7b26da |
+ break;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ case 16: /* Branch Conditional */
|
|
|
7b26da |
+ if ((PPC_BO (insn) & 0x4) == 0)
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_ctr_regnum);
|
|
|
7b26da |
+ /* FALL-THROUGH */
|
|
|
7b26da |
+ case 18: /* Branch */
|
|
|
7b26da |
+ if (PPC_LK (insn))
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_lr_regnum);
|
|
|
7b26da |
+ break;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ case 19:
|
|
|
7b26da |
+ if (ppc_process_record_op19 (gdbarch, regcache, addr, insn) != 0)
|
|
|
7b26da |
+ return -1;
|
|
|
7b26da |
+ break;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ case 20: /* Rotate Left Word Immediate then Mask Insert */
|
|
|
7b26da |
+ case 21: /* Rotate Left Word Immediate then AND with Mask */
|
|
|
7b26da |
+ case 23: /* Rotate Left Word then AND with Mask */
|
|
|
7b26da |
+ case 30: /* Rotate Left Doubleword Immediate then Clear Left */
|
|
|
7b26da |
+ /* Rotate Left Doubleword Immediate then Clear Right */
|
|
|
7b26da |
+ /* Rotate Left Doubleword Immediate then Clear */
|
|
|
7b26da |
+ /* Rotate Left Doubleword then Clear Left */
|
|
|
7b26da |
+ /* Rotate Left Doubleword then Clear Right */
|
|
|
7b26da |
+ /* Rotate Left Doubleword Immediate then Mask Insert */
|
|
|
7b26da |
+ if (PPC_RC (insn))
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache,
|
|
|
7b26da |
+ tdep->ppc_gp0_regnum + PPC_RA (insn));
|
|
|
7b26da |
+ break;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ case 28: /* AND Immediate */
|
|
|
7b26da |
+ case 29: /* AND Immediate Shifted */
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
|
|
|
7b26da |
+ /* FALL-THROUGH */
|
|
|
7b26da |
+ case 24: /* OR Immediate */
|
|
|
7b26da |
+ case 25: /* OR Immediate Shifted */
|
|
|
7b26da |
+ case 26: /* XOR Immediate */
|
|
|
7b26da |
+ case 27: /* XOR Immediate Shifted */
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache,
|
|
|
7b26da |
+ tdep->ppc_gp0_regnum + PPC_RA (insn));
|
|
|
7b26da |
+ break;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ case 31:
|
|
|
7b26da |
+ if (ppc_process_record_op31 (gdbarch, regcache, addr, insn) != 0)
|
|
|
7b26da |
+ return -1;
|
|
|
7b26da |
+ break;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ case 33: /* Load Word and Zero with Update */
|
|
|
7b26da |
+ case 35: /* Load Byte and Zero with Update */
|
|
|
7b26da |
+ case 41: /* Load Halfword and Zero with Update */
|
|
|
7b26da |
+ case 43: /* Load Halfword Algebraic with Update */
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache,
|
|
|
7b26da |
+ tdep->ppc_gp0_regnum + PPC_RA (insn));
|
|
|
7b26da |
+ /* FALL-THROUGH */
|
|
|
7b26da |
+ case 32: /* Load Word and Zero */
|
|
|
7b26da |
+ case 34: /* Load Byte and Zero */
|
|
|
7b26da |
+ case 40: /* Load Halfword and Zero */
|
|
|
7b26da |
+ case 42: /* Load Halfword Algebraic */
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache,
|
|
|
7b26da |
+ tdep->ppc_gp0_regnum + PPC_RT (insn));
|
|
|
7b26da |
+ break;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ case 46: /* Load Multiple Word */
|
|
|
7b26da |
+ for (i = PPC_RT (insn); i < 32; i++)
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_gp0_regnum + i);
|
|
|
7b26da |
+ break;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ case 56: /* Load Quadword */
|
|
|
7b26da |
+ tmp = tdep->ppc_gp0_regnum + (PPC_RT (insn) & ~1);
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tmp);
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tmp + 1);
|
|
|
7b26da |
+ break;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ case 49: /* Load Floating-Point Single with Update */
|
|
|
7b26da |
+ case 51: /* Load Floating-Point Double with Update */
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache,
|
|
|
7b26da |
+ tdep->ppc_gp0_regnum + PPC_RA (insn));
|
|
|
7b26da |
+ /* FALL-THROUGH */
|
|
|
7b26da |
+ case 48: /* Load Floating-Point Single */
|
|
|
7b26da |
+ case 50: /* Load Floating-Point Double */
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache,
|
|
|
7b26da |
+ tdep->ppc_fp0_regnum + PPC_FRT (insn));
|
|
|
7b26da |
+ break;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ case 47: /* Store Multiple Word */
|
|
|
7b26da |
+ {
|
|
|
7b26da |
+ ULONGEST addr = 0;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ if (PPC_RA (insn) != 0)
|
|
|
7b26da |
+ regcache_raw_read_unsigned (regcache,
|
|
|
7b26da |
+ tdep->ppc_gp0_regnum + PPC_RA (insn),
|
|
|
7b26da |
+ &addr);
|
|
|
7b26da |
+
|
|
|
7b26da |
+ addr += PPC_D (insn);
|
|
|
7b26da |
+ if (record_full_arch_list_add_mem (addr, 4 * (32 - PPC_RS (insn))) != 0)
|
|
|
7b26da |
+ return -1;
|
|
|
7b26da |
+ }
|
|
|
7b26da |
+ break;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ case 37: /* Store Word with Update */
|
|
|
7b26da |
+ case 39: /* Store Byte with Update */
|
|
|
7b26da |
+ case 45: /* Store Halfword with Update */
|
|
|
7b26da |
+ case 53: /* Store Floating-Point Single with Update */
|
|
|
7b26da |
+ case 55: /* Store Floating-Point Double with Update */
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache,
|
|
|
7b26da |
+ tdep->ppc_gp0_regnum + PPC_RA (insn));
|
|
|
7b26da |
+ /* FALL-THROUGH */
|
|
|
7b26da |
+ case 36: /* Store Word */
|
|
|
7b26da |
+ case 38: /* Store Byte */
|
|
|
7b26da |
+ case 44: /* Store Halfword */
|
|
|
7b26da |
+ case 52: /* Store Floating-Point Single */
|
|
|
7b26da |
+ case 54: /* Store Floating-Point Double */
|
|
|
7b26da |
+ {
|
|
|
7b26da |
+ ULONGEST addr = 0;
|
|
|
7b26da |
+ int size = -1;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ if (PPC_RA (insn) != 0)
|
|
|
7b26da |
+ regcache_raw_read_unsigned (regcache,
|
|
|
7b26da |
+ tdep->ppc_gp0_regnum + PPC_RA (insn),
|
|
|
7b26da |
+ &addr);
|
|
|
7b26da |
+ addr += PPC_D (insn);
|
|
|
7b26da |
+
|
|
|
7b26da |
+ if (op6 == 36 || op6 == 37 || op6 == 52 || op6 == 53)
|
|
|
7b26da |
+ size = 4;
|
|
|
7b26da |
+ else if (op6 == 54 || op6 == 55)
|
|
|
7b26da |
+ size = 8;
|
|
|
7b26da |
+ else if (op6 == 44 || op6 == 45)
|
|
|
7b26da |
+ size = 2;
|
|
|
7b26da |
+ else if (op6 == 38 || op6 == 39)
|
|
|
7b26da |
+ size = 1;
|
|
|
7b26da |
+ else
|
|
|
7b26da |
+ gdb_assert (0);
|
|
|
7b26da |
+
|
|
|
7b26da |
+ if (record_full_arch_list_add_mem (addr, size) != 0)
|
|
|
7b26da |
+ return -1;
|
|
|
7b26da |
+ }
|
|
|
7b26da |
+ break;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ case 57: /* Load Floating-Point Double Pair */
|
|
|
7b26da |
+ if (PPC_FIELD (insn, 30, 2) != 0)
|
|
|
7b26da |
+ goto UNKNOWN_OP;
|
|
|
7b26da |
+ tmp = tdep->ppc_fp0_regnum + (PPC_RT (insn) & ~1);
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tmp);
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache, tmp + 1);
|
|
|
7b26da |
+ break;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ case 58: /* Load Doubleword */
|
|
|
7b26da |
+ /* Load Doubleword with Update */
|
|
|
7b26da |
+ /* Load Word Algebraic */
|
|
|
7b26da |
+ if (PPC_FIELD (insn, 30, 2) > 2)
|
|
|
7b26da |
+ goto UNKNOWN_OP;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache,
|
|
|
7b26da |
+ tdep->ppc_gp0_regnum + PPC_RT (insn));
|
|
|
7b26da |
+ if (PPC_BIT (insn, 31))
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache,
|
|
|
7b26da |
+ tdep->ppc_gp0_regnum + PPC_RA (insn));
|
|
|
7b26da |
+ break;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ case 59:
|
|
|
7b26da |
+ if (ppc_process_record_op59 (gdbarch, regcache, addr, insn) != 0)
|
|
|
7b26da |
+ return -1;
|
|
|
7b26da |
+ break;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ case 60:
|
|
|
7b26da |
+ if (ppc_process_record_op60 (gdbarch, regcache, addr, insn) != 0)
|
|
|
7b26da |
+ return -1;
|
|
|
7b26da |
+ break;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ case 61: /* Store Floating-Point Double Pair */
|
|
|
7b26da |
+ case 62: /* Store Doubleword */
|
|
|
7b26da |
+ /* Store Doubleword with Update */
|
|
|
7b26da |
+ /* Store Quadword with Update */
|
|
|
7b26da |
+ {
|
|
|
7b26da |
+ ULONGEST addr = 0;
|
|
|
7b26da |
+ int size;
|
|
|
7b26da |
+ int sub2 = PPC_FIELD (insn, 30, 2);
|
|
|
7b26da |
+
|
|
|
7b26da |
+ if ((op6 == 61 && sub2 != 0) || (op6 == 62 && sub2 > 2))
|
|
|
7b26da |
+ goto UNKNOWN_OP;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ if (PPC_RA (insn) != 0)
|
|
|
7b26da |
+ regcache_raw_read_unsigned (regcache,
|
|
|
7b26da |
+ tdep->ppc_gp0_regnum + PPC_RA (insn),
|
|
|
7b26da |
+ &addr);
|
|
|
7b26da |
+
|
|
|
7b26da |
+ size = ((op6 == 61) || sub2 == 2) ? 16 : 8;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ addr += PPC_DS (insn) << 2;
|
|
|
7b26da |
+ if (record_full_arch_list_add_mem (addr, size) != 0)
|
|
|
7b26da |
+ return -1;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ if (op6 == 62 && sub2 == 1)
|
|
|
7b26da |
+ record_full_arch_list_add_reg (regcache,
|
|
|
7b26da |
+ tdep->ppc_gp0_regnum +
|
|
|
7b26da |
+ PPC_RA (insn));
|
|
|
7b26da |
+
|
|
|
7b26da |
+ break;
|
|
|
7b26da |
+ }
|
|
|
7b26da |
+
|
|
|
7b26da |
+ case 63:
|
|
|
7b26da |
+ if (ppc_process_record_op63 (gdbarch, regcache, addr, insn) != 0)
|
|
|
7b26da |
+ return -1;
|
|
|
7b26da |
+ break;
|
|
|
7b26da |
+
|
|
|
7b26da |
+ default:
|
|
|
7b26da |
+UNKNOWN_OP:
|
|
|
7b26da |
+ fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record "
|
|
|
7b26da |
+ "%08x at %08lx, %d.\n", insn, addr, op6);
|
|
|
7b26da |
+ return -1;
|
|
|
7b26da |
+ }
|
|
|
7b26da |
+
|
|
|
7b26da |
+ if (record_full_arch_list_add_reg (regcache, PPC_PC_REGNUM))
|
|
|
7b26da |
+ return -1;
|
|
|
7b26da |
+ if (record_full_arch_list_add_end ())
|
|
|
7b26da |
+ return -1;
|
|
|
7b26da |
+ return 0;
|
|
|
7b26da |
+}
|
|
|
7b26da |
+
|
|
|
7b26da |
/* Initialize the current architecture based on INFO. If possible, re-use an
|
|
|
7b26da |
architecture from ARCHES, which is a list of architectures already created
|
|
|
7b26da |
during this debugging session.
|
|
|
7b26da |
Index: gdb-7.6.1/gdb/testsuite/lib/gdb.exp
|
|
|
7b26da |
===================================================================
|
|
|
7b26da |
--- gdb-7.6.1.orig/gdb/testsuite/lib/gdb.exp
|
|
|
7b26da |
+++ gdb-7.6.1/gdb/testsuite/lib/gdb.exp
|
|
|
7b26da |
@@ -1784,7 +1784,8 @@ proc supports_process_record {} {
|
|
|
7b26da |
return [target_info gdb,use_precord]
|
|
|
7b26da |
}
|
|
|
7b26da |
|
|
|
7b26da |
- if { [istarget "x86_64-*-linux*"] || [istarget "i\[34567\]86-*-linux*"] } {
|
|
|
7b26da |
+ if { [istarget "x86_64-*-linux*"] || [istarget "i\[34567\]86-*-linux*"]
|
|
|
7b26da |
+ || [istarget "powerpc*-*-linux*"] } {
|
|
|
7b26da |
return 1
|
|
|
7b26da |
}
|
|
|
7b26da |
|
|
|
7b26da |
@@ -1799,7 +1800,8 @@ proc supports_reverse {} {
|
|
|
7b26da |
return [target_info gdb,can_reverse]
|
|
|
7b26da |
}
|
|
|
7b26da |
|
|
|
7b26da |
- if { [istarget "x86_64-*-linux*"] || [istarget "i\[34567\]86-*-linux*"] } {
|
|
|
7b26da |
+ if { [istarget "x86_64-*-linux*"] || [istarget "i\[34567\]86-*-linux*"]
|
|
|
7b26da |
+ || [istarget "powerpc*-*-linux*"] } {
|
|
|
7b26da |
return 1
|
|
|
7b26da |
}
|
|
|
7b26da |
|