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From FEDORA_PATCHES Mon Sep 17 00:00:00 2001
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From: Keith Seitz <keiths@redhat.com>
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Date: Fri, 11 Jan 2019 17:02:17 -0500
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Subject: gdb-rhbz1187581-power8-regs-not-in-8.2-11of15.patch
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;; [PowerPC] Add support for TAR
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;; Edjunior Barbosa Machado and Pedro Franco de Carvalho, RH BZ 1187581
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[PowerPC] Add support for TAR
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This patch adds support for the Target Address Register for powerpc
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linux native and core file targets, and in the powerpc linux server
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stub.
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gdb/ChangeLog:
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2018-10-26 Edjunior Barbosa Machado <emachado@linux.vnet.ibm.com>
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Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
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* arch/ppc-linux-tdesc.h (tdesc_powerpc_isa207_vsx32l)
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(tdesc_powerpc_isa207_vsx64l): Declare.
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* arch/ppc-linux-common.h (PPC_LINUX_SIZEOF_TARREGSET): Define.
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(struct ppc_linux_features) <isa207>: New field.
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(ppc_linux_no_features): Add initializer for isa207 field.
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* arch/ppc-linux-common.c (ppc_linux_match_description): Return
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new tdescs.
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* nat/ppc-linux.h (PPC_FEATURE2_ARCH_2_07, PPC_FEATURE2_TAR)
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(NT_PPC_TAR): Define if not already defined.
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* features/Makefile (WHICH): Add rs6000/powerpc-isa207-vsx32l and
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rs6000/powerpc-isa207-vsx64l.
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(XMLTOC): Add rs6000/powerpc-isa207-vsx32l.xml and
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rs6000/powerpc-isa207-vsx64l.xml.
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* features/rs6000/power-tar.xml: New file.
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* features/rs6000/powerpc-isa207-vsx32l.xml: New file.
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* features/rs6000/powerpc-isa207-vsx64l.xml: New file.
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* features/rs6000/powerpc-isa207-vsx32l.c: Generate.
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* features/rs6000/powerpc-isa207-vsx64l.c: Generate.
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* regformats/rs6000/powerpc-isa207-vsx32l.dat: Generate.
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* regformats/rs6000/powerpc-isa207-vsx64l.dat: Generate.
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* ppc-linux-nat.c (fetch_register, fetch_ppc_registers): Call
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fetch_regset with the TAR regset.
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(store_register, store_ppc_registers): Call store_regset with the
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TAR regset.
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(ppc_linux_nat_target::read_description): Set isa207 field in the
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features struct if needed.
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* ppc-linux-tdep.c: Include
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features/rs6000/powerpc-isa207-vsx32l.c and
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features/rs6000/powerpc-isa207-vsx64l.c.
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(ppc32_regmap_tar, ppc32_linux_tarregset): New globals.
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(ppc_linux_iterate_over_regset_sections): Call back with the tar
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regset.
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(ppc_linux_core_read_description): Check if the tar section is
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present and set isa207 in the features struct.
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(_initialize_ppc_linux_tdep): Call
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initialize_tdesc_powerpc_isa207_vsx32l and
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initialize_tdesc_powerpc_isa207_vsx64l.
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* ppc-linux-tdep.h (ppc32_linux_tarregset): Declare.
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* ppc-tdep.h (gdbarch_tdep) <ppc_tar_regnum>: New field.
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(enum) <PPC_TAR_REGNUM>: New enum value.
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* rs6000-tdep.c (rs6000_gdbarch_init): Look for and validate tar
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feature.
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(ppc_process_record_op31): Record changes to TAR.
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gdb/gdbserver/ChangeLog:
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2018-10-26 Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
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* configure.srv (ipa_ppc_linux_regobj): Add
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powerpc-isa207-vsx64l-ipa.o and powerpc-isa207-vsx32l-ipa.o.
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(powerpc*-*-linux*): Add powerpc-isa207-vsx32l.o and
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powerpc-isa207-vsx64l.o to srv_regobj, add rs6000/power-tar.xml,
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rs6000/powerpc-isa207-vsx32l.xml, and
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rs6000/powerpc-isa207-vsx64l.xml to srv_xmlfiles.
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* linux-ppc-tdesc-init.h (enum ppc_linux_tdesc)
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<PPC_TDESC_ISA207_VSX>: New enum value.
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(init_registers_powerpc_isa207_vsx32l): Declare.
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(init_registers_powerpc_isa207_vsx64l): Declare.
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* linux-ppc-low.c (ppc_fill_tarregset): New function.
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(ppc_store_tarregset): New function.
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(ppc_regsets): Add entry for the TAR regset.
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(ppc_arch_setup): Set isa207 in features struct when needed. Set
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size for the TAR regsets.
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(ppc_get_ipa_tdesc_idx): Return PPC_TDESC_ISA207_VSX.
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(initialize_low_arch): Call init_registers_powerpc_isa207_vsx32l
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and init_registers_powerpc_isa207_vsx64l.
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* linux-ppc-ipa.c (get_ipa_tdesc): Handle PPC_TDESC_ISA207_VSX.
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(initialize_low_tracepoint): Call
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init_registers_powerpc_isa207_vsx32l and
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init_registers_powerpc_isa207_vsx64l.
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gdb/testsuite/ChangeLog:
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2018-10-26 Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
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* gdb.arch/powerpc-tar.c: New file.
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* gdb.arch/powerpc-tar.exp: New file.
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gdb/doc/ChangeLog:
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2018-10-26 Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
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* gdb.texinfo (PowerPC Features): Describe new feature
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"org.gnu.gdb.power.tar".
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diff --git a/gdb/arch/ppc-linux-common.c b/gdb/arch/ppc-linux-common.c
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--- a/gdb/arch/ppc-linux-common.c
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+++ b/gdb/arch/ppc-linux-common.c
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@@ -53,7 +53,8 @@ ppc_linux_match_description (struct ppc_linux_features features)
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if (features.cell)
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tdesc = tdesc_powerpc_cell64l;
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else if (features.vsx)
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- tdesc = (features.ppr_dscr? tdesc_powerpc_isa205_ppr_dscr_vsx64l
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+ tdesc = (features.isa207? tdesc_powerpc_isa207_vsx64l
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+ : features.ppr_dscr? tdesc_powerpc_isa205_ppr_dscr_vsx64l
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: features.isa205? tdesc_powerpc_isa205_vsx64l
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: tdesc_powerpc_vsx64l);
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else if (features.altivec)
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@@ -70,7 +71,8 @@ ppc_linux_match_description (struct ppc_linux_features features)
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if (features.cell)
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tdesc = tdesc_powerpc_cell32l;
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else if (features.vsx)
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- tdesc = (features.ppr_dscr? tdesc_powerpc_isa205_ppr_dscr_vsx32l
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+ tdesc = (features.isa207? tdesc_powerpc_isa207_vsx32l
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+ : features.ppr_dscr? tdesc_powerpc_isa205_ppr_dscr_vsx32l
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: features.isa205? tdesc_powerpc_isa205_vsx32l
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: tdesc_powerpc_vsx32l);
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else if (features.altivec)
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diff --git a/gdb/arch/ppc-linux-common.h b/gdb/arch/ppc-linux-common.h
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--- a/gdb/arch/ppc-linux-common.h
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+++ b/gdb/arch/ppc-linux-common.h
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@@ -32,6 +32,7 @@ struct target_desc;
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#define PPC_LINUX_SIZEOF_VSXREGSET 256
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#define PPC_LINUX_SIZEOF_PPRREGSET 8
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#define PPC_LINUX_SIZEOF_DSCRREGSET 8
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+#define PPC_LINUX_SIZEOF_TARREGSET 8
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/* Check if the hwcap auxv entry indicates that isa205 is supported. */
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bool ppc_linux_has_isa205 (CORE_ADDR hwcap);
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@@ -44,6 +45,7 @@ struct ppc_linux_features
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bool vsx;
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bool isa205;
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bool ppr_dscr;
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+ bool isa207;
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bool cell;
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};
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@@ -55,6 +57,7 @@ const struct ppc_linux_features ppc_linux_no_features = {
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false,
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false,
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false,
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+ false,
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};
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/* Return a target description that matches FEATURES. */
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diff --git a/gdb/arch/ppc-linux-tdesc.h b/gdb/arch/ppc-linux-tdesc.h
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--- a/gdb/arch/ppc-linux-tdesc.h
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+++ b/gdb/arch/ppc-linux-tdesc.h
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@@ -30,6 +30,7 @@ extern struct target_desc *tdesc_powerpc_isa205_32l;
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extern struct target_desc *tdesc_powerpc_isa205_altivec32l;
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extern struct target_desc *tdesc_powerpc_isa205_vsx32l;
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extern struct target_desc *tdesc_powerpc_isa205_ppr_dscr_vsx32l;
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+extern struct target_desc *tdesc_powerpc_isa207_vsx32l;
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extern struct target_desc *tdesc_powerpc_e500l;
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extern struct target_desc *tdesc_powerpc_64l;
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@@ -40,5 +41,6 @@ extern struct target_desc *tdesc_powerpc_isa205_64l;
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extern struct target_desc *tdesc_powerpc_isa205_altivec64l;
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extern struct target_desc *tdesc_powerpc_isa205_vsx64l;
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extern struct target_desc *tdesc_powerpc_isa205_ppr_dscr_vsx64l;
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+extern struct target_desc *tdesc_powerpc_isa207_vsx64l;
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#endif /* ARCH_PPC_LINUX_TDESC_H */
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diff --git a/gdb/doc/gdb.texinfo b/gdb/doc/gdb.texinfo
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--- a/gdb/doc/gdb.texinfo
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+++ b/gdb/doc/gdb.texinfo
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@@ -42561,6 +42561,9 @@ contain the 64-bit register @samp{ppr}.
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The @samp{org.gnu.gdb.power.dscr} feature is optional. It should
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contain the 64-bit register @samp{dscr}.
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+The @samp{org.gnu.gdb.power.tar} feature is optional. It should
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+contain the 64-bit register @samp{tar}.
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+
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@node S/390 and System z Features
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@subsection S/390 and System z Features
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@cindex target descriptions, S/390 features
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diff --git a/gdb/features/Makefile b/gdb/features/Makefile
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--- a/gdb/features/Makefile
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+++ b/gdb/features/Makefile
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@@ -75,6 +75,7 @@ WHICH = aarch64 \
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rs6000/powerpc-isa205-vsx32l rs6000/powerpc-isa205-vsx64l \
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rs6000/powerpc-isa205-ppr-dscr-vsx32l \
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rs6000/powerpc-isa205-ppr-dscr-vsx64l \
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+ rs6000/powerpc-isa207-vsx32l rs6000/powerpc-isa207-vsx64l \
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s390-linux32 s390-linux64 s390x-linux64 \
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s390-linux32v1 s390-linux64v1 s390x-linux64v1 \
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s390-linux32v2 s390-linux64v2 s390x-linux64v2 \
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@@ -171,6 +172,8 @@ XMLTOC = \
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rs6000/powerpc-isa205-vsx64l.xml \
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rs6000/powerpc-isa205-ppr-dscr-vsx32l.xml \
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rs6000/powerpc-isa205-ppr-dscr-vsx64l.xml \
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+ rs6000/powerpc-isa207-vsx32l.xml \
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+ rs6000/powerpc-isa207-vsx64l.xml \
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rs6000/powerpc-vsx32.xml \
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rs6000/powerpc-vsx32l.xml \
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rs6000/powerpc-vsx64.xml \
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diff --git a/gdb/features/rs6000/power-tar.xml b/gdb/features/rs6000/power-tar.xml
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new file mode 100644
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--- /dev/null
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+++ b/gdb/features/rs6000/power-tar.xml
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@@ -0,0 +1,12 @@
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+
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+
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+
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+ Copying and distribution of this file, with or without modification,
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+ are permitted in any medium without royalty provided the copyright
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+ notice and this notice are preserved. -->
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+
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+
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+
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+<feature name="org.gnu.gdb.power.tar">
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+ <reg name="tar" bitsize="64" type="uint64"/>
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+</feature>
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diff --git a/gdb/features/rs6000/powerpc-isa207-vsx32l.c b/gdb/features/rs6000/powerpc-isa207-vsx32l.c
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new file mode 100644
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--- /dev/null
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+++ b/gdb/features/rs6000/powerpc-isa207-vsx32l.c
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@@ -0,0 +1,203 @@
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+/* THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi:set ro:
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+ Original: powerpc-isa207-vsx32l.xml */
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+
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+#include "defs.h"
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+#include "osabi.h"
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+#include "target-descriptions.h"
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+
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+struct target_desc *tdesc_powerpc_isa207_vsx32l;
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+static void
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+initialize_tdesc_powerpc_isa207_vsx32l (void)
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+{
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+ struct target_desc *result = allocate_target_description ();
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+ set_tdesc_architecture (result, bfd_scan_arch ("powerpc:common"));
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+
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+ struct tdesc_feature *feature;
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+
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+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.core");
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+ tdesc_create_reg (feature, "r0", 0, 1, NULL, 32, "uint32");
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+ tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "uint32");
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+ tdesc_create_reg (feature, "r2", 2, 1, NULL, 32, "uint32");
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+ tdesc_create_reg (feature, "r3", 3, 1, NULL, 32, "uint32");
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+ tdesc_create_reg (feature, "r4", 4, 1, NULL, 32, "uint32");
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+ tdesc_create_reg (feature, "r5", 5, 1, NULL, 32, "uint32");
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+ tdesc_create_reg (feature, "r6", 6, 1, NULL, 32, "uint32");
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|
|
7cb06c |
+ tdesc_create_reg (feature, "r7", 7, 1, NULL, 32, "uint32");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "r8", 8, 1, NULL, 32, "uint32");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "r9", 9, 1, NULL, 32, "uint32");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "r10", 10, 1, NULL, 32, "uint32");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "r11", 11, 1, NULL, 32, "uint32");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "r12", 12, 1, NULL, 32, "uint32");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "r13", 13, 1, NULL, 32, "uint32");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "r14", 14, 1, NULL, 32, "uint32");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "r15", 15, 1, NULL, 32, "uint32");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "r16", 16, 1, NULL, 32, "uint32");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "r17", 17, 1, NULL, 32, "uint32");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "r18", 18, 1, NULL, 32, "uint32");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "r19", 19, 1, NULL, 32, "uint32");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "r20", 20, 1, NULL, 32, "uint32");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "r21", 21, 1, NULL, 32, "uint32");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "r22", 22, 1, NULL, 32, "uint32");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "r23", 23, 1, NULL, 32, "uint32");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "r24", 24, 1, NULL, 32, "uint32");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "r25", 25, 1, NULL, 32, "uint32");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "r26", 26, 1, NULL, 32, "uint32");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "r27", 27, 1, NULL, 32, "uint32");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "r28", 28, 1, NULL, 32, "uint32");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "r29", 29, 1, NULL, 32, "uint32");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "r30", 30, 1, NULL, 32, "uint32");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "r31", 31, 1, NULL, 32, "uint32");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "pc", 64, 1, NULL, 32, "code_ptr");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "msr", 65, 1, NULL, 32, "uint32");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "cr", 66, 1, NULL, 32, "uint32");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "lr", 67, 1, NULL, 32, "code_ptr");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "ctr", 68, 1, NULL, 32, "uint32");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "xer", 69, 1, NULL, 32, "uint32");
|
|
|
7cb06c |
+
|
|
|
7cb06c |
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.fpu");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "f0", 32, 1, NULL, 64, "ieee_double");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "f1", 33, 1, NULL, 64, "ieee_double");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "f2", 34, 1, NULL, 64, "ieee_double");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "f3", 35, 1, NULL, 64, "ieee_double");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "f4", 36, 1, NULL, 64, "ieee_double");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "f5", 37, 1, NULL, 64, "ieee_double");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "f6", 38, 1, NULL, 64, "ieee_double");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "f7", 39, 1, NULL, 64, "ieee_double");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "f8", 40, 1, NULL, 64, "ieee_double");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "f9", 41, 1, NULL, 64, "ieee_double");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "f10", 42, 1, NULL, 64, "ieee_double");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "f11", 43, 1, NULL, 64, "ieee_double");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "f12", 44, 1, NULL, 64, "ieee_double");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "f13", 45, 1, NULL, 64, "ieee_double");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "f14", 46, 1, NULL, 64, "ieee_double");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "f15", 47, 1, NULL, 64, "ieee_double");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "f16", 48, 1, NULL, 64, "ieee_double");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "f17", 49, 1, NULL, 64, "ieee_double");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "f18", 50, 1, NULL, 64, "ieee_double");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "f19", 51, 1, NULL, 64, "ieee_double");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "f20", 52, 1, NULL, 64, "ieee_double");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "f21", 53, 1, NULL, 64, "ieee_double");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "f22", 54, 1, NULL, 64, "ieee_double");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "f23", 55, 1, NULL, 64, "ieee_double");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "f24", 56, 1, NULL, 64, "ieee_double");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "f25", 57, 1, NULL, 64, "ieee_double");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "f26", 58, 1, NULL, 64, "ieee_double");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "f27", 59, 1, NULL, 64, "ieee_double");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "f28", 60, 1, NULL, 64, "ieee_double");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "f29", 61, 1, NULL, 64, "ieee_double");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "f30", 62, 1, NULL, 64, "ieee_double");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "f31", 63, 1, NULL, 64, "ieee_double");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "fpscr", 70, 1, "float", 64, "int");
|
|
|
7cb06c |
+
|
|
|
7cb06c |
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.linux");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "orig_r3", 71, 1, NULL, 32, "int");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "trap", 72, 1, NULL, 32, "int");
|
|
|
7cb06c |
+
|
|
|
7cb06c |
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.altivec");
|
|
|
7cb06c |
+ tdesc_type *element_type;
|
|
|
7cb06c |
+ element_type = tdesc_named_type (feature, "ieee_single");
|
|
|
7cb06c |
+ tdesc_create_vector (feature, "v4f", element_type, 4);
|
|
|
7cb06c |
+
|
|
|
7cb06c |
+ element_type = tdesc_named_type (feature, "int32");
|
|
|
7cb06c |
+ tdesc_create_vector (feature, "v4i32", element_type, 4);
|
|
|
7cb06c |
+
|
|
|
7cb06c |
+ element_type = tdesc_named_type (feature, "int16");
|
|
|
7cb06c |
+ tdesc_create_vector (feature, "v8i16", element_type, 8);
|
|
|
7cb06c |
+
|
|
|
7cb06c |
+ element_type = tdesc_named_type (feature, "int8");
|
|
|
7cb06c |
+ tdesc_create_vector (feature, "v16i8", element_type, 16);
|
|
|
7cb06c |
+
|
|
|
7cb06c |
+ tdesc_type_with_fields *type_with_fields;
|
|
|
7cb06c |
+ type_with_fields = tdesc_create_union (feature, "vec128");
|
|
|
7cb06c |
+ tdesc_type *field_type;
|
|
|
7cb06c |
+ field_type = tdesc_named_type (feature, "uint128");
|
|
|
7cb06c |
+ tdesc_add_field (type_with_fields, "uint128", field_type);
|
|
|
7cb06c |
+ field_type = tdesc_named_type (feature, "v4f");
|
|
|
7cb06c |
+ tdesc_add_field (type_with_fields, "v4_float", field_type);
|
|
|
7cb06c |
+ field_type = tdesc_named_type (feature, "v4i32");
|
|
|
7cb06c |
+ tdesc_add_field (type_with_fields, "v4_int32", field_type);
|
|
|
7cb06c |
+ field_type = tdesc_named_type (feature, "v8i16");
|
|
|
7cb06c |
+ tdesc_add_field (type_with_fields, "v8_int16", field_type);
|
|
|
7cb06c |
+ field_type = tdesc_named_type (feature, "v16i8");
|
|
|
7cb06c |
+ tdesc_add_field (type_with_fields, "v16_int8", field_type);
|
|
|
7cb06c |
+
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr0", 73, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr1", 74, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr2", 75, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr3", 76, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr4", 77, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr5", 78, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr6", 79, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr7", 80, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr8", 81, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr9", 82, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr10", 83, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr11", 84, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr12", 85, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr13", 86, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr14", 87, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr15", 88, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr16", 89, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr17", 90, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr18", 91, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr19", 92, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr20", 93, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr21", 94, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr22", 95, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr23", 96, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr24", 97, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr25", 98, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr26", 99, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr27", 100, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr28", 101, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr29", 102, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr30", 103, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr31", 104, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vscr", 105, 1, "vector", 32, "int");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vrsave", 106, 1, "vector", 32, "int");
|
|
|
7cb06c |
+
|
|
|
7cb06c |
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.vsx");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs0h", 107, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs1h", 108, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs2h", 109, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs3h", 110, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs4h", 111, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs5h", 112, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs6h", 113, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs7h", 114, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs8h", 115, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs9h", 116, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs10h", 117, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs11h", 118, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs12h", 119, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs13h", 120, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs14h", 121, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs15h", 122, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs16h", 123, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs17h", 124, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs18h", 125, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs19h", 126, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs20h", 127, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs21h", 128, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs22h", 129, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs23h", 130, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs24h", 131, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs25h", 132, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs26h", 133, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs27h", 134, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs28h", 135, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs29h", 136, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs30h", 137, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs31h", 138, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+
|
|
|
7cb06c |
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.ppr");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "ppr", 139, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+
|
|
|
7cb06c |
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.dscr");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "dscr", 140, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+
|
|
|
7cb06c |
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.tar");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "tar", 141, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+
|
|
|
7cb06c |
+ tdesc_powerpc_isa207_vsx32l = result;
|
|
|
7cb06c |
+}
|
|
|
7cb06c |
diff --git a/gdb/features/rs6000/powerpc-isa207-vsx32l.xml b/gdb/features/rs6000/powerpc-isa207-vsx32l.xml
|
|
|
7cb06c |
new file mode 100644
|
|
|
7cb06c |
--- /dev/null
|
|
|
7cb06c |
+++ b/gdb/features/rs6000/powerpc-isa207-vsx32l.xml
|
|
|
7cb06c |
@@ -0,0 +1,19 @@
|
|
|
7cb06c |
+
|
|
|
7cb06c |
+
|
|
|
7cb06c |
+
|
|
|
7cb06c |
+ Copying and distribution of this file, with or without modification,
|
|
|
7cb06c |
+ are permitted in any medium without royalty provided the copyright
|
|
|
7cb06c |
+ notice and this notice are preserved. -->
|
|
|
7cb06c |
+
|
|
|
7cb06c |
+
|
|
|
7cb06c |
+<target>
|
|
|
7cb06c |
+ <architecture>powerpc:common</architecture>
|
|
|
7cb06c |
+ <xi:include href="power-core.xml"/>
|
|
|
7cb06c |
+ <xi:include href="power-fpu-isa205.xml"/>
|
|
|
7cb06c |
+ <xi:include href="power-linux.xml"/>
|
|
|
7cb06c |
+ <xi:include href="power-altivec.xml"/>
|
|
|
7cb06c |
+ <xi:include href="power-vsx.xml"/>
|
|
|
7cb06c |
+ <xi:include href="power-ppr.xml"/>
|
|
|
7cb06c |
+ <xi:include href="power-dscr.xml"/>
|
|
|
7cb06c |
+ <xi:include href="power-tar.xml"/>
|
|
|
7cb06c |
+</target>
|
|
|
7cb06c |
diff --git a/gdb/features/rs6000/powerpc-isa207-vsx64l.c b/gdb/features/rs6000/powerpc-isa207-vsx64l.c
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7cb06c |
new file mode 100644
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7cb06c |
--- /dev/null
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7cb06c |
+++ b/gdb/features/rs6000/powerpc-isa207-vsx64l.c
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7cb06c |
@@ -0,0 +1,203 @@
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7cb06c |
+/* THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi:set ro:
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7cb06c |
+ Original: powerpc-isa207-vsx64l.xml */
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7cb06c |
+
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7cb06c |
+#include "defs.h"
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7cb06c |
+#include "osabi.h"
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7cb06c |
+#include "target-descriptions.h"
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7cb06c |
+
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7cb06c |
+struct target_desc *tdesc_powerpc_isa207_vsx64l;
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7cb06c |
+static void
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7cb06c |
+initialize_tdesc_powerpc_isa207_vsx64l (void)
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7cb06c |
+{
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7cb06c |
+ struct target_desc *result = allocate_target_description ();
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7cb06c |
+ set_tdesc_architecture (result, bfd_scan_arch ("powerpc:common64"));
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7cb06c |
+
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7cb06c |
+ struct tdesc_feature *feature;
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|
|
7cb06c |
+
|
|
|
7cb06c |
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.core");
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|
|
7cb06c |
+ tdesc_create_reg (feature, "r0", 0, 1, NULL, 64, "uint64");
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|
|
7cb06c |
+ tdesc_create_reg (feature, "r1", 1, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "r2", 2, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "r3", 3, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "r4", 4, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "r5", 5, 1, NULL, 64, "uint64");
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|
|
7cb06c |
+ tdesc_create_reg (feature, "r6", 6, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "r7", 7, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "r8", 8, 1, NULL, 64, "uint64");
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|
|
7cb06c |
+ tdesc_create_reg (feature, "r9", 9, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "r10", 10, 1, NULL, 64, "uint64");
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|
|
7cb06c |
+ tdesc_create_reg (feature, "r11", 11, 1, NULL, 64, "uint64");
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|
|
7cb06c |
+ tdesc_create_reg (feature, "r12", 12, 1, NULL, 64, "uint64");
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|
|
7cb06c |
+ tdesc_create_reg (feature, "r13", 13, 1, NULL, 64, "uint64");
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|
|
7cb06c |
+ tdesc_create_reg (feature, "r14", 14, 1, NULL, 64, "uint64");
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|
|
7cb06c |
+ tdesc_create_reg (feature, "r15", 15, 1, NULL, 64, "uint64");
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|
|
7cb06c |
+ tdesc_create_reg (feature, "r16", 16, 1, NULL, 64, "uint64");
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|
|
7cb06c |
+ tdesc_create_reg (feature, "r17", 17, 1, NULL, 64, "uint64");
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|
|
7cb06c |
+ tdesc_create_reg (feature, "r18", 18, 1, NULL, 64, "uint64");
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|
|
7cb06c |
+ tdesc_create_reg (feature, "r19", 19, 1, NULL, 64, "uint64");
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|
|
7cb06c |
+ tdesc_create_reg (feature, "r20", 20, 1, NULL, 64, "uint64");
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|
|
7cb06c |
+ tdesc_create_reg (feature, "r21", 21, 1, NULL, 64, "uint64");
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|
|
7cb06c |
+ tdesc_create_reg (feature, "r22", 22, 1, NULL, 64, "uint64");
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|
|
7cb06c |
+ tdesc_create_reg (feature, "r23", 23, 1, NULL, 64, "uint64");
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|
|
7cb06c |
+ tdesc_create_reg (feature, "r24", 24, 1, NULL, 64, "uint64");
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|
|
7cb06c |
+ tdesc_create_reg (feature, "r25", 25, 1, NULL, 64, "uint64");
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|
|
7cb06c |
+ tdesc_create_reg (feature, "r26", 26, 1, NULL, 64, "uint64");
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|
|
7cb06c |
+ tdesc_create_reg (feature, "r27", 27, 1, NULL, 64, "uint64");
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|
|
7cb06c |
+ tdesc_create_reg (feature, "r28", 28, 1, NULL, 64, "uint64");
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|
|
7cb06c |
+ tdesc_create_reg (feature, "r29", 29, 1, NULL, 64, "uint64");
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|
|
7cb06c |
+ tdesc_create_reg (feature, "r30", 30, 1, NULL, 64, "uint64");
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|
|
7cb06c |
+ tdesc_create_reg (feature, "r31", 31, 1, NULL, 64, "uint64");
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|
|
7cb06c |
+ tdesc_create_reg (feature, "pc", 64, 1, NULL, 64, "code_ptr");
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|
|
7cb06c |
+ tdesc_create_reg (feature, "msr", 65, 1, NULL, 64, "uint64");
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|
7cb06c |
+ tdesc_create_reg (feature, "cr", 66, 1, NULL, 32, "uint32");
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|
|
7cb06c |
+ tdesc_create_reg (feature, "lr", 67, 1, NULL, 64, "code_ptr");
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|
|
7cb06c |
+ tdesc_create_reg (feature, "ctr", 68, 1, NULL, 64, "uint64");
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|
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7cb06c |
+ tdesc_create_reg (feature, "xer", 69, 1, NULL, 32, "uint32");
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|
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7cb06c |
+
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|
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7cb06c |
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.fpu");
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|
|
7cb06c |
+ tdesc_create_reg (feature, "f0", 32, 1, NULL, 64, "ieee_double");
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|
|
7cb06c |
+ tdesc_create_reg (feature, "f1", 33, 1, NULL, 64, "ieee_double");
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|
7cb06c |
+ tdesc_create_reg (feature, "f2", 34, 1, NULL, 64, "ieee_double");
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|
7cb06c |
+ tdesc_create_reg (feature, "f3", 35, 1, NULL, 64, "ieee_double");
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|
|
7cb06c |
+ tdesc_create_reg (feature, "f4", 36, 1, NULL, 64, "ieee_double");
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|
|
7cb06c |
+ tdesc_create_reg (feature, "f5", 37, 1, NULL, 64, "ieee_double");
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|
|
7cb06c |
+ tdesc_create_reg (feature, "f6", 38, 1, NULL, 64, "ieee_double");
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|
|
7cb06c |
+ tdesc_create_reg (feature, "f7", 39, 1, NULL, 64, "ieee_double");
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|
7cb06c |
+ tdesc_create_reg (feature, "f8", 40, 1, NULL, 64, "ieee_double");
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|
|
7cb06c |
+ tdesc_create_reg (feature, "f9", 41, 1, NULL, 64, "ieee_double");
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|
|
7cb06c |
+ tdesc_create_reg (feature, "f10", 42, 1, NULL, 64, "ieee_double");
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|
7cb06c |
+ tdesc_create_reg (feature, "f11", 43, 1, NULL, 64, "ieee_double");
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|
7cb06c |
+ tdesc_create_reg (feature, "f12", 44, 1, NULL, 64, "ieee_double");
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|
7cb06c |
+ tdesc_create_reg (feature, "f13", 45, 1, NULL, 64, "ieee_double");
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|
|
7cb06c |
+ tdesc_create_reg (feature, "f14", 46, 1, NULL, 64, "ieee_double");
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|
7cb06c |
+ tdesc_create_reg (feature, "f15", 47, 1, NULL, 64, "ieee_double");
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|
|
7cb06c |
+ tdesc_create_reg (feature, "f16", 48, 1, NULL, 64, "ieee_double");
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|
|
7cb06c |
+ tdesc_create_reg (feature, "f17", 49, 1, NULL, 64, "ieee_double");
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|
|
7cb06c |
+ tdesc_create_reg (feature, "f18", 50, 1, NULL, 64, "ieee_double");
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|
|
7cb06c |
+ tdesc_create_reg (feature, "f19", 51, 1, NULL, 64, "ieee_double");
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|
|
7cb06c |
+ tdesc_create_reg (feature, "f20", 52, 1, NULL, 64, "ieee_double");
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|
|
7cb06c |
+ tdesc_create_reg (feature, "f21", 53, 1, NULL, 64, "ieee_double");
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|
|
7cb06c |
+ tdesc_create_reg (feature, "f22", 54, 1, NULL, 64, "ieee_double");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "f23", 55, 1, NULL, 64, "ieee_double");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "f24", 56, 1, NULL, 64, "ieee_double");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "f25", 57, 1, NULL, 64, "ieee_double");
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|
|
7cb06c |
+ tdesc_create_reg (feature, "f26", 58, 1, NULL, 64, "ieee_double");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "f27", 59, 1, NULL, 64, "ieee_double");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "f28", 60, 1, NULL, 64, "ieee_double");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "f29", 61, 1, NULL, 64, "ieee_double");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "f30", 62, 1, NULL, 64, "ieee_double");
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|
|
7cb06c |
+ tdesc_create_reg (feature, "f31", 63, 1, NULL, 64, "ieee_double");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "fpscr", 70, 1, "float", 64, "int");
|
|
|
7cb06c |
+
|
|
|
7cb06c |
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.linux");
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|
|
7cb06c |
+ tdesc_create_reg (feature, "orig_r3", 71, 1, NULL, 64, "int");
|
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|
7cb06c |
+ tdesc_create_reg (feature, "trap", 72, 1, NULL, 64, "int");
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|
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7cb06c |
+
|
|
|
7cb06c |
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.altivec");
|
|
|
7cb06c |
+ tdesc_type *element_type;
|
|
|
7cb06c |
+ element_type = tdesc_named_type (feature, "ieee_single");
|
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|
7cb06c |
+ tdesc_create_vector (feature, "v4f", element_type, 4);
|
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|
7cb06c |
+
|
|
|
7cb06c |
+ element_type = tdesc_named_type (feature, "int32");
|
|
|
7cb06c |
+ tdesc_create_vector (feature, "v4i32", element_type, 4);
|
|
|
7cb06c |
+
|
|
|
7cb06c |
+ element_type = tdesc_named_type (feature, "int16");
|
|
|
7cb06c |
+ tdesc_create_vector (feature, "v8i16", element_type, 8);
|
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|
7cb06c |
+
|
|
|
7cb06c |
+ element_type = tdesc_named_type (feature, "int8");
|
|
|
7cb06c |
+ tdesc_create_vector (feature, "v16i8", element_type, 16);
|
|
|
7cb06c |
+
|
|
|
7cb06c |
+ tdesc_type_with_fields *type_with_fields;
|
|
|
7cb06c |
+ type_with_fields = tdesc_create_union (feature, "vec128");
|
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|
7cb06c |
+ tdesc_type *field_type;
|
|
|
7cb06c |
+ field_type = tdesc_named_type (feature, "uint128");
|
|
|
7cb06c |
+ tdesc_add_field (type_with_fields, "uint128", field_type);
|
|
|
7cb06c |
+ field_type = tdesc_named_type (feature, "v4f");
|
|
|
7cb06c |
+ tdesc_add_field (type_with_fields, "v4_float", field_type);
|
|
|
7cb06c |
+ field_type = tdesc_named_type (feature, "v4i32");
|
|
|
7cb06c |
+ tdesc_add_field (type_with_fields, "v4_int32", field_type);
|
|
|
7cb06c |
+ field_type = tdesc_named_type (feature, "v8i16");
|
|
|
7cb06c |
+ tdesc_add_field (type_with_fields, "v8_int16", field_type);
|
|
|
7cb06c |
+ field_type = tdesc_named_type (feature, "v16i8");
|
|
|
7cb06c |
+ tdesc_add_field (type_with_fields, "v16_int8", field_type);
|
|
|
7cb06c |
+
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr0", 73, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr1", 74, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr2", 75, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr3", 76, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr4", 77, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr5", 78, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr6", 79, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr7", 80, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr8", 81, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr9", 82, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr10", 83, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr11", 84, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr12", 85, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr13", 86, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr14", 87, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr15", 88, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr16", 89, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr17", 90, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr18", 91, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr19", 92, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr20", 93, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr21", 94, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr22", 95, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr23", 96, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr24", 97, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr25", 98, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr26", 99, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr27", 100, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr28", 101, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr29", 102, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr30", 103, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vr31", 104, 1, NULL, 128, "vec128");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vscr", 105, 1, "vector", 32, "int");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vrsave", 106, 1, "vector", 32, "int");
|
|
|
7cb06c |
+
|
|
|
7cb06c |
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.vsx");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs0h", 107, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs1h", 108, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs2h", 109, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs3h", 110, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs4h", 111, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs5h", 112, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs6h", 113, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs7h", 114, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs8h", 115, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs9h", 116, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs10h", 117, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs11h", 118, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs12h", 119, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs13h", 120, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs14h", 121, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs15h", 122, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs16h", 123, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs17h", 124, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs18h", 125, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs19h", 126, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs20h", 127, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs21h", 128, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs22h", 129, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs23h", 130, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs24h", 131, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs25h", 132, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs26h", 133, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs27h", 134, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs28h", 135, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs29h", 136, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs30h", 137, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "vs31h", 138, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+
|
|
|
7cb06c |
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.ppr");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "ppr", 139, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+
|
|
|
7cb06c |
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.dscr");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "dscr", 140, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+
|
|
|
7cb06c |
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.tar");
|
|
|
7cb06c |
+ tdesc_create_reg (feature, "tar", 141, 1, NULL, 64, "uint64");
|
|
|
7cb06c |
+
|
|
|
7cb06c |
+ tdesc_powerpc_isa207_vsx64l = result;
|
|
|
7cb06c |
+}
|
|
|
7cb06c |
diff --git a/gdb/features/rs6000/powerpc-isa207-vsx64l.xml b/gdb/features/rs6000/powerpc-isa207-vsx64l.xml
|
|
|
7cb06c |
new file mode 100644
|
|
|
7cb06c |
--- /dev/null
|
|
|
7cb06c |
+++ b/gdb/features/rs6000/powerpc-isa207-vsx64l.xml
|
|
|
7cb06c |
@@ -0,0 +1,19 @@
|
|
|
7cb06c |
+
|
|
|
7cb06c |
+
|
|
|
7cb06c |
+
|
|
|
7cb06c |
+ Copying and distribution of this file, with or without modification,
|
|
|
7cb06c |
+ are permitted in any medium without royalty provided the copyright
|
|
|
7cb06c |
+ notice and this notice are preserved. -->
|
|
|
7cb06c |
+
|
|
|
7cb06c |
+
|
|
|
7cb06c |
+<target>
|
|
|
7cb06c |
+ <architecture>powerpc:common64</architecture>
|
|
|
7cb06c |
+ <xi:include href="power64-core.xml"/>
|
|
|
7cb06c |
+ <xi:include href="power-fpu-isa205.xml"/>
|
|
|
7cb06c |
+ <xi:include href="power64-linux.xml"/>
|
|
|
7cb06c |
+ <xi:include href="power-altivec.xml"/>
|
|
|
7cb06c |
+ <xi:include href="power-vsx.xml"/>
|
|
|
7cb06c |
+ <xi:include href="power-ppr.xml"/>
|
|
|
7cb06c |
+ <xi:include href="power-dscr.xml"/>
|
|
|
7cb06c |
+ <xi:include href="power-tar.xml"/>
|
|
|
7cb06c |
+</target>
|
|
|
7cb06c |
diff --git a/gdb/gdbserver/configure.srv b/gdb/gdbserver/configure.srv
|
|
|
7cb06c |
--- a/gdb/gdbserver/configure.srv
|
|
|
7cb06c |
+++ b/gdb/gdbserver/configure.srv
|
|
|
7cb06c |
@@ -32,7 +32,7 @@ else
|
|
|
7cb06c |
srv_amd64_linux_regobj=""
|
|
|
7cb06c |
fi
|
|
|
7cb06c |
|
|
|
7cb06c |
-ipa_ppc_linux_regobj="powerpc-32l-ipa.o powerpc-altivec32l-ipa.o powerpc-cell32l-ipa.o powerpc-vsx32l-ipa.o powerpc-isa205-32l-ipa.o powerpc-isa205-altivec32l-ipa.o powerpc-isa205-vsx32l-ipa.o powerpc-isa205-ppr-dscr-vsx32l-ipa.o powerpc-e500l-ipa.o powerpc-64l-ipa.o powerpc-altivec64l-ipa.o powerpc-cell64l-ipa.o powerpc-vsx64l-ipa.o powerpc-isa205-64l-ipa.o powerpc-isa205-altivec64l-ipa.o powerpc-isa205-vsx64l-ipa.o powerpc-isa205-ppr-dscr-vsx64l-ipa.o"
|
|
|
7cb06c |
+ipa_ppc_linux_regobj="powerpc-32l-ipa.o powerpc-altivec32l-ipa.o powerpc-cell32l-ipa.o powerpc-vsx32l-ipa.o powerpc-isa205-32l-ipa.o powerpc-isa205-altivec32l-ipa.o powerpc-isa205-vsx32l-ipa.o powerpc-isa205-ppr-dscr-vsx32l-ipa.o powerpc-isa207-vsx32l-ipa.o powerpc-e500l-ipa.o powerpc-64l-ipa.o powerpc-altivec64l-ipa.o powerpc-cell64l-ipa.o powerpc-vsx64l-ipa.o powerpc-isa205-64l-ipa.o powerpc-isa205-altivec64l-ipa.o powerpc-isa205-vsx64l-ipa.o powerpc-isa205-ppr-dscr-vsx64l-ipa.o powerpc-isa207-vsx64l-ipa.o"
|
|
|
7cb06c |
|
|
|
7cb06c |
# Linux object files. This is so we don't have to repeat
|
|
|
7cb06c |
# these files over and over again.
|
|
|
7cb06c |
@@ -218,6 +218,7 @@ case "${target}" in
|
|
|
7cb06c |
srv_regobj="${srv_regobj} powerpc-isa205-altivec32l.o"
|
|
|
7cb06c |
srv_regobj="${srv_regobj} powerpc-isa205-vsx32l.o"
|
|
|
7cb06c |
srv_regobj="${srv_regobj} powerpc-isa205-ppr-dscr-vsx32l.o"
|
|
|
7cb06c |
+ srv_regobj="${srv_regobj} powerpc-isa207-vsx32l.o"
|
|
|
7cb06c |
srv_regobj="${srv_regobj} powerpc-e500l.o"
|
|
|
7cb06c |
srv_regobj="${srv_regobj} powerpc-64l.o"
|
|
|
7cb06c |
srv_regobj="${srv_regobj} powerpc-altivec64l.o"
|
|
|
7cb06c |
@@ -227,6 +228,7 @@ case "${target}" in
|
|
|
7cb06c |
srv_regobj="${srv_regobj} powerpc-isa205-altivec64l.o"
|
|
|
7cb06c |
srv_regobj="${srv_regobj} powerpc-isa205-vsx64l.o"
|
|
|
7cb06c |
srv_regobj="${srv_regobj} powerpc-isa205-ppr-dscr-vsx64l.o"
|
|
|
7cb06c |
+ srv_regobj="${srv_regobj} powerpc-isa207-vsx64l.o"
|
|
|
7cb06c |
srv_tgtobj="$srv_linux_obj linux-ppc-low.o ppc-linux.o"
|
|
|
7cb06c |
srv_tgtobj="${srv_tgtobj} arch/ppc-linux-common.o"
|
|
|
7cb06c |
srv_xmlfiles="rs6000/powerpc-32l.xml"
|
|
|
7cb06c |
@@ -237,6 +239,7 @@ case "${target}" in
|
|
|
7cb06c |
srv_xmlfiles="${srv_xmlfiles} rs6000/powerpc-isa205-altivec32l.xml"
|
|
|
7cb06c |
srv_xmlfiles="${srv_xmlfiles} rs6000/powerpc-isa205-vsx32l.xml"
|
|
|
7cb06c |
srv_xmlfiles="${srv_xmlfiles} rs6000/powerpc-isa205-ppr-dscr-vsx32l.xml"
|
|
|
7cb06c |
+ srv_xmlfiles="${srv_xmlfiles} rs6000/powerpc-isa207-vsx32l.xml"
|
|
|
7cb06c |
srv_xmlfiles="${srv_xmlfiles} rs6000/power-altivec.xml"
|
|
|
7cb06c |
srv_xmlfiles="${srv_xmlfiles} rs6000/power-vsx.xml"
|
|
|
7cb06c |
srv_xmlfiles="${srv_xmlfiles} rs6000/power-core.xml"
|
|
|
7cb06c |
@@ -245,6 +248,7 @@ case "${target}" in
|
|
|
7cb06c |
srv_xmlfiles="${srv_xmlfiles} rs6000/power-fpu-isa205.xml"
|
|
|
7cb06c |
srv_xmlfiles="${srv_xmlfiles} rs6000/power-dscr.xml"
|
|
|
7cb06c |
srv_xmlfiles="${srv_xmlfiles} rs6000/power-ppr.xml"
|
|
|
7cb06c |
+ srv_xmlfiles="${srv_xmlfiles} rs6000/power-tar.xml"
|
|
|
7cb06c |
srv_xmlfiles="${srv_xmlfiles} rs6000/powerpc-e500l.xml"
|
|
|
7cb06c |
srv_xmlfiles="${srv_xmlfiles} rs6000/power-spe.xml"
|
|
|
7cb06c |
srv_xmlfiles="${srv_xmlfiles} rs6000/powerpc-64l.xml"
|
|
|
7cb06c |
@@ -255,6 +259,7 @@ case "${target}" in
|
|
|
7cb06c |
srv_xmlfiles="${srv_xmlfiles} rs6000/powerpc-isa205-altivec64l.xml"
|
|
|
7cb06c |
srv_xmlfiles="${srv_xmlfiles} rs6000/powerpc-isa205-vsx64l.xml"
|
|
|
7cb06c |
srv_xmlfiles="${srv_xmlfiles} rs6000/powerpc-isa205-ppr-dscr-vsx64l.xml"
|
|
|
7cb06c |
+ srv_xmlfiles="${srv_xmlfiles} rs6000/powerpc-isa207-vsx64l.xml"
|
|
|
7cb06c |
srv_xmlfiles="${srv_xmlfiles} rs6000/power64-core.xml"
|
|
|
7cb06c |
srv_xmlfiles="${srv_xmlfiles} rs6000/power64-linux.xml"
|
|
|
7cb06c |
srv_linux_usrregs=yes
|
|
|
7cb06c |
diff --git a/gdb/gdbserver/linux-ppc-ipa.c b/gdb/gdbserver/linux-ppc-ipa.c
|
|
|
7cb06c |
--- a/gdb/gdbserver/linux-ppc-ipa.c
|
|
|
7cb06c |
+++ b/gdb/gdbserver/linux-ppc-ipa.c
|
|
|
7cb06c |
@@ -193,6 +193,8 @@ get_ipa_tdesc (int idx)
|
|
|
7cb06c |
return tdesc_powerpc_isa205_vsx64l;
|
|
|
7cb06c |
case PPC_TDESC_ISA205_PPR_DSCR_VSX:
|
|
|
7cb06c |
return tdesc_powerpc_isa205_ppr_dscr_vsx64l;
|
|
|
7cb06c |
+ case PPC_TDESC_ISA207_VSX:
|
|
|
7cb06c |
+ return tdesc_powerpc_isa207_vsx64l;
|
|
|
7cb06c |
#else
|
|
|
7cb06c |
case PPC_TDESC_BASE:
|
|
|
7cb06c |
return tdesc_powerpc_32l;
|
|
|
7cb06c |
@@ -210,6 +212,8 @@ get_ipa_tdesc (int idx)
|
|
|
7cb06c |
return tdesc_powerpc_isa205_vsx32l;
|
|
|
7cb06c |
case PPC_TDESC_ISA205_PPR_DSCR_VSX:
|
|
|
7cb06c |
return tdesc_powerpc_isa205_ppr_dscr_vsx32l;
|
|
|
7cb06c |
+ case PPC_TDESC_ISA207_VSX:
|
|
|
7cb06c |
+ return tdesc_powerpc_isa207_vsx32l;
|
|
|
7cb06c |
case PPC_TDESC_E500:
|
|
|
7cb06c |
return tdesc_powerpc_e500l;
|
|
|
7cb06c |
#endif
|
|
|
7cb06c |
@@ -239,6 +243,7 @@ initialize_low_tracepoint (void)
|
|
|
7cb06c |
init_registers_powerpc_isa205_altivec64l ();
|
|
|
7cb06c |
init_registers_powerpc_isa205_vsx64l ();
|
|
|
7cb06c |
init_registers_powerpc_isa205_ppr_dscr_vsx64l ();
|
|
|
7cb06c |
+ init_registers_powerpc_isa207_vsx64l ();
|
|
|
7cb06c |
#else
|
|
|
7cb06c |
init_registers_powerpc_32l ();
|
|
|
7cb06c |
init_registers_powerpc_altivec32l ();
|
|
|
7cb06c |
@@ -248,6 +253,7 @@ initialize_low_tracepoint (void)
|
|
|
7cb06c |
init_registers_powerpc_isa205_altivec32l ();
|
|
|
7cb06c |
init_registers_powerpc_isa205_vsx32l ();
|
|
|
7cb06c |
init_registers_powerpc_isa205_ppr_dscr_vsx32l ();
|
|
|
7cb06c |
+ init_registers_powerpc_isa207_vsx32l ();
|
|
|
7cb06c |
init_registers_powerpc_e500l ();
|
|
|
7cb06c |
#endif
|
|
|
7cb06c |
}
|
|
|
7cb06c |
diff --git a/gdb/gdbserver/linux-ppc-low.c b/gdb/gdbserver/linux-ppc-low.c
|
|
|
7cb06c |
--- a/gdb/gdbserver/linux-ppc-low.c
|
|
|
7cb06c |
+++ b/gdb/gdbserver/linux-ppc-low.c
|
|
|
7cb06c |
@@ -525,6 +525,26 @@ ppc_store_dscrregset (struct regcache *regcache, const void *buf)
|
|
|
7cb06c |
supply_register_by_name (regcache, "dscr", dscr);
|
|
|
7cb06c |
}
|
|
|
7cb06c |
|
|
|
7cb06c |
+/* Target Address Register regset fill function. */
|
|
|
7cb06c |
+
|
|
|
7cb06c |
+static void
|
|
|
7cb06c |
+ppc_fill_tarregset (struct regcache *regcache, void *buf)
|
|
|
7cb06c |
+{
|
|
|
7cb06c |
+ char *tar = (char *) buf;
|
|
|
7cb06c |
+
|
|
|
7cb06c |
+ collect_register_by_name (regcache, "tar", tar);
|
|
|
7cb06c |
+}
|
|
|
7cb06c |
+
|
|
|
7cb06c |
+/* Target Address Register regset store function. */
|
|
|
7cb06c |
+
|
|
|
7cb06c |
+static void
|
|
|
7cb06c |
+ppc_store_tarregset (struct regcache *regcache, const void *buf)
|
|
|
7cb06c |
+{
|
|
|
7cb06c |
+ const char *tar = (const char *) buf;
|
|
|
7cb06c |
+
|
|
|
7cb06c |
+ supply_register_by_name (regcache, "tar", tar);
|
|
|
7cb06c |
+}
|
|
|
7cb06c |
+
|
|
|
7cb06c |
static void
|
|
|
7cb06c |
ppc_fill_vsxregset (struct regcache *regcache, void *buf)
|
|
|
7cb06c |
{
|
|
|
7cb06c |
@@ -634,6 +654,8 @@ static struct regset_info ppc_regsets[] = {
|
|
|
7cb06c |
fetch them every time, but still fall back to PTRACE_PEEKUSER for the
|
|
|
7cb06c |
general registers. Some kernels support these, but not the newer
|
|
|
7cb06c |
PPC_PTRACE_GETREGS. */
|
|
|
7cb06c |
+ { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TAR, 0, EXTENDED_REGS,
|
|
|
7cb06c |
+ ppc_fill_tarregset, ppc_store_tarregset },
|
|
|
7cb06c |
{ PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_PPR, 0, EXTENDED_REGS,
|
|
|
7cb06c |
ppc_fill_pprregset, ppc_store_pprregset },
|
|
|
7cb06c |
{ PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_DSCR, 0, EXTENDED_REGS,
|
|
|
7cb06c |
@@ -708,7 +730,14 @@ ppc_arch_setup (void)
|
|
|
7cb06c |
if ((ppc_hwcap2 & PPC_FEATURE2_DSCR)
|
|
|
7cb06c |
&& ppc_check_regset (tid, NT_PPC_DSCR, PPC_LINUX_SIZEOF_DSCRREGSET)
|
|
|
7cb06c |
&& ppc_check_regset (tid, NT_PPC_PPR, PPC_LINUX_SIZEOF_PPRREGSET))
|
|
|
7cb06c |
- features.ppr_dscr = true;
|
|
|
7cb06c |
+ {
|
|
|
7cb06c |
+ features.ppr_dscr = true;
|
|
|
7cb06c |
+ if ((ppc_hwcap2 & PPC_FEATURE2_ARCH_2_07)
|
|
|
7cb06c |
+ && (ppc_hwcap2 & PPC_FEATURE2_TAR)
|
|
|
7cb06c |
+ && ppc_check_regset (tid, NT_PPC_TAR,
|
|
|
7cb06c |
+ PPC_LINUX_SIZEOF_TARREGSET))
|
|
|
7cb06c |
+ features.isa207 = true;
|
|
|
7cb06c |
+ }
|
|
|
7cb06c |
|
|
|
7cb06c |
if (ppc_hwcap & PPC_FEATURE_CELL)
|
|
|
7cb06c |
features.cell = true;
|
|
|
7cb06c |
@@ -765,6 +794,10 @@ ppc_arch_setup (void)
|
|
|
7cb06c |
regset->size = (features.ppr_dscr ?
|
|
|
7cb06c |
PPC_LINUX_SIZEOF_DSCRREGSET : 0);
|
|
|
7cb06c |
break;
|
|
|
7cb06c |
+ case NT_PPC_TAR:
|
|
|
7cb06c |
+ regset->size = (features.isa207 ?
|
|
|
7cb06c |
+ PPC_LINUX_SIZEOF_TARREGSET : 0);
|
|
|
7cb06c |
+ break;
|
|
|
7cb06c |
default:
|
|
|
7cb06c |
break;
|
|
|
7cb06c |
}
|
|
|
7cb06c |
@@ -3146,6 +3179,8 @@ ppc_get_ipa_tdesc_idx (void)
|
|
|
7cb06c |
return PPC_TDESC_ISA205_VSX;
|
|
|
7cb06c |
if (tdesc == tdesc_powerpc_isa205_ppr_dscr_vsx64l)
|
|
|
7cb06c |
return PPC_TDESC_ISA205_PPR_DSCR_VSX;
|
|
|
7cb06c |
+ if (tdesc == tdesc_powerpc_isa207_vsx64l)
|
|
|
7cb06c |
+ return PPC_TDESC_ISA207_VSX;
|
|
|
7cb06c |
#endif
|
|
|
7cb06c |
|
|
|
7cb06c |
if (tdesc == tdesc_powerpc_32l)
|
|
|
7cb06c |
@@ -3164,6 +3199,8 @@ ppc_get_ipa_tdesc_idx (void)
|
|
|
7cb06c |
return PPC_TDESC_ISA205_VSX;
|
|
|
7cb06c |
if (tdesc == tdesc_powerpc_isa205_ppr_dscr_vsx32l)
|
|
|
7cb06c |
return PPC_TDESC_ISA205_PPR_DSCR_VSX;
|
|
|
7cb06c |
+ if (tdesc == tdesc_powerpc_isa207_vsx32l)
|
|
|
7cb06c |
+ return PPC_TDESC_ISA207_VSX;
|
|
|
7cb06c |
if (tdesc == tdesc_powerpc_e500l)
|
|
|
7cb06c |
return PPC_TDESC_E500;
|
|
|
7cb06c |
|
|
|
7cb06c |
@@ -3223,6 +3260,7 @@ initialize_low_arch (void)
|
|
|
7cb06c |
init_registers_powerpc_isa205_altivec32l ();
|
|
|
7cb06c |
init_registers_powerpc_isa205_vsx32l ();
|
|
|
7cb06c |
init_registers_powerpc_isa205_ppr_dscr_vsx32l ();
|
|
|
7cb06c |
+ init_registers_powerpc_isa207_vsx32l ();
|
|
|
7cb06c |
init_registers_powerpc_e500l ();
|
|
|
7cb06c |
#if __powerpc64__
|
|
|
7cb06c |
init_registers_powerpc_64l ();
|
|
|
7cb06c |
@@ -3233,6 +3271,7 @@ initialize_low_arch (void)
|
|
|
7cb06c |
init_registers_powerpc_isa205_altivec64l ();
|
|
|
7cb06c |
init_registers_powerpc_isa205_vsx64l ();
|
|
|
7cb06c |
init_registers_powerpc_isa205_ppr_dscr_vsx64l ();
|
|
|
7cb06c |
+ init_registers_powerpc_isa207_vsx64l ();
|
|
|
7cb06c |
#endif
|
|
|
7cb06c |
|
|
|
7cb06c |
initialize_regsets_info (&ppc_regsets_info);
|
|
|
7cb06c |
diff --git a/gdb/gdbserver/linux-ppc-tdesc-init.h b/gdb/gdbserver/linux-ppc-tdesc-init.h
|
|
|
7cb06c |
--- a/gdb/gdbserver/linux-ppc-tdesc-init.h
|
|
|
7cb06c |
+++ b/gdb/gdbserver/linux-ppc-tdesc-init.h
|
|
|
7cb06c |
@@ -30,6 +30,7 @@ enum ppc_linux_tdesc {
|
|
|
7cb06c |
PPC_TDESC_ISA205_ALTIVEC,
|
|
|
7cb06c |
PPC_TDESC_ISA205_VSX,
|
|
|
7cb06c |
PPC_TDESC_ISA205_PPR_DSCR_VSX,
|
|
|
7cb06c |
+ PPC_TDESC_ISA207_VSX,
|
|
|
7cb06c |
PPC_TDESC_E500,
|
|
|
7cb06c |
};
|
|
|
7cb06c |
|
|
|
7cb06c |
@@ -59,6 +60,9 @@ void init_registers_powerpc_isa205_vsx32l (void);
|
|
|
7cb06c |
/* Defined in auto-generated file powerpc-isa205-ppr-dscr-vsx32l.c. */
|
|
|
7cb06c |
void init_registers_powerpc_isa205_ppr_dscr_vsx32l (void);
|
|
|
7cb06c |
|
|
|
7cb06c |
+/* Defined in auto-generated file powerpc-isa207-vsx32l.c. */
|
|
|
7cb06c |
+void init_registers_powerpc_isa207_vsx32l (void);
|
|
|
7cb06c |
+
|
|
|
7cb06c |
/* Defined in auto-generated file powerpc-e500l.c. */
|
|
|
7cb06c |
void init_registers_powerpc_e500l (void);
|
|
|
7cb06c |
|
|
|
7cb06c |
@@ -90,4 +94,7 @@ void init_registers_powerpc_isa205_vsx64l (void);
|
|
|
7cb06c |
/* Defined in auto-generated file powerpc-isa205-ppr-dscr-vsx64l.c. */
|
|
|
7cb06c |
void init_registers_powerpc_isa205_ppr_dscr_vsx64l (void);
|
|
|
7cb06c |
|
|
|
7cb06c |
+/* Defined in auto-generated file powerpc-isa207-vsx64l.c. */
|
|
|
7cb06c |
+void init_registers_powerpc_isa207_vsx64l (void);
|
|
|
7cb06c |
+
|
|
|
7cb06c |
#endif
|
|
|
7cb06c |
diff --git a/gdb/nat/ppc-linux.h b/gdb/nat/ppc-linux.h
|
|
|
7cb06c |
--- a/gdb/nat/ppc-linux.h
|
|
|
7cb06c |
+++ b/gdb/nat/ppc-linux.h
|
|
|
7cb06c |
@@ -54,6 +54,12 @@
|
|
|
7cb06c |
#ifndef PPC_FEATURE2_DSCR
|
|
|
7cb06c |
#define PPC_FEATURE2_DSCR 0x20000000
|
|
|
7cb06c |
#endif
|
|
|
7cb06c |
+#ifndef PPC_FEATURE2_ARCH_2_07
|
|
|
7cb06c |
+#define PPC_FEATURE2_ARCH_2_07 0x80000000
|
|
|
7cb06c |
+#endif
|
|
|
7cb06c |
+#ifndef PPC_FEATURE2_TAR
|
|
|
7cb06c |
+#define PPC_FEATURE2_TAR 0x04000000
|
|
|
7cb06c |
+#endif
|
|
|
7cb06c |
|
|
|
7cb06c |
/* Glibc's headers don't define PTRACE_GETVRREGS so we cannot use a
|
|
|
7cb06c |
configure time check. Some older glibc's (for instance 2.2.1)
|
|
|
7cb06c |
@@ -85,6 +91,11 @@
|
|
|
7cb06c |
#define PTRACE_SETEVRREGS 21
|
|
|
7cb06c |
#endif
|
|
|
7cb06c |
|
|
|
7cb06c |
+/* Target Address Register. */
|
|
|
7cb06c |
+#ifndef NT_PPC_TAR
|
|
|
7cb06c |
+#define NT_PPC_TAR 0x103
|
|
|
7cb06c |
+#endif
|
|
|
7cb06c |
+
|
|
|
7cb06c |
/* Program Priority Register. */
|
|
|
7cb06c |
#ifndef NT_PPC_PPR
|
|
|
7cb06c |
#define NT_PPC_PPR 0x104
|
|
|
7cb06c |
diff --git a/gdb/ppc-linux-nat.c b/gdb/ppc-linux-nat.c
|
|
|
7cb06c |
--- a/gdb/ppc-linux-nat.c
|
|
|
7cb06c |
+++ b/gdb/ppc-linux-nat.c
|
|
|
7cb06c |
@@ -658,6 +658,15 @@ fetch_register (struct regcache *regcache, int tid, int regno)
|
|
|
7cb06c |
&ppc32_linux_pprregset);
|
|
|
7cb06c |
return;
|
|
|
7cb06c |
}
|
|
|
7cb06c |
+ else if (regno == PPC_TAR_REGNUM)
|
|
|
7cb06c |
+ {
|
|
|
7cb06c |
+ gdb_assert (tdep->ppc_tar_regnum != -1);
|
|
|
7cb06c |
+
|
|
|
7cb06c |
+ fetch_regset (regcache, tid, NT_PPC_TAR,
|
|
|
7cb06c |
+ PPC_LINUX_SIZEOF_TARREGSET,
|
|
|
7cb06c |
+ &ppc32_linux_tarregset);
|
|
|
7cb06c |
+ return;
|
|
|
7cb06c |
+ }
|
|
|
7cb06c |
|
|
|
7cb06c |
if (regaddr == -1)
|
|
|
7cb06c |
{
|
|
|
7cb06c |
@@ -862,6 +871,10 @@ fetch_ppc_registers (struct regcache *regcache, int tid)
|
|
|
7cb06c |
fetch_regset (regcache, tid, NT_PPC_DSCR,
|
|
|
7cb06c |
PPC_LINUX_SIZEOF_DSCRREGSET,
|
|
|
7cb06c |
&ppc32_linux_dscrregset);
|
|
|
7cb06c |
+ if (tdep->ppc_tar_regnum != -1)
|
|
|
7cb06c |
+ fetch_regset (regcache, tid, NT_PPC_TAR,
|
|
|
7cb06c |
+ PPC_LINUX_SIZEOF_TARREGSET,
|
|
|
7cb06c |
+ &ppc32_linux_tarregset);
|
|
|
7cb06c |
}
|
|
|
7cb06c |
|
|
|
7cb06c |
/* Fetch registers from the child process. Fetch all registers if
|
|
|
7cb06c |
@@ -1060,6 +1073,15 @@ store_register (const struct regcache *regcache, int tid, int regno)
|
|
|
7cb06c |
&ppc32_linux_pprregset);
|
|
|
7cb06c |
return;
|
|
|
7cb06c |
}
|
|
|
7cb06c |
+ else if (regno == PPC_TAR_REGNUM)
|
|
|
7cb06c |
+ {
|
|
|
7cb06c |
+ gdb_assert (tdep->ppc_tar_regnum != -1);
|
|
|
7cb06c |
+
|
|
|
7cb06c |
+ store_regset (regcache, tid, regno, NT_PPC_TAR,
|
|
|
7cb06c |
+ PPC_LINUX_SIZEOF_TARREGSET,
|
|
|
7cb06c |
+ &ppc32_linux_tarregset);
|
|
|
7cb06c |
+ return;
|
|
|
7cb06c |
+ }
|
|
|
7cb06c |
|
|
|
7cb06c |
if (regaddr == -1)
|
|
|
7cb06c |
return;
|
|
|
7cb06c |
@@ -1282,6 +1304,10 @@ store_ppc_registers (const struct regcache *regcache, int tid)
|
|
|
7cb06c |
store_regset (regcache, tid, -1, NT_PPC_DSCR,
|
|
|
7cb06c |
PPC_LINUX_SIZEOF_DSCRREGSET,
|
|
|
7cb06c |
&ppc32_linux_dscrregset);
|
|
|
7cb06c |
+ if (tdep->ppc_tar_regnum != -1)
|
|
|
7cb06c |
+ store_regset (regcache, tid, -1, NT_PPC_TAR,
|
|
|
7cb06c |
+ PPC_LINUX_SIZEOF_TARREGSET,
|
|
|
7cb06c |
+ &ppc32_linux_tarregset);
|
|
|
7cb06c |
}
|
|
|
7cb06c |
|
|
|
7cb06c |
/* Fetch the AT_HWCAP entry from the aux vector. */
|
|
|
7cb06c |
@@ -2409,7 +2435,13 @@ ppc_linux_nat_target::read_description ()
|
|
|
7cb06c |
if ((hwcap2 & PPC_FEATURE2_DSCR)
|
|
|
7cb06c |
&& check_regset (tid, NT_PPC_PPR, PPC_LINUX_SIZEOF_PPRREGSET)
|
|
|
7cb06c |
&& check_regset (tid, NT_PPC_DSCR, PPC_LINUX_SIZEOF_DSCRREGSET))
|
|
|
7cb06c |
- features.ppr_dscr = true;
|
|
|
7cb06c |
+ {
|
|
|
7cb06c |
+ features.ppr_dscr = true;
|
|
|
7cb06c |
+ if ((hwcap2 & PPC_FEATURE2_ARCH_2_07)
|
|
|
7cb06c |
+ && (hwcap2 & PPC_FEATURE2_TAR)
|
|
|
7cb06c |
+ && check_regset (tid, NT_PPC_TAR, PPC_LINUX_SIZEOF_TARREGSET))
|
|
|
7cb06c |
+ features.isa207 = true;
|
|
|
7cb06c |
+ }
|
|
|
7cb06c |
|
|
|
7cb06c |
return ppc_linux_match_description (features);
|
|
|
7cb06c |
}
|
|
|
7cb06c |
diff --git a/gdb/ppc-linux-tdep.c b/gdb/ppc-linux-tdep.c
|
|
|
7cb06c |
--- a/gdb/ppc-linux-tdep.c
|
|
|
7cb06c |
+++ b/gdb/ppc-linux-tdep.c
|
|
|
7cb06c |
@@ -72,6 +72,7 @@
|
|
|
7cb06c |
#include "features/rs6000/powerpc-isa205-altivec32l.c"
|
|
|
7cb06c |
#include "features/rs6000/powerpc-isa205-vsx32l.c"
|
|
|
7cb06c |
#include "features/rs6000/powerpc-isa205-ppr-dscr-vsx32l.c"
|
|
|
7cb06c |
+#include "features/rs6000/powerpc-isa207-vsx32l.c"
|
|
|
7cb06c |
#include "features/rs6000/powerpc-64l.c"
|
|
|
7cb06c |
#include "features/rs6000/powerpc-altivec64l.c"
|
|
|
7cb06c |
#include "features/rs6000/powerpc-cell64l.c"
|
|
|
7cb06c |
@@ -80,6 +81,7 @@
|
|
|
7cb06c |
#include "features/rs6000/powerpc-isa205-altivec64l.c"
|
|
|
7cb06c |
#include "features/rs6000/powerpc-isa205-vsx64l.c"
|
|
|
7cb06c |
#include "features/rs6000/powerpc-isa205-ppr-dscr-vsx64l.c"
|
|
|
7cb06c |
+#include "features/rs6000/powerpc-isa207-vsx64l.c"
|
|
|
7cb06c |
#include "features/rs6000/powerpc-e500l.c"
|
|
|
7cb06c |
|
|
|
7cb06c |
/* Shared library operations for PowerPC-Linux. */
|
|
|
7cb06c |
@@ -581,6 +583,22 @@ const struct regset ppc32_linux_dscrregset = {
|
|
|
7cb06c |
regcache_collect_regset
|
|
|
7cb06c |
};
|
|
|
7cb06c |
|
|
|
7cb06c |
+/* Target Address Register regmap. */
|
|
|
7cb06c |
+
|
|
|
7cb06c |
+static const struct regcache_map_entry ppc32_regmap_tar[] =
|
|
|
7cb06c |
+ {
|
|
|
7cb06c |
+ { 1, PPC_TAR_REGNUM, 8 },
|
|
|
7cb06c |
+ { 0 }
|
|
|
7cb06c |
+ };
|
|
|
7cb06c |
+
|
|
|
7cb06c |
+/* Target Address Register regset. */
|
|
|
7cb06c |
+
|
|
|
7cb06c |
+const struct regset ppc32_linux_tarregset = {
|
|
|
7cb06c |
+ ppc32_regmap_tar,
|
|
|
7cb06c |
+ regcache_supply_regset,
|
|
|
7cb06c |
+ regcache_collect_regset
|
|
|
7cb06c |
+};
|
|
|
7cb06c |
+
|
|
|
7cb06c |
const struct regset *
|
|
|
7cb06c |
ppc_linux_gregset (int wordsize)
|
|
|
7cb06c |
{
|
|
|
7cb06c |
@@ -621,6 +639,7 @@ ppc_linux_iterate_over_regset_sections (struct gdbarch *gdbarch,
|
|
|
7cb06c |
int have_vsx = tdep->ppc_vsr0_upper_regnum != -1;
|
|
|
7cb06c |
int have_ppr = tdep->ppc_ppr_regnum != -1;
|
|
|
7cb06c |
int have_dscr = tdep->ppc_dscr_regnum != -1;
|
|
|
7cb06c |
+ int have_tar = tdep->ppc_tar_regnum != -1;
|
|
|
7cb06c |
|
|
|
7cb06c |
if (tdep->wordsize == 4)
|
|
|
7cb06c |
cb (".reg", 48 * 4, 48 * 4, &ppc32_linux_gregset, NULL, cb_data);
|
|
|
7cb06c |
@@ -650,6 +669,11 @@ ppc_linux_iterate_over_regset_sections (struct gdbarch *gdbarch,
|
|
|
7cb06c |
PPC_LINUX_SIZEOF_DSCRREGSET,
|
|
|
7cb06c |
&ppc32_linux_dscrregset, "Data Stream Control Register",
|
|
|
7cb06c |
cb_data);
|
|
|
7cb06c |
+
|
|
|
7cb06c |
+ if (have_tar)
|
|
|
7cb06c |
+ cb (".reg-ppc-tar", PPC_LINUX_SIZEOF_TARREGSET,
|
|
|
7cb06c |
+ PPC_LINUX_SIZEOF_TARREGSET,
|
|
|
7cb06c |
+ &ppc32_linux_tarregset, "Target Address Register", cb_data);
|
|
|
7cb06c |
}
|
|
|
7cb06c |
|
|
|
7cb06c |
static void
|
|
|
7cb06c |
@@ -1064,6 +1088,7 @@ ppc_linux_core_read_description (struct gdbarch *gdbarch,
|
|
|
7cb06c |
asection *section = bfd_get_section_by_name (abfd, ".reg");
|
|
|
7cb06c |
asection *ppr = bfd_get_section_by_name (abfd, ".reg-ppc-ppr");
|
|
|
7cb06c |
asection *dscr = bfd_get_section_by_name (abfd, ".reg-ppc-dscr");
|
|
|
7cb06c |
+ asection *tar = bfd_get_section_by_name (abfd, ".reg-ppc-tar");
|
|
|
7cb06c |
|
|
|
7cb06c |
if (! section)
|
|
|
7cb06c |
return NULL;
|
|
|
7cb06c |
@@ -1097,7 +1122,11 @@ ppc_linux_core_read_description (struct gdbarch *gdbarch,
|
|
|
7cb06c |
features.isa205 = ppc_linux_has_isa205 (hwcap);
|
|
|
7cb06c |
|
|
|
7cb06c |
if (ppr && dscr)
|
|
|
7cb06c |
- features.ppr_dscr = true;
|
|
|
7cb06c |
+ {
|
|
|
7cb06c |
+ features.ppr_dscr = true;
|
|
|
7cb06c |
+ if (tar)
|
|
|
7cb06c |
+ features.isa207 = true;
|
|
|
7cb06c |
+ }
|
|
|
7cb06c |
|
|
|
7cb06c |
return ppc_linux_match_description (features);
|
|
|
7cb06c |
}
|
|
|
7cb06c |
@@ -1973,6 +2002,7 @@ _initialize_ppc_linux_tdep (void)
|
|
|
7cb06c |
initialize_tdesc_powerpc_isa205_altivec32l ();
|
|
|
7cb06c |
initialize_tdesc_powerpc_isa205_vsx32l ();
|
|
|
7cb06c |
initialize_tdesc_powerpc_isa205_ppr_dscr_vsx32l ();
|
|
|
7cb06c |
+ initialize_tdesc_powerpc_isa207_vsx32l ();
|
|
|
7cb06c |
initialize_tdesc_powerpc_64l ();
|
|
|
7cb06c |
initialize_tdesc_powerpc_altivec64l ();
|
|
|
7cb06c |
initialize_tdesc_powerpc_cell64l ();
|
|
|
7cb06c |
@@ -1981,5 +2011,6 @@ _initialize_ppc_linux_tdep (void)
|
|
|
7cb06c |
initialize_tdesc_powerpc_isa205_altivec64l ();
|
|
|
7cb06c |
initialize_tdesc_powerpc_isa205_vsx64l ();
|
|
|
7cb06c |
initialize_tdesc_powerpc_isa205_ppr_dscr_vsx64l ();
|
|
|
7cb06c |
+ initialize_tdesc_powerpc_isa207_vsx64l ();
|
|
|
7cb06c |
initialize_tdesc_powerpc_e500l ();
|
|
|
7cb06c |
}
|
|
|
7cb06c |
diff --git a/gdb/ppc-linux-tdep.h b/gdb/ppc-linux-tdep.h
|
|
|
7cb06c |
--- a/gdb/ppc-linux-tdep.h
|
|
|
7cb06c |
+++ b/gdb/ppc-linux-tdep.h
|
|
|
7cb06c |
@@ -47,5 +47,6 @@ int ppc_linux_trap_reg_p (struct gdbarch *gdbarch);
|
|
|
7cb06c |
/* Additional register sets, defined in ppc-linux-tdep.c. */
|
|
|
7cb06c |
extern const struct regset ppc32_linux_pprregset;
|
|
|
7cb06c |
extern const struct regset ppc32_linux_dscrregset;
|
|
|
7cb06c |
+extern const struct regset ppc32_linux_tarregset;
|
|
|
7cb06c |
|
|
|
7cb06c |
#endif /* PPC_LINUX_TDEP_H */
|
|
|
7cb06c |
diff --git a/gdb/ppc-tdep.h b/gdb/ppc-tdep.h
|
|
|
7cb06c |
--- a/gdb/ppc-tdep.h
|
|
|
7cb06c |
+++ b/gdb/ppc-tdep.h
|
|
|
7cb06c |
@@ -259,6 +259,9 @@ struct gdbarch_tdep
|
|
|
7cb06c |
/* Data Stream Control Register. */
|
|
|
7cb06c |
int ppc_dscr_regnum;
|
|
|
7cb06c |
|
|
|
7cb06c |
+ /* Target Address Register. */
|
|
|
7cb06c |
+ int ppc_tar_regnum;
|
|
|
7cb06c |
+
|
|
|
7cb06c |
/* Decimal 128 registers. */
|
|
|
7cb06c |
int ppc_dl0_regnum; /* First Decimal128 argument register pair. */
|
|
|
7cb06c |
|
|
|
7cb06c |
@@ -317,6 +320,7 @@ enum {
|
|
|
7cb06c |
PPC_VSR31_UPPER_REGNUM = 171,
|
|
|
7cb06c |
PPC_PPR_REGNUM = 172,
|
|
|
7cb06c |
PPC_DSCR_REGNUM = 173,
|
|
|
7cb06c |
+ PPC_TAR_REGNUM = 174,
|
|
|
7cb06c |
PPC_NUM_REGS
|
|
|
7cb06c |
};
|
|
|
7cb06c |
|
|
|
7cb06c |
diff --git a/gdb/regformats/rs6000/powerpc-isa207-vsx32l.dat b/gdb/regformats/rs6000/powerpc-isa207-vsx32l.dat
|
|
|
7cb06c |
new file mode 100644
|
|
|
7cb06c |
--- /dev/null
|
|
|
7cb06c |
+++ b/gdb/regformats/rs6000/powerpc-isa207-vsx32l.dat
|
|
|
7cb06c |
@@ -0,0 +1,147 @@
|
|
|
7cb06c |
+# THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi :set ro:
|
|
|
7cb06c |
+# Generated from: rs6000/powerpc-isa207-vsx32l.xml
|
|
|
7cb06c |
+name:powerpc_isa207_vsx32l
|
|
|
7cb06c |
+xmltarget:powerpc-isa207-vsx32l.xml
|
|
|
7cb06c |
+expedite:r1,pc
|
|
|
7cb06c |
+32:r0
|
|
|
7cb06c |
+32:r1
|
|
|
7cb06c |
+32:r2
|
|
|
7cb06c |
+32:r3
|
|
|
7cb06c |
+32:r4
|
|
|
7cb06c |
+32:r5
|
|
|
7cb06c |
+32:r6
|
|
|
7cb06c |
+32:r7
|
|
|
7cb06c |
+32:r8
|
|
|
7cb06c |
+32:r9
|
|
|
7cb06c |
+32:r10
|
|
|
7cb06c |
+32:r11
|
|
|
7cb06c |
+32:r12
|
|
|
7cb06c |
+32:r13
|
|
|
7cb06c |
+32:r14
|
|
|
7cb06c |
+32:r15
|
|
|
7cb06c |
+32:r16
|
|
|
7cb06c |
+32:r17
|
|
|
7cb06c |
+32:r18
|
|
|
7cb06c |
+32:r19
|
|
|
7cb06c |
+32:r20
|
|
|
7cb06c |
+32:r21
|
|
|
7cb06c |
+32:r22
|
|
|
7cb06c |
+32:r23
|
|
|
7cb06c |
+32:r24
|
|
|
7cb06c |
+32:r25
|
|
|
7cb06c |
+32:r26
|
|
|
7cb06c |
+32:r27
|
|
|
7cb06c |
+32:r28
|
|
|
7cb06c |
+32:r29
|
|
|
7cb06c |
+32:r30
|
|
|
7cb06c |
+32:r31
|
|
|
7cb06c |
+64:f0
|
|
|
7cb06c |
+64:f1
|
|
|
7cb06c |
+64:f2
|
|
|
7cb06c |
+64:f3
|
|
|
7cb06c |
+64:f4
|
|
|
7cb06c |
+64:f5
|
|
|
7cb06c |
+64:f6
|
|
|
7cb06c |
+64:f7
|
|
|
7cb06c |
+64:f8
|
|
|
7cb06c |
+64:f9
|
|
|
7cb06c |
+64:f10
|
|
|
7cb06c |
+64:f11
|
|
|
7cb06c |
+64:f12
|
|
|
7cb06c |
+64:f13
|
|
|
7cb06c |
+64:f14
|
|
|
7cb06c |
+64:f15
|
|
|
7cb06c |
+64:f16
|
|
|
7cb06c |
+64:f17
|
|
|
7cb06c |
+64:f18
|
|
|
7cb06c |
+64:f19
|
|
|
7cb06c |
+64:f20
|
|
|
7cb06c |
+64:f21
|
|
|
7cb06c |
+64:f22
|
|
|
7cb06c |
+64:f23
|
|
|
7cb06c |
+64:f24
|
|
|
7cb06c |
+64:f25
|
|
|
7cb06c |
+64:f26
|
|
|
7cb06c |
+64:f27
|
|
|
7cb06c |
+64:f28
|
|
|
7cb06c |
+64:f29
|
|
|
7cb06c |
+64:f30
|
|
|
7cb06c |
+64:f31
|
|
|
7cb06c |
+32:pc
|
|
|
7cb06c |
+32:msr
|
|
|
7cb06c |
+32:cr
|
|
|
7cb06c |
+32:lr
|
|
|
7cb06c |
+32:ctr
|
|
|
7cb06c |
+32:xer
|
|
|
7cb06c |
+64:fpscr
|
|
|
7cb06c |
+32:orig_r3
|
|
|
7cb06c |
+32:trap
|
|
|
7cb06c |
+128:vr0
|
|
|
7cb06c |
+128:vr1
|
|
|
7cb06c |
+128:vr2
|
|
|
7cb06c |
+128:vr3
|
|
|
7cb06c |
+128:vr4
|
|
|
7cb06c |
+128:vr5
|
|
|
7cb06c |
+128:vr6
|
|
|
7cb06c |
+128:vr7
|
|
|
7cb06c |
+128:vr8
|
|
|
7cb06c |
+128:vr9
|
|
|
7cb06c |
+128:vr10
|
|
|
7cb06c |
+128:vr11
|
|
|
7cb06c |
+128:vr12
|
|
|
7cb06c |
+128:vr13
|
|
|
7cb06c |
+128:vr14
|
|
|
7cb06c |
+128:vr15
|
|
|
7cb06c |
+128:vr16
|
|
|
7cb06c |
+128:vr17
|
|
|
7cb06c |
+128:vr18
|
|
|
7cb06c |
+128:vr19
|
|
|
7cb06c |
+128:vr20
|
|
|
7cb06c |
+128:vr21
|
|
|
7cb06c |
+128:vr22
|
|
|
7cb06c |
+128:vr23
|
|
|
7cb06c |
+128:vr24
|
|
|
7cb06c |
+128:vr25
|
|
|
7cb06c |
+128:vr26
|
|
|
7cb06c |
+128:vr27
|
|
|
7cb06c |
+128:vr28
|
|
|
7cb06c |
+128:vr29
|
|
|
7cb06c |
+128:vr30
|
|
|
7cb06c |
+128:vr31
|
|
|
7cb06c |
+32:vscr
|
|
|
7cb06c |
+32:vrsave
|
|
|
7cb06c |
+64:vs0h
|
|
|
7cb06c |
+64:vs1h
|
|
|
7cb06c |
+64:vs2h
|
|
|
7cb06c |
+64:vs3h
|
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7cb06c |
+64:vs4h
|
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7cb06c |
+64:vs5h
|
|
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7cb06c |
+64:vs6h
|
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7cb06c |
+64:vs7h
|
|
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7cb06c |
+64:vs8h
|
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|
7cb06c |
+64:vs9h
|
|
|
7cb06c |
+64:vs10h
|
|
|
7cb06c |
+64:vs11h
|
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7cb06c |
+64:vs12h
|
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7cb06c |
+64:vs13h
|
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7cb06c |
+64:vs14h
|
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7cb06c |
+64:vs15h
|
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7cb06c |
+64:vs16h
|
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7cb06c |
+64:vs17h
|
|
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7cb06c |
+64:vs18h
|
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7cb06c |
+64:vs19h
|
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7cb06c |
+64:vs20h
|
|
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7cb06c |
+64:vs21h
|
|
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7cb06c |
+64:vs22h
|
|
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7cb06c |
+64:vs23h
|
|
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7cb06c |
+64:vs24h
|
|
|
7cb06c |
+64:vs25h
|
|
|
7cb06c |
+64:vs26h
|
|
|
7cb06c |
+64:vs27h
|
|
|
7cb06c |
+64:vs28h
|
|
|
7cb06c |
+64:vs29h
|
|
|
7cb06c |
+64:vs30h
|
|
|
7cb06c |
+64:vs31h
|
|
|
7cb06c |
+64:ppr
|
|
|
7cb06c |
+64:dscr
|
|
|
7cb06c |
+64:tar
|
|
|
7cb06c |
diff --git a/gdb/regformats/rs6000/powerpc-isa207-vsx64l.dat b/gdb/regformats/rs6000/powerpc-isa207-vsx64l.dat
|
|
|
7cb06c |
new file mode 100644
|
|
|
7cb06c |
--- /dev/null
|
|
|
7cb06c |
+++ b/gdb/regformats/rs6000/powerpc-isa207-vsx64l.dat
|
|
|
7cb06c |
@@ -0,0 +1,147 @@
|
|
|
7cb06c |
+# THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi :set ro:
|
|
|
7cb06c |
+# Generated from: rs6000/powerpc-isa207-vsx64l.xml
|
|
|
7cb06c |
+name:powerpc_isa207_vsx64l
|
|
|
7cb06c |
+xmltarget:powerpc-isa207-vsx64l.xml
|
|
|
7cb06c |
+expedite:r1,pc
|
|
|
7cb06c |
+64:r0
|
|
|
7cb06c |
+64:r1
|
|
|
7cb06c |
+64:r2
|
|
|
7cb06c |
+64:r3
|
|
|
7cb06c |
+64:r4
|
|
|
7cb06c |
+64:r5
|
|
|
7cb06c |
+64:r6
|
|
|
7cb06c |
+64:r7
|
|
|
7cb06c |
+64:r8
|
|
|
7cb06c |
+64:r9
|
|
|
7cb06c |
+64:r10
|
|
|
7cb06c |
+64:r11
|
|
|
7cb06c |
+64:r12
|
|
|
7cb06c |
+64:r13
|
|
|
7cb06c |
+64:r14
|
|
|
7cb06c |
+64:r15
|
|
|
7cb06c |
+64:r16
|
|
|
7cb06c |
+64:r17
|
|
|
7cb06c |
+64:r18
|
|
|
7cb06c |
+64:r19
|
|
|
7cb06c |
+64:r20
|
|
|
7cb06c |
+64:r21
|
|
|
7cb06c |
+64:r22
|
|
|
7cb06c |
+64:r23
|
|
|
7cb06c |
+64:r24
|
|
|
7cb06c |
+64:r25
|
|
|
7cb06c |
+64:r26
|
|
|
7cb06c |
+64:r27
|
|
|
7cb06c |
+64:r28
|
|
|
7cb06c |
+64:r29
|
|
|
7cb06c |
+64:r30
|
|
|
7cb06c |
+64:r31
|
|
|
7cb06c |
+64:f0
|
|
|
7cb06c |
+64:f1
|
|
|
7cb06c |
+64:f2
|
|
|
7cb06c |
+64:f3
|
|
|
7cb06c |
+64:f4
|
|
|
7cb06c |
+64:f5
|
|
|
7cb06c |
+64:f6
|
|
|
7cb06c |
+64:f7
|
|
|
7cb06c |
+64:f8
|
|
|
7cb06c |
+64:f9
|
|
|
7cb06c |
+64:f10
|
|
|
7cb06c |
+64:f11
|
|
|
7cb06c |
+64:f12
|
|
|
7cb06c |
+64:f13
|
|
|
7cb06c |
+64:f14
|
|
|
7cb06c |
+64:f15
|
|
|
7cb06c |
+64:f16
|
|
|
7cb06c |
+64:f17
|
|
|
7cb06c |
+64:f18
|
|
|
7cb06c |
+64:f19
|
|
|
7cb06c |
+64:f20
|
|
|
7cb06c |
+64:f21
|
|
|
7cb06c |
+64:f22
|
|
|
7cb06c |
+64:f23
|
|
|
7cb06c |
+64:f24
|
|
|
7cb06c |
+64:f25
|
|
|
7cb06c |
+64:f26
|
|
|
7cb06c |
+64:f27
|
|
|
7cb06c |
+64:f28
|
|
|
7cb06c |
+64:f29
|
|
|
7cb06c |
+64:f30
|
|
|
7cb06c |
+64:f31
|
|
|
7cb06c |
+64:pc
|
|
|
7cb06c |
+64:msr
|
|
|
7cb06c |
+32:cr
|
|
|
7cb06c |
+64:lr
|
|
|
7cb06c |
+64:ctr
|
|
|
7cb06c |
+32:xer
|
|
|
7cb06c |
+64:fpscr
|
|
|
7cb06c |
+64:orig_r3
|
|
|
7cb06c |
+64:trap
|
|
|
7cb06c |
+128:vr0
|
|
|
7cb06c |
+128:vr1
|
|
|
7cb06c |
+128:vr2
|
|
|
7cb06c |
+128:vr3
|
|
|
7cb06c |
+128:vr4
|
|
|
7cb06c |
+128:vr5
|
|
|
7cb06c |
+128:vr6
|
|
|
7cb06c |
+128:vr7
|
|
|
7cb06c |
+128:vr8
|
|
|
7cb06c |
+128:vr9
|
|
|
7cb06c |
+128:vr10
|
|
|
7cb06c |
+128:vr11
|
|
|
7cb06c |
+128:vr12
|
|
|
7cb06c |
+128:vr13
|
|
|
7cb06c |
+128:vr14
|
|
|
7cb06c |
+128:vr15
|
|
|
7cb06c |
+128:vr16
|
|
|
7cb06c |
+128:vr17
|
|
|
7cb06c |
+128:vr18
|
|
|
7cb06c |
+128:vr19
|
|
|
7cb06c |
+128:vr20
|
|
|
7cb06c |
+128:vr21
|
|
|
7cb06c |
+128:vr22
|
|
|
7cb06c |
+128:vr23
|
|
|
7cb06c |
+128:vr24
|
|
|
7cb06c |
+128:vr25
|
|
|
7cb06c |
+128:vr26
|
|
|
7cb06c |
+128:vr27
|
|
|
7cb06c |
+128:vr28
|
|
|
7cb06c |
+128:vr29
|
|
|
7cb06c |
+128:vr30
|
|
|
7cb06c |
+128:vr31
|
|
|
7cb06c |
+32:vscr
|
|
|
7cb06c |
+32:vrsave
|
|
|
7cb06c |
+64:vs0h
|
|
|
7cb06c |
+64:vs1h
|
|
|
7cb06c |
+64:vs2h
|
|
|
7cb06c |
+64:vs3h
|
|
|
7cb06c |
+64:vs4h
|
|
|
7cb06c |
+64:vs5h
|
|
|
7cb06c |
+64:vs6h
|
|
|
7cb06c |
+64:vs7h
|
|
|
7cb06c |
+64:vs8h
|
|
|
7cb06c |
+64:vs9h
|
|
|
7cb06c |
+64:vs10h
|
|
|
7cb06c |
+64:vs11h
|
|
|
7cb06c |
+64:vs12h
|
|
|
7cb06c |
+64:vs13h
|
|
|
7cb06c |
+64:vs14h
|
|
|
7cb06c |
+64:vs15h
|
|
|
7cb06c |
+64:vs16h
|
|
|
7cb06c |
+64:vs17h
|
|
|
7cb06c |
+64:vs18h
|
|
|
7cb06c |
+64:vs19h
|
|
|
7cb06c |
+64:vs20h
|
|
|
7cb06c |
+64:vs21h
|
|
|
7cb06c |
+64:vs22h
|
|
|
7cb06c |
+64:vs23h
|
|
|
7cb06c |
+64:vs24h
|
|
|
7cb06c |
+64:vs25h
|
|
|
7cb06c |
+64:vs26h
|
|
|
7cb06c |
+64:vs27h
|
|
|
7cb06c |
+64:vs28h
|
|
|
7cb06c |
+64:vs29h
|
|
|
7cb06c |
+64:vs30h
|
|
|
7cb06c |
+64:vs31h
|
|
|
7cb06c |
+64:ppr
|
|
|
7cb06c |
+64:dscr
|
|
|
7cb06c |
+64:tar
|
|
|
7cb06c |
diff --git a/gdb/rs6000-tdep.c b/gdb/rs6000-tdep.c
|
|
|
7cb06c |
--- a/gdb/rs6000-tdep.c
|
|
|
7cb06c |
+++ b/gdb/rs6000-tdep.c
|
|
|
7cb06c |
@@ -4699,6 +4699,10 @@ ppc_process_record_op31 (struct gdbarch *gdbarch, struct regcache *regcache,
|
|
|
7cb06c |
case 256: /* VRSAVE */
|
|
|
7cb06c |
record_full_arch_list_add_reg (regcache, tdep->ppc_vrsave_regnum);
|
|
|
7cb06c |
return 0;
|
|
|
7cb06c |
+ case 815: /* TAR */
|
|
|
7cb06c |
+ if (tdep->ppc_tar_regnum >= 0)
|
|
|
7cb06c |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_tar_regnum);
|
|
|
7cb06c |
+ return 0;
|
|
|
7cb06c |
case 896:
|
|
|
7cb06c |
case 898: /* PPR */
|
|
|
7cb06c |
if (tdep->ppc_ppr_regnum >= 0)
|
|
|
7cb06c |
@@ -5867,6 +5871,7 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
|
|
|
7cb06c |
enum powerpc_elf_abi elf_abi = POWERPC_ELF_AUTO;
|
|
|
7cb06c |
int have_fpu = 0, have_spe = 0, have_mq = 0, have_altivec = 0;
|
|
|
7cb06c |
int have_dfp = 0, have_vsx = 0, have_ppr = 0, have_dscr = 0;
|
|
|
7cb06c |
+ int have_tar = 0;
|
|
|
7cb06c |
int tdesc_wordsize = -1;
|
|
|
7cb06c |
const struct target_desc *tdesc = info.target_desc;
|
|
|
7cb06c |
struct tdesc_arch_data *tdesc_data = NULL;
|
|
|
7cb06c |
@@ -6187,6 +6192,25 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
|
|
|
7cb06c |
}
|
|
|
7cb06c |
else
|
|
|
7cb06c |
have_dscr = 0;
|
|
|
7cb06c |
+
|
|
|
7cb06c |
+ /* Target Address Register. */
|
|
|
7cb06c |
+ feature = tdesc_find_feature (tdesc,
|
|
|
7cb06c |
+ "org.gnu.gdb.power.tar");
|
|
|
7cb06c |
+ if (feature != NULL)
|
|
|
7cb06c |
+ {
|
|
|
7cb06c |
+ valid_p = 1;
|
|
|
7cb06c |
+ valid_p &= tdesc_numbered_register (feature, tdesc_data,
|
|
|
7cb06c |
+ PPC_TAR_REGNUM, "tar");
|
|
|
7cb06c |
+
|
|
|
7cb06c |
+ if (!valid_p)
|
|
|
7cb06c |
+ {
|
|
|
7cb06c |
+ tdesc_data_cleanup (tdesc_data);
|
|
|
7cb06c |
+ return NULL;
|
|
|
7cb06c |
+ }
|
|
|
7cb06c |
+ have_tar = 1;
|
|
|
7cb06c |
+ }
|
|
|
7cb06c |
+ else
|
|
|
7cb06c |
+ have_tar = 0;
|
|
|
7cb06c |
}
|
|
|
7cb06c |
|
|
|
7cb06c |
/* If we have a 64-bit binary on a 32-bit target, complain. Also
|
|
|
7cb06c |
@@ -6383,6 +6407,7 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
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tdep->ppc_spefscr_regnum = have_spe ? PPC_SPE_FSCR_REGNUM : -1;
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tdep->ppc_ppr_regnum = have_ppr ? PPC_PPR_REGNUM : -1;
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tdep->ppc_dscr_regnum = have_dscr ? PPC_DSCR_REGNUM : -1;
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+ tdep->ppc_tar_regnum = have_tar ? PPC_TAR_REGNUM : -1;
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set_gdbarch_pc_regnum (gdbarch, PPC_PC_REGNUM);
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set_gdbarch_sp_regnum (gdbarch, PPC_R0_REGNUM + 1);
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diff --git a/gdb/testsuite/gdb.arch/powerpc-tar.c b/gdb/testsuite/gdb.arch/powerpc-tar.c
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new file mode 100644
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--- /dev/null
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+++ b/gdb/testsuite/gdb.arch/powerpc-tar.c
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@@ -0,0 +1,33 @@
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+/* This testcase is part of GDB, the GNU debugger.
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+
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+ Copyright (C) 2018 Free Software Foundation, Inc.
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+
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+ This program is free software; you can redistribute it and/or modify
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+ it under the terms of the GNU General Public License as published by
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+ the Free Software Foundation; either version 3 of the License, or
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+ (at your option) any later version.
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+
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+ This program is distributed in the hope that it will be useful,
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+ but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ GNU General Public License for more details.
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+
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+ You should have received a copy of the GNU General Public License
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+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
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+
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+int main (void)
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+{
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+ void * target1 = &&target1_l;
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+ void * target2 = &&target2_l;
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+ asm volatile ("mtspr 815,%0" : : "r" (target1) : );
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+
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+ /* Branch always to TAR. */
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+ asm volatile ("bctar 20,0,0"); // marker
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+
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+ target2_l:
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+ asm volatile ("nop"); // marker 2
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+ target1_l:
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+ asm volatile ("nop");
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+
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+ return 0;
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+}
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diff --git a/gdb/testsuite/gdb.arch/powerpc-tar.exp b/gdb/testsuite/gdb.arch/powerpc-tar.exp
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new file mode 100644
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--- /dev/null
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+++ b/gdb/testsuite/gdb.arch/powerpc-tar.exp
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@@ -0,0 +1,122 @@
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+# Copyright (C) 2018 Free Software Foundation, Inc.
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+
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+# This program is free software; you can redistribute it and/or modify
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+# it under the terms of the GNU General Public License as published by
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+# the Free Software Foundation; either version 3 of the License, or
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+# (at your option) any later version.
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+#
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+# This program is distributed in the hope that it will be useful,
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+# but WITHOUT ANY WARRANTY; without even the implied warranty of
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+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+# GNU General Public License for more details.
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+#
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+# You should have received a copy of the GNU General Public License
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+# along with this program. If not, see <http://www.gnu.org/licenses/>.
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+
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+# This file is part of the gdb testsuite.
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+
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+# Test access to special purpose register TAR (the Target Address
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+# Register). The test inferior writes to this register, we check that
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+# GDB reads the same value, then write to the register the address of
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+# another label. We then let the inferior continue and execute a
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+# branch to TAR and check that we stop at the address that we wrote to
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+# register.
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+
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+if {![istarget "powerpc*-*-linux*"]} then {
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+ verbose "Skipping PowerPC test for the TAR register."
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+ return
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+}
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+
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+standard_testfile .c
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+
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+if {[build_executable "compile" $binfile $srcfile {debug}] == -1} {
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+ return -1
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+}
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+
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+proc check_register_access { regname } {
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+ global gdb_prompt
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+
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+ set test "$regname register access"
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+ gdb_test_multiple "info reg $regname" "$test" {
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+ -re "Invalid register.*\r\n$gdb_prompt $" {
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+ unsupported "$test"
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+ return 0
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+ }
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+ -re "\r\n$regname.*\r\n$gdb_prompt $" {
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+ pass "$test"
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+ return 1
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+ }
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+ }
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+ return 0
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+}
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+
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+proc tar_available {} {
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+ global gdb_prompt
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+ global inferior_exited_re
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+
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+ set test "TAR available to inferior"
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+ gdb_test_multiple "continue" "" {
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+ -re "Illegal instruction.*\r\n$gdb_prompt $" {
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+ unsupported "$test"
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+ return 0
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+ }
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+ -re "$inferior_exited_re normally.*$gdb_prompt $" {
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+ pass "$test"
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+ return 1
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+ }
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+ }
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+ return 0
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+}
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+
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+# Do one pass to check if TAR is usable, system
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+# software can prevent it from being used.
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+with_test_prefix "check TAR access" {
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+ clean_restart $binfile
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+
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+ if ![runto_main] {
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+ return
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+ }
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+
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+ if {![check_register_access "tar"]} {
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+ return
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+ }
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+
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+ if {![tar_available]} {
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+ return
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+ }
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+}
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+
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+# Now do the actual test
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+clean_restart $binfile
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+
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+if ![runto_main] {
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+ return
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+}
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+
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+gdb_breakpoint [gdb_get_line_number "marker"]
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+
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+gdb_continue_to_breakpoint "continue to marker"
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+
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+set target1 [get_hexadecimal_valueof "target1" -1]
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+set tar [get_hexadecimal_valueof "\$tar" -2]
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+
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+set test "TAR value from mtspr"
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+
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+if {${target1} == ${tar}} {
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+ pass $test
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+} else {
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+ fail $test
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+}
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+
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+set target2 [get_hexadecimal_valueof "target2" -1]
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+
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+if {$target2 == -1} {
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+ fail "Could not get value of target2"
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+ return
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+}
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+
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+gdb_test_no_output "set \$tar = $target2" "set tar"
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+
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+gdb_breakpoint [gdb_get_line_number "marker 2"]
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+
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+gdb_continue_to_breakpoint "continue to new target address" ".*marker 2.*"
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