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From FEDORA_PATCHES Mon Sep 17 00:00:00 2001
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From: Keith Seitz <keiths@redhat.com>
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Date: Fri, 11 Jan 2019 17:02:16 -0500
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Subject: gdb-rhbz1187581-power8-regs-not-in-8.2-10of15.patch
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;; [PowerPC] Add support for PPR and DSCR
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;; Edjunior Barbosa Machado and Pedro Franco de Carvalho, RH BZ 1187581
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[PowerPC] Add support for PPR and DSCR
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This patch adds gdb support for the Program Priorty Register and the
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Data Stream Control Register, for the powerpc linux native and core
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file targets, and for the powerpc linux server stub.
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gdb/ChangeLog:
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2018-10-26 Edjunior Barbosa Machado <emachado@linux.vnet.ibm.com>
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Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
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* arch/ppc-linux-tdesc.h (tdesc_powerpc_isa205_ppr_dscr_vsx32l)
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(tdesc_powerpc_isa205_ppr_dscr_vsx64l): Declare.
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* arch/ppc-linux-common.h (PPC_LINUX_SIZEOF_PPRREGSET)
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(PPC_LINUX_SIZEOF_DSCRREGSET): Define.
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(struct ppc_linux_features) <ppr_dscr>: New field.
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(ppc_linux_no_features): Add initializer for ppr_dscr field.
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* arch/ppc-linux-common.c (ppc_linux_match_description): Return
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new tdescs.
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* nat/ppc-linux.h (PPC_FEATURE2_DSCR, NT_PPC_PPR, NT_PPC_DSCR):
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Define if not already defined.
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* features/Makefile (WHICH): Add
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rs6000/powerpc-isa205-ppr-dscr-vsx32l and
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rs6000/powerpc-isa205-ppr-dscr-vsx64l.
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(XMLTOC): Add rs6000/powerpc-isa205-ppr-dscr-vsx32l.xml and
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rs6000/powerpc-isa205-ppr-dscr-vsx64l.xml.
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* features/rs6000/power-dscr.xml: New file.
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* features/rs6000/power-ppr.xml: New file.
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* features/rs6000/powerpc-isa205-ppr-dscr-vsx32l.xml: New file.
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* features/rs6000/powerpc-isa205-ppr-dscr-vsx64l.xml: New file.
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* features/rs6000/powerpc-isa205-ppr-dscr-vsx32l.c: Generate.
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* features/rs6000/powerpc-isa205-ppr-dscr-vsx64l.c: Generate.
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* regformats/rs6000/powerpc-isa205-ppr-dscr-vsx32l.dat: Generate.
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* regformats/rs6000/powerpc-isa205-ppr-dscr-vsx64l.dat: Generate.
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* ppc-linux-nat.c: Include <sys/uio.h>.
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(fetch_regset, store_regset, check_regset): New functions.
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(fetch_register, fetch_ppc_registers): Call fetch_regset with
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DSCR and PPR regsets.
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(store_register, store_ppc_registers): Call store_regset with
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DSCR and PPR regsets.
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(ppc_linux_get_hwcap2): New function.
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(ppc_linux_nat_target::read_description): Call
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ppc_linux_get_hwcap2 and check_regset, set ppr_dscr field in the
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features struct if needed.
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* ppc-linux-tdep.c: Include
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features/rs6000/powerpc-isa205-ppr-dscr-vsx32l.c and
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features/rs6000/powerpc-isa205-ppr-dscr-vsx64l.c.
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(ppc32_regmap_ppr, ppc32_regmap_dscr, ppc32_linux_pprregset)
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(ppc32_linux_dscrregset): New globals.
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(ppc_linux_iterate_over_regset_sections): Call back with the ppr
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and dscr regsets.
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(ppc_linux_core_read_description): Check if the ppr and dscr
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sections are present and set ppr_dscr in the features struct.
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(_initialize_ppc_linux_tdep): Call
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initialize_tdesc_powerpc_isa205_ppr_dscr_vsx32l and
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initialize_tdesc_powerpc_isa205_ppr_dscr_vsx64l.
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* ppc-linux-tdep.h (ppc32_linux_pprregset)
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(ppc32_linux_dscrregset): Declare.
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* ppc-tdep.h (struct gdbarch_tdep) <ppc_ppr_regnum>: New field.
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<ppc_dscr_regnum>: New field.
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(enum) <PPC_PPR_REGNUM, PPC_DSCR_REGNUM>: New enum values.
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* rs6000-tdep.c (rs6000_gdbarch_init): Look for and validate ppr
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and dscr features.
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(ppc_process_record_op31): Record changes to PPR and DSCR.
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gdb/gdbserver/ChangeLog:
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2018-10-26 Edjunior Barbosa Machado <emachado@linux.vnet.ibm.com>
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Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
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* configure.srv (ipa_ppc_linux_regobj): Add
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powerpc-isa205-ppr-dscr-vsx32l-ipa.o and
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powerpc-isa205-ppr-dscr-vsx64l-ipa.o.
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(powerpc*-*-linux*): Add powerpc-isa205-ppr-dscr-vsx32l.o and
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powerpc-isa205-ppr-dscr-vsx64l.o to srv_regobj, add
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rs6000/power-dscr.xml, rs6000/power-ppr.xml,
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rs6000/powerpc-isa205-ppr-dscr-vsx32l.xml and
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rs6000/powerpc-isa205-ppr-dscr-vsx64l.xml to srv_xmlfiles.
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* linux-ppc-tdesc-init.h (enum ppc_linux_tdesc)
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<PPC_TDESC_ISA205_PPR_DSCR_VSX>: New enum value.
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(init_registers_powerpc_isa205_ppr_dscr_vsx32l)
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(init_registers_powerpc_isa205_ppr_dscr_vsx64l): Declare.
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* linux-ppc-low.c: Include "elf/common.h" and <sys/uio.h>.
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(ppc_hwcap): Add comment.
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(ppc_hwcap2): New global.
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(ppc_check_regset, ppc_fill_pprregset, ppc_store_pprregset)
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(ppc_fill_dscrregset, ppc_store_dscrregset): New functions.
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(ppc_regsets): Add entries for the DSCR and PPR regsets.
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(ppc_arch_setup): Get AT_HWCAP2. Set ppr_dscr in features struct
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when needed. Set sizes for the the DSCR and PPR regsets.
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(ppc_get_ipa_tdesc_idx): Return PPC_TDESC_ISA205_PPR_DSCR_VSX.
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(initialize_low_arch): Call
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init_registers_powerpc_isa205_ppr_dscr_vsx32l and
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init_registers_powerpc_isa205_ppr_dscr_vsx64l.
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* linux-ppc-ipa.c (get_ipa_tdesc): Handle
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PPC_TDESC_ISA205_PPR_DSCR_VSX.
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(initialize_low_tracepoint): Call
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init_registers_powerpc_isa205_ppr_dscr_vsx32l and
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init_registers_powerpc_isa205_ppr_dscr_vsx64l.
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gdb/testsuite/ChangeLog:
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2018-10-26 Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
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* gdb.arch/powerpc-ppr-dscr.c: New file.
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* gdb.arch/powerpc-ppr-dscr.exp: New file.
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gdb/doc/ChangeLog:
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2018-10-26 Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
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* gdb.texinfo (PowerPC Features): Describe new features
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"org.gnu.gdb.power.ppr" and "org.gnu.gdb.power.dscr".
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diff --git a/gdb/arch/ppc-linux-common.c b/gdb/arch/ppc-linux-common.c
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--- a/gdb/arch/ppc-linux-common.c
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+++ b/gdb/arch/ppc-linux-common.c
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@@ -53,7 +53,8 @@ ppc_linux_match_description (struct ppc_linux_features features)
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if (features.cell)
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tdesc = tdesc_powerpc_cell64l;
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else if (features.vsx)
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- tdesc = (features.isa205? tdesc_powerpc_isa205_vsx64l
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+ tdesc = (features.ppr_dscr? tdesc_powerpc_isa205_ppr_dscr_vsx64l
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+ : features.isa205? tdesc_powerpc_isa205_vsx64l
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: tdesc_powerpc_vsx64l);
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else if (features.altivec)
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tdesc = (features.isa205? tdesc_powerpc_isa205_altivec64l
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@@ -69,7 +70,8 @@ ppc_linux_match_description (struct ppc_linux_features features)
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if (features.cell)
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tdesc = tdesc_powerpc_cell32l;
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else if (features.vsx)
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- tdesc = (features.isa205? tdesc_powerpc_isa205_vsx32l
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+ tdesc = (features.ppr_dscr? tdesc_powerpc_isa205_ppr_dscr_vsx32l
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+ : features.isa205? tdesc_powerpc_isa205_vsx32l
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: tdesc_powerpc_vsx32l);
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else if (features.altivec)
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tdesc = (features.isa205? tdesc_powerpc_isa205_altivec32l
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diff --git a/gdb/arch/ppc-linux-common.h b/gdb/arch/ppc-linux-common.h
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--- a/gdb/arch/ppc-linux-common.h
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+++ b/gdb/arch/ppc-linux-common.h
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@@ -30,6 +30,8 @@ struct target_desc;
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#define PPC_LINUX_SIZEOF_VRREGSET 544
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#define PPC_LINUX_SIZEOF_VSXREGSET 256
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+#define PPC_LINUX_SIZEOF_PPRREGSET 8
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+#define PPC_LINUX_SIZEOF_DSCRREGSET 8
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/* Check if the hwcap auxv entry indicates that isa205 is supported. */
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bool ppc_linux_has_isa205 (CORE_ADDR hwcap);
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@@ -41,6 +43,7 @@ struct ppc_linux_features
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bool altivec;
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bool vsx;
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bool isa205;
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+ bool ppr_dscr;
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bool cell;
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};
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@@ -51,6 +54,7 @@ const struct ppc_linux_features ppc_linux_no_features = {
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false,
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false,
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false,
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+ false,
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};
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/* Return a target description that matches FEATURES. */
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diff --git a/gdb/arch/ppc-linux-tdesc.h b/gdb/arch/ppc-linux-tdesc.h
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--- a/gdb/arch/ppc-linux-tdesc.h
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+++ b/gdb/arch/ppc-linux-tdesc.h
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@@ -29,6 +29,7 @@ extern struct target_desc *tdesc_powerpc_vsx32l;
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extern struct target_desc *tdesc_powerpc_isa205_32l;
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extern struct target_desc *tdesc_powerpc_isa205_altivec32l;
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extern struct target_desc *tdesc_powerpc_isa205_vsx32l;
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+extern struct target_desc *tdesc_powerpc_isa205_ppr_dscr_vsx32l;
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extern struct target_desc *tdesc_powerpc_e500l;
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extern struct target_desc *tdesc_powerpc_64l;
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@@ -38,5 +39,6 @@ extern struct target_desc *tdesc_powerpc_vsx64l;
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extern struct target_desc *tdesc_powerpc_isa205_64l;
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extern struct target_desc *tdesc_powerpc_isa205_altivec64l;
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extern struct target_desc *tdesc_powerpc_isa205_vsx64l;
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+extern struct target_desc *tdesc_powerpc_isa205_ppr_dscr_vsx64l;
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#endif /* ARCH_PPC_LINUX_TDESC_H */
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diff --git a/gdb/doc/gdb.texinfo b/gdb/doc/gdb.texinfo
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--- a/gdb/doc/gdb.texinfo
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+++ b/gdb/doc/gdb.texinfo
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@@ -42555,6 +42555,12 @@ contain registers @samp{ev0h} through @samp{ev31h}, @samp{acc}, and
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these to present registers @samp{ev0} through @samp{ev31} to the
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user.
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+The @samp{org.gnu.gdb.power.ppr} feature is optional. It should
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+contain the 64-bit register @samp{ppr}.
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+
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+The @samp{org.gnu.gdb.power.dscr} feature is optional. It should
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+contain the 64-bit register @samp{dscr}.
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+
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@node S/390 and System z Features
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@subsection S/390 and System z Features
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@cindex target descriptions, S/390 features
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diff --git a/gdb/features/Makefile b/gdb/features/Makefile
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--- a/gdb/features/Makefile
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+++ b/gdb/features/Makefile
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190f2a |
@@ -73,6 +73,8 @@ WHICH = aarch64 \
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rs6000/powerpc-isa205-32l rs6000/powerpc-isa205-64l \
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rs6000/powerpc-isa205-altivec32l rs6000/powerpc-isa205-altivec64l \
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rs6000/powerpc-isa205-vsx32l rs6000/powerpc-isa205-vsx64l \
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+ rs6000/powerpc-isa205-ppr-dscr-vsx32l \
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+ rs6000/powerpc-isa205-ppr-dscr-vsx64l \
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s390-linux32 s390-linux64 s390x-linux64 \
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s390-linux32v1 s390-linux64v1 s390x-linux64v1 \
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s390-linux32v2 s390-linux64v2 s390x-linux64v2 \
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190f2a |
@@ -167,6 +169,8 @@ XMLTOC = \
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rs6000/powerpc-isa205-altivec64l.xml \
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rs6000/powerpc-isa205-vsx32l.xml \
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rs6000/powerpc-isa205-vsx64l.xml \
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+ rs6000/powerpc-isa205-ppr-dscr-vsx32l.xml \
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+ rs6000/powerpc-isa205-ppr-dscr-vsx64l.xml \
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rs6000/powerpc-vsx32.xml \
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rs6000/powerpc-vsx32l.xml \
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rs6000/powerpc-vsx64.xml \
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diff --git a/gdb/features/rs6000/power-dscr.xml b/gdb/features/rs6000/power-dscr.xml
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new file mode 100644
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--- /dev/null
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+++ b/gdb/features/rs6000/power-dscr.xml
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@@ -0,0 +1,12 @@
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+
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+
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+
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+ Copying and distribution of this file, with or without modification,
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+ are permitted in any medium without royalty provided the copyright
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+ notice and this notice are preserved. -->
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+
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+
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+
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+<feature name="org.gnu.gdb.power.dscr">
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+ <reg name="dscr" bitsize="64" type="uint64"/>
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+</feature>
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190f2a |
diff --git a/gdb/features/rs6000/power-ppr.xml b/gdb/features/rs6000/power-ppr.xml
|
|
|
190f2a |
new file mode 100644
|
|
|
190f2a |
--- /dev/null
|
|
|
190f2a |
+++ b/gdb/features/rs6000/power-ppr.xml
|
|
|
190f2a |
@@ -0,0 +1,12 @@
|
|
|
190f2a |
+
|
|
|
190f2a |
+
|
|
|
190f2a |
+
|
|
|
190f2a |
+ Copying and distribution of this file, with or without modification,
|
|
|
190f2a |
+ are permitted in any medium without royalty provided the copyright
|
|
|
190f2a |
+ notice and this notice are preserved. -->
|
|
|
190f2a |
+
|
|
|
190f2a |
+
|
|
|
190f2a |
+
|
|
|
190f2a |
+<feature name="org.gnu.gdb.power.ppr">
|
|
|
190f2a |
+ <reg name="ppr" bitsize="64" type="uint64"/>
|
|
|
190f2a |
+</feature>
|
|
|
190f2a |
diff --git a/gdb/features/rs6000/powerpc-isa205-ppr-dscr-vsx32l.c b/gdb/features/rs6000/powerpc-isa205-ppr-dscr-vsx32l.c
|
|
|
190f2a |
new file mode 100644
|
|
|
190f2a |
--- /dev/null
|
|
|
190f2a |
+++ b/gdb/features/rs6000/powerpc-isa205-ppr-dscr-vsx32l.c
|
|
|
190f2a |
@@ -0,0 +1,200 @@
|
|
|
190f2a |
+/* THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi:set ro:
|
|
|
190f2a |
+ Original: powerpc-isa205-ppr-dscr-vsx32l.xml */
|
|
|
190f2a |
+
|
|
|
190f2a |
+#include "defs.h"
|
|
|
190f2a |
+#include "osabi.h"
|
|
|
190f2a |
+#include "target-descriptions.h"
|
|
|
190f2a |
+
|
|
|
190f2a |
+struct target_desc *tdesc_powerpc_isa205_ppr_dscr_vsx32l;
|
|
|
190f2a |
+static void
|
|
|
190f2a |
+initialize_tdesc_powerpc_isa205_ppr_dscr_vsx32l (void)
|
|
|
190f2a |
+{
|
|
|
190f2a |
+ struct target_desc *result = allocate_target_description ();
|
|
|
190f2a |
+ set_tdesc_architecture (result, bfd_scan_arch ("powerpc:common"));
|
|
|
190f2a |
+
|
|
|
190f2a |
+ struct tdesc_feature *feature;
|
|
|
190f2a |
+
|
|
|
190f2a |
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.core");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r0", 0, 1, NULL, 32, "uint32");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "uint32");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r2", 2, 1, NULL, 32, "uint32");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r3", 3, 1, NULL, 32, "uint32");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r4", 4, 1, NULL, 32, "uint32");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r5", 5, 1, NULL, 32, "uint32");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r6", 6, 1, NULL, 32, "uint32");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r7", 7, 1, NULL, 32, "uint32");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r8", 8, 1, NULL, 32, "uint32");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r9", 9, 1, NULL, 32, "uint32");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r10", 10, 1, NULL, 32, "uint32");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r11", 11, 1, NULL, 32, "uint32");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r12", 12, 1, NULL, 32, "uint32");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r13", 13, 1, NULL, 32, "uint32");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r14", 14, 1, NULL, 32, "uint32");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r15", 15, 1, NULL, 32, "uint32");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r16", 16, 1, NULL, 32, "uint32");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r17", 17, 1, NULL, 32, "uint32");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r18", 18, 1, NULL, 32, "uint32");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r19", 19, 1, NULL, 32, "uint32");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r20", 20, 1, NULL, 32, "uint32");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r21", 21, 1, NULL, 32, "uint32");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r22", 22, 1, NULL, 32, "uint32");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r23", 23, 1, NULL, 32, "uint32");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r24", 24, 1, NULL, 32, "uint32");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r25", 25, 1, NULL, 32, "uint32");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r26", 26, 1, NULL, 32, "uint32");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r27", 27, 1, NULL, 32, "uint32");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r28", 28, 1, NULL, 32, "uint32");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r29", 29, 1, NULL, 32, "uint32");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r30", 30, 1, NULL, 32, "uint32");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r31", 31, 1, NULL, 32, "uint32");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "pc", 64, 1, NULL, 32, "code_ptr");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "msr", 65, 1, NULL, 32, "uint32");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "cr", 66, 1, NULL, 32, "uint32");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "lr", 67, 1, NULL, 32, "code_ptr");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "ctr", 68, 1, NULL, 32, "uint32");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "xer", 69, 1, NULL, 32, "uint32");
|
|
|
190f2a |
+
|
|
|
190f2a |
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.fpu");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f0", 32, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f1", 33, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f2", 34, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f3", 35, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f4", 36, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f5", 37, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f6", 38, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f7", 39, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f8", 40, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f9", 41, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f10", 42, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f11", 43, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f12", 44, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f13", 45, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f14", 46, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f15", 47, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f16", 48, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f17", 49, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f18", 50, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f19", 51, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f20", 52, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f21", 53, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f22", 54, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f23", 55, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f24", 56, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f25", 57, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f26", 58, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f27", 59, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f28", 60, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f29", 61, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f30", 62, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f31", 63, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "fpscr", 70, 1, "float", 64, "int");
|
|
|
190f2a |
+
|
|
|
190f2a |
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.linux");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "orig_r3", 71, 1, NULL, 32, "int");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "trap", 72, 1, NULL, 32, "int");
|
|
|
190f2a |
+
|
|
|
190f2a |
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.altivec");
|
|
|
190f2a |
+ tdesc_type *element_type;
|
|
|
190f2a |
+ element_type = tdesc_named_type (feature, "ieee_single");
|
|
|
190f2a |
+ tdesc_create_vector (feature, "v4f", element_type, 4);
|
|
|
190f2a |
+
|
|
|
190f2a |
+ element_type = tdesc_named_type (feature, "int32");
|
|
|
190f2a |
+ tdesc_create_vector (feature, "v4i32", element_type, 4);
|
|
|
190f2a |
+
|
|
|
190f2a |
+ element_type = tdesc_named_type (feature, "int16");
|
|
|
190f2a |
+ tdesc_create_vector (feature, "v8i16", element_type, 8);
|
|
|
190f2a |
+
|
|
|
190f2a |
+ element_type = tdesc_named_type (feature, "int8");
|
|
|
190f2a |
+ tdesc_create_vector (feature, "v16i8", element_type, 16);
|
|
|
190f2a |
+
|
|
|
190f2a |
+ tdesc_type_with_fields *type_with_fields;
|
|
|
190f2a |
+ type_with_fields = tdesc_create_union (feature, "vec128");
|
|
|
190f2a |
+ tdesc_type *field_type;
|
|
|
190f2a |
+ field_type = tdesc_named_type (feature, "uint128");
|
|
|
190f2a |
+ tdesc_add_field (type_with_fields, "uint128", field_type);
|
|
|
190f2a |
+ field_type = tdesc_named_type (feature, "v4f");
|
|
|
190f2a |
+ tdesc_add_field (type_with_fields, "v4_float", field_type);
|
|
|
190f2a |
+ field_type = tdesc_named_type (feature, "v4i32");
|
|
|
190f2a |
+ tdesc_add_field (type_with_fields, "v4_int32", field_type);
|
|
|
190f2a |
+ field_type = tdesc_named_type (feature, "v8i16");
|
|
|
190f2a |
+ tdesc_add_field (type_with_fields, "v8_int16", field_type);
|
|
|
190f2a |
+ field_type = tdesc_named_type (feature, "v16i8");
|
|
|
190f2a |
+ tdesc_add_field (type_with_fields, "v16_int8", field_type);
|
|
|
190f2a |
+
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr0", 73, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr1", 74, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr2", 75, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr3", 76, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr4", 77, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr5", 78, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr6", 79, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr7", 80, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr8", 81, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr9", 82, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr10", 83, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr11", 84, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr12", 85, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr13", 86, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr14", 87, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr15", 88, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr16", 89, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr17", 90, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr18", 91, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr19", 92, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr20", 93, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr21", 94, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr22", 95, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr23", 96, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr24", 97, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr25", 98, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr26", 99, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr27", 100, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr28", 101, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr29", 102, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr30", 103, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr31", 104, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vscr", 105, 1, "vector", 32, "int");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vrsave", 106, 1, "vector", 32, "int");
|
|
|
190f2a |
+
|
|
|
190f2a |
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.vsx");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs0h", 107, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs1h", 108, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs2h", 109, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs3h", 110, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs4h", 111, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs5h", 112, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs6h", 113, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs7h", 114, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs8h", 115, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs9h", 116, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs10h", 117, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs11h", 118, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs12h", 119, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs13h", 120, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs14h", 121, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs15h", 122, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs16h", 123, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs17h", 124, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs18h", 125, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs19h", 126, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs20h", 127, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs21h", 128, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs22h", 129, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs23h", 130, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs24h", 131, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs25h", 132, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs26h", 133, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs27h", 134, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs28h", 135, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs29h", 136, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs30h", 137, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs31h", 138, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+
|
|
|
190f2a |
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.ppr");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "ppr", 139, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+
|
|
|
190f2a |
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.dscr");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "dscr", 140, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+
|
|
|
190f2a |
+ tdesc_powerpc_isa205_ppr_dscr_vsx32l = result;
|
|
|
190f2a |
+}
|
|
|
190f2a |
diff --git a/gdb/features/rs6000/powerpc-isa205-ppr-dscr-vsx32l.xml b/gdb/features/rs6000/powerpc-isa205-ppr-dscr-vsx32l.xml
|
|
|
190f2a |
new file mode 100644
|
|
|
190f2a |
--- /dev/null
|
|
|
190f2a |
+++ b/gdb/features/rs6000/powerpc-isa205-ppr-dscr-vsx32l.xml
|
|
|
190f2a |
@@ -0,0 +1,18 @@
|
|
|
190f2a |
+
|
|
|
190f2a |
+
|
|
|
190f2a |
+
|
|
|
190f2a |
+ Copying and distribution of this file, with or without modification,
|
|
|
190f2a |
+ are permitted in any medium without royalty provided the copyright
|
|
|
190f2a |
+ notice and this notice are preserved. -->
|
|
|
190f2a |
+
|
|
|
190f2a |
+
|
|
|
190f2a |
+<target>
|
|
|
190f2a |
+ <architecture>powerpc:common</architecture>
|
|
|
190f2a |
+ <xi:include href="power-core.xml"/>
|
|
|
190f2a |
+ <xi:include href="power-fpu-isa205.xml"/>
|
|
|
190f2a |
+ <xi:include href="power-linux.xml"/>
|
|
|
190f2a |
+ <xi:include href="power-altivec.xml"/>
|
|
|
190f2a |
+ <xi:include href="power-vsx.xml"/>
|
|
|
190f2a |
+ <xi:include href="power-ppr.xml"/>
|
|
|
190f2a |
+ <xi:include href="power-dscr.xml"/>
|
|
|
190f2a |
+</target>
|
|
|
190f2a |
diff --git a/gdb/features/rs6000/powerpc-isa205-ppr-dscr-vsx64l.c b/gdb/features/rs6000/powerpc-isa205-ppr-dscr-vsx64l.c
|
|
|
190f2a |
new file mode 100644
|
|
|
190f2a |
--- /dev/null
|
|
|
190f2a |
+++ b/gdb/features/rs6000/powerpc-isa205-ppr-dscr-vsx64l.c
|
|
|
190f2a |
@@ -0,0 +1,200 @@
|
|
|
190f2a |
+/* THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi:set ro:
|
|
|
190f2a |
+ Original: powerpc-isa205-ppr-dscr-vsx64l.xml */
|
|
|
190f2a |
+
|
|
|
190f2a |
+#include "defs.h"
|
|
|
190f2a |
+#include "osabi.h"
|
|
|
190f2a |
+#include "target-descriptions.h"
|
|
|
190f2a |
+
|
|
|
190f2a |
+struct target_desc *tdesc_powerpc_isa205_ppr_dscr_vsx64l;
|
|
|
190f2a |
+static void
|
|
|
190f2a |
+initialize_tdesc_powerpc_isa205_ppr_dscr_vsx64l (void)
|
|
|
190f2a |
+{
|
|
|
190f2a |
+ struct target_desc *result = allocate_target_description ();
|
|
|
190f2a |
+ set_tdesc_architecture (result, bfd_scan_arch ("powerpc:common64"));
|
|
|
190f2a |
+
|
|
|
190f2a |
+ struct tdesc_feature *feature;
|
|
|
190f2a |
+
|
|
|
190f2a |
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.core");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r0", 0, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r1", 1, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r2", 2, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r3", 3, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r4", 4, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r5", 5, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r6", 6, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r7", 7, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r8", 8, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r9", 9, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r10", 10, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r11", 11, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r12", 12, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r13", 13, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r14", 14, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r15", 15, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r16", 16, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r17", 17, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r18", 18, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r19", 19, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r20", 20, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r21", 21, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r22", 22, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r23", 23, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r24", 24, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r25", 25, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r26", 26, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r27", 27, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r28", 28, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r29", 29, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r30", 30, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "r31", 31, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "pc", 64, 1, NULL, 64, "code_ptr");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "msr", 65, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "cr", 66, 1, NULL, 32, "uint32");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "lr", 67, 1, NULL, 64, "code_ptr");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "ctr", 68, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "xer", 69, 1, NULL, 32, "uint32");
|
|
|
190f2a |
+
|
|
|
190f2a |
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.fpu");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f0", 32, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f1", 33, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f2", 34, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f3", 35, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f4", 36, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f5", 37, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f6", 38, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f7", 39, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f8", 40, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f9", 41, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f10", 42, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f11", 43, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f12", 44, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f13", 45, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f14", 46, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f15", 47, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f16", 48, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f17", 49, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f18", 50, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f19", 51, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f20", 52, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f21", 53, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f22", 54, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f23", 55, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f24", 56, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f25", 57, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f26", 58, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f27", 59, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f28", 60, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f29", 61, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f30", 62, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "f31", 63, 1, NULL, 64, "ieee_double");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "fpscr", 70, 1, "float", 64, "int");
|
|
|
190f2a |
+
|
|
|
190f2a |
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.linux");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "orig_r3", 71, 1, NULL, 64, "int");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "trap", 72, 1, NULL, 64, "int");
|
|
|
190f2a |
+
|
|
|
190f2a |
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.altivec");
|
|
|
190f2a |
+ tdesc_type *element_type;
|
|
|
190f2a |
+ element_type = tdesc_named_type (feature, "ieee_single");
|
|
|
190f2a |
+ tdesc_create_vector (feature, "v4f", element_type, 4);
|
|
|
190f2a |
+
|
|
|
190f2a |
+ element_type = tdesc_named_type (feature, "int32");
|
|
|
190f2a |
+ tdesc_create_vector (feature, "v4i32", element_type, 4);
|
|
|
190f2a |
+
|
|
|
190f2a |
+ element_type = tdesc_named_type (feature, "int16");
|
|
|
190f2a |
+ tdesc_create_vector (feature, "v8i16", element_type, 8);
|
|
|
190f2a |
+
|
|
|
190f2a |
+ element_type = tdesc_named_type (feature, "int8");
|
|
|
190f2a |
+ tdesc_create_vector (feature, "v16i8", element_type, 16);
|
|
|
190f2a |
+
|
|
|
190f2a |
+ tdesc_type_with_fields *type_with_fields;
|
|
|
190f2a |
+ type_with_fields = tdesc_create_union (feature, "vec128");
|
|
|
190f2a |
+ tdesc_type *field_type;
|
|
|
190f2a |
+ field_type = tdesc_named_type (feature, "uint128");
|
|
|
190f2a |
+ tdesc_add_field (type_with_fields, "uint128", field_type);
|
|
|
190f2a |
+ field_type = tdesc_named_type (feature, "v4f");
|
|
|
190f2a |
+ tdesc_add_field (type_with_fields, "v4_float", field_type);
|
|
|
190f2a |
+ field_type = tdesc_named_type (feature, "v4i32");
|
|
|
190f2a |
+ tdesc_add_field (type_with_fields, "v4_int32", field_type);
|
|
|
190f2a |
+ field_type = tdesc_named_type (feature, "v8i16");
|
|
|
190f2a |
+ tdesc_add_field (type_with_fields, "v8_int16", field_type);
|
|
|
190f2a |
+ field_type = tdesc_named_type (feature, "v16i8");
|
|
|
190f2a |
+ tdesc_add_field (type_with_fields, "v16_int8", field_type);
|
|
|
190f2a |
+
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr0", 73, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr1", 74, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr2", 75, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr3", 76, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr4", 77, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr5", 78, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr6", 79, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr7", 80, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr8", 81, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr9", 82, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr10", 83, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr11", 84, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr12", 85, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr13", 86, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr14", 87, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr15", 88, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr16", 89, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr17", 90, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr18", 91, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr19", 92, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr20", 93, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr21", 94, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr22", 95, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr23", 96, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr24", 97, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr25", 98, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr26", 99, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr27", 100, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr28", 101, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr29", 102, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr30", 103, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vr31", 104, 1, NULL, 128, "vec128");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vscr", 105, 1, "vector", 32, "int");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vrsave", 106, 1, "vector", 32, "int");
|
|
|
190f2a |
+
|
|
|
190f2a |
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.vsx");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs0h", 107, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs1h", 108, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs2h", 109, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs3h", 110, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs4h", 111, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs5h", 112, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs6h", 113, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs7h", 114, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs8h", 115, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs9h", 116, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs10h", 117, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs11h", 118, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs12h", 119, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs13h", 120, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs14h", 121, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs15h", 122, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs16h", 123, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs17h", 124, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs18h", 125, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs19h", 126, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs20h", 127, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs21h", 128, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs22h", 129, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs23h", 130, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs24h", 131, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs25h", 132, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs26h", 133, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs27h", 134, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs28h", 135, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs29h", 136, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs30h", 137, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "vs31h", 138, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+
|
|
|
190f2a |
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.ppr");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "ppr", 139, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+
|
|
|
190f2a |
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.dscr");
|
|
|
190f2a |
+ tdesc_create_reg (feature, "dscr", 140, 1, NULL, 64, "uint64");
|
|
|
190f2a |
+
|
|
|
190f2a |
+ tdesc_powerpc_isa205_ppr_dscr_vsx64l = result;
|
|
|
190f2a |
+}
|
|
|
190f2a |
diff --git a/gdb/features/rs6000/powerpc-isa205-ppr-dscr-vsx64l.xml b/gdb/features/rs6000/powerpc-isa205-ppr-dscr-vsx64l.xml
|
|
|
190f2a |
new file mode 100644
|
|
|
190f2a |
--- /dev/null
|
|
|
190f2a |
+++ b/gdb/features/rs6000/powerpc-isa205-ppr-dscr-vsx64l.xml
|
|
|
190f2a |
@@ -0,0 +1,18 @@
|
|
|
190f2a |
+
|
|
|
190f2a |
+
|
|
|
190f2a |
+
|
|
|
190f2a |
+ Copying and distribution of this file, with or without modification,
|
|
|
190f2a |
+ are permitted in any medium without royalty provided the copyright
|
|
|
190f2a |
+ notice and this notice are preserved. -->
|
|
|
190f2a |
+
|
|
|
190f2a |
+
|
|
|
190f2a |
+<target>
|
|
|
190f2a |
+ <architecture>powerpc:common64</architecture>
|
|
|
190f2a |
+ <xi:include href="power64-core.xml"/>
|
|
|
190f2a |
+ <xi:include href="power-fpu-isa205.xml"/>
|
|
|
190f2a |
+ <xi:include href="power64-linux.xml"/>
|
|
|
190f2a |
+ <xi:include href="power-altivec.xml"/>
|
|
|
190f2a |
+ <xi:include href="power-vsx.xml"/>
|
|
|
190f2a |
+ <xi:include href="power-ppr.xml"/>
|
|
|
190f2a |
+ <xi:include href="power-dscr.xml"/>
|
|
|
190f2a |
+</target>
|
|
|
190f2a |
diff --git a/gdb/gdbserver/configure.srv b/gdb/gdbserver/configure.srv
|
|
|
190f2a |
--- a/gdb/gdbserver/configure.srv
|
|
|
190f2a |
+++ b/gdb/gdbserver/configure.srv
|
|
|
190f2a |
@@ -32,7 +32,7 @@ else
|
|
|
190f2a |
srv_amd64_linux_regobj=""
|
|
|
190f2a |
fi
|
|
|
190f2a |
|
|
|
190f2a |
-ipa_ppc_linux_regobj="powerpc-32l-ipa.o powerpc-altivec32l-ipa.o powerpc-cell32l-ipa.o powerpc-vsx32l-ipa.o powerpc-isa205-32l-ipa.o powerpc-isa205-altivec32l-ipa.o powerpc-isa205-vsx32l-ipa.o powerpc-e500l-ipa.o powerpc-64l-ipa.o powerpc-altivec64l-ipa.o powerpc-cell64l-ipa.o powerpc-vsx64l-ipa.o powerpc-isa205-64l-ipa.o powerpc-isa205-altivec64l-ipa.o powerpc-isa205-vsx64l-ipa.o"
|
|
|
190f2a |
+ipa_ppc_linux_regobj="powerpc-32l-ipa.o powerpc-altivec32l-ipa.o powerpc-cell32l-ipa.o powerpc-vsx32l-ipa.o powerpc-isa205-32l-ipa.o powerpc-isa205-altivec32l-ipa.o powerpc-isa205-vsx32l-ipa.o powerpc-isa205-ppr-dscr-vsx32l-ipa.o powerpc-e500l-ipa.o powerpc-64l-ipa.o powerpc-altivec64l-ipa.o powerpc-cell64l-ipa.o powerpc-vsx64l-ipa.o powerpc-isa205-64l-ipa.o powerpc-isa205-altivec64l-ipa.o powerpc-isa205-vsx64l-ipa.o powerpc-isa205-ppr-dscr-vsx64l-ipa.o"
|
|
|
190f2a |
|
|
|
190f2a |
# Linux object files. This is so we don't have to repeat
|
|
|
190f2a |
# these files over and over again.
|
|
|
190f2a |
@@ -217,6 +217,7 @@ case "${target}" in
|
|
|
190f2a |
srv_regobj="${srv_regobj} powerpc-isa205-32l.o"
|
|
|
190f2a |
srv_regobj="${srv_regobj} powerpc-isa205-altivec32l.o"
|
|
|
190f2a |
srv_regobj="${srv_regobj} powerpc-isa205-vsx32l.o"
|
|
|
190f2a |
+ srv_regobj="${srv_regobj} powerpc-isa205-ppr-dscr-vsx32l.o"
|
|
|
190f2a |
srv_regobj="${srv_regobj} powerpc-e500l.o"
|
|
|
190f2a |
srv_regobj="${srv_regobj} powerpc-64l.o"
|
|
|
190f2a |
srv_regobj="${srv_regobj} powerpc-altivec64l.o"
|
|
|
190f2a |
@@ -225,6 +226,7 @@ case "${target}" in
|
|
|
190f2a |
srv_regobj="${srv_regobj} powerpc-isa205-64l.o"
|
|
|
190f2a |
srv_regobj="${srv_regobj} powerpc-isa205-altivec64l.o"
|
|
|
190f2a |
srv_regobj="${srv_regobj} powerpc-isa205-vsx64l.o"
|
|
|
190f2a |
+ srv_regobj="${srv_regobj} powerpc-isa205-ppr-dscr-vsx64l.o"
|
|
|
190f2a |
srv_tgtobj="$srv_linux_obj linux-ppc-low.o ppc-linux.o"
|
|
|
190f2a |
srv_tgtobj="${srv_tgtobj} arch/ppc-linux-common.o"
|
|
|
190f2a |
srv_xmlfiles="rs6000/powerpc-32l.xml"
|
|
|
190f2a |
@@ -234,12 +236,15 @@ case "${target}" in
|
|
|
190f2a |
srv_xmlfiles="${srv_xmlfiles} rs6000/powerpc-isa205-32l.xml"
|
|
|
190f2a |
srv_xmlfiles="${srv_xmlfiles} rs6000/powerpc-isa205-altivec32l.xml"
|
|
|
190f2a |
srv_xmlfiles="${srv_xmlfiles} rs6000/powerpc-isa205-vsx32l.xml"
|
|
|
190f2a |
+ srv_xmlfiles="${srv_xmlfiles} rs6000/powerpc-isa205-ppr-dscr-vsx32l.xml"
|
|
|
190f2a |
srv_xmlfiles="${srv_xmlfiles} rs6000/power-altivec.xml"
|
|
|
190f2a |
srv_xmlfiles="${srv_xmlfiles} rs6000/power-vsx.xml"
|
|
|
190f2a |
srv_xmlfiles="${srv_xmlfiles} rs6000/power-core.xml"
|
|
|
190f2a |
srv_xmlfiles="${srv_xmlfiles} rs6000/power-linux.xml"
|
|
|
190f2a |
srv_xmlfiles="${srv_xmlfiles} rs6000/power-fpu.xml"
|
|
|
190f2a |
srv_xmlfiles="${srv_xmlfiles} rs6000/power-fpu-isa205.xml"
|
|
|
190f2a |
+ srv_xmlfiles="${srv_xmlfiles} rs6000/power-dscr.xml"
|
|
|
190f2a |
+ srv_xmlfiles="${srv_xmlfiles} rs6000/power-ppr.xml"
|
|
|
190f2a |
srv_xmlfiles="${srv_xmlfiles} rs6000/powerpc-e500l.xml"
|
|
|
190f2a |
srv_xmlfiles="${srv_xmlfiles} rs6000/power-spe.xml"
|
|
|
190f2a |
srv_xmlfiles="${srv_xmlfiles} rs6000/powerpc-64l.xml"
|
|
|
190f2a |
@@ -249,6 +254,7 @@ case "${target}" in
|
|
|
190f2a |
srv_xmlfiles="${srv_xmlfiles} rs6000/powerpc-isa205-64l.xml"
|
|
|
190f2a |
srv_xmlfiles="${srv_xmlfiles} rs6000/powerpc-isa205-altivec64l.xml"
|
|
|
190f2a |
srv_xmlfiles="${srv_xmlfiles} rs6000/powerpc-isa205-vsx64l.xml"
|
|
|
190f2a |
+ srv_xmlfiles="${srv_xmlfiles} rs6000/powerpc-isa205-ppr-dscr-vsx64l.xml"
|
|
|
190f2a |
srv_xmlfiles="${srv_xmlfiles} rs6000/power64-core.xml"
|
|
|
190f2a |
srv_xmlfiles="${srv_xmlfiles} rs6000/power64-linux.xml"
|
|
|
190f2a |
srv_linux_usrregs=yes
|
|
|
190f2a |
diff --git a/gdb/gdbserver/linux-ppc-ipa.c b/gdb/gdbserver/linux-ppc-ipa.c
|
|
|
190f2a |
--- a/gdb/gdbserver/linux-ppc-ipa.c
|
|
|
190f2a |
+++ b/gdb/gdbserver/linux-ppc-ipa.c
|
|
|
190f2a |
@@ -191,6 +191,8 @@ get_ipa_tdesc (int idx)
|
|
|
190f2a |
return tdesc_powerpc_isa205_altivec64l;
|
|
|
190f2a |
case PPC_TDESC_ISA205_VSX:
|
|
|
190f2a |
return tdesc_powerpc_isa205_vsx64l;
|
|
|
190f2a |
+ case PPC_TDESC_ISA205_PPR_DSCR_VSX:
|
|
|
190f2a |
+ return tdesc_powerpc_isa205_ppr_dscr_vsx64l;
|
|
|
190f2a |
#else
|
|
|
190f2a |
case PPC_TDESC_BASE:
|
|
|
190f2a |
return tdesc_powerpc_32l;
|
|
|
190f2a |
@@ -206,6 +208,8 @@ get_ipa_tdesc (int idx)
|
|
|
190f2a |
return tdesc_powerpc_isa205_altivec32l;
|
|
|
190f2a |
case PPC_TDESC_ISA205_VSX:
|
|
|
190f2a |
return tdesc_powerpc_isa205_vsx32l;
|
|
|
190f2a |
+ case PPC_TDESC_ISA205_PPR_DSCR_VSX:
|
|
|
190f2a |
+ return tdesc_powerpc_isa205_ppr_dscr_vsx32l;
|
|
|
190f2a |
case PPC_TDESC_E500:
|
|
|
190f2a |
return tdesc_powerpc_e500l;
|
|
|
190f2a |
#endif
|
|
|
190f2a |
@@ -234,6 +238,7 @@ initialize_low_tracepoint (void)
|
|
|
190f2a |
init_registers_powerpc_isa205_64l ();
|
|
|
190f2a |
init_registers_powerpc_isa205_altivec64l ();
|
|
|
190f2a |
init_registers_powerpc_isa205_vsx64l ();
|
|
|
190f2a |
+ init_registers_powerpc_isa205_ppr_dscr_vsx64l ();
|
|
|
190f2a |
#else
|
|
|
190f2a |
init_registers_powerpc_32l ();
|
|
|
190f2a |
init_registers_powerpc_altivec32l ();
|
|
|
190f2a |
@@ -242,6 +247,7 @@ initialize_low_tracepoint (void)
|
|
|
190f2a |
init_registers_powerpc_isa205_32l ();
|
|
|
190f2a |
init_registers_powerpc_isa205_altivec32l ();
|
|
|
190f2a |
init_registers_powerpc_isa205_vsx32l ();
|
|
|
190f2a |
+ init_registers_powerpc_isa205_ppr_dscr_vsx32l ();
|
|
|
190f2a |
init_registers_powerpc_e500l ();
|
|
|
190f2a |
#endif
|
|
|
190f2a |
}
|
|
|
190f2a |
diff --git a/gdb/gdbserver/linux-ppc-low.c b/gdb/gdbserver/linux-ppc-low.c
|
|
|
190f2a |
--- a/gdb/gdbserver/linux-ppc-low.c
|
|
|
190f2a |
+++ b/gdb/gdbserver/linux-ppc-low.c
|
|
|
190f2a |
@@ -20,6 +20,8 @@
|
|
|
190f2a |
#include "server.h"
|
|
|
190f2a |
#include "linux-low.h"
|
|
|
190f2a |
|
|
|
190f2a |
+#include "elf/common.h"
|
|
|
190f2a |
+#include <sys/uio.h>
|
|
|
190f2a |
#include <elf.h>
|
|
|
190f2a |
#include <asm/ptrace.h>
|
|
|
190f2a |
|
|
|
190f2a |
@@ -41,8 +43,14 @@
|
|
|
190f2a |
#define PPC_LI(insn) (PPC_SEXT (PPC_FIELD (insn, 6, 24), 24) << 2)
|
|
|
190f2a |
#define PPC_BD(insn) (PPC_SEXT (PPC_FIELD (insn, 16, 14), 14) << 2)
|
|
|
190f2a |
|
|
|
190f2a |
+/* Holds the AT_HWCAP auxv entry. */
|
|
|
190f2a |
+
|
|
|
190f2a |
static unsigned long ppc_hwcap;
|
|
|
190f2a |
|
|
|
190f2a |
+/* Holds the AT_HWCAP2 auxv entry. */
|
|
|
190f2a |
+
|
|
|
190f2a |
+static unsigned long ppc_hwcap2;
|
|
|
190f2a |
+
|
|
|
190f2a |
|
|
|
190f2a |
#define ppc_num_regs 73
|
|
|
190f2a |
|
|
|
190f2a |
@@ -116,6 +124,24 @@ static int ppc_regmap_e500[] =
|
|
|
190f2a |
};
|
|
|
190f2a |
#endif
|
|
|
190f2a |
|
|
|
190f2a |
+/* Check whether the kernel provides a register set with number
|
|
|
190f2a |
+ REGSET_ID of size REGSETSIZE for process/thread TID. */
|
|
|
190f2a |
+
|
|
|
190f2a |
+static int
|
|
|
190f2a |
+ppc_check_regset (int tid, int regset_id, int regsetsize)
|
|
|
190f2a |
+{
|
|
|
190f2a |
+ void *buf = alloca (regsetsize);
|
|
|
190f2a |
+ struct iovec iov;
|
|
|
190f2a |
+
|
|
|
190f2a |
+ iov.iov_base = buf;
|
|
|
190f2a |
+ iov.iov_len = regsetsize;
|
|
|
190f2a |
+
|
|
|
190f2a |
+ if (ptrace (PTRACE_GETREGSET, tid, regset_id, &iov) >= 0
|
|
|
190f2a |
+ || errno == ENODATA)
|
|
|
190f2a |
+ return 1;
|
|
|
190f2a |
+ return 0;
|
|
|
190f2a |
+}
|
|
|
190f2a |
+
|
|
|
190f2a |
static int
|
|
|
190f2a |
ppc_cannot_store_register (int regno)
|
|
|
190f2a |
{
|
|
|
190f2a |
@@ -459,6 +485,46 @@ static void ppc_fill_gregset (struct regcache *regcache, void *buf)
|
|
|
190f2a |
ppc_collect_ptrace_register (regcache, i, (char *) buf + ppc_regmap[i]);
|
|
|
190f2a |
}
|
|
|
190f2a |
|
|
|
190f2a |
+/* Program Priority Register regset fill function. */
|
|
|
190f2a |
+
|
|
|
190f2a |
+static void
|
|
|
190f2a |
+ppc_fill_pprregset (struct regcache *regcache, void *buf)
|
|
|
190f2a |
+{
|
|
|
190f2a |
+ char *ppr = (char *) buf;
|
|
|
190f2a |
+
|
|
|
190f2a |
+ collect_register_by_name (regcache, "ppr", ppr);
|
|
|
190f2a |
+}
|
|
|
190f2a |
+
|
|
|
190f2a |
+/* Program Priority Register regset store function. */
|
|
|
190f2a |
+
|
|
|
190f2a |
+static void
|
|
|
190f2a |
+ppc_store_pprregset (struct regcache *regcache, const void *buf)
|
|
|
190f2a |
+{
|
|
|
190f2a |
+ const char *ppr = (const char *) buf;
|
|
|
190f2a |
+
|
|
|
190f2a |
+ supply_register_by_name (regcache, "ppr", ppr);
|
|
|
190f2a |
+}
|
|
|
190f2a |
+
|
|
|
190f2a |
+/* Data Stream Control Register regset fill function. */
|
|
|
190f2a |
+
|
|
|
190f2a |
+static void
|
|
|
190f2a |
+ppc_fill_dscrregset (struct regcache *regcache, void *buf)
|
|
|
190f2a |
+{
|
|
|
190f2a |
+ char *dscr = (char *) buf;
|
|
|
190f2a |
+
|
|
|
190f2a |
+ collect_register_by_name (regcache, "dscr", dscr);
|
|
|
190f2a |
+}
|
|
|
190f2a |
+
|
|
|
190f2a |
+/* Data Stream Control Register regset store function. */
|
|
|
190f2a |
+
|
|
|
190f2a |
+static void
|
|
|
190f2a |
+ppc_store_dscrregset (struct regcache *regcache, const void *buf)
|
|
|
190f2a |
+{
|
|
|
190f2a |
+ const char *dscr = (const char *) buf;
|
|
|
190f2a |
+
|
|
|
190f2a |
+ supply_register_by_name (regcache, "dscr", dscr);
|
|
|
190f2a |
+}
|
|
|
190f2a |
+
|
|
|
190f2a |
static void
|
|
|
190f2a |
ppc_fill_vsxregset (struct regcache *regcache, void *buf)
|
|
|
190f2a |
{
|
|
|
190f2a |
@@ -568,6 +634,10 @@ static struct regset_info ppc_regsets[] = {
|
|
|
190f2a |
fetch them every time, but still fall back to PTRACE_PEEKUSER for the
|
|
|
190f2a |
general registers. Some kernels support these, but not the newer
|
|
|
190f2a |
PPC_PTRACE_GETREGS. */
|
|
|
190f2a |
+ { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_PPR, 0, EXTENDED_REGS,
|
|
|
190f2a |
+ ppc_fill_pprregset, ppc_store_pprregset },
|
|
|
190f2a |
+ { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_DSCR, 0, EXTENDED_REGS,
|
|
|
190f2a |
+ ppc_fill_dscrregset, ppc_store_dscrregset },
|
|
|
190f2a |
{ PTRACE_GETVSXREGS, PTRACE_SETVSXREGS, 0, 0, EXTENDED_REGS,
|
|
|
190f2a |
ppc_fill_vsxregset, ppc_store_vsxregset },
|
|
|
190f2a |
{ PTRACE_GETVRREGS, PTRACE_SETVRREGS, 0, 0, EXTENDED_REGS,
|
|
|
190f2a |
@@ -625,6 +695,7 @@ ppc_arch_setup (void)
|
|
|
190f2a |
/* The value of current_process ()->tdesc needs to be set for this
|
|
|
190f2a |
call. */
|
|
|
190f2a |
ppc_get_auxv (AT_HWCAP, &ppc_hwcap);
|
|
|
190f2a |
+ ppc_get_auxv (AT_HWCAP2, &ppc_hwcap2);
|
|
|
190f2a |
|
|
|
190f2a |
features.isa205 = ppc_linux_has_isa205 (ppc_hwcap);
|
|
|
190f2a |
|
|
|
190f2a |
@@ -634,6 +705,11 @@ ppc_arch_setup (void)
|
|
|
190f2a |
if (ppc_hwcap & PPC_FEATURE_HAS_ALTIVEC)
|
|
|
190f2a |
features.altivec = true;
|
|
|
190f2a |
|
|
|
190f2a |
+ if ((ppc_hwcap2 & PPC_FEATURE2_DSCR)
|
|
|
190f2a |
+ && ppc_check_regset (tid, NT_PPC_DSCR, PPC_LINUX_SIZEOF_DSCRREGSET)
|
|
|
190f2a |
+ && ppc_check_regset (tid, NT_PPC_PPR, PPC_LINUX_SIZEOF_PPRREGSET))
|
|
|
190f2a |
+ features.ppr_dscr = true;
|
|
|
190f2a |
+
|
|
|
190f2a |
if (ppc_hwcap & PPC_FEATURE_CELL)
|
|
|
190f2a |
features.cell = true;
|
|
|
190f2a |
|
|
|
190f2a |
@@ -678,6 +754,21 @@ ppc_arch_setup (void)
|
|
|
190f2a |
else
|
|
|
190f2a |
regset->size = 0;
|
|
|
190f2a |
break;
|
|
|
190f2a |
+ case PTRACE_GETREGSET:
|
|
|
190f2a |
+ switch (regset->nt_type)
|
|
|
190f2a |
+ {
|
|
|
190f2a |
+ case NT_PPC_PPR:
|
|
|
190f2a |
+ regset->size = (features.ppr_dscr ?
|
|
|
190f2a |
+ PPC_LINUX_SIZEOF_PPRREGSET : 0);
|
|
|
190f2a |
+ break;
|
|
|
190f2a |
+ case NT_PPC_DSCR:
|
|
|
190f2a |
+ regset->size = (features.ppr_dscr ?
|
|
|
190f2a |
+ PPC_LINUX_SIZEOF_DSCRREGSET : 0);
|
|
|
190f2a |
+ break;
|
|
|
190f2a |
+ default:
|
|
|
190f2a |
+ break;
|
|
|
190f2a |
+ }
|
|
|
190f2a |
+ break;
|
|
|
190f2a |
default:
|
|
|
190f2a |
break;
|
|
|
190f2a |
}
|
|
|
190f2a |
@@ -3053,6 +3144,8 @@ ppc_get_ipa_tdesc_idx (void)
|
|
|
190f2a |
return PPC_TDESC_ISA205_ALTIVEC;
|
|
|
190f2a |
if (tdesc == tdesc_powerpc_isa205_vsx64l)
|
|
|
190f2a |
return PPC_TDESC_ISA205_VSX;
|
|
|
190f2a |
+ if (tdesc == tdesc_powerpc_isa205_ppr_dscr_vsx64l)
|
|
|
190f2a |
+ return PPC_TDESC_ISA205_PPR_DSCR_VSX;
|
|
|
190f2a |
#endif
|
|
|
190f2a |
|
|
|
190f2a |
if (tdesc == tdesc_powerpc_32l)
|
|
|
190f2a |
@@ -3069,6 +3162,8 @@ ppc_get_ipa_tdesc_idx (void)
|
|
|
190f2a |
return PPC_TDESC_ISA205_ALTIVEC;
|
|
|
190f2a |
if (tdesc == tdesc_powerpc_isa205_vsx32l)
|
|
|
190f2a |
return PPC_TDESC_ISA205_VSX;
|
|
|
190f2a |
+ if (tdesc == tdesc_powerpc_isa205_ppr_dscr_vsx32l)
|
|
|
190f2a |
+ return PPC_TDESC_ISA205_PPR_DSCR_VSX;
|
|
|
190f2a |
if (tdesc == tdesc_powerpc_e500l)
|
|
|
190f2a |
return PPC_TDESC_E500;
|
|
|
190f2a |
|
|
|
190f2a |
@@ -3127,6 +3222,7 @@ initialize_low_arch (void)
|
|
|
190f2a |
init_registers_powerpc_isa205_32l ();
|
|
|
190f2a |
init_registers_powerpc_isa205_altivec32l ();
|
|
|
190f2a |
init_registers_powerpc_isa205_vsx32l ();
|
|
|
190f2a |
+ init_registers_powerpc_isa205_ppr_dscr_vsx32l ();
|
|
|
190f2a |
init_registers_powerpc_e500l ();
|
|
|
190f2a |
#if __powerpc64__
|
|
|
190f2a |
init_registers_powerpc_64l ();
|
|
|
190f2a |
@@ -3136,6 +3232,7 @@ initialize_low_arch (void)
|
|
|
190f2a |
init_registers_powerpc_isa205_64l ();
|
|
|
190f2a |
init_registers_powerpc_isa205_altivec64l ();
|
|
|
190f2a |
init_registers_powerpc_isa205_vsx64l ();
|
|
|
190f2a |
+ init_registers_powerpc_isa205_ppr_dscr_vsx64l ();
|
|
|
190f2a |
#endif
|
|
|
190f2a |
|
|
|
190f2a |
initialize_regsets_info (&ppc_regsets_info);
|
|
|
190f2a |
diff --git a/gdb/gdbserver/linux-ppc-tdesc-init.h b/gdb/gdbserver/linux-ppc-tdesc-init.h
|
|
|
190f2a |
--- a/gdb/gdbserver/linux-ppc-tdesc-init.h
|
|
|
190f2a |
+++ b/gdb/gdbserver/linux-ppc-tdesc-init.h
|
|
|
190f2a |
@@ -29,6 +29,7 @@ enum ppc_linux_tdesc {
|
|
|
190f2a |
PPC_TDESC_ISA205,
|
|
|
190f2a |
PPC_TDESC_ISA205_ALTIVEC,
|
|
|
190f2a |
PPC_TDESC_ISA205_VSX,
|
|
|
190f2a |
+ PPC_TDESC_ISA205_PPR_DSCR_VSX,
|
|
|
190f2a |
PPC_TDESC_E500,
|
|
|
190f2a |
};
|
|
|
190f2a |
|
|
|
190f2a |
@@ -55,6 +56,9 @@ void init_registers_powerpc_isa205_altivec32l (void);
|
|
|
190f2a |
/* Defined in auto-generated file powerpc-isa205-vsx32l.c. */
|
|
|
190f2a |
void init_registers_powerpc_isa205_vsx32l (void);
|
|
|
190f2a |
|
|
|
190f2a |
+/* Defined in auto-generated file powerpc-isa205-ppr-dscr-vsx32l.c. */
|
|
|
190f2a |
+void init_registers_powerpc_isa205_ppr_dscr_vsx32l (void);
|
|
|
190f2a |
+
|
|
|
190f2a |
/* Defined in auto-generated file powerpc-e500l.c. */
|
|
|
190f2a |
void init_registers_powerpc_e500l (void);
|
|
|
190f2a |
|
|
|
190f2a |
@@ -83,4 +87,7 @@ void init_registers_powerpc_isa205_altivec64l (void);
|
|
|
190f2a |
/* Defined in auto-generated file powerpc-isa205-vsx64l.c. */
|
|
|
190f2a |
void init_registers_powerpc_isa205_vsx64l (void);
|
|
|
190f2a |
|
|
|
190f2a |
+/* Defined in auto-generated file powerpc-isa205-ppr-dscr-vsx64l.c. */
|
|
|
190f2a |
+void init_registers_powerpc_isa205_ppr_dscr_vsx64l (void);
|
|
|
190f2a |
+
|
|
|
190f2a |
#endif
|
|
|
190f2a |
diff --git a/gdb/nat/ppc-linux.h b/gdb/nat/ppc-linux.h
|
|
|
190f2a |
--- a/gdb/nat/ppc-linux.h
|
|
|
190f2a |
+++ b/gdb/nat/ppc-linux.h
|
|
|
190f2a |
@@ -51,6 +51,9 @@
|
|
|
190f2a |
#ifndef PPC_FEATURE_HAS_SPE
|
|
|
190f2a |
#define PPC_FEATURE_HAS_SPE 0x00800000
|
|
|
190f2a |
#endif
|
|
|
190f2a |
+#ifndef PPC_FEATURE2_DSCR
|
|
|
190f2a |
+#define PPC_FEATURE2_DSCR 0x20000000
|
|
|
190f2a |
+#endif
|
|
|
190f2a |
|
|
|
190f2a |
/* Glibc's headers don't define PTRACE_GETVRREGS so we cannot use a
|
|
|
190f2a |
configure time check. Some older glibc's (for instance 2.2.1)
|
|
|
190f2a |
@@ -82,6 +85,16 @@
|
|
|
190f2a |
#define PTRACE_SETEVRREGS 21
|
|
|
190f2a |
#endif
|
|
|
190f2a |
|
|
|
190f2a |
+/* Program Priority Register. */
|
|
|
190f2a |
+#ifndef NT_PPC_PPR
|
|
|
190f2a |
+#define NT_PPC_PPR 0x104
|
|
|
190f2a |
+#endif
|
|
|
190f2a |
+
|
|
|
190f2a |
+/* Data Stream Control Register. */
|
|
|
190f2a |
+#ifndef NT_PPC_DSCR
|
|
|
190f2a |
+#define NT_PPC_DSCR 0x105
|
|
|
190f2a |
+#endif
|
|
|
190f2a |
+
|
|
|
190f2a |
/* Return the wordsize of the target, either 4 or 8 bytes. */
|
|
|
190f2a |
int ppc_linux_target_wordsize (int tid);
|
|
|
190f2a |
|
|
|
190f2a |
diff --git a/gdb/ppc-linux-nat.c b/gdb/ppc-linux-nat.c
|
|
|
190f2a |
--- a/gdb/ppc-linux-nat.c
|
|
|
190f2a |
+++ b/gdb/ppc-linux-nat.c
|
|
|
190f2a |
@@ -31,6 +31,7 @@
|
|
|
190f2a |
#include <signal.h>
|
|
|
190f2a |
#include <sys/user.h>
|
|
|
190f2a |
#include <sys/ioctl.h>
|
|
|
190f2a |
+#include <sys/uio.h>
|
|
|
190f2a |
#include "gdb_wait.h"
|
|
|
190f2a |
#include <fcntl.h>
|
|
|
190f2a |
#include <sys/procfs.h>
|
|
|
190f2a |
@@ -528,6 +529,78 @@ fetch_spe_register (struct regcache *regcache, int tid, int regno)
|
|
|
190f2a |
regcache->raw_supply (tdep->ppc_spefscr_regnum, &evrregs.spefscr);
|
|
|
190f2a |
}
|
|
|
190f2a |
|
|
|
190f2a |
+/* Use ptrace to fetch all registers from the register set with note
|
|
|
190f2a |
+ type REGSET_ID, size REGSIZE, and layout described by REGSET, from
|
|
|
190f2a |
+ process/thread TID and supply their values to REGCACHE. If ptrace
|
|
|
190f2a |
+ returns ENODATA to indicate the regset is unavailable, mark the
|
|
|
190f2a |
+ registers as unavailable in REGCACHE. */
|
|
|
190f2a |
+
|
|
|
190f2a |
+static void
|
|
|
190f2a |
+fetch_regset (struct regcache *regcache, int tid,
|
|
|
190f2a |
+ int regset_id, int regsetsize, const struct regset *regset)
|
|
|
190f2a |
+{
|
|
|
190f2a |
+ void *buf = alloca (regsetsize);
|
|
|
190f2a |
+ struct iovec iov;
|
|
|
190f2a |
+
|
|
|
190f2a |
+ iov.iov_base = buf;
|
|
|
190f2a |
+ iov.iov_len = regsetsize;
|
|
|
190f2a |
+
|
|
|
190f2a |
+ if (ptrace (PTRACE_GETREGSET, tid, regset_id, &iov) < 0)
|
|
|
190f2a |
+ {
|
|
|
190f2a |
+ if (errno == ENODATA)
|
|
|
190f2a |
+ regset->supply_regset (regset, regcache, -1, NULL, regsetsize);
|
|
|
190f2a |
+ else
|
|
|
190f2a |
+ perror_with_name (_("Couldn't get register set"));
|
|
|
190f2a |
+ }
|
|
|
190f2a |
+ else
|
|
|
190f2a |
+ regset->supply_regset (regset, regcache, -1, buf, regsetsize);
|
|
|
190f2a |
+}
|
|
|
190f2a |
+
|
|
|
190f2a |
+/* Use ptrace to store register REGNUM of the regset with note type
|
|
|
190f2a |
+ REGSET_ID, size REGSETSIZE, and layout described by REGSET, from
|
|
|
190f2a |
+ REGCACHE back to process/thread TID. If REGNUM is -1 all registers
|
|
|
190f2a |
+ in the set are collected and stored. */
|
|
|
190f2a |
+
|
|
|
190f2a |
+static void
|
|
|
190f2a |
+store_regset (const struct regcache *regcache, int tid, int regnum,
|
|
|
190f2a |
+ int regset_id, int regsetsize, const struct regset *regset)
|
|
|
190f2a |
+{
|
|
|
190f2a |
+ void *buf = alloca (regsetsize);
|
|
|
190f2a |
+ struct iovec iov;
|
|
|
190f2a |
+
|
|
|
190f2a |
+ iov.iov_base = buf;
|
|
|
190f2a |
+ iov.iov_len = regsetsize;
|
|
|
190f2a |
+
|
|
|
190f2a |
+ /* Make sure that the buffer that will be stored has up to date values
|
|
|
190f2a |
+ for the registers that won't be collected. */
|
|
|
190f2a |
+ if (ptrace (PTRACE_GETREGSET, tid, regset_id, &iov) < 0)
|
|
|
190f2a |
+ perror_with_name (_("Couldn't get register set"));
|
|
|
190f2a |
+
|
|
|
190f2a |
+ regset->collect_regset (regset, regcache, regnum, buf, regsetsize);
|
|
|
190f2a |
+
|
|
|
190f2a |
+ if (ptrace (PTRACE_SETREGSET, tid, regset_id, &iov) < 0)
|
|
|
190f2a |
+ perror_with_name (_("Couldn't set register set"));
|
|
|
190f2a |
+}
|
|
|
190f2a |
+
|
|
|
190f2a |
+/* Check whether the kernel provides a register set with number
|
|
|
190f2a |
+ REGSET_ID of size REGSETSIZE for process/thread TID. */
|
|
|
190f2a |
+
|
|
|
190f2a |
+static bool
|
|
|
190f2a |
+check_regset (int tid, int regset_id, int regsetsize)
|
|
|
190f2a |
+{
|
|
|
190f2a |
+ void *buf = alloca (regsetsize);
|
|
|
190f2a |
+ struct iovec iov;
|
|
|
190f2a |
+
|
|
|
190f2a |
+ iov.iov_base = buf;
|
|
|
190f2a |
+ iov.iov_len = regsetsize;
|
|
|
190f2a |
+
|
|
|
190f2a |
+ if (ptrace (PTRACE_GETREGSET, tid, regset_id, &iov) >= 0
|
|
|
190f2a |
+ || errno == ENODATA)
|
|
|
190f2a |
+ return true;
|
|
|
190f2a |
+ else
|
|
|
190f2a |
+ return false;
|
|
|
190f2a |
+}
|
|
|
190f2a |
+
|
|
|
190f2a |
static void
|
|
|
190f2a |
fetch_register (struct regcache *regcache, int tid, int regno)
|
|
|
190f2a |
{
|
|
|
190f2a |
@@ -567,6 +640,24 @@ fetch_register (struct regcache *regcache, int tid, int regno)
|
|
|
190f2a |
fetch_spe_register (regcache, tid, regno);
|
|
|
190f2a |
return;
|
|
|
190f2a |
}
|
|
|
190f2a |
+ else if (regno == PPC_DSCR_REGNUM)
|
|
|
190f2a |
+ {
|
|
|
190f2a |
+ gdb_assert (tdep->ppc_dscr_regnum != -1);
|
|
|
190f2a |
+
|
|
|
190f2a |
+ fetch_regset (regcache, tid, NT_PPC_DSCR,
|
|
|
190f2a |
+ PPC_LINUX_SIZEOF_DSCRREGSET,
|
|
|
190f2a |
+ &ppc32_linux_dscrregset);
|
|
|
190f2a |
+ return;
|
|
|
190f2a |
+ }
|
|
|
190f2a |
+ else if (regno == PPC_PPR_REGNUM)
|
|
|
190f2a |
+ {
|
|
|
190f2a |
+ gdb_assert (tdep->ppc_ppr_regnum != -1);
|
|
|
190f2a |
+
|
|
|
190f2a |
+ fetch_regset (regcache, tid, NT_PPC_PPR,
|
|
|
190f2a |
+ PPC_LINUX_SIZEOF_PPRREGSET,
|
|
|
190f2a |
+ &ppc32_linux_pprregset);
|
|
|
190f2a |
+ return;
|
|
|
190f2a |
+ }
|
|
|
190f2a |
|
|
|
190f2a |
if (regaddr == -1)
|
|
|
190f2a |
{
|
|
|
190f2a |
@@ -763,6 +854,14 @@ fetch_ppc_registers (struct regcache *regcache, int tid)
|
|
|
190f2a |
fetch_vsx_registers (regcache, tid, -1);
|
|
|
190f2a |
if (tdep->ppc_ev0_upper_regnum >= 0)
|
|
|
190f2a |
fetch_spe_register (regcache, tid, -1);
|
|
|
190f2a |
+ if (tdep->ppc_ppr_regnum != -1)
|
|
|
190f2a |
+ fetch_regset (regcache, tid, NT_PPC_PPR,
|
|
|
190f2a |
+ PPC_LINUX_SIZEOF_PPRREGSET,
|
|
|
190f2a |
+ &ppc32_linux_pprregset);
|
|
|
190f2a |
+ if (tdep->ppc_dscr_regnum != -1)
|
|
|
190f2a |
+ fetch_regset (regcache, tid, NT_PPC_DSCR,
|
|
|
190f2a |
+ PPC_LINUX_SIZEOF_DSCRREGSET,
|
|
|
190f2a |
+ &ppc32_linux_dscrregset);
|
|
|
190f2a |
}
|
|
|
190f2a |
|
|
|
190f2a |
/* Fetch registers from the child process. Fetch all registers if
|
|
|
190f2a |
@@ -943,6 +1042,24 @@ store_register (const struct regcache *regcache, int tid, int regno)
|
|
|
190f2a |
store_spe_register (regcache, tid, regno);
|
|
|
190f2a |
return;
|
|
|
190f2a |
}
|
|
|
190f2a |
+ else if (regno == PPC_DSCR_REGNUM)
|
|
|
190f2a |
+ {
|
|
|
190f2a |
+ gdb_assert (tdep->ppc_dscr_regnum != -1);
|
|
|
190f2a |
+
|
|
|
190f2a |
+ store_regset (regcache, tid, regno, NT_PPC_DSCR,
|
|
|
190f2a |
+ PPC_LINUX_SIZEOF_DSCRREGSET,
|
|
|
190f2a |
+ &ppc32_linux_dscrregset);
|
|
|
190f2a |
+ return;
|
|
|
190f2a |
+ }
|
|
|
190f2a |
+ else if (regno == PPC_PPR_REGNUM)
|
|
|
190f2a |
+ {
|
|
|
190f2a |
+ gdb_assert (tdep->ppc_ppr_regnum != -1);
|
|
|
190f2a |
+
|
|
|
190f2a |
+ store_regset (regcache, tid, regno, NT_PPC_PPR,
|
|
|
190f2a |
+ PPC_LINUX_SIZEOF_PPRREGSET,
|
|
|
190f2a |
+ &ppc32_linux_pprregset);
|
|
|
190f2a |
+ return;
|
|
|
190f2a |
+ }
|
|
|
190f2a |
|
|
|
190f2a |
if (regaddr == -1)
|
|
|
190f2a |
return;
|
|
|
190f2a |
@@ -1157,6 +1274,14 @@ store_ppc_registers (const struct regcache *regcache, int tid)
|
|
|
190f2a |
store_vsx_registers (regcache, tid, -1);
|
|
|
190f2a |
if (tdep->ppc_ev0_upper_regnum >= 0)
|
|
|
190f2a |
store_spe_register (regcache, tid, -1);
|
|
|
190f2a |
+ if (tdep->ppc_ppr_regnum != -1)
|
|
|
190f2a |
+ store_regset (regcache, tid, -1, NT_PPC_PPR,
|
|
|
190f2a |
+ PPC_LINUX_SIZEOF_PPRREGSET,
|
|
|
190f2a |
+ &ppc32_linux_pprregset);
|
|
|
190f2a |
+ if (tdep->ppc_dscr_regnum != -1)
|
|
|
190f2a |
+ store_regset (regcache, tid, -1, NT_PPC_DSCR,
|
|
|
190f2a |
+ PPC_LINUX_SIZEOF_DSCRREGSET,
|
|
|
190f2a |
+ &ppc32_linux_dscrregset);
|
|
|
190f2a |
}
|
|
|
190f2a |
|
|
|
190f2a |
/* Fetch the AT_HWCAP entry from the aux vector. */
|
|
|
190f2a |
@@ -1171,6 +1296,19 @@ ppc_linux_get_hwcap (void)
|
|
|
190f2a |
return field;
|
|
|
190f2a |
}
|
|
|
190f2a |
|
|
|
190f2a |
+/* Fetch the AT_HWCAP2 entry from the aux vector. */
|
|
|
190f2a |
+
|
|
|
190f2a |
+static CORE_ADDR
|
|
|
190f2a |
+ppc_linux_get_hwcap2 (void)
|
|
|
190f2a |
+{
|
|
|
190f2a |
+ CORE_ADDR field;
|
|
|
190f2a |
+
|
|
|
190f2a |
+ if (target_auxv_search (current_top_target (), AT_HWCAP2, &field) != 1)
|
|
|
190f2a |
+ return 0;
|
|
|
190f2a |
+
|
|
|
190f2a |
+ return field;
|
|
|
190f2a |
+}
|
|
|
190f2a |
+
|
|
|
190f2a |
/* The cached DABR value, to install in new threads.
|
|
|
190f2a |
This variable is used when the PowerPC HWDEBUG ptrace
|
|
|
190f2a |
interface is not available. */
|
|
|
190f2a |
@@ -2233,6 +2371,7 @@ ppc_linux_nat_target::read_description ()
|
|
|
190f2a |
features.wordsize = ppc_linux_target_wordsize (tid);
|
|
|
190f2a |
|
|
|
190f2a |
CORE_ADDR hwcap = ppc_linux_get_hwcap ();
|
|
|
190f2a |
+ CORE_ADDR hwcap2 = ppc_linux_get_hwcap2 ();
|
|
|
190f2a |
|
|
|
190f2a |
if (have_ptrace_getsetvsxregs
|
|
|
190f2a |
&& (hwcap & PPC_FEATURE_HAS_VSX))
|
|
|
190f2a |
@@ -2267,6 +2406,11 @@ ppc_linux_nat_target::read_description ()
|
|
|
190f2a |
|
|
|
190f2a |
features.isa205 = ppc_linux_has_isa205 (hwcap);
|
|
|
190f2a |
|
|
|
190f2a |
+ if ((hwcap2 & PPC_FEATURE2_DSCR)
|
|
|
190f2a |
+ && check_regset (tid, NT_PPC_PPR, PPC_LINUX_SIZEOF_PPRREGSET)
|
|
|
190f2a |
+ && check_regset (tid, NT_PPC_DSCR, PPC_LINUX_SIZEOF_DSCRREGSET))
|
|
|
190f2a |
+ features.ppr_dscr = true;
|
|
|
190f2a |
+
|
|
|
190f2a |
return ppc_linux_match_description (features);
|
|
|
190f2a |
}
|
|
|
190f2a |
|
|
|
190f2a |
diff --git a/gdb/ppc-linux-tdep.c b/gdb/ppc-linux-tdep.c
|
|
|
190f2a |
--- a/gdb/ppc-linux-tdep.c
|
|
|
190f2a |
+++ b/gdb/ppc-linux-tdep.c
|
|
|
190f2a |
@@ -71,6 +71,7 @@
|
|
|
190f2a |
#include "features/rs6000/powerpc-isa205-32l.c"
|
|
|
190f2a |
#include "features/rs6000/powerpc-isa205-altivec32l.c"
|
|
|
190f2a |
#include "features/rs6000/powerpc-isa205-vsx32l.c"
|
|
|
190f2a |
+#include "features/rs6000/powerpc-isa205-ppr-dscr-vsx32l.c"
|
|
|
190f2a |
#include "features/rs6000/powerpc-64l.c"
|
|
|
190f2a |
#include "features/rs6000/powerpc-altivec64l.c"
|
|
|
190f2a |
#include "features/rs6000/powerpc-cell64l.c"
|
|
|
190f2a |
@@ -78,6 +79,7 @@
|
|
|
190f2a |
#include "features/rs6000/powerpc-isa205-64l.c"
|
|
|
190f2a |
#include "features/rs6000/powerpc-isa205-altivec64l.c"
|
|
|
190f2a |
#include "features/rs6000/powerpc-isa205-vsx64l.c"
|
|
|
190f2a |
+#include "features/rs6000/powerpc-isa205-ppr-dscr-vsx64l.c"
|
|
|
190f2a |
#include "features/rs6000/powerpc-e500l.c"
|
|
|
190f2a |
|
|
|
190f2a |
/* Shared library operations for PowerPC-Linux. */
|
|
|
190f2a |
@@ -547,6 +549,38 @@ static const struct regset ppc32_linux_vsxregset = {
|
|
|
190f2a |
regcache_collect_regset
|
|
|
190f2a |
};
|
|
|
190f2a |
|
|
|
190f2a |
+/* Program Priorty Register regmap. */
|
|
|
190f2a |
+
|
|
|
190f2a |
+static const struct regcache_map_entry ppc32_regmap_ppr[] =
|
|
|
190f2a |
+ {
|
|
|
190f2a |
+ { 1, PPC_PPR_REGNUM, 8 },
|
|
|
190f2a |
+ { 0 }
|
|
|
190f2a |
+ };
|
|
|
190f2a |
+
|
|
|
190f2a |
+/* Program Priorty Register regset. */
|
|
|
190f2a |
+
|
|
|
190f2a |
+const struct regset ppc32_linux_pprregset = {
|
|
|
190f2a |
+ ppc32_regmap_ppr,
|
|
|
190f2a |
+ regcache_supply_regset,
|
|
|
190f2a |
+ regcache_collect_regset
|
|
|
190f2a |
+};
|
|
|
190f2a |
+
|
|
|
190f2a |
+/* Data Stream Control Register regmap. */
|
|
|
190f2a |
+
|
|
|
190f2a |
+static const struct regcache_map_entry ppc32_regmap_dscr[] =
|
|
|
190f2a |
+ {
|
|
|
190f2a |
+ { 1, PPC_DSCR_REGNUM, 8 },
|
|
|
190f2a |
+ { 0 }
|
|
|
190f2a |
+ };
|
|
|
190f2a |
+
|
|
|
190f2a |
+/* Data Stream Control Register regset. */
|
|
|
190f2a |
+
|
|
|
190f2a |
+const struct regset ppc32_linux_dscrregset = {
|
|
|
190f2a |
+ ppc32_regmap_dscr,
|
|
|
190f2a |
+ regcache_supply_regset,
|
|
|
190f2a |
+ regcache_collect_regset
|
|
|
190f2a |
+};
|
|
|
190f2a |
+
|
|
|
190f2a |
const struct regset *
|
|
|
190f2a |
ppc_linux_gregset (int wordsize)
|
|
|
190f2a |
{
|
|
|
190f2a |
@@ -585,6 +619,8 @@ ppc_linux_iterate_over_regset_sections (struct gdbarch *gdbarch,
|
|
|
190f2a |
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
|
|
|
190f2a |
int have_altivec = tdep->ppc_vr0_regnum != -1;
|
|
|
190f2a |
int have_vsx = tdep->ppc_vsr0_upper_regnum != -1;
|
|
|
190f2a |
+ int have_ppr = tdep->ppc_ppr_regnum != -1;
|
|
|
190f2a |
+ int have_dscr = tdep->ppc_dscr_regnum != -1;
|
|
|
190f2a |
|
|
|
190f2a |
if (tdep->wordsize == 4)
|
|
|
190f2a |
cb (".reg", 48 * 4, 48 * 4, &ppc32_linux_gregset, NULL, cb_data);
|
|
|
190f2a |
@@ -603,6 +639,17 @@ ppc_linux_iterate_over_regset_sections (struct gdbarch *gdbarch,
|
|
|
190f2a |
if (have_vsx)
|
|
|
190f2a |
cb (".reg-ppc-vsx", PPC_LINUX_SIZEOF_VSXREGSET, PPC_LINUX_SIZEOF_VSXREGSET,
|
|
|
190f2a |
&ppc32_linux_vsxregset, "POWER7 VSX", cb_data);
|
|
|
190f2a |
+
|
|
|
190f2a |
+ if (have_ppr)
|
|
|
190f2a |
+ cb (".reg-ppc-ppr", PPC_LINUX_SIZEOF_PPRREGSET,
|
|
|
190f2a |
+ PPC_LINUX_SIZEOF_PPRREGSET,
|
|
|
190f2a |
+ &ppc32_linux_pprregset, "Priority Program Register", cb_data);
|
|
|
190f2a |
+
|
|
|
190f2a |
+ if (have_dscr)
|
|
|
190f2a |
+ cb (".reg-ppc-dscr", PPC_LINUX_SIZEOF_DSCRREGSET,
|
|
|
190f2a |
+ PPC_LINUX_SIZEOF_DSCRREGSET,
|
|
|
190f2a |
+ &ppc32_linux_dscrregset, "Data Stream Control Register",
|
|
|
190f2a |
+ cb_data);
|
|
|
190f2a |
}
|
|
|
190f2a |
|
|
|
190f2a |
static void
|
|
|
190f2a |
@@ -1015,6 +1062,8 @@ ppc_linux_core_read_description (struct gdbarch *gdbarch,
|
|
|
190f2a |
asection *altivec = bfd_get_section_by_name (abfd, ".reg-ppc-vmx");
|
|
|
190f2a |
asection *vsx = bfd_get_section_by_name (abfd, ".reg-ppc-vsx");
|
|
|
190f2a |
asection *section = bfd_get_section_by_name (abfd, ".reg");
|
|
|
190f2a |
+ asection *ppr = bfd_get_section_by_name (abfd, ".reg-ppc-ppr");
|
|
|
190f2a |
+ asection *dscr = bfd_get_section_by_name (abfd, ".reg-ppc-dscr");
|
|
|
190f2a |
|
|
|
190f2a |
if (! section)
|
|
|
190f2a |
return NULL;
|
|
|
190f2a |
@@ -1047,6 +1096,9 @@ ppc_linux_core_read_description (struct gdbarch *gdbarch,
|
|
|
190f2a |
|
|
|
190f2a |
features.isa205 = ppc_linux_has_isa205 (hwcap);
|
|
|
190f2a |
|
|
|
190f2a |
+ if (ppr && dscr)
|
|
|
190f2a |
+ features.ppr_dscr = true;
|
|
|
190f2a |
+
|
|
|
190f2a |
return ppc_linux_match_description (features);
|
|
|
190f2a |
}
|
|
|
190f2a |
|
|
|
190f2a |
@@ -1920,6 +1972,7 @@ _initialize_ppc_linux_tdep (void)
|
|
|
190f2a |
initialize_tdesc_powerpc_isa205_32l ();
|
|
|
190f2a |
initialize_tdesc_powerpc_isa205_altivec32l ();
|
|
|
190f2a |
initialize_tdesc_powerpc_isa205_vsx32l ();
|
|
|
190f2a |
+ initialize_tdesc_powerpc_isa205_ppr_dscr_vsx32l ();
|
|
|
190f2a |
initialize_tdesc_powerpc_64l ();
|
|
|
190f2a |
initialize_tdesc_powerpc_altivec64l ();
|
|
|
190f2a |
initialize_tdesc_powerpc_cell64l ();
|
|
|
190f2a |
@@ -1927,5 +1980,6 @@ _initialize_ppc_linux_tdep (void)
|
|
|
190f2a |
initialize_tdesc_powerpc_isa205_64l ();
|
|
|
190f2a |
initialize_tdesc_powerpc_isa205_altivec64l ();
|
|
|
190f2a |
initialize_tdesc_powerpc_isa205_vsx64l ();
|
|
|
190f2a |
+ initialize_tdesc_powerpc_isa205_ppr_dscr_vsx64l ();
|
|
|
190f2a |
initialize_tdesc_powerpc_e500l ();
|
|
|
190f2a |
}
|
|
|
190f2a |
diff --git a/gdb/ppc-linux-tdep.h b/gdb/ppc-linux-tdep.h
|
|
|
190f2a |
--- a/gdb/ppc-linux-tdep.h
|
|
|
190f2a |
+++ b/gdb/ppc-linux-tdep.h
|
|
|
190f2a |
@@ -44,4 +44,8 @@ enum {
|
|
|
190f2a |
/* Return 1 if PPC_ORIG_R3_REGNUM and PPC_TRAP_REGNUM are usable. */
|
|
|
190f2a |
int ppc_linux_trap_reg_p (struct gdbarch *gdbarch);
|
|
|
190f2a |
|
|
|
190f2a |
+/* Additional register sets, defined in ppc-linux-tdep.c. */
|
|
|
190f2a |
+extern const struct regset ppc32_linux_pprregset;
|
|
|
190f2a |
+extern const struct regset ppc32_linux_dscrregset;
|
|
|
190f2a |
+
|
|
|
190f2a |
#endif /* PPC_LINUX_TDEP_H */
|
|
|
190f2a |
diff --git a/gdb/ppc-tdep.h b/gdb/ppc-tdep.h
|
|
|
190f2a |
--- a/gdb/ppc-tdep.h
|
|
|
190f2a |
+++ b/gdb/ppc-tdep.h
|
|
|
190f2a |
@@ -253,6 +253,12 @@ struct gdbarch_tdep
|
|
|
190f2a |
int ppc_acc_regnum; /* SPE 'acc' register. */
|
|
|
190f2a |
int ppc_spefscr_regnum; /* SPE 'spefscr' register. */
|
|
|
190f2a |
|
|
|
190f2a |
+ /* Program Priority Register. */
|
|
|
190f2a |
+ int ppc_ppr_regnum;
|
|
|
190f2a |
+
|
|
|
190f2a |
+ /* Data Stream Control Register. */
|
|
|
190f2a |
+ int ppc_dscr_regnum;
|
|
|
190f2a |
+
|
|
|
190f2a |
/* Decimal 128 registers. */
|
|
|
190f2a |
int ppc_dl0_regnum; /* First Decimal128 argument register pair. */
|
|
|
190f2a |
|
|
|
190f2a |
@@ -309,6 +315,8 @@ enum {
|
|
|
190f2a |
PPC_VRSAVE_REGNUM = 139,
|
|
|
190f2a |
PPC_VSR0_UPPER_REGNUM = 140,
|
|
|
190f2a |
PPC_VSR31_UPPER_REGNUM = 171,
|
|
|
190f2a |
+ PPC_PPR_REGNUM = 172,
|
|
|
190f2a |
+ PPC_DSCR_REGNUM = 173,
|
|
|
190f2a |
PPC_NUM_REGS
|
|
|
190f2a |
};
|
|
|
190f2a |
|
|
|
190f2a |
diff --git a/gdb/regformats/rs6000/powerpc-isa205-ppr-dscr-vsx32l.dat b/gdb/regformats/rs6000/powerpc-isa205-ppr-dscr-vsx32l.dat
|
|
|
190f2a |
new file mode 100644
|
|
|
190f2a |
--- /dev/null
|
|
|
190f2a |
+++ b/gdb/regformats/rs6000/powerpc-isa205-ppr-dscr-vsx32l.dat
|
|
|
190f2a |
@@ -0,0 +1,146 @@
|
|
|
190f2a |
+# THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi :set ro:
|
|
|
190f2a |
+# Generated from: rs6000/powerpc-isa205-ppr-dscr-vsx32l.xml
|
|
|
190f2a |
+name:powerpc_isa205_ppr_dscr_vsx32l
|
|
|
190f2a |
+xmltarget:powerpc-isa205-ppr-dscr-vsx32l.xml
|
|
|
190f2a |
+expedite:r1,pc
|
|
|
190f2a |
+32:r0
|
|
|
190f2a |
+32:r1
|
|
|
190f2a |
+32:r2
|
|
|
190f2a |
+32:r3
|
|
|
190f2a |
+32:r4
|
|
|
190f2a |
+32:r5
|
|
|
190f2a |
+32:r6
|
|
|
190f2a |
+32:r7
|
|
|
190f2a |
+32:r8
|
|
|
190f2a |
+32:r9
|
|
|
190f2a |
+32:r10
|
|
|
190f2a |
+32:r11
|
|
|
190f2a |
+32:r12
|
|
|
190f2a |
+32:r13
|
|
|
190f2a |
+32:r14
|
|
|
190f2a |
+32:r15
|
|
|
190f2a |
+32:r16
|
|
|
190f2a |
+32:r17
|
|
|
190f2a |
+32:r18
|
|
|
190f2a |
+32:r19
|
|
|
190f2a |
+32:r20
|
|
|
190f2a |
+32:r21
|
|
|
190f2a |
+32:r22
|
|
|
190f2a |
+32:r23
|
|
|
190f2a |
+32:r24
|
|
|
190f2a |
+32:r25
|
|
|
190f2a |
+32:r26
|
|
|
190f2a |
+32:r27
|
|
|
190f2a |
+32:r28
|
|
|
190f2a |
+32:r29
|
|
|
190f2a |
+32:r30
|
|
|
190f2a |
+32:r31
|
|
|
190f2a |
+64:f0
|
|
|
190f2a |
+64:f1
|
|
|
190f2a |
+64:f2
|
|
|
190f2a |
+64:f3
|
|
|
190f2a |
+64:f4
|
|
|
190f2a |
+64:f5
|
|
|
190f2a |
+64:f6
|
|
|
190f2a |
+64:f7
|
|
|
190f2a |
+64:f8
|
|
|
190f2a |
+64:f9
|
|
|
190f2a |
+64:f10
|
|
|
190f2a |
+64:f11
|
|
|
190f2a |
+64:f12
|
|
|
190f2a |
+64:f13
|
|
|
190f2a |
+64:f14
|
|
|
190f2a |
+64:f15
|
|
|
190f2a |
+64:f16
|
|
|
190f2a |
+64:f17
|
|
|
190f2a |
+64:f18
|
|
|
190f2a |
+64:f19
|
|
|
190f2a |
+64:f20
|
|
|
190f2a |
+64:f21
|
|
|
190f2a |
+64:f22
|
|
|
190f2a |
+64:f23
|
|
|
190f2a |
+64:f24
|
|
|
190f2a |
+64:f25
|
|
|
190f2a |
+64:f26
|
|
|
190f2a |
+64:f27
|
|
|
190f2a |
+64:f28
|
|
|
190f2a |
+64:f29
|
|
|
190f2a |
+64:f30
|
|
|
190f2a |
+64:f31
|
|
|
190f2a |
+32:pc
|
|
|
190f2a |
+32:msr
|
|
|
190f2a |
+32:cr
|
|
|
190f2a |
+32:lr
|
|
|
190f2a |
+32:ctr
|
|
|
190f2a |
+32:xer
|
|
|
190f2a |
+64:fpscr
|
|
|
190f2a |
+32:orig_r3
|
|
|
190f2a |
+32:trap
|
|
|
190f2a |
+128:vr0
|
|
|
190f2a |
+128:vr1
|
|
|
190f2a |
+128:vr2
|
|
|
190f2a |
+128:vr3
|
|
|
190f2a |
+128:vr4
|
|
|
190f2a |
+128:vr5
|
|
|
190f2a |
+128:vr6
|
|
|
190f2a |
+128:vr7
|
|
|
190f2a |
+128:vr8
|
|
|
190f2a |
+128:vr9
|
|
|
190f2a |
+128:vr10
|
|
|
190f2a |
+128:vr11
|
|
|
190f2a |
+128:vr12
|
|
|
190f2a |
+128:vr13
|
|
|
190f2a |
+128:vr14
|
|
|
190f2a |
+128:vr15
|
|
|
190f2a |
+128:vr16
|
|
|
190f2a |
+128:vr17
|
|
|
190f2a |
+128:vr18
|
|
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190f2a |
+128:vr19
|
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|
190f2a |
+128:vr20
|
|
|
190f2a |
+128:vr21
|
|
|
190f2a |
+128:vr22
|
|
|
190f2a |
+128:vr23
|
|
|
190f2a |
+128:vr24
|
|
|
190f2a |
+128:vr25
|
|
|
190f2a |
+128:vr26
|
|
|
190f2a |
+128:vr27
|
|
|
190f2a |
+128:vr28
|
|
|
190f2a |
+128:vr29
|
|
|
190f2a |
+128:vr30
|
|
|
190f2a |
+128:vr31
|
|
|
190f2a |
+32:vscr
|
|
|
190f2a |
+32:vrsave
|
|
|
190f2a |
+64:vs0h
|
|
|
190f2a |
+64:vs1h
|
|
|
190f2a |
+64:vs2h
|
|
|
190f2a |
+64:vs3h
|
|
|
190f2a |
+64:vs4h
|
|
|
190f2a |
+64:vs5h
|
|
|
190f2a |
+64:vs6h
|
|
|
190f2a |
+64:vs7h
|
|
|
190f2a |
+64:vs8h
|
|
|
190f2a |
+64:vs9h
|
|
|
190f2a |
+64:vs10h
|
|
|
190f2a |
+64:vs11h
|
|
|
190f2a |
+64:vs12h
|
|
|
190f2a |
+64:vs13h
|
|
|
190f2a |
+64:vs14h
|
|
|
190f2a |
+64:vs15h
|
|
|
190f2a |
+64:vs16h
|
|
|
190f2a |
+64:vs17h
|
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|
190f2a |
+64:vs18h
|
|
|
190f2a |
+64:vs19h
|
|
|
190f2a |
+64:vs20h
|
|
|
190f2a |
+64:vs21h
|
|
|
190f2a |
+64:vs22h
|
|
|
190f2a |
+64:vs23h
|
|
|
190f2a |
+64:vs24h
|
|
|
190f2a |
+64:vs25h
|
|
|
190f2a |
+64:vs26h
|
|
|
190f2a |
+64:vs27h
|
|
|
190f2a |
+64:vs28h
|
|
|
190f2a |
+64:vs29h
|
|
|
190f2a |
+64:vs30h
|
|
|
190f2a |
+64:vs31h
|
|
|
190f2a |
+64:ppr
|
|
|
190f2a |
+64:dscr
|
|
|
190f2a |
diff --git a/gdb/regformats/rs6000/powerpc-isa205-ppr-dscr-vsx64l.dat b/gdb/regformats/rs6000/powerpc-isa205-ppr-dscr-vsx64l.dat
|
|
|
190f2a |
new file mode 100644
|
|
|
190f2a |
--- /dev/null
|
|
|
190f2a |
+++ b/gdb/regformats/rs6000/powerpc-isa205-ppr-dscr-vsx64l.dat
|
|
|
190f2a |
@@ -0,0 +1,146 @@
|
|
|
190f2a |
+# THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi :set ro:
|
|
|
190f2a |
+# Generated from: rs6000/powerpc-isa205-ppr-dscr-vsx64l.xml
|
|
|
190f2a |
+name:powerpc_isa205_ppr_dscr_vsx64l
|
|
|
190f2a |
+xmltarget:powerpc-isa205-ppr-dscr-vsx64l.xml
|
|
|
190f2a |
+expedite:r1,pc
|
|
|
190f2a |
+64:r0
|
|
|
190f2a |
+64:r1
|
|
|
190f2a |
+64:r2
|
|
|
190f2a |
+64:r3
|
|
|
190f2a |
+64:r4
|
|
|
190f2a |
+64:r5
|
|
|
190f2a |
+64:r6
|
|
|
190f2a |
+64:r7
|
|
|
190f2a |
+64:r8
|
|
|
190f2a |
+64:r9
|
|
|
190f2a |
+64:r10
|
|
|
190f2a |
+64:r11
|
|
|
190f2a |
+64:r12
|
|
|
190f2a |
+64:r13
|
|
|
190f2a |
+64:r14
|
|
|
190f2a |
+64:r15
|
|
|
190f2a |
+64:r16
|
|
|
190f2a |
+64:r17
|
|
|
190f2a |
+64:r18
|
|
|
190f2a |
+64:r19
|
|
|
190f2a |
+64:r20
|
|
|
190f2a |
+64:r21
|
|
|
190f2a |
+64:r22
|
|
|
190f2a |
+64:r23
|
|
|
190f2a |
+64:r24
|
|
|
190f2a |
+64:r25
|
|
|
190f2a |
+64:r26
|
|
|
190f2a |
+64:r27
|
|
|
190f2a |
+64:r28
|
|
|
190f2a |
+64:r29
|
|
|
190f2a |
+64:r30
|
|
|
190f2a |
+64:r31
|
|
|
190f2a |
+64:f0
|
|
|
190f2a |
+64:f1
|
|
|
190f2a |
+64:f2
|
|
|
190f2a |
+64:f3
|
|
|
190f2a |
+64:f4
|
|
|
190f2a |
+64:f5
|
|
|
190f2a |
+64:f6
|
|
|
190f2a |
+64:f7
|
|
|
190f2a |
+64:f8
|
|
|
190f2a |
+64:f9
|
|
|
190f2a |
+64:f10
|
|
|
190f2a |
+64:f11
|
|
|
190f2a |
+64:f12
|
|
|
190f2a |
+64:f13
|
|
|
190f2a |
+64:f14
|
|
|
190f2a |
+64:f15
|
|
|
190f2a |
+64:f16
|
|
|
190f2a |
+64:f17
|
|
|
190f2a |
+64:f18
|
|
|
190f2a |
+64:f19
|
|
|
190f2a |
+64:f20
|
|
|
190f2a |
+64:f21
|
|
|
190f2a |
+64:f22
|
|
|
190f2a |
+64:f23
|
|
|
190f2a |
+64:f24
|
|
|
190f2a |
+64:f25
|
|
|
190f2a |
+64:f26
|
|
|
190f2a |
+64:f27
|
|
|
190f2a |
+64:f28
|
|
|
190f2a |
+64:f29
|
|
|
190f2a |
+64:f30
|
|
|
190f2a |
+64:f31
|
|
|
190f2a |
+64:pc
|
|
|
190f2a |
+64:msr
|
|
|
190f2a |
+32:cr
|
|
|
190f2a |
+64:lr
|
|
|
190f2a |
+64:ctr
|
|
|
190f2a |
+32:xer
|
|
|
190f2a |
+64:fpscr
|
|
|
190f2a |
+64:orig_r3
|
|
|
190f2a |
+64:trap
|
|
|
190f2a |
+128:vr0
|
|
|
190f2a |
+128:vr1
|
|
|
190f2a |
+128:vr2
|
|
|
190f2a |
+128:vr3
|
|
|
190f2a |
+128:vr4
|
|
|
190f2a |
+128:vr5
|
|
|
190f2a |
+128:vr6
|
|
|
190f2a |
+128:vr7
|
|
|
190f2a |
+128:vr8
|
|
|
190f2a |
+128:vr9
|
|
|
190f2a |
+128:vr10
|
|
|
190f2a |
+128:vr11
|
|
|
190f2a |
+128:vr12
|
|
|
190f2a |
+128:vr13
|
|
|
190f2a |
+128:vr14
|
|
|
190f2a |
+128:vr15
|
|
|
190f2a |
+128:vr16
|
|
|
190f2a |
+128:vr17
|
|
|
190f2a |
+128:vr18
|
|
|
190f2a |
+128:vr19
|
|
|
190f2a |
+128:vr20
|
|
|
190f2a |
+128:vr21
|
|
|
190f2a |
+128:vr22
|
|
|
190f2a |
+128:vr23
|
|
|
190f2a |
+128:vr24
|
|
|
190f2a |
+128:vr25
|
|
|
190f2a |
+128:vr26
|
|
|
190f2a |
+128:vr27
|
|
|
190f2a |
+128:vr28
|
|
|
190f2a |
+128:vr29
|
|
|
190f2a |
+128:vr30
|
|
|
190f2a |
+128:vr31
|
|
|
190f2a |
+32:vscr
|
|
|
190f2a |
+32:vrsave
|
|
|
190f2a |
+64:vs0h
|
|
|
190f2a |
+64:vs1h
|
|
|
190f2a |
+64:vs2h
|
|
|
190f2a |
+64:vs3h
|
|
|
190f2a |
+64:vs4h
|
|
|
190f2a |
+64:vs5h
|
|
|
190f2a |
+64:vs6h
|
|
|
190f2a |
+64:vs7h
|
|
|
190f2a |
+64:vs8h
|
|
|
190f2a |
+64:vs9h
|
|
|
190f2a |
+64:vs10h
|
|
|
190f2a |
+64:vs11h
|
|
|
190f2a |
+64:vs12h
|
|
|
190f2a |
+64:vs13h
|
|
|
190f2a |
+64:vs14h
|
|
|
190f2a |
+64:vs15h
|
|
|
190f2a |
+64:vs16h
|
|
|
190f2a |
+64:vs17h
|
|
|
190f2a |
+64:vs18h
|
|
|
190f2a |
+64:vs19h
|
|
|
190f2a |
+64:vs20h
|
|
|
190f2a |
+64:vs21h
|
|
|
190f2a |
+64:vs22h
|
|
|
190f2a |
+64:vs23h
|
|
|
190f2a |
+64:vs24h
|
|
|
190f2a |
+64:vs25h
|
|
|
190f2a |
+64:vs26h
|
|
|
190f2a |
+64:vs27h
|
|
|
190f2a |
+64:vs28h
|
|
|
190f2a |
+64:vs29h
|
|
|
190f2a |
+64:vs30h
|
|
|
190f2a |
+64:vs31h
|
|
|
190f2a |
+64:ppr
|
|
|
190f2a |
+64:dscr
|
|
|
190f2a |
diff --git a/gdb/rs6000-tdep.c b/gdb/rs6000-tdep.c
|
|
|
190f2a |
--- a/gdb/rs6000-tdep.c
|
|
|
190f2a |
+++ b/gdb/rs6000-tdep.c
|
|
|
190f2a |
@@ -4466,6 +4466,17 @@ ppc_process_record_op31 (struct gdbarch *gdbarch, struct regcache *regcache,
|
|
|
190f2a |
case 570: /* Count Trailing Zeros Doubleword */
|
|
|
190f2a |
case 890: /* Extend-Sign Word and Shift Left Immediate (445) */
|
|
|
190f2a |
case 890 | 1: /* Extend-Sign Word and Shift Left Immediate (445) */
|
|
|
190f2a |
+
|
|
|
190f2a |
+ if (ext == 444 && tdep->ppc_ppr_regnum >= 0
|
|
|
190f2a |
+ && (PPC_RS (insn) == PPC_RA (insn))
|
|
|
190f2a |
+ && (PPC_RA (insn) == PPC_RB (insn))
|
|
|
190f2a |
+ && !PPC_RC (insn))
|
|
|
190f2a |
+ {
|
|
|
190f2a |
+ /* or Rx,Rx,Rx alters PRI in PPR. */
|
|
|
190f2a |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_ppr_regnum);
|
|
|
190f2a |
+ return 0;
|
|
|
190f2a |
+ }
|
|
|
190f2a |
+
|
|
|
190f2a |
if (PPC_RC (insn))
|
|
|
190f2a |
record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
|
|
|
190f2a |
record_full_arch_list_add_reg (regcache,
|
|
|
190f2a |
@@ -4675,6 +4686,10 @@ ppc_process_record_op31 (struct gdbarch *gdbarch, struct regcache *regcache,
|
|
|
190f2a |
case 1: /* XER */
|
|
|
190f2a |
record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum);
|
|
|
190f2a |
return 0;
|
|
|
190f2a |
+ case 3: /* DSCR */
|
|
|
190f2a |
+ if (tdep->ppc_dscr_regnum >= 0)
|
|
|
190f2a |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_dscr_regnum);
|
|
|
190f2a |
+ return 0;
|
|
|
190f2a |
case 8: /* LR */
|
|
|
190f2a |
record_full_arch_list_add_reg (regcache, tdep->ppc_lr_regnum);
|
|
|
190f2a |
return 0;
|
|
|
190f2a |
@@ -4684,6 +4699,11 @@ ppc_process_record_op31 (struct gdbarch *gdbarch, struct regcache *regcache,
|
|
|
190f2a |
case 256: /* VRSAVE */
|
|
|
190f2a |
record_full_arch_list_add_reg (regcache, tdep->ppc_vrsave_regnum);
|
|
|
190f2a |
return 0;
|
|
|
190f2a |
+ case 896:
|
|
|
190f2a |
+ case 898: /* PPR */
|
|
|
190f2a |
+ if (tdep->ppc_ppr_regnum >= 0)
|
|
|
190f2a |
+ record_full_arch_list_add_reg (regcache, tdep->ppc_ppr_regnum);
|
|
|
190f2a |
+ return 0;
|
|
|
190f2a |
}
|
|
|
190f2a |
|
|
|
190f2a |
goto UNKNOWN_OP;
|
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190f2a |
@@ -5846,7 +5866,7 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
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enum powerpc_vector_abi vector_abi = powerpc_vector_abi_global;
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enum powerpc_elf_abi elf_abi = POWERPC_ELF_AUTO;
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int have_fpu = 0, have_spe = 0, have_mq = 0, have_altivec = 0;
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- int have_dfp = 0, have_vsx = 0;
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+ int have_dfp = 0, have_vsx = 0, have_ppr = 0, have_dscr = 0;
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int tdesc_wordsize = -1;
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const struct target_desc *tdesc = info.target_desc;
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struct tdesc_arch_data *tdesc_data = NULL;
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@@ -6129,6 +6149,44 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
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}
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else
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have_spe = 0;
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+
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+ /* Program Priority Register. */
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+ feature = tdesc_find_feature (tdesc,
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+ "org.gnu.gdb.power.ppr");
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+ if (feature != NULL)
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+ {
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+ valid_p = 1;
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+ valid_p &= tdesc_numbered_register (feature, tdesc_data,
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+ PPC_PPR_REGNUM, "ppr");
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+
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+ if (!valid_p)
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+ {
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+ tdesc_data_cleanup (tdesc_data);
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+ return NULL;
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+ }
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+ have_ppr = 1;
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+ }
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+ else
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+ have_ppr = 0;
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+
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+ /* Data Stream Control Register. */
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+ feature = tdesc_find_feature (tdesc,
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+ "org.gnu.gdb.power.dscr");
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+ if (feature != NULL)
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+ {
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+ valid_p = 1;
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+ valid_p &= tdesc_numbered_register (feature, tdesc_data,
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+ PPC_DSCR_REGNUM, "dscr");
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+
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+ if (!valid_p)
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+ {
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+ tdesc_data_cleanup (tdesc_data);
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+ return NULL;
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+ }
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+ have_dscr = 1;
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+ }
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+ else
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+ have_dscr = 0;
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}
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/* If we have a 64-bit binary on a 32-bit target, complain. Also
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@@ -6323,6 +6381,8 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
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tdep->ppc_ev0_upper_regnum = have_spe ? PPC_SPE_UPPER_GP0_REGNUM : -1;
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tdep->ppc_acc_regnum = have_spe ? PPC_SPE_ACC_REGNUM : -1;
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tdep->ppc_spefscr_regnum = have_spe ? PPC_SPE_FSCR_REGNUM : -1;
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+ tdep->ppc_ppr_regnum = have_ppr ? PPC_PPR_REGNUM : -1;
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+ tdep->ppc_dscr_regnum = have_dscr ? PPC_DSCR_REGNUM : -1;
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set_gdbarch_pc_regnum (gdbarch, PPC_PC_REGNUM);
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set_gdbarch_sp_regnum (gdbarch, PPC_R0_REGNUM + 1);
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diff --git a/gdb/testsuite/gdb.arch/powerpc-ppr-dscr.c b/gdb/testsuite/gdb.arch/powerpc-ppr-dscr.c
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new file mode 100644
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--- /dev/null
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+++ b/gdb/testsuite/gdb.arch/powerpc-ppr-dscr.c
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@@ -0,0 +1,34 @@
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+/* This testcase is part of GDB, the GNU debugger.
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+
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+ Copyright (C) 2018 Free Software Foundation, Inc.
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+
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+ This program is free software; you can redistribute it and/or modify
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+ it under the terms of the GNU General Public License as published by
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+ the Free Software Foundation; either version 3 of the License, or
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+ (at your option) any later version.
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+
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+ This program is distributed in the hope that it will be useful,
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+ but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ GNU General Public License for more details.
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+
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+ You should have received a copy of the GNU General Public License
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+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
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+
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+int main (void)
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+{
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+ /* Set Load Stream Disable bit in DSCR. */
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+ unsigned long dscr = 0x20;
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+
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+ /* This is the non-privileged SPR number to access DSCR,
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+ available since isa 207. */
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+ asm volatile ("mtspr 3,%0" : : "r" (dscr));
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+
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+ /* Set PPR to low priority (010 in bits 11:13, or
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+ 0x0008000000000000). */
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+ asm volatile ("or 1,1,1");
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+ asm volatile ("nop"); // marker
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+ asm volatile ("nop");
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+
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+ return 0;
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+}
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diff --git a/gdb/testsuite/gdb.arch/powerpc-ppr-dscr.exp b/gdb/testsuite/gdb.arch/powerpc-ppr-dscr.exp
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new file mode 100644
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--- /dev/null
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+++ b/gdb/testsuite/gdb.arch/powerpc-ppr-dscr.exp
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@@ -0,0 +1,120 @@
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+# Copyright (C) 2018 Free Software Foundation, Inc.
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+
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+# This program is free software; you can redistribute it and/or modify
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+# it under the terms of the GNU General Public License as published by
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190f2a |
+# the Free Software Foundation; either version 3 of the License, or
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190f2a |
+# (at your option) any later version.
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+#
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+# This program is distributed in the hope that it will be useful,
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190f2a |
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
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190f2a |
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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190f2a |
+# GNU General Public License for more details.
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190f2a |
+#
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+# You should have received a copy of the GNU General Public License
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190f2a |
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
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+
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+# This file is part of the gdb testsuite.
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+
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+# Test access to special purpose registers PPR and DSCR. The test
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+# inferior writes to these registers, we check that GDB reads the same
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+# values, then write to the registers trough GDB, step once, and check
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+# again if we read back the same values.
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+
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+if {![istarget "powerpc*-*-linux*"]} then {
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+ verbose "Skipping PowerPC test for PPR and DSCR registers."
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+ return
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+}
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+
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+standard_testfile .c
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+
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+if {[build_executable "compile" $binfile $srcfile {debug}] == -1} {
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+ return
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+}
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+
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+proc check_register_access { regname } {
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+ global gdb_prompt
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+
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+ set test "$regname register access"
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+ gdb_test_multiple "info reg $regname" "$test" {
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+ -re "Invalid register.*\r\n$gdb_prompt $" {
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+ unsupported "$test"
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+ return 0
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+ }
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+ -re "\r\n$regname.*\r\n$gdb_prompt $" {
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+ pass "$test"
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+ return 1
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+ }
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+ }
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+ return 0
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+}
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+
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+# Do one pass to check if the instructions in our test programs are
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+# available to this processor (e.g. mtspr 3, RS for accessing DSCR).
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+proc ppr_dscr_available {} {
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+ global gdb_prompt
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+ global inferior_exited_re
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+
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+ set test "PPR/DSCR available to inferior"
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+ gdb_test_multiple "continue" "" {
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+ -re "Illegal instruction.*\r\n$gdb_prompt $" {
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+ unsupported "$test"
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+ return 0
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+ }
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+ -re "$inferior_exited_re normally.*$gdb_prompt $" {
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+ pass "$test"
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+ return 1
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+ }
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+ }
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+ return 0
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+}
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+
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+with_test_prefix "check PPR/DSCR access" {
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+ clean_restart $binfile
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+
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+ if ![runto_main] {
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+ return
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+ }
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+
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+ if {![check_register_access "ppr"]} {
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+ return
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+ }
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+
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+ if {![check_register_access "dscr"]} {
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+ return
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+ }
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+
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+ if {![ppr_dscr_available]} {
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+ return
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+ }
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+}
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+
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+# Now do the actual test
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+clean_restart $binfile
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+
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+if ![runto_main] {
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+ return
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+}
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+
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+gdb_breakpoint [gdb_get_line_number "marker"]
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+
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+gdb_continue_to_breakpoint "continue to marker"
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+
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+# At the breakpoint the inferior should have set the
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+# registers to these expected values.
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+
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+with_test_prefix "before write" {
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+ gdb_test "info reg dscr" "dscr.*0x0*20\[ \t\]+.*"
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+ gdb_test "info reg ppr" "ppr.*0x0*8000000000000\[ \t\]+.*"
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+}
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+
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+# Set Store Stream Enable in DSCR and set PPR to the medium-low
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+# priority.
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+gdb_test_no_output "set \$dscr = 0x8"
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+gdb_test_no_output "set \$ppr = 0xC000000000000"
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+
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+gdb_test "stepi" "asm.*"
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+
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+with_test_prefix "after write" {
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+ gdb_test "info reg dscr" "dscr.*0x0*8+\[ \t\]+.*"
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+ gdb_test "info reg ppr" "ppr.*0x0*\[cC\]000000000000\[ \t\]+.*"
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+}
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