commit 1e2e8c529c1cf4fcc8cbae382aa0a653d0b65da6

Author: Andreas Krebbel <krebbel@linux.vnet.ibm.com>

Date:   Fri Jan 16 12:19:21 2015 +0100

    S/390: Add support for IBM z13.

    - 32 128 bit vector registers (overlapping with the existing 16 64 bit

      floating point registers)

    - vector double instructions

    - vector integer instructions

    - scalar vector instructions (allowing to have more floating point

      registers for scalar operations)

    - vector string instructions

    gas/ChangeLog:

    	* config/tc-s390.c (struct pd_reg): Remove.

    	(pre_defined_registers): Remove.

    	(REG_NAME_CNT): Remove.

    	(reg_name_search): Calculate the register number instead of doing

    	a lookup.

    	(register_name, tc_s390_regname_to_dw2regnum): Adopt to the new

    	reg_name_search signature.

    	(s390_parse_cpu): Support the new arch string z13.

    	(s390_insert_operand): Support for vector registers with the extra

    	field for the fifth bit of each vector register operand.

    	(md_gather_operand): Adjust to the new handling of optional

    	parameters.

    	* doc/as.texinfo: Document the z13 cpu string.

    gas/testsuite/ChangeLog:

    	* gas/s390/esa-g5.d: Add a variant without the optional operand.

    	* gas/s390/esa-g5.s: Likewise.

    	* gas/s390/esa-z9-109.d: Likewise.

    	* gas/s390/esa-z9-109.s: Likewise.

    	* gas/s390/zarch-z9-109.d: Likewise.

    	* gas/s390/zarch-z9-109.s: Likewise.

    	* gas/s390/zarch-z10.d: For variants with a zero optional argument

    	it is not dumped by objdump anymore.

    	* gas/s390/zarch-zEC12.d: Likewise.

    	* gas/s390/zarch-z13.d: New file.

    	* gas/s390/zarch-z13.s: New file.

    	* gas/s390/s390.exp: Run the test for the z13 files.

    include/opcode/ChangeLog:

    	* s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13.

    ld/testsuite/ChangeLog:

    	* ld-s390/tlsbin.dd: The nopr register operand is optional and not

    	printed if 0 anymore.

    opcodes/ChangeLog:

    	* s390-dis.c (s390_extract_operand): Support vector register

    	operands.

    	(s390_print_insn_with_opcode): Support new operands types and add

    	new handling of optional operands.

    	* s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove

    	and include opcode/s390.h instead.

    	(struct op_struct): New field `flags'.

    	(insertOpcode, insertExpandedMnemonic): New parameter `flags'.

    	(dumpTable): Dump flags.

    	(main): Parse flags from the s390-opc.txt file.  Add z13 as cpu

    	string.

    	* s390-opc.c: Add new operands types, instruction formats, and

    	instruction masks.

    	(s390_opformats): Add new formats for .insn.

    	* s390-opc.txt: Add new instructions.

### a/include/opcode/ChangeLog

### b/include/opcode/ChangeLog

## -1,3 +1,7 @@

+2015-01-16  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

+

+	* s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13.

+

 2015-01-01  Alan Modra  <amodra@gmail.com>

 	Update year range in copyright notice of all files.

--- a/include/opcode/s390.h

+++ b/include/opcode/s390.h

@@ -41,9 +41,13 @@ enum s390_opcode_cpu_val

     S390_OPCODE_Z10,

     S390_OPCODE_Z196,

     S390_OPCODE_ZEC12,

+    S390_OPCODE_Z13,

     S390_OPCODE_MAXCPU

   };

+/* Instruction specific flags.  */

+#define S390_INSTR_FLAG_OPTPARM 0x1

+

 /* The opcode table is an array of struct s390_opcode.  */

 struct s390_opcode

@@ -74,6 +78,9 @@ struct s390_opcode

     /* First cpu this opcode is available for.  */

     enum s390_opcode_cpu_val min_cpu;

+

+    /* Instruction specific flags.  */

+    unsigned int flags;

   };

 /* The table itself is sorted by major opcode number, and is otherwise

@@ -86,7 +93,7 @@ extern const int                s390_num_opcodes;

 extern const struct s390_opcode s390_opformats[];

 extern const int                s390_num_opformats;

-/* Values defined for the flags field of a struct powerpc_opcode.  */

+/* Values defined for the flags field of a struct s390_opcode.  */

 /* The operands table is an array of struct s390_operand.  */

@@ -103,7 +110,7 @@ struct s390_operand

   };

 /* Elements in the table are retrieved by indexing with values from

-   the operands field of the powerpc_opcodes table.  */

+   the operands field of the s390_opcodes table.  */

 extern const struct s390_operand s390_operands[];

@@ -151,4 +158,14 @@ extern const struct s390_operand s390_operands[];

 /* The operand needs to be a valid GP or FP register pair.  */

 #define S390_OPERAND_REG_PAIR 0x800

-	#endif /* S390_H */

+/* This operand names a vector register.  The disassembler uses this

+   to print register names with a leading 'v'.  */

+#define S390_OPERAND_VR 0x1000

+

+#define S390_OPERAND_CP16 0x2000

+

+#define S390_OPERAND_OR1 0x4000

+#define S390_OPERAND_OR2 0x8000

+#define S390_OPERAND_OR8 0x10000

+

+#endif /* S390_H */

--- a/opcodes/s390-dis.c

+++ b/opcodes/s390-dis.c

@@ -107,6 +107,7 @@ s390_extract_operand (const bfd_byte *insn,

   union operand_value ret;

   unsigned int val;

   int bits;

+  const bfd_byte *orig_insn = insn;

   /* Extract fragments of the operand byte for byte.  */

   insn += operand->shift / 8;

@@ -140,6 +141,16 @@ s390_extract_operand (const bfd_byte *insn,

   else if (operand->flags & S390_OPERAND_LENGTH)

     /* Length x in an instruction has real length x + 1.  */

     ret.u = val + 1;

+

+  else if (operand->flags & S390_OPERAND_VR)

+    {

+      /* Extract the extra bits for a vector register operand stored

+	 in the RXB field.  */

+      unsigned vr = operand->shift == 32 ? 3

+	: (unsigned) operand->shift / 4 - 2;

+

+      ret.u = val | ((orig_insn[4] & (1 << (3 - vr))) << (vr + 1));

+    }

   else

     ret.u = val;

@@ -178,22 +189,45 @@ s390_print_insn_with_opcode (bfd_vma memaddr,

 	  continue;

 	}

-      info->fprintf_func (info->stream, "%c", separator);

+      /* For instructions with a last optional operand don't print it

+	 if zero.  */

+      if ((opcode->flags & S390_INSTR_FLAG_OPTPARM)

+	  && val.u == 0

+	  && opindex[1] == 0)

+	break;

       if (flags & S390_OPERAND_GPR)

-	info->fprintf_func (info->stream, "%%r%u", val.u);

+	info->fprintf_func (info->stream, "%c%%r%u", separator, val.u);

       else if (flags & S390_OPERAND_FPR)

-	info->fprintf_func (info->stream, "%%f%u", val.u);

+	info->fprintf_func (info->stream, "%c%%f%u", separator, val.u);

+      else if (flags & S390_OPERAND_VR)

+	info->fprintf_func (info->stream, "%c%%v%i", separator, val.u);

       else if (flags & S390_OPERAND_AR)

-	info->fprintf_func (info->stream, "%%a%u", val.u);

+	info->fprintf_func (info->stream, "%c%%a%u", separator, val.u);

       else if (flags & S390_OPERAND_CR)

-	info->fprintf_func (info->stream, "%%c%u", val.u);

+	info->fprintf_func (info->stream, "%c%%c%u", separator, val.u);

       else if (flags & S390_OPERAND_PCREL)

-	info->print_address_func (memaddr + val.i + val.i, info);

+	{

+	  info->fprintf_func (info->stream, "%c", separator);

+	  info->print_address_func (memaddr + val.i + val.i, info);

+	}

       else if (flags & S390_OPERAND_SIGNED)

-	info->fprintf_func (info->stream, "%i", val.i);

+	info->fprintf_func (info->stream, "%c%i", separator, val.i);

       else

-	info->fprintf_func (info->stream, "%u", val.u);

+	{

+	  if (flags & S390_OPERAND_OR1)

+	    val.u &= ~1;

+	  if (flags & S390_OPERAND_OR2)

+	    val.u &= ~2;

+	  if (flags & S390_OPERAND_OR8)

+	    val.u &= ~8;

+

+	  if ((opcode->flags & S390_INSTR_FLAG_OPTPARM)

+	      && val.u == 0

+	      && opindex[1] == 0)

+	    break;

+	  info->fprintf_func (info->stream, "%c%u", separator, val.u);

+	}

       if (flags & S390_OPERAND_DISP)

 	separator = '(';

--- a/opcodes/s390-mkopc.c

+++ b/opcodes/s390-mkopc.c

@@ -22,26 +22,7 @@

 #include <stdio.h>

 #include <stdlib.h>

 #include <string.h>

-

-/* Taken from opcodes/s390.h */

-enum s390_opcode_mode_val

-  {

-    S390_OPCODE_ESA = 0,

-    S390_OPCODE_ZARCH

-  };

-

-enum s390_opcode_cpu_val

-  {

-    S390_OPCODE_G5 = 0,

-    S390_OPCODE_G6,

-    S390_OPCODE_Z900,

-    S390_OPCODE_Z990,

-    S390_OPCODE_Z9_109,

-    S390_OPCODE_Z9_EC,

-    S390_OPCODE_Z10,

-    S390_OPCODE_Z196,

-    S390_OPCODE_ZEC12

-  };

+#include "opcode/s390.h"

 struct op_struct

   {

@@ -50,6 +31,7 @@ struct op_struct

     char  format[16];

     int   mode_bits;

     int   min_cpu;

+    int   flags;

     unsigned long long sort_value;

     int   no_nibbles;

@@ -71,7 +53,7 @@ createTable (void)

 static void

 insertOpcode (char *opcode, char *mnemonic, char *format,

-	      int min_cpu, int mode_bits)

+	      int min_cpu, int mode_bits, int flags)

 {

   char *str;

   unsigned long long sort_value;

@@ -115,6 +97,7 @@ insertOpcode (char *opcode, char *mnemonic, char *format,

   op_array[ix].no_nibbles = no_nibbles;

   op_array[ix].min_cpu = min_cpu;

   op_array[ix].mode_bits = mode_bits;

+  op_array[ix].flags = flags;

   no_ops++;

 }

@@ -176,7 +159,7 @@ const struct s390_cond_ext_format s390_crb_extensions[NUM_CRB_EXTENSIONS] =

 static void

 insertExpandedMnemonic (char *opcode, char *mnemonic, char *format,

-			int min_cpu, int mode_bits)

+			int min_cpu, int mode_bits, int flags)

 {

   char *tag;

   char prefix[15];

@@ -189,7 +172,7 @@ insertExpandedMnemonic (char *opcode, char *mnemonic, char *format,

   if (!(tag = strpbrk (mnemonic, "*$")))

     {

-      insertOpcode (opcode, mnemonic, format, min_cpu, mode_bits);

+      insertOpcode (opcode, mnemonic, format, min_cpu, mode_bits, flags);

       return;

     }

@@ -268,7 +251,7 @@ insertExpandedMnemonic (char *opcode, char *mnemonic, char *format,

       opcode[mask_start] = ext_table[i].nibble;

       strcat (new_mnemonic, ext_table[i].extension);

       strcat (new_mnemonic, suffix);

-      insertOpcode (opcode, new_mnemonic, format, min_cpu, mode_bits);

+      insertOpcode (opcode, new_mnemonic, format, min_cpu, mode_bits, flags);

     }

   return;

@@ -286,7 +269,10 @@ static const char file_header[] =

   "     which bits in the actual opcode must match OPCODE.\n"

   "   OPERANDS is the list of operands.\n\n"

   "   The disassembler reads the table in order and prints the first\n"

-  "   instruction which matches.  */\n\n"

+  "   instruction which matches.\n"

+  "   MODE_BITS - zarch or esa\n"

+  "   MIN_CPU - number of the min cpu level required\n"

+  "   FLAGS - instruction flags.  */\n\n"

   "const struct s390_opcode s390_opcodes[] =\n  {\n";

 /* `dumpTable': write opcode table.  */

@@ -311,7 +297,8 @@ dumpTable (void)

       printf ("MASK_%s, INSTR_%s, ",

 	      op_array[ix].format, op_array[ix].format);

       printf ("%i, ", op_array[ix].mode_bits);

-      printf ("%i}", op_array[ix].min_cpu);

+      printf ("%i, ", op_array[ix].min_cpu);

+      printf ("%i}", op_array[ix].flags);

       if (ix < no_ops-1)

 	printf (",\n");

       else

@@ -339,67 +326,91 @@ main (void)

       char  description[80];

       char  cpu_string[16];

       char  modes_string[16];

+      char  flags_string[80];

       int   min_cpu;

       int   mode_bits;

+      int   flag_bits;

+      int   num_matched;

       char  *str;

       if (currentLine[0] == '#' || currentLine[0] == '\n')

         continue;

       memset (opcode, 0, 8);

-      if (sscanf (currentLine, "%15s %15s %15s \"%79[^\"]\" %15s %15s",

-		  opcode, mnemonic, format, description,

-		  cpu_string, modes_string) == 6)

+      num_matched =

+	sscanf (currentLine, "%15s %15s %15s \"%79[^\"]\" %15s %15s %79[^\n]",

+		opcode, mnemonic, format, description,

+		cpu_string, modes_string, flags_string);

+      if (num_matched != 6 && num_matched != 7)

 	{

-	  if (strcmp (cpu_string, "g5") == 0)

-	    min_cpu = S390_OPCODE_G5;

-	  else if (strcmp (cpu_string, "g6") == 0)

-	    min_cpu = S390_OPCODE_G6;

-	  else if (strcmp (cpu_string, "z900") == 0)

-	    min_cpu = S390_OPCODE_Z900;

-	  else if (strcmp (cpu_string, "z990") == 0)

-	    min_cpu = S390_OPCODE_Z990;

-	  else if (strcmp (cpu_string, "z9-109") == 0)

-	    min_cpu = S390_OPCODE_Z9_109;

-	  else if (strcmp (cpu_string, "z9-ec") == 0)

-	    min_cpu = S390_OPCODE_Z9_EC;

-	  else if (strcmp (cpu_string, "z10") == 0)

-	    min_cpu = S390_OPCODE_Z10;

-	  else if (strcmp (cpu_string, "z196") == 0)

-	    min_cpu = S390_OPCODE_Z196;

-	  else if (strcmp (cpu_string, "zEC12") == 0)

-	    min_cpu = S390_OPCODE_ZEC12;

-	  else {

-	    fprintf (stderr, "Couldn't parse cpu string %s\n", cpu_string);

-	    exit (1);

-	  }

+	  fprintf (stderr, "Couldn't scan line %s\n", currentLine);

+	  exit (1);

+	}

-	  str = modes_string;

-	  mode_bits = 0;

+      if (strcmp (cpu_string, "g5") == 0)

+	min_cpu = S390_OPCODE_G5;

+      else if (strcmp (cpu_string, "g6") == 0)

+	min_cpu = S390_OPCODE_G6;

+      else if (strcmp (cpu_string, "z900") == 0)

+	min_cpu = S390_OPCODE_Z900;

+      else if (strcmp (cpu_string, "z990") == 0)

+	min_cpu = S390_OPCODE_Z990;

+      else if (strcmp (cpu_string, "z9-109") == 0)

+	min_cpu = S390_OPCODE_Z9_109;

+      else if (strcmp (cpu_string, "z9-ec") == 0)

+	min_cpu = S390_OPCODE_Z9_EC;

+      else if (strcmp (cpu_string, "z10") == 0)

+	min_cpu = S390_OPCODE_Z10;

+      else if (strcmp (cpu_string, "z196") == 0)

+	min_cpu = S390_OPCODE_Z196;

+      else if (strcmp (cpu_string, "zEC12") == 0)

+	min_cpu = S390_OPCODE_ZEC12;

+      else if (strcmp (cpu_string, "z13") == 0)

+	min_cpu = S390_OPCODE_Z13;

+      else {

+	fprintf (stderr, "Couldn't parse cpu string %s\n", cpu_string);

+	exit (1);

+      }

+

+      str = modes_string;

+      mode_bits = 0;

+      do {

+	if (strncmp (str, "esa", 3) == 0

+	    && (str[3] == 0 || str[3] == ',')) {

+	  mode_bits |= 1 << S390_OPCODE_ESA;

+	  str += 3;

+	} else if (strncmp (str, "zarch", 5) == 0

+		   && (str[5] == 0 || str[5] == ',')) {

+	  mode_bits |= 1 << S390_OPCODE_ZARCH;

+	  str += 5;

+	} else {

+	  fprintf (stderr, "Couldn't parse modes string %s\n",

+		   modes_string);

+	  exit (1);

+	}

+	if (*str == ',')

+	  str++;

+      } while (*str != 0);

+

+      flag_bits = 0;

+

+      if (num_matched == 7)

+	{

+	  str = flags_string;

 	  do {

-	    if (strncmp (str, "esa", 3) == 0

-		&& (str[3] == 0 || str[3] == ',')) {

-	      mode_bits |= 1 << S390_OPCODE_ESA;

-	      str += 3;

-	    } else if (strncmp (str, "zarch", 5) == 0

-		       && (str[5] == 0 || str[5] == ',')) {

-	      mode_bits |= 1 << S390_OPCODE_ZARCH;

-	      str += 5;

+	    if (strncmp (str, "optparm", 7) == 0

+		&& (str[7] == 0 || str[7] == ',')) {

+	      flag_bits |= S390_INSTR_FLAG_OPTPARM;

+	      str += 7;

 	    } else {

-	      fprintf (stderr, "Couldn't parse modes string %s\n",

-		       modes_string);

+	      fprintf (stderr, "Couldn't parse flags string %s\n",

+		       flags_string);

 	      exit (1);

 	    }

 	    if (*str == ',')

 	      str++;

 	  } while (*str != 0);

-

-	  insertExpandedMnemonic (opcode, mnemonic, format, min_cpu, mode_bits);

-	}

-      else

-	{

-	  fprintf (stderr, "Couldn't scan line %s\n", currentLine);

-	  exit (1);

 	}

+      insertExpandedMnemonic (opcode, mnemonic, format, min_cpu, mode_bits, flag_bits);

     }

   dumpTable ();

--- a/opcodes/s390-opc.c

+++ b/opcodes/s390-opc.c

@@ -44,197 +44,210 @@ const struct s390_operand s390_operands[] =

 /* General purpose register operands.  */

-#define R_8    1                  /* GPR starting at position 8 */

+#define R_8         1             /* GPR starting at position 8 */

   { 4, 8, S390_OPERAND_GPR },

-#define R_12   2                  /* GPR starting at position 12 */

+#define R_12        2             /* GPR starting at position 12 */

   { 4, 12, S390_OPERAND_GPR },

-#define RO_12  3                 /* optional GPR starting at position 12 */

-  { 4, 12, S390_OPERAND_GPR | S390_OPERAND_OPTIONAL },

-#define R_16   4                  /* GPR starting at position 16 */

+#define R_16        3             /* GPR starting at position 16 */

   { 4, 16, S390_OPERAND_GPR },

-#define R_20   5                  /* GPR starting at position 20 */

+#define R_20        4             /* GPR starting at position 20 */

   { 4, 20, S390_OPERAND_GPR },

-#define R_24   6                  /* GPR starting at position 24 */

+#define R_24        5             /* GPR starting at position 24 */

   { 4, 24, S390_OPERAND_GPR },

-#define R_28   7                  /* GPR starting at position 28 */

+#define R_28        6             /* GPR starting at position 28 */

   { 4, 28, S390_OPERAND_GPR },

-#define RO_28  8                  /* optional GPR starting at position 28 */

-  { 4, 28, (S390_OPERAND_GPR | S390_OPERAND_OPTIONAL) },

-#define R_32   9                  /* GPR starting at position 32 */

+#define R_32        7             /* GPR starting at position 32 */

   { 4, 32, S390_OPERAND_GPR },

 /* General purpose register pair operands.  */

-#define RE_8    10                  /* GPR starting at position 8 */

+#define RE_8        8             /* GPR starting at position 8 */

   { 4, 8, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR },

-#define RE_12   11                  /* GPR starting at position 12 */

+#define RE_12       9             /* GPR starting at position 12 */

   { 4, 12, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR },

-#define RE_16   12                  /* GPR starting at position 16 */

+#define RE_16       10            /* GPR starting at position 16 */

   { 4, 16, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR },

-#define RE_20   13                  /* GPR starting at position 20 */

+#define RE_20       11            /* GPR starting at position 20 */

   { 4, 20, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR },

-#define RE_24   14                  /* GPR starting at position 24 */

+#define RE_24       12            /* GPR starting at position 24 */

   { 4, 24, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR },

-#define RE_28   15                  /* GPR starting at position 28 */

+#define RE_28       13            /* GPR starting at position 28 */

   { 4, 28, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR },

-#define RE_32   16                  /* GPR starting at position 32 */

+#define RE_32       14            /* GPR starting at position 32 */

   { 4, 32, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR },

-

 /* Floating point register operands.  */

-#define F_8    17                 /* FPR starting at position 8 */

+#define F_8         15            /* FPR starting at position 8 */

   { 4, 8, S390_OPERAND_FPR },

-#define F_12   18                 /* FPR starting at position 12 */

+#define F_12        16            /* FPR starting at position 12 */

   { 4, 12, S390_OPERAND_FPR },

-#define F_16   19                 /* FPR starting at position 16 */

+#define F_16        17            /* FPR starting at position 16 */

   { 4, 16, S390_OPERAND_FPR },

-#define F_20   20                 /* FPR starting at position 16 */

+#define F_20        18            /* FPR starting at position 16 */

   { 4, 16, S390_OPERAND_FPR },

-#define F_24   21                 /* FPR starting at position 24 */

+#define F_24        19            /* FPR starting at position 24 */

   { 4, 24, S390_OPERAND_FPR },

-#define F_28   22                 /* FPR starting at position 28 */

+#define F_28        20            /* FPR starting at position 28 */

   { 4, 28, S390_OPERAND_FPR },

-#define F_32   23                 /* FPR starting at position 32 */

+#define F_32        21            /* FPR starting at position 32 */

   { 4, 32, S390_OPERAND_FPR },

 /* Floating point register pair operands.  */

-#define FE_8    24                 /* FPR starting at position 8 */

+#define FE_8        22            /* FPR starting at position 8 */

   { 4, 8, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR },

-#define FE_12   25                 /* FPR starting at position 12 */

+#define FE_12       23            /* FPR starting at position 12 */

   { 4, 12, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR },

-#define FE_16   26                 /* FPR starting at position 16 */

+#define FE_16       24            /* FPR starting at position 16 */

   { 4, 16, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR },

-#define FE_20   27                 /* FPR starting at position 16 */

+#define FE_20       25            /* FPR starting at position 16 */

   { 4, 16, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR },

-#define FE_24   28                 /* FPR starting at position 24 */

+#define FE_24       26            /* FPR starting at position 24 */

   { 4, 24, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR },

-#define FE_28   29                 /* FPR starting at position 28 */

+#define FE_28       27            /* FPR starting at position 28 */

   { 4, 28, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR },

-#define FE_32   30                 /* FPR starting at position 32 */

+#define FE_32       28            /* FPR starting at position 32 */

   { 4, 32, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR },

+/* Vector register operands.  */

+

+/* For each of these operands and additional bit in the RXB operand is

+   needed.  */

+

+#define V_8         29            /* Vector reg. starting at position 8 */

+  { 4, 8, S390_OPERAND_VR },

+#define V_12        30            /* Vector reg. starting at position 12 */

+  { 4, 12, S390_OPERAND_VR },

+#define V_CP16_12   31            /* Vector reg. starting at position 12 */

+  { 4, 12, S390_OPERAND_VR | S390_OPERAND_CP16 }, /* with a copy at pos 16 */

+#define V_16        32            /* Vector reg. starting at position 16 */

+  { 4, 16, S390_OPERAND_VR },

+#define V_32        33            /* Vector reg. starting at position 32 */

+  { 4, 32, S390_OPERAND_VR },

 /* Access register operands.  */

-#define A_8    31                 /* Access reg. starting at position 8 */

+#define A_8         34            /* Access reg. starting at position 8 */

   { 4, 8, S390_OPERAND_AR },

-#define A_12   32                 /* Access reg. starting at position 12 */

+#define A_12        35            /* Access reg. starting at position 12 */

   { 4, 12, S390_OPERAND_AR },

-#define A_24   33                 /* Access reg. starting at position 24 */

+#define A_24        36            /* Access reg. starting at position 24 */

   { 4, 24, S390_OPERAND_AR },

-#define A_28   34                 /* Access reg. starting at position 28 */

+#define A_28        37            /* Access reg. starting at position 28 */

   { 4, 28, S390_OPERAND_AR },

 /* Control register operands.  */

-#define C_8    35                 /* Control reg. starting at position 8 */

+#define C_8         38            /* Control reg. starting at position 8 */

   { 4, 8, S390_OPERAND_CR },

-#define C_12   36                 /* Control reg. starting at position 12 */

+#define C_12        39            /* Control reg. starting at position 12 */

   { 4, 12, S390_OPERAND_CR },

 /* Base register operands.  */

-#define B_16   37                 /* Base register starting at position 16 */

+#define B_16        40            /* Base register starting at position 16 */

   { 4, 16, S390_OPERAND_BASE | S390_OPERAND_GPR },

-#define B_32   38                 /* Base register starting at position 32 */

+#define B_32        41            /* Base register starting at position 32 */

   { 4, 32, S390_OPERAND_BASE | S390_OPERAND_GPR },

-#define X_12   39                 /* Index register starting at position 12 */

+#define X_12        42            /* Index register starting at position 12 */

   { 4, 12, S390_OPERAND_INDEX | S390_OPERAND_GPR },

+#define VX_12       43     /* Vector index register starting at position 12 */

+  { 4, 12, S390_OPERAND_INDEX | S390_OPERAND_VR },

+

 /* Address displacement operands.  */

-#define D_20   40                 /* Displacement starting at position 20 */

+#define D_20        44            /* Displacement starting at position 20 */

   { 12, 20, S390_OPERAND_DISP },

-#define DO_20  41                 /* optional Displ. starting at position 20 */

-  { 12, 20, S390_OPERAND_DISP | S390_OPERAND_OPTIONAL },

-#define D_36   42                 /* Displacement starting at position 36 */

+#define D_36        45            /* Displacement starting at position 36 */

   { 12, 36, S390_OPERAND_DISP },

-#define D20_20 43		  /* 20 bit displacement starting at 20 */

+#define D20_20      46		  /* 20 bit displacement starting at 20 */

   { 20, 20, S390_OPERAND_DISP | S390_OPERAND_SIGNED },

 /* Length operands.  */

-#define L4_8   44                 /* 4 bit length starting at position 8 */

+#define L4_8        47            /* 4 bit length starting at position 8 */

   { 4, 8, S390_OPERAND_LENGTH },

-#define L4_12  45                 /* 4 bit length starting at position 12 */

+#define L4_12       48            /* 4 bit length starting at position 12 */

   { 4, 12, S390_OPERAND_LENGTH },

-#define L8_8   46                 /* 8 bit length starting at position 8 */

+#define L8_8        49            /* 8 bit length starting at position 8 */

   { 8, 8, S390_OPERAND_LENGTH },

 /* Signed immediate operands.  */

-#define I8_8   47		  /* 8 bit signed value starting at 8 */

+#define I8_8        50		  /* 8 bit signed value starting at 8 */

   { 8, 8, S390_OPERAND_SIGNED },

-#define I8_32  48		  /* 8 bit signed value starting at 32 */

+#define I8_32       51		  /* 8 bit signed value starting at 32 */

   { 8, 32, S390_OPERAND_SIGNED },

-#define I12_12 49		  /* 12 bit signed value starting at 12 */

+#define I12_12      52		  /* 12 bit signed value starting at 12 */

   { 12, 12, S390_OPERAND_SIGNED },

-#define I16_16 50                 /* 16 bit signed value starting at 16 */

+#define I16_16      53            /* 16 bit signed value starting at 16 */

   { 16, 16, S390_OPERAND_SIGNED },

-#define I16_32 51                 /* 16 bit signed value starting at 32 */

+#define I16_32      54            /* 16 bit signed value starting at 32 */

   { 16, 32, S390_OPERAND_SIGNED },

-#define I24_24 52		  /* 24 bit signed value starting at 24 */

+#define I24_24      55		  /* 24 bit signed value starting at 24 */

   { 24, 24, S390_OPERAND_SIGNED },

-#define I32_16 53		  /* 32 bit signed value starting at 16 */

+#define I32_16      56		  /* 32 bit signed value starting at 16 */

   { 32, 16, S390_OPERAND_SIGNED },

 /* Unsigned immediate operands.  */

-#define U4_8   54                 /* 4 bit unsigned value starting at 8 */

+#define U4_8        57            /* 4 bit unsigned value starting at 8 */

   { 4, 8, 0 },

-#define U4_12  55                 /* 4 bit unsigned value starting at 12 */

+#define U4_12       58            /* 4 bit unsigned value starting at 12 */

   { 4, 12, 0 },

-#define U4_16  56                 /* 4 bit unsigned value starting at 16 */

+#define U4_16       59            /* 4 bit unsigned value starting at 16 */

   { 4, 16, 0 },

-#define U4_20  57                 /* 4 bit unsigned value starting at 20 */

+#define U4_20       60            /* 4 bit unsigned value starting at 20 */

   { 4, 20, 0 },

-#define U4_24  58                 /* 4 bit unsigned value starting at 24 */

+#define U4_24       61            /* 4 bit unsigned value starting at 24 */

   { 4, 24, 0 },

-#define U4_28  59                 /* 4 bit unsigned value starting at 28 */

+#define U4_OR1_24   62            /* 4 bit unsigned value starting at 24 */

+  { 4, 24, S390_OPERAND_OR1 },

+#define U4_OR2_24   63            /* 4 bit unsigned value starting at 24 */

+  { 4, 24, S390_OPERAND_OR2 },

+#define U4_OR3_24   64            /* 4 bit unsigned value starting at 24 */

+  { 4, 24, S390_OPERAND_OR1 | S390_OPERAND_OR2 },

+#define U4_28       65            /* 4 bit unsigned value starting at 28 */

   { 4, 28, 0 },

-#define U4_32  60                 /* 4 bit unsigned value starting at 32 */

+#define U4_OR8_28   66

+  { 4, 28, S390_OPERAND_OR8 },

+#define U4_32       67            /* 4 bit unsigned value starting at 32 */

   { 4, 32, 0 },

-#define U4_36  61                 /* 4 bit unsigned value starting at 36 */

+#define U4_36       68            /* 4 bit unsigned value starting at 36 */

   { 4, 36, 0 },

-#define U8_8   62                 /* 8 bit unsigned value starting at 8 */

+#define U8_8        69            /* 8 bit unsigned value starting at 8 */

   { 8, 8, 0 },

-#define U8_16  63                 /* 8 bit unsigned value starting at 16 */

+#define U8_16       70            /* 8 bit unsigned value starting at 16 */

   { 8, 16, 0 },

-#define U8_24  64                 /* 8 bit unsigned value starting at 24 */

+#define U8_24       71            /* 8 bit unsigned value starting at 24 */

   { 8, 24, 0 },