|
 |
0b42f8 |
commit fb798c50b2c896195fb94af229dfbcc52babdfea
|
|
|
0b42f8 |
Author: Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
|
|
|
0b42f8 |
Date: Fri Jul 5 09:45:44 2013 +0000
|
|
|
0b42f8 |
|
|
|
0b42f8 |
2013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
|
|
|
0b42f8 |
opcodes/
|
|
|
0b42f8 |
* s390-opc.c (J12_12, J24_24): New macros.
|
|
|
0b42f8 |
(INSTR_MII_UPI): Rename to INSTR_MII_UPP.
|
|
|
0b42f8 |
(MASK_MII_UPI): Rename to MASK_MII_UPP.
|
|
|
0b42f8 |
* s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
|
|
|
0b42f8 |
|
|
|
0b42f8 |
include/elf/
|
|
|
0b42f8 |
* s390.h: Add new relocs R_390_PC12DBL, R_390_PLT12DBL,
|
|
|
0b42f8 |
R_390_PC24DBL, and R_390_PLT24DBL.
|
|
|
0b42f8 |
|
|
|
0b42f8 |
gas/testsuite/
|
|
|
0b42f8 |
* gas/s390/zarch-zEC12.s: Change bprp second operand and add
|
|
|
0b42f8 |
variants requiring relocations.
|
|
|
0b42f8 |
* gas/s390/zarch-zEC12.d: Likewise.
|
|
|
0b42f8 |
|
|
|
0b42f8 |
gas/
|
|
|
0b42f8 |
* config/tc-s390.c (md_gather_operands, md_apply_fix): Support new
|
|
|
0b42f8 |
relocs.
|
|
|
0b42f8 |
bfd/
|
|
|
0b42f8 |
* elf32-s390.c: Add new relocation definitions R_390_PC12DBL,
|
|
|
0b42f8 |
R_390_PLT12DBL, R_390_PC24DBL, and R_390_PLT24DBL.
|
|
|
0b42f8 |
(elf_s390_reloc_type_lookup, elf_s390_check_relocs)
|
|
|
0b42f8 |
(elf_s390_gc_sweep_hook, elf_s390_relocate_section): Support new
|
|
|
0b42f8 |
relocations.
|
|
|
0b42f8 |
* elf64-s390.c: See elf32-s390.c
|
|
|
0b42f8 |
* bfd-in2.h: Add new relocs to enum bfd_reloc_code_real.
|
|
|
0b42f8 |
* libbfd.h: Add new reloc strings.
|
|
|
0b42f8 |
|
|
|
0b42f8 |
### a/bfd/ChangeLog
|
|
|
0b42f8 |
### b/bfd/ChangeLog
|
|
|
0b42f8 |
## -1,3 +1,14 @@
|
|
|
0b42f8 |
+2013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
|
|
|
0b42f8 |
+
|
|
|
0b42f8 |
+ * elf32-s390.c: Add new relocation definitions R_390_PC12DBL,
|
|
|
0b42f8 |
+ R_390_PLT12DBL, R_390_PC24DBL, and R_390_PLT24DBL.
|
|
|
0b42f8 |
+ (elf_s390_reloc_type_lookup, elf_s390_check_relocs)
|
|
|
0b42f8 |
+ (elf_s390_gc_sweep_hook, elf_s390_relocate_section): Support new
|
|
|
0b42f8 |
+ relocations.
|
|
|
0b42f8 |
+ * elf64-s390.c: See elf32-s390.c
|
|
|
0b42f8 |
+ * bfd-in2.h: Add new relocs to enum bfd_reloc_code_real.
|
|
|
0b42f8 |
+ * libbfd.h: Add new reloc strings.
|
|
|
0b42f8 |
+
|
|
|
0b42f8 |
2013-07-03 Marcus Shawcroft <marcus.shawcroft@arm.com>
|
|
|
0b42f8 |
|
|
|
0b42f8 |
* elfnn-aarch64.c (elfNN_aarch64_final_link_relocate): Reorder case
|
|
|
0b42f8 |
--- a/bfd/bfd-in2.h
|
|
|
0b42f8 |
+++ b/bfd/bfd-in2.h
|
|
|
0b42f8 |
@@ -4332,12 +4332,24 @@ in .byte hlo8(symbol) */
|
|
|
0b42f8 |
/* 16 bit GOT offset. */
|
|
|
0b42f8 |
BFD_RELOC_390_GOT16,
|
|
|
0b42f8 |
|
|
|
0b42f8 |
+/* PC relative 12 bit shifted by 1. */
|
|
|
0b42f8 |
+ BFD_RELOC_390_PC12DBL,
|
|
|
0b42f8 |
+
|
|
|
0b42f8 |
+/* 12 bit PC rel. PLT shifted by 1. */
|
|
|
0b42f8 |
+ BFD_RELOC_390_PLT12DBL,
|
|
|
0b42f8 |
+
|
|
|
0b42f8 |
/* PC relative 16 bit shifted by 1. */
|
|
|
0b42f8 |
BFD_RELOC_390_PC16DBL,
|
|
|
0b42f8 |
|
|
|
0b42f8 |
/* 16 bit PC rel. PLT shifted by 1. */
|
|
|
0b42f8 |
BFD_RELOC_390_PLT16DBL,
|
|
|
0b42f8 |
|
|
|
0b42f8 |
+/* PC relative 24 bit shifted by 1. */
|
|
|
0b42f8 |
+ BFD_RELOC_390_PC24DBL,
|
|
|
0b42f8 |
+
|
|
|
0b42f8 |
+/* 24 bit PC rel. PLT shifted by 1. */
|
|
|
0b42f8 |
+ BFD_RELOC_390_PLT24DBL,
|
|
|
0b42f8 |
+
|
|
|
0b42f8 |
/* PC relative 32 bit shifted by 1. */
|
|
|
0b42f8 |
BFD_RELOC_390_PC32DBL,
|
|
|
0b42f8 |
|
|
|
0b42f8 |
--- a/bfd/elf32-s390.c
|
|
|
0b42f8 |
+++ b/bfd/elf32-s390.c
|
|
|
0b42f8 |
@@ -40,7 +40,7 @@ static reloc_howto_type elf_howto_table[] =
|
|
|
0b42f8 |
{
|
|
|
0b42f8 |
HOWTO (R_390_NONE, /* type */
|
|
|
0b42f8 |
0, /* rightshift */
|
|
|
0b42f8 |
- 0, /* size (0 = byte, 1 = short, 2 = long) */
|
|
|
0b42f8 |
+ 0, /* size (0 = byte, 1 = 2 byte, 2 = 4 byte) */
|
|
|
0b42f8 |
0, /* bitsize */
|
|
|
0b42f8 |
FALSE, /* pc_relative */
|
|
|
0b42f8 |
0, /* bitpos */
|
|
|
0b42f8 |
@@ -161,6 +161,14 @@ static reloc_howto_type elf_howto_table[] =
|
|
|
0b42f8 |
s390_elf_ldisp_reloc, "R_390_TLS_GOTIE20", FALSE, 0,0x0fffff00, FALSE),
|
|
|
0b42f8 |
HOWTO(R_390_IRELATIVE, 0, 2, 32, TRUE, 0, complain_overflow_bitfield,
|
|
|
0b42f8 |
bfd_elf_generic_reloc, "R_390_IRELATIVE", FALSE, 0, 0xffffffff, FALSE),
|
|
|
0b42f8 |
+ HOWTO(R_390_PC12DBL, 1, 1, 12, TRUE, 0, complain_overflow_bitfield,
|
|
|
0b42f8 |
+ bfd_elf_generic_reloc, "R_390_PC12DBL", FALSE, 0,0x00000fff, TRUE),
|
|
|
0b42f8 |
+ HOWTO(R_390_PLT12DBL, 1, 1, 12, TRUE, 0, complain_overflow_bitfield,
|
|
|
0b42f8 |
+ bfd_elf_generic_reloc, "R_390_PLT12DBL", FALSE, 0,0x00000fff, TRUE),
|
|
|
0b42f8 |
+ HOWTO(R_390_PC24DBL, 1, 2, 24, TRUE, 0, complain_overflow_bitfield,
|
|
|
0b42f8 |
+ bfd_elf_generic_reloc, "R_390_PC24DBL", FALSE, 0,0x00ffffff, TRUE),
|
|
|
0b42f8 |
+ HOWTO(R_390_PLT24DBL, 1, 2, 24, TRUE, 0, complain_overflow_bitfield,
|
|
|
0b42f8 |
+ bfd_elf_generic_reloc, "R_390_PLT24DBL", FALSE, 0,0x00ffffff, TRUE),
|
|
|
0b42f8 |
};
|
|
|
0b42f8 |
|
|
|
0b42f8 |
/* GNU extension to record C++ vtable hierarchy. */
|
|
|
0b42f8 |
@@ -211,10 +219,18 @@ elf_s390_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
|
|
|
0b42f8 |
return &elf_howto_table[(int) R_390_GOT16];
|
|
|
0b42f8 |
case BFD_RELOC_16_PCREL:
|
|
|
0b42f8 |
return &elf_howto_table[(int) R_390_PC16];
|
|
|
0b42f8 |
+ case BFD_RELOC_390_PC12DBL:
|
|
|
0b42f8 |
+ return &elf_howto_table[(int) R_390_PC12DBL];
|
|
|
0b42f8 |
+ case BFD_RELOC_390_PLT12DBL:
|
|
|
0b42f8 |
+ return &elf_howto_table[(int) R_390_PLT12DBL];
|
|
|
0b42f8 |
case BFD_RELOC_390_PC16DBL:
|
|
|
0b42f8 |
return &elf_howto_table[(int) R_390_PC16DBL];
|
|
|
0b42f8 |
case BFD_RELOC_390_PLT16DBL:
|
|
|
0b42f8 |
return &elf_howto_table[(int) R_390_PLT16DBL];
|
|
|
0b42f8 |
+ case BFD_RELOC_390_PC24DBL:
|
|
|
0b42f8 |
+ return &elf_howto_table[(int) R_390_PC24DBL];
|
|
|
0b42f8 |
+ case BFD_RELOC_390_PLT24DBL:
|
|
|
0b42f8 |
+ return &elf_howto_table[(int) R_390_PLT24DBL];
|
|
|
0b42f8 |
case BFD_RELOC_390_PC32DBL:
|
|
|
0b42f8 |
return &elf_howto_table[(int) R_390_PC32DBL];
|
|
|
0b42f8 |
case BFD_RELOC_390_PLT32DBL:
|
|
|
0b42f8 |
@@ -1107,7 +1123,9 @@ elf_s390_check_relocs (bfd *abfd,
|
|
|
0b42f8 |
are done. */
|
|
|
0b42f8 |
break;
|
|
|
0b42f8 |
|
|
|
0b42f8 |
+ case R_390_PLT12DBL:
|
|
|
0b42f8 |
case R_390_PLT16DBL:
|
|
|
0b42f8 |
+ case R_390_PLT24DBL:
|
|
|
0b42f8 |
case R_390_PLT32DBL:
|
|
|
0b42f8 |
case R_390_PLT32:
|
|
|
0b42f8 |
case R_390_PLTOFF16:
|
|
|
0b42f8 |
@@ -1242,7 +1260,9 @@ elf_s390_check_relocs (bfd *abfd,
|
|
|
0b42f8 |
case R_390_16:
|
|
|
0b42f8 |
case R_390_32:
|
|
|
0b42f8 |
case R_390_PC16:
|
|
|
0b42f8 |
+ case R_390_PC12DBL:
|
|
|
0b42f8 |
case R_390_PC16DBL:
|
|
|
0b42f8 |
+ case R_390_PC24DBL:
|
|
|
0b42f8 |
case R_390_PC32DBL:
|
|
|
0b42f8 |
case R_390_PC32:
|
|
|
0b42f8 |
if (h != NULL)
|
|
|
0b42f8 |
@@ -1287,7 +1307,9 @@ elf_s390_check_relocs (bfd *abfd,
|
|
|
0b42f8 |
if ((info->shared
|
|
|
0b42f8 |
&& (sec->flags & SEC_ALLOC) != 0
|
|
|
0b42f8 |
&& ((ELF32_R_TYPE (rel->r_info) != R_390_PC16
|
|
|
0b42f8 |
+ && ELF32_R_TYPE (rel->r_info) != R_390_PC12DBL
|
|
|
0b42f8 |
&& ELF32_R_TYPE (rel->r_info) != R_390_PC16DBL
|
|
|
0b42f8 |
+ && ELF32_R_TYPE (rel->r_info) != R_390_PC24DBL
|
|
|
0b42f8 |
&& ELF32_R_TYPE (rel->r_info) != R_390_PC32DBL
|
|
|
0b42f8 |
&& ELF32_R_TYPE (rel->r_info) != R_390_PC32)
|
|
|
0b42f8 |
|| (h != NULL
|
|
|
0b42f8 |
@@ -1364,7 +1386,9 @@ elf_s390_check_relocs (bfd *abfd,
|
|
|
0b42f8 |
|
|
|
0b42f8 |
p->count += 1;
|
|
|
0b42f8 |
if (ELF32_R_TYPE (rel->r_info) == R_390_PC16
|
|
|
0b42f8 |
+ || ELF32_R_TYPE (rel->r_info) == R_390_PC12DBL
|
|
|
0b42f8 |
|| ELF32_R_TYPE (rel->r_info) == R_390_PC16DBL
|
|
|
0b42f8 |
+ || ELF32_R_TYPE (rel->r_info) == R_390_PC24DBL
|
|
|
0b42f8 |
|| ELF32_R_TYPE (rel->r_info) == R_390_PC32DBL
|
|
|
0b42f8 |
|| ELF32_R_TYPE (rel->r_info) == R_390_PC32)
|
|
|
0b42f8 |
p->pc_count += 1;
|
|
|
0b42f8 |
@@ -1531,14 +1555,18 @@ elf_s390_gc_sweep_hook (bfd *abfd,
|
|
|
0b42f8 |
case R_390_20:
|
|
|
0b42f8 |
case R_390_32:
|
|
|
0b42f8 |
case R_390_PC16:
|
|
|
0b42f8 |
+ case R_390_PC12DBL:
|
|
|
0b42f8 |
case R_390_PC16DBL:
|
|
|
0b42f8 |
+ case R_390_PC24DBL:
|
|
|
0b42f8 |
case R_390_PC32DBL:
|
|
|
0b42f8 |
case R_390_PC32:
|
|
|
0b42f8 |
if (info->shared)
|
|
|
0b42f8 |
break;
|
|
|
0b42f8 |
/* Fall through. */
|
|
|
0b42f8 |
|
|
|
0b42f8 |
+ case R_390_PLT12DBL:
|
|
|
0b42f8 |
case R_390_PLT16DBL:
|
|
|
0b42f8 |
+ case R_390_PLT24DBL:
|
|
|
0b42f8 |
case R_390_PLT32DBL:
|
|
|
0b42f8 |
case R_390_PLT32:
|
|
|
0b42f8 |
case R_390_PLTOFF16:
|
|
|
0b42f8 |
@@ -2588,7 +2616,9 @@ elf_s390_relocate_section (bfd *output_bfd,
|
|
|
0b42f8 |
unresolved_reloc = FALSE;
|
|
|
0b42f8 |
break;
|
|
|
0b42f8 |
|
|
|
0b42f8 |
+ case R_390_PLT12DBL:
|
|
|
0b42f8 |
case R_390_PLT16DBL:
|
|
|
0b42f8 |
+ case R_390_PLT24DBL:
|
|
|
0b42f8 |
case R_390_PLT32DBL:
|
|
|
0b42f8 |
case R_390_PLT32:
|
|
|
0b42f8 |
/* Relocation is to the entry for this symbol in the
|
|
|
0b42f8 |
@@ -2651,7 +2681,9 @@ elf_s390_relocate_section (bfd *output_bfd,
|
|
|
0b42f8 |
case R_390_16:
|
|
|
0b42f8 |
case R_390_32:
|
|
|
0b42f8 |
case R_390_PC16:
|
|
|
0b42f8 |
+ case R_390_PC12DBL:
|
|
|
0b42f8 |
case R_390_PC16DBL:
|
|
|
0b42f8 |
+ case R_390_PC24DBL:
|
|
|
0b42f8 |
case R_390_PC32DBL:
|
|
|
0b42f8 |
case R_390_PC32:
|
|
|
0b42f8 |
if (h != NULL
|
|
|
0b42f8 |
@@ -2723,7 +2755,9 @@ elf_s390_relocate_section (bfd *output_bfd,
|
|
|
0b42f8 |
|| ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
|
|
|
0b42f8 |
|| h->root.type != bfd_link_hash_undefweak)
|
|
|
0b42f8 |
&& ((r_type != R_390_PC16
|
|
|
0b42f8 |
+ && r_type != R_390_PC12DBL
|
|
|
0b42f8 |
&& r_type != R_390_PC16DBL
|
|
|
0b42f8 |
+ && r_type != R_390_PC24DBL
|
|
|
0b42f8 |
&& r_type != R_390_PC32DBL
|
|
|
0b42f8 |
&& r_type != R_390_PC32)
|
|
|
0b42f8 |
|| !SYMBOL_CALLS_LOCAL (info, h)))
|
|
|
0b42f8 |
@@ -2764,7 +2798,9 @@ elf_s390_relocate_section (bfd *output_bfd,
|
|
|
0b42f8 |
else if (h != NULL
|
|
|
0b42f8 |
&& h->dynindx != -1
|
|
|
0b42f8 |
&& (r_type == R_390_PC16
|
|
|
0b42f8 |
+ || r_type == R_390_PC12DBL
|
|
|
0b42f8 |
|| r_type == R_390_PC16DBL
|
|
|
0b42f8 |
+ || r_type == R_390_PC24DBL
|
|
|
0b42f8 |
|| r_type == R_390_PC32DBL
|
|
|
0b42f8 |
|| r_type == R_390_PC32
|
|
|
0b42f8 |
|| !info->shared
|
|
|
0b42f8 |
@@ -3242,6 +3278,13 @@ elf_s390_relocate_section (bfd *output_bfd,
|
|
|
0b42f8 |
|
|
|
0b42f8 |
do_relocation:
|
|
|
0b42f8 |
|
|
|
0b42f8 |
+ /* When applying a 24 bit reloc we need to start one byte
|
|
|
0b42f8 |
+ earlier. Otherwise the 32 bit get/put bfd operations might
|
|
|
0b42f8 |
+ access a byte after the actual section. */
|
|
|
0b42f8 |
+ if (r_type == R_390_PC24DBL
|
|
|
0b42f8 |
+ || r_type == R_390_PLT24DBL)
|
|
|
0b42f8 |
+ rel->r_offset--;
|
|
|
0b42f8 |
+
|
|
|
0b42f8 |
if (r_type == R_390_20
|
|
|
0b42f8 |
|| r_type == R_390_GOT20
|
|
|
0b42f8 |
|| r_type == R_390_GOTPLT20
|
|
|
0b42f8 |
--- a/bfd/elf64-s390.c
|
|
|
0b42f8 |
+++ b/bfd/elf64-s390.c
|
|
|
0b42f8 |
@@ -43,7 +43,7 @@ static reloc_howto_type elf_howto_table[] =
|
|
|
0b42f8 |
{
|
|
|
0b42f8 |
HOWTO (R_390_NONE, /* type */
|
|
|
0b42f8 |
0, /* rightshift */
|
|
|
0b42f8 |
- 0, /* size (0 = byte, 1 = short, 2 = long) */
|
|
|
0b42f8 |
+ 0, /* size (0 = byte, 1 = 2 byte, 2 = 4 byte) */
|
|
|
0b42f8 |
0, /* bitsize */
|
|
|
0b42f8 |
FALSE, /* pc_relative */
|
|
|
0b42f8 |
0, /* bitpos */
|
|
|
0b42f8 |
@@ -171,7 +171,14 @@ static reloc_howto_type elf_howto_table[] =
|
|
|
0b42f8 |
s390_elf_ldisp_reloc, "R_390_TLS_GOTIE20", FALSE, 0,0x0fffff00, FALSE),
|
|
|
0b42f8 |
HOWTO(R_390_IRELATIVE, 0, 4, 64, FALSE, 0, complain_overflow_bitfield,
|
|
|
0b42f8 |
bfd_elf_generic_reloc, "R_390_IRELATIVE", FALSE, 0, MINUS_ONE, FALSE),
|
|
|
0b42f8 |
-
|
|
|
0b42f8 |
+ HOWTO(R_390_PC12DBL, 1, 1, 12, TRUE, 0, complain_overflow_bitfield,
|
|
|
0b42f8 |
+ bfd_elf_generic_reloc, "R_390_PC12DBL", FALSE, 0,0x00000fff, TRUE),
|
|
|
0b42f8 |
+ HOWTO(R_390_PLT12DBL, 1, 1, 12, TRUE, 0, complain_overflow_bitfield,
|
|
|
0b42f8 |
+ bfd_elf_generic_reloc, "R_390_PLT12DBL", FALSE, 0,0x00000fff, TRUE),
|
|
|
0b42f8 |
+ HOWTO(R_390_PC24DBL, 1, 2, 24, TRUE, 0, complain_overflow_bitfield,
|
|
|
0b42f8 |
+ bfd_elf_generic_reloc, "R_390_PC24DBL", FALSE, 0,0x00ffffff, TRUE),
|
|
|
0b42f8 |
+ HOWTO(R_390_PLT24DBL, 1, 2, 24, TRUE, 0, complain_overflow_bitfield,
|
|
|
0b42f8 |
+ bfd_elf_generic_reloc, "R_390_PLT24DBL", FALSE, 0,0x00ffffff, TRUE),
|
|
|
0b42f8 |
};
|
|
|
0b42f8 |
|
|
|
0b42f8 |
/* GNU extension to record C++ vtable hierarchy. */
|
|
|
0b42f8 |
@@ -222,10 +229,18 @@ elf_s390_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
|
|
|
0b42f8 |
return &elf_howto_table[(int) R_390_GOT16];
|
|
|
0b42f8 |
case BFD_RELOC_16_PCREL:
|
|
|
0b42f8 |
return &elf_howto_table[(int) R_390_PC16];
|
|
|
0b42f8 |
+ case BFD_RELOC_390_PC12DBL:
|
|
|
0b42f8 |
+ return &elf_howto_table[(int) R_390_PC12DBL];
|
|
|
0b42f8 |
+ case BFD_RELOC_390_PLT12DBL:
|
|
|
0b42f8 |
+ return &elf_howto_table[(int) R_390_PLT12DBL];
|
|
|
0b42f8 |
case BFD_RELOC_390_PC16DBL:
|
|
|
0b42f8 |
return &elf_howto_table[(int) R_390_PC16DBL];
|
|
|
0b42f8 |
case BFD_RELOC_390_PLT16DBL:
|
|
|
0b42f8 |
return &elf_howto_table[(int) R_390_PLT16DBL];
|
|
|
0b42f8 |
+ case BFD_RELOC_390_PC24DBL:
|
|
|
0b42f8 |
+ return &elf_howto_table[(int) R_390_PC24DBL];
|
|
|
0b42f8 |
+ case BFD_RELOC_390_PLT24DBL:
|
|
|
0b42f8 |
+ return &elf_howto_table[(int) R_390_PLT24DBL];
|
|
|
0b42f8 |
case BFD_RELOC_390_PC32DBL:
|
|
|
0b42f8 |
return &elf_howto_table[(int) R_390_PC32DBL];
|
|
|
0b42f8 |
case BFD_RELOC_390_PLT32DBL:
|
|
|
0b42f8 |
@@ -1037,7 +1052,9 @@ elf_s390_check_relocs (bfd *abfd,
|
|
|
0b42f8 |
are done. */
|
|
|
0b42f8 |
break;
|
|
|
0b42f8 |
|
|
|
0b42f8 |
+ case R_390_PLT12DBL:
|
|
|
0b42f8 |
case R_390_PLT16DBL:
|
|
|
0b42f8 |
+ case R_390_PLT24DBL:
|
|
|
0b42f8 |
case R_390_PLT32:
|
|
|
0b42f8 |
case R_390_PLT32DBL:
|
|
|
0b42f8 |
case R_390_PLT64:
|
|
|
0b42f8 |
@@ -1176,8 +1193,10 @@ elf_s390_check_relocs (bfd *abfd,
|
|
|
0b42f8 |
case R_390_16:
|
|
|
0b42f8 |
case R_390_32:
|
|
|
0b42f8 |
case R_390_64:
|
|
|
0b42f8 |
+ case R_390_PC12DBL:
|
|
|
0b42f8 |
case R_390_PC16:
|
|
|
0b42f8 |
case R_390_PC16DBL:
|
|
|
0b42f8 |
+ case R_390_PC24DBL:
|
|
|
0b42f8 |
case R_390_PC32:
|
|
|
0b42f8 |
case R_390_PC32DBL:
|
|
|
0b42f8 |
case R_390_PC64:
|
|
|
0b42f8 |
@@ -1223,7 +1242,9 @@ elf_s390_check_relocs (bfd *abfd,
|
|
|
0b42f8 |
if ((info->shared
|
|
|
0b42f8 |
&& (sec->flags & SEC_ALLOC) != 0
|
|
|
0b42f8 |
&& ((ELF64_R_TYPE (rel->r_info) != R_390_PC16
|
|
|
0b42f8 |
+ && ELF64_R_TYPE (rel->r_info) != R_390_PC12DBL
|
|
|
0b42f8 |
&& ELF64_R_TYPE (rel->r_info) != R_390_PC16DBL
|
|
|
0b42f8 |
+ && ELF64_R_TYPE (rel->r_info) != R_390_PC24DBL
|
|
|
0b42f8 |
&& ELF64_R_TYPE (rel->r_info) != R_390_PC32
|
|
|
0b42f8 |
&& ELF64_R_TYPE (rel->r_info) != R_390_PC32DBL
|
|
|
0b42f8 |
&& ELF64_R_TYPE (rel->r_info) != R_390_PC64)
|
|
|
0b42f8 |
@@ -1300,6 +1321,8 @@ elf_s390_check_relocs (bfd *abfd,
|
|
|
0b42f8 |
|
|
|
0b42f8 |
p->count += 1;
|
|
|
0b42f8 |
if (ELF64_R_TYPE (rel->r_info) == R_390_PC16
|
|
|
0b42f8 |
+ || ELF64_R_TYPE (rel->r_info) == R_390_PC12DBL
|
|
|
0b42f8 |
+ || ELF64_R_TYPE (rel->r_info) == R_390_PC16DBL
|
|
|
0b42f8 |
|| ELF64_R_TYPE (rel->r_info) == R_390_PC16DBL
|
|
|
0b42f8 |
|| ELF64_R_TYPE (rel->r_info) == R_390_PC32
|
|
|
0b42f8 |
|| ELF64_R_TYPE (rel->r_info) == R_390_PC32DBL
|
|
|
0b42f8 |
@@ -1471,7 +1494,9 @@ elf_s390_gc_sweep_hook (bfd *abfd,
|
|
|
0b42f8 |
case R_390_32:
|
|
|
0b42f8 |
case R_390_64:
|
|
|
0b42f8 |
case R_390_PC16:
|
|
|
0b42f8 |
+ case R_390_PC12DBL:
|
|
|
0b42f8 |
case R_390_PC16DBL:
|
|
|
0b42f8 |
+ case R_390_PC24DBL:
|
|
|
0b42f8 |
case R_390_PC32:
|
|
|
0b42f8 |
case R_390_PC32DBL:
|
|
|
0b42f8 |
case R_390_PC64:
|
|
|
0b42f8 |
@@ -1479,7 +1504,9 @@ elf_s390_gc_sweep_hook (bfd *abfd,
|
|
|
0b42f8 |
break;
|
|
|
0b42f8 |
/* Fall through */
|
|
|
0b42f8 |
|
|
|
0b42f8 |
+ case R_390_PLT12DBL:
|
|
|
0b42f8 |
case R_390_PLT16DBL:
|
|
|
0b42f8 |
+ case R_390_PLT24DBL:
|
|
|
0b42f8 |
case R_390_PLT32:
|
|
|
0b42f8 |
case R_390_PLT32DBL:
|
|
|
0b42f8 |
case R_390_PLT64:
|
|
|
0b42f8 |
@@ -2550,7 +2577,9 @@ elf_s390_relocate_section (bfd *output_bfd,
|
|
|
0b42f8 |
unresolved_reloc = FALSE;
|
|
|
0b42f8 |
break;
|
|
|
0b42f8 |
|
|
|
0b42f8 |
+ case R_390_PLT12DBL:
|
|
|
0b42f8 |
case R_390_PLT16DBL:
|
|
|
0b42f8 |
+ case R_390_PLT24DBL:
|
|
|
0b42f8 |
case R_390_PLT32:
|
|
|
0b42f8 |
case R_390_PLT32DBL:
|
|
|
0b42f8 |
case R_390_PLT64:
|
|
|
0b42f8 |
@@ -2615,7 +2644,9 @@ elf_s390_relocate_section (bfd *output_bfd,
|
|
|
0b42f8 |
case R_390_32:
|
|
|
0b42f8 |
case R_390_64:
|
|
|
0b42f8 |
case R_390_PC16:
|
|
|
0b42f8 |
+ case R_390_PC12DBL:
|
|
|
0b42f8 |
case R_390_PC16DBL:
|
|
|
0b42f8 |
+ case R_390_PC24DBL:
|
|
|
0b42f8 |
case R_390_PC32:
|
|
|
0b42f8 |
case R_390_PC32DBL:
|
|
|
0b42f8 |
case R_390_PC64:
|
|
|
0b42f8 |
@@ -2689,7 +2720,9 @@ elf_s390_relocate_section (bfd *output_bfd,
|
|
|
0b42f8 |
|| ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
|
|
|
0b42f8 |
|| h->root.type != bfd_link_hash_undefweak)
|
|
|
0b42f8 |
&& ((r_type != R_390_PC16
|
|
|
0b42f8 |
+ && r_type != R_390_PC12DBL
|
|
|
0b42f8 |
&& r_type != R_390_PC16DBL
|
|
|
0b42f8 |
+ && r_type != R_390_PC24DBL
|
|
|
0b42f8 |
&& r_type != R_390_PC32
|
|
|
0b42f8 |
&& r_type != R_390_PC32DBL
|
|
|
0b42f8 |
&& r_type != R_390_PC64)
|
|
|
0b42f8 |
@@ -2731,7 +2764,9 @@ elf_s390_relocate_section (bfd *output_bfd,
|
|
|
0b42f8 |
else if (h != NULL
|
|
|
0b42f8 |
&& h->dynindx != -1
|
|
|
0b42f8 |
&& (r_type == R_390_PC16
|
|
|
0b42f8 |
+ || r_type == R_390_PC12DBL
|
|
|
0b42f8 |
|| r_type == R_390_PC16DBL
|
|
|
0b42f8 |
+ || r_type == R_390_PC24DBL
|
|
|
0b42f8 |
|| r_type == R_390_PC32
|
|
|
0b42f8 |
|| r_type == R_390_PC32DBL
|
|
|
0b42f8 |
|| r_type == R_390_PC64
|
|
|
0b42f8 |
@@ -3168,6 +3203,13 @@ elf_s390_relocate_section (bfd *output_bfd,
|
|
|
0b42f8 |
|
|
|
0b42f8 |
do_relocation:
|
|
|
0b42f8 |
|
|
|
0b42f8 |
+ /* When applying a 24 bit reloc we need to start one byte
|
|
|
0b42f8 |
+ earlier. Otherwise the 32 bit get/put bfd operations might
|
|
|
0b42f8 |
+ access a byte after the actual section. */
|
|
|
0b42f8 |
+ if (r_type == R_390_PC24DBL
|
|
|
0b42f8 |
+ || r_type == R_390_PLT24DBL)
|
|
|
0b42f8 |
+ rel->r_offset--;
|
|
|
0b42f8 |
+
|
|
|
0b42f8 |
if (r_type == R_390_20
|
|
|
0b42f8 |
|| r_type == R_390_GOT20
|
|
|
0b42f8 |
|| r_type == R_390_GOTPLT20
|
|
|
0b42f8 |
--- a/bfd/libbfd.h
|
|
|
0b42f8 |
+++ b/bfd/libbfd.h
|
|
|
0b42f8 |
@@ -2008,8 +2008,12 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
|
|
|
0b42f8 |
"BFD_RELOC_390_RELATIVE",
|
|
|
0b42f8 |
"BFD_RELOC_390_GOTPC",
|
|
|
0b42f8 |
"BFD_RELOC_390_GOT16",
|
|
|
0b42f8 |
+ "BFD_RELOC_390_PC12DBL",
|
|
|
0b42f8 |
+ "BFD_RELOC_390_PLT12DBL",
|
|
|
0b42f8 |
"BFD_RELOC_390_PC16DBL",
|
|
|
0b42f8 |
"BFD_RELOC_390_PLT16DBL",
|
|
|
0b42f8 |
+ "BFD_RELOC_390_PC24DBL",
|
|
|
0b42f8 |
+ "BFD_RELOC_390_PLT24DBL",
|
|
|
0b42f8 |
"BFD_RELOC_390_PC32DBL",
|
|
|
0b42f8 |
"BFD_RELOC_390_PLT32DBL",
|
|
|
0b42f8 |
"BFD_RELOC_390_GOTPCDBL",
|
|
|
0b42f8 |
### a/include/elf/ChangeLog
|
|
|
0b42f8 |
### b/include/elf/ChangeLog
|
|
|
0b42f8 |
## -1,3 +1,8 @@
|
|
|
0b42f8 |
+2013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
|
|
|
0b42f8 |
+
|
|
|
0b42f8 |
+ * s390.h: Add new relocs R_390_PC12DBL, R_390_PLT12DBL,
|
|
|
0b42f8 |
+ R_390_PC24DBL, and R_390_PLT24DBL.
|
|
|
0b42f8 |
+
|
|
|
0b42f8 |
2013-06-26 Yufeng Zhang <yufeng.zhang@arm.com>
|
|
|
0b42f8 |
|
|
|
0b42f8 |
* aarch64.h: Add ELF32 reloc codes and remove fake ELF64 ones.
|
|
|
0b42f8 |
--- a/include/elf/s390.h
|
|
|
0b42f8 |
+++ b/include/elf/s390.h
|
|
|
0b42f8 |
@@ -57,8 +57,12 @@ START_RELOC_NUMBERS (elf_s390_reloc_type)
|
|
|
0b42f8 |
RELOC_NUMBER (R_390_GOTPC, 14) /* 32 bit PC relative offset to GOT. */
|
|
|
0b42f8 |
RELOC_NUMBER (R_390_GOT16, 15) /* 16 bit GOT offset. */
|
|
|
0b42f8 |
RELOC_NUMBER (R_390_PC16, 16) /* PC relative 16 bit. */
|
|
|
0b42f8 |
+ RELOC_NUMBER (R_390_PC12DBL, 62) /* PC relative 12 bit shifted by 1. */
|
|
|
0b42f8 |
+ RELOC_NUMBER (R_390_PLT12DBL, 63) /* 12 bit PC rel. PLT shifted by 1. */
|
|
|
0b42f8 |
RELOC_NUMBER (R_390_PC16DBL, 17) /* PC relative 16 bit shifted by 1. */
|
|
|
0b42f8 |
RELOC_NUMBER (R_390_PLT16DBL, 18) /* 16 bit PC rel. PLT shifted by 1. */
|
|
|
0b42f8 |
+ RELOC_NUMBER (R_390_PC24DBL, 64) /* PC relative 24 bit shifted by 1. */
|
|
|
0b42f8 |
+ RELOC_NUMBER (R_390_PLT24DBL, 65) /* 24 bit PC rel. PLT shifted by 1. */
|
|
|
0b42f8 |
RELOC_NUMBER (R_390_PC32DBL, 19) /* PC relative 32 bit shifted by 1. */
|
|
|
0b42f8 |
RELOC_NUMBER (R_390_PLT32DBL, 20) /* 32 bit PC rel. PLT shifted by 1. */
|
|
|
0b42f8 |
RELOC_NUMBER (R_390_GOTPCDBL, 21) /* 32 bit PC rel. GOT shifted by 1. */
|
|
|
0b42f8 |
### a/opcodes/ChangeLog
|
|
|
0b42f8 |
### b/opcodes/ChangeLog
|
|
|
0b42f8 |
## -1,3 +1,10 @@
|
|
|
0b42f8 |
+2013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
|
|
|
0b42f8 |
+
|
|
|
0b42f8 |
+ * s390-opc.c (J12_12, J24_24): New macros.
|
|
|
0b42f8 |
+ (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
|
|
|
0b42f8 |
+ (MASK_MII_UPI): Rename to MASK_MII_UPP.
|
|
|
0b42f8 |
+ * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
|
|
|
0b42f8 |
+
|
|
|
0b42f8 |
2013-07-04 Alan Modra <amodra@gmail.com>
|
|
|
0b42f8 |
|
|
|
0b42f8 |
* ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
|
|
|
0b42f8 |
--- a/opcodes/s390-opc.c
|
|
|
0b42f8 |
+++ b/opcodes/s390-opc.c
|
|
|
0b42f8 |
@@ -217,20 +217,23 @@ const struct s390_operand s390_operands[] =
|
|
|
0b42f8 |
|
|
|
0b42f8 |
/* PC-relative address operands. */
|
|
|
0b42f8 |
|
|
|
0b42f8 |
-#define J12_12 69 /* PC relative offset at 12 */
|
|
|
0b42f8 |
+#define J12_12 69 /* 12 bit PC relative offset at 12 */
|
|
|
0b42f8 |
{ 12, 12, S390_OPERAND_PCREL },
|
|
|
0b42f8 |
-#define J16_16 70 /* PC relative offset at 16 */
|
|
|
0b42f8 |
+#define J16_16 70 /* 16 bit PC relative offset at 16 */
|
|
|
0b42f8 |
{ 16, 16, S390_OPERAND_PCREL },
|
|
|
0b42f8 |
-#define J16_32 71 /* PC relative offset at 16 */
|
|
|
0b42f8 |
+#define J16_32 71 /* 16 bit PC relative offset at 32 */
|
|
|
0b42f8 |
{ 16, 32, S390_OPERAND_PCREL },
|
|
|
0b42f8 |
-#define J32_16 72 /* PC relative offset at 16 */
|
|
|
0b42f8 |
+#define J24_24 72 /* 24 bit PC relative offset at 24 */
|
|
|
0b42f8 |
+ { 24, 24, S390_OPERAND_PCREL },
|
|
|
0b42f8 |
+#define J32_16 73 /* 32 bit PC relative offset at 16 */
|
|
|
0b42f8 |
{ 32, 16, S390_OPERAND_PCREL },
|
|
|
0b42f8 |
|
|
|
0b42f8 |
+
|
|
|
0b42f8 |
/* Conditional mask operands. */
|
|
|
0b42f8 |
|
|
|
0b42f8 |
-#define M_16OPT 73 /* 4 bit optional mask starting at 16 */
|
|
|
0b42f8 |
+#define M_16OPT 74 /* 4 bit optional mask starting at 16 */
|
|
|
0b42f8 |
{ 4, 16, S390_OPERAND_OPTIONAL },
|
|
|
0b42f8 |
-#define M_20OPT 74 /* 4 bit optional mask starting at 20 */
|
|
|
0b42f8 |
+#define M_20OPT 75 /* 4 bit optional mask starting at 20 */
|
|
|
0b42f8 |
{ 4, 20, S390_OPERAND_OPTIONAL },
|
|
|
0b42f8 |
|
|
|
0b42f8 |
};
|
|
|
0b42f8 |
@@ -284,7 +287,7 @@ const struct s390_operand s390_operands[] =
|
|
|
0b42f8 |
|
|
|
0b42f8 |
#define INSTR_E 2, { 0,0,0,0,0,0 } /* e.g. pr */
|
|
|
0b42f8 |
#define INSTR_IE_UU 4, { U4_24,U4_28,0,0,0,0 } /* e.g. niai */
|
|
|
0b42f8 |
-#define INSTR_MII_UPI 6, { U4_8,J12_12,I24_24 } /* e.g. bprp */
|
|
|
0b42f8 |
+#define INSTR_MII_UPP 6, { U4_8,J12_12,J24_24 } /* e.g. bprp */
|
|
|
0b42f8 |
#define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */
|
|
|
0b42f8 |
#define INSTR_RIE_RRPU 6, { R_8,R_12,U4_32,J16_16,0,0 } /* e.g. crj */
|
|
|
0b42f8 |
#define INSTR_RIE_RRP0 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. crjne */
|
|
|
0b42f8 |
@@ -446,7 +449,7 @@ const struct s390_operand s390_operands[] =
|
|
|
0b42f8 |
|
|
|
0b42f8 |
#define MASK_E { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
|
|
|
0b42f8 |
#define MASK_IE_UU { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
|
|
|
0b42f8 |
-#define MASK_MII_UPI { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
|
|
|
0b42f8 |
+#define MASK_MII_UPP { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
|
|
|
0b42f8 |
#define MASK_RIE_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
|
|
|
0b42f8 |
#define MASK_RIE_RRPU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
|
|
|
0b42f8 |
#define MASK_RIE_RRP0 { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff }
|
|
|
0b42f8 |
--- a/opcodes/s390-opc.txt
|
|
|
0b42f8 |
+++ b/opcodes/s390-opc.txt
|
|
|
0b42f8 |
@@ -1126,7 +1126,7 @@ e560 tbegin SIL_RDU "transaction begin" zEC12 zarch
|
|
|
0b42f8 |
e561 tbeginc SIL_RDU "constrained transaction begin" zEC12 zarch
|
|
|
0b42f8 |
b2f8 tend S_00 "transaction end" zEC12 zarch
|
|
|
0b42f8 |
c7 bpp SMI_U0RDP "branch prediction preload" zEC12 zarch
|
|
|
0b42f8 |
-c5 bprp MII_UPI "branch prediction relative preload" zEC12 zarch
|
|
|
0b42f8 |
+c5 bprp MII_UPP "branch prediction relative preload" zEC12 zarch
|
|
|
0b42f8 |
b2e8 ppa RRF_U0RR "perform processor assist" zEC12 zarch
|
|
|
0b42f8 |
b2fa niai IE_UU "next instruction access intent" zEC12 zarch
|
|
|
0b42f8 |
b98f crdte RRF_RMRR "compare and replace DAT table entry" zEC12 zarch
|