|
 |
01917d |
commit 084ee54552f6c35d740e8b9bc81a4fe8d8bb178b
|
|
|
01917d |
Author: Ulrich Weigand <ulrich.weigand@de.ibm.com>
|
|
|
01917d |
Date: Tue Feb 4 18:31:38 2014 +0100
|
|
|
01917d |
|
|
|
01917d |
PowerPC64 little-endian fixes: VSX tests and pseudo-regs
|
|
|
01917d |
|
|
|
01917d |
Many VSX test were failing on powerpc64le-linux, since -as opposed to the
|
|
|
01917d |
AltiVec tests- there never were little-endian versions of the test patterns.
|
|
|
01917d |
|
|
|
01917d |
This patch adds such patterns, along the lines of altivec-regs.exp.
|
|
|
01917d |
|
|
|
01917d |
In addition, there is an actual code change required: For those VSX
|
|
|
01917d |
registers that overlap a floating-point register, the FP register
|
|
|
01917d |
overlaps the most-significant half of the VSX register both on big-
|
|
|
01917d |
and little-endian systems. However, on little-endian systems, that
|
|
|
01917d |
half is stored at an offset of 8 bytes (not 0). This works already
|
|
|
01917d |
for the "real" FP registers, but current code gets it wrong for
|
|
|
01917d |
the "extended" pseudo FP register GDB generates for the second
|
|
|
01917d |
half of the VSX register bank.
|
|
|
01917d |
|
|
|
01917d |
This patch updates the corresponding pseudo read/write routines
|
|
|
01917d |
to take the appropriate offset into consideration.
|
|
|
01917d |
|
|
|
01917d |
gdb/ChangeLog:
|
|
|
01917d |
|
|
|
01917d |
* rs6000-tdep.c (efpr_pseudo_register_read): Use correct offset
|
|
|
01917d |
of the overlapped FP register within the VSX register on little-
|
|
|
01917d |
endian platforms.
|
|
|
01917d |
(efpr_pseudo_register_write): Likewise.
|
|
|
01917d |
|
|
|
01917d |
gdb/testsuite/ChangeLog:
|
|
|
01917d |
|
|
|
01917d |
* gdb.arch/vsx-regs.exp: Check target endianness. Provide variants
|
|
|
01917d |
of the test patterns for use on little-endian systems.
|
|
|
01917d |
|
|
|
01917d |
Index: gdb-7.6.1/gdb/rs6000-tdep.c
|
|
|
01917d |
===================================================================
|
|
|
01917d |
--- gdb-7.6.1.orig/gdb/rs6000-tdep.c
|
|
|
01917d |
+++ gdb-7.6.1/gdb/rs6000-tdep.c
|
|
|
01917d |
@@ -2830,10 +2830,12 @@ efpr_pseudo_register_read (struct gdbarc
|
|
|
01917d |
{
|
|
|
01917d |
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
|
|
|
01917d |
int reg_index = reg_nr - tdep->ppc_efpr0_regnum;
|
|
|
01917d |
+ int offset = gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG ? 0 : 8;
|
|
|
01917d |
|
|
|
01917d |
/* Read the portion that overlaps the VMX register. */
|
|
|
01917d |
- return regcache_raw_read_part (regcache, tdep->ppc_vr0_regnum + reg_index, 0,
|
|
|
01917d |
- register_size (gdbarch, reg_nr), buffer);
|
|
|
01917d |
+ return regcache_raw_read_part (regcache, tdep->ppc_vr0_regnum + reg_index,
|
|
|
01917d |
+ offset, register_size (gdbarch, reg_nr),
|
|
|
01917d |
+ buffer);
|
|
|
01917d |
}
|
|
|
01917d |
|
|
|
01917d |
/* Write method for POWER7 Extended FP pseudo-registers. */
|
|
|
01917d |
@@ -2843,10 +2845,12 @@ efpr_pseudo_register_write (struct gdbar
|
|
|
01917d |
{
|
|
|
01917d |
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
|
|
|
01917d |
int reg_index = reg_nr - tdep->ppc_efpr0_regnum;
|
|
|
01917d |
+ int offset = gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG ? 0 : 8;
|
|
|
01917d |
|
|
|
01917d |
/* Write the portion that overlaps the VMX register. */
|
|
|
01917d |
- regcache_raw_write_part (regcache, tdep->ppc_vr0_regnum + reg_index, 0,
|
|
|
01917d |
- register_size (gdbarch, reg_nr), buffer);
|
|
|
01917d |
+ regcache_raw_write_part (regcache, tdep->ppc_vr0_regnum + reg_index,
|
|
|
01917d |
+ offset, register_size (gdbarch, reg_nr),
|
|
|
01917d |
+ buffer);
|
|
|
01917d |
}
|
|
|
01917d |
|
|
|
01917d |
static enum register_status
|
|
|
01917d |
Index: gdb-7.6.1/gdb/testsuite/gdb.arch/vsx-regs.exp
|
|
|
01917d |
===================================================================
|
|
|
01917d |
--- gdb-7.6.1.orig/gdb/testsuite/gdb.arch/vsx-regs.exp
|
|
|
01917d |
+++ gdb-7.6.1/gdb/testsuite/gdb.arch/vsx-regs.exp
|
|
|
01917d |
@@ -58,19 +58,45 @@ if ![runto_main] then {
|
|
|
01917d |
gdb_suppress_tests
|
|
|
01917d |
}
|
|
|
01917d |
|
|
|
01917d |
+set endianness ""
|
|
|
01917d |
+set msg "detect endianness"
|
|
|
01917d |
+gdb_test_multiple "show endian" "$msg" {
|
|
|
01917d |
+ -re "(The target endianness is set automatically .currently )(big|little)( endian.*)$gdb_prompt $" {
|
|
|
01917d |
+ pass "$msg"
|
|
|
01917d |
+ set endianness $expect_out(2,string)
|
|
|
01917d |
+ }
|
|
|
01917d |
+ -re ".*$gdb_prompt $" {
|
|
|
01917d |
+ fail "$msg"
|
|
|
01917d |
+ }
|
|
|
01917d |
+}
|
|
|
01917d |
+
|
|
|
01917d |
# Data sets used throughout the test
|
|
|
01917d |
|
|
|
01917d |
-set vector_register1 ".uint128 = 0x3ff4cccccccccccc0000000000000000, v2_double = .0x1, 0x0., v4_float = .0x1, 0xf99999a0, 0x0, 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccc, 0x0, 0x0., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccc, 0x0, 0x0, 0x0, 0x0., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0.."
|
|
|
01917d |
+if {$endianness == "big"} {
|
|
|
01917d |
+ set vector_register1 ".uint128 = 0x3ff4cccccccccccc0000000000000000, v2_double = .0x1, 0x0., v4_float = .0x1, 0xf99999a0, 0x0, 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccc, 0x0, 0x0., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccc, 0x0, 0x0, 0x0, 0x0., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0.."
|
|
|
01917d |
+
|
|
|
01917d |
+ set vector_register1_vr ".uint128 = 0x3ff4cccccccccccc0000000100000001, v4_float = .0x1, 0xf99999a0, 0x0, 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccc, 0x1, 0x1., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccc, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
|
|
|
01917d |
+
|
|
|
01917d |
+ set vector_register2 "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double = .0x1, 0x1., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.."
|
|
|
01917d |
|
|
|
01917d |
-set vector_register1_vr ".uint128 = 0x3ff4cccccccccccc0000000100000001, v4_float = .0x1, 0xf99999a0, 0x0, 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccc, 0x1, 0x1., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccc, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
|
|
|
01917d |
+ set vector_register2_vr "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.."
|
|
|
01917d |
|
|
|
01917d |
-set vector_register2 "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double = .0x1, 0x1., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.."
|
|
|
01917d |
+ set vector_register3 ".uint128 = 0x00000001000000010000000100000001, v2_double = .0x0, 0x0., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
|
|
|
01917d |
|
|
|
01917d |
-set vector_register2_vr "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.."
|
|
|
01917d |
+ set vector_register3_vr ".uint128 = 0x00000001000000010000000100000001, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
|
|
|
01917d |
+} else {
|
|
|
01917d |
+ set vector_register1 ".uint128 = 0x3ff4cccccccccccc0000000000000000, v2_double = .0x0, 0x1., v4_float = .0x0, 0x0, 0xf99999a0, 0x1., v4_int32 = .0x0, 0x0, 0xcccccccc, 0x3ff4cccc., v8_int16 = .0x0, 0x0, 0x0, 0x0, 0xcccc, 0xcccc, 0xcccc, 0x3ff4., v16_int8 = .0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xf4, 0x3f.."
|
|
|
01917d |
|
|
|
01917d |
-set vector_register3 ".uint128 = 0x00000001000000010000000100000001, v2_double = .0x0, 0x0., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
|
|
|
01917d |
+ set vector_register1_vr ".uint128 = 0x3ff4cccccccccccc0000000100000001, v4_float = .0x0, 0x0, 0xf99999a0, 0x1., v4_int32 = .0x1, 0x1, 0xcccccccc, 0x3ff4cccc., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0xcccc, 0xcccc, 0xcccc, 0x3ff4., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xf4, 0x3f.."
|
|
|
01917d |
|
|
|
01917d |
-set vector_register3_vr ".uint128 = 0x00000001000000010000000100000001, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
|
|
|
01917d |
+ set vector_register2 "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double = .0x1, 0x1., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead., v16_int8 = .0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde.."
|
|
|
01917d |
+
|
|
|
01917d |
+ set vector_register2_vr "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead., v16_int8 = .0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde.."
|
|
|
01917d |
+
|
|
|
01917d |
+ set vector_register3 ".uint128 = 0x00000001000000010000000100000001, v2_double = .0x0, 0x0., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0.."
|
|
|
01917d |
+
|
|
|
01917d |
+ set vector_register3_vr ".uint128 = 0x00000001000000010000000100000001, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0.."
|
|
|
01917d |
+}
|
|
|
01917d |
|
|
|
01917d |
set float_register ".raw 0xdeadbeefdeadbeef."
|
|
|
01917d |
|