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56d343 |
2015-10-14 Peter Bergner <bergner@vnet.ibm.com>
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56d343 |
Torvald Riegel <triegel@redhat.com>
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56d343 |
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56d343 |
PR target/67281
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56d343 |
* config/rs6000/htm.md (UNSPEC_HTM_FENCE): New.
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56d343 |
(tabort, tabort<wd>c, tabort<wd>ci, tbegin, tcheck, tend,
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56d343 |
trechkpt, treclaim, tsr, ttest): Rename define_insns from this...
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56d343 |
(*tabort, *tabort<wd>c, *tabort<wd>ci, *tbegin, *tcheck, *tend,
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56d343 |
*trechkpt, *treclaim, *tsr, *ttest): ...to this. Add memory barrier.
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56d343 |
(tabort, tabort<wd>c, tabort<wd>ci, tbegin, tcheck, tend,
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56d343 |
trechkpt, treclaim, tsr, ttest): New define_expands.
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56d343 |
* config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Define
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56d343 |
__TM_FENCE__ for htm.
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56d343 |
* doc/extend.texi: Update documentation for htm builtins.
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56d343 |
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56d343 |
2015-08-03 Peter Bergner <bergner@vnet.ibm.com>
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56d343 |
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56d343 |
* config/rs6000/htm.md (tabort.): Restrict the source operand to
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56d343 |
using a base register.
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56d343 |
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56d343 |
* gcc.target/powerpc/htm-tabort-no-r0.c: New test.
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56d343 |
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56d343 |
--- gcc/doc/extend.texi (revision 228826)
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56d343 |
+++ gcc/doc/extend.texi (revision 228827)
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56d343 |
@@ -16092,6 +16092,28 @@ unsigned int __builtin_tresume (void)
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56d343 |
unsigned int __builtin_tsuspend (void)
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56d343 |
@end smallexample
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56d343 |
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56d343 |
+Note that the semantics of the above HTM builtins are required to mimic
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56d343 |
+the locking semantics used for critical sections. Builtins that are used
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56d343 |
+to create a new transaction or restart a suspended transaction must have
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56d343 |
+lock acquisition like semantics while those builtins that end or suspend a
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56d343 |
+transaction must have lock release like semantics. Specifically, this must
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56d343 |
+mimic lock semantics as specified by C++11, for example: Lock acquisition is
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56d343 |
+as-if an execution of __atomic_exchange_n(&globallock,1,__ATOMIC_ACQUIRE)
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56d343 |
+that returns 0, and lock release is as-if an execution of
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56d343 |
+__atomic_store(&globallock,0,__ATOMIC_RELEASE), with globallock being an
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56d343 |
+implicit implementation-defined lock used for all transactions. The HTM
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56d343 |
+instructions associated with with the builtins inherently provide the
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56d343 |
+correct acquisition and release hardware barriers required. However,
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56d343 |
+the compiler must also be prohibited from moving loads and stores across
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56d343 |
+the builtins in a way that would violate their semantics. This has been
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56d343 |
+accomplished by adding memory barriers to the associated HTM instructions
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56d343 |
+(which is a conservative approach to provide acquire and release semantics).
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56d343 |
+Earlier versions of the compiler did not treat the HTM instructions as
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56d343 |
+memory barriers. A @code{__TM_FENCE__} macro has been added, which can
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56d343 |
+be used to determine whether the current compiler treats HTM instructions
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56d343 |
+as memory barriers or not. This allows the user to explicitly add memory
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56d343 |
+barriers to their code when using an older version of the compiler.
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56d343 |
+
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56d343 |
The following set of built-in functions are available to gain access
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56d343 |
to the HTM specific special purpose registers.
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56d343 |
|
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56d343 |
--- gcc/config/rs6000/htm.md (revision 226531)
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56d343 |
+++ gcc/config/rs6000/htm.md (revision 228827)
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56d343 |
@@ -27,6 +27,14 @@ (define_constants
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56d343 |
])
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56d343 |
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56d343 |
;;
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56d343 |
+;; UNSPEC usage
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56d343 |
+;;
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56d343 |
+
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56d343 |
+(define_c_enum "unspec"
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56d343 |
+ [UNSPEC_HTM_FENCE
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56d343 |
+ ])
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56d343 |
+
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56d343 |
+;;
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56d343 |
;; UNSPEC_VOLATILE usage
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56d343 |
;;
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56d343 |
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56d343 |
@@ -45,96 +53,223 @@ (define_c_enum "unspecv"
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56d343 |
UNSPECV_HTM_MTSPR
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56d343 |
])
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56d343 |
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56d343 |
+(define_expand "tabort"
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56d343 |
+ [(parallel
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56d343 |
+ [(set (match_operand:CC 1 "cc_reg_operand" "=x")
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56d343 |
+ (unspec_volatile:CC [(match_operand:SI 0 "base_reg_operand" "b")]
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56d343 |
+ UNSPECV_HTM_TABORT))
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56d343 |
+ (set (match_dup 2) (unspec:BLK [(match_dup 2)] UNSPEC_HTM_FENCE))])]
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56d343 |
+ "TARGET_HTM"
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56d343 |
+{
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56d343 |
+ operands[2] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
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56d343 |
+ MEM_VOLATILE_P (operands[2]) = 1;
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56d343 |
+})
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56d343 |
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56d343 |
-(define_insn "tabort"
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56d343 |
+(define_insn "*tabort"
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56d343 |
[(set (match_operand:CC 1 "cc_reg_operand" "=x")
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56d343 |
- (unspec_volatile:CC [(match_operand:SI 0 "gpc_reg_operand" "r")]
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56d343 |
- UNSPECV_HTM_TABORT))]
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56d343 |
+ (unspec_volatile:CC [(match_operand:SI 0 "base_reg_operand" "b")]
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56d343 |
+ UNSPECV_HTM_TABORT))
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56d343 |
+ (set (match_operand:BLK 2) (unspec:BLK [(match_dup 2)] UNSPEC_HTM_FENCE))]
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56d343 |
"TARGET_HTM"
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56d343 |
"tabort. %0"
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56d343 |
[(set_attr "type" "htm")
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56d343 |
(set_attr "length" "4")])
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56d343 |
|
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56d343 |
-(define_insn "tabort<wd>c"
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56d343 |
+(define_expand "tabort<wd>c"
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56d343 |
+ [(parallel
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56d343 |
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x")
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56d343 |
+ (unspec_volatile:CC [(match_operand 0 "u5bit_cint_operand" "n")
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56d343 |
+ (match_operand:GPR 1 "gpc_reg_operand" "r")
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56d343 |
+ (match_operand:GPR 2 "gpc_reg_operand" "r")]
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56d343 |
+ UNSPECV_HTM_TABORTXC))
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56d343 |
+ (set (match_dup 4) (unspec:BLK [(match_dup 4)] UNSPEC_HTM_FENCE))])]
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56d343 |
+ "TARGET_HTM"
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56d343 |
+{
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|
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56d343 |
+ operands[4] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
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|
56d343 |
+ MEM_VOLATILE_P (operands[4]) = 1;
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56d343 |
+})
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56d343 |
+
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56d343 |
+(define_insn "*tabort<wd>c"
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56d343 |
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
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56d343 |
(unspec_volatile:CC [(match_operand 0 "u5bit_cint_operand" "n")
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56d343 |
(match_operand:GPR 1 "gpc_reg_operand" "r")
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56d343 |
(match_operand:GPR 2 "gpc_reg_operand" "r")]
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56d343 |
- UNSPECV_HTM_TABORTXC))]
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56d343 |
+ UNSPECV_HTM_TABORTXC))
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56d343 |
+ (set (match_operand:BLK 4) (unspec:BLK [(match_dup 4)] UNSPEC_HTM_FENCE))]
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56d343 |
"TARGET_HTM"
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56d343 |
"tabort<wd>c. %0,%1,%2"
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56d343 |
[(set_attr "type" "htm")
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56d343 |
(set_attr "length" "4")])
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56d343 |
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56d343 |
-(define_insn "tabort<wd>ci"
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56d343 |
+(define_expand "tabort<wd>ci"
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56d343 |
+ [(parallel
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56d343 |
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x")
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56d343 |
+ (unspec_volatile:CC [(match_operand 0 "u5bit_cint_operand" "n")
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56d343 |
+ (match_operand:GPR 1 "gpc_reg_operand" "r")
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56d343 |
+ (match_operand 2 "s5bit_cint_operand" "n")]
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56d343 |
+ UNSPECV_HTM_TABORTXCI))
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56d343 |
+ (set (match_dup 4) (unspec:BLK [(match_dup 4)] UNSPEC_HTM_FENCE))])]
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56d343 |
+ "TARGET_HTM"
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56d343 |
+{
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56d343 |
+ operands[4] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
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56d343 |
+ MEM_VOLATILE_P (operands[4]) = 1;
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56d343 |
+})
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56d343 |
+
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56d343 |
+(define_insn "*tabort<wd>ci"
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56d343 |
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
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56d343 |
(unspec_volatile:CC [(match_operand 0 "u5bit_cint_operand" "n")
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56d343 |
(match_operand:GPR 1 "gpc_reg_operand" "r")
|
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56d343 |
(match_operand 2 "s5bit_cint_operand" "n")]
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56d343 |
- UNSPECV_HTM_TABORTXCI))]
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56d343 |
+ UNSPECV_HTM_TABORTXCI))
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56d343 |
+ (set (match_operand:BLK 4) (unspec:BLK [(match_dup 4)] UNSPEC_HTM_FENCE))]
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56d343 |
"TARGET_HTM"
|
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56d343 |
"tabort<wd>ci. %0,%1,%2"
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56d343 |
[(set_attr "type" "htm")
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56d343 |
(set_attr "length" "4")])
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56d343 |
|
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56d343 |
-(define_insn "tbegin"
|
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|
56d343 |
+(define_expand "tbegin"
|
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56d343 |
+ [(parallel
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56d343 |
+ [(set (match_operand:CC 1 "cc_reg_operand" "=x")
|
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|
56d343 |
+ (unspec_volatile:CC [(match_operand 0 "const_0_to_1_operand" "n")]
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56d343 |
+ UNSPECV_HTM_TBEGIN))
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56d343 |
+ (set (match_dup 2) (unspec:BLK [(match_dup 2)] UNSPEC_HTM_FENCE))])]
|
|
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56d343 |
+ "TARGET_HTM"
|
|
|
56d343 |
+{
|
|
|
56d343 |
+ operands[2] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
|
|
|
56d343 |
+ MEM_VOLATILE_P (operands[2]) = 1;
|
|
|
56d343 |
+})
|
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|
56d343 |
+
|
|
|
56d343 |
+(define_insn "*tbegin"
|
|
|
56d343 |
[(set (match_operand:CC 1 "cc_reg_operand" "=x")
|
|
|
56d343 |
(unspec_volatile:CC [(match_operand 0 "const_0_to_1_operand" "n")]
|
|
|
56d343 |
- UNSPECV_HTM_TBEGIN))]
|
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56d343 |
+ UNSPECV_HTM_TBEGIN))
|
|
|
56d343 |
+ (set (match_operand:BLK 2) (unspec:BLK [(match_dup 2)] UNSPEC_HTM_FENCE))]
|
|
|
56d343 |
"TARGET_HTM"
|
|
|
56d343 |
"tbegin. %0"
|
|
|
56d343 |
[(set_attr "type" "htm")
|
|
|
56d343 |
(set_attr "length" "4")])
|
|
|
56d343 |
|
|
|
56d343 |
-(define_insn "tcheck"
|
|
|
56d343 |
+(define_expand "tcheck"
|
|
|
56d343 |
+ [(parallel
|
|
|
56d343 |
+ [(set (match_operand:CC 0 "cc_reg_operand" "=y")
|
|
|
56d343 |
+ (unspec_volatile:CC [(const_int 0)] UNSPECV_HTM_TCHECK))
|
|
|
56d343 |
+ (set (match_dup 1) (unspec:BLK [(match_dup 1)] UNSPEC_HTM_FENCE))])]
|
|
|
56d343 |
+ "TARGET_HTM"
|
|
|
56d343 |
+{
|
|
|
56d343 |
+ operands[1] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
|
|
|
56d343 |
+ MEM_VOLATILE_P (operands[1]) = 1;
|
|
|
56d343 |
+})
|
|
|
56d343 |
+
|
|
|
56d343 |
+(define_insn "*tcheck"
|
|
|
56d343 |
[(set (match_operand:CC 0 "cc_reg_operand" "=y")
|
|
|
56d343 |
- (unspec_volatile:CC [(const_int 0)]
|
|
|
56d343 |
- UNSPECV_HTM_TCHECK))]
|
|
|
56d343 |
+ (unspec_volatile:CC [(const_int 0)] UNSPECV_HTM_TCHECK))
|
|
|
56d343 |
+ (set (match_operand:BLK 1) (unspec:BLK [(match_dup 1)] UNSPEC_HTM_FENCE))]
|
|
|
56d343 |
"TARGET_HTM"
|
|
|
56d343 |
"tcheck %0"
|
|
|
56d343 |
[(set_attr "type" "htm")
|
|
|
56d343 |
(set_attr "length" "4")])
|
|
|
56d343 |
|
|
|
56d343 |
-(define_insn "tend"
|
|
|
56d343 |
+(define_expand "tend"
|
|
|
56d343 |
+ [(parallel
|
|
|
56d343 |
+ [(set (match_operand:CC 1 "cc_reg_operand" "=x")
|
|
|
56d343 |
+ (unspec_volatile:CC [(match_operand 0 "const_0_to_1_operand" "n")]
|
|
|
56d343 |
+ UNSPECV_HTM_TEND))
|
|
|
56d343 |
+ (set (match_dup 2) (unspec:BLK [(match_dup 2)] UNSPEC_HTM_FENCE))])]
|
|
|
56d343 |
+ "TARGET_HTM"
|
|
|
56d343 |
+{
|
|
|
56d343 |
+ operands[2] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
|
|
|
56d343 |
+ MEM_VOLATILE_P (operands[2]) = 1;
|
|
|
56d343 |
+})
|
|
|
56d343 |
+
|
|
|
56d343 |
+(define_insn "*tend"
|
|
|
56d343 |
[(set (match_operand:CC 1 "cc_reg_operand" "=x")
|
|
|
56d343 |
(unspec_volatile:CC [(match_operand 0 "const_0_to_1_operand" "n")]
|
|
|
56d343 |
- UNSPECV_HTM_TEND))]
|
|
|
56d343 |
+ UNSPECV_HTM_TEND))
|
|
|
56d343 |
+ (set (match_operand:BLK 2) (unspec:BLK [(match_dup 2)] UNSPEC_HTM_FENCE))]
|
|
|
56d343 |
"TARGET_HTM"
|
|
|
56d343 |
"tend. %0"
|
|
|
56d343 |
[(set_attr "type" "htm")
|
|
|
56d343 |
(set_attr "length" "4")])
|
|
|
56d343 |
|
|
|
56d343 |
-(define_insn "trechkpt"
|
|
|
56d343 |
+(define_expand "trechkpt"
|
|
|
56d343 |
+ [(parallel
|
|
|
56d343 |
+ [(set (match_operand:CC 0 "cc_reg_operand" "=x")
|
|
|
56d343 |
+ (unspec_volatile:CC [(const_int 0)] UNSPECV_HTM_TRECHKPT))
|
|
|
56d343 |
+ (set (match_dup 1) (unspec:BLK [(match_dup 1)] UNSPEC_HTM_FENCE))])]
|
|
|
56d343 |
+ "TARGET_HTM"
|
|
|
56d343 |
+{
|
|
|
56d343 |
+ operands[1] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
|
|
|
56d343 |
+ MEM_VOLATILE_P (operands[1]) = 1;
|
|
|
56d343 |
+})
|
|
|
56d343 |
+
|
|
|
56d343 |
+(define_insn "*trechkpt"
|
|
|
56d343 |
[(set (match_operand:CC 0 "cc_reg_operand" "=x")
|
|
|
56d343 |
- (unspec_volatile:CC [(const_int 0)]
|
|
|
56d343 |
- UNSPECV_HTM_TRECHKPT))]
|
|
|
56d343 |
+ (unspec_volatile:CC [(const_int 0)] UNSPECV_HTM_TRECHKPT))
|
|
|
56d343 |
+ (set (match_operand:BLK 1) (unspec:BLK [(match_dup 1)] UNSPEC_HTM_FENCE))]
|
|
|
56d343 |
"TARGET_HTM"
|
|
|
56d343 |
"trechkpt."
|
|
|
56d343 |
[(set_attr "type" "htm")
|
|
|
56d343 |
(set_attr "length" "4")])
|
|
|
56d343 |
|
|
|
56d343 |
-(define_insn "treclaim"
|
|
|
56d343 |
+(define_expand "treclaim"
|
|
|
56d343 |
+ [(parallel
|
|
|
56d343 |
+ [(set (match_operand:CC 1 "cc_reg_operand" "=x")
|
|
|
56d343 |
+ (unspec_volatile:CC [(match_operand:SI 0 "gpc_reg_operand" "r")]
|
|
|
56d343 |
+ UNSPECV_HTM_TRECLAIM))
|
|
|
56d343 |
+ (set (match_dup 2) (unspec:BLK [(match_dup 2)] UNSPEC_HTM_FENCE))])]
|
|
|
56d343 |
+ "TARGET_HTM"
|
|
|
56d343 |
+{
|
|
|
56d343 |
+ operands[2] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
|
|
|
56d343 |
+ MEM_VOLATILE_P (operands[2]) = 1;
|
|
|
56d343 |
+})
|
|
|
56d343 |
+
|
|
|
56d343 |
+(define_insn "*treclaim"
|
|
|
56d343 |
[(set (match_operand:CC 1 "cc_reg_operand" "=x")
|
|
|
56d343 |
(unspec_volatile:CC [(match_operand:SI 0 "gpc_reg_operand" "r")]
|
|
|
56d343 |
- UNSPECV_HTM_TRECLAIM))]
|
|
|
56d343 |
+ UNSPECV_HTM_TRECLAIM))
|
|
|
56d343 |
+ (set (match_operand:BLK 2) (unspec:BLK [(match_dup 2)] UNSPEC_HTM_FENCE))]
|
|
|
56d343 |
"TARGET_HTM"
|
|
|
56d343 |
"treclaim. %0"
|
|
|
56d343 |
[(set_attr "type" "htm")
|
|
|
56d343 |
(set_attr "length" "4")])
|
|
|
56d343 |
|
|
|
56d343 |
-(define_insn "tsr"
|
|
|
56d343 |
+(define_expand "tsr"
|
|
|
56d343 |
+ [(parallel
|
|
|
56d343 |
+ [(set (match_operand:CC 1 "cc_reg_operand" "=x")
|
|
|
56d343 |
+ (unspec_volatile:CC [(match_operand 0 "const_0_to_1_operand" "n")]
|
|
|
56d343 |
+ UNSPECV_HTM_TSR))
|
|
|
56d343 |
+ (set (match_dup 2) (unspec:BLK [(match_dup 2)] UNSPEC_HTM_FENCE))])]
|
|
|
56d343 |
+ "TARGET_HTM"
|
|
|
56d343 |
+{
|
|
|
56d343 |
+ operands[2] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
|
|
|
56d343 |
+ MEM_VOLATILE_P (operands[2]) = 1;
|
|
|
56d343 |
+})
|
|
|
56d343 |
+
|
|
|
56d343 |
+(define_insn "*tsr"
|
|
|
56d343 |
[(set (match_operand:CC 1 "cc_reg_operand" "=x")
|
|
|
56d343 |
(unspec_volatile:CC [(match_operand 0 "const_0_to_1_operand" "n")]
|
|
|
56d343 |
- UNSPECV_HTM_TSR))]
|
|
|
56d343 |
+ UNSPECV_HTM_TSR))
|
|
|
56d343 |
+ (set (match_operand:BLK 2) (unspec:BLK [(match_dup 2)] UNSPEC_HTM_FENCE))]
|
|
|
56d343 |
"TARGET_HTM"
|
|
|
56d343 |
"tsr. %0"
|
|
|
56d343 |
[(set_attr "type" "htm")
|
|
|
56d343 |
(set_attr "length" "4")])
|
|
|
56d343 |
|
|
|
56d343 |
-(define_insn "ttest"
|
|
|
56d343 |
+(define_expand "ttest"
|
|
|
56d343 |
+ [(parallel
|
|
|
56d343 |
+ [(set (match_operand:CC 0 "cc_reg_operand" "=x")
|
|
|
56d343 |
+ (unspec_volatile:CC [(const_int 0)] UNSPECV_HTM_TTEST))
|
|
|
56d343 |
+ (set (match_dup 1) (unspec:BLK [(match_dup 1)] UNSPEC_HTM_FENCE))])]
|
|
|
56d343 |
+ "TARGET_HTM"
|
|
|
56d343 |
+{
|
|
|
56d343 |
+ operands[1] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
|
|
|
56d343 |
+ MEM_VOLATILE_P (operands[1]) = 1;
|
|
|
56d343 |
+})
|
|
|
56d343 |
+
|
|
|
56d343 |
+(define_insn "*ttest"
|
|
|
56d343 |
[(set (match_operand:CC 0 "cc_reg_operand" "=x")
|
|
|
56d343 |
- (unspec_volatile:CC [(const_int 0)]
|
|
|
56d343 |
- UNSPECV_HTM_TTEST))]
|
|
|
56d343 |
+ (unspec_volatile:CC [(const_int 0)] UNSPECV_HTM_TTEST))
|
|
|
56d343 |
+ (set (match_operand:BLK 1) (unspec:BLK [(match_dup 1)] UNSPEC_HTM_FENCE))]
|
|
|
56d343 |
"TARGET_HTM"
|
|
|
56d343 |
"tabortwci. 0,1,0"
|
|
|
56d343 |
[(set_attr "type" "htm")
|
|
|
56d343 |
--- gcc/config/rs6000/rs6000-c.c (revision 228826)
|
|
|
56d343 |
+++ gcc/config/rs6000/rs6000-c.c (revision 228827)
|
|
|
56d343 |
@@ -372,7 +372,11 @@ rs6000_target_modify_macros (bool define
|
|
|
56d343 |
if ((flags & OPTION_MASK_VSX) != 0)
|
|
|
56d343 |
rs6000_define_or_undefine_macro (define_p, "__VSX__");
|
|
|
56d343 |
if ((flags & OPTION_MASK_HTM) != 0)
|
|
|
56d343 |
- rs6000_define_or_undefine_macro (define_p, "__HTM__");
|
|
|
56d343 |
+ {
|
|
|
56d343 |
+ rs6000_define_or_undefine_macro (define_p, "__HTM__");
|
|
|
56d343 |
+ /* Tell the user that our HTM insn patterns act as memory barriers. */
|
|
|
56d343 |
+ rs6000_define_or_undefine_macro (define_p, "__TM_FENCE__");
|
|
|
56d343 |
+ }
|
|
|
56d343 |
if ((flags & OPTION_MASK_P8_VECTOR) != 0)
|
|
|
56d343 |
rs6000_define_or_undefine_macro (define_p, "__POWER8_VECTOR__");
|
|
|
56d343 |
if ((flags & OPTION_MASK_QUAD_MEMORY) != 0)
|
|
|
56d343 |
--- gcc/testsuite/gcc.target/powerpc/htm-tabort-no-r0.c (revision 0)
|
|
|
56d343 |
+++ gcc/testsuite/gcc.target/powerpc/htm-tabort-no-r0.c (revision 226532)
|
|
|
56d343 |
@@ -0,0 +1,12 @@
|
|
|
56d343 |
+/* { dg-do compile { target { powerpc*-*-* } } } */
|
|
|
56d343 |
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
|
|
|
56d343 |
+/* { dg-require-effective-target powerpc_htm_ok } */
|
|
|
56d343 |
+/* { dg-options "-O2 -mhtm -ffixed-r3 -ffixed-r4 -ffixed-r5 -ffixed-r6 -ffixed-r7 -ffixed-r8 -ffixed-r9 -ffixed-r10 -ffixed-r11 -ffixed-r12" } */
|
|
|
56d343 |
+
|
|
|
56d343 |
+/* { dg-final { scan-assembler-not "tabort\\.\[ \t\]0" } } */
|
|
|
56d343 |
+
|
|
|
56d343 |
+int
|
|
|
56d343 |
+foo (void)
|
|
|
56d343 |
+{
|
|
|
56d343 |
+ return __builtin_tabort (10);
|
|
|
56d343 |
+}
|