From eeb5bc939fd2b771a58b7cea86c7125f725a1ae7 Mon Sep 17 00:00:00 2001 From: CentOS Sources Date: Jan 21 2020 20:49:57 +0000 Subject: import gcc-toolset-9-binutils-2.32-17.el8 --- diff --git a/SOURCES/binutils-CVE-2019-14250.patch b/SOURCES/binutils-CVE-2019-14250.patch new file mode 100644 index 0000000..c37b92e --- /dev/null +++ b/SOURCES/binutils-CVE-2019-14250.patch @@ -0,0 +1,17 @@ +--- binutils.orig/libiberty/simple-object-elf.c 2019-08-09 14:13:51.677330065 +0100 ++++ binutils-2.32/libiberty/simple-object-elf.c 2019-08-09 14:14:31.177076298 +0100 +@@ -549,6 +549,14 @@ simple_object_elf_match (unsigned char h + return NULL; + } + ++ if (eor->shstrndx == 0) ++ { ++ *errmsg = "invalid ELF shstrndx == 0"; ++ *err = 0; ++ XDELETE (eor); ++ return NULL; ++ } ++ + return (void *) eor; + } + diff --git a/SOURCES/binutils-CVE-2019-14444.patch b/SOURCES/binutils-CVE-2019-14444.patch new file mode 100644 index 0000000..ad554f5 --- /dev/null +++ b/SOURCES/binutils-CVE-2019-14444.patch @@ -0,0 +1,11 @@ +--- binutils.orig/binutils/readelf.c 2019-08-13 10:03:33.518792590 +0100 ++++ binutils-2.32/binutils/readelf.c 2019-08-13 10:04:22.885418269 +0100 +@@ -13234,7 +13234,7 @@ apply_relocations (Filedata * + } + + rloc = start + rp->r_offset; +- if ((rloc + reloc_size) > end || (rloc < start)) ++ if (rloc >= end || (rloc + reloc_size) > end || (rloc < start)) + { + warn (_("skipping invalid relocation offset 0x%lx in section %s\n"), + (unsigned long) rp->r_offset, diff --git a/SOURCES/binutils-CVE-2019-17450.patch b/SOURCES/binutils-CVE-2019-17450.patch new file mode 100644 index 0000000..c664ee8 --- /dev/null +++ b/SOURCES/binutils-CVE-2019-17450.patch @@ -0,0 +1,62 @@ +--- binutils.orig/bfd/dwarf2.c 2019-11-13 11:49:52.211121564 +0000 ++++ binutils-2.33.1/bfd/dwarf2.c 2019-11-13 11:53:26.991423055 +0000 +@@ -2813,8 +2813,8 @@ static bfd_boolean comp_unit_maybe_decod + + static bfd_boolean + find_abstract_instance (struct comp_unit * unit, +- bfd_byte * orig_info_ptr, + struct attribute * attr_ptr, ++ unsigned int recur_count, + const char ** pname, + bfd_boolean * is_linkage, + char ** filename_ptr, +@@ -2829,6 +2829,14 @@ find_abstract_instance (struct comp_unit + struct attribute attr; + const char *name = NULL; + ++ if (recur_count == 100) ++ { ++ _bfd_error_handler ++ (_("DWARF error: abstract instance recursion detected")); ++ bfd_set_error (bfd_error_bad_value); ++ return FALSE; ++ } ++ + /* DW_FORM_ref_addr can reference an entry in a different CU. It + is an offset from the .debug_info section, not the current CU. */ + if (attr_ptr->form == DW_FORM_ref_addr) +@@ -2962,15 +2970,7 @@ find_abstract_instance (struct comp_unit + info_ptr, info_ptr_end); + if (info_ptr == NULL) + break; +- /* It doesn't ever make sense for DW_AT_specification to +- refer to the same DIE. Stop simple recursion. */ +- if (info_ptr == orig_info_ptr) +- { +- _bfd_error_handler +- (_("DWARF error: abstract instance recursion detected")); +- bfd_set_error (bfd_error_bad_value); +- return FALSE; +- } ++ + switch (attr.name) + { + case DW_AT_name: +@@ -2984,7 +2984,7 @@ find_abstract_instance (struct comp_unit + } + break; + case DW_AT_specification: +- if (!find_abstract_instance (unit, info_ptr, &attr, ++ if (!find_abstract_instance (unit, &attr, recur_count + 1, + &name, is_linkage, + filename_ptr, linenumber_ptr)) + return FALSE; +@@ -3200,7 +3200,7 @@ scan_unit_for_symbols (struct comp_unit + + case DW_AT_abstract_origin: + case DW_AT_specification: +- if (!find_abstract_instance (unit, info_ptr, &attr, ++ if (!find_abstract_instance (unit, &attr, 0, + &func->name, + &func->is_linkage, + &func->file, diff --git a/SOURCES/binutils-CVE-2019-17451.patch b/SOURCES/binutils-CVE-2019-17451.patch new file mode 100644 index 0000000..0f503a3 --- /dev/null +++ b/SOURCES/binutils-CVE-2019-17451.patch @@ -0,0 +1,20 @@ +--- binutils.orig/bfd/dwarf2.c 2019-11-13 11:32:09.395430104 +0000 ++++ binutils-2.33.1/bfd/dwarf2.c 2019-11-13 11:33:17.272899503 +0000 +@@ -4440,7 +4440,16 @@ _bfd_dwarf2_slurp_debug_info (bfd *abfd, + for (total_size = 0; + msec; + msec = find_debug_info (debug_bfd, debug_sections, msec)) +- total_size += msec->size; ++ { ++ /* Catch PR25070 testcase overflowing size calculation here. */ ++ if (total_size + msec->size < total_size ++ || total_size + msec->size < msec->size) ++ { ++ bfd_set_error (bfd_error_no_memory); ++ return FALSE; ++ } ++ total_size += msec->size; ++ } + + stash->info_ptr_memory = (bfd_byte *) bfd_malloc (total_size); + if (stash->info_ptr_memory == NULL) diff --git a/SOURCES/binutils-PELC-licence-corrections.patch b/SOURCES/binutils-PELC-licence-corrections.patch new file mode 100644 index 0000000..c0e7462 --- /dev/null +++ b/SOURCES/binutils-PELC-licence-corrections.patch @@ -0,0 +1,11 @@ +--- binutils.orig/gold/ftruncate.c 2019-06-25 11:36:51.074941484 +0100 ++++ binutils-2.32/gold/ftruncate.c 2019-06-25 11:37:28.108690037 +0100 +@@ -1,7 +1,6 @@ + /* ftruncate emulations that work on some System V's. +- This file is in the public domain. */ + +-/* Copyright (C) 2012-2019 Free Software Foundation, Inc. ++ Copyright (C) 2012-2019 Free Software Foundation, Inc. + + This file is part of gold. + diff --git a/SOURCES/binutils-aarch64-STO_AARCH64_VARIANT_PCS.patch b/SOURCES/binutils-aarch64-STO_AARCH64_VARIANT_PCS.patch new file mode 100644 index 0000000..d0db8c8 --- /dev/null +++ b/SOURCES/binutils-aarch64-STO_AARCH64_VARIANT_PCS.patch @@ -0,0 +1,866 @@ +diff -rup binutils.orig/bfd/elfnn-aarch64.c binutils-2.32/bfd/elfnn-aarch64.c +--- binutils.orig/bfd/elfnn-aarch64.c 2019-07-02 17:30:19.407892712 +0100 ++++ binutils-2.32/bfd/elfnn-aarch64.c 2019-07-02 17:35:21.874749884 +0100 +@@ -2579,6 +2579,9 @@ struct elf_aarch64_link_hash_table + unsigned int top_index; + asection **input_list; + ++ /* JUMP_SLOT relocs for variant PCS symbols may be present. */ ++ int variant_pcs; ++ + /* The offset into splt of the PLT entry for the TLS descriptor + resolver. Special values are 0, if not necessary (or not found + to be necessary yet), and -1 if needed but not determined +@@ -2790,6 +2793,31 @@ elfNN_aarch64_copy_indirect_symbol (stru + _bfd_elf_link_hash_copy_indirect (info, dir, ind); + } + ++/* Merge non-visibility st_other attributes. */ ++ ++static void ++elfNN_aarch64_merge_symbol_attribute (struct elf_link_hash_entry *h, ++ const Elf_Internal_Sym *isym, ++ bfd_boolean definition ATTRIBUTE_UNUSED, ++ bfd_boolean dynamic ATTRIBUTE_UNUSED) ++{ ++ unsigned int isym_sto = isym->st_other & ~ELF_ST_VISIBILITY (-1); ++ unsigned int h_sto = h->other & ~ELF_ST_VISIBILITY (-1); ++ ++ if (isym_sto == h_sto) ++ return; ++ ++ if (isym_sto & ~STO_AARCH64_VARIANT_PCS) ++ /* Not fatal, this callback cannot fail. */ ++ _bfd_error_handler (_("unknown attribute for symbol `%s': 0x%02x"), ++ h->root.root.string, isym_sto); ++ ++ /* Note: Ideally we would warn about any attribute mismatch, but ++ this api does not allow that without substantial changes. */ ++ if (isym_sto & STO_AARCH64_VARIANT_PCS) ++ h->other |= STO_AARCH64_VARIANT_PCS; ++} ++ + /* Destroy an AArch64 elf linker hash table. */ + + static void +@@ -8370,6 +8398,12 @@ elfNN_aarch64_allocate_dynrelocs (struct + updated. */ + + htab->root.srelplt->reloc_count++; ++ ++ /* Mark the DSO in case R__JUMP_SLOT relocs against ++ variant PCS symbols are present. */ ++ if (h->other & STO_AARCH64_VARIANT_PCS) ++ htab->variant_pcs = 1; ++ + } + else + { +@@ -8958,6 +8992,10 @@ elfNN_aarch64_size_dynamic_sections (bfd + || !add_dynamic_entry (DT_JMPREL, 0)) + return FALSE; + ++ if (htab->variant_pcs ++ && !add_dynamic_entry (DT_AARCH64_VARIANT_PCS, 0)) ++ return FALSE; ++ + if (htab->tlsdesc_plt + && (!add_dynamic_entry (DT_TLSDESC_PLT, 0) + || !add_dynamic_entry (DT_TLSDESC_GOT, 0))) +@@ -9708,6 +9746,9 @@ const struct elf_size_info elfNN_aarch64 + #define elf_backend_copy_indirect_symbol \ + elfNN_aarch64_copy_indirect_symbol + ++#define elf_backend_merge_symbol_attribute \ ++ elfNN_aarch64_merge_symbol_attribute ++ + /* Create .dynbss, and .rela.bss sections in DYNOBJ, and set up shortcuts + to them in our hash. */ + #define elf_backend_create_dynamic_sections \ +diff -rup binutils.orig/binutils/readelf.c binutils-2.32/binutils/readelf.c +--- binutils.orig/binutils/readelf.c 2019-07-02 17:30:18.890896375 +0100 ++++ binutils-2.32/binutils/readelf.c 2019-07-02 17:32:25.008002901 +0100 +@@ -1797,6 +1797,19 @@ dump_relocations (Filedata * fi + } + + static const char * ++get_aarch64_dynamic_type (unsigned long type) ++{ ++ switch (type) ++ { ++ case DT_AARCH64_BTI_PLT: return "AARCH64_BTI_PLT"; ++ case DT_AARCH64_PAC_PLT: return "AARCH64_PAC_PLT"; ++ case DT_AARCH64_VARIANT_PCS: return "AARCH64_VARIANT_PCS"; ++ default: ++ return NULL; ++ } ++} ++ ++static const char * + get_mips_dynamic_type (unsigned long type) + { + switch (type) +@@ -2169,6 +2182,9 @@ get_dynamic_type (Filedata * filedata, u + + switch (filedata->file_header.e_machine) + { ++ case EM_AARCH64: ++ result = get_aarch64_dynamic_type (type); ++ break; + case EM_MIPS: + case EM_MIPS_RS3_LE: + result = get_mips_dynamic_type (type); +@@ -11054,6 +11070,22 @@ get_solaris_symbol_visibility (unsigned + } + + static const char * ++get_aarch64_symbol_other (unsigned int other) ++{ ++ static char buf[32]; ++ ++ if (other & STO_AARCH64_VARIANT_PCS) ++ { ++ other &= ~STO_AARCH64_VARIANT_PCS; ++ if (other == 0) ++ return "VARIANT_PCS"; ++ snprintf (buf, sizeof buf, "VARIANT_PCS | %x", other); ++ return buf; ++ } ++ return NULL; ++} ++ ++static const char * + get_mips_symbol_other (unsigned int other) + { + switch (other) +@@ -11164,6 +11196,9 @@ get_symbol_other (Filedata * filedata, u + + switch (filedata->file_header.e_machine) + { ++ case EM_AARCH64: ++ result = get_aarch64_symbol_other (other); ++ break; + case EM_MIPS: + result = get_mips_symbol_other (other); + break; +diff -rup binutils.orig/gas/config/tc-aarch64.c binutils-2.32/gas/config/tc-aarch64.c +--- binutils.orig/gas/config/tc-aarch64.c 2019-07-02 17:30:19.131894667 +0100 ++++ binutils-2.32/gas/config/tc-aarch64.c 2019-07-02 17:35:45.202584620 +0100 +@@ -1938,6 +1938,28 @@ s_aarch64_elf_cons (int nbytes) + demand_empty_rest_of_line (); + } + ++/* Mark symbol that it follows a variant PCS convention. */ ++ ++static void ++s_variant_pcs (int ignored ATTRIBUTE_UNUSED) ++{ ++ char *name; ++ char c; ++ symbolS *sym; ++ asymbol *bfdsym; ++ elf_symbol_type *elfsym; ++ ++ c = get_symbol_name (&name); ++ if (!*name) ++ as_bad (_("Missing symbol name in directive")); ++ sym = symbol_find_or_make (name); ++ restore_line_pointer (c); ++ demand_empty_rest_of_line (); ++ bfdsym = symbol_get_bfdsym (sym); ++ elfsym = elf_symbol_from (bfd_asymbol_bfd (bfdsym), bfdsym); ++ gas_assert (elfsym); ++ elfsym->internal_elf_sym.st_other |= STO_AARCH64_VARIANT_PCS; ++} + #endif /* OBJ_ELF */ + + /* Output a 32-bit word, but mark as an instruction. */ +@@ -2084,6 +2106,7 @@ const pseudo_typeS md_pseudo_table[] = { + {"long", s_aarch64_elf_cons, 4}, + {"xword", s_aarch64_elf_cons, 8}, + {"dword", s_aarch64_elf_cons, 8}, ++ {"variant_pcs", s_variant_pcs, 0}, + #endif + {0, 0, 0} + }; +@@ -9320,3 +9343,35 @@ aarch64_copy_symbol_attributes (symbolS + { + AARCH64_GET_FLAG (dest) = AARCH64_GET_FLAG (src); + } ++ ++#ifdef OBJ_ELF ++/* Same as elf_copy_symbol_attributes, but without copying st_other. ++ This is needed so AArch64 specific st_other values can be independently ++ specified for an IFUNC resolver (that is called by the dynamic linker) ++ and the symbol it resolves (aliased to the resolver). In particular, ++ if a function symbol has special st_other value set via directives, ++ then attaching an IFUNC resolver to that symbol should not override ++ the st_other setting. Requiring the directive on the IFUNC resolver ++ symbol would be unexpected and problematic in C code, where the two ++ symbols appear as two independent function declarations. */ ++ ++void ++aarch64_elf_copy_symbol_attributes (symbolS *dest, symbolS *src) ++{ ++ struct elf_obj_sy *srcelf = symbol_get_obj (src); ++ struct elf_obj_sy *destelf = symbol_get_obj (dest); ++ if (srcelf->size) ++ { ++ if (destelf->size == NULL) ++ destelf->size = XNEW (expressionS); ++ *destelf->size = *srcelf->size; ++ } ++ else ++ { ++ if (destelf->size != NULL) ++ free (destelf->size); ++ destelf->size = NULL; ++ } ++ S_SET_SIZE (dest, S_GET_SIZE (src)); ++} ++#endif +diff -rup binutils.orig/gas/config/tc-aarch64.h binutils-2.32/gas/config/tc-aarch64.h +--- binutils.orig/gas/config/tc-aarch64.h 2019-07-02 17:30:19.136894632 +0100 ++++ binutils-2.32/gas/config/tc-aarch64.h 2019-07-02 17:35:45.202584620 +0100 +@@ -130,6 +130,12 @@ void aarch64_copy_symbol_attributes (sym + (aarch64_copy_symbol_attributes (DEST, SRC)) + #endif + ++#ifdef OBJ_ELF ++void aarch64_elf_copy_symbol_attributes (symbolS *, symbolS *); ++#define OBJ_COPY_SYMBOL_ATTRIBUTES(DEST, SRC) \ ++ aarch64_elf_copy_symbol_attributes (DEST, SRC) ++#endif ++ + #define TC_START_LABEL(STR, NUL_CHAR, NEXT_CHAR) \ + (NEXT_CHAR == ':' || (NEXT_CHAR == '/' && aarch64_data_in_code ())) + #define tc_canonicalize_symbol_name(str) aarch64_canonicalize_symbol_name (str); +diff -rup binutils.orig/gas/doc/c-aarch64.texi binutils-2.32/gas/doc/c-aarch64.texi +--- binutils.orig/gas/doc/c-aarch64.texi 2019-07-02 17:30:19.125894710 +0100 ++++ binutils-2.32/gas/doc/c-aarch64.texi 2019-07-02 17:35:11.362824354 +0100 +@@ -425,6 +425,12 @@ should only be done if it is really nece + + @c VVVVVVVVVVVVVVVVVVVVVVVVVV + ++@cindex @code{.variant_pcs} directive, AArch64 ++@item .variant_pcs @var{symbol} ++This directive marks @var{symbol} referencing a function that may ++follow a variant procedure call standard with different register ++usage convention from the base procedure call standard. ++ + @c WWWWWWWWWWWWWWWWWWWWWWWWWW + @c XXXXXXXXXXXXXXXXXXXXXXXXXX + +diff -rup binutils.orig/include/elf/aarch64.h binutils-2.32/include/elf/aarch64.h +--- binutils.orig/include/elf/aarch64.h 2019-07-02 17:30:18.850896658 +0100 ++++ binutils-2.32/include/elf/aarch64.h 2019-07-02 17:32:55.678785616 +0100 +@@ -36,6 +36,15 @@ + #define SHF_COMDEF 0x80000000 /* Section may be multiply defined + in the input to a link step. */ + ++/* Processor specific dynamic array tags. */ ++#define DT_AARCH64_BTI_PLT (DT_LOPROC + 1) ++#define DT_AARCH64_PAC_PLT (DT_LOPROC + 3) ++#define DT_AARCH64_VARIANT_PCS (DT_LOPROC + 5) ++ ++/* AArch64-specific values for st_other. */ ++#define STO_AARCH64_VARIANT_PCS 0x80 /* Symbol may follow different call ++ convention from the base PCS. */ ++ + /* Relocation types. */ + + START_RELOC_NUMBERS (elf_aarch64_reloc_type) +diff -rup binutils.orig/ld/testsuite/ld-aarch64/aarch64-elf.exp binutils-2.32/ld/testsuite/ld-aarch64/aarch64-elf.exp +--- binutils.orig/ld/testsuite/ld-aarch64/aarch64-elf.exp 2019-07-02 17:30:18.922896148 +0100 ++++ binutils-2.32/ld/testsuite/ld-aarch64/aarch64-elf.exp 2019-07-02 17:35:21.875749878 +0100 +@@ -371,6 +371,10 @@ run_dump_test_lp64 "rela-abs-relative-op + + run_dump_test_lp64 "pie-bind-locally" + ++run_dump_test_lp64 "variant_pcs-r" ++run_dump_test_lp64 "variant_pcs-shared" ++run_dump_test_lp64 "variant_pcs-now" ++ + set aarch64elflinktests { + {"ld-aarch64/so with global symbol" "-shared" "" "" {copy-reloc-so.s} + {} "copy-reloc-so.so"} +--- /dev/null 2019-07-02 08:01:33.386842704 +0100 ++++ binutils-2.32/gas/testsuite/gas/aarch64/symbol-variant_pcs-1.d 2019-07-02 17:35:11.362824354 +0100 +@@ -0,0 +1,10 @@ ++#objdump: -t ++ ++.*: file format .* ++ ++SYMBOL TABLE: ++0+ l d \.text 0+ \.text ++0+ l d \.data 0+ \.data ++0+ l d \.bss 0+ \.bss ++0+ l \.text 0+ func ++0+ \*UND\* 0+ 0x80 foobar +--- /dev/null 2019-07-02 08:01:33.386842704 +0100 ++++ binutils-2.32/gas/testsuite/gas/aarch64/symbol-variant_pcs-1.s 2019-07-02 17:35:11.362824354 +0100 +@@ -0,0 +1,8 @@ ++.text ++.variant_pcs foobar ++func: ++ bl foobar ++ b foobar ++ ++.data ++.xword foobar +--- /dev/null 2019-07-02 08:01:33.386842704 +0100 ++++ binutils-2.32/gas/testsuite/gas/aarch64/symbol-variant_pcs-2.d 2019-07-02 17:35:11.362824354 +0100 +@@ -0,0 +1,9 @@ ++#objdump: -t ++ ++.*: file format .* ++ ++SYMBOL TABLE: ++0+ l d \.text 0+ \.text ++0+ l d \.data 0+ \.data ++0+ l d \.bss 0+ \.bss ++0+ l \.text 0+ 0x80 foo +--- /dev/null 2019-07-02 08:01:33.386842704 +0100 ++++ binutils-2.32/gas/testsuite/gas/aarch64/symbol-variant_pcs-2.s 2019-07-02 17:35:11.362824354 +0100 +@@ -0,0 +1,4 @@ ++.text ++.variant_pcs foo ++foo: ++ ret +--- /dev/null 2019-07-02 08:01:33.386842704 +0100 ++++ binutils-2.32/gas/testsuite/gas/aarch64/symbol-variant_pcs-3.s 2019-07-02 17:35:45.202584620 +0100 +@@ -0,0 +1,20 @@ ++.text ++.global foo_vpcs ++.global foo_base ++.global alias_vpcs ++.global alias_base ++ ++.variant_pcs foo_vpcs ++.variant_pcs alias_vpcs ++ ++foo_vpcs: ++foo_base: ++ bl foo_vpcs ++ bl foo_base ++ bl alias_vpcs ++ bl alias_base ++ ++/* Check that the STO_AARCH64_VARIANT_PCS is not affected by .set. */ ++ ++.set alias_base, foo_vpcs ++.set alias_vpcs, foo_base +--- /dev/null 2019-07-02 08:01:33.386842704 +0100 ++++ binutils-2.32/gas/testsuite/gas/aarch64/symbol-variant_pcs-3.d 2019-07-02 17:35:45.202584620 +0100 +@@ -0,0 +1,12 @@ ++#objdump: -t ++ ++.*: file format .* ++ ++SYMBOL TABLE: ++0+ l d \.text 0+ \.text ++0+ l d \.data 0+ \.data ++0+ l d \.bss 0+ \.bss ++0+ g \.text 0+ 0x80 foo_vpcs ++0+ g \.text 0+ foo_base ++0+ g \.text 0+ 0x80 alias_vpcs ++0+ g \.text 0+ alias_base +--- /dev/null 2019-07-02 08:01:33.386842704 +0100 ++++ binutils-2.32/ld/testsuite/ld-aarch64/variant_pcs-1.s 2019-07-02 17:35:21.875749878 +0100 +@@ -0,0 +1,59 @@ ++.text ++ ++.variant_pcs f_spec_global_default_def ++.variant_pcs f_spec_global_default_undef ++.variant_pcs f_spec_global_hidden_def ++.variant_pcs f_spec_local ++.variant_pcs f_spec_global_default_ifunc ++.variant_pcs f_spec_global_hidden_ifunc ++.variant_pcs f_spec_local_ifunc ++ ++.global f_spec_global_default_def ++.global f_spec_global_default_undef ++.global f_spec_global_hidden_def ++.global f_spec_global_default_ifunc ++.global f_spec_global_hidden_ifunc ++.global f_base_global_default_def ++.global f_base_global_default_undef ++.global f_base_global_hidden_def ++.global f_base_global_default_ifunc ++.global f_base_global_hidden_ifunc ++ ++.hidden f_spec_global_hidden_def ++.hidden f_spec_global_hidden_ifunc ++.hidden f_base_global_hidden_def ++.hidden f_base_global_hidden_ifunc ++ ++.type f_spec_global_default_ifunc, %gnu_indirect_function ++.type f_spec_global_hidden_ifunc, %gnu_indirect_function ++.type f_spec_local_ifunc, %gnu_indirect_function ++.type f_base_global_default_ifunc, %gnu_indirect_function ++.type f_base_global_hidden_ifunc, %gnu_indirect_function ++.type f_base_local_ifunc, %gnu_indirect_function ++ ++f_spec_global_default_def: ++f_spec_global_hidden_def: ++f_spec_local: ++f_base_global_default_def: ++f_base_global_hidden_def: ++f_base_local: ++f_spec_global_default_ifunc: ++f_spec_global_hidden_ifunc: ++f_spec_local_ifunc: ++f_base_global_default_ifunc: ++f_base_global_hidden_ifunc: ++f_base_local_ifunc: ++ bl f_spec_global_default_def ++ bl f_spec_global_default_undef ++ bl f_spec_global_hidden_def ++ bl f_spec_local ++ bl f_base_global_default_def ++ bl f_base_global_default_undef ++ bl f_base_global_hidden_def ++ bl f_base_local ++ bl f_spec_global_default_ifunc ++ bl f_spec_global_hidden_ifunc ++ bl f_spec_local_ifunc ++ bl f_base_global_default_ifunc ++ bl f_base_global_hidden_ifunc ++ bl f_base_local_ifunc +--- /dev/null 2019-07-02 08:01:33.386842704 +0100 ++++ binutils-2.32/ld/testsuite/ld-aarch64/variant_pcs-2.s 2019-07-02 17:35:21.875749878 +0100 +@@ -0,0 +1,47 @@ ++.text ++ ++.variant_pcs f_spec_global_default_def ++.variant_pcs f_spec_global_default_undef ++.variant_pcs f_spec_global_hidden_def ++.variant_pcs f_spec_local2 ++.variant_pcs f_spec_global_default_ifunc ++.variant_pcs f_spec_global_hidden_ifunc ++.variant_pcs f_spec_local2_ifunc ++ ++.global f_spec_global_default_def ++.global f_spec_global_default_undef ++.global f_spec_global_hidden_def ++.global f_spec_global_default_ifunc ++.global f_spec_global_hidden_ifunc ++.global f_base_global_default_def ++.global f_base_global_default_undef ++.global f_base_global_hidden_def ++.global f_base_global_default_ifunc ++.global f_base_global_hidden_ifunc ++ ++.hidden f_spec_global_hidden_def ++.hidden f_spec_global_hidden_ifunc ++.hidden f_base_global_hidden_def ++.hidden f_base_global_hidden_ifunc ++ ++.type f_spec_local2_ifunc, %gnu_indirect_function ++.type f_base_local2_ifunc, %gnu_indirect_function ++ ++f_spec_local2: ++f_base_local2: ++f_spec_local2_ifunc: ++f_base_local2_ifunc: ++ bl f_spec_global_default_def ++ bl f_spec_global_default_undef ++ bl f_spec_global_hidden_def ++ bl f_spec_local2 ++ bl f_base_global_default_def ++ bl f_base_global_default_undef ++ bl f_base_global_hidden_def ++ bl f_base_local2 ++ bl f_spec_global_default_ifunc ++ bl f_spec_global_hidden_ifunc ++ bl f_spec_local2_ifunc ++ bl f_base_global_default_ifunc ++ bl f_base_global_hidden_ifunc ++ bl f_base_local2_ifunc +--- /dev/null 2019-07-02 08:01:33.386842704 +0100 ++++ binutils-2.32/ld/testsuite/ld-aarch64/variant_pcs.ld 2019-07-02 17:35:37.100642017 +0100 +@@ -0,0 +1,23 @@ ++/* Script for .variant_pcs symbol tests. */ ++OUTPUT_ARCH(aarch64) ++ENTRY(_start) ++SECTIONS ++{ ++ /* Read-only sections, merged into text segment: */ ++ PROVIDE (__executable_start = 0x8000); . = 0x8000; ++ .text : ++ { ++ *(.before) ++ *(.text) ++ *(.after) ++ } =0 ++ . = 0x9000; ++ .got : { *(.got) *(.got.plt)} ++ . = 0x10000; ++ .rela.dyn : { *(.rela.ifunc) } ++ . = 0x11000; ++ .rela.plt : { *(.rela.plt) *(.rela.iplt) } ++ . = 0x12340000; ++ .far : { *(.far) } ++ .ARM.attributes 0 : { *(.ARM.atttributes) } ++} +--- /dev/null 2019-07-02 08:01:33.386842704 +0100 ++++ binutils-2.32/ld/testsuite/ld-aarch64/variant_pcs-now.d 2019-07-02 17:34:37.557063849 +0100 +@@ -0,0 +1,67 @@ ++#source: variant_pcs-1.s ++#source: variant_pcs-2.s ++#ld: -shared --hash-style=sysv -T variant_pcs.ld -z now ++#readelf: -rsW ++ ++Relocation section '\.rela\.plt' at offset 0x11000 contains 12 entries: ++ Offset Info Type Symbol's Value Symbol's Name \+ Addend ++0000000000009020 0000000100000402 R_AARCH64_JUMP_SLOT 0000000000000000 f_base_global_default_undef \+ 0 ++0000000000009028 0000000200000402 R_AARCH64_JUMP_SLOT 0000000000000000 f_spec_global_default_undef \+ 0 ++0000000000009030 0000000400000402 R_AARCH64_JUMP_SLOT 0000000000008000 f_base_global_default_def \+ 0 ++0000000000009038 0000000500000402 R_AARCH64_JUMP_SLOT 0000000000008000 f_spec_global_default_def \+ 0 ++0000000000009040 0000000000000408 R_AARCH64_IRELATIVE 8000 ++0000000000009048 0000000300000402 R_AARCH64_JUMP_SLOT f_spec_global_default_ifunc\(\) f_spec_global_default_ifunc \+ 0 ++0000000000009050 0000000000000408 R_AARCH64_IRELATIVE 8000 ++0000000000009058 0000000600000402 R_AARCH64_JUMP_SLOT f_base_global_default_ifunc\(\) f_base_global_default_ifunc \+ 0 ++0000000000009060 0000000000000408 R_AARCH64_IRELATIVE 8038 ++0000000000009068 0000000000000408 R_AARCH64_IRELATIVE 8000 ++0000000000009070 0000000000000408 R_AARCH64_IRELATIVE 8000 ++0000000000009078 0000000000000408 R_AARCH64_IRELATIVE 8038 ++ ++Symbol table '\.dynsym' contains 7 entries: ++ Num: Value Size Type Bind Vis Ndx Name ++ 0: 0000000000000000 0 NOTYPE LOCAL DEFAULT UND ++ 1: 0000000000000000 0 NOTYPE GLOBAL DEFAULT UND f_base_global_default_undef ++ 2: 0000000000000000 0 NOTYPE GLOBAL DEFAULT \[VARIANT_PCS\] UND f_spec_global_default_undef ++ 3: 0000000000008000 0 IFUNC GLOBAL DEFAULT \[VARIANT_PCS\] 1 f_spec_global_default_ifunc ++ 4: 0000000000008000 0 NOTYPE GLOBAL DEFAULT 1 f_base_global_default_def ++ 5: 0000000000008000 0 NOTYPE GLOBAL DEFAULT \[VARIANT_PCS\] 1 f_spec_global_default_def ++ 6: 0000000000008000 0 IFUNC GLOBAL DEFAULT 1 f_base_global_default_ifunc ++ ++Symbol table '\.symtab' contains 35 entries: ++ Num: Value Size Type Bind Vis Ndx Name ++ 0: 0000000000000000 0 NOTYPE LOCAL DEFAULT UND ++ 1: 0000000000008000 0 SECTION LOCAL DEFAULT 1 ++ 2: 0000000000008070 0 SECTION LOCAL DEFAULT 2 ++ 3: 0000000000009000 0 SECTION LOCAL DEFAULT 3 ++ 4: 0000000000009080 0 SECTION LOCAL DEFAULT 4 ++ 5: 0000000000011000 0 SECTION LOCAL DEFAULT 5 ++ 6: 0000000000011120 0 SECTION LOCAL DEFAULT 6 ++ 7: 00000000000111c8 0 SECTION LOCAL DEFAULT 7 ++ 8: 0000000000011270 0 SECTION LOCAL DEFAULT 8 ++ 9: 0000000000000000 0 FILE LOCAL DEFAULT ABS .*variant_pcs-1\.o ++ 10: 0000000000008000 0 NOTYPE LOCAL DEFAULT \[VARIANT_PCS\] 1 f_spec_local ++ 11: 0000000000008000 0 IFUNC LOCAL DEFAULT \[VARIANT_PCS\] 1 f_spec_local_ifunc ++ 12: 0000000000008000 0 IFUNC LOCAL DEFAULT 1 f_base_local_ifunc ++ 13: 0000000000008000 0 NOTYPE LOCAL DEFAULT 1 f_base_local ++ 14: 0000000000008000 0 NOTYPE LOCAL DEFAULT 1 \$x ++ 15: 0000000000000000 0 FILE LOCAL DEFAULT ABS .*variant_pcs-2\.o ++ 16: 0000000000008038 0 NOTYPE LOCAL DEFAULT \[VARIANT_PCS\] 1 f_spec_local2 ++ 17: 0000000000008038 0 IFUNC LOCAL DEFAULT \[VARIANT_PCS\] 1 f_spec_local2_ifunc ++ 18: 0000000000008038 0 IFUNC LOCAL DEFAULT 1 f_base_local2_ifunc ++ 19: 0000000000008038 0 NOTYPE LOCAL DEFAULT 1 f_base_local2 ++ 20: 0000000000008038 0 NOTYPE LOCAL DEFAULT 1 \$x ++ 21: 0000000000000000 0 FILE LOCAL DEFAULT ABS ++ 22: 0000000000009080 0 OBJECT LOCAL DEFAULT ABS _DYNAMIC ++ 23: 0000000000008000 0 NOTYPE LOCAL DEFAULT \[VARIANT_PCS\] 1 f_spec_global_hidden_def ++ 24: 0000000000008000 0 IFUNC LOCAL DEFAULT 1 f_base_global_hidden_ifunc ++ 25: 0000000000008000 0 NOTYPE LOCAL DEFAULT 1 f_base_global_hidden_def ++ 26: 0000000000009000 0 OBJECT LOCAL DEFAULT ABS _GLOBAL_OFFSET_TABLE_ ++ 27: 0000000000008000 0 IFUNC LOCAL DEFAULT \[VARIANT_PCS\] 1 f_spec_global_hidden_ifunc ++ 28: 0000000000008070 0 NOTYPE LOCAL DEFAULT 2 \$x ++ 29: 0000000000000000 0 NOTYPE GLOBAL DEFAULT UND f_base_global_default_undef ++ 30: 0000000000000000 0 NOTYPE GLOBAL DEFAULT \[VARIANT_PCS\] UND f_spec_global_default_undef ++ 31: 0000000000008000 0 IFUNC GLOBAL DEFAULT \[VARIANT_PCS\] 1 f_spec_global_default_ifunc ++ 32: 0000000000008000 0 NOTYPE GLOBAL DEFAULT 1 f_base_global_default_def ++ 33: 0000000000008000 0 NOTYPE GLOBAL DEFAULT \[VARIANT_PCS\] 1 f_spec_global_default_def ++ 34: 0000000000008000 0 IFUNC GLOBAL DEFAULT 1 f_base_global_default_ifunc +--- /dev/null 2019-07-02 08:01:33.386842704 +0100 ++++ binutils-2.32/ld/testsuite/ld-aarch64/variant_pcs-r.d 2019-07-02 17:35:35.244655166 +0100 +@@ -0,0 +1,60 @@ ++#source: variant_pcs-1.s ++#source: variant_pcs-2.s ++#ld: -r ++#readelf: -rsW ++ ++Relocation section '\.rela\.text' at offset .* contains 24 entries: ++ Offset Info Type Symbol's Value Symbol's Name \+ Addend ++0000000000000000 000000180000011b R_AARCH64_CALL26 0000000000000000 f_spec_global_default_def \+ 0 ++0000000000000004 000000110000011b R_AARCH64_CALL26 0000000000000000 f_spec_global_default_undef \+ 0 ++0000000000000008 000000120000011b R_AARCH64_CALL26 0000000000000000 f_spec_global_hidden_def \+ 0 ++0000000000000010 000000170000011b R_AARCH64_CALL26 0000000000000000 f_base_global_default_def \+ 0 ++0000000000000014 000000100000011b R_AARCH64_CALL26 0000000000000000 f_base_global_default_undef \+ 0 ++0000000000000018 000000150000011b R_AARCH64_CALL26 0000000000000000 f_base_global_hidden_def \+ 0 ++0000000000000020 000000140000011b R_AARCH64_CALL26 f_spec_global_default_ifunc\(\) f_spec_global_default_ifunc \+ 0 ++0000000000000024 000000160000011b R_AARCH64_CALL26 f_spec_global_hidden_ifunc\(\) f_spec_global_hidden_ifunc \+ 0 ++0000000000000028 000000060000011b R_AARCH64_CALL26 f_spec_local_ifunc\(\) f_spec_local_ifunc \+ 0 ++000000000000002c 000000190000011b R_AARCH64_CALL26 f_base_global_default_ifunc\(\) f_base_global_default_ifunc \+ 0 ++0000000000000030 000000130000011b R_AARCH64_CALL26 f_base_global_hidden_ifunc\(\) f_base_global_hidden_ifunc \+ 0 ++0000000000000034 000000070000011b R_AARCH64_CALL26 f_base_local_ifunc\(\) f_base_local_ifunc \+ 0 ++0000000000000038 000000180000011b R_AARCH64_CALL26 0000000000000000 f_spec_global_default_def \+ 0 ++000000000000003c 000000110000011b R_AARCH64_CALL26 0000000000000000 f_spec_global_default_undef \+ 0 ++0000000000000040 000000120000011b R_AARCH64_CALL26 0000000000000000 f_spec_global_hidden_def \+ 0 ++0000000000000048 000000170000011b R_AARCH64_CALL26 0000000000000000 f_base_global_default_def \+ 0 ++000000000000004c 000000100000011b R_AARCH64_CALL26 0000000000000000 f_base_global_default_undef \+ 0 ++0000000000000050 000000150000011b R_AARCH64_CALL26 0000000000000000 f_base_global_hidden_def \+ 0 ++0000000000000058 000000140000011b R_AARCH64_CALL26 f_spec_global_default_ifunc\(\) f_spec_global_default_ifunc \+ 0 ++000000000000005c 000000160000011b R_AARCH64_CALL26 f_spec_global_hidden_ifunc\(\) f_spec_global_hidden_ifunc \+ 0 ++0000000000000060 0000000c0000011b R_AARCH64_CALL26 f_spec_local2_ifunc\(\) f_spec_local2_ifunc \+ 0 ++0000000000000064 000000190000011b R_AARCH64_CALL26 f_base_global_default_ifunc\(\) f_base_global_default_ifunc \+ 0 ++0000000000000068 000000130000011b R_AARCH64_CALL26 f_base_global_hidden_ifunc\(\) f_base_global_hidden_ifunc \+ 0 ++000000000000006c 0000000d0000011b R_AARCH64_CALL26 f_base_local2_ifunc\(\) f_base_local2_ifunc \+ 0 ++ ++Symbol table '\.symtab' contains 26 entries: ++ Num: Value Size Type Bind Vis Ndx Name ++ 0: 0000000000000000 0 NOTYPE LOCAL DEFAULT UND ++ 1: 0000000000000000 0 SECTION LOCAL DEFAULT 1 ++ 2: 0000000000000000 0 SECTION LOCAL DEFAULT 3 ++ 3: 0000000000000000 0 SECTION LOCAL DEFAULT 4 ++ 4: 0000000000000000 0 FILE LOCAL DEFAULT ABS .*variant_pcs-1\.o ++ 5: 0000000000000000 0 NOTYPE LOCAL DEFAULT \[VARIANT_PCS\] 1 f_spec_local ++ 6: 0000000000000000 0 IFUNC LOCAL DEFAULT \[VARIANT_PCS\] 1 f_spec_local_ifunc ++ 7: 0000000000000000 0 IFUNC LOCAL DEFAULT 1 f_base_local_ifunc ++ 8: 0000000000000000 0 NOTYPE LOCAL DEFAULT 1 f_base_local ++ 9: 0000000000000000 0 NOTYPE LOCAL DEFAULT 1 \$x ++ 10: 0000000000000000 0 FILE LOCAL DEFAULT ABS .*variant_pcs-2\.o ++ 11: 0000000000000038 0 NOTYPE LOCAL DEFAULT \[VARIANT_PCS\] 1 f_spec_local2 ++ 12: 0000000000000038 0 IFUNC LOCAL DEFAULT \[VARIANT_PCS\] 1 f_spec_local2_ifunc ++ 13: 0000000000000038 0 IFUNC LOCAL DEFAULT 1 f_base_local2_ifunc ++ 14: 0000000000000038 0 NOTYPE LOCAL DEFAULT 1 f_base_local2 ++ 15: 0000000000000038 0 NOTYPE LOCAL DEFAULT 1 \$x ++ 16: 0000000000000000 0 NOTYPE GLOBAL DEFAULT UND f_base_global_default_undef ++ 17: 0000000000000000 0 NOTYPE GLOBAL DEFAULT \[VARIANT_PCS\] UND f_spec_global_default_undef ++ 18: 0000000000000000 0 NOTYPE GLOBAL HIDDEN \[VARIANT_PCS\] 1 f_spec_global_hidden_def ++ 19: 0000000000000000 0 IFUNC GLOBAL HIDDEN 1 f_base_global_hidden_ifunc ++ 20: 0000000000000000 0 IFUNC GLOBAL DEFAULT \[VARIANT_PCS\] 1 f_spec_global_default_ifunc ++ 21: 0000000000000000 0 NOTYPE GLOBAL HIDDEN 1 f_base_global_hidden_def ++ 22: 0000000000000000 0 IFUNC GLOBAL HIDDEN \[VARIANT_PCS\] 1 f_spec_global_hidden_ifunc ++ 23: 0000000000000000 0 NOTYPE GLOBAL DEFAULT 1 f_base_global_default_def ++ 24: 0000000000000000 0 NOTYPE GLOBAL DEFAULT \[VARIANT_PCS\] 1 f_spec_global_default_def ++ 25: 0000000000000000 0 IFUNC GLOBAL DEFAULT 1 f_base_global_default_ifunc +--- /dev/null 2019-07-02 08:01:33.386842704 +0100 ++++ binutils-2.32/ld/testsuite/ld-aarch64/variant_pcs-shared.d 2019-07-02 17:34:45.635006622 +0100 +@@ -0,0 +1,67 @@ ++#source: variant_pcs-1.s ++#source: variant_pcs-2.s ++#ld: -shared --hash-style=sysv -T variant_pcs.ld ++#readelf: -rsW ++ ++Relocation section '\.rela\.plt' at offset 0x11000 contains 12 entries: ++ Offset Info Type Symbol's Value Symbol's Name \+ Addend ++0000000000009020 0000000100000402 R_AARCH64_JUMP_SLOT 0000000000000000 f_base_global_default_undef \+ 0 ++0000000000009028 0000000200000402 R_AARCH64_JUMP_SLOT 0000000000000000 f_spec_global_default_undef \+ 0 ++0000000000009030 0000000400000402 R_AARCH64_JUMP_SLOT 0000000000008000 f_base_global_default_def \+ 0 ++0000000000009038 0000000500000402 R_AARCH64_JUMP_SLOT 0000000000008000 f_spec_global_default_def \+ 0 ++0000000000009040 0000000000000408 R_AARCH64_IRELATIVE 8000 ++0000000000009048 0000000300000402 R_AARCH64_JUMP_SLOT f_spec_global_default_ifunc\(\) f_spec_global_default_ifunc \+ 0 ++0000000000009050 0000000000000408 R_AARCH64_IRELATIVE 8000 ++0000000000009058 0000000600000402 R_AARCH64_JUMP_SLOT f_base_global_default_ifunc\(\) f_base_global_default_ifunc \+ 0 ++0000000000009060 0000000000000408 R_AARCH64_IRELATIVE 8038 ++0000000000009068 0000000000000408 R_AARCH64_IRELATIVE 8000 ++0000000000009070 0000000000000408 R_AARCH64_IRELATIVE 8000 ++0000000000009078 0000000000000408 R_AARCH64_IRELATIVE 8038 ++ ++Symbol table '\.dynsym' contains 7 entries: ++ Num: Value Size Type Bind Vis Ndx Name ++ 0: 0000000000000000 0 NOTYPE LOCAL DEFAULT UND ++ 1: 0000000000000000 0 NOTYPE GLOBAL DEFAULT UND f_base_global_default_undef ++ 2: 0000000000000000 0 NOTYPE GLOBAL DEFAULT \[VARIANT_PCS\] UND f_spec_global_default_undef ++ 3: 0000000000008000 0 IFUNC GLOBAL DEFAULT \[VARIANT_PCS\] 1 f_spec_global_default_ifunc ++ 4: 0000000000008000 0 NOTYPE GLOBAL DEFAULT 1 f_base_global_default_def ++ 5: 0000000000008000 0 NOTYPE GLOBAL DEFAULT \[VARIANT_PCS\] 1 f_spec_global_default_def ++ 6: 0000000000008000 0 IFUNC GLOBAL DEFAULT 1 f_base_global_default_ifunc ++ ++Symbol table '\.symtab' contains 35 entries: ++ Num: Value Size Type Bind Vis Ndx Name ++ 0: 0000000000000000 0 NOTYPE LOCAL DEFAULT UND ++ 1: 0000000000008000 0 SECTION LOCAL DEFAULT 1 ++ 2: 0000000000008070 0 SECTION LOCAL DEFAULT 2 ++ 3: 0000000000009000 0 SECTION LOCAL DEFAULT 3 ++ 4: 0000000000009080 0 SECTION LOCAL DEFAULT 4 ++ 5: 0000000000011000 0 SECTION LOCAL DEFAULT 5 ++ 6: 0000000000011120 0 SECTION LOCAL DEFAULT 6 ++ 7: 00000000000111c8 0 SECTION LOCAL DEFAULT 7 ++ 8: 0000000000011270 0 SECTION LOCAL DEFAULT 8 ++ 9: 0000000000000000 0 FILE LOCAL DEFAULT ABS .*variant_pcs-1\.o ++ 10: 0000000000008000 0 NOTYPE LOCAL DEFAULT \[VARIANT_PCS\] 1 f_spec_local ++ 11: 0000000000008000 0 IFUNC LOCAL DEFAULT \[VARIANT_PCS\] 1 f_spec_local_ifunc ++ 12: 0000000000008000 0 IFUNC LOCAL DEFAULT 1 f_base_local_ifunc ++ 13: 0000000000008000 0 NOTYPE LOCAL DEFAULT 1 f_base_local ++ 14: 0000000000008000 0 NOTYPE LOCAL DEFAULT 1 \$x ++ 15: 0000000000000000 0 FILE LOCAL DEFAULT ABS .*variant_pcs-2\.o ++ 16: 0000000000008038 0 NOTYPE LOCAL DEFAULT \[VARIANT_PCS\] 1 f_spec_local2 ++ 17: 0000000000008038 0 IFUNC LOCAL DEFAULT \[VARIANT_PCS\] 1 f_spec_local2_ifunc ++ 18: 0000000000008038 0 IFUNC LOCAL DEFAULT 1 f_base_local2_ifunc ++ 19: 0000000000008038 0 NOTYPE LOCAL DEFAULT 1 f_base_local2 ++ 20: 0000000000008038 0 NOTYPE LOCAL DEFAULT 1 \$x ++ 21: 0000000000000000 0 FILE LOCAL DEFAULT ABS ++ 22: 0000000000009080 0 OBJECT LOCAL DEFAULT ABS _DYNAMIC ++ 23: 0000000000008000 0 NOTYPE LOCAL DEFAULT \[VARIANT_PCS\] 1 f_spec_global_hidden_def ++ 24: 0000000000008000 0 IFUNC LOCAL DEFAULT 1 f_base_global_hidden_ifunc ++ 25: 0000000000008000 0 NOTYPE LOCAL DEFAULT 1 f_base_global_hidden_def ++ 26: 0000000000009000 0 OBJECT LOCAL DEFAULT ABS _GLOBAL_OFFSET_TABLE_ ++ 27: 0000000000008000 0 IFUNC LOCAL DEFAULT \[VARIANT_PCS\] 1 f_spec_global_hidden_ifunc ++ 28: 0000000000008070 0 NOTYPE LOCAL DEFAULT 2 \$x ++ 29: 0000000000000000 0 NOTYPE GLOBAL DEFAULT UND f_base_global_default_undef ++ 30: 0000000000000000 0 NOTYPE GLOBAL DEFAULT \[VARIANT_PCS\] UND f_spec_global_default_undef ++ 31: 0000000000008000 0 IFUNC GLOBAL DEFAULT \[VARIANT_PCS\] 1 f_spec_global_default_ifunc ++ 32: 0000000000008000 0 NOTYPE GLOBAL DEFAULT 1 f_base_global_default_def ++ 33: 0000000000008000 0 NOTYPE GLOBAL DEFAULT \[VARIANT_PCS\] 1 f_spec_global_default_def ++ 34: 0000000000008000 0 IFUNC GLOBAL DEFAULT 1 f_base_global_default_ifunc +--- binutils.orig/bfd/archive.c 2019-07-03 10:06:20.527408416 +0100 ++++ binutils-2.32/bfd/archive.c 2019-07-03 10:06:57.887142988 +0100 +@@ -1076,8 +1076,6 @@ do_slurp_coff_armap (bfd *abfd) + *stringend = 0; + for (i = 0; i < nsymz; i++) + { +- bfd_size_type len; +- + rawptr = raw_armap + i; + carsyms->file_offset = swap ((bfd_byte *) rawptr); + carsyms->name = stringbase; +diff -rup binutils.orig/ld/testsuite/ld-aarch64/variant_pcs-now.d binutils-2.32/ld/testsuite/ld-aarch64/variant_pcs-now.d +--- binutils.orig/ld/testsuite/ld-aarch64/variant_pcs-now.d 2019-07-03 10:06:20.012412075 +0100 ++++ binutils-2.32/ld/testsuite/ld-aarch64/variant_pcs-now.d 2019-07-03 10:20:51.959203582 +0100 +@@ -22,10 +22,10 @@ Symbol table '\.dynsym' contains 7 entri + Num: Value Size Type Bind Vis Ndx Name + 0: 0000000000000000 0 NOTYPE LOCAL DEFAULT UND + 1: 0000000000000000 0 NOTYPE GLOBAL DEFAULT UND f_base_global_default_undef +- 2: 0000000000000000 0 NOTYPE GLOBAL DEFAULT \[VARIANT_PCS\] UND f_spec_global_default_undef +- 3: 0000000000008000 0 IFUNC GLOBAL DEFAULT \[VARIANT_PCS\] 1 f_spec_global_default_ifunc ++ 2: 0000000000000000 0 NOTYPE GLOBAL DEFAULT UND f_spec_global_default_undef \[VARIANT_PCS\] ++ 3: 0000000000008000 0 IFUNC GLOBAL DEFAULT 1 f_spec_global_default_ifunc \[VARIANT_PCS\] + 4: 0000000000008000 0 NOTYPE GLOBAL DEFAULT 1 f_base_global_default_def +- 5: 0000000000008000 0 NOTYPE GLOBAL DEFAULT \[VARIANT_PCS\] 1 f_spec_global_default_def ++ 5: 0000000000008000 0 NOTYPE GLOBAL DEFAULT 1 f_spec_global_default_def \[VARIANT_PCS\] + 6: 0000000000008000 0 IFUNC GLOBAL DEFAULT 1 f_base_global_default_ifunc + + Symbol table '\.symtab' contains 35 entries: +@@ -40,28 +40,28 @@ Symbol table '\.symtab' contains 35 entr + 7: 00000000000111c8 0 SECTION LOCAL DEFAULT 7 + 8: 0000000000011270 0 SECTION LOCAL DEFAULT 8 + 9: 0000000000000000 0 FILE LOCAL DEFAULT ABS .*variant_pcs-1\.o +- 10: 0000000000008000 0 NOTYPE LOCAL DEFAULT \[VARIANT_PCS\] 1 f_spec_local +- 11: 0000000000008000 0 IFUNC LOCAL DEFAULT \[VARIANT_PCS\] 1 f_spec_local_ifunc ++ 10: 0000000000008000 0 NOTYPE LOCAL DEFAULT 1 f_spec_local \[VARIANT_PCS\] ++ 11: 0000000000008000 0 IFUNC LOCAL DEFAULT 1 f_spec_local_ifunc \[VARIANT_PCS\] + 12: 0000000000008000 0 IFUNC LOCAL DEFAULT 1 f_base_local_ifunc + 13: 0000000000008000 0 NOTYPE LOCAL DEFAULT 1 f_base_local + 14: 0000000000008000 0 NOTYPE LOCAL DEFAULT 1 \$x + 15: 0000000000000000 0 FILE LOCAL DEFAULT ABS .*variant_pcs-2\.o +- 16: 0000000000008038 0 NOTYPE LOCAL DEFAULT \[VARIANT_PCS\] 1 f_spec_local2 +- 17: 0000000000008038 0 IFUNC LOCAL DEFAULT \[VARIANT_PCS\] 1 f_spec_local2_ifunc ++ 16: 0000000000008038 0 NOTYPE LOCAL DEFAULT 1 f_spec_local2 \[VARIANT_PCS\] ++ 17: 0000000000008038 0 IFUNC LOCAL DEFAULT 1 f_spec_local2_ifunc \[VARIANT_PCS\] + 18: 0000000000008038 0 IFUNC LOCAL DEFAULT 1 f_base_local2_ifunc + 19: 0000000000008038 0 NOTYPE LOCAL DEFAULT 1 f_base_local2 + 20: 0000000000008038 0 NOTYPE LOCAL DEFAULT 1 \$x + 21: 0000000000000000 0 FILE LOCAL DEFAULT ABS + 22: 0000000000009080 0 OBJECT LOCAL DEFAULT ABS _DYNAMIC +- 23: 0000000000008000 0 NOTYPE LOCAL DEFAULT \[VARIANT_PCS\] 1 f_spec_global_hidden_def ++ 23: 0000000000008000 0 NOTYPE LOCAL DEFAULT 1 f_spec_global_hidden_def \[VARIANT_PCS\] + 24: 0000000000008000 0 IFUNC LOCAL DEFAULT 1 f_base_global_hidden_ifunc + 25: 0000000000008000 0 NOTYPE LOCAL DEFAULT 1 f_base_global_hidden_def + 26: 0000000000009000 0 OBJECT LOCAL DEFAULT ABS _GLOBAL_OFFSET_TABLE_ +- 27: 0000000000008000 0 IFUNC LOCAL DEFAULT \[VARIANT_PCS\] 1 f_spec_global_hidden_ifunc ++ 27: 0000000000008000 0 IFUNC LOCAL DEFAULT 1 f_spec_global_hidden_ifunc \[VARIANT_PCS\] + 28: 0000000000008070 0 NOTYPE LOCAL DEFAULT 2 \$x + 29: 0000000000000000 0 NOTYPE GLOBAL DEFAULT UND f_base_global_default_undef +- 30: 0000000000000000 0 NOTYPE GLOBAL DEFAULT \[VARIANT_PCS\] UND f_spec_global_default_undef +- 31: 0000000000008000 0 IFUNC GLOBAL DEFAULT \[VARIANT_PCS\] 1 f_spec_global_default_ifunc ++ 30: 0000000000000000 0 NOTYPE GLOBAL DEFAULT UND f_spec_global_default_undef \[VARIANT_PCS\] ++ 31: 0000000000008000 0 IFUNC GLOBAL DEFAULT 1 f_spec_global_default_ifunc \[VARIANT_PCS\] + 32: 0000000000008000 0 NOTYPE GLOBAL DEFAULT 1 f_base_global_default_def +- 33: 0000000000008000 0 NOTYPE GLOBAL DEFAULT \[VARIANT_PCS\] 1 f_spec_global_default_def ++ 33: 0000000000008000 0 NOTYPE GLOBAL DEFAULT 1 f_spec_global_default_def \[VARIANT_PCS\] + 34: 0000000000008000 0 IFUNC GLOBAL DEFAULT 1 f_base_global_default_ifunc +diff -rup binutils.orig/ld/testsuite/ld-aarch64/variant_pcs-r.d binutils-2.32/ld/testsuite/ld-aarch64/variant_pcs-r.d +--- binutils.orig/ld/testsuite/ld-aarch64/variant_pcs-r.d 2019-07-03 10:06:20.012412075 +0100 ++++ binutils-2.32/ld/testsuite/ld-aarch64/variant_pcs-r.d 2019-07-03 10:14:28.152933189 +0100 +@@ -37,24 +37,24 @@ Symbol table '\.symtab' contains 26 entr + 2: 0000000000000000 0 SECTION LOCAL DEFAULT 3 + 3: 0000000000000000 0 SECTION LOCAL DEFAULT 4 + 4: 0000000000000000 0 FILE LOCAL DEFAULT ABS .*variant_pcs-1\.o +- 5: 0000000000000000 0 NOTYPE LOCAL DEFAULT \[VARIANT_PCS\] 1 f_spec_local +- 6: 0000000000000000 0 IFUNC LOCAL DEFAULT \[VARIANT_PCS\] 1 f_spec_local_ifunc ++ 5: 0000000000000000 0 NOTYPE LOCAL DEFAULT 1 f_spec_local \[VARIANT_PCS\] ++ 6: 0000000000000000 0 IFUNC LOCAL DEFAULT 1 f_spec_local_ifunc \[VARIANT_PCS\] + 7: 0000000000000000 0 IFUNC LOCAL DEFAULT 1 f_base_local_ifunc + 8: 0000000000000000 0 NOTYPE LOCAL DEFAULT 1 f_base_local + 9: 0000000000000000 0 NOTYPE LOCAL DEFAULT 1 \$x + 10: 0000000000000000 0 FILE LOCAL DEFAULT ABS .*variant_pcs-2\.o +- 11: 0000000000000038 0 NOTYPE LOCAL DEFAULT \[VARIANT_PCS\] 1 f_spec_local2 +- 12: 0000000000000038 0 IFUNC LOCAL DEFAULT \[VARIANT_PCS\] 1 f_spec_local2_ifunc ++ 11: 0000000000000038 0 NOTYPE LOCAL DEFAULT 1 f_spec_local2 \[VARIANT_PCS\] ++ 12: 0000000000000038 0 IFUNC LOCAL DEFAULT 1 f_spec_local2_ifunc \[VARIANT_PCS\] + 13: 0000000000000038 0 IFUNC LOCAL DEFAULT 1 f_base_local2_ifunc + 14: 0000000000000038 0 NOTYPE LOCAL DEFAULT 1 f_base_local2 + 15: 0000000000000038 0 NOTYPE LOCAL DEFAULT 1 \$x + 16: 0000000000000000 0 NOTYPE GLOBAL DEFAULT UND f_base_global_default_undef +- 17: 0000000000000000 0 NOTYPE GLOBAL DEFAULT \[VARIANT_PCS\] UND f_spec_global_default_undef +- 18: 0000000000000000 0 NOTYPE GLOBAL HIDDEN \[VARIANT_PCS\] 1 f_spec_global_hidden_def ++ 17: 0000000000000000 0 NOTYPE GLOBAL DEFAULT UND f_spec_global_default_undef \[VARIANT_PCS\] ++ 18: 0000000000000000 0 NOTYPE GLOBAL HIDDEN 1 f_spec_global_hidden_def \[VARIANT_PCS\] + 19: 0000000000000000 0 IFUNC GLOBAL HIDDEN 1 f_base_global_hidden_ifunc +- 20: 0000000000000000 0 IFUNC GLOBAL DEFAULT \[VARIANT_PCS\] 1 f_spec_global_default_ifunc ++ 20: 0000000000000000 0 IFUNC GLOBAL DEFAULT 1 f_spec_global_default_ifunc \[VARIANT_PCS\] + 21: 0000000000000000 0 NOTYPE GLOBAL HIDDEN 1 f_base_global_hidden_def +- 22: 0000000000000000 0 IFUNC GLOBAL HIDDEN \[VARIANT_PCS\] 1 f_spec_global_hidden_ifunc ++ 22: 0000000000000000 0 IFUNC GLOBAL HIDDEN 1 f_spec_global_hidden_ifunc \[VARIANT_PCS\] + 23: 0000000000000000 0 NOTYPE GLOBAL DEFAULT 1 f_base_global_default_def +- 24: 0000000000000000 0 NOTYPE GLOBAL DEFAULT \[VARIANT_PCS\] 1 f_spec_global_default_def ++ 24: 0000000000000000 0 NOTYPE GLOBAL DEFAULT 1 f_spec_global_default_def \[VARIANT_PCS\] + 25: 0000000000000000 0 IFUNC GLOBAL DEFAULT 1 f_base_global_default_ifunc +diff -rup binutils.orig/ld/testsuite/ld-aarch64/variant_pcs-shared.d binutils-2.32/ld/testsuite/ld-aarch64/variant_pcs-shared.d +--- binutils.orig/ld/testsuite/ld-aarch64/variant_pcs-shared.d 2019-07-03 10:06:20.012412075 +0100 ++++ binutils-2.32/ld/testsuite/ld-aarch64/variant_pcs-shared.d 2019-07-03 10:19:00.760994532 +0100 +@@ -22,10 +22,10 @@ Symbol table '\.dynsym' contains 7 entri + Num: Value Size Type Bind Vis Ndx Name + 0: 0000000000000000 0 NOTYPE LOCAL DEFAULT UND + 1: 0000000000000000 0 NOTYPE GLOBAL DEFAULT UND f_base_global_default_undef +- 2: 0000000000000000 0 NOTYPE GLOBAL DEFAULT \[VARIANT_PCS\] UND f_spec_global_default_undef +- 3: 0000000000008000 0 IFUNC GLOBAL DEFAULT \[VARIANT_PCS\] 1 f_spec_global_default_ifunc ++ 2: 0000000000000000 0 NOTYPE GLOBAL DEFAULT UND f_spec_global_default_undef \[VARIANT_PCS\] ++ 3: 0000000000008000 0 IFUNC GLOBAL DEFAULT 1 f_spec_global_default_ifunc \[VARIANT_PCS\] + 4: 0000000000008000 0 NOTYPE GLOBAL DEFAULT 1 f_base_global_default_def +- 5: 0000000000008000 0 NOTYPE GLOBAL DEFAULT \[VARIANT_PCS\] 1 f_spec_global_default_def ++ 5: 0000000000008000 0 NOTYPE GLOBAL DEFAULT 1 f_spec_global_default_def \[VARIANT_PCS\] + 6: 0000000000008000 0 IFUNC GLOBAL DEFAULT 1 f_base_global_default_ifunc + + Symbol table '\.symtab' contains 35 entries: +@@ -40,28 +40,28 @@ Symbol table '\.symtab' contains 35 entr + 7: 00000000000111c8 0 SECTION LOCAL DEFAULT 7 + 8: 0000000000011270 0 SECTION LOCAL DEFAULT 8 + 9: 0000000000000000 0 FILE LOCAL DEFAULT ABS .*variant_pcs-1\.o +- 10: 0000000000008000 0 NOTYPE LOCAL DEFAULT \[VARIANT_PCS\] 1 f_spec_local +- 11: 0000000000008000 0 IFUNC LOCAL DEFAULT \[VARIANT_PCS\] 1 f_spec_local_ifunc ++ 10: 0000000000008000 0 NOTYPE LOCAL DEFAULT 1 f_spec_local \[VARIANT_PCS\] ++ 11: 0000000000008000 0 IFUNC LOCAL DEFAULT 1 f_spec_local_ifunc \[VARIANT_PCS\] + 12: 0000000000008000 0 IFUNC LOCAL DEFAULT 1 f_base_local_ifunc + 13: 0000000000008000 0 NOTYPE LOCAL DEFAULT 1 f_base_local + 14: 0000000000008000 0 NOTYPE LOCAL DEFAULT 1 \$x + 15: 0000000000000000 0 FILE LOCAL DEFAULT ABS .*variant_pcs-2\.o +- 16: 0000000000008038 0 NOTYPE LOCAL DEFAULT \[VARIANT_PCS\] 1 f_spec_local2 +- 17: 0000000000008038 0 IFUNC LOCAL DEFAULT \[VARIANT_PCS\] 1 f_spec_local2_ifunc ++ 16: 0000000000008038 0 NOTYPE LOCAL DEFAULT 1 f_spec_local2 \[VARIANT_PCS\] ++ 17: 0000000000008038 0 IFUNC LOCAL DEFAULT 1 f_spec_local2_ifunc \[VARIANT_PCS\] + 18: 0000000000008038 0 IFUNC LOCAL DEFAULT 1 f_base_local2_ifunc + 19: 0000000000008038 0 NOTYPE LOCAL DEFAULT 1 f_base_local2 + 20: 0000000000008038 0 NOTYPE LOCAL DEFAULT 1 \$x + 21: 0000000000000000 0 FILE LOCAL DEFAULT ABS + 22: 0000000000009080 0 OBJECT LOCAL DEFAULT ABS _DYNAMIC +- 23: 0000000000008000 0 NOTYPE LOCAL DEFAULT \[VARIANT_PCS\] 1 f_spec_global_hidden_def ++ 23: 0000000000008000 0 NOTYPE LOCAL DEFAULT 1 f_spec_global_hidden_def \[VARIANT_PCS\] + 24: 0000000000008000 0 IFUNC LOCAL DEFAULT 1 f_base_global_hidden_ifunc + 25: 0000000000008000 0 NOTYPE LOCAL DEFAULT 1 f_base_global_hidden_def + 26: 0000000000009000 0 OBJECT LOCAL DEFAULT ABS _GLOBAL_OFFSET_TABLE_ +- 27: 0000000000008000 0 IFUNC LOCAL DEFAULT \[VARIANT_PCS\] 1 f_spec_global_hidden_ifunc ++ 27: 0000000000008000 0 IFUNC LOCAL DEFAULT 1 f_spec_global_hidden_ifunc \[VARIANT_PCS\] + 28: 0000000000008070 0 NOTYPE LOCAL DEFAULT 2 \$x + 29: 0000000000000000 0 NOTYPE GLOBAL DEFAULT UND f_base_global_default_undef +- 30: 0000000000000000 0 NOTYPE GLOBAL DEFAULT \[VARIANT_PCS\] UND f_spec_global_default_undef +- 31: 0000000000008000 0 IFUNC GLOBAL DEFAULT \[VARIANT_PCS\] 1 f_spec_global_default_ifunc ++ 30: 0000000000000000 0 NOTYPE GLOBAL DEFAULT UND f_spec_global_default_undef \[VARIANT_PCS\] ++ 31: 0000000000008000 0 IFUNC GLOBAL DEFAULT 1 f_spec_global_default_ifunc \[VARIANT_PCS\] + 32: 0000000000008000 0 NOTYPE GLOBAL DEFAULT 1 f_base_global_default_def +- 33: 0000000000008000 0 NOTYPE GLOBAL DEFAULT \[VARIANT_PCS\] 1 f_spec_global_default_def ++ 33: 0000000000008000 0 NOTYPE GLOBAL DEFAULT 1 f_spec_global_default_def \[VARIANT_PCS\] + 34: 0000000000008000 0 IFUNC GLOBAL DEFAULT 1 f_base_global_default_ifunc diff --git a/SOURCES/binutils-gas-build-note-relocs.patch b/SOURCES/binutils-gas-build-note-relocs.patch new file mode 100644 index 0000000..52a4c0b --- /dev/null +++ b/SOURCES/binutils-gas-build-note-relocs.patch @@ -0,0 +1,55 @@ +--- binutils.orig/gas/write.c 2019-07-01 16:23:28.133707500 +0100 ++++ binutils-2.32/gas/write.c 2019-07-01 16:24:50.699130611 +0100 +@@ -1891,7 +1891,8 @@ create_obj_attrs_section (void) + static void + create_note_reloc (segT sec, + symbolS * sym, +- bfd_size_type offset, ++ bfd_size_type note_offset, ++ bfd_size_type desc2_offset, + int reloc_type, + bfd_vma addend, + char * note) +@@ -1901,10 +1902,10 @@ create_note_reloc (segT sec, + reloc = XNEW (struct reloc_list); + + /* We create a .b type reloc as resolve_reloc_expr_symbols() has already been called. */ +- reloc->u.b.sec = sec; +- reloc->u.b.s = symbol_get_bfdsym (sym); ++ reloc->u.b.sec = sec; ++ reloc->u.b.s = symbol_get_bfdsym (sym); + reloc->u.b.r.sym_ptr_ptr = & reloc->u.b.s; +- reloc->u.b.r.address = offset; ++ reloc->u.b.r.address = note_offset + desc2_offset; + reloc->u.b.r.addend = addend; + reloc->u.b.r.howto = bfd_reloc_type_lookup (stdoutput, reloc_type); + +@@ -1929,12 +1930,12 @@ create_note_reloc (segT sec, + if (target_big_endian) + { + if (bfd_arch_bits_per_address (stdoutput) <= 32) +- note[offset + 3] = addend; ++ note[desc2_offset + 3] = addend; + else +- note[offset + 7] = addend; ++ note[desc2_offset + 7] = addend; + } + else +- note[offset] = addend; ++ note[desc2_offset] = addend; + } + } + +@@ -2037,10 +2038,10 @@ maybe_generate_build_notes (void) + memcpy (note + 12, "GA$3a1", 8); + + /* Create a relocation to install the start address of the note... */ +- create_note_reloc (sec, sym, total_size + 20, desc_reloc, 0, note); ++ create_note_reloc (sec, sym, total_size, 20, desc_reloc, 0, note); + + /* ...and another one to install the end address. */ +- create_note_reloc (sec, sym, total_size + desc2_offset, desc_reloc, ++ create_note_reloc (sec, sym, total_size, desc2_offset, desc_reloc, + bfd_get_section_size (bsym->section), + note); + diff --git a/SOURCES/binutils-gold-mismatched-section-flags.patch b/SOURCES/binutils-gold-mismatched-section-flags.patch new file mode 100644 index 0000000..4125801 --- /dev/null +++ b/SOURCES/binutils-gold-mismatched-section-flags.patch @@ -0,0 +1,36 @@ +diff -rup binutils.orig/gold/layout.cc binutils-2.32/gold/layout.cc +--- binutils.orig/gold/layout.cc 2019-06-24 14:37:36.013086899 +0100 ++++ binutils-2.32/gold/layout.cc 2019-06-24 14:41:40.054517479 +0100 +@@ -868,6 +868,7 @@ Layout::get_output_section(const char* n + && (same_name->flags() & elfcpp::SHF_TLS) == 0) + os = same_name; + } ++#if 0 /* BZ 1722715, PR 17556. */ + else if ((flags & elfcpp::SHF_TLS) == 0) + { + elfcpp::Elf_Xword zero_flags = 0; +@@ -878,6 +879,7 @@ Layout::get_output_section(const char* n + if (p != this->section_name_map_.end()) + os = p->second; + } ++#endif + } + + if (os == NULL) +diff -rup binutils.orig/gold/object.cc binutils-2.32/gold/object.cc +--- binutils.orig/gold/object.cc 2019-06-24 14:37:36.012086906 +0100 ++++ binutils-2.32/gold/object.cc 2019-06-24 14:39:59.287165501 +0100 +@@ -1644,6 +1644,13 @@ Sized_relobj_file::do_ + omit[i] = true; + } + ++ // Skip empty sections without flags. ++ if (!(shdr.get_sh_flags() & ~elfcpp::SHF_GROUP) ++ && !shdr.get_sh_size()) ++ { ++ omit[i] = true; ++ } ++ + bool discard = omit[i]; + if (!discard) + { diff --git a/SOURCES/binutils-ignore-duplicate-FDE-entries.patch b/SOURCES/binutils-ignore-duplicate-FDE-entries.patch new file mode 100644 index 0000000..2675759 --- /dev/null +++ b/SOURCES/binutils-ignore-duplicate-FDE-entries.patch @@ -0,0 +1,24 @@ +--- binutils-2.32.orig/bfd/elf-eh-frame.c 2019-06-26 07:05:43.839194746 -0400 ++++ binutils-2.32/bfd/elf-eh-frame.c 2019-06-26 07:32:37.124219479 -0400 +@@ -2478,11 +2478,16 @@ write_dwarf_eh_frame_hdr (bfd *abfd, str + != sec->output_section->vma + val)) + overflow = TRUE; + bfd_put_32 (abfd, val, contents + EH_FRAME_HDR_SIZE + i * 8 + 8); +- if (i != 0 +- && (hdr_info->u.dwarf.array[i].initial_loc +- < (hdr_info->u.dwarf.array[i - 1].initial_loc +- + hdr_info->u.dwarf.array[i - 1].range))) +- overlap = TRUE; ++ if (i != 0) ++ { ++ struct eh_frame_array_ent * this_entry = hdr_info->u.dwarf.array + i; ++ struct eh_frame_array_ent * prev_entry = hdr_info->u.dwarf.array + (i - 1); ++ ++ if (this_entry->initial_loc < prev_entry->initial_loc + prev_entry->range ++ && (this_entry->initial_loc != prev_entry->initial_loc ++ || this_entry->range != prev_entry->range)) ++ overlap = TRUE; ++ } + } + if (overflow) + _bfd_error_handler (_(".eh_frame_hdr entry overflow")); diff --git a/SOURCES/binutils-no-builder-comment-in-bfd-stdint.patch b/SOURCES/binutils-no-builder-comment-in-bfd-stdint.patch new file mode 100644 index 0000000..d8d5f4f --- /dev/null +++ b/SOURCES/binutils-no-builder-comment-in-bfd-stdint.patch @@ -0,0 +1,19 @@ +--- binutils.orig/bfd/configure 2019-06-24 14:37:35.984087086 +0100 ++++ binutils-2.32/bfd/configure 2019-06-24 17:32:52.515541752 +0100 +@@ -18865,11 +18865,11 @@ _LT_EOF + esac + done ;; + "bfd_stdint.h":C) +-if test "$GCC" = yes; then +- echo "/* generated for " `$CC --version | sed 1q` "*/" > tmp-stdint.h +-else +- echo "/* generated for $CC */" > tmp-stdint.h +-fi ++ ++ ++ ++ ++ + + sed 's/^ *//' >> tmp-stdint.h <note.namesz == pnote->note.namesz + && memcmp (back->note.namedata, pnote->note.namedata, pnote->note.namesz) == 0) + { +- fprintf (stderr, "DUP FUNXC\n"); + duplicate_found = TRUE; + pnote->note.type = 0; + break; diff --git a/SOURCES/binutils-s390x-arch13-descriptions.patch b/SOURCES/binutils-s390x-arch13-descriptions.patch new file mode 100644 index 0000000..de33997 --- /dev/null +++ b/SOURCES/binutils-s390x-arch13-descriptions.patch @@ -0,0 +1,355 @@ +diff -rup binutils.orig/gas/testsuite/gas/s390/zarch-arch13.d binutils-2.30/gas/testsuite/gas/s390/zarch-arch13.d +--- binutils.orig/gas/testsuite/gas/s390/zarch-arch13.d 2019-06-18 13:41:27.796052644 +0100 ++++ binutils-2.30/gas/testsuite/gas/s390/zarch-arch13.d 2019-06-18 13:48:01.504295109 +0100 +@@ -61,27 +61,27 @@ Disassembly of section .text: + .*: b9 e3 bd 69 [ ]*selgrnh %r6,%r9,%r11 + .*: b9 e3 bd 69 [ ]*selgrnh %r6,%r9,%r11 + .*: b9 e3 be 69 [ ]*selgrno %r6,%r9,%r11 +-.*: b9 c0 bd 69 [ ]*selhhhrnh %r6,%r9,%r11 +-.*: b9 c0 b1 69 [ ]*selhhhro %r6,%r9,%r11 +-.*: b9 c0 b2 69 [ ]*selhhhrh %r6,%r9,%r11 +-.*: b9 c0 b2 69 [ ]*selhhhrh %r6,%r9,%r11 +-.*: b9 c0 b3 69 [ ]*selhhhrnle %r6,%r9,%r11 +-.*: b9 c0 b4 69 [ ]*selhhhrl %r6,%r9,%r11 +-.*: b9 c0 b4 69 [ ]*selhhhrl %r6,%r9,%r11 +-.*: b9 c0 b5 69 [ ]*selhhhrnhe %r6,%r9,%r11 +-.*: b9 c0 b6 69 [ ]*selhhhrlh %r6,%r9,%r11 +-.*: b9 c0 b7 69 [ ]*selhhhrne %r6,%r9,%r11 +-.*: b9 c0 b7 69 [ ]*selhhhrne %r6,%r9,%r11 +-.*: b9 c0 b8 69 [ ]*selhhhre %r6,%r9,%r11 +-.*: b9 c0 b8 69 [ ]*selhhhre %r6,%r9,%r11 +-.*: b9 c0 b9 69 [ ]*selhhhrnlh %r6,%r9,%r11 +-.*: b9 c0 ba 69 [ ]*selhhhrhe %r6,%r9,%r11 +-.*: b9 c0 bb 69 [ ]*selhhhrnl %r6,%r9,%r11 +-.*: b9 c0 bb 69 [ ]*selhhhrnl %r6,%r9,%r11 +-.*: b9 c0 bc 69 [ ]*selhhhrle %r6,%r9,%r11 +-.*: b9 c0 bd 69 [ ]*selhhhrnh %r6,%r9,%r11 +-.*: b9 c0 bd 69 [ ]*selhhhrnh %r6,%r9,%r11 +-.*: b9 c0 be 69 [ ]*selhhhrno %r6,%r9,%r11 ++.*: b9 c0 bd 69 [ ]*selfhrnh %r6,%r9,%r11 ++.*: b9 c0 b1 69 [ ]*selfhro %r6,%r9,%r11 ++.*: b9 c0 b2 69 [ ]*selfhrh %r6,%r9,%r11 ++.*: b9 c0 b2 69 [ ]*selfhrh %r6,%r9,%r11 ++.*: b9 c0 b3 69 [ ]*selfhrnle %r6,%r9,%r11 ++.*: b9 c0 b4 69 [ ]*selfhrl %r6,%r9,%r11 ++.*: b9 c0 b4 69 [ ]*selfhrl %r6,%r9,%r11 ++.*: b9 c0 b5 69 [ ]*selfhrnhe %r6,%r9,%r11 ++.*: b9 c0 b6 69 [ ]*selfhrlh %r6,%r9,%r11 ++.*: b9 c0 b7 69 [ ]*selfhrne %r6,%r9,%r11 ++.*: b9 c0 b7 69 [ ]*selfhrne %r6,%r9,%r11 ++.*: b9 c0 b8 69 [ ]*selfhre %r6,%r9,%r11 ++.*: b9 c0 b8 69 [ ]*selfhre %r6,%r9,%r11 ++.*: b9 c0 b9 69 [ ]*selfhrnlh %r6,%r9,%r11 ++.*: b9 c0 ba 69 [ ]*selfhrhe %r6,%r9,%r11 ++.*: b9 c0 bb 69 [ ]*selfhrnl %r6,%r9,%r11 ++.*: b9 c0 bb 69 [ ]*selfhrnl %r6,%r9,%r11 ++.*: b9 c0 bc 69 [ ]*selfhrle %r6,%r9,%r11 ++.*: b9 c0 bd 69 [ ]*selfhrnh %r6,%r9,%r11 ++.*: b9 c0 bd 69 [ ]*selfhrnh %r6,%r9,%r11 ++.*: b9 c0 be 69 [ ]*selfhrno %r6,%r9,%r11 + .*: e6 f6 9f a0 d0 06 [ ]*vlbr %v15,4000\(%r6,%r9\),13 + .*: e6 f6 9f a0 10 06 [ ]*vlbrh %v15,4000\(%r6,%r9\) + .*: e6 f6 9f a0 20 06 [ ]*vlbrf %v15,4000\(%r6,%r9\) +@@ -130,11 +130,8 @@ Disassembly of section .text: + .*: e7 f1 42 00 87 8b [ ]*vstrsf %v15,%v17,%v20,%v24 + .*: e7 f1 42 d0 87 8b [ ]*vstrsf %v15,%v17,%v20,%v24,13 + .*: e7 f1 40 20 87 8b [ ]*vstrszb %v15,%v17,%v20,%v24 +-.*: e7 f1 40 f0 87 8b [ ]*vstrszb %v15,%v17,%v20,%v24,13 + .*: e7 f1 41 20 87 8b [ ]*vstrszh %v15,%v17,%v20,%v24 +-.*: e7 f1 41 f0 87 8b [ ]*vstrszh %v15,%v17,%v20,%v24,13 + .*: e7 f1 42 20 87 8b [ ]*vstrszf %v15,%v17,%v20,%v24 +-.*: e7 f1 42 f0 87 8b [ ]*vstrszf %v15,%v17,%v20,%v24,13 + .*: e7 f1 00 bc d4 c3 [ ]*vcfps %v15,%v17,13,12,11 + .*: e7 f1 00 cd 24 c3 [ ]*wcefb %v15,%v17,5,12 + .*: e7 f1 00 cd 24 c3 [ ]*wcefb %v15,%v17,5,12 +@@ -154,3 +151,4 @@ Disassembly of section .text: + .*: e6 6f 00 d0 00 52 [ ]*vcvbg %r6,%v15,13 + .*: e6 6f 00 dc 00 52 [ ]*vcvbg %r6,%v15,13,12 + .*: b9 3a 00 69 [ ]*kdsa %r6,%r9 ++.*: 07 07 [ ]*nopr %r7 +diff -rup binutils.orig/gas/testsuite/gas/s390/zarch-arch13.s binutils-2.30/gas/testsuite/gas/s390/zarch-arch13.s +--- binutils.orig/gas/testsuite/gas/s390/zarch-arch13.s 2019-06-18 13:41:27.794052658 +0100 ++++ binutils-2.30/gas/testsuite/gas/s390/zarch-arch13.s 2019-06-18 13:48:01.504295109 +0100 +@@ -55,27 +55,27 @@ foo: + selgrnh %r6,%r9,%r11 + selgrnp %r6,%r9,%r11 + selgrno %r6,%r9,%r11 +- selhhhr %r6,%r9,%r11,13 +- selhhhro %r6,%r9,%r11 +- selhhhrh %r6,%r9,%r11 +- selhhhrp %r6,%r9,%r11 +- selhhhrnle %r6,%r9,%r11 +- selhhhrl %r6,%r9,%r11 +- selhhhrm %r6,%r9,%r11 +- selhhhrnhe %r6,%r9,%r11 +- selhhhrlh %r6,%r9,%r11 +- selhhhrne %r6,%r9,%r11 +- selhhhrnz %r6,%r9,%r11 +- selhhhre %r6,%r9,%r11 +- selhhhrz %r6,%r9,%r11 +- selhhhrnlh %r6,%r9,%r11 +- selhhhrhe %r6,%r9,%r11 +- selhhhrnl %r6,%r9,%r11 +- selhhhrnm %r6,%r9,%r11 +- selhhhrle %r6,%r9,%r11 +- selhhhrnh %r6,%r9,%r11 +- selhhhrnp %r6,%r9,%r11 +- selhhhrno %r6,%r9,%r11 ++ selfhr %r6,%r9,%r11,13 ++ selfhro %r6,%r9,%r11 ++ selfhrh %r6,%r9,%r11 ++ selfhrp %r6,%r9,%r11 ++ selfhrnle %r6,%r9,%r11 ++ selfhrl %r6,%r9,%r11 ++ selfhrm %r6,%r9,%r11 ++ selfhrnhe %r6,%r9,%r11 ++ selfhrlh %r6,%r9,%r11 ++ selfhrne %r6,%r9,%r11 ++ selfhrnz %r6,%r9,%r11 ++ selfhre %r6,%r9,%r11 ++ selfhrz %r6,%r9,%r11 ++ selfhrnlh %r6,%r9,%r11 ++ selfhrhe %r6,%r9,%r11 ++ selfhrnl %r6,%r9,%r11 ++ selfhrnm %r6,%r9,%r11 ++ selfhrle %r6,%r9,%r11 ++ selfhrnh %r6,%r9,%r11 ++ selfhrnp %r6,%r9,%r11 ++ selfhrno %r6,%r9,%r11 + vlbr %v15,4000(%r6,%r9),13 + vlbrh %v15,4000(%r6,%r9) + vlbrf %v15,4000(%r6,%r9) +@@ -124,11 +124,8 @@ foo: + vstrsf %v15,%v17,%v20,%v24 + vstrsf %v15,%v17,%v20,%v24,13 + vstrszb %v15,%v17,%v20,%v24 +- vstrszb %v15,%v17,%v20,%v24,13 + vstrszh %v15,%v17,%v20,%v24 +- vstrszh %v15,%v17,%v20,%v24,13 + vstrszf %v15,%v17,%v20,%v24 +- vstrszf %v15,%v17,%v20,%v24,13 + vcfps %v15,%v17,13,12,11 + vcefb %v15,%v17,13,12 + wcefb %v15,%v17,13,12 +diff -rup binutils.orig/opcodes/s390-opc.txt binutils-2.30/opcodes/s390-opc.txt +--- binutils.orig/opcodes/s390-opc.txt 2019-06-18 13:41:27.578054171 +0100 ++++ binutils-2.30/opcodes/s390-opc.txt 2019-06-18 13:48:01.505295102 +0100 +@@ -1889,106 +1889,120 @@ e70000000036 vlm VRS_VVRDU "vector load + e7000000000e vst VRX_VRRDU "vector store" arch12 zarch optparm + e7000000003e vstm VRS_VVRDU "vector store multiple" arch12 zarch optparm + ++ + # arch13 instructions + +-b9f5 ncrk RRF_R0RR2 " " arch13 zarch +-b9e5 ncgrk RRF_R0RR2 " " arch13 zarch +-e50a mvcrl SSE_RDRD " " arch13 zarch +-b974 nnrk RRF_R0RR2 " " arch13 zarch +-b964 nngrk RRF_R0RR2 " " arch13 zarch +-b976 nork RRF_R0RR2 " " arch13 zarch +-b966 nogrk RRF_R0RR2 " " arch13 zarch +-b977 nxrk RRF_R0RR2 " " arch13 zarch +-b967 nxgrk RRF_R0RR2 " " arch13 zarch +-b975 ocrk RRF_R0RR2 " " arch13 zarch +-b965 ocgrk RRF_R0RR2 " " arch13 zarch +-b9e1 popcnt RRF_U0RR " " arch13 zarch optparm +-b9f0 selr RRF_RURR " " arch13 zarch +-b9f00000 selr*20 RRF_R0RR3 " " arch13 zarch +-b9e3 selgr RRF_RURR " " arch13 zarch +-b9e30000 selgr*20 RRF_R0RR3 " " arch13 zarch +-b9c0 selhhhr RRF_RURR " " arch13 zarch +-b9c00000 selhhhr*20 RRF_R0RR3 " " arch13 zarch +- +-e60000000006 vlbr VRX_VRRDU " " arch13 zarch +-e60000001006 vlbrh VRX_VRRD " " arch13 zarch +-e60000002006 vlbrf VRX_VRRD " " arch13 zarch +-e60000003006 vlbrg VRX_VRRD " " arch13 zarch +-e60000004006 vlbrq VRX_VRRD " " arch13 zarch +- +-e60000000007 vler VRX_VRRDU " " arch13 zarch +-e60000001007 vlerh VRX_VRRD " " arch13 zarch +-e60000002007 vlerf VRX_VRRD " " arch13 zarch +-e60000003007 vlerg VRX_VRRD " " arch13 zarch +- +-e60000000004 vllebrz VRX_VRRDU " " arch13 zarch +-e60000001004 vllebrzh VRX_VRRD " " arch13 zarch +-e60000002004 vllebrzf VRX_VRRD " " arch13 zarch +-e60000003004 ldrv VRX_VRRD " " arch13 zarch +-e60000003004 vllebrzg VRX_VRRD " " arch13 zarch +-e60000006004 lerv VRX_VRRD " " arch13 zarch +-e60000006004 vllebrze VRX_VRRD " " arch13 zarch +- +-e60000000001 vlebrh VRX_VRRDU " " arch13 zarch +-e60000000003 vlebrf VRX_VRRDU " " arch13 zarch +-e60000000002 vlebrg VRX_VRRDU " " arch13 zarch +- +-e60000000005 vlbrrep VRX_VRRDU " " arch13 zarch +-e60000001005 vlbrreph VRX_VRRD " " arch13 zarch +-e60000002005 vlbrrepf VRX_VRRD " " arch13 zarch +-e60000003005 vlbrrepg VRX_VRRD " " arch13 zarch +- +-e6000000000e vstbr VRX_VRRDU " " arch13 zarch +-e6000000100e vstbrh VRX_VRRD " " arch13 zarch +-e6000000200e vstbrf VRX_VRRD " " arch13 zarch +-e6000000300e vstbrg VRX_VRRD " " arch13 zarch +-e6000000400e vstbrq VRX_VRRD " " arch13 zarch +- +-e6000000000f vster VRX_VRRDU " " arch13 zarch +-e6000000100f vsterh VRX_VRRD " " arch13 zarch +-e6000000200f vsterf VRX_VRRD " " arch13 zarch +-e6000000300f vsterg VRX_VRRD " " arch13 zarch +- +-e60000000009 vstebrh VRX_VRRDU " " arch13 zarch +-e6000000000b vstebrf VRX_VRRDU " " arch13 zarch +-e6000000000b sterv VRX_VRRD " " arch13 zarch +-e6000000000a vstebrg VRX_VRRDU " " arch13 zarch +-e6000000000a stdrv VRX_VRRD " " arch13 zarch +- +-e70000000086 vsld VRI_VVV0U " " arch13 zarch +-e70000000087 vsrd VRI_VVV0U " " arch13 zarch +- +-e7000000008b vstrs VRR_VVVUU0V " " arch13 zarch optparm +- +-e7000000008b vstrsb VRR_VVVU0VB " " arch13 zarch optparm +-e7000100008b vstrsh VRR_VVVU0VB " " arch13 zarch optparm +-e7000200008b vstrsf VRR_VVVU0VB " " arch13 zarch optparm +- +-e7000020008b vstrszb VRR_VVVU0VB2 " " arch13 zarch optparm +-e7000120008b vstrszh VRR_VVVU0VB2 " " arch13 zarch optparm +-e7000220008b vstrszf VRR_VVVU0VB2 " " arch13 zarch optparm +- +-e700000000c3 vcfps VRR_VV0UUU " " arch13 zarch +-e700000020c3 vcefb VRR_VV0UU " " arch13 zarch +-e700000820c3 wcefb VRR_VV0UU8 " " arch13 zarch +- +-e700000000c1 vcfpl VRR_VV0UUU " " arch13 zarch +-e700000020c1 vcelfb VRR_VV0UU " " arch13 zarch +-e700000820c1 wcelfb VRR_VV0UU8 " " arch13 zarch +- +-e700000000c2 vcsfp VRR_VV0UUU " " arch13 zarch +-e700000020c2 vcfeb VRR_VV0UU " " arch13 zarch +-e700000820c2 wcfeb VRR_VV0UU8 " " arch13 zarch +- +-e700000000c0 vclfp VRR_VV0UUU " " arch13 zarch +-e700000020c0 vclfeb VRR_VV0UU " " arch13 zarch +-e700000820c0 wclfeb VRR_VV0UU8 " " arch13 zarch + +-b939 dfltcc RRF_R0RR2 " " arch13 zarch ++# Miscellaneous Instruction Extensions Facility 2 ++ ++b9f5 ncrk RRF_R0RR2 "and with complement 32 bit" arch13 zarch ++b9e5 ncgrk RRF_R0RR2 "and with complement 64 bit" arch13 zarch ++e50a mvcrl SSE_RDRD "move right to left" arch13 zarch ++b974 nnrk RRF_R0RR2 "nand 32 bit" arch13 zarch ++b964 nngrk RRF_R0RR2 "nand 64 bit" arch13 zarch ++b976 nork RRF_R0RR2 "nor 32 bit" arch13 zarch ++b966 nogrk RRF_R0RR2 "nor 64 bit" arch13 zarch ++b977 nxrk RRF_R0RR2 "not exclusive or 32 bit" arch13 zarch ++b967 nxgrk RRF_R0RR2 "not exclusive or 64 bit" arch13 zarch ++b975 ocrk RRF_R0RR2 "or with complement 32 bit" arch13 zarch ++b965 ocgrk RRF_R0RR2 "or with complement 64 bit" arch13 zarch ++b9e1 popcnt RRF_U0RR "population count arch13" arch13 zarch optparm ++b9f0 selr RRF_RURR "select 32 bit" arch13 zarch ++b9f00000 selr*20 RRF_R0RR3 "select 32 bit" arch13 zarch ++b9e3 selgr RRF_RURR "select 64 bit" arch13 zarch ++b9e30000 selgr*20 RRF_R0RR3 "select 64 bit" arch13 zarch ++b9c0 selfhr RRF_RURR "select high" arch13 zarch ++b9c00000 selfhr*20 RRF_R0RR3 "select high" arch13 zarch ++ ++# Vector Enhancements Facility 2 ++ ++e60000000006 vlbr VRX_VRRDU "vector load byte reversed elements" arch13 zarch ++e60000001006 vlbrh VRX_VRRD "vector load byte reversed halfword elements" arch13 zarch ++e60000002006 vlbrf VRX_VRRD "vector load byte reversed word elements" arch13 zarch ++e60000003006 vlbrg VRX_VRRD "vector load byte reversed doubleword elements" arch13 zarch ++e60000004006 vlbrq VRX_VRRD "vector load byte reversed quadword elements" arch13 zarch ++ ++e60000000007 vler VRX_VRRDU "vector load elements reversed" arch13 zarch ++e60000001007 vlerh VRX_VRRD "vector load halfword elements reversed" arch13 zarch ++e60000002007 vlerf VRX_VRRD "vector load word elements reversed" arch13 zarch ++e60000003007 vlerg VRX_VRRD "vector load doubleword elements reversed" arch13 zarch ++ ++e60000000004 vllebrz VRX_VRRDU "vector load byte reversed element and zero" arch13 zarch ++e60000001004 vllebrzh VRX_VRRD "vector load byte reversed halfword element and zero" arch13 zarch ++e60000002004 vllebrzf VRX_VRRD "vector load byte reversed word element and zero" arch13 zarch ++e60000003004 ldrv VRX_VRRD "load byte reversed doubleword" arch13 zarch ++e60000003004 vllebrzg VRX_VRRD "vector load byte reversed doubleword element and zero" arch13 zarch ++e60000006004 lerv VRX_VRRD "load byte reversed word" arch13 zarch ++e60000006004 vllebrze VRX_VRRD "vector load byte reversed word element left-aligned and zero" arch13 zarch ++ ++e60000000001 vlebrh VRX_VRRDU "vector load byte reversed halfword element" arch13 zarch ++e60000000003 vlebrf VRX_VRRDU "vector load byte reversed word element" arch13 zarch ++e60000000002 vlebrg VRX_VRRDU "vector load byte reversed doubleword element" arch13 zarch ++ ++e60000000005 vlbrrep VRX_VRRDU "vector load byte reversed element and replicate" arch13 zarch ++e60000001005 vlbrreph VRX_VRRD "vector load byte reversed halfword element and replicate" arch13 zarch ++e60000002005 vlbrrepf VRX_VRRD "vector load byte reversed word element and replicate" arch13 zarch ++e60000003005 vlbrrepg VRX_VRRD "vector load byte reversed doubleword element and replicate" arch13 zarch ++ ++e6000000000e vstbr VRX_VRRDU "vector store byte reversed elements" arch13 zarch ++e6000000100e vstbrh VRX_VRRD "vector store byte reversed halfword elements" arch13 zarch ++e6000000200e vstbrf VRX_VRRD "vector store byte reversed word elements" arch13 zarch ++e6000000300e vstbrg VRX_VRRD "vector store byte reversed doubleword elements" arch13 zarch ++e6000000400e vstbrq VRX_VRRD "vector store byte reversed quadword elements" arch13 zarch ++ ++e6000000000f vster VRX_VRRDU "vector store elements reversed" arch13 zarch ++e6000000100f vsterh VRX_VRRD "vector store halfword elements reversed" arch13 zarch ++e6000000200f vsterf VRX_VRRD "vector store word elements reversed" arch13 zarch ++e6000000300f vsterg VRX_VRRD "vector store doubleword elements reversed" arch13 zarch ++ ++e60000000009 vstebrh VRX_VRRDU "vector store byte reversed halfword element" arch13 zarch ++e6000000000b vstebrf VRX_VRRDU "vector store byte reversed word element" arch13 zarch ++e6000000000b sterv VRX_VRRD "store byte reversed word" arch13 zarch ++e6000000000a vstebrg VRX_VRRDU "vector store byte reversed doubleword element" arch13 zarch ++e6000000000a stdrv VRX_VRRD "store byte reversed doubleword" arch13 zarch ++ ++e70000000086 vsld VRI_VVV0U "vector shift left double by bit" arch13 zarch ++e70000000087 vsrd VRI_VVV0U "vector shift right double by bit" arch13 zarch ++ ++e7000000008b vstrs VRR_VVVUU0V "vector string search" arch13 zarch optparm ++ ++e7000000008b vstrsb VRR_VVVU0VB "vector string search byte" arch13 zarch optparm ++e7000100008b vstrsh VRR_VVVU0VB "vector string search halfword" arch13 zarch optparm ++e7000200008b vstrsf VRR_VVVU0VB "vector string search word" arch13 zarch optparm ++ ++e7000020008b vstrszb VRR_VVV0V "vector string search byte zero" arch13 zarch ++e7000120008b vstrszh VRR_VVV0V "vector string search halfword zero" arch13 zarch ++e7000220008b vstrszf VRR_VVV0V "vector string search word zero" arch13 zarch ++ ++e700000000c3 vcfps VRR_VV0UUU "vector fp convert from fixed" arch13 zarch ++e700000020c3 vcefb VRR_VV0UU "vector fp convert from fixed 32 bit" arch13 zarch ++e700000820c3 wcefb VRR_VV0UU8 "vector fp convert from fixed 32 bit" arch13 zarch ++ ++e700000000c1 vcfpl VRR_VV0UUU "vector fp convert from logical" arch13 zarch ++e700000020c1 vcelfb VRR_VV0UU "vector fp convert from logical 32 bit" arch13 zarch ++e700000820c1 wcelfb VRR_VV0UU8 "vector fp convert from logical 32 bit" arch13 zarch ++ ++e700000000c2 vcsfp VRR_VV0UUU "vector fp convert to fixed" arch13 zarch ++e700000020c2 vcfeb VRR_VV0UU "vector fp convert to fixed 32 bit" arch13 zarch ++e700000820c2 wcfeb VRR_VV0UU8 "vector fp convert to fixed 32 bit" arch13 zarch ++ ++e700000000c0 vclfp VRR_VV0UUU "vector fp convert to logical" arch13 zarch ++e700000020c0 vclfeb VRR_VV0UU "vector fp convert to logical 32 bit" arch13 zarch ++e700000820c0 wclfeb VRR_VV0UU8 "vector fp convert to logical 32 bit" arch13 zarch ++ ++# Deflate conversion facility ++ ++b939 dfltcc RRF_R0RR2 "deflate conversion call" arch13 zarch ++ ++# Enhanced-Sort Facility ++ ++b938 sortl RRE_RR "sort lists" arch13 zarch ++ ++# Vector packed decimal enhancement facility + +-b938 sortl RRE_RR " " arch13 zarch ++e60000000050 vcvb VRR_RV0UU "vector convert to binary 32 bit" arch13 zarch optparm ++e60000000052 vcvbg VRR_RV0UU "vector convert to binary 64 bit" arch13 zarch optparm + +-e60000000050 vcvb VRR_RV0UU " " arch13 zarch optparm +-e60000000052 vcvbg VRR_RV0UU " " arch13 zarch optparm ++# Message Security Assist Extension 9 + +-b93a kdsa RRE_RR " " arch13 zarch ++b93a kdsa RRE_RR "compute digital signature authentication" arch13 zarch +Only in binutils-2.30/opcodes: s390-opc.txt.orig diff --git a/SOURCES/binutils-x86-JCC-Errata.patch b/SOURCES/binutils-x86-JCC-Errata.patch new file mode 100644 index 0000000..ef6e118 --- /dev/null +++ b/SOURCES/binutils-x86-JCC-Errata.patch @@ -0,0 +1,3747 @@ +diff -rupN binutils-2.32/gas/config/tc-i386.c binutils.new/gas/config/tc-i386.c +--- binutils-2.32/gas/config/tc-i386.c 2019-01-19 16:01:33.000000000 +0000 ++++ binutils.new/gas/config/tc-i386.c 2019-11-25 14:01:00.626325922 +0000 +@@ -351,6 +351,9 @@ struct _i386_insn + /* Has ZMM register operands. */ + bfd_boolean has_regzmm; + ++ /* Has GOTPC relocation. */ ++ bfd_boolean has_gotpc_reloc; ++ + /* RM and SIB are the modrm byte and the sib byte where the + addressing modes of this insn are encoded. */ + modrm_byte rm; +@@ -545,6 +548,8 @@ static enum flag_code flag_code; + static unsigned int object_64bit; + static unsigned int disallow_64bit_reloc; + static int use_rela_relocations = 0; ++/* __tls_get_addr/___tls_get_addr symbol for TLS. */ ++static const char *tls_get_addr; + + #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ + || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ +@@ -605,6 +610,21 @@ static int omit_lock_prefix = 0; + "lock addl $0, (%{re}sp)". */ + static int avoid_fence = 0; + ++/* Type of the previous instruction. */ ++static struct ++ { ++ segT seg; ++ const char *file; ++ const char *name; ++ unsigned int line; ++ enum last_insn_kind ++ { ++ last_insn_other = 0, ++ last_insn_directive, ++ last_insn_prefix ++ } kind; ++ } last_insn; ++ + /* 1 if the assembler should generate relax relocations. */ + + static int generate_relax_relocations +@@ -618,6 +638,31 @@ static enum check_kind + } + sse_check, operand_check = check_warning; + ++/* Non-zero if branches should be aligned within power of 2 boundary. */ ++static int align_branch_power = 0; ++ ++/* Types of branches to align. */ ++enum align_branch_kind ++ { ++ align_branch_none = 0, ++ align_branch_jcc = 1 << 0, ++ align_branch_fused = 1 << 1, ++ align_branch_jmp = 1 << 2, ++ align_branch_call = 1 << 3, ++ align_branch_indirect = 1 << 4, ++ align_branch_ret = 1 << 5 ++ }; ++ ++static unsigned int align_branch = (align_branch_jcc ++ | align_branch_fused ++ | align_branch_jmp); ++ ++/* The maximum padding size for fused jcc. */ ++#define MAX_FUSED_JCC_PADDING_SIZE 20 ++ ++/* The maximum number of prefixes added for an instruction. */ ++static unsigned int align_branch_prefix_size = 5; ++ + /* Optimization: + 1. Clear the REX_W bit with register operand if possible. + 2. Above plus use 128bit vector instruction to clear the full vector +@@ -721,12 +766,19 @@ int x86_cie_data_alignment; + /* Interface to relax_segment. + There are 3 major relax states for 386 jump insns because the + different types of jumps add different sizes to frags when we're +- figuring out what sort of jump to choose to reach a given label. */ ++ figuring out what sort of jump to choose to reach a given label. ++ ++ BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align ++ branches which are handled by md_estimate_size_before_relax() and ++ i386_generic_table_relax_frag(). */ + + /* Types. */ + #define UNCOND_JUMP 0 + #define COND_JUMP 1 + #define COND_JUMP86 2 ++#define BRANCH_PADDING 3 ++#define BRANCH_PREFIX 4 ++#define FUSED_JCC_PADDING 5 + + /* Sizes. */ + #define CODE16 1 +@@ -1345,6 +1397,12 @@ i386_generate_nops (fragS *fragP, char * + case rs_fill_nop: + case rs_align_code: + break; ++ case rs_machine_dependent: ++ /* Allow NOP padding for jumps and calls. */ ++ if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING ++ || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING) ++ break; ++ /* Fall through. */ + default: + return; + } +@@ -1489,7 +1547,7 @@ i386_generate_nops (fragS *fragP, char * + return; + } + } +- else ++ else if (fragP->fr_type != rs_machine_dependent) + fragP->fr_var = count; + + if ((count / max_single_nop_size) > max_number_of_nops) +@@ -2957,6 +3015,11 @@ md_begin (void) + x86_dwarf2_return_column = 8; + x86_cie_data_alignment = -4; + } ++ ++ /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it ++ can be turned into BRANCH_PREFIX frag. */ ++ if (align_branch_prefix_size > MAX_FUSED_JCC_PADDING_SIZE) ++ abort (); + } + + void +@@ -4386,6 +4449,17 @@ md_assemble (char *line) + + /* We are ready to output the insn. */ + output_insn (); ++ ++ last_insn.seg = now_seg; ++ ++ if (i.tm.opcode_modifier.isprefix) ++ { ++ last_insn.kind = last_insn_prefix; ++ last_insn.name = i.tm.name; ++ last_insn.file = as_where (&last_insn.line); ++ } ++ else ++ last_insn.kind = last_insn_other; + } + + static char * +@@ -8001,11 +8075,202 @@ x86_cleanup (void) + } + #endif + ++/* Return 1 for test, and, cmp, add, sub, inc and dec which may ++ be macro-fused with conditional jumps. */ ++ ++static int ++maybe_fused_with_jcc_p (void) ++{ ++ /* No RIP address. */ ++ if (i.base_reg && i.base_reg->reg_num == RegIP) ++ return 0; ++ ++ /* and, add, sub with destination register. */ ++ if (!strcmp (i.tm.name, "and") ++ || !strcmp (i.tm.name, "add") ++ || !strcmp (i.tm.name, "sub")) ++ return i.types[1].bitfield.reg; ++ ++ /* test, cmp with any register. */ ++ if (!strcmp (i.tm.name, "test") || !strcmp (i.tm.name, "cmp")) ++ return (i.types[0].bitfield.reg ++ || i.types[1].bitfield.reg); ++ ++ /* inc, dec with 16/32/64-bit register. */ ++ if (!strcmp (i.tm.name, "inc") || !strcmp (i.tm.name, "dec")) ++ return i.types[0].bitfield.reg; ++ ++ return 0; ++} ++ ++/* Return 1 if a FUSED_JCC_PADDING frag should be generated. */ ++ ++static int ++add_fused_jcc_padding_frag_p (void) ++{ ++ if (!align_branch_power ++ || now_seg == absolute_section ++ || !cpu_arch_flags.bitfield.cpui386 ++ || !(align_branch & align_branch_fused)) ++ return 0; ++ ++ if (maybe_fused_with_jcc_p ()) ++ { ++ if (last_insn.kind != last_insn_other ++ && last_insn.seg == now_seg) ++ { ++ if (flag_debug) ++ as_warn_where (last_insn.file, last_insn.line, ++ _("`%s` skips -malign-branch-boundary on `%s`"), ++ last_insn.name, i.tm.name); ++ return 0; ++ } ++ return 1; ++ } ++ ++ return 0; ++} ++ ++/* Return 1 if a BRANCH_PREFIX frag should be generated. */ ++ ++static int ++add_branch_prefix_frag_p (void) ++{ ++ if (!align_branch_power ++ || now_seg == absolute_section ++ || i.tm.cpu_flags.bitfield.cpupadlock ++ || !cpu_arch_flags.bitfield.cpui386) ++ return 0; ++ ++ /* Don't add prefix if it is a prefix or there is no operand. */ ++ if (!i.operands || i.tm.opcode_modifier.isprefix) ++ return 0; ++ ++ if (last_insn.kind != last_insn_other ++ && last_insn.seg == now_seg) ++ { ++ if (flag_debug) ++ as_warn_where (last_insn.file, last_insn.line, ++ _("`%s` skips -malign-branch-boundary on `%s`"), ++ last_insn.name, i.tm.name); ++ return 0; ++ } ++ ++ return 1; ++} ++ ++/* Return 1 if a BRANCH_PADDING frag should be generated. */ ++ ++static int ++add_branch_padding_frag_p (enum align_branch_kind *branch_p) ++{ ++ int add_padding; ++ ++ if (!align_branch_power ++ || now_seg == absolute_section ++ || !cpu_arch_flags.bitfield.cpui386) ++ return 0; ++ ++ add_padding = 0; ++ ++ /* Check for jcc and direct jmp. */ ++ if (i.tm.opcode_modifier.jump) ++ { ++ if (i.tm.base_opcode == JUMP_PC_RELATIVE) ++ { ++ *branch_p = align_branch_jmp; ++ add_padding = align_branch & align_branch_jmp; ++ } ++ else ++ { ++ *branch_p = align_branch_jcc; ++ if ((align_branch & align_branch_jcc)) ++ add_padding = 1; ++ } ++ } ++ else if (i.tm.base_opcode == 0xc2 ++ || i.tm.base_opcode == 0xc3 ++ || i.tm.base_opcode == 0xca ++ || i.tm.base_opcode == 0xcb) ++ { ++ *branch_p = align_branch_ret; ++ if ((align_branch & align_branch_ret)) ++ add_padding = 1; ++ } ++ else ++ { ++ if (i.tm.base_opcode == 0xe8) ++ { ++ *branch_p = align_branch_call; ++ if ((align_branch & align_branch_call)) ++ add_padding = 1; ++ } ++ else if (i.tm.base_opcode == 0xff ++ && (i.rm.reg == 2 || i.rm.reg == 4)) ++ { ++ *branch_p = align_branch_indirect; ++ if ((align_branch & align_branch_indirect)) ++ add_padding = 1; ++ } ++ ++ /* Check for indirect jmp, direct and indirect calls. */ ++ if (add_padding ++ && i.disp_operands ++ && tls_get_addr ++ && (i.op[0].disps->X_op == O_symbol ++ || (i.op[0].disps->X_op == O_subtract ++ && i.op[0].disps->X_op_symbol == GOT_symbol))) ++ { ++ symbolS *s = i.op[0].disps->X_add_symbol; ++ /* No padding to call to global or undefined tls_get_addr. */ ++ if ((S_IS_EXTERNAL (s) || !S_IS_DEFINED (s)) ++ && strcmp (S_GET_NAME (s), tls_get_addr) == 0) ++ return 0; ++ } ++ } ++ ++ if (add_padding ++ && last_insn.kind != last_insn_other ++ && last_insn.seg == now_seg) ++ { ++ if (flag_debug) ++ as_warn_where (last_insn.file, last_insn.line, ++ _("`%s` skips -malign-branch-boundary on `%s`"), ++ last_insn.name, i.tm.name); ++ return 0; ++ } ++ ++ return add_padding; ++} ++ ++static unsigned int ++encoding_length (const fragS *start_frag, offsetT start_off, ++ const char *frag_now_ptr) ++{ ++ unsigned int len = 0; ++ ++ if (start_frag != frag_now) ++ { ++ const fragS *fr = start_frag; ++ ++ do ++ { ++ len += fr->fr_fix; ++ fr = fr->fr_next; ++ } ++ while (fr && fr != frag_now); ++ } ++ ++ return len - start_off + (frag_now_ptr - frag_now->fr_literal); ++} ++ + static void + output_insn (void) + { + fragS *insn_start_frag; + offsetT insn_start_off; ++ fragS *fragP = NULL; ++ enum align_branch_kind branch = align_branch_none; + + #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) + if (IS_ELF && x86_used_note) +@@ -8100,6 +8365,30 @@ output_insn (void) + insn_start_frag = frag_now; + insn_start_off = frag_now_fix (); + ++ if (add_branch_padding_frag_p (&branch)) ++ { ++ char *p; ++ unsigned int max_branch_padding_size = 14; ++ ++ /* Align section to boundary. */ ++ record_alignment (now_seg, align_branch_power); ++ ++ /* Make room for padding. */ ++ frag_grow (max_branch_padding_size); ++ ++ /* Start of the padding. */ ++ p = frag_more (0); ++ ++ fragP = frag_now; ++ ++ frag_var (rs_machine_dependent, max_branch_padding_size, 0, ++ ENCODE_RELAX_STATE (BRANCH_PADDING, 0), ++ NULL, 0, p); ++ ++ fragP->tc_frag_data.branch_type = branch; ++ fragP->tc_frag_data.max_bytes = max_branch_padding_size; ++ } ++ + /* Output jumps. */ + if (i.tm.opcode_modifier.jump) + output_branch (); +@@ -8141,6 +8430,44 @@ output_insn (void) + i.prefix[LOCK_PREFIX] = 0; + } + ++ if (branch) ++ /* Skip if this is a branch. */ ++ ; ++ else if (add_fused_jcc_padding_frag_p ()) ++ { ++ unsigned int max_fused_padding_size ++ = MAX_FUSED_JCC_PADDING_SIZE; ++ ++ /* Make room for padding. */ ++ frag_grow (max_fused_padding_size); ++ p = frag_more (0); ++ ++ fragP = frag_now; ++ ++ frag_var (rs_machine_dependent, max_fused_padding_size, 0, ++ ENCODE_RELAX_STATE (FUSED_JCC_PADDING, 0), ++ NULL, 0, p); ++ ++ fragP->tc_frag_data.branch_type = align_branch_fused; ++ fragP->tc_frag_data.max_bytes = max_fused_padding_size; ++ } ++ else if (add_branch_prefix_frag_p ()) ++ { ++ unsigned int max_prefix_size = align_branch_prefix_size; ++ ++ /* Make room for padding. */ ++ frag_grow (max_prefix_size); ++ p = frag_more (0); ++ ++ fragP = frag_now; ++ ++ frag_var (rs_machine_dependent, max_prefix_size, 0, ++ ENCODE_RELAX_STATE (BRANCH_PREFIX, 0), ++ NULL, 0, p); ++ ++ fragP->tc_frag_data.max_bytes = max_prefix_size; ++ } ++ + /* Since the VEX/EVEX prefix contains the implicit prefix, we + don't need the explicit prefix. */ + if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex) +@@ -8276,6 +8603,88 @@ output_insn (void) + + if (i.imm_operands) + output_imm (insn_start_frag, insn_start_off); ++ ++ /* ++ * frag_now_fix () returning plain abs_section_offset when we're in the ++ * absolute section, and abs_section_offset not getting updated as data ++ * gets added to the frag breaks the logic below. ++ */ ++ if (now_seg != absolute_section) ++ { ++ j = encoding_length (insn_start_frag, insn_start_off, frag_more (0)); ++ if (fragP) ++ { ++ /* NB: Don't add prefix with GOTPC relocation since ++ output_disp() above depends on the fixed encoding ++ length. */ ++ unsigned int max = i.has_gotpc_reloc ? 0 : 15 - j; ++ /* Prefix count on the current instruction. */ ++ unsigned int count = !!is_any_vex_encoding (&i.tm); ++ unsigned int k; ++ for (k = 0; k < ARRAY_SIZE (i.prefix); k++) ++ if (i.prefix[k]) ++ count++; ++ ++ /* NB: prefix count + instruction size must be <= 15. */ ++ if (j > 15) ++ as_fatal (_("instruction length of %u bytes exceeds the limit of 15"), ++ j); ++ ++ if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) ++ == BRANCH_PREFIX) ++ { ++ /* Set the maximum prefix size in BRANCH_PREFIX ++ frag. */ ++ if (fragP->tc_frag_data.max_bytes > max) ++ fragP->tc_frag_data.max_bytes = max; ++ if (fragP->tc_frag_data.max_bytes > count) ++ fragP->tc_frag_data.max_bytes -= count; ++ else ++ fragP->tc_frag_data.max_bytes = 0; ++ } ++ else ++ { ++ /* Remember the maximum prefix size in FUSED_JCC_PADDING ++ frag. */ ++ unsigned int max_prefix_size; ++ if (align_branch_prefix_size > max) ++ max_prefix_size = max; ++ else ++ max_prefix_size = align_branch_prefix_size; ++ if (max_prefix_size > count) ++ fragP->tc_frag_data.max_prefix_length ++ = max_prefix_size - count; ++ } ++ ++ /* Use existing segment prefix if possible. Use CS ++ segment prefix in 64-bit mode. In 32-bit mode, use SS ++ segment prefix with ESP/EBP base register and use DS ++ segment prefix without ESP/EBP base register. */ ++ if (i.prefix[SEG_PREFIX]) ++ fragP->tc_frag_data.default_prefix = i.prefix[SEG_PREFIX]; ++ else if (flag_code == CODE_64BIT) ++ fragP->tc_frag_data.default_prefix = CS_PREFIX_OPCODE; ++ else if (i.base_reg ++ && (i.base_reg->reg_num == 4 ++ || i.base_reg->reg_num == 5)) ++ fragP->tc_frag_data.default_prefix = SS_PREFIX_OPCODE; ++ else ++ fragP->tc_frag_data.default_prefix = DS_PREFIX_OPCODE; ++ } ++ else if (j > 15) ++ as_warn (_("instruction length of %u bytes exceeds the limit of 15"), ++ j); ++ } ++ } ++ ++ if (align_branch_power ++ && now_seg != absolute_section ++ && cpu_arch_flags.bitfield.cpui386) ++ { ++ /* Terminate each frag so that we can add prefix and check for ++ fused jcc. */ ++ frag_wane (frag_now); ++ frag_new (0); + } + + #ifdef DEBUG386 +@@ -8402,6 +8811,7 @@ output_disp (fragS *insn_start_frag, off + if (!object_64bit) + { + reloc_type = BFD_RELOC_386_GOTPC; ++ i.has_gotpc_reloc = TRUE; + i.op[n].imms->X_add_number += add; + } + else if (reloc_type == BFD_RELOC_64) +@@ -8568,6 +8978,7 @@ output_imm (fragS *insn_start_frag, offs + reloc_type = BFD_RELOC_X86_64_GOTPC32; + else if (size == 8) + reloc_type = BFD_RELOC_X86_64_GOTPC64; ++ i.has_gotpc_reloc = TRUE; + i.op[n].imms->X_add_number += add; + } + fix_new_exp (frag_now, p - frag_now->fr_literal, size, +@@ -10193,6 +10604,355 @@ elf_symbol_resolved_in_segment_p (symbol + } + #endif + ++/* Return the next non-empty frag. */ ++ ++static fragS * ++i386_next_non_empty_frag (fragS *fragP) ++{ ++ /* There may be a frag with a ".fill 0" when there is no room in ++ the current frag for frag_grow in output_insn. */ ++ for (fragP = fragP->fr_next; ++ (fragP != NULL ++ && fragP->fr_type == rs_fill ++ && fragP->fr_fix == 0); ++ fragP = fragP->fr_next) ++ ; ++ return fragP; ++} ++ ++/* Return the next jcc frag after BRANCH_PADDING. */ ++ ++static fragS * ++i386_next_jcc_frag (fragS *fragP) ++{ ++ if (!fragP) ++ return NULL; ++ ++ if (fragP->fr_type == rs_machine_dependent ++ && (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) ++ == BRANCH_PADDING)) ++ { ++ fragP = i386_next_non_empty_frag (fragP); ++ if (fragP->fr_type != rs_machine_dependent) ++ return NULL; ++ if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == COND_JUMP) ++ return fragP; ++ } ++ ++ return NULL; ++} ++ ++/* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */ ++ ++static void ++i386_classify_machine_dependent_frag (fragS *fragP) ++{ ++ fragS *cmp_fragP; ++ fragS *pad_fragP; ++ fragS *branch_fragP; ++ fragS *next_fragP; ++ unsigned int max_prefix_length; ++ ++ if (fragP->tc_frag_data.classified) ++ return; ++ ++ /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert ++ FUSED_JCC_PADDING and merge BRANCH_PADDING. */ ++ for (next_fragP = fragP; ++ next_fragP != NULL; ++ next_fragP = next_fragP->fr_next) ++ { ++ next_fragP->tc_frag_data.classified = 1; ++ if (next_fragP->fr_type == rs_machine_dependent) ++ switch (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype)) ++ { ++ case BRANCH_PADDING: ++ /* The BRANCH_PADDING frag must be followed by a branch ++ frag. */ ++ branch_fragP = i386_next_non_empty_frag (next_fragP); ++ next_fragP->tc_frag_data.u.branch_fragP = branch_fragP; ++ break; ++ case FUSED_JCC_PADDING: ++ /* Check if this is a fused jcc: ++ FUSED_JCC_PADDING ++ CMP ++ BRANCH_PADDING ++ COND_JUMP ++ */ ++ cmp_fragP = i386_next_non_empty_frag (next_fragP); ++ pad_fragP = i386_next_non_empty_frag (cmp_fragP); ++ branch_fragP = i386_next_jcc_frag (pad_fragP); ++ if (branch_fragP) ++ { ++ /* The BRANCH_PADDING frag is merged with the ++ FUSED_JCC_PADDING frag. */ ++ next_fragP->tc_frag_data.u.branch_fragP = branch_fragP; ++ /* CMP instruction size. */ ++ next_fragP->tc_frag_data.cmp_size = cmp_fragP->fr_fix; ++ frag_wane (pad_fragP); ++ /* Skip to branch_fragP. */ ++ next_fragP = branch_fragP; ++ } ++ else if (next_fragP->tc_frag_data.max_prefix_length) ++ { ++ /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't ++ a fused jcc. */ ++ next_fragP->fr_subtype ++ = ENCODE_RELAX_STATE (BRANCH_PREFIX, 0); ++ next_fragP->tc_frag_data.max_bytes ++ = next_fragP->tc_frag_data.max_prefix_length; ++ /* This will be updated in the BRANCH_PREFIX scan. */ ++ next_fragP->tc_frag_data.max_prefix_length = 0; ++ } ++ else ++ frag_wane (next_fragP); ++ break; ++ } ++ } ++ ++ /* Scan for BRANCH_PREFIX. */ ++ for (; fragP != NULL; fragP = fragP->fr_next) ++ if (fragP->fr_type == rs_machine_dependent ++ && (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) ++ == BRANCH_PREFIX)) ++ { ++ /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and ++ COND_JUMP_PREFIX. */ ++ max_prefix_length = 0; ++ for (next_fragP = fragP; ++ next_fragP != NULL; ++ next_fragP = next_fragP->fr_next) ++ { ++ if (next_fragP->fr_type == rs_fill) ++ /* Skip rs_fill frags. */ ++ ; ++ else if (next_fragP->fr_type == rs_machine_dependent) ++ { ++ if (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) ++ == BRANCH_PREFIX) ++ { ++ /* Count BRANCH_PREFIX frags. */ ++ if (max_prefix_length >= MAX_FUSED_JCC_PADDING_SIZE) ++ { ++ max_prefix_length = MAX_FUSED_JCC_PADDING_SIZE; ++ frag_wane (next_fragP); ++ } ++ else ++ max_prefix_length ++ += next_fragP->tc_frag_data.max_bytes; ++ } ++ else if ((TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) ++ == BRANCH_PADDING) ++ || (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) ++ == FUSED_JCC_PADDING)) ++ { ++ /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */ ++ fragP->tc_frag_data.u.padding_fragP = next_fragP; ++ break; ++ } ++ else ++ /* Stop for other rs_machine_dependent frags. */ ++ break; ++ } ++ else ++ /* Stop for all other frags. */ ++ break; ++ } ++ ++ fragP->tc_frag_data.max_prefix_length = max_prefix_length; ++ ++ /* Skip to the next frag. */ ++ fragP = next_fragP; ++ } ++} ++ ++/* Compute padding size for ++ ++ FUSED_JCC_PADDING ++ CMP ++ BRANCH_PADDING ++ COND_JUMP/UNCOND_JUMP ++ ++ or ++ ++ BRANCH_PADDING ++ COND_JUMP/UNCOND_JUMP ++ */ ++ ++static int ++i386_branch_padding_size (fragS *fragP, offsetT address) ++{ ++ unsigned int offset, size, padding_size; ++ fragS *branch_fragP = fragP->tc_frag_data.u.branch_fragP; ++ ++ /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */ ++ if (!address) ++ address = fragP->fr_address; ++ address += fragP->fr_fix; ++ ++ /* CMP instrunction size. */ ++ size = fragP->tc_frag_data.cmp_size; ++ ++ /* The base size of the branch frag. */ ++ size += branch_fragP->fr_fix; ++ ++ /* Add opcode and displacement bytes for the rs_machine_dependent ++ branch frag. */ ++ if (branch_fragP->fr_type == rs_machine_dependent) ++ size += md_relax_table[branch_fragP->fr_subtype].rlx_length; ++ ++ /* Check if branch is within boundary and doesn't end at the last ++ byte. */ ++ offset = address & ((1U << align_branch_power) - 1); ++ if ((offset + size) >= (1U << align_branch_power)) ++ /* Padding needed to avoid crossing boundary. */ ++ padding_size = (1 << align_branch_power) - offset; ++ else ++ /* No padding needed. */ ++ padding_size = 0; ++ ++ if (!fits_in_signed_byte (padding_size)) ++ abort (); ++ ++ return padding_size; ++} ++ ++/* i386_generic_table_relax_frag() ++ ++ Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to ++ grow/shrink padding to align branch frags. Hand others to ++ relax_frag(). */ ++ ++long ++i386_generic_table_relax_frag (segT segment, fragS *fragP, long stretch) ++{ ++ if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING ++ || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING) ++ { ++ long padding_size = i386_branch_padding_size (fragP, 0); ++ long grow = padding_size - fragP->tc_frag_data.length; ++ ++ /* When the BRANCH_PREFIX frag is used, the computed address ++ must match the actual address and there should be no padding. */ ++ if (fragP->tc_frag_data.padding_address ++ && (fragP->tc_frag_data.padding_address != fragP->fr_address ++ || padding_size)) ++ abort (); ++ ++ /* Update the padding size. */ ++ if (grow) ++ fragP->tc_frag_data.length = padding_size; ++ ++ return grow; ++ } ++ else if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX) ++ { ++ fragS *padding_fragP, *next_fragP; ++ long padding_size, left_size, last_size; ++ ++ padding_fragP = fragP->tc_frag_data.u.padding_fragP; ++ if (!padding_fragP) ++ /* Use the padding set by the leading BRANCH_PREFIX frag. */ ++ return (fragP->tc_frag_data.length ++ - fragP->tc_frag_data.last_length); ++ ++ /* Compute the relative address of the padding frag in the very ++ first time where the BRANCH_PREFIX frag sizes are zero. */ ++ if (!fragP->tc_frag_data.padding_address) ++ fragP->tc_frag_data.padding_address ++ = padding_fragP->fr_address - (fragP->fr_address - stretch); ++ ++ /* First update the last length from the previous interation. */ ++ left_size = fragP->tc_frag_data.prefix_length; ++ for (next_fragP = fragP; ++ next_fragP != padding_fragP; ++ next_fragP = next_fragP->fr_next) ++ if (next_fragP->fr_type == rs_machine_dependent ++ && (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) ++ == BRANCH_PREFIX)) ++ { ++ if (left_size) ++ { ++ int max = next_fragP->tc_frag_data.max_bytes; ++ if (max) ++ { ++ int size; ++ if (max > left_size) ++ size = left_size; ++ else ++ size = max; ++ left_size -= size; ++ next_fragP->tc_frag_data.last_length = size; ++ } ++ } ++ else ++ next_fragP->tc_frag_data.last_length = 0; ++ } ++ ++ /* Check the padding size for the padding frag. */ ++ padding_size = i386_branch_padding_size ++ (padding_fragP, (fragP->fr_address ++ + fragP->tc_frag_data.padding_address)); ++ ++ last_size = fragP->tc_frag_data.prefix_length; ++ /* Check if there is change from the last interation. */ ++ if (padding_size == last_size) ++ { ++ /* Update the expected address of the padding frag. */ ++ padding_fragP->tc_frag_data.padding_address ++ = (fragP->fr_address + padding_size ++ + fragP->tc_frag_data.padding_address); ++ return 0; ++ } ++ ++ if (padding_size > fragP->tc_frag_data.max_prefix_length) ++ { ++ /* No padding if there is no sufficient room. Clear the ++ expected address of the padding frag. */ ++ padding_fragP->tc_frag_data.padding_address = 0; ++ padding_size = 0; ++ } ++ else ++ /* Store the expected address of the padding frag. */ ++ padding_fragP->tc_frag_data.padding_address ++ = (fragP->fr_address + padding_size ++ + fragP->tc_frag_data.padding_address); ++ ++ fragP->tc_frag_data.prefix_length = padding_size; ++ ++ /* Update the length for the current interation. */ ++ left_size = padding_size; ++ for (next_fragP = fragP; ++ next_fragP != padding_fragP; ++ next_fragP = next_fragP->fr_next) ++ if (next_fragP->fr_type == rs_machine_dependent ++ && (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) ++ == BRANCH_PREFIX)) ++ { ++ if (left_size) ++ { ++ int max = next_fragP->tc_frag_data.max_bytes; ++ if (max) ++ { ++ int size; ++ if (max > left_size) ++ size = left_size; ++ else ++ size = max; ++ left_size -= size; ++ next_fragP->tc_frag_data.length = size; ++ } ++ } ++ else ++ next_fragP->tc_frag_data.length = 0; ++ } ++ ++ return (fragP->tc_frag_data.length ++ - fragP->tc_frag_data.last_length); ++ } ++ return relax_frag (segment, fragP, stretch); ++} ++ + /* md_estimate_size_before_relax() + + Called just before relax() for rs_machine_dependent frags. The x86 +@@ -10209,6 +10969,14 @@ elf_symbol_resolved_in_segment_p (symbol + int + md_estimate_size_before_relax (fragS *fragP, segT segment) + { ++ if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING ++ || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX ++ || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING) ++ { ++ i386_classify_machine_dependent_frag (fragP); ++ return fragP->tc_frag_data.length; ++ } ++ + /* We've already got fragP->fr_subtype right; all we have to do is + check for un-relaxable symbols. On an ELF system, we can't relax + an externally visible symbol, because it may be overridden by a +@@ -10342,6 +11110,106 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNU + unsigned int extension = 0; + offsetT displacement_from_opcode_start; + ++ if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING ++ || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING ++ || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX) ++ { ++ /* Generate nop padding. */ ++ unsigned int size = fragP->tc_frag_data.length; ++ if (size) ++ { ++ if (size > fragP->tc_frag_data.max_bytes) ++ abort (); ++ ++ if (flag_debug) ++ { ++ const char *msg; ++ const char *branch = "branch"; ++ const char *prefix = ""; ++ fragS *padding_fragP; ++ if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) ++ == BRANCH_PREFIX) ++ { ++ padding_fragP = fragP->tc_frag_data.u.padding_fragP; ++ switch (fragP->tc_frag_data.default_prefix) ++ { ++ default: ++ abort (); ++ break; ++ case CS_PREFIX_OPCODE: ++ prefix = " cs"; ++ break; ++ case DS_PREFIX_OPCODE: ++ prefix = " ds"; ++ break; ++ case ES_PREFIX_OPCODE: ++ prefix = " es"; ++ break; ++ case FS_PREFIX_OPCODE: ++ prefix = " fs"; ++ break; ++ case GS_PREFIX_OPCODE: ++ prefix = " gs"; ++ break; ++ case SS_PREFIX_OPCODE: ++ prefix = " ss"; ++ break; ++ } ++ if (padding_fragP) ++ msg = _("%s:%u: add %d%s at 0x%llx to align " ++ "%s within %d-byte boundary\n"); ++ else ++ msg = _("%s:%u: add additional %d%s at 0x%llx to " ++ "align %s within %d-byte boundary\n"); ++ } ++ else ++ { ++ padding_fragP = fragP; ++ msg = _("%s:%u: add %d%s-byte nop at 0x%llx to align " ++ "%s within %d-byte boundary\n"); ++ } ++ ++ if (padding_fragP) ++ switch (padding_fragP->tc_frag_data.branch_type) ++ { ++ case align_branch_jcc: ++ branch = "jcc"; ++ break; ++ case align_branch_fused: ++ branch = "fused jcc"; ++ break; ++ case align_branch_jmp: ++ branch = "jmp"; ++ break; ++ case align_branch_call: ++ branch = "call"; ++ break; ++ case align_branch_indirect: ++ branch = "indiret branch"; ++ break; ++ case align_branch_ret: ++ branch = "ret"; ++ break; ++ default: ++ break; ++ } ++ ++ fprintf (stdout, msg, ++ fragP->fr_file, fragP->fr_line, size, prefix, ++ (long long) fragP->fr_address, branch, ++ 1 << align_branch_power); ++ } ++ if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX) ++ memset (fragP->fr_opcode, ++ fragP->tc_frag_data.default_prefix, size); ++ else ++ i386_generate_nops (fragP, (char *) fragP->fr_opcode, ++ size, 0); ++ fragP->fr_fix += size; ++ } ++ return; ++ } ++ + opcode = (unsigned char *) fragP->fr_opcode; + + /* Address we want to reach in file space. */ +@@ -10898,6 +11766,10 @@ const char *md_shortopts = "qnO::"; + #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24) + #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25) + #define OPTION_MVEXWIG (OPTION_MD_BASE + 26) ++#define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27) ++#define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28) ++#define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29) ++#define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30) + + struct option md_longopts[] = + { +@@ -10933,6 +11805,10 @@ struct option md_longopts[] = + {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD}, + {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS}, + {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG}, ++ {"malign-branch-boundary", required_argument, NULL, OPTION_MALIGN_BRANCH_BOUNDARY}, ++ {"malign-branch-prefix-size", required_argument, NULL, OPTION_MALIGN_BRANCH_PREFIX_SIZE}, ++ {"malign-branch", required_argument, NULL, OPTION_MALIGN_BRANCH}, ++ {"mbranches-within-32B-boundaries", no_argument, NULL, OPTION_MBRANCHES_WITH_32B_BOUNDARIES}, + {"mamd64", no_argument, NULL, OPTION_MAMD64}, + {"mintel64", no_argument, NULL, OPTION_MINTEL64}, + {NULL, no_argument, NULL, 0} +@@ -10943,7 +11819,7 @@ int + md_parse_option (int c, const char *arg) + { + unsigned int j; +- char *arch, *next, *saved; ++ char *arch, *next, *saved, *type; + + switch (c) + { +@@ -11319,6 +12195,86 @@ md_parse_option (int c, const char *arg) + as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg); + break; + ++ case OPTION_MALIGN_BRANCH_BOUNDARY: ++ { ++ char *end; ++ int align = strtoul (arg, &end, 0); ++ if (*end == '\0') ++ { ++ if (align == 0) ++ { ++ align_branch_power = 0; ++ break; ++ } ++ else if (align >= 32) ++ { ++ int align_power; ++ for (align_power = 0; ++ (align & 1) == 0; ++ align >>= 1, align_power++) ++ continue; ++ if (align == 1) ++ { ++ align_branch_power = align_power; ++ break; ++ } ++ } ++ } ++ as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg); ++ } ++ break; ++ ++ case OPTION_MALIGN_BRANCH_PREFIX_SIZE: ++ { ++ char *end; ++ int align = strtoul (arg, &end, 0); ++ if (*end == '\0' && align >= 0 && align < 6) ++ { ++ align_branch_prefix_size = align; ++ break; ++ } ++ as_fatal (_("invalid -malign-branch-prefix-size= value: %s"), ++ arg); ++ } ++ break; ++ ++ case OPTION_MALIGN_BRANCH: ++ align_branch = 0; ++ saved = xstrdup (arg); ++ type = saved; ++ do ++ { ++ next = strchr (type, '+'); ++ if (next) ++ *next++ = '\0'; ++ if (strcasecmp (type, "jcc") == 0) ++ align_branch |= align_branch_jcc; ++ else if (strcasecmp (type, "fused") == 0) ++ align_branch |= align_branch_fused; ++ else if (strcasecmp (type, "jmp") == 0) ++ align_branch |= align_branch_jmp; ++ else if (strcasecmp (type, "call") == 0) ++ align_branch |= align_branch_call; ++ else if (strcasecmp (type, "ret") == 0) ++ align_branch |= align_branch_ret; ++ else if (strcasecmp (type, "indirect") == 0) ++ align_branch |= align_branch_indirect; ++ else ++ as_fatal (_("invalid -malign-branch= option: `%s'"), arg); ++ type = next; ++ } ++ while (next != NULL); ++ free (saved); ++ break; ++ ++ case OPTION_MBRANCHES_WITH_32B_BOUNDARIES: ++ align_branch_power = 5; ++ align_branch_prefix_size = 5; ++ align_branch = (align_branch_jcc ++ | align_branch_fused ++ | align_branch_jmp); ++ break; ++ + case OPTION_MAMD64: + intel64 = 0; + break; +@@ -11571,6 +12527,20 @@ md_show_usage (FILE *stream) + fprintf (stream, _("\ + generate relax relocations\n")); + fprintf (stream, _("\ ++ -malign-branch-boundary=NUM (default: 0)\n\ ++ align branches within NUM byte boundary\n")); ++ fprintf (stream, _("\ ++ -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\ ++ TYPE is combination of jcc, fused, jmp, call, ret,\n\ ++ indirect\n\ ++ specify types of branches to align\n")); ++ fprintf (stream, _("\ ++ -malign-branch-prefix-size=NUM (default: 5)\n\ ++ align branches with NUM prefixes per instruction\n")); ++ fprintf (stream, _("\ ++ -mbranches-within-32B-boundaries\n\ ++ align branches within 32 byte boundary\n")); ++ fprintf (stream, _("\ + -mamd64 accept only AMD64 ISA [default]\n")); + fprintf (stream, _("\ + -mintel64 accept only Intel64 ISA\n")); +@@ -11654,15 +12624,24 @@ i386_target_format (void) + { + default: + format = ELF_TARGET_FORMAT; ++#ifndef TE_SOLARIS ++ tls_get_addr = "___tls_get_addr"; ++#endif + break; + case X86_64_ABI: + use_rela_relocations = 1; + object_64bit = 1; ++#ifndef TE_SOLARIS ++ tls_get_addr = "__tls_get_addr"; ++#endif + format = ELF_TARGET_FORMAT64; + break; + case X86_64_X32_ABI: + use_rela_relocations = 1; + object_64bit = 1; ++#ifndef TE_SOLARIS ++ tls_get_addr = "__tls_get_addr"; ++#endif + disallow_64bit_reloc = 1; + format = ELF_TARGET_FORMAT32; + break; +@@ -11779,6 +12758,21 @@ s_bss (int ignore ATTRIBUTE_UNUSED) + + #endif + ++/* Remember constant diretive. */ ++ ++void ++i386_cons_worker (int ignore ATTRIBUTE_UNUSED) ++{ ++ if (last_insn.kind != last_insn_directive ++ && (bfd_get_section_flags (NULL, now_seg) & SEC_CODE)) ++ { ++ last_insn.seg = now_seg; ++ last_insn.kind = last_insn_directive; ++ last_insn.name = "constant diretive"; ++ last_insn.file = as_where (&last_insn.line); ++ } ++} ++ + void + i386_validate_fix (fixS *fixp) + { +diff -rupN binutils-2.32/gas/config/tc-i386.h binutils.new/gas/config/tc-i386.h +--- binutils-2.32/gas/config/tc-i386.h 2019-01-19 16:01:33.000000000 +0000 ++++ binutils.new/gas/config/tc-i386.h 2019-11-25 14:01:00.626325922 +0000 +@@ -208,12 +208,19 @@ if ((n) \ + + #define MAX_MEM_FOR_RS_ALIGN_CODE 4095 + ++extern void i386_cons_worker (int); ++#define md_cons_worker(nbytes) i386_cons_worker (nbytes) ++ + void i386_print_statistics (FILE *); + #define tc_print_statistics i386_print_statistics + + extern unsigned int i386_frag_max_var (fragS *); + #define md_frag_max_var i386_frag_max_var + ++extern long i386_generic_table_relax_frag (segT, fragS *, long); ++#define md_generic_table_relax_frag(segment, fragP, stretch) \ ++ i386_generic_table_relax_frag (segment, fragP, stretch) ++ + #define md_number_to_chars number_to_chars_littleendian + + enum processor_type +@@ -248,9 +255,24 @@ extern i386_cpu_flags cpu_arch_isa_flags + + struct i386_tc_frag_data + { ++ union ++ { ++ fragS *padding_fragP; ++ fragS *branch_fragP; ++ } u; ++ addressT padding_address; + enum processor_type isa; + i386_cpu_flags isa_flags; ++ unsigned int max_bytes; + enum processor_type tune; ++ signed char length; ++ signed char last_length; ++ signed char max_prefix_length; ++ signed char prefix_length; ++ signed char default_prefix; ++ signed char cmp_size; ++ unsigned int classified : 1; ++ unsigned int branch_type : 7; + }; + + /* We need to emit the right NOP pattern in .align frags. This is +@@ -261,9 +283,20 @@ struct i386_tc_frag_data + #define TC_FRAG_INIT(FRAGP) \ + do \ + { \ ++ (FRAGP)->tc_frag_data.u.padding_fragP = NULL; \ ++ (FRAGP)->tc_frag_data.padding_address = 0; \ + (FRAGP)->tc_frag_data.isa = cpu_arch_isa; \ + (FRAGP)->tc_frag_data.isa_flags = cpu_arch_isa_flags; \ + (FRAGP)->tc_frag_data.tune = cpu_arch_tune; \ ++ (FRAGP)->tc_frag_data.length = 0; \ ++ (FRAGP)->tc_frag_data.max_bytes = max_chars; \ ++ (FRAGP)->tc_frag_data.last_length = 0; \ ++ (FRAGP)->tc_frag_data.max_prefix_length = 0; \ ++ (FRAGP)->tc_frag_data.prefix_length = 0; \ ++ (FRAGP)->tc_frag_data.default_prefix = 0; \ ++ (FRAGP)->tc_frag_data.cmp_size = 0; \ ++ (FRAGP)->tc_frag_data.classified = 0; \ ++ (FRAGP)->tc_frag_data.branch_type = 0; \ + } \ + while (0) + +diff -rupN binutils-2.32/gas/doc/c-i386.texi binutils.new/gas/doc/c-i386.texi +--- binutils-2.32/gas/doc/c-i386.texi 2019-01-19 16:01:33.000000000 +0000 ++++ binutils.new/gas/doc/c-i386.texi 2019-11-25 14:01:00.615325994 +0000 +@@ -410,6 +410,43 @@ R_X86_64_REX_GOTPCRELX, in 64-bit mode. + relocations. The default can be controlled by a configure option + @option{--enable-x86-relax-relocations}. + ++@cindex @samp{-malign-branch-boundary=} option, i386 ++@cindex @samp{-malign-branch-boundary=} option, x86-64 ++@item -malign-branch-boundary=@var{NUM} ++This option controls how the assembler should align branches with segment ++prefixes or NOP. @var{NUM} must be a power of 2. It should be 0 or ++no less than 32. Branches will be aligned within @var{NUM} byte ++boundary. @option{-malign-branch-boundary=0}, which is the default, ++doesn't align branches. ++ ++@cindex @samp{-malign-branch=} option, i386 ++@cindex @samp{-malign-branch=} option, x86-64 ++@item -malign-branch=@var{TYPE}[+@var{TYPE}...] ++This option specifies types of branches to align. @var{TYPE} is ++combination of @samp{jcc}, which aligns conditional jumps, ++@samp{fused}, which aligns fused conditional jumps, @samp{jmp}, ++which aligns unconditional jumps, @samp{call} which aligns calls, ++@samp{ret}, which aligns rets, @samp{indirect}, which aligns indirect ++jumps and calls. The default is @option{-malign-branch=jcc+fused+jmp}. ++ ++@cindex @samp{-malign-branch-prefix-size=} option, i386 ++@cindex @samp{-malign-branch-prefix-size=} option, x86-64 ++@item -malign-branch-prefix-size=@var{NUM} ++This option specifies the maximum number of prefixes on an instruction ++to align branches. @var{NUM} should be between 0 and 5. The default ++@var{NUM} is 5. ++ ++@cindex @samp{-mbranches-within-32B-boundaries} option, i386 ++@cindex @samp{-mbranches-within-32B-boundaries} option, x86-64 ++@item -mbranches-within-32B-boundaries ++This option aligns conditional jumps, fused conditional jumps and ++unconditional jumps within 32 byte boundary with up to 5 segment prefixes ++on an instruction. It is equivalent to ++@option{-malign-branch-boundary=32} ++@option{-malign-branch=jcc+fused+jmp} ++@option{-malign-branch-prefix-size=5}. ++The default doesn't align branches. ++ + @cindex @samp{-mx86-used-note=} option, i386 + @cindex @samp{-mx86-used-note=} option, x86-64 + @item -mx86-used-note=@var{no} +diff -rupN binutils-2.32/gas/read.c binutils.new/gas/read.c +--- binutils-2.32/gas/read.c 2019-01-19 16:01:33.000000000 +0000 ++++ binutils.new/gas/read.c 2019-11-25 14:01:00.616325988 +0000 +@@ -3976,6 +3976,10 @@ cons_worker (int nbytes, /* 1=.byte, 2=. + md_cons_align (nbytes); + #endif + ++#ifdef md_cons_worker ++ md_cons_worker (nbytes); ++#endif ++ + c = 0; + do + { +diff -rupN binutils-2.32/gas/testsuite/gas/i386/align-branch-1a.d binutils.new/gas/testsuite/gas/i386/align-branch-1a.d +--- binutils-2.32/gas/testsuite/gas/i386/align-branch-1a.d 1970-01-01 01:00:00.000000000 +0100 ++++ binutils.new/gas/testsuite/gas/i386/align-branch-1a.d 2019-11-25 14:01:00.632325883 +0000 +@@ -0,0 +1,77 @@ ++#source: align-branch-1.s ++#as: -malign-branch-boundary=32 ++#objdump: -dw ++ ++.*: +file format .* ++ ++Disassembly of section .text: ++ ++0+ : ++ 0: 65 65 65 a3 01 00 00 00 gs gs mov %eax,%gs:0x1 ++ 8: 55 push %ebp ++ 9: 55 push %ebp ++ a: 55 push %ebp ++ b: 55 push %ebp ++ c: 89 e5 mov %esp,%ebp ++ e: 89 7d f8 mov %edi,-0x8\(%ebp\) ++ 11: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 14: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 17: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 1a: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 1d: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 20: 39 c5 cmp %eax,%ebp ++ 22: 74 5e je 82 ++ 24: 3e 89 73 f4 mov %esi,%ds:-0xc\(%ebx\) ++ 28: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 2b: 89 7d f8 mov %edi,-0x8\(%ebp\) ++ 2e: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 31: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 34: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 37: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 3a: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 3d: 5d pop %ebp ++ 3e: 5d pop %ebp ++ 3f: 5d pop %ebp ++ 40: 74 40 je 82 ++ 42: 5d pop %ebp ++ 43: 74 3d je 82 ++ 45: 36 89 44 24 fc mov %eax,%ss:-0x4\(%esp\) ++ 4a: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 4d: 89 7d f8 mov %edi,-0x8\(%ebp\) ++ 50: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 53: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 56: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 59: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 5c: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 5f: 5d pop %ebp ++ 60: eb 26 jmp 88 ++ 62: eb 24 jmp 88 ++ 64: eb 22 jmp 88 ++ 66: 89 45 fc mov %eax,-0x4\(%ebp\) ++ 69: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 6c: 89 7d f8 mov %edi,-0x8\(%ebp\) ++ 6f: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 72: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 75: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 78: 5d pop %ebp ++ 79: 5d pop %ebp ++ 7a: 39 c5 cmp %eax,%ebp ++ 7c: 74 04 je 82 ++ 7e: 66 90 xchg %ax,%ax ++ 80: eb 06 jmp 88 ++ 82: 8b 45 f4 mov -0xc\(%ebp\),%eax ++ 85: 89 45 fc mov %eax,-0x4\(%ebp\) ++ 88: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ 8e: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ 94: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ 9a: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ a0: 89 75 0c mov %esi,0xc\(%ebp\) ++ a3: e9 [0-9a-f ]+ jmp .* ++ a8: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ ae: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ b4: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ ba: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ c0: 89 75 00 mov %esi,0x0\(%ebp\) ++ c3: 74 c3 je 88 ++ c5: 74 c1 je 88 ++#pass +diff -rupN binutils-2.32/gas/testsuite/gas/i386/align-branch-1b.d binutils.new/gas/testsuite/gas/i386/align-branch-1b.d +--- binutils-2.32/gas/testsuite/gas/i386/align-branch-1b.d 1970-01-01 01:00:00.000000000 +0100 ++++ binutils.new/gas/testsuite/gas/i386/align-branch-1b.d 2019-11-25 14:01:00.679325573 +0000 +@@ -0,0 +1,77 @@ ++#source: align-branch-1.s ++#as: -malign-branch-boundary=32 -malign-branch=fused+jcc+jmp ++#objdump: -dw ++ ++.*: +file format .* ++ ++Disassembly of section .text: ++ ++0+ : ++ 0: 65 65 65 a3 01 00 00 00 gs gs mov %eax,%gs:0x1 ++ 8: 55 push %ebp ++ 9: 55 push %ebp ++ a: 55 push %ebp ++ b: 55 push %ebp ++ c: 89 e5 mov %esp,%ebp ++ e: 89 7d f8 mov %edi,-0x8\(%ebp\) ++ 11: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 14: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 17: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 1a: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 1d: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 20: 39 c5 cmp %eax,%ebp ++ 22: 74 5e je 82 ++ 24: 3e 89 73 f4 mov %esi,%ds:-0xc\(%ebx\) ++ 28: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 2b: 89 7d f8 mov %edi,-0x8\(%ebp\) ++ 2e: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 31: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 34: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 37: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 3a: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 3d: 5d pop %ebp ++ 3e: 5d pop %ebp ++ 3f: 5d pop %ebp ++ 40: 74 40 je 82 ++ 42: 5d pop %ebp ++ 43: 74 3d je 82 ++ 45: 36 89 44 24 fc mov %eax,%ss:-0x4\(%esp\) ++ 4a: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 4d: 89 7d f8 mov %edi,-0x8\(%ebp\) ++ 50: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 53: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 56: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 59: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 5c: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 5f: 5d pop %ebp ++ 60: eb 26 jmp 88 ++ 62: eb 24 jmp 88 ++ 64: eb 22 jmp 88 ++ 66: 89 45 fc mov %eax,-0x4\(%ebp\) ++ 69: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 6c: 89 7d f8 mov %edi,-0x8\(%ebp\) ++ 6f: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 72: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 75: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 78: 5d pop %ebp ++ 79: 5d pop %ebp ++ 7a: 39 c5 cmp %eax,%ebp ++ 7c: 74 04 je 82 ++ 7e: 66 90 xchg %ax,%ax ++ 80: eb 06 jmp 88 ++ 82: 8b 45 f4 mov -0xc\(%ebp\),%eax ++ 85: 89 45 fc mov %eax,-0x4\(%ebp\) ++ 88: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ 8e: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ 94: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ 9a: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ a0: 89 75 0c mov %esi,0xc\(%ebp\) ++ a3: e9 [0-9a-f ]+ jmp .* ++ a8: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ ae: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ b4: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ ba: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ c0: 89 75 00 mov %esi,0x0\(%ebp\) ++ c3: 74 c3 je 88 ++ c5: 74 c1 je 88 ++#pass +diff -rupN binutils-2.32/gas/testsuite/gas/i386/align-branch-1c.d binutils.new/gas/testsuite/gas/i386/align-branch-1c.d +--- binutils-2.32/gas/testsuite/gas/i386/align-branch-1c.d 1970-01-01 01:00:00.000000000 +0100 ++++ binutils.new/gas/testsuite/gas/i386/align-branch-1c.d 2019-11-25 14:01:00.680325567 +0000 +@@ -0,0 +1,77 @@ ++#source: align-branch-1.s ++#as: -malign-branch-boundary=32 -malign-branch-prefix-size=1 ++#objdump: -dw ++ ++.*: +file format .* ++ ++Disassembly of section .text: ++ ++0+ : ++ 0: 65 a3 01 00 00 00 mov %eax,%gs:0x1 ++ 6: 3e 55 ds push %ebp ++ 8: 3e 55 ds push %ebp ++ a: 55 push %ebp ++ b: 55 push %ebp ++ c: 89 e5 mov %esp,%ebp ++ e: 89 7d f8 mov %edi,-0x8\(%ebp\) ++ 11: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 14: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 17: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 1a: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 1d: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 20: 39 c5 cmp %eax,%ebp ++ 22: 74 5e je 82 ++ 24: 3e 89 73 f4 mov %esi,%ds:-0xc\(%ebx\) ++ 28: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 2b: 89 7d f8 mov %edi,-0x8\(%ebp\) ++ 2e: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 31: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 34: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 37: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 3a: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 3d: 5d pop %ebp ++ 3e: 5d pop %ebp ++ 3f: 5d pop %ebp ++ 40: 74 40 je 82 ++ 42: 5d pop %ebp ++ 43: 74 3d je 82 ++ 45: 36 89 44 24 fc mov %eax,%ss:-0x4\(%esp\) ++ 4a: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 4d: 89 7d f8 mov %edi,-0x8\(%ebp\) ++ 50: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 53: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 56: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 59: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 5c: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 5f: 5d pop %ebp ++ 60: eb 26 jmp 88 ++ 62: eb 24 jmp 88 ++ 64: eb 22 jmp 88 ++ 66: 89 45 fc mov %eax,-0x4\(%ebp\) ++ 69: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 6c: 89 7d f8 mov %edi,-0x8\(%ebp\) ++ 6f: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 72: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 75: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 78: 5d pop %ebp ++ 79: 5d pop %ebp ++ 7a: 39 c5 cmp %eax,%ebp ++ 7c: 74 04 je 82 ++ 7e: 66 90 xchg %ax,%ax ++ 80: eb 06 jmp 88 ++ 82: 8b 45 f4 mov -0xc\(%ebp\),%eax ++ 85: 89 45 fc mov %eax,-0x4\(%ebp\) ++ 88: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ 8e: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ 94: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ 9a: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ a0: 89 75 0c mov %esi,0xc\(%ebp\) ++ a3: e9 [0-9a-f ]+ jmp .* ++ a8: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ ae: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ b4: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ ba: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ c0: 89 75 00 mov %esi,0x0\(%ebp\) ++ c3: 74 c3 je 88 ++ c5: 74 c1 je 88 ++#pass +diff -rupN binutils-2.32/gas/testsuite/gas/i386/align-branch-1d.d binutils.new/gas/testsuite/gas/i386/align-branch-1d.d +--- binutils-2.32/gas/testsuite/gas/i386/align-branch-1d.d 1970-01-01 01:00:00.000000000 +0100 ++++ binutils.new/gas/testsuite/gas/i386/align-branch-1d.d 2019-11-25 14:01:00.680325567 +0000 +@@ -0,0 +1,76 @@ ++#source: align-branch-1.s ++#as: -malign-branch-boundary=32 -malign-branch=fused+jcc ++#objdump: -dw ++ ++.*: +file format .* ++ ++Disassembly of section .text: ++ ++0+ : ++ 0: 65 65 65 a3 01 00 00 00 gs gs mov %eax,%gs:0x1 ++ 8: 55 push %ebp ++ 9: 55 push %ebp ++ a: 55 push %ebp ++ b: 55 push %ebp ++ c: 89 e5 mov %esp,%ebp ++ e: 89 7d f8 mov %edi,-0x8\(%ebp\) ++ 11: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 14: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 17: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 1a: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 1d: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 20: 39 c5 cmp %eax,%ebp ++ 22: 74 5b je 7f ++ 24: 3e 89 73 f4 mov %esi,%ds:-0xc\(%ebx\) ++ 28: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 2b: 89 7d f8 mov %edi,-0x8\(%ebp\) ++ 2e: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 31: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 34: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 37: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 3a: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 3d: 5d pop %ebp ++ 3e: 5d pop %ebp ++ 3f: 5d pop %ebp ++ 40: 74 3d je 7f ++ 42: 5d pop %ebp ++ 43: 74 3a je 7f ++ 45: 89 44 24 fc mov %eax,-0x4\(%esp\) ++ 49: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 4c: 89 7d f8 mov %edi,-0x8\(%ebp\) ++ 4f: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 52: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 55: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 58: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 5b: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 5e: 5d pop %ebp ++ 5f: eb 24 jmp 85 ++ 61: eb 22 jmp 85 ++ 63: eb 20 jmp 85 ++ 65: 89 45 fc mov %eax,-0x4\(%ebp\) ++ 68: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 6b: 89 7d f8 mov %edi,-0x8\(%ebp\) ++ 6e: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 71: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 74: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 77: 5d pop %ebp ++ 78: 5d pop %ebp ++ 79: 39 c5 cmp %eax,%ebp ++ 7b: 74 02 je 7f ++ 7d: eb 06 jmp 85 ++ 7f: 8b 45 f4 mov -0xc\(%ebp\),%eax ++ 82: 89 45 fc mov %eax,-0x4\(%ebp\) ++ 85: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ 8b: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ 91: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ 97: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ 9d: 89 75 0c mov %esi,0xc\(%ebp\) ++ a0: e9 [0-9a-f ]+ jmp .* ++ a5: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ ab: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ b1: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ b7: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ bd: 89 75 00 mov %esi,0x0\(%ebp\) ++ c0: 74 c3 je 85 ++ c2: 74 c1 je 85 ++#pass +diff -rupN binutils-2.32/gas/testsuite/gas/i386/align-branch-1e.d binutils.new/gas/testsuite/gas/i386/align-branch-1e.d +--- binutils-2.32/gas/testsuite/gas/i386/align-branch-1e.d 1970-01-01 01:00:00.000000000 +0100 ++++ binutils.new/gas/testsuite/gas/i386/align-branch-1e.d 2019-11-25 14:01:00.680325567 +0000 +@@ -0,0 +1,77 @@ ++#source: align-branch-1.s ++#as: -malign-branch-boundary=32 -malign-branch=jcc ++#objdump: -dw ++ ++.*: +file format .* ++ ++Disassembly of section .text: ++ ++0+ : ++ 0: 65 a3 01 00 00 00 mov %eax,%gs:0x1 ++ 6: 55 push %ebp ++ 7: 55 push %ebp ++ 8: 55 push %ebp ++ 9: 55 push %ebp ++ a: 89 e5 mov %esp,%ebp ++ c: 89 7d f8 mov %edi,-0x8\(%ebp\) ++ f: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 12: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 15: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 18: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 1b: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 1e: 39 c5 cmp %eax,%ebp ++ 20: 74 5a je 7c ++ 22: 89 73 f4 mov %esi,-0xc\(%ebx\) ++ 25: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 28: 89 7d f8 mov %edi,-0x8\(%ebp\) ++ 2b: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 2e: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 31: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 34: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 37: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 3a: 5d pop %ebp ++ 3b: 5d pop %ebp ++ 3c: 5d pop %ebp ++ 3d: 74 3d je 7c ++ 3f: 5d pop %ebp ++ 40: 74 3a je 7c ++ 42: 89 44 24 fc mov %eax,-0x4\(%esp\) ++ 46: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 49: 89 7d f8 mov %edi,-0x8\(%ebp\) ++ 4c: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 4f: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 52: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 55: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 58: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 5b: 5d pop %ebp ++ 5c: eb 24 jmp 82 ++ 5e: eb 22 jmp 82 ++ 60: eb 20 jmp 82 ++ 62: 89 45 fc mov %eax,-0x4\(%ebp\) ++ 65: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 68: 89 7d f8 mov %edi,-0x8\(%ebp\) ++ 6b: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 6e: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 71: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 74: 5d pop %ebp ++ 75: 5d pop %ebp ++ 76: 39 c5 cmp %eax,%ebp ++ 78: 74 02 je 7c ++ 7a: eb 06 jmp 82 ++ 7c: 8b 45 f4 mov -0xc\(%ebp\),%eax ++ 7f: 89 45 fc mov %eax,-0x4\(%ebp\) ++ 82: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ 88: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ 8e: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ 94: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ 9a: 89 75 0c mov %esi,0xc\(%ebp\) ++ 9d: e9 [0-9a-f ]+ jmp .* ++ a2: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ a8: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ ae: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ b4: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ ba: 89 75 00 mov %esi,0x0\(%ebp\) ++ bd: 74 c3 je 82 ++ bf: 90 nop ++ c0: 74 c0 je 82 ++#pass +diff -rupN binutils-2.32/gas/testsuite/gas/i386/align-branch-1f.d binutils.new/gas/testsuite/gas/i386/align-branch-1f.d +--- binutils-2.32/gas/testsuite/gas/i386/align-branch-1f.d 1970-01-01 01:00:00.000000000 +0100 ++++ binutils.new/gas/testsuite/gas/i386/align-branch-1f.d 2019-11-25 14:01:00.680325567 +0000 +@@ -0,0 +1,77 @@ ++#source: align-branch-1.s ++#as: -malign-branch-boundary=32 -malign-branch=jcc+jmp ++#objdump: -dw ++ ++.*: +file format .* ++ ++Disassembly of section .text: ++ ++0+ : ++ 0: 65 a3 01 00 00 00 mov %eax,%gs:0x1 ++ 6: 55 push %ebp ++ 7: 55 push %ebp ++ 8: 55 push %ebp ++ 9: 55 push %ebp ++ a: 89 e5 mov %esp,%ebp ++ c: 89 7d f8 mov %edi,-0x8\(%ebp\) ++ f: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 12: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 15: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 18: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 1b: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 1e: 39 c5 cmp %eax,%ebp ++ 20: 74 5c je 7e ++ 22: 89 73 f4 mov %esi,-0xc\(%ebx\) ++ 25: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 28: 89 7d f8 mov %edi,-0x8\(%ebp\) ++ 2b: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 2e: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 31: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 34: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 37: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 3a: 5d pop %ebp ++ 3b: 5d pop %ebp ++ 3c: 5d pop %ebp ++ 3d: 74 3f je 7e ++ 3f: 5d pop %ebp ++ 40: 74 3c je 7e ++ 42: 89 44 24 fc mov %eax,-0x4\(%esp\) ++ 46: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 49: 89 7d f8 mov %edi,-0x8\(%ebp\) ++ 4c: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 4f: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 52: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 55: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 58: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 5b: 5d pop %ebp ++ 5c: eb 27 jmp 85 ++ 5e: 66 90 xchg %ax,%ax ++ 60: eb 23 jmp 85 ++ 62: eb 21 jmp 85 ++ 64: 89 45 fc mov %eax,-0x4\(%ebp\) ++ 67: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 6a: 89 7d f8 mov %edi,-0x8\(%ebp\) ++ 6d: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 70: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 73: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 76: 5d pop %ebp ++ 77: 5d pop %ebp ++ 78: 39 c5 cmp %eax,%ebp ++ 7a: 74 02 je 7e ++ 7c: eb 07 jmp 85 ++ 7e: 36 8b 45 f4 mov %ss:-0xc\(%ebp\),%eax ++ 82: 89 45 fc mov %eax,-0x4\(%ebp\) ++ 85: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ 8b: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ 91: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ 97: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ 9d: 89 75 0c mov %esi,0xc\(%ebp\) ++ a0: e9 [0-9a-f ]+ jmp .* ++ a5: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ ab: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ b1: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ b7: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ bd: 89 75 00 mov %esi,0x0\(%ebp\) ++ c0: 74 c3 je 85 ++ c2: 74 c1 je 85 ++#pass +diff -rupN binutils-2.32/gas/testsuite/gas/i386/align-branch-1g.d binutils.new/gas/testsuite/gas/i386/align-branch-1g.d +--- binutils-2.32/gas/testsuite/gas/i386/align-branch-1g.d 1970-01-01 01:00:00.000000000 +0100 ++++ binutils.new/gas/testsuite/gas/i386/align-branch-1g.d 2019-11-25 14:01:00.680325567 +0000 +@@ -0,0 +1,77 @@ ++#source: align-branch-1.s ++#as: -mbranches-within-32B-boundaries ++#objdump: -dw ++ ++.*: +file format .* ++ ++Disassembly of section .text: ++ ++0+ : ++ 0: 65 65 65 a3 01 00 00 00 gs gs mov %eax,%gs:0x1 ++ 8: 55 push %ebp ++ 9: 55 push %ebp ++ a: 55 push %ebp ++ b: 55 push %ebp ++ c: 89 e5 mov %esp,%ebp ++ e: 89 7d f8 mov %edi,-0x8\(%ebp\) ++ 11: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 14: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 17: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 1a: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 1d: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 20: 39 c5 cmp %eax,%ebp ++ 22: 74 5e je 82 ++ 24: 3e 89 73 f4 mov %esi,%ds:-0xc\(%ebx\) ++ 28: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 2b: 89 7d f8 mov %edi,-0x8\(%ebp\) ++ 2e: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 31: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 34: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 37: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 3a: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 3d: 5d pop %ebp ++ 3e: 5d pop %ebp ++ 3f: 5d pop %ebp ++ 40: 74 40 je 82 ++ 42: 5d pop %ebp ++ 43: 74 3d je 82 ++ 45: 36 89 44 24 fc mov %eax,%ss:-0x4\(%esp\) ++ 4a: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 4d: 89 7d f8 mov %edi,-0x8\(%ebp\) ++ 50: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 53: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 56: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 59: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 5c: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 5f: 5d pop %ebp ++ 60: eb 26 jmp 88 ++ 62: eb 24 jmp 88 ++ 64: eb 22 jmp 88 ++ 66: 89 45 fc mov %eax,-0x4\(%ebp\) ++ 69: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 6c: 89 7d f8 mov %edi,-0x8\(%ebp\) ++ 6f: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 72: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 75: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 78: 5d pop %ebp ++ 79: 5d pop %ebp ++ 7a: 39 c5 cmp %eax,%ebp ++ 7c: 74 04 je 82 ++ 7e: 66 90 xchg %ax,%ax ++ 80: eb 06 jmp 88 ++ 82: 8b 45 f4 mov -0xc\(%ebp\),%eax ++ 85: 89 45 fc mov %eax,-0x4\(%ebp\) ++ 88: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ 8e: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ 94: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ 9a: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ a0: 89 75 0c mov %esi,0xc\(%ebp\) ++ a3: e9 [0-9a-f ]+ jmp .* ++ a8: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ ae: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ b4: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ ba: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ c0: 89 75 00 mov %esi,0x0\(%ebp\) ++ c3: 74 c3 je 88 ++ c5: 74 c1 je 88 ++#pass +diff -rupN binutils-2.32/gas/testsuite/gas/i386/align-branch-1h.d binutils.new/gas/testsuite/gas/i386/align-branch-1h.d +--- binutils-2.32/gas/testsuite/gas/i386/align-branch-1h.d 1970-01-01 01:00:00.000000000 +0100 ++++ binutils.new/gas/testsuite/gas/i386/align-branch-1h.d 2019-11-25 14:01:00.680325567 +0000 +@@ -0,0 +1,76 @@ ++#source: align-branch-1.s ++#as: -mbranches-within-32B-boundaries -malign-branch-boundary=0 ++#objdump: -dw ++ ++.*: +file format .* ++ ++Disassembly of section .text: ++ ++0+ : ++ 0: 65 a3 01 00 00 00 mov %eax,%gs:0x1 ++ 6: 55 push %ebp ++ 7: 55 push %ebp ++ 8: 55 push %ebp ++ 9: 55 push %ebp ++ a: 89 e5 mov %esp,%ebp ++ c: 89 7d f8 mov %edi,-0x8\(%ebp\) ++ f: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 12: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 15: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 18: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 1b: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 1e: 39 c5 cmp %eax,%ebp ++ 20: 74 5a je 7c ++ 22: 89 73 f4 mov %esi,-0xc\(%ebx\) ++ 25: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 28: 89 7d f8 mov %edi,-0x8\(%ebp\) ++ 2b: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 2e: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 31: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 34: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 37: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 3a: 5d pop %ebp ++ 3b: 5d pop %ebp ++ 3c: 5d pop %ebp ++ 3d: 74 3d je 7c ++ 3f: 5d pop %ebp ++ 40: 74 3a je 7c ++ 42: 89 44 24 fc mov %eax,-0x4\(%esp\) ++ 46: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 49: 89 7d f8 mov %edi,-0x8\(%ebp\) ++ 4c: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 4f: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 52: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 55: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 58: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 5b: 5d pop %ebp ++ 5c: eb 24 jmp 82 ++ 5e: eb 22 jmp 82 ++ 60: eb 20 jmp 82 ++ 62: 89 45 fc mov %eax,-0x4\(%ebp\) ++ 65: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 68: 89 7d f8 mov %edi,-0x8\(%ebp\) ++ 6b: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 6e: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 71: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 74: 5d pop %ebp ++ 75: 5d pop %ebp ++ 76: 39 c5 cmp %eax,%ebp ++ 78: 74 02 je 7c ++ 7a: eb 06 jmp 82 ++ 7c: 8b 45 f4 mov -0xc\(%ebp\),%eax ++ 7f: 89 45 fc mov %eax,-0x4\(%ebp\) ++ 82: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ 88: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ 8e: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ 94: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ 9a: 89 75 0c mov %esi,0xc\(%ebp\) ++ 9d: e9 [0-9a-f ]+ jmp .* ++ a2: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ a8: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ ae: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ b4: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\) ++ ba: 89 75 00 mov %esi,0x0\(%ebp\) ++ bd: 74 c3 je 82 ++ bf: 74 c1 je 82 ++#pass +diff -rupN binutils-2.32/gas/testsuite/gas/i386/align-branch-1.s binutils.new/gas/testsuite/gas/i386/align-branch-1.s +--- binutils-2.32/gas/testsuite/gas/i386/align-branch-1.s 1970-01-01 01:00:00.000000000 +0100 ++++ binutils.new/gas/testsuite/gas/i386/align-branch-1.s 2019-11-25 14:01:00.632325883 +0000 +@@ -0,0 +1,72 @@ ++ .text ++ .globl foo ++ .p2align 4 ++foo: ++ movl %eax, %gs:0x1 ++ pushl %ebp ++ pushl %ebp ++ pushl %ebp ++ pushl %ebp ++ movl %esp, %ebp ++ movl %edi, -8(%ebp) ++ movl %esi, -12(%ebp) ++ movl %esi, -12(%ebp) ++ movl %esi, -12(%ebp) ++ movl %esi, -12(%ebp) ++ movl %esi, -12(%ebp) ++ cmp %eax, %ebp ++ je .L_2 ++ movl %esi, -12(%ebx) ++ movl %esi, -12(%ebp) ++ movl %edi, -8(%ebp) ++ movl %esi, -12(%ebp) ++ movl %esi, -12(%ebp) ++ movl %esi, -12(%ebp) ++ movl %esi, -12(%ebp) ++ movl %esi, -12(%ebp) ++ popl %ebp ++ popl %ebp ++ popl %ebp ++ je .L_2 ++ popl %ebp ++ je .L_2 ++ movl %eax, -4(%esp) ++ movl %esi, -12(%ebp) ++ movl %edi, -8(%ebp) ++ movl %esi, -12(%ebp) ++ movl %esi, -12(%ebp) ++ movl %esi, -12(%ebp) ++ movl %esi, -12(%ebp) ++ movl %esi, -12(%ebp) ++ popl %ebp ++ jmp .L_3 ++ jmp .L_3 ++ jmp .L_3 ++ movl %eax, -4(%ebp) ++ movl %esi, -12(%ebp) ++ movl %edi, -8(%ebp) ++ movl %esi, -12(%ebp) ++ movl %esi, -12(%ebp) ++ movl %esi, -12(%ebp) ++ popl %ebp ++ popl %ebp ++ cmp %eax, %ebp ++ je .L_2 ++ jmp .L_3 ++.L_2: ++ movl -12(%ebp), %eax ++ movl %eax, -4(%ebp) ++.L_3: ++ movl %esi, -1200(%ebp) ++ movl %esi, -1200(%ebp) ++ movl %esi, -1200(%ebp) ++ movl %esi, -1200(%ebp) ++ movl %esi, 12(%ebp) ++ jmp bar ++ movl %esi, -1200(%ebp) ++ movl %esi, -1200(%ebp) ++ movl %esi, -1200(%ebp) ++ movl %esi, -1200(%ebp) ++ movl %esi, (%ebp) ++ je .L_3 ++ je .L_3 +diff -rupN binutils-2.32/gas/testsuite/gas/i386/align-branch-2a.d binutils.new/gas/testsuite/gas/i386/align-branch-2a.d +--- binutils-2.32/gas/testsuite/gas/i386/align-branch-2a.d 1970-01-01 01:00:00.000000000 +0100 ++++ binutils.new/gas/testsuite/gas/i386/align-branch-2a.d 2019-11-25 14:01:00.680325567 +0000 +@@ -0,0 +1,55 @@ ++#source: align-branch-2.s ++#as: -malign-branch-boundary=32 -malign-branch=fused+jcc+jmp ++#objdump: -dw ++ ++.*: +file format .* ++ ++Disassembly of section .text: ++ ++0+ : ++ 0: 64 a3 01 00 00 00 mov %eax,%fs:0x1 ++ 6: 55 push %ebp ++ 7: 55 push %ebp ++ 8: 55 push %ebp ++ 9: 55 push %ebp ++ a: 89 e5 mov %esp,%ebp ++ c: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ f: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 12: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 15: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 18: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 1b: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 1e: ff e0 jmp \*%eax ++ 20: 55 push %ebp ++ 21: 55 push %ebp ++ 22: 64 a3 01 00 00 00 mov %eax,%fs:0x1 ++ 28: 89 e5 mov %esp,%ebp ++ 2a: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 2d: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 30: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 33: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 36: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 39: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 3c: ff d0 call \*%eax ++ 3e: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 41: 55 push %ebp ++ 42: 55 push %ebp ++ 43: 64 a3 01 00 00 00 mov %eax,%fs:0x1 ++ 49: 89 e5 mov %esp,%ebp ++ 4b: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 4e: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 51: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 54: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 57: e8 [0-9a-f ]+ call .* ++ 5c: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 5f: 55 push %ebp ++ 60: 55 push %ebp ++ 61: 55 push %ebp ++ 62: 55 push %ebp ++ 63: 64 a3 01 00 00 00 mov %eax,%fs:0x1 ++ 69: 89 e5 mov %esp,%ebp ++ 6b: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 6e: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 71: ff 15 00 00 00 00 call \*0x0 ++ 77: 55 push %ebp ++#pass +diff -rupN binutils-2.32/gas/testsuite/gas/i386/align-branch-2b.d binutils.new/gas/testsuite/gas/i386/align-branch-2b.d +--- binutils-2.32/gas/testsuite/gas/i386/align-branch-2b.d 1970-01-01 01:00:00.000000000 +0100 ++++ binutils.new/gas/testsuite/gas/i386/align-branch-2b.d 2019-11-25 14:01:00.680325567 +0000 +@@ -0,0 +1,55 @@ ++#source: align-branch-2.s ++#as: -malign-branch-boundary=32 -malign-branch=indirect ++#objdump: -dw ++ ++.*: +file format .* ++ ++Disassembly of section .text: ++ ++0+ : ++ 0: 64 64 64 a3 01 00 00 00 fs fs mov %eax,%fs:0x1 ++ 8: 55 push %ebp ++ 9: 55 push %ebp ++ a: 55 push %ebp ++ b: 55 push %ebp ++ c: 89 e5 mov %esp,%ebp ++ e: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 11: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 14: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 17: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 1a: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 1d: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 20: ff e0 jmp \*%eax ++ 22: 3e 3e 55 ds ds push %ebp ++ 25: 55 push %ebp ++ 26: 64 a3 01 00 00 00 mov %eax,%fs:0x1 ++ 2c: 89 e5 mov %esp,%ebp ++ 2e: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 31: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 34: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 37: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 3a: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 3d: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 40: ff d0 call \*%eax ++ 42: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 45: 55 push %ebp ++ 46: 55 push %ebp ++ 47: 64 a3 01 00 00 00 mov %eax,%fs:0x1 ++ 4d: 89 e5 mov %esp,%ebp ++ 4f: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 52: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 55: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 58: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 5b: e8 [0-9a-f ]+ call .* ++ 60: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 63: 55 push %ebp ++ 64: 55 push %ebp ++ 65: 55 push %ebp ++ 66: 55 push %ebp ++ 67: 64 a3 01 00 00 00 mov %eax,%fs:0x1 ++ 6d: 89 e5 mov %esp,%ebp ++ 6f: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 72: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 75: ff 15 00 00 00 00 call \*0x0 ++ 7b: 55 push %ebp ++#pass +diff -rupN binutils-2.32/gas/testsuite/gas/i386/align-branch-2c.d binutils.new/gas/testsuite/gas/i386/align-branch-2c.d +--- binutils-2.32/gas/testsuite/gas/i386/align-branch-2c.d 1970-01-01 01:00:00.000000000 +0100 ++++ binutils.new/gas/testsuite/gas/i386/align-branch-2c.d 2019-11-25 14:01:00.680325567 +0000 +@@ -0,0 +1,55 @@ ++#source: align-branch-2.s ++#as: -malign-branch-boundary=32 -malign-branch=indirect+call ++#objdump: -dw ++ ++.*: +file format .* ++ ++Disassembly of section .text: ++ ++0+ : ++ 0: 64 64 64 a3 01 00 00 00 fs fs mov %eax,%fs:0x1 ++ 8: 55 push %ebp ++ 9: 55 push %ebp ++ a: 55 push %ebp ++ b: 55 push %ebp ++ c: 89 e5 mov %esp,%ebp ++ e: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 11: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 14: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 17: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 1a: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 1d: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 20: ff e0 jmp \*%eax ++ 22: 3e 3e 55 ds ds push %ebp ++ 25: 55 push %ebp ++ 26: 64 a3 01 00 00 00 mov %eax,%fs:0x1 ++ 2c: 89 e5 mov %esp,%ebp ++ 2e: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 31: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 34: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 37: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 3a: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 3d: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 40: ff d0 call \*%eax ++ 42: 36 36 36 36 36 89 75 f4 ss ss ss ss mov %esi,%ss:-0xc\(%ebp\) ++ 4a: 55 push %ebp ++ 4b: 55 push %ebp ++ 4c: 64 a3 01 00 00 00 mov %eax,%fs:0x1 ++ 52: 89 e5 mov %esp,%ebp ++ 54: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 57: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 5a: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 5d: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 60: e8 [0-9a-f ]+ call .* ++ 65: 36 36 36 36 36 89 75 f4 ss ss ss ss mov %esi,%ss:-0xc\(%ebp\) ++ 6d: 3e 55 ds push %ebp ++ 6f: 55 push %ebp ++ 70: 55 push %ebp ++ 71: 55 push %ebp ++ 72: 64 a3 01 00 00 00 mov %eax,%fs:0x1 ++ 78: 89 e5 mov %esp,%ebp ++ 7a: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 7d: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 80: ff 15 00 00 00 00 call \*0x0 ++ 86: 55 push %ebp ++#pass +diff -rupN binutils-2.32/gas/testsuite/gas/i386/align-branch-2.s binutils.new/gas/testsuite/gas/i386/align-branch-2.s +--- binutils-2.32/gas/testsuite/gas/i386/align-branch-2.s 1970-01-01 01:00:00.000000000 +0100 ++++ binutils.new/gas/testsuite/gas/i386/align-branch-2.s 2019-11-25 14:01:00.680325567 +0000 +@@ -0,0 +1,49 @@ ++ .text ++ .globl foo ++ .p2align 4 ++foo: ++ movl %eax, %fs:0x1 ++ pushl %ebp ++ pushl %ebp ++ pushl %ebp ++ pushl %ebp ++ movl %esp, %ebp ++ movl %esi, -12(%ebp) ++ movl %esi, -12(%ebp) ++ movl %esi, -12(%ebp) ++ movl %esi, -12(%ebp) ++ movl %esi, -12(%ebp) ++ movl %esi, -12(%ebp) ++ jmp *%eax ++ pushl %ebp ++ pushl %ebp ++ movl %eax, %fs:0x1 ++ movl %esp, %ebp ++ movl %esi, -12(%ebp) ++ movl %esi, -12(%ebp) ++ movl %esi, -12(%ebp) ++ movl %esi, -12(%ebp) ++ movl %esi, -12(%ebp) ++ movl %esi, -12(%ebp) ++ call *%eax ++ movl %esi, -12(%ebp) ++ pushl %ebp ++ pushl %ebp ++ movl %eax, %fs:0x1 ++ movl %esp, %ebp ++ movl %esi, -12(%ebp) ++ movl %esi, -12(%ebp) ++ movl %esi, -12(%ebp) ++ movl %esi, -12(%ebp) ++ call foo ++ movl %esi, -12(%ebp) ++ pushl %ebp ++ pushl %ebp ++ pushl %ebp ++ pushl %ebp ++ movl %eax, %fs:0x1 ++ movl %esp, %ebp ++ movl %esi, -12(%ebp) ++ movl %esi, -12(%ebp) ++ call *foo ++ pushl %ebp +diff -rupN binutils-2.32/gas/testsuite/gas/i386/align-branch-3.d binutils.new/gas/testsuite/gas/i386/align-branch-3.d +--- binutils-2.32/gas/testsuite/gas/i386/align-branch-3.d 1970-01-01 01:00:00.000000000 +0100 ++++ binutils.new/gas/testsuite/gas/i386/align-branch-3.d 2019-11-25 14:01:00.680325567 +0000 +@@ -0,0 +1,33 @@ ++#as: -malign-branch-boundary=32 -malign-branch=indirect+call ++#objdump: -dw ++ ++.*: +file format .* ++ ++Disassembly of section .text: ++ ++0+ : ++ 0: 64 a3 01 00 00 00 mov %eax,%fs:0x1 ++ 6: 55 push %ebp ++ 7: 55 push %ebp ++ 8: 55 push %ebp ++ 9: 55 push %ebp ++ a: 89 e5 mov %esp,%ebp ++ c: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ f: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 12: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 15: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 18: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 1b: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 1e: e8 fc ff ff ff call 1f ++ 23: 55 push %ebp ++ 24: 55 push %ebp ++ 25: 64 a3 01 00 00 00 mov %eax,%fs:0x1 ++ 2b: 89 e5 mov %esp,%ebp ++ 2d: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 30: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 33: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 36: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 39: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 3c: ff 91 00 00 00 00 call \*0x0\(%ecx\) ++ 42: 89 75 f4 mov %esi,-0xc\(%ebp\) ++#pass +diff -rupN binutils-2.32/gas/testsuite/gas/i386/align-branch-3.s binutils.new/gas/testsuite/gas/i386/align-branch-3.s +--- binutils-2.32/gas/testsuite/gas/i386/align-branch-3.s 1970-01-01 01:00:00.000000000 +0100 ++++ binutils.new/gas/testsuite/gas/i386/align-branch-3.s 2019-11-25 14:01:00.680325567 +0000 +@@ -0,0 +1,28 @@ ++ .text ++ .globl foo ++ .p2align 4 ++foo: ++ movl %eax, %fs:0x1 ++ pushl %ebp ++ pushl %ebp ++ pushl %ebp ++ pushl %ebp ++ movl %esp, %ebp ++ movl %esi, -12(%ebp) ++ movl %esi, -12(%ebp) ++ movl %esi, -12(%ebp) ++ movl %esi, -12(%ebp) ++ movl %esi, -12(%ebp) ++ movl %esi, -12(%ebp) ++ call ___tls_get_addr ++ pushl %ebp ++ pushl %ebp ++ movl %eax, %fs:0x1 ++ movl %esp, %ebp ++ movl %esi, -12(%ebp) ++ movl %esi, -12(%ebp) ++ movl %esi, -12(%ebp) ++ movl %esi, -12(%ebp) ++ movl %esi, -12(%ebp) ++ call *___tls_get_addr@GOT(%ecx) ++ movl %esi, -12(%ebp) +diff -rupN binutils-2.32/gas/testsuite/gas/i386/align-branch-4a.d binutils.new/gas/testsuite/gas/i386/align-branch-4a.d +--- binutils-2.32/gas/testsuite/gas/i386/align-branch-4a.d 1970-01-01 01:00:00.000000000 +0100 ++++ binutils.new/gas/testsuite/gas/i386/align-branch-4a.d 2019-11-25 14:01:00.680325567 +0000 +@@ -0,0 +1,36 @@ ++#source: align-branch-4.s ++#as: -malign-branch-boundary=32 -malign-branch=fused+jcc+jmp ++#objdump: -dw ++ ++.*: +file format .* ++ ++Disassembly of section .text: ++ ++0+ : ++ 0: 64 a3 01 00 00 00 mov %eax,%fs:0x1 ++ 6: 55 push %ebp ++ 7: 55 push %ebp ++ 8: 55 push %ebp ++ 9: 55 push %ebp ++ a: 55 push %ebp ++ b: 89 e5 mov %esp,%ebp ++ d: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 10: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 13: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 16: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 19: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 1c: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 1f: c3 ret ++ 20: 55 push %ebp ++ 21: 55 push %ebp ++ 22: 64 a3 01 00 00 00 mov %eax,%fs:0x1 ++ 28: 89 e5 mov %esp,%ebp ++ 2a: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 2d: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 30: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 33: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 36: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 39: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 3c: c2 1e 00 ret \$0x1e ++ 3f: 89 75 f4 mov %esi,-0xc\(%ebp\) ++#pass +diff -rupN binutils-2.32/gas/testsuite/gas/i386/align-branch-4b.d binutils.new/gas/testsuite/gas/i386/align-branch-4b.d +--- binutils-2.32/gas/testsuite/gas/i386/align-branch-4b.d 1970-01-01 01:00:00.000000000 +0100 ++++ binutils.new/gas/testsuite/gas/i386/align-branch-4b.d 2019-11-25 14:01:00.680325567 +0000 +@@ -0,0 +1,36 @@ ++#source: align-branch-4.s ++#as: -malign-branch-boundary=32 -malign-branch=ret ++#objdump: -dw ++ ++.*: +file format .* ++ ++Disassembly of section .text: ++ ++0+ : ++ 0: 64 64 a3 01 00 00 00 fs mov %eax,%fs:0x1 ++ 7: 55 push %ebp ++ 8: 55 push %ebp ++ 9: 55 push %ebp ++ a: 55 push %ebp ++ b: 55 push %ebp ++ c: 89 e5 mov %esp,%ebp ++ e: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 11: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 14: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 17: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 1a: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 1d: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 20: c3 ret ++ 21: 3e 3e 3e 55 ds ds ds push %ebp ++ 25: 55 push %ebp ++ 26: 64 a3 01 00 00 00 mov %eax,%fs:0x1 ++ 2c: 89 e5 mov %esp,%ebp ++ 2e: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 31: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 34: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 37: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 3a: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 3d: 89 75 f4 mov %esi,-0xc\(%ebp\) ++ 40: c2 1e 00 ret \$0x1e ++ 43: 89 75 f4 mov %esi,-0xc\(%ebp\) ++#pass +diff -rupN binutils-2.32/gas/testsuite/gas/i386/align-branch-4.s binutils.new/gas/testsuite/gas/i386/align-branch-4.s +--- binutils-2.32/gas/testsuite/gas/i386/align-branch-4.s 1970-01-01 01:00:00.000000000 +0100 ++++ binutils.new/gas/testsuite/gas/i386/align-branch-4.s 2019-11-25 14:01:00.680325567 +0000 +@@ -0,0 +1,30 @@ ++ .text ++ .globl foo ++ .p2align 4 ++foo: ++ movl %eax, %fs:0x1 ++ pushl %ebp ++ pushl %ebp ++ pushl %ebp ++ pushl %ebp ++ pushl %ebp ++ movl %esp, %ebp ++ movl %esi, -12(%ebp) ++ movl %esi, -12(%ebp) ++ movl %esi, -12(%ebp) ++ movl %esi, -12(%ebp) ++ movl %esi, -12(%ebp) ++ movl %esi, -12(%ebp) ++ ret ++ pushl %ebp ++ pushl %ebp ++ movl %eax, %fs:0x1 ++ movl %esp, %ebp ++ movl %esi, -12(%ebp) ++ movl %esi, -12(%ebp) ++ movl %esi, -12(%ebp) ++ movl %esi, -12(%ebp) ++ movl %esi, -12(%ebp) ++ movl %esi, -12(%ebp) ++ ret $30 ++ movl %esi, -12(%ebp) +diff -rupN binutils-2.32/gas/testsuite/gas/i386/align-branch-5.d binutils.new/gas/testsuite/gas/i386/align-branch-5.d +--- binutils-2.32/gas/testsuite/gas/i386/align-branch-5.d 1970-01-01 01:00:00.000000000 +0100 ++++ binutils.new/gas/testsuite/gas/i386/align-branch-5.d 2019-11-25 14:01:00.680325567 +0000 +@@ -0,0 +1,36 @@ ++#as: -malign-branch-boundary=32 -malign-branch=jcc+fused+jmp ++#objdump: -dw ++ ++.*: +file format .* ++ ++Disassembly of section .text: ++ ++0+ : ++ 0: c1 e9 02 shr \$0x2,%ecx ++ 3: c1 e9 02 shr \$0x2,%ecx ++ 6: c1 e9 02 shr \$0x2,%ecx ++ 9: 89 d1 mov %edx,%ecx ++ b: 31 c0 xor %eax,%eax ++ d: c1 e9 02 shr \$0x2,%ecx ++ 10: c1 e9 02 shr \$0x2,%ecx ++ 13: c1 e9 02 shr \$0x2,%ecx ++ 16: c1 e9 02 shr \$0x2,%ecx ++ 19: c1 e9 02 shr \$0x2,%ecx ++ 1c: c1 e9 02 shr \$0x2,%ecx ++ 1f: f6 c2 02 test \$0x2,%dl ++ 22: f3 ab rep stos %eax,%es:\(%edi\) ++ 24: 75 dd jne 3 ++ 26: 31 c0 xor %eax,%eax ++ 28: c1 e9 02 shr \$0x2,%ecx ++ 2b: c1 e9 02 shr \$0x2,%ecx ++ 2e: c1 e9 02 shr \$0x2,%ecx ++ 31: 89 d1 mov %edx,%ecx ++ 33: 31 c0 xor %eax,%eax ++ 35: c1 e9 02 shr \$0x2,%ecx ++ 38: c1 e9 02 shr \$0x2,%ecx ++ 3b: c1 e9 02 shr \$0x2,%ecx ++ 3e: f6 c2 02 test \$0x2,%dl ++ 41: e8 [0-9a-f ]+ call .* ++ 46: 75 e3 jne 2b ++ 48: 31 c0 xor %eax,%eax ++#pass +diff -rupN binutils-2.32/gas/testsuite/gas/i386/align-branch-5.s binutils.new/gas/testsuite/gas/i386/align-branch-5.s +--- binutils-2.32/gas/testsuite/gas/i386/align-branch-5.s 1970-01-01 01:00:00.000000000 +0100 ++++ binutils.new/gas/testsuite/gas/i386/align-branch-5.s 2019-11-25 14:01:00.680325567 +0000 +@@ -0,0 +1,32 @@ ++ .text ++ .p2align 4,,15 ++foo: ++ shrl $2, %ecx ++.L1: ++ shrl $2, %ecx ++ shrl $2, %ecx ++ movl %edx, %ecx ++ xorl %eax, %eax ++ shrl $2, %ecx ++ shrl $2, %ecx ++ shrl $2, %ecx ++ shrl $2, %ecx ++ shrl $2, %ecx ++ shrl $2, %ecx ++ testb $2, %dl ++ rep stosl ++ jne .L1 ++ xorl %eax, %eax ++ shrl $2, %ecx ++.L2: ++ shrl $2, %ecx ++ shrl $2, %ecx ++ movl %edx, %ecx ++ xorl %eax, %eax ++ shrl $2, %ecx ++ shrl $2, %ecx ++ shrl $2, %ecx ++ testb $2, %dl ++ call bar ++ jne .L2 ++ xorl %eax, %eax +diff -rupN binutils-2.32/gas/testsuite/gas/i386/i386.exp binutils.new/gas/testsuite/gas/i386/i386.exp +--- binutils-2.32/gas/testsuite/gas/i386/i386.exp 2019-01-19 16:01:33.000000000 +0000 ++++ binutils.new/gas/testsuite/gas/i386/i386.exp 2019-11-25 14:01:00.680325567 +0000 +@@ -472,6 +472,20 @@ if [expr ([istarget "i*86-*-*"] || [ist + run_dump_test "optimize-3" + run_dump_test "optimize-4" + run_dump_test "optimize-5" ++ run_dump_test "align-branch-1a" ++ run_dump_test "align-branch-1b" ++ run_dump_test "align-branch-1c" ++ run_dump_test "align-branch-1d" ++ run_dump_test "align-branch-1e" ++ run_dump_test "align-branch-1f" ++ run_dump_test "align-branch-1g" ++ run_dump_test "align-branch-1h" ++ run_dump_test "align-branch-2a" ++ run_dump_test "align-branch-2b" ++ run_dump_test "align-branch-2c" ++ run_dump_test "align-branch-4a" ++ run_dump_test "align-branch-4b" ++ run_dump_test "align-branch-5" + + # These tests require support for 8 and 16 bit relocs, + # so we only run them for ELF and COFF targets. +@@ -543,6 +557,10 @@ if [expr ([istarget "i*86-*-*"] || [ist + run_dump_test "evex-no-scale-32" + run_dump_test "property-1" + ++ if {[istarget "*-*-linux*"]} then { ++ run_dump_test "align-branch-3" ++ } ++ + if { [gas_64_check] } then { + run_dump_test "att-regs" + run_dump_test "intel-regs" +@@ -982,6 +1000,20 @@ if [expr ([istarget "i*86-*-*"] || [ista + run_dump_test "x86-64-optimize-4" + run_dump_test "x86-64-optimize-5" + run_dump_test "x86-64-optimize-6" ++ run_dump_test "x86-64-align-branch-1a" ++ run_dump_test "x86-64-align-branch-1b" ++ run_dump_test "x86-64-align-branch-1c" ++ run_dump_test "x86-64-align-branch-1d" ++ run_dump_test "x86-64-align-branch-1e" ++ run_dump_test "x86-64-align-branch-1f" ++ run_dump_test "x86-64-align-branch-1g" ++ run_dump_test "x86-64-align-branch-1h" ++ run_dump_test "x86-64-align-branch-2a" ++ run_dump_test "x86-64-align-branch-2b" ++ run_dump_test "x86-64-align-branch-2c" ++ run_dump_test "x86-64-align-branch-4a" ++ run_dump_test "x86-64-align-branch-4b" ++ run_dump_test "x86-64-align-branch-5" + + if { ![istarget "*-*-aix*"] + && ![istarget "*-*-beos*"] +@@ -1047,6 +1079,10 @@ if [expr ([istarget "i*86-*-*"] || [ista + + run_dump_test "evex-no-scale-64" + run_dump_test "x86-64-property-1" ++ ++ if {[istarget "*-*-linux*"]} then { ++ run_dump_test "x86-64-align-branch-3" ++ } + } + + set ASFLAGS "$old_ASFLAGS" +diff -rupN binutils-2.32/gas/testsuite/gas/i386/x86-64-align-branch-1a.d binutils.new/gas/testsuite/gas/i386/x86-64-align-branch-1a.d +--- binutils-2.32/gas/testsuite/gas/i386/x86-64-align-branch-1a.d 1970-01-01 01:00:00.000000000 +0100 ++++ binutils.new/gas/testsuite/gas/i386/x86-64-align-branch-1a.d 2019-11-25 14:01:00.680325567 +0000 +@@ -0,0 +1,75 @@ ++#source: x86-64-align-branch-1.s ++#as: -malign-branch-boundary=32 ++#objdump: -dw ++ ++.*: +file format .* ++ ++Disassembly of section .text: ++ ++0+ : ++ 0: 64 64 64 64 89 04 25 01 00 00 00 fs fs fs mov %eax,%fs:0x1 ++ b: 55 push %rbp ++ c: 55 push %rbp ++ d: 55 push %rbp ++ e: 48 89 e5 mov %rsp,%rbp ++ 11: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 14: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 17: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 1a: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 1d: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 20: 48 39 c5 cmp %rax,%rbp ++ 23: 74 5d je 82 ++ 25: 2e 89 75 f4 mov %esi,%cs:-0xc\(%rbp\) ++ 29: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 2c: 89 7d f8 mov %edi,-0x8\(%rbp\) ++ 2f: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 32: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 35: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 38: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 3b: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 3e: 5d pop %rbp ++ 3f: 5d pop %rbp ++ 40: 74 40 je 82 ++ 42: 5d pop %rbp ++ 43: 74 3d je 82 ++ 45: 2e 89 45 fc mov %eax,%cs:-0x4\(%rbp\) ++ 49: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 4c: 89 7d f8 mov %edi,-0x8\(%rbp\) ++ 4f: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 52: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 55: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 58: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 5b: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 5e: 5d pop %rbp ++ 5f: 5d pop %rbp ++ 60: eb 26 jmp 88 ++ 62: eb 24 jmp 88 ++ 64: eb 22 jmp 88 ++ 66: 89 45 fc mov %eax,-0x4\(%rbp\) ++ 69: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 6c: 89 7d f8 mov %edi,-0x8\(%rbp\) ++ 6f: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 72: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 75: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 78: 5d pop %rbp ++ 79: 5d pop %rbp ++ 7a: 48 39 c5 cmp %rax,%rbp ++ 7d: 74 03 je 82 ++ 7f: 90 nop ++ 80: eb 06 jmp 88 ++ 82: 8b 45 f4 mov -0xc\(%rbp\),%eax ++ 85: 89 45 fc mov %eax,-0x4\(%rbp\) ++ 88: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ 8e: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ 94: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ 9a: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ a0: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ a6: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ ac: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ b2: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ b8: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ be: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ c4: eb c2 jmp 88 ++ c6: 5d pop %rbp ++ c7: c3 retq ++#pass +diff -rupN binutils-2.32/gas/testsuite/gas/i386/x86-64-align-branch-1b.d binutils.new/gas/testsuite/gas/i386/x86-64-align-branch-1b.d +--- binutils-2.32/gas/testsuite/gas/i386/x86-64-align-branch-1b.d 1970-01-01 01:00:00.000000000 +0100 ++++ binutils.new/gas/testsuite/gas/i386/x86-64-align-branch-1b.d 2019-11-25 14:01:00.680325567 +0000 +@@ -0,0 +1,75 @@ ++#source: x86-64-align-branch-1.s ++#as: -malign-branch-boundary=32 -malign-branch=fused+jcc+jmp ++#objdump: -dw ++ ++.*: +file format .* ++ ++Disassembly of section .text: ++ ++0+ : ++ 0: 64 64 64 64 89 04 25 01 00 00 00 fs fs fs mov %eax,%fs:0x1 ++ b: 55 push %rbp ++ c: 55 push %rbp ++ d: 55 push %rbp ++ e: 48 89 e5 mov %rsp,%rbp ++ 11: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 14: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 17: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 1a: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 1d: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 20: 48 39 c5 cmp %rax,%rbp ++ 23: 74 5d je 82 ++ 25: 2e 89 75 f4 mov %esi,%cs:-0xc\(%rbp\) ++ 29: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 2c: 89 7d f8 mov %edi,-0x8\(%rbp\) ++ 2f: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 32: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 35: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 38: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 3b: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 3e: 5d pop %rbp ++ 3f: 5d pop %rbp ++ 40: 74 40 je 82 ++ 42: 5d pop %rbp ++ 43: 74 3d je 82 ++ 45: 2e 89 45 fc mov %eax,%cs:-0x4\(%rbp\) ++ 49: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 4c: 89 7d f8 mov %edi,-0x8\(%rbp\) ++ 4f: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 52: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 55: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 58: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 5b: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 5e: 5d pop %rbp ++ 5f: 5d pop %rbp ++ 60: eb 26 jmp 88 ++ 62: eb 24 jmp 88 ++ 64: eb 22 jmp 88 ++ 66: 89 45 fc mov %eax,-0x4\(%rbp\) ++ 69: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 6c: 89 7d f8 mov %edi,-0x8\(%rbp\) ++ 6f: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 72: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 75: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 78: 5d pop %rbp ++ 79: 5d pop %rbp ++ 7a: 48 39 c5 cmp %rax,%rbp ++ 7d: 74 03 je 82 ++ 7f: 90 nop ++ 80: eb 06 jmp 88 ++ 82: 8b 45 f4 mov -0xc\(%rbp\),%eax ++ 85: 89 45 fc mov %eax,-0x4\(%rbp\) ++ 88: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ 8e: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ 94: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ 9a: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ a0: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ a6: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ ac: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ b2: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ b8: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ be: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ c4: eb c2 jmp 88 ++ c6: 5d pop %rbp ++ c7: c3 retq ++#pass +diff -rupN binutils-2.32/gas/testsuite/gas/i386/x86-64-align-branch-1c.d binutils.new/gas/testsuite/gas/i386/x86-64-align-branch-1c.d +--- binutils-2.32/gas/testsuite/gas/i386/x86-64-align-branch-1c.d 1970-01-01 01:00:00.000000000 +0100 ++++ binutils.new/gas/testsuite/gas/i386/x86-64-align-branch-1c.d 2019-11-25 14:01:00.680325567 +0000 +@@ -0,0 +1,75 @@ ++#source: x86-64-align-branch-1.s ++#as: -malign-branch-boundary=32 -malign-branch-prefix-size=1 ++#objdump: -dw ++ ++.*: +file format .* ++ ++Disassembly of section .text: ++ ++0+ : ++ 0: 64 89 04 25 01 00 00 00 mov %eax,%fs:0x1 ++ 8: 2e 55 cs push %rbp ++ a: 2e 55 cs push %rbp ++ c: 2e 55 cs push %rbp ++ e: 48 89 e5 mov %rsp,%rbp ++ 11: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 14: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 17: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 1a: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 1d: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 20: 48 39 c5 cmp %rax,%rbp ++ 23: 74 5d je 82 ++ 25: 2e 89 75 f4 mov %esi,%cs:-0xc\(%rbp\) ++ 29: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 2c: 89 7d f8 mov %edi,-0x8\(%rbp\) ++ 2f: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 32: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 35: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 38: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 3b: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 3e: 5d pop %rbp ++ 3f: 5d pop %rbp ++ 40: 74 40 je 82 ++ 42: 5d pop %rbp ++ 43: 74 3d je 82 ++ 45: 2e 89 45 fc mov %eax,%cs:-0x4\(%rbp\) ++ 49: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 4c: 89 7d f8 mov %edi,-0x8\(%rbp\) ++ 4f: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 52: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 55: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 58: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 5b: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 5e: 5d pop %rbp ++ 5f: 5d pop %rbp ++ 60: eb 26 jmp 88 ++ 62: eb 24 jmp 88 ++ 64: eb 22 jmp 88 ++ 66: 89 45 fc mov %eax,-0x4\(%rbp\) ++ 69: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 6c: 89 7d f8 mov %edi,-0x8\(%rbp\) ++ 6f: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 72: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 75: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 78: 5d pop %rbp ++ 79: 5d pop %rbp ++ 7a: 48 39 c5 cmp %rax,%rbp ++ 7d: 74 03 je 82 ++ 7f: 90 nop ++ 80: eb 06 jmp 88 ++ 82: 8b 45 f4 mov -0xc\(%rbp\),%eax ++ 85: 89 45 fc mov %eax,-0x4\(%rbp\) ++ 88: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ 8e: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ 94: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ 9a: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ a0: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ a6: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ ac: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ b2: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ b8: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ be: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ c4: eb c2 jmp 88 ++ c6: 5d pop %rbp ++ c7: c3 retq ++#pass +diff -rupN binutils-2.32/gas/testsuite/gas/i386/x86-64-align-branch-1d.d binutils.new/gas/testsuite/gas/i386/x86-64-align-branch-1d.d +--- binutils-2.32/gas/testsuite/gas/i386/x86-64-align-branch-1d.d 1970-01-01 01:00:00.000000000 +0100 ++++ binutils.new/gas/testsuite/gas/i386/x86-64-align-branch-1d.d 2019-11-25 14:01:00.680325567 +0000 +@@ -0,0 +1,74 @@ ++#source: x86-64-align-branch-1.s ++#as: -malign-branch-boundary=32 -malign-branch=fused+jcc ++#objdump: -dw ++ ++.*: +file format .* ++ ++Disassembly of section .text: ++ ++0+ : ++ 0: 64 64 64 64 89 04 25 01 00 00 00 fs fs fs mov %eax,%fs:0x1 ++ b: 55 push %rbp ++ c: 55 push %rbp ++ d: 55 push %rbp ++ e: 48 89 e5 mov %rsp,%rbp ++ 11: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 14: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 17: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 1a: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 1d: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 20: 48 39 c5 cmp %rax,%rbp ++ 23: 74 5b je 80 ++ 25: 2e 89 75 f4 mov %esi,%cs:-0xc\(%rbp\) ++ 29: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 2c: 89 7d f8 mov %edi,-0x8\(%rbp\) ++ 2f: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 32: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 35: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 38: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 3b: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 3e: 5d pop %rbp ++ 3f: 5d pop %rbp ++ 40: 74 3e je 80 ++ 42: 5d pop %rbp ++ 43: 74 3b je 80 ++ 45: 89 45 fc mov %eax,-0x4\(%rbp\) ++ 48: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 4b: 89 7d f8 mov %edi,-0x8\(%rbp\) ++ 4e: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 51: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 54: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 57: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 5a: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 5d: 5d pop %rbp ++ 5e: 5d pop %rbp ++ 5f: eb 25 jmp 86 ++ 61: eb 23 jmp 86 ++ 63: eb 21 jmp 86 ++ 65: 89 45 fc mov %eax,-0x4\(%rbp\) ++ 68: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 6b: 89 7d f8 mov %edi,-0x8\(%rbp\) ++ 6e: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 71: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 74: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 77: 5d pop %rbp ++ 78: 5d pop %rbp ++ 79: 48 39 c5 cmp %rax,%rbp ++ 7c: 74 02 je 80 ++ 7e: eb 06 jmp 86 ++ 80: 8b 45 f4 mov -0xc\(%rbp\),%eax ++ 83: 89 45 fc mov %eax,-0x4\(%rbp\) ++ 86: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ 8c: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ 92: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ 98: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ 9e: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ a4: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ aa: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ b0: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ b6: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ bc: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ c2: eb c2 jmp 86 ++ c4: 5d pop %rbp ++ c5: c3 retq ++#pass +diff -rupN binutils-2.32/gas/testsuite/gas/i386/x86-64-align-branch-1e.d binutils.new/gas/testsuite/gas/i386/x86-64-align-branch-1e.d +--- binutils-2.32/gas/testsuite/gas/i386/x86-64-align-branch-1e.d 1970-01-01 01:00:00.000000000 +0100 ++++ binutils.new/gas/testsuite/gas/i386/x86-64-align-branch-1e.d 2019-11-25 14:01:00.680325567 +0000 +@@ -0,0 +1,74 @@ ++#source: x86-64-align-branch-1.s ++#as: -malign-branch-boundary=32 -malign-branch=jcc ++#objdump: -dw ++ ++.*: +file format .* ++ ++Disassembly of section .text: ++ ++0+ : ++ 0: 64 89 04 25 01 00 00 00 mov %eax,%fs:0x1 ++ 8: 55 push %rbp ++ 9: 55 push %rbp ++ a: 55 push %rbp ++ b: 48 89 e5 mov %rsp,%rbp ++ e: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 11: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 14: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 17: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 1a: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 1d: 48 39 c5 cmp %rax,%rbp ++ 20: 74 5b je 7d ++ 22: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 25: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 28: 89 7d f8 mov %edi,-0x8\(%rbp\) ++ 2b: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 2e: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 31: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 34: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 37: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 3a: 5d pop %rbp ++ 3b: 5d pop %rbp ++ 3c: 74 3f je 7d ++ 3e: 2e 5d cs pop %rbp ++ 40: 74 3b je 7d ++ 42: 89 45 fc mov %eax,-0x4\(%rbp\) ++ 45: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 48: 89 7d f8 mov %edi,-0x8\(%rbp\) ++ 4b: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 4e: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 51: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 54: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 57: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 5a: 5d pop %rbp ++ 5b: 5d pop %rbp ++ 5c: eb 25 jmp 83 ++ 5e: eb 23 jmp 83 ++ 60: eb 21 jmp 83 ++ 62: 89 45 fc mov %eax,-0x4\(%rbp\) ++ 65: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 68: 89 7d f8 mov %edi,-0x8\(%rbp\) ++ 6b: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 6e: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 71: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 74: 5d pop %rbp ++ 75: 5d pop %rbp ++ 76: 48 39 c5 cmp %rax,%rbp ++ 79: 74 02 je 7d ++ 7b: eb 06 jmp 83 ++ 7d: 8b 45 f4 mov -0xc\(%rbp\),%eax ++ 80: 89 45 fc mov %eax,-0x4\(%rbp\) ++ 83: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ 89: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ 8f: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ 95: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ 9b: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ a1: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ a7: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ ad: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ b3: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ b9: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ bf: eb c2 jmp 83 ++ c1: 5d pop %rbp ++ c2: c3 retq ++#pass +diff -rupN binutils-2.32/gas/testsuite/gas/i386/x86-64-align-branch-1f.d binutils.new/gas/testsuite/gas/i386/x86-64-align-branch-1f.d +--- binutils-2.32/gas/testsuite/gas/i386/x86-64-align-branch-1f.d 1970-01-01 01:00:00.000000000 +0100 ++++ binutils.new/gas/testsuite/gas/i386/x86-64-align-branch-1f.d 2019-11-25 14:01:00.680325567 +0000 +@@ -0,0 +1,75 @@ ++#source: x86-64-align-branch-1.s ++#as: -malign-branch-boundary=32 -malign-branch=jcc+jmp ++#objdump: -dw ++ ++.*: +file format .* ++ ++Disassembly of section .text: ++ ++0+ : ++ 0: 64 89 04 25 01 00 00 00 mov %eax,%fs:0x1 ++ 8: 55 push %rbp ++ 9: 55 push %rbp ++ a: 55 push %rbp ++ b: 48 89 e5 mov %rsp,%rbp ++ e: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 11: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 14: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 17: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 1a: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 1d: 48 39 c5 cmp %rax,%rbp ++ 20: 74 5d je 7f ++ 22: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 25: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 28: 89 7d f8 mov %edi,-0x8\(%rbp\) ++ 2b: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 2e: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 31: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 34: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 37: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 3a: 5d pop %rbp ++ 3b: 5d pop %rbp ++ 3c: 74 41 je 7f ++ 3e: 2e 5d cs pop %rbp ++ 40: 74 3d je 7f ++ 42: 89 45 fc mov %eax,-0x4\(%rbp\) ++ 45: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 48: 89 7d f8 mov %edi,-0x8\(%rbp\) ++ 4b: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 4e: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 51: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 54: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 57: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 5a: 5d pop %rbp ++ 5b: 5d pop %rbp ++ 5c: eb 27 jmp 85 ++ 5e: 66 90 xchg %ax,%ax ++ 60: eb 23 jmp 85 ++ 62: eb 21 jmp 85 ++ 64: 89 45 fc mov %eax,-0x4\(%rbp\) ++ 67: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 6a: 89 7d f8 mov %edi,-0x8\(%rbp\) ++ 6d: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 70: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 73: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 76: 5d pop %rbp ++ 77: 5d pop %rbp ++ 78: 48 39 c5 cmp %rax,%rbp ++ 7b: 74 02 je 7f ++ 7d: eb 06 jmp 85 ++ 7f: 8b 45 f4 mov -0xc\(%rbp\),%eax ++ 82: 89 45 fc mov %eax,-0x4\(%rbp\) ++ 85: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ 8b: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ 91: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ 97: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ 9d: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ a3: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ a9: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ af: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ b5: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ bb: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ c1: eb c2 jmp 85 ++ c3: 5d pop %rbp ++ c4: c3 retq ++#pass +diff -rupN binutils-2.32/gas/testsuite/gas/i386/x86-64-align-branch-1g.d binutils.new/gas/testsuite/gas/i386/x86-64-align-branch-1g.d +--- binutils-2.32/gas/testsuite/gas/i386/x86-64-align-branch-1g.d 1970-01-01 01:00:00.000000000 +0100 ++++ binutils.new/gas/testsuite/gas/i386/x86-64-align-branch-1g.d 2019-11-25 14:01:00.680325567 +0000 +@@ -0,0 +1,75 @@ ++#source: x86-64-align-branch-1.s ++#as: -mbranches-within-32B-boundaries ++#objdump: -dw ++ ++.*: +file format .* ++ ++Disassembly of section .text: ++ ++0+ : ++ 0: 64 64 64 64 89 04 25 01 00 00 00 fs fs fs mov %eax,%fs:0x1 ++ b: 55 push %rbp ++ c: 55 push %rbp ++ d: 55 push %rbp ++ e: 48 89 e5 mov %rsp,%rbp ++ 11: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 14: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 17: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 1a: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 1d: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 20: 48 39 c5 cmp %rax,%rbp ++ 23: 74 5d je 82 ++ 25: 2e 89 75 f4 mov %esi,%cs:-0xc\(%rbp\) ++ 29: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 2c: 89 7d f8 mov %edi,-0x8\(%rbp\) ++ 2f: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 32: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 35: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 38: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 3b: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 3e: 5d pop %rbp ++ 3f: 5d pop %rbp ++ 40: 74 40 je 82 ++ 42: 5d pop %rbp ++ 43: 74 3d je 82 ++ 45: 2e 89 45 fc mov %eax,%cs:-0x4\(%rbp\) ++ 49: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 4c: 89 7d f8 mov %edi,-0x8\(%rbp\) ++ 4f: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 52: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 55: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 58: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 5b: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 5e: 5d pop %rbp ++ 5f: 5d pop %rbp ++ 60: eb 26 jmp 88 ++ 62: eb 24 jmp 88 ++ 64: eb 22 jmp 88 ++ 66: 89 45 fc mov %eax,-0x4\(%rbp\) ++ 69: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 6c: 89 7d f8 mov %edi,-0x8\(%rbp\) ++ 6f: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 72: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 75: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 78: 5d pop %rbp ++ 79: 5d pop %rbp ++ 7a: 48 39 c5 cmp %rax,%rbp ++ 7d: 74 03 je 82 ++ 7f: 90 nop ++ 80: eb 06 jmp 88 ++ 82: 8b 45 f4 mov -0xc\(%rbp\),%eax ++ 85: 89 45 fc mov %eax,-0x4\(%rbp\) ++ 88: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ 8e: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ 94: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ 9a: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ a0: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ a6: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ ac: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ b2: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ b8: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ be: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ c4: eb c2 jmp 88 ++ c6: 5d pop %rbp ++ c7: c3 retq ++#pass +diff -rupN binutils-2.32/gas/testsuite/gas/i386/x86-64-align-branch-1h.d binutils.new/gas/testsuite/gas/i386/x86-64-align-branch-1h.d +--- binutils-2.32/gas/testsuite/gas/i386/x86-64-align-branch-1h.d 1970-01-01 01:00:00.000000000 +0100 ++++ binutils.new/gas/testsuite/gas/i386/x86-64-align-branch-1h.d 2019-11-25 14:01:00.680325567 +0000 +@@ -0,0 +1,74 @@ ++#source: x86-64-align-branch-1.s ++#as: -mbranches-within-32B-boundaries -malign-branch-boundary=0 ++#objdump: -dw ++ ++.*: +file format .* ++ ++Disassembly of section .text: ++ ++0+ : ++ 0: 64 89 04 25 01 00 00 00 mov %eax,%fs:0x1 ++ 8: 55 push %rbp ++ 9: 55 push %rbp ++ a: 55 push %rbp ++ b: 48 89 e5 mov %rsp,%rbp ++ e: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 11: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 14: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 17: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 1a: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 1d: 48 39 c5 cmp %rax,%rbp ++ 20: 74 5a je 7c ++ 22: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 25: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 28: 89 7d f8 mov %edi,-0x8\(%rbp\) ++ 2b: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 2e: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 31: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 34: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 37: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 3a: 5d pop %rbp ++ 3b: 5d pop %rbp ++ 3c: 74 3e je 7c ++ 3e: 5d pop %rbp ++ 3f: 74 3b je 7c ++ 41: 89 45 fc mov %eax,-0x4\(%rbp\) ++ 44: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 47: 89 7d f8 mov %edi,-0x8\(%rbp\) ++ 4a: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 4d: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 50: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 53: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 56: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 59: 5d pop %rbp ++ 5a: 5d pop %rbp ++ 5b: eb 25 jmp 82 ++ 5d: eb 23 jmp 82 ++ 5f: eb 21 jmp 82 ++ 61: 89 45 fc mov %eax,-0x4\(%rbp\) ++ 64: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 67: 89 7d f8 mov %edi,-0x8\(%rbp\) ++ 6a: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 6d: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 70: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 73: 5d pop %rbp ++ 74: 5d pop %rbp ++ 75: 48 39 c5 cmp %rax,%rbp ++ 78: 74 02 je 7c ++ 7a: eb 06 jmp 82 ++ 7c: 8b 45 f4 mov -0xc\(%rbp\),%eax ++ 7f: 89 45 fc mov %eax,-0x4\(%rbp\) ++ 82: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ 88: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ 8e: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ 94: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ 9a: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ a0: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ a6: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ ac: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ b2: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ b8: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%rbp\) ++ be: eb c2 jmp 82 ++ c0: 5d pop %rbp ++ c1: c3 retq ++#pass +diff -rupN binutils-2.32/gas/testsuite/gas/i386/x86-64-align-branch-1.s binutils.new/gas/testsuite/gas/i386/x86-64-align-branch-1.s +--- binutils-2.32/gas/testsuite/gas/i386/x86-64-align-branch-1.s 1970-01-01 01:00:00.000000000 +0100 ++++ binutils.new/gas/testsuite/gas/i386/x86-64-align-branch-1.s 2019-11-25 14:01:00.680325567 +0000 +@@ -0,0 +1,70 @@ ++ .text ++ .globl foo ++ .p2align 4 ++foo: ++ movl %eax, %fs:0x1 ++ pushq %rbp ++ pushq %rbp ++ pushq %rbp ++ movq %rsp, %rbp ++ movl %esi, -12(%rbp) ++ movl %esi, -12(%rbp) ++ movl %esi, -12(%rbp) ++ movl %esi, -12(%rbp) ++ movl %esi, -12(%rbp) ++ cmp %rax, %rbp ++ je .L_2 ++ movl %esi, -12(%rbp) ++ movl %esi, -12(%rbp) ++ movl %edi, -8(%rbp) ++ movl %esi, -12(%rbp) ++ movl %esi, -12(%rbp) ++ movl %esi, -12(%rbp) ++ movl %esi, -12(%rbp) ++ movl %esi, -12(%rbp) ++ popq %rbp ++ popq %rbp ++ je .L_2 ++ popq %rbp ++ je .L_2 ++ movl %eax, -4(%rbp) ++ movl %esi, -12(%rbp) ++ movl %edi, -8(%rbp) ++ movl %esi, -12(%rbp) ++ movl %esi, -12(%rbp) ++ movl %esi, -12(%rbp) ++ movl %esi, -12(%rbp) ++ movl %esi, -12(%rbp) ++ popq %rbp ++ popq %rbp ++ jmp .L_3 ++ jmp .L_3 ++ jmp .L_3 ++ movl %eax, -4(%rbp) ++ movl %esi, -12(%rbp) ++ movl %edi, -8(%rbp) ++ movl %esi, -12(%rbp) ++ movl %esi, -12(%rbp) ++ movl %esi, -12(%rbp) ++ popq %rbp ++ popq %rbp ++ cmp %rax, %rbp ++ je .L_2 ++ jmp .L_3 ++.L_2: ++ movl -12(%rbp), %eax ++ movl %eax, -4(%rbp) ++.L_3: ++ movl %esi, -1200(%rbp) ++ movl %esi, -1200(%rbp) ++ movl %esi, -1200(%rbp) ++ movl %esi, -1200(%rbp) ++ movl %esi, -1200(%rbp) ++ movl %esi, -1200(%rbp) ++ movl %esi, -1200(%rbp) ++ movl %esi, -1200(%rbp) ++ movl %esi, -1200(%rbp) ++ movl %esi, -1200(%rbp) ++ jmp .L_3 ++ popq %rbp ++ retq +diff -rupN binutils-2.32/gas/testsuite/gas/i386/x86-64-align-branch-2a.d binutils.new/gas/testsuite/gas/i386/x86-64-align-branch-2a.d +--- binutils-2.32/gas/testsuite/gas/i386/x86-64-align-branch-2a.d 1970-01-01 01:00:00.000000000 +0100 ++++ binutils.new/gas/testsuite/gas/i386/x86-64-align-branch-2a.d 2019-11-25 14:01:00.680325567 +0000 +@@ -0,0 +1,50 @@ ++#source: x86-64-align-branch-2.s ++#as: -malign-branch-boundary=32 -malign-branch=fused+jcc+jmp ++#objdump: -dw ++ ++.*: +file format .* ++ ++Disassembly of section .text: ++ ++0+ : ++ 0: 64 89 04 25 01 00 00 00 mov %eax,%fs:0x1 ++ 8: 55 push %rbp ++ 9: 55 push %rbp ++ a: 55 push %rbp ++ b: 55 push %rbp ++ c: 48 89 e5 mov %rsp,%rbp ++ f: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 12: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 15: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 18: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 1b: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 1e: ff e0 jmpq \*%rax ++ 20: 55 push %rbp ++ 21: 55 push %rbp ++ 22: 64 89 04 25 01 00 00 00 mov %eax,%fs:0x1 ++ 2a: 48 89 e5 mov %rsp,%rbp ++ 2d: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 30: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 33: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 36: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 39: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 3c: ff d0 callq \*%rax ++ 3e: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 41: 55 push %rbp ++ 42: 55 push %rbp ++ 43: 64 89 04 25 01 00 00 00 mov %eax,%fs:0x1 ++ 4b: 48 89 e5 mov %rsp,%rbp ++ 4e: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 51: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 54: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 57: e8 [0-9a-f ]+ callq .* ++ 5c: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 5f: 55 push %rbp ++ 60: 55 push %rbp ++ 61: 55 push %rbp ++ 62: 64 89 04 25 01 00 00 00 mov %eax,%fs:0x1 ++ 6a: 48 89 e5 mov %rsp,%rbp ++ 6d: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 70: ff 14 25 00 00 00 00 callq \*0x0 ++ 77: 55 push %rbp ++#pass +diff -rupN binutils-2.32/gas/testsuite/gas/i386/x86-64-align-branch-2b.d binutils.new/gas/testsuite/gas/i386/x86-64-align-branch-2b.d +--- binutils-2.32/gas/testsuite/gas/i386/x86-64-align-branch-2b.d 1970-01-01 01:00:00.000000000 +0100 ++++ binutils.new/gas/testsuite/gas/i386/x86-64-align-branch-2b.d 2019-11-25 14:01:00.680325567 +0000 +@@ -0,0 +1,50 @@ ++#source: x86-64-align-branch-2.s ++#as: -malign-branch-boundary=32 -malign-branch=indirect ++#objdump: -dw ++ ++.*: +file format .* ++ ++Disassembly of section .text: ++ ++0+ : ++ 0: 64 64 64 89 04 25 01 00 00 00 fs fs mov %eax,%fs:0x1 ++ a: 55 push %rbp ++ b: 55 push %rbp ++ c: 55 push %rbp ++ d: 55 push %rbp ++ e: 48 89 e5 mov %rsp,%rbp ++ 11: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 14: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 17: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 1a: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 1d: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 20: ff e0 jmpq \*%rax ++ 22: 2e 2e 55 cs cs push %rbp ++ 25: 55 push %rbp ++ 26: 64 89 04 25 01 00 00 00 mov %eax,%fs:0x1 ++ 2e: 48 89 e5 mov %rsp,%rbp ++ 31: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 34: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 37: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 3a: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 3d: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 40: ff d0 callq \*%rax ++ 42: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 45: 55 push %rbp ++ 46: 55 push %rbp ++ 47: 64 89 04 25 01 00 00 00 mov %eax,%fs:0x1 ++ 4f: 48 89 e5 mov %rsp,%rbp ++ 52: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 55: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 58: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 5b: e8 [0-9a-f ]+ callq .* ++ 60: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 63: 55 push %rbp ++ 64: 55 push %rbp ++ 65: 55 push %rbp ++ 66: 64 89 04 25 01 00 00 00 mov %eax,%fs:0x1 ++ 6e: 48 89 e5 mov %rsp,%rbp ++ 71: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 74: ff 14 25 00 00 00 00 callq \*0x0 ++ 7b: 55 push %rbp ++#pass +diff -rupN binutils-2.32/gas/testsuite/gas/i386/x86-64-align-branch-2c.d binutils.new/gas/testsuite/gas/i386/x86-64-align-branch-2c.d +--- binutils-2.32/gas/testsuite/gas/i386/x86-64-align-branch-2c.d 1970-01-01 01:00:00.000000000 +0100 ++++ binutils.new/gas/testsuite/gas/i386/x86-64-align-branch-2c.d 2019-11-25 14:01:00.680325567 +0000 +@@ -0,0 +1,50 @@ ++#source: x86-64-align-branch-2.s ++#as: -malign-branch-boundary=32 -malign-branch=indirect+call ++#objdump: -dw ++ ++.*: +file format .* ++ ++Disassembly of section .text: ++ ++0+ : ++ 0: 64 64 64 89 04 25 01 00 00 00 fs fs mov %eax,%fs:0x1 ++ a: 55 push %rbp ++ b: 55 push %rbp ++ c: 55 push %rbp ++ d: 55 push %rbp ++ e: 48 89 e5 mov %rsp,%rbp ++ 11: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 14: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 17: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 1a: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 1d: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 20: ff e0 jmpq \*%rax ++ 22: 2e 2e 55 cs cs push %rbp ++ 25: 55 push %rbp ++ 26: 64 89 04 25 01 00 00 00 mov %eax,%fs:0x1 ++ 2e: 48 89 e5 mov %rsp,%rbp ++ 31: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 34: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 37: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 3a: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 3d: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 40: ff d0 callq \*%rax ++ 42: 2e 2e 2e 2e 2e 89 75 f4 cs cs cs cs mov %esi,%cs:-0xc\(%rbp\) ++ 4a: 55 push %rbp ++ 4b: 55 push %rbp ++ 4c: 64 89 04 25 01 00 00 00 mov %eax,%fs:0x1 ++ 54: 48 89 e5 mov %rsp,%rbp ++ 57: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 5a: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 5d: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 60: e8 [0-9a-f ]+ callq .* ++ 65: 2e 2e 2e 2e 2e 89 75 f4 cs cs cs cs mov %esi,%cs:-0xc\(%rbp\) ++ 6d: 2e 2e 55 cs cs push %rbp ++ 70: 55 push %rbp ++ 71: 55 push %rbp ++ 72: 64 89 04 25 01 00 00 00 mov %eax,%fs:0x1 ++ 7a: 48 89 e5 mov %rsp,%rbp ++ 7d: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 80: ff 14 25 00 00 00 00 callq \*0x0 ++ 87: 55 push %rbp ++#pass +diff -rupN binutils-2.32/gas/testsuite/gas/i386/x86-64-align-branch-2.s binutils.new/gas/testsuite/gas/i386/x86-64-align-branch-2.s +--- binutils-2.32/gas/testsuite/gas/i386/x86-64-align-branch-2.s 1970-01-01 01:00:00.000000000 +0100 ++++ binutils.new/gas/testsuite/gas/i386/x86-64-align-branch-2.s 2019-11-25 14:01:00.680325567 +0000 +@@ -0,0 +1,44 @@ ++ .text ++ .globl foo ++ .p2align 4 ++foo: ++ movl %eax, %fs:0x1 ++ pushq %rbp ++ pushq %rbp ++ pushq %rbp ++ pushq %rbp ++ movq %rsp, %rbp ++ movl %esi, -12(%rbp) ++ movl %esi, -12(%rbp) ++ movl %esi, -12(%rbp) ++ movl %esi, -12(%rbp) ++ movl %esi, -12(%rbp) ++ jmp *%rax ++ pushq %rbp ++ pushq %rbp ++ movl %eax, %fs:0x1 ++ movq %rsp, %rbp ++ movl %esi, -12(%rbp) ++ movl %esi, -12(%rbp) ++ movl %esi, -12(%rbp) ++ movl %esi, -12(%rbp) ++ movl %esi, -12(%rbp) ++ call *%rax ++ movl %esi, -12(%rbp) ++ pushq %rbp ++ pushq %rbp ++ movl %eax, %fs:0x1 ++ movq %rsp, %rbp ++ movl %esi, -12(%rbp) ++ movl %esi, -12(%rbp) ++ movl %esi, -12(%rbp) ++ call foo ++ movl %esi, -12(%rbp) ++ pushq %rbp ++ pushq %rbp ++ pushq %rbp ++ movl %eax, %fs:0x1 ++ movq %rsp, %rbp ++ movl %esi, -12(%rbp) ++ call *foo ++ pushq %rbp +diff -rupN binutils-2.32/gas/testsuite/gas/i386/x86-64-align-branch-3.d binutils.new/gas/testsuite/gas/i386/x86-64-align-branch-3.d +--- binutils-2.32/gas/testsuite/gas/i386/x86-64-align-branch-3.d 1970-01-01 01:00:00.000000000 +0100 ++++ binutils.new/gas/testsuite/gas/i386/x86-64-align-branch-3.d 2019-11-25 14:01:00.680325567 +0000 +@@ -0,0 +1,32 @@ ++#as: -malign-branch-boundary=32 -malign-branch=indirect+call ++#objdump: -dw ++ ++.*: +file format .* ++ ++Disassembly of section .text: ++ ++0+ : ++ 0: 64 89 04 25 01 00 00 00 mov %eax,%fs:0x1 ++ 8: 55 push %rbp ++ 9: 55 push %rbp ++ a: 55 push %rbp ++ b: 55 push %rbp ++ c: 48 89 e5 mov %rsp,%rbp ++ f: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 12: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 15: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 18: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 1b: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 1e: e8 00 00 00 00 callq 23 ++ 23: 55 push %rbp ++ 24: 55 push %rbp ++ 25: 64 89 04 25 01 00 00 00 mov %eax,%fs:0x1 ++ 2d: 48 89 e5 mov %rsp,%rbp ++ 30: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 33: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 36: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 39: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 3c: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 3f: ff 15 00 00 00 00 callq \*0x0\(%rip\) # 45 ++ 45: 89 75 f4 mov %esi,-0xc\(%rbp\) ++#pass +diff -rupN binutils-2.32/gas/testsuite/gas/i386/x86-64-align-branch-3.s binutils.new/gas/testsuite/gas/i386/x86-64-align-branch-3.s +--- binutils-2.32/gas/testsuite/gas/i386/x86-64-align-branch-3.s 1970-01-01 01:00:00.000000000 +0100 ++++ binutils.new/gas/testsuite/gas/i386/x86-64-align-branch-3.s 2019-11-25 14:01:00.680325567 +0000 +@@ -0,0 +1,27 @@ ++ .text ++ .globl foo ++ .p2align 4 ++foo: ++ movl %eax, %fs:0x1 ++ pushq %rbp ++ pushq %rbp ++ pushq %rbp ++ pushq %rbp ++ movq %rsp, %rbp ++ movl %esi, -12(%rbp) ++ movl %esi, -12(%rbp) ++ movl %esi, -12(%rbp) ++ movl %esi, -12(%rbp) ++ movl %esi, -12(%rbp) ++ call __tls_get_addr ++ pushq %rbp ++ pushq %rbp ++ movl %eax, %fs:0x1 ++ movq %rsp, %rbp ++ movl %esi, -12(%rbp) ++ movl %esi, -12(%rbp) ++ movl %esi, -12(%rbp) ++ movl %esi, -12(%rbp) ++ movl %esi, -12(%rbp) ++ call *__tls_get_addr@GOTPCREL(%rip) ++ movl %esi, -12(%rbp) +diff -rupN binutils-2.32/gas/testsuite/gas/i386/x86-64-align-branch-4a.d binutils.new/gas/testsuite/gas/i386/x86-64-align-branch-4a.d +--- binutils-2.32/gas/testsuite/gas/i386/x86-64-align-branch-4a.d 1970-01-01 01:00:00.000000000 +0100 ++++ binutils.new/gas/testsuite/gas/i386/x86-64-align-branch-4a.d 2019-11-25 14:01:00.680325567 +0000 +@@ -0,0 +1,33 @@ ++#source: x86-64-align-branch-4.s ++#as: -malign-branch-boundary=32 -malign-branch=fused+jcc+jmp ++#objdump: -dw ++ ++.*: +file format .* ++ ++Disassembly of section .text: ++ ++0+ : ++ 0: 64 89 04 25 01 00 00 00 mov %eax,%fs:0x1 ++ 8: 55 push %rbp ++ 9: 55 push %rbp ++ a: 48 89 e5 mov %rsp,%rbp ++ d: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 10: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 13: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 16: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 19: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 1c: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 1f: c3 retq ++ 20: 55 push %rbp ++ 21: 64 89 04 25 01 00 00 00 mov %eax,%fs:0x1 ++ 29: 55 push %rbp ++ 2a: 55 push %rbp ++ 2b: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 2e: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 31: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 34: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 37: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 3a: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 3d: c2 1e 00 retq \$0x1e ++ 40: 55 push %rbp ++#pass +diff -rupN binutils-2.32/gas/testsuite/gas/i386/x86-64-align-branch-4b.d binutils.new/gas/testsuite/gas/i386/x86-64-align-branch-4b.d +--- binutils-2.32/gas/testsuite/gas/i386/x86-64-align-branch-4b.d 1970-01-01 01:00:00.000000000 +0100 ++++ binutils.new/gas/testsuite/gas/i386/x86-64-align-branch-4b.d 2019-11-25 14:01:00.680325567 +0000 +@@ -0,0 +1,33 @@ ++#source: x86-64-align-branch-4.s ++#as: -malign-branch-boundary=32 -malign-branch=ret ++#objdump: -dw ++ ++.*: +file format .* ++ ++Disassembly of section .text: ++ ++0+ : ++ 0: 64 64 89 04 25 01 00 00 00 fs mov %eax,%fs:0x1 ++ 9: 55 push %rbp ++ a: 55 push %rbp ++ b: 48 89 e5 mov %rsp,%rbp ++ e: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 11: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 14: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 17: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 1a: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 1d: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 20: c3 retq ++ 21: 2e 2e 55 cs cs push %rbp ++ 24: 64 89 04 25 01 00 00 00 mov %eax,%fs:0x1 ++ 2c: 55 push %rbp ++ 2d: 55 push %rbp ++ 2e: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 31: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 34: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 37: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 3a: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 3d: 89 75 f4 mov %esi,-0xc\(%rbp\) ++ 40: c2 1e 00 retq \$0x1e ++ 43: 55 push %rbp ++#pass +diff -rupN binutils-2.32/gas/testsuite/gas/i386/x86-64-align-branch-4.s binutils.new/gas/testsuite/gas/i386/x86-64-align-branch-4.s +--- binutils-2.32/gas/testsuite/gas/i386/x86-64-align-branch-4.s 1970-01-01 01:00:00.000000000 +0100 ++++ binutils.new/gas/testsuite/gas/i386/x86-64-align-branch-4.s 2019-11-25 14:01:00.680325567 +0000 +@@ -0,0 +1,27 @@ ++ .text ++ .globl foo ++ .p2align 4 ++foo: ++ movl %eax, %fs:0x1 ++ pushq %rbp ++ pushq %rbp ++ movq %rsp, %rbp ++ movl %esi, -12(%rbp) ++ movl %esi, -12(%rbp) ++ movl %esi, -12(%rbp) ++ movl %esi, -12(%rbp) ++ movl %esi, -12(%rbp) ++ movl %esi, -12(%rbp) ++ ret ++ pushq %rbp ++ movl %eax, %fs:0x1 ++ pushq %rbp ++ pushq %rbp ++ movl %esi, -12(%rbp) ++ movl %esi, -12(%rbp) ++ movl %esi, -12(%rbp) ++ movl %esi, -12(%rbp) ++ movl %esi, -12(%rbp) ++ movl %esi, -12(%rbp) ++ ret $30 ++ pushq %rbp +diff -rupN binutils-2.32/gas/testsuite/gas/i386/x86-64-align-branch-5.d binutils.new/gas/testsuite/gas/i386/x86-64-align-branch-5.d +--- binutils-2.32/gas/testsuite/gas/i386/x86-64-align-branch-5.d 1970-01-01 01:00:00.000000000 +0100 ++++ binutils.new/gas/testsuite/gas/i386/x86-64-align-branch-5.d 2019-11-25 14:01:00.680325567 +0000 +@@ -0,0 +1,37 @@ ++#source: align-branch-5.s ++#as: -malign-branch-boundary=32 -malign-branch=jcc+fused+jmp ++#objdump: -dw ++ ++.*: +file format .* ++ ++Disassembly of section .text: ++ ++0+ : ++ 0: c1 e9 02 shr \$0x2,%ecx ++ 3: c1 e9 02 shr \$0x2,%ecx ++ 6: c1 e9 02 shr \$0x2,%ecx ++ 9: 89 d1 mov %edx,%ecx ++ b: 31 c0 xor %eax,%eax ++ d: c1 e9 02 shr \$0x2,%ecx ++ 10: c1 e9 02 shr \$0x2,%ecx ++ 13: c1 e9 02 shr \$0x2,%ecx ++ 16: c1 e9 02 shr \$0x2,%ecx ++ 19: c1 e9 02 shr \$0x2,%ecx ++ 1c: c1 e9 02 shr \$0x2,%ecx ++ 1f: f6 c2 02 test \$0x2,%dl ++ 22: f3 ab rep stos %eax,%es:\(%rdi\) ++ 24: 75 dd jne 3 ++ 26: 31 c0 xor %eax,%eax ++ 28: c1 e9 02 shr \$0x2,%ecx ++ 2b: c1 e9 02 shr \$0x2,%ecx ++ 2e: c1 e9 02 shr \$0x2,%ecx ++ 31: 89 d1 mov %edx,%ecx ++ 33: 31 c0 xor %eax,%eax ++ 35: c1 e9 02 shr \$0x2,%ecx ++ 38: c1 e9 02 shr \$0x2,%ecx ++ 3b: c1 e9 02 shr \$0x2,%ecx ++ 3e: f6 c2 02 test \$0x2,%dl ++ 41: e8 00 00 00 00 callq 46 ++ 46: 75 e3 jne 2b ++ 48: 31 c0 xor %eax,%eax ++#pass +diff -rupN binutils-2.32/gas/write.c binutils.new/gas/write.c +--- binutils-2.32/gas/write.c 2019-11-25 14:01:09.888265017 +0000 ++++ binutils.new/gas/write.c 2019-11-25 14:01:00.901324114 +0000 +@@ -3031,7 +3031,12 @@ relax_segment (struct frag *segment_frag + #ifdef TC_GENERIC_RELAX_TABLE + /* The default way to relax a frag is to look through + TC_GENERIC_RELAX_TABLE. */ ++#ifdef md_generic_table_relax_frag ++ growth = md_generic_table_relax_frag (segment, fragP, ++ stretch); ++#else + growth = relax_frag (segment, fragP, stretch); ++#endif /* md_generic_table_relax_frag */ + #endif /* TC_GENERIC_RELAX_TABLE */ + #endif + break; diff --git a/SPECS/binutils.spec b/SPECS/binutils.spec index ebaf06d..2b50b1d 100644 --- a/SPECS/binutils.spec +++ b/SPECS/binutils.spec @@ -1,3 +1,14 @@ + +%define __python /opt/rh/gcc-toolset-9/root/usr/bin/python3 +%{?scl:%{?scl_package:%scl_package binutils}} + +Summary: A GNU collection of binary utilities +Name: %{?scl_prefix}%{?cross}binutils%{?_with_debug:-debug} +Version: 2.32 +Release: 17%{?dist} +License: GPLv3+ +URL: https://sourceware.org/binutils + # Binutils SPEC file. Can be invoked with the following parameters: # --define "binutils_target arm-linux-gnu" to create arm-linux-gnu-binutils. @@ -36,9 +47,6 @@ #----End of Configure Options------------------------------------------------ -%define __python /opt/rh/gcc-toolset-9/root/usr/bin/python3 -%{?scl:%{?scl_package:%scl_package binutils}} - # Default: Not bootstrapping. %bcond_with bootstrap # Default: Not debug @@ -69,13 +77,6 @@ #---------------------------------------------------------------------------- -Summary: A GNU collection of binary utilities -Name: %{?scl_prefix}%{?cross}binutils%{?_with_debug:-debug} -Version: 2.32 -Release: 5%{?dist} -License: GPLv3+ -URL: https://sourceware.org/binutils - # Note - the Linux Kernel binutils releases are too unstable and contain # too many controversial patches so we stick with the official FSF version # instead. @@ -234,6 +235,71 @@ Patch23: binutils-ld-testsuite-fixes.patch # Lifetime: Maybe fixed in 2.33. Patch24: binutils-gold-8-byte-note-segments.patch +# Purpose: Add descriptions to the new s390x arch13 instructions +# Lifetime: 2.33 +Patch25: binutils-s390x-arch13-descriptions.patch + +# Purpose: Stop gold from aborting when input sections with the same name +# have different flags. +# Lifetime: 2.33 (probably) +Patch26: binutils-gold-mismatched-section-flags.patch + +# Purpose: Remove the builder id comment from bfd-stdint.h. It causes +# conflicts when both the i686 and x86_64 binutils devel rpms +# are installed, as the comments makes the file compare as +# being different. +# Lifetime: Permanent. +Patch27: binutils-no-builder-comment-in-bfd-stdint.patch + +# Purpose: Correct licence strings rejected by PELC review. +# Lifetime: Permanent. +Patch28: binutils-PELC-licence-corrections.patch + +# Purpose: Ignore duplicate FDE entries found in some AArch64 libraries. +# Lifetime: Permanent. +Patch29: binutils-ignore-duplicate-FDE-entries.patch + +# Purpose: Corrcect a memory corruption when generating relocs for build +# notes in the assembler. +# Lifetime: Fixed in 2.33 +Patch30: binutils-gas-build-note-relocs.patch + +# Purpose: Support the generation of variant ABI functions in AArch64 binaries. +# Lifetime: Fixed in 2.33 +Patch31: binutils-aarch64-STO_AARCH64_VARIANT_PCS.patch + +# Purpose: Remove a debugging print statement left in the objcopy code. +# Lifetime: Fixed in 2.33 +Patch32: binutils-remove-DUP-FUNXC-debug-fprintf.patch + +# Purpose: Stop strip from complaining about build notes that do not start +# with a version note. +# Lifetime: Fixed in 2.33 +Patch33: binutils-objcopy-version-note.patch + +# Purpose: Add check to libiberty library in order to prevent an integer overflow in the gold linker. +# Lifetime: Fixed in 2.33 +Patch34: binutils-CVE-2019-14250.patch + +# Purpose: Add check to readelf in order to prevent an integer overflow. +# Lifetime: Fixed in 2.33 +Patch35: binutils-CVE-2019-14444.patch + +# Purpose: Fix a potential seg-fault in the BFD library when parsing +# pathalogical debug_info sections. +# Lifetime: Fixed in 2.34 +Patch36: binutils-CVE-2019-17451.patch + +# Purpose: Fix a memory exhaustion bug in the BFD library when parsing +# corrupt DWARF debug information. +# Lifetime: Fixed in 2.34 +Patch37: binutils-CVE-2019-17450.patch + +# Purpose: Add a feature to the x86/64 assembler to create +# workarounds for the Intel Jcc Erratum. +# Lifetime: Fixed in 2.34 +Patch38: binutils-x86-JCC-Errata.patch + #---------------------------------------------------------------------------- Provides: bundled(libiberty) @@ -290,9 +356,11 @@ BuildRequires: findutils %if %{with testsuite} # relro_test.sh uses dc which is part of the bc rpm, hence its inclusion here. BuildRequires: dejagnu, zlib-static, glibc-static, sharutils, bc +%if "%{build_gold}" == "both" # The GOLD testsuite needs a static libc++ BuildRequires: libstdc++-static %endif +%endif Conflicts: gcc-c++ < 4.0.0 @@ -381,6 +449,20 @@ using libelf instead of BFD. %patch22 -p1 %patch23 -p1 %patch24 -p1 +%patch25 -p1 +%patch26 -p1 +%patch27 -p1 +%patch28 -p1 +%patch29 -p1 +%patch30 -p1 +%patch31 -p1 +%patch32 -p1 +%patch33 -p1 +%patch34 -p1 +%patch35 -p1 +%patch36 -p1 +%patch37 -p1 +%patch38 -p1 # We cannot run autotools as there is an exact requirement of autoconf-2.59. # FIXME - this is no longer true. Maybe try reinstating autotool use ? @@ -721,7 +803,7 @@ fi /sbin/install-info --info-dir=%{_infodir} %{_infodir}/ld.info.gz /sbin/install-info --info-dir=%{_infodir} %{_infodir}/standards.info.gz %endif # with docs -%endif +%endif # isnative exit 0 @@ -763,7 +845,7 @@ exit 0 /sbin/install-info --delete --info-dir=%{_infodir} %{_infodir}/ld.info.gz /sbin/install-info --quiet --delete --info-dir=%{_infodir} %{_infodir}/standards.info.gz fi -%endif +%endif # isnative #---------------------------------------------------------------------------- @@ -787,13 +869,13 @@ exit 0 %{_infodir}/ld.info.* %{_infodir}/bfd.info.* %{_infodir}/standards.info.* -%endif +%endif # with docs %if %{enable_shared} %{_libdir}/lib*.so %exclude %{_libdir}/libbfd.so %exclude %{_libdir}/libopcodes.so -%endif +%endif # enable_shared %if %{isnative} @@ -816,6 +898,43 @@ exit 0 #---------------------------------------------------------------------------- %changelog +* Sun Dec 08 2019 Nick Clifton - 2.32-17 +- Fix a potential seg-fault in the BFD library when parsing pathalogical debug_info sections. (#1779255) +- Fix a potential memory exhaustion in the BFD library when parsing corrupt DWARF debug information. +- Backport H.J.Lu's patch to add a workaround for the JCC Errata to the assembler. (#1779417) +- Fix potential integer overflow in readelf. (#1740470) +- Fix potential integer overflow in GOLD. (#1739491) + +* Tue Aug 06 2019 Nick Clifton - 2.32-15 +- Stop strip from complaining if the first build note is not a version note. (#1736114) + +* Mon Aug 05 2019 Nick Clifton - 2.32-14 +- Remove debugging print statement in objcopy sources. (#1733868) + +* Fri Jul 05 2019 Nick Clifton - 2.32-13 +- Define scl before Name. + +* Tue Jul 02 2019 Nick Clifton - 2.32-12 +- Add support for AArch64 function calls that use a variant PCS. + +* Mon Jul 01 2019 Nick Clifton - 2.32-11 +- Stop gas from triggering a seg-fault when creating relocs for build notes. (PR 24748) + +* Tue Jun 25 2019 Nick Clifton - 2.32-10 +- Ignore duplicate FDE entries in AArch64 libraries. (#1709827) + +* Tue Jun 25 2019 Nick Clifton - 2.32-9 +- Correct licences rejected by PELC review. + +* Mon Jun 24 2019 Nick Clifton - 2.32-8 +- Remove the builder command from bfd-stdint.h. + +* Mon Jun 24 2019 Nick Clifton - 2.32-7 +- Stop gold from aborting when it encounters input sections with the same name and different flags. (#1722715) + +* Tue Jun 18 2019 Nick Clifton - 2.32-6 +- Add descriptions to the new s390x arch13 instructions. (#1690457) + * Wed Jun 12 2019 Nick Clifton - 2.32-5 - Import patch to fix alignment of note segments created by GOLD. (#1614908)