diff --git a/SOURCES/binutils-PPC-dcbt.patch b/SOURCES/binutils-PPC-dcbt.patch new file mode 100644 index 0000000..deef8c5 --- /dev/null +++ b/SOURCES/binutils-PPC-dcbt.patch @@ -0,0 +1,144 @@ +diff -rup binutils.orig/gas/testsuite/gas/ppc/power4_32.d binutils-2.35/gas/testsuite/gas/ppc/power4_32.d +--- binutils.orig/gas/testsuite/gas/ppc/power4_32.d 2022-01-25 13:39:48.063563099 +0000 ++++ binutils-2.35/gas/testsuite/gas/ppc/power4_32.d 2022-01-25 13:48:30.857981751 +0000 +@@ -41,7 +41,7 @@ Disassembly of section \.text: + 7c: (7c 01 17 ec|ec 17 01 7c) dcbz r1,r2 + 80: (7c 23 27 ec|ec 27 23 7c) dcbzl r3,r4 + 84: (7c 05 37 ec|ec 37 05 7c) dcbz r5,r6 +- 88: (7c 05 32 2c|2c 32 05 7c) dcbt r5,r6 +- 8c: (7c 05 32 2c|2c 32 05 7c) dcbt r5,r6 +- 90: (7d 05 32 2c|2c 32 05 7d) dcbt r5,r6,8 ++ 88: (7c 05 32 2c|2c 32 05 7c) dcbtct r5,r6 ++ 8c: (7c 05 32 2c|2c 32 05 7c) dcbtct r5,r6 ++ 90: (7d 05 32 2c|2c 32 05 7d) dcbtds r5,r6 + #pass +diff -rup binutils.orig/opcodes/ppc-opc.c binutils-2.35/opcodes/ppc-opc.c +--- binutils.orig/opcodes/ppc-opc.c 2022-01-25 13:39:47.650565929 +0000 ++++ binutils-2.35/opcodes/ppc-opc.c 2022-01-25 13:47:09.056542122 +0000 +@@ -2205,6 +2205,74 @@ extract_sxl (uint64_t insn, + return 1; + return (insn >> 11) & 0x1; + } ++ ++/* The list of embedded processors that use the embedded operand ordering ++ for the 3 operand dcbt and dcbtst instructions. */ ++#define DCBT_EO (PPC_OPCODE_E500 | PPC_OPCODE_E500MC | PPC_OPCODE_476 \ ++ | PPC_OPCODE_A2) ++ ++/* ISA 2.03 and later specify extended mnemonics dcbtct, dcbtds, and ++ dcbtstct, dcbtstds with a note saying these should be used in new ++ programs rather than the base mnemonics "so that it can be coded ++ with TH as the last operand for all categories". For that reason ++ the extended mnemonics are enabled in the assembler for the ++ embedded processors, but not for the disassembler so as to display ++ the embedded dcbt or dcbtst expected form with TH first for ++ embedded programmers. */ ++ ++static uint64_t ++insert_thct (uint64_t insn, ++ int64_t value, ++ ppc_cpu_t dialect ATTRIBUTE_UNUSED, ++ const char **errmsg) ++{ ++ if ((uint64_t) value > 7) ++ *errmsg = _("invalid TH value"); ++ return insn | ((value & 7) << 21); ++} ++ ++static int64_t ++extract_thct (uint64_t insn, ++ ppc_cpu_t dialect, ++ int *invalid) ++{ ++ /* Missing optional operands have a value of 0. */ ++ if (*invalid < 0) ++ return 0; ++ ++ int64_t value = (insn >> 21) & 0x1f; ++ if (value > 7 || (dialect & DCBT_EO) != 0) ++ *invalid = 1; ++ ++ return value; ++} ++ ++static uint64_t ++insert_thds (uint64_t insn, ++ int64_t value, ++ ppc_cpu_t dialect ATTRIBUTE_UNUSED, ++ const char **errmsg) ++{ ++ if (value < 8 || value > 15) ++ *errmsg = _("invalid TH value"); ++ return insn | ((value & 0x1f) << 21); ++} ++ ++static int64_t ++extract_thds (uint64_t insn, ++ ppc_cpu_t dialect, ++ int *invalid) ++{ ++ /* Missing optional operands have a value of 8. */ ++ if (*invalid < 0) ++ return 8; ++ ++ int64_t value = (insn >> 21) & 0x1f; ++ if (value < 8 || value > 15 || (dialect & DCBT_EO) != 0) ++ *invalid = 1; ++ ++ return value; ++} + + /* The operands table. + +@@ -2402,10 +2470,18 @@ const struct powerpc_operand powerpc_ope + #define MO CT + { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, + ++ /* The TH field in dcbtct. */ ++#define THCT CT + 1 ++ { 0x1f, 21, insert_thct, extract_thct, PPC_OPERAND_OPTIONAL }, ++ ++ /* The TH field in dcbtds. */ ++#define THDS THCT + 1 ++ { 0x1f, 21, insert_thds, extract_thds, PPC_OPERAND_OPTIONAL }, ++ + /* The D field in a D form instruction. This is a displacement off + a register, and implies that the next operand is a register in + parentheses. */ +-#define D CT + 1 ++#define D THDS + 1 + { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, + + /* The D8 field in a D form instruction. This is a displacement off +@@ -4211,12 +4287,6 @@ const unsigned int num_powerpc_operands + #define PPCHTM PPC_OPCODE_POWER8 + #define E200Z4 PPC_OPCODE_E200Z4 + #define PPCLSP PPC_OPCODE_LSP +-/* The list of embedded processors that use the embedded operand ordering +- for the 3 operand dcbt and dcbtst instructions. */ +-#define DCBT_EO (PPC_OPCODE_E500 | PPC_OPCODE_E500MC | PPC_OPCODE_476 \ +- | PPC_OPCODE_A2) +- +- + + /* The opcode table. + +@@ -6592,6 +6662,8 @@ const struct powerpc_opcode powerpc_opco + {"mtvsrwz", X(31,243), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}}, + + {"dcbtstt", XRT(31,246,0x10), XRT_MASK, POWER7, 0, {RA0, RB}}, ++{"dcbtstct", X(31,246), X_MASK, POWER4, 0, {RA0, RB, THCT}}, ++{"dcbtstds", X(31,246), X_MASK, POWER4, 0, {RA0, RB, THDS}}, + {"dcbtst", X(31,246), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}}, + {"dcbtst", X(31,246), X_MASK, DCBT_EO, 0, {CT, RA0, RB}}, + {"dcbtst", X(31,246), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}}, +@@ -6643,6 +6715,9 @@ const struct powerpc_opcode powerpc_opco + {"lscbx.", XRC(31,277,1), X_MASK, M601, 0, {RT, RA, RB}}, + + {"dcbtt", XRT(31,278,0x10), XRT_MASK, POWER7, 0, {RA0, RB}}, ++{"dcbna", XRT(31,278,0x11), XRT_MASK, POWER10, 0, {RA0, RB}}, ++{"dcbtct", X(31,278), X_MASK, POWER4, 0, {RA0, RB, THCT}}, ++{"dcbtds", X(31,278), X_MASK, POWER4, 0, {RA0, RB, THDS}}, + {"dcbt", X(31,278), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}}, + {"dcbt", X(31,278), X_MASK, DCBT_EO, 0, {CT, RA0, RB}}, + {"dcbt", X(31,278), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}}, diff --git a/SOURCES/binutils-ppc-hash-insert.patch b/SOURCES/binutils-ppc-hash-insert.patch new file mode 100644 index 0000000..3879954 --- /dev/null +++ b/SOURCES/binutils-ppc-hash-insert.patch @@ -0,0 +1,107 @@ +diff -rup binutils.orig/gas/config/tc-ppc.c binutils-2.35/gas/config/tc-ppc.c +--- binutils.orig/gas/config/tc-ppc.c 2022-02-03 11:10:42.835719394 +0000 ++++ binutils-2.35/gas/config/tc-ppc.c 2022-02-03 11:13:04.298724661 +0000 +@@ -1738,12 +1738,12 @@ ppc_setup_opcodes (void) + + if ((ppc_cpu & op->flags) != 0 + && !(ppc_cpu & op->deprecated)) +- str_hash_insert (ppc_hash, op->name, (void *) op); ++ str_hash_insert_or_replace (ppc_hash, op->name, (void *) op, 0); + } + + if ((ppc_cpu & PPC_OPCODE_ANY) != 0) + for (op = powerpc_opcodes; op < op_end; op++) +- str_hash_insert (ppc_hash, op->name, (void *) op); ++ str_hash_insert_or_replace (ppc_hash, op->name, (void *) op, 0); + + op_end = prefix_opcodes + prefix_num_opcodes; + for (op = prefix_opcodes; op < op_end; op++) +@@ -1772,12 +1772,12 @@ ppc_setup_opcodes (void) + + if ((ppc_cpu & op->flags) != 0 + && !(ppc_cpu & op->deprecated)) +- str_hash_insert (ppc_hash, op->name, (void *) op); ++ str_hash_insert_or_replace (ppc_hash, op->name, (void *) op, 0); + } + + if ((ppc_cpu & PPC_OPCODE_ANY) != 0) + for (op = prefix_opcodes; op < op_end; op++) +- str_hash_insert (ppc_hash, op->name, (void *) op); ++ str_hash_insert_or_replace (ppc_hash, op->name, (void *) op, 0); + + op_end = vle_opcodes + vle_num_opcodes; + for (op = vle_opcodes; op < op_end; op++) +@@ -1807,7 +1807,7 @@ ppc_setup_opcodes (void) + + if ((ppc_cpu & op->flags) != 0 + && !(ppc_cpu & op->deprecated)) +- str_hash_insert (ppc_hash, op->name, (void *) op); ++ str_hash_insert_or_replace (ppc_hash, op->name, (void *) op, 0); + } + + /* SPE2 instructions */ +@@ -1841,11 +1841,11 @@ ppc_setup_opcodes (void) + } + + if ((ppc_cpu & op->flags) != 0 && !(ppc_cpu & op->deprecated)) +- str_hash_insert (ppc_hash, op->name, (void *) op); ++ str_hash_insert_or_replace (ppc_hash, op->name, (void *) op, 0); + } + + for (op = spe2_opcodes; op < op_end; op++) +- str_hash_insert (ppc_hash, op->name, (void *) op); ++ str_hash_insert_or_replace (ppc_hash, op->name, (void *) op, 0); + } + + /* Insert the macros into a hash table. */ +diff -rup binutils.orig/gas/hash.c binutils-2.35/gas/hash.c +--- binutils.orig/gas/hash.c 2022-02-03 11:10:42.827719448 +0000 ++++ binutils-2.35/gas/hash.c 2022-02-03 11:12:00.506175797 +0000 +@@ -32,6 +32,24 @@ htab_insert (htab_t htab, PTR element) + *slot = element; + } + ++void ** ++htab_insert_or_replace (htab_t htab, void *element, int replace) ++{ ++ void **slot = htab_find_slot (htab, element, INSERT); ++ if (*slot != NULL) ++ { ++ if (replace) ++ { ++ if (htab->del_f) ++ (*htab->del_f) (*slot); ++ *slot = element; ++ } ++ return slot; ++ } ++ *slot = element; ++ return NULL; ++} ++ + /* Print statistics about a hash table. */ + + void +diff -rup binutils.orig/gas/hash.h binutils-2.35/gas/hash.h +--- binutils.orig/gas/hash.h 2022-02-03 11:10:42.830719428 +0000 ++++ binutils-2.35/gas/hash.h 2022-02-03 11:12:25.002002561 +0000 +@@ -103,6 +103,19 @@ str_hash_insert (htab_t table, const cha + htab_insert (table, string_tuple_alloc (key, value)); + } + ++extern void ** htab_insert_or_replace (htab_t, void *, int); ++ ++static inline void ** ++str_hash_insert_or_replace (htab_t table, const char *key, void *value, int replace) ++{ ++ string_tuple_t *elt = string_tuple_alloc (key, value); ++ void **slot = htab_insert_or_replace (table, elt, replace); ++ if (slot && !replace) ++ free (elt); ++ return slot; ++} ++ ++ + static inline htab_t + str_htab_create (void) + { diff --git a/SPECS/binutils.spec b/SPECS/binutils.spec index 3273944..977cd62 100644 --- a/SPECS/binutils.spec +++ b/SPECS/binutils.spec @@ -5,7 +5,7 @@ Summary: A GNU collection of binary utilities Name: %{?scl_prefix}%{?cross}binutils%{?_with_debug:-debug} Version: 2.35 -Release: 8%{?dist}.6 +Release: 11%{?dist} License: GPLv3+ URL: https://sourceware.org/binutils @@ -283,6 +283,14 @@ Patch36: binutils-gas-speedups.patch # Lifetime: Fixed in 2.38 (maybe) Patch37: binutils.unicode.patch +# Purpose: Fix the assembly of the three-operand variant of the DCBT insn. +# Lifetime: Fixed in 2.36.1 +Patch38: binutils-PPC-dcbt.patch + +# Purpose: Fix the assembly of the three-operand variant of the DCBT insn (again). +# Lifetime: Fixed in 2.36.1 +Patch39: binutils-ppc-hash-insert.patch + #---------------------------------------------------------------------------- Provides: bundled(libiberty) @@ -919,17 +927,17 @@ exit 0 #---------------------------------------------------------------------------- %changelog -* Thu Oct 21 2021 Nick Clifton - 2.35-8.6 -- Add ability to control the display of unicode characters. (#2009176) - -* Wed Aug 11 2021 Nick Clifton - 2.35-8.4 -- Backport some more speed up patches. (#1978174) +* Thu Feb 03 2022 Nick Clifton - 2.35-11 +- Fix the assembly of the three-operand variant of the DCBT insn. (#2044523) -* Mon Jul 05 2021 Nick Clifton - 2.35-8.2 -- NVR bump to enable rebuild with correct tag. +* Tue Jan 25 2022 Nick Clifton - 2.35-10 +- Fix the assembly of the three-operand variant of the DCBT insn. (#2044523) -* Mon Jun 28 2021 Nick Clifton - 2.35-8.1 +* Mon Nov 29 2021 Nick Clifton - 2.35-9 +- Add ability to control the display of unicode characters. (#2009178) +- Backport some more speed up patches. (#1978174) - Remove a quadratic performance penalty processing files. (#1978174) +- Extend vulnerability fix again. (#1925779) * Mon Feb 08 2021 Nick Clifton - 2.35-8 - Extend vulnerability fix again. (#1925779)